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dfad12b5 | 1 | /* Subroutines used for MIPS code generation. |
214be03f | 2 | Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, |
67e67979 | 3 | 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 |
6fb5fa3c | 4 | Free Software Foundation, Inc. |
cee98a59 | 5 | Contributed by A. Lichnewsky, lich@inria.inria.fr. |
b2a68403 | 6 | Changes by Michael Meissner, meissner@osf.org. |
85f65093 | 7 | 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and |
147255d8 | 8 | Brendan Eich, brendan@microunity.com. |
cee98a59 | 9 | |
7ec022b2 | 10 | This file is part of GCC. |
cee98a59 | 11 | |
7ec022b2 | 12 | GCC is free software; you can redistribute it and/or modify |
cee98a59 | 13 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 14 | the Free Software Foundation; either version 3, or (at your option) |
cee98a59 MM |
15 | any later version. |
16 | ||
7ec022b2 | 17 | GCC is distributed in the hope that it will be useful, |
cee98a59 MM |
18 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
19 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | GNU General Public License for more details. | |
21 | ||
22 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
23 | along with GCC; see the file COPYING3. If not see |
24 | <http://www.gnu.org/licenses/>. */ | |
cee98a59 MM |
25 | |
26 | #include "config.h" | |
50b2596f | 27 | #include "system.h" |
4977bab6 ZW |
28 | #include "coretypes.h" |
29 | #include "tm.h" | |
50b2596f | 30 | #include <signal.h> |
cee98a59 MM |
31 | #include "rtl.h" |
32 | #include "regs.h" | |
33 | #include "hard-reg-set.h" | |
cee98a59 MM |
34 | #include "insn-config.h" |
35 | #include "conditions.h" | |
cee98a59 | 36 | #include "insn-attr.h" |
cee98a59 | 37 | #include "recog.h" |
50b2596f | 38 | #include "toplev.h" |
c5c76735 | 39 | #include "output.h" |
cee98a59 | 40 | #include "tree.h" |
49ad7cfa | 41 | #include "function.h" |
cee98a59 | 42 | #include "expr.h" |
c15c90bb | 43 | #include "optabs.h" |
e2ff10a9 | 44 | #include "libfuncs.h" |
cee98a59 | 45 | #include "flags.h" |
2bcb2ab3 | 46 | #include "reload.h" |
bd9f1972 | 47 | #include "tm_p.h" |
d07d525a | 48 | #include "ggc.h" |
7719ffbf | 49 | #include "gstab.h" |
920ae24b RH |
50 | #include "hashtab.h" |
51 | #include "debug.h" | |
672a6f42 NB |
52 | #include "target.h" |
53 | #include "target-def.h" | |
cafe096b | 54 | #include "integrate.h" |
2743a50a | 55 | #include "langhooks.h" |
b85aed9e | 56 | #include "cfglayout.h" |
dc884a86 | 57 | #include "sched-int.h" |
726a989a | 58 | #include "gimple.h" |
912f2dac | 59 | #include "bitmap.h" |
566dfd71 | 60 | #include "diagnostic.h" |
cee98a59 | 61 | |
65239d20 | 62 | /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ |
108b61d5 RS |
63 | #define UNSPEC_ADDRESS_P(X) \ |
64 | (GET_CODE (X) == UNSPEC \ | |
65 | && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \ | |
66 | && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES) | |
67 | ||
68 | /* Extract the symbol or label from UNSPEC wrapper X. */ | |
69 | #define UNSPEC_ADDRESS(X) \ | |
70 | XVECEXP (X, 0, 0) | |
71 | ||
72 | /* Extract the symbol type from UNSPEC wrapper X. */ | |
73 | #define UNSPEC_ADDRESS_TYPE(X) \ | |
74 | ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST)) | |
75 | ||
be763023 | 76 | /* The maximum distance between the top of the stack frame and the |
e1260576 RS |
77 | value $sp has when we save and restore registers. |
78 | ||
79 | The value for normal-mode code must be a SMALL_OPERAND and must | |
80 | preserve the maximum stack alignment. We therefore use a value | |
81 | of 0x7ff0 in this case. | |
82 | ||
83 | MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by | |
84 | up to 0x7f8 bytes and can usually save or restore all the registers | |
85 | that we need to save or restore. (Note that we can only use these | |
86 | instructions for o32, for which the stack alignment is 8 bytes.) | |
87 | ||
88 | We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and | |
89 | RESTORE are not available. We can then use unextended instructions | |
90 | to save and restore registers, and to allocate and deallocate the top | |
91 | part of the frame. */ | |
92 | #define MIPS_MAX_FIRST_STACK_STEP \ | |
93 | (!TARGET_MIPS16 ? 0x7ff0 \ | |
94 | : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \ | |
95 | : TARGET_64BIT ? 0x100 : 0x400) | |
be763023 | 96 | |
dc884a86 RS |
97 | /* True if INSN is a mips.md pattern or asm statement. */ |
98 | #define USEFUL_INSN_P(INSN) \ | |
006b29ab | 99 | (NONDEBUG_INSN_P (INSN) \ |
dc884a86 RS |
100 | && GET_CODE (PATTERN (INSN)) != USE \ |
101 | && GET_CODE (PATTERN (INSN)) != CLOBBER \ | |
102 | && GET_CODE (PATTERN (INSN)) != ADDR_VEC \ | |
103 | && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC) | |
104 | ||
105 | /* If INSN is a delayed branch sequence, return the first instruction | |
106 | in the sequence, otherwise return INSN itself. */ | |
107 | #define SEQ_BEGIN(INSN) \ | |
108 | (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ | |
109 | ? XVECEXP (PATTERN (INSN), 0, 0) \ | |
110 | : (INSN)) | |
111 | ||
112 | /* Likewise for the last instruction in a delayed branch sequence. */ | |
113 | #define SEQ_END(INSN) \ | |
114 | (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \ | |
115 | ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \ | |
116 | : (INSN)) | |
117 | ||
118 | /* Execute the following loop body with SUBINSN set to each instruction | |
119 | between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */ | |
120 | #define FOR_EACH_SUBINSN(SUBINSN, INSN) \ | |
121 | for ((SUBINSN) = SEQ_BEGIN (INSN); \ | |
122 | (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \ | |
123 | (SUBINSN) = NEXT_INSN (SUBINSN)) | |
cafe096b | 124 | |
e1260576 RS |
125 | /* True if bit BIT is set in VALUE. */ |
126 | #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0) | |
127 | ||
c640a3bd RS |
128 | /* Return the opcode for a ptr_mode load of the form: |
129 | ||
130 | l[wd] DEST, OFFSET(BASE). */ | |
131 | #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \ | |
132 | (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \ | |
133 | | ((BASE) << 21) \ | |
134 | | ((DEST) << 16) \ | |
135 | | (OFFSET)) | |
136 | ||
137 | /* Return the opcode to move register SRC into register DEST. */ | |
138 | #define MIPS_MOVE(DEST, SRC) \ | |
139 | ((TARGET_64BIT ? 0x2d : 0x21) \ | |
140 | | ((DEST) << 11) \ | |
141 | | ((SRC) << 21)) | |
142 | ||
143 | /* Return the opcode for: | |
144 | ||
145 | lui DEST, VALUE. */ | |
146 | #define MIPS_LUI(DEST, VALUE) \ | |
147 | ((0xf << 26) | ((DEST) << 16) | (VALUE)) | |
148 | ||
149 | /* Return the opcode to jump to register DEST. */ | |
150 | #define MIPS_JR(DEST) \ | |
151 | (((DEST) << 21) | 0x8) | |
152 | ||
153 | /* Return the opcode for: | |
154 | ||
155 | bal . + (1 + OFFSET) * 4. */ | |
156 | #define MIPS_BAL(OFFSET) \ | |
157 | ((0x1 << 26) | (0x11 << 16) | (OFFSET)) | |
158 | ||
159 | /* Return the usual opcode for a nop. */ | |
160 | #define MIPS_NOP 0 | |
161 | ||
cafe096b EC |
162 | /* Classifies an address. |
163 | ||
cafe096b EC |
164 | ADDRESS_REG |
165 | A natural register + offset address. The register satisfies | |
166 | mips_valid_base_register_p and the offset is a const_arith_operand. | |
167 | ||
168 | ADDRESS_LO_SUM | |
169 | A LO_SUM rtx. The first operand is a valid base register and | |
170 | the second operand is a symbolic address. | |
171 | ||
172 | ADDRESS_CONST_INT | |
173 | A signed 16-bit constant address. | |
174 | ||
175 | ADDRESS_SYMBOLIC: | |
65239d20 | 176 | A constant symbolic address. */ |
cafe096b | 177 | enum mips_address_type { |
cafe096b EC |
178 | ADDRESS_REG, |
179 | ADDRESS_LO_SUM, | |
180 | ADDRESS_CONST_INT, | |
181 | ADDRESS_SYMBOLIC | |
182 | }; | |
183 | ||
4d210b07 RS |
184 | /* Enumerates the setting of the -mr10k-cache-barrier option. */ |
185 | enum mips_r10k_cache_barrier_setting { | |
186 | R10K_CACHE_BARRIER_NONE, | |
187 | R10K_CACHE_BARRIER_STORE, | |
188 | R10K_CACHE_BARRIER_LOAD_STORE | |
189 | }; | |
190 | ||
41030557 RS |
191 | /* Macros to create an enumeration identifier for a function prototype. */ |
192 | #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B | |
193 | #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C | |
194 | #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D | |
195 | #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E | |
196 | ||
65239d20 RS |
197 | /* Classifies the prototype of a built-in function. */ |
198 | enum mips_function_type { | |
41030557 RS |
199 | #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST, |
200 | #include "config/mips/mips-ftypes.def" | |
201 | #undef DEF_MIPS_FTYPE | |
4ca1f68f RS |
202 | MIPS_MAX_FTYPE_MAX |
203 | }; | |
204 | ||
65239d20 RS |
205 | /* Specifies how a built-in function should be converted into rtl. */ |
206 | enum mips_builtin_type { | |
207 | /* The function corresponds directly to an .md pattern. The return | |
4ca1f68f RS |
208 | value is mapped to operand 0 and the arguments are mapped to |
209 | operands 1 and above. */ | |
210 | MIPS_BUILTIN_DIRECT, | |
211 | ||
65239d20 | 212 | /* The function corresponds directly to an .md pattern. There is no return |
118ea793 CF |
213 | value and the arguments are mapped to operands 0 and above. */ |
214 | MIPS_BUILTIN_DIRECT_NO_TARGET, | |
215 | ||
65239d20 | 216 | /* The function corresponds to a comparison instruction followed by |
4ca1f68f RS |
217 | a mips_cond_move_tf_ps pattern. The first two arguments are the |
218 | values to compare and the second two arguments are the vector | |
219 | operands for the movt.ps or movf.ps instruction (in assembly order). */ | |
220 | MIPS_BUILTIN_MOVF, | |
221 | MIPS_BUILTIN_MOVT, | |
222 | ||
65239d20 | 223 | /* The function corresponds to a V2SF comparison instruction. Operand 0 |
4ca1f68f RS |
224 | of this instruction is the result of the comparison, which has mode |
225 | CCV2 or CCV4. The function arguments are mapped to operands 1 and | |
226 | above. The function's return value is an SImode boolean that is | |
227 | true under the following conditions: | |
228 | ||
229 | MIPS_BUILTIN_CMP_ANY: one of the registers is true | |
230 | MIPS_BUILTIN_CMP_ALL: all of the registers are true | |
231 | MIPS_BUILTIN_CMP_LOWER: the first register is true | |
232 | MIPS_BUILTIN_CMP_UPPER: the second register is true. */ | |
233 | MIPS_BUILTIN_CMP_ANY, | |
234 | MIPS_BUILTIN_CMP_ALL, | |
235 | MIPS_BUILTIN_CMP_UPPER, | |
236 | MIPS_BUILTIN_CMP_LOWER, | |
237 | ||
238 | /* As above, but the instruction only sets a single $fcc register. */ | |
118ea793 CF |
239 | MIPS_BUILTIN_CMP_SINGLE, |
240 | ||
241 | /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */ | |
242 | MIPS_BUILTIN_BPOSGE32 | |
4ca1f68f RS |
243 | }; |
244 | ||
65239d20 | 245 | /* Invoke MACRO (COND) for each C.cond.fmt condition. */ |
308cd611 RS |
246 | #define MIPS_FP_CONDITIONS(MACRO) \ |
247 | MACRO (f), \ | |
248 | MACRO (un), \ | |
249 | MACRO (eq), \ | |
250 | MACRO (ueq), \ | |
251 | MACRO (olt), \ | |
252 | MACRO (ult), \ | |
253 | MACRO (ole), \ | |
254 | MACRO (ule), \ | |
255 | MACRO (sf), \ | |
256 | MACRO (ngle), \ | |
257 | MACRO (seq), \ | |
258 | MACRO (ngl), \ | |
259 | MACRO (lt), \ | |
260 | MACRO (nge), \ | |
261 | MACRO (le), \ | |
262 | MACRO (ngt) | |
263 | ||
264 | /* Enumerates the codes above as MIPS_FP_COND_<X>. */ | |
265 | #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X | |
266 | enum mips_fp_condition { | |
267 | MIPS_FP_CONDITIONS (DECLARE_MIPS_COND) | |
268 | }; | |
269 | ||
270 | /* Index X provides the string representation of MIPS_FP_COND_<X>. */ | |
271 | #define STRINGIFY(X) #X | |
272 | static const char *const mips_fp_conditions[] = { | |
273 | MIPS_FP_CONDITIONS (STRINGIFY) | |
274 | }; | |
275 | ||
16dc5c28 | 276 | /* Information about a function's frame layout. */ |
d1b38208 | 277 | struct GTY(()) mips_frame_info { |
37017f4d RS |
278 | /* The size of the frame in bytes. */ |
279 | HOST_WIDE_INT total_size; | |
280 | ||
281 | /* The number of bytes allocated to variables. */ | |
282 | HOST_WIDE_INT var_size; | |
283 | ||
284 | /* The number of bytes allocated to outgoing function arguments. */ | |
285 | HOST_WIDE_INT args_size; | |
286 | ||
287 | /* The number of bytes allocated to the .cprestore slot, or 0 if there | |
288 | is no such slot. */ | |
289 | HOST_WIDE_INT cprestore_size; | |
290 | ||
37017f4d RS |
291 | /* Bit X is set if the function saves or restores GPR X. */ |
292 | unsigned int mask; | |
293 | ||
294 | /* Likewise FPR X. */ | |
295 | unsigned int fmask; | |
296 | ||
e19da24c CF |
297 | /* Likewise doubleword accumulator X ($acX). */ |
298 | unsigned int acc_mask; | |
299 | ||
300 | /* The number of GPRs, FPRs, doubleword accumulators and COP0 | |
301 | registers saved. */ | |
37017f4d RS |
302 | unsigned int num_gp; |
303 | unsigned int num_fp; | |
e19da24c CF |
304 | unsigned int num_acc; |
305 | unsigned int num_cop0_regs; | |
37017f4d | 306 | |
e19da24c CF |
307 | /* The offset of the topmost GPR, FPR, accumulator and COP0-register |
308 | save slots from the top of the frame, or zero if no such slots are | |
309 | needed. */ | |
37017f4d RS |
310 | HOST_WIDE_INT gp_save_offset; |
311 | HOST_WIDE_INT fp_save_offset; | |
e19da24c CF |
312 | HOST_WIDE_INT acc_save_offset; |
313 | HOST_WIDE_INT cop0_save_offset; | |
37017f4d RS |
314 | |
315 | /* Likewise, but giving offsets from the bottom of the frame. */ | |
316 | HOST_WIDE_INT gp_sp_offset; | |
317 | HOST_WIDE_INT fp_sp_offset; | |
e19da24c CF |
318 | HOST_WIDE_INT acc_sp_offset; |
319 | HOST_WIDE_INT cop0_sp_offset; | |
37017f4d | 320 | |
c376dbfb DD |
321 | /* Similar, but the value passed to _mcount. */ |
322 | HOST_WIDE_INT ra_fp_offset; | |
323 | ||
ba6adec4 | 324 | /* The offset of arg_pointer_rtx from the bottom of the frame. */ |
f374e413 RS |
325 | HOST_WIDE_INT arg_pointer_offset; |
326 | ||
ba6adec4 | 327 | /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */ |
f374e413 | 328 | HOST_WIDE_INT hard_frame_pointer_offset; |
b2471838 RS |
329 | }; |
330 | ||
d1b38208 | 331 | struct GTY(()) machine_function { |
65239d20 | 332 | /* The register returned by mips16_gp_pseudo_reg; see there for details. */ |
c8d1b2b7 | 333 | rtx mips16_gp_pseudo_rtx; |
b2471838 | 334 | |
4001cd89 RS |
335 | /* The number of extra stack bytes taken up by register varargs. |
336 | This area is allocated by the callee at the very top of the frame. */ | |
337 | int varargs_size; | |
338 | ||
65239d20 | 339 | /* The current frame information, calculated by mips_compute_frame_info. */ |
b2471838 RS |
340 | struct mips_frame_info frame; |
341 | ||
8d9d9172 RS |
342 | /* The register to use as the function's global pointer, or INVALID_REGNUM |
343 | if the function doesn't need one. */ | |
f833ffd4 | 344 | unsigned int global_pointer; |
6f2993e5 | 345 | |
0c433c31 RS |
346 | /* How many instructions it takes to load a label into $AT, or 0 if |
347 | this property hasn't yet been calculated. */ | |
348 | unsigned int load_label_length; | |
349 | ||
6f2993e5 RS |
350 | /* True if mips_adjust_insn_length should ignore an instruction's |
351 | hazard attribute. */ | |
352 | bool ignore_hazard_length_p; | |
353 | ||
354 | /* True if the whole function is suitable for .set noreorder and | |
355 | .set nomacro. */ | |
356 | bool all_noreorder_p; | |
108b61d5 | 357 | |
0c433c31 RS |
358 | /* True if the function has "inflexible" and "flexible" references |
359 | to the global pointer. See mips_cfun_has_inflexible_gp_ref_p | |
360 | and mips_cfun_has_flexible_gp_ref_p for details. */ | |
361 | bool has_inflexible_gp_insn_p; | |
362 | bool has_flexible_gp_insn_p; | |
363 | ||
364 | /* True if the function's prologue must load the global pointer | |
365 | value into pic_offset_table_rtx and store the same value in | |
366 | the function's cprestore slot (if any). Even if this value | |
367 | is currently false, we may decide to set it to true later; | |
368 | see mips_must_initialize_gp_p () for details. */ | |
369 | bool must_initialize_gp_p; | |
370 | ||
371 | /* True if the current function must restore $gp after any potential | |
372 | clobber. This value is only meaningful during the first post-epilogue | |
373 | split_insns pass; see mips_must_initialize_gp_p () for details. */ | |
374 | bool must_restore_gp_when_clobbered_p; | |
d6076cee RS |
375 | |
376 | /* True if we have emitted an instruction to initialize | |
377 | mips16_gp_pseudo_rtx. */ | |
378 | bool initialized_mips16_gp_pseudo_p; | |
e19da24c CF |
379 | |
380 | /* True if this is an interrupt handler. */ | |
381 | bool interrupt_handler_p; | |
382 | ||
383 | /* True if this is an interrupt handler that uses shadow registers. */ | |
384 | bool use_shadow_register_set_p; | |
385 | ||
386 | /* True if this is an interrupt handler that should keep interrupts | |
387 | masked. */ | |
388 | bool keep_interrupts_masked_p; | |
389 | ||
390 | /* True if this is an interrupt handler that should use DERET | |
391 | instead of ERET. */ | |
392 | bool use_debug_exception_return_p; | |
c8d1b2b7 AO |
393 | }; |
394 | ||
4d72536e | 395 | /* Information about a single argument. */ |
65239d20 | 396 | struct mips_arg_info { |
4d72536e RS |
397 | /* True if the argument is passed in a floating-point register, or |
398 | would have been if we hadn't run out of registers. */ | |
399 | bool fpr_p; | |
400 | ||
4d72536e RS |
401 | /* The number of words passed in registers, rounded up. */ |
402 | unsigned int reg_words; | |
403 | ||
b11a9d5f RS |
404 | /* For EABI, the offset of the first register from GP_ARG_FIRST or |
405 | FP_ARG_FIRST. For other ABIs, the offset of the first register from | |
406 | the start of the ABI's argument structure (see the CUMULATIVE_ARGS | |
407 | comment for details). | |
408 | ||
409 | The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely | |
4d72536e RS |
410 | on the stack. */ |
411 | unsigned int reg_offset; | |
412 | ||
413 | /* The number of words that must be passed on the stack, rounded up. */ | |
414 | unsigned int stack_words; | |
415 | ||
416 | /* The offset from the start of the stack overflow area of the argument's | |
a0ab749a | 417 | first stack word. Only meaningful when STACK_WORDS is nonzero. */ |
4d72536e RS |
418 | unsigned int stack_offset; |
419 | }; | |
c8d1b2b7 | 420 | |
cafe096b EC |
421 | /* Information about an address described by mips_address_type. |
422 | ||
cafe096b EC |
423 | ADDRESS_CONST_INT |
424 | No fields are used. | |
425 | ||
426 | ADDRESS_REG | |
427 | REG is the base register and OFFSET is the constant offset. | |
428 | ||
429 | ADDRESS_LO_SUM | |
65239d20 RS |
430 | REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE |
431 | is the type of symbol it references. | |
cafe096b EC |
432 | |
433 | ADDRESS_SYMBOLIC | |
65239d20 RS |
434 | SYMBOL_TYPE is the type of symbol that the address references. */ |
435 | struct mips_address_info { | |
108b61d5 | 436 | enum mips_address_type type; |
cafe096b EC |
437 | rtx reg; |
438 | rtx offset; | |
108b61d5 | 439 | enum mips_symbol_type symbol_type; |
cafe096b EC |
440 | }; |
441 | ||
b259a9a6 RS |
442 | /* One stage in a constant building sequence. These sequences have |
443 | the form: | |
444 | ||
445 | A = VALUE[0] | |
446 | A = A CODE[1] VALUE[1] | |
447 | A = A CODE[2] VALUE[2] | |
448 | ... | |
449 | ||
450 | where A is an accumulator, each CODE[i] is a binary rtl operation | |
65239d20 | 451 | and each VALUE[i] is a constant integer. CODE[0] is undefined. */ |
b259a9a6 RS |
452 | struct mips_integer_op { |
453 | enum rtx_code code; | |
454 | unsigned HOST_WIDE_INT value; | |
455 | }; | |
456 | ||
b259a9a6 RS |
457 | /* The largest number of operations needed to load an integer constant. |
458 | The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI. | |
459 | When the lowest bit is clear, we can try, but reject a sequence with | |
460 | an extra SLL at the end. */ | |
461 | #define MIPS_MAX_INTEGER_OPS 7 | |
462 | ||
e1260576 RS |
463 | /* Information about a MIPS16e SAVE or RESTORE instruction. */ |
464 | struct mips16e_save_restore_info { | |
465 | /* The number of argument registers saved by a SAVE instruction. | |
466 | 0 for RESTORE instructions. */ | |
467 | unsigned int nargs; | |
468 | ||
469 | /* Bit X is set if the instruction saves or restores GPR X. */ | |
470 | unsigned int mask; | |
471 | ||
472 | /* The total number of bytes to allocate. */ | |
473 | HOST_WIDE_INT size; | |
474 | }; | |
b259a9a6 | 475 | |
cee98a59 MM |
476 | /* Global variables for machine-dependent things. */ |
477 | ||
65239d20 RS |
478 | /* The -G setting, or the configuration's default small-data limit if |
479 | no -G option is given. */ | |
480 | static unsigned int mips_small_data_threshold; | |
cee98a59 | 481 | |
65239d20 RS |
482 | /* The number of file directives written by mips_output_filename. */ |
483 | int num_source_filenames; | |
cee98a59 | 484 | |
65239d20 RS |
485 | /* The name that appeared in the last .file directive written by |
486 | mips_output_filename, or "" if mips_output_filename hasn't | |
487 | written anything yet. */ | |
ab77a036 RS |
488 | const char *current_function_file = ""; |
489 | ||
65239d20 RS |
490 | /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */ |
491 | int sdb_label_count; | |
cee98a59 | 492 | |
65239d20 | 493 | /* Arrays that map GCC register numbers to debugger register numbers. */ |
ab77a036 RS |
494 | int mips_dbx_regno[FIRST_PSEUDO_REGISTER]; |
495 | int mips_dwarf_regno[FIRST_PSEUDO_REGISTER]; | |
cee98a59 | 496 | |
65239d20 | 497 | /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */ |
cf5fb4b0 RS |
498 | struct mips_asm_switch mips_noreorder = { "reorder", 0 }; |
499 | struct mips_asm_switch mips_nomacro = { "macro", 0 }; | |
500 | struct mips_asm_switch mips_noat = { "at", 0 }; | |
cee98a59 | 501 | |
65239d20 RS |
502 | /* True if we're writing out a branch-likely instruction rather than a |
503 | normal branch. */ | |
504 | static bool mips_branch_likely; | |
cee98a59 | 505 | |
65239d20 | 506 | /* The current instruction-set architecture. */ |
7dac2f89 | 507 | enum processor_type mips_arch; |
a27fb29b | 508 | const struct mips_cpu_info *mips_arch_info; |
7dac2f89 | 509 | |
65239d20 | 510 | /* The processor that we should tune the code for. */ |
7dac2f89 | 511 | enum processor_type mips_tune; |
a27fb29b | 512 | const struct mips_cpu_info *mips_tune_info; |
7dac2f89 | 513 | |
65239d20 | 514 | /* The ISA level associated with mips_arch. */ |
cee98a59 MM |
515 | int mips_isa; |
516 | ||
65239d20 RS |
517 | /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */ |
518 | static const struct mips_cpu_info *mips_isa_option_info; | |
ab77a036 | 519 | |
dfad12b5 | 520 | /* Which ABI to use. */ |
d522e7a2 | 521 | int mips_abi = MIPS_ABI_DEFAULT; |
cee98a59 | 522 | |
65239d20 | 523 | /* Which cost information to use. */ |
c1bd2d66 EC |
524 | const struct mips_rtx_cost_data *mips_cost; |
525 | ||
65239d20 | 526 | /* The ambient target flags, excluding MASK_MIPS16. */ |
f9e4a411 | 527 | static int mips_base_target_flags; |
65239d20 RS |
528 | |
529 | /* True if MIPS16 is the default mode. */ | |
60730ade | 530 | bool mips_base_mips16; |
65239d20 RS |
531 | |
532 | /* The ambient values of other global variables. */ | |
f9e4a411 SL |
533 | static int mips_base_schedule_insns; /* flag_schedule_insns */ |
534 | static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */ | |
8d1d0dee | 535 | static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */ |
f9e4a411 SL |
536 | static int mips_base_align_loops; /* align_loops */ |
537 | static int mips_base_align_jumps; /* align_jumps */ | |
538 | static int mips_base_align_functions; /* align_functions */ | |
f9e4a411 | 539 | |
65239d20 | 540 | /* The -mcode-readable setting. */ |
c93c5160 RS |
541 | enum mips_code_readable_setting mips_code_readable = CODE_READABLE_YES; |
542 | ||
4d210b07 RS |
543 | /* The -mr10k-cache-barrier setting. */ |
544 | static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier; | |
545 | ||
65239d20 RS |
546 | /* Index [M][R] is true if register R is allowed to hold a value of mode M. */ |
547 | bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; | |
cee98a59 | 548 | |
65239d20 RS |
549 | /* Index C is true if character C is a valid PRINT_OPERAND punctation |
550 | character. */ | |
6e9e0126 | 551 | static bool mips_print_operand_punct[256]; |
cee98a59 | 552 | |
cafe096b EC |
553 | static GTY (()) int mips_output_filename_first_time = 1; |
554 | ||
108b61d5 | 555 | /* mips_split_p[X] is true if symbols of type X can be split by |
65239d20 | 556 | mips_split_symbol. */ |
ea462dd0 | 557 | bool mips_split_p[NUM_SYMBOL_TYPES]; |
108b61d5 | 558 | |
08d0963a RS |
559 | /* mips_split_hi_p[X] is true if the high parts of symbols of type X |
560 | can be split by mips_split_symbol. */ | |
561 | bool mips_split_hi_p[NUM_SYMBOL_TYPES]; | |
562 | ||
108b61d5 RS |
563 | /* mips_lo_relocs[X] is the relocation to use when a symbol of type X |
564 | appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or | |
565 | if they are matched by a special .md file pattern. */ | |
566 | static const char *mips_lo_relocs[NUM_SYMBOL_TYPES]; | |
567 | ||
568 | /* Likewise for HIGHs. */ | |
569 | static const char *mips_hi_relocs[NUM_SYMBOL_TYPES]; | |
570 | ||
65239d20 RS |
571 | /* Index R is the smallest register class that contains register R. */ |
572 | const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = { | |
08d0963a | 573 | LEA_REGS, LEA_REGS, M16_REGS, V1_REG, |
2bcb2ab3 | 574 | M16_REGS, M16_REGS, M16_REGS, M16_REGS, |
cafe096b EC |
575 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, |
576 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, | |
08d0963a | 577 | M16_REGS, M16_REGS, LEA_REGS, LEA_REGS, |
cafe096b EC |
578 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, |
579 | T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS, | |
580 | LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS, | |
cee98a59 MM |
581 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, |
582 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
583 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
584 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
585 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
586 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
587 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
588 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
48156a39 | 589 | MD0_REG, MD1_REG, NO_REGS, ST_REGS, |
b8eb88d0 | 590 | ST_REGS, ST_REGS, ST_REGS, ST_REGS, |
cafe096b | 591 | ST_REGS, ST_REGS, ST_REGS, NO_REGS, |
7314c7dd | 592 | NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS, |
d604bca3 MH |
593 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, |
594 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
595 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
596 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
597 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
598 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
599 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
600 | COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS, | |
601 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
602 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
603 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
604 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
605 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
606 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
607 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
608 | COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS, | |
609 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
610 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
611 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
612 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
613 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
614 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
615 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, | |
118ea793 CF |
616 | COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS, |
617 | DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, | |
618 | DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS, | |
619 | ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS | |
cee98a59 MM |
620 | }; |
621 | ||
65239d20 | 622 | /* The value of TARGET_ATTRIBUTE_TABLE. */ |
6bc7bc14 | 623 | static const struct attribute_spec mips_attribute_table[] = { |
65239d20 | 624 | /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ |
4dbdb061 | 625 | { "long_call", 0, 0, false, true, true, NULL }, |
cd3a59b3 SL |
626 | { "far", 0, 0, false, true, true, NULL }, |
627 | { "near", 0, 0, false, true, true, NULL }, | |
65239d20 RS |
628 | /* We would really like to treat "mips16" and "nomips16" as type |
629 | attributes, but GCC doesn't provide the hooks we need to support | |
630 | the right conversion rules. As declaration attributes, they affect | |
631 | code generation but don't carry other semantics. */ | |
9a6dfb47 RS |
632 | { "mips16", 0, 0, true, false, false, NULL }, |
633 | { "nomips16", 0, 0, true, false, false, NULL }, | |
e19da24c CF |
634 | /* Allow functions to be specified as interrupt handlers */ |
635 | { "interrupt", 0, 0, false, true, true, NULL }, | |
636 | { "use_shadow_register_set", 0, 0, false, true, true, NULL }, | |
637 | { "keep_interrupts_masked", 0, 0, false, true, true, NULL }, | |
638 | { "use_debug_exception_return", 0, 0, false, true, true, NULL }, | |
4dbdb061 JW |
639 | { NULL, 0, 0, false, false, false, NULL } |
640 | }; | |
672a6f42 | 641 | \f |
65239d20 | 642 | /* A table describing all the processors GCC knows about. Names are |
a27fb29b RS |
643 | matched in the order listed. The first mention of an ISA level is |
644 | taken as the canonical name for that ISA. | |
645 | ||
7d8bed7b | 646 | To ease comparison, please keep this table in the same order |
65239d20 | 647 | as GAS's mips_cpu_info_table. Please also make sure that |
7d8bed7b RS |
648 | MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march |
649 | options correctly. */ | |
65239d20 RS |
650 | static const struct mips_cpu_info mips_cpu_info_table[] = { |
651 | /* Entries for generic ISAs. */ | |
0da4c1ea RS |
652 | { "mips1", PROCESSOR_R3000, 1, 0 }, |
653 | { "mips2", PROCESSOR_R6000, 2, 0 }, | |
654 | { "mips3", PROCESSOR_R4000, 3, 0 }, | |
655 | { "mips4", PROCESSOR_R8000, 4, 0 }, | |
656 | /* Prefer not to use branch-likely instructions for generic MIPS32rX | |
657 | and MIPS64rX code. The instructions were officially deprecated | |
658 | in revisions 2 and earlier, but revision 3 is likely to downgrade | |
659 | that to a recommendation to avoid the instructions in code that | |
660 | isn't tuned to a specific processor. */ | |
661 | { "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY }, | |
662 | { "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY }, | |
663 | { "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY }, | |
f2d6ca50 AN |
664 | /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */ |
665 | { "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY }, | |
a27fb29b | 666 | |
65239d20 | 667 | /* MIPS I processors. */ |
0da4c1ea | 668 | { "r3000", PROCESSOR_R3000, 1, 0 }, |
65239d20 | 669 | { "r2000", PROCESSOR_R3000, 1, 0 }, |
0da4c1ea | 670 | { "r3900", PROCESSOR_R3900, 1, 0 }, |
a27fb29b | 671 | |
65239d20 | 672 | /* MIPS II processors. */ |
0da4c1ea | 673 | { "r6000", PROCESSOR_R6000, 2, 0 }, |
a27fb29b | 674 | |
65239d20 | 675 | /* MIPS III processors. */ |
0da4c1ea RS |
676 | { "r4000", PROCESSOR_R4000, 3, 0 }, |
677 | { "vr4100", PROCESSOR_R4100, 3, 0 }, | |
678 | { "vr4111", PROCESSOR_R4111, 3, 0 }, | |
679 | { "vr4120", PROCESSOR_R4120, 3, 0 }, | |
680 | { "vr4130", PROCESSOR_R4130, 3, 0 }, | |
681 | { "vr4300", PROCESSOR_R4300, 3, 0 }, | |
65239d20 | 682 | { "r4400", PROCESSOR_R4000, 3, 0 }, |
0da4c1ea | 683 | { "r4600", PROCESSOR_R4600, 3, 0 }, |
65239d20 | 684 | { "orion", PROCESSOR_R4600, 3, 0 }, |
0da4c1ea | 685 | { "r4650", PROCESSOR_R4650, 3, 0 }, |
33db2060 MS |
686 | /* ST Loongson 2E/2F processors. */ |
687 | { "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY }, | |
688 | { "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY }, | |
a27fb29b | 689 | |
65239d20 | 690 | /* MIPS IV processors. */ |
0da4c1ea | 691 | { "r8000", PROCESSOR_R8000, 4, 0 }, |
7a3446ec JK |
692 | { "r10000", PROCESSOR_R10000, 4, 0 }, |
693 | { "r12000", PROCESSOR_R10000, 4, 0 }, | |
694 | { "r14000", PROCESSOR_R10000, 4, 0 }, | |
695 | { "r16000", PROCESSOR_R10000, 4, 0 }, | |
0da4c1ea RS |
696 | { "vr5000", PROCESSOR_R5000, 4, 0 }, |
697 | { "vr5400", PROCESSOR_R5400, 4, 0 }, | |
698 | { "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY }, | |
699 | { "rm7000", PROCESSOR_R7000, 4, 0 }, | |
700 | { "rm9000", PROCESSOR_R9000, 4, 0 }, | |
5ce6f47b | 701 | |
65239d20 | 702 | /* MIPS32 processors. */ |
0da4c1ea | 703 | { "4kc", PROCESSOR_4KC, 32, 0 }, |
65239d20 | 704 | { "4km", PROCESSOR_4KC, 32, 0 }, |
0da4c1ea RS |
705 | { "4kp", PROCESSOR_4KP, 32, 0 }, |
706 | { "4ksc", PROCESSOR_4KC, 32, 0 }, | |
a27fb29b | 707 | |
65239d20 | 708 | /* MIPS32 Release 2 processors. */ |
0da4c1ea RS |
709 | { "m4k", PROCESSOR_M4K, 33, 0 }, |
710 | { "4kec", PROCESSOR_4KC, 33, 0 }, | |
711 | { "4kem", PROCESSOR_4KC, 33, 0 }, | |
712 | { "4kep", PROCESSOR_4KP, 33, 0 }, | |
713 | { "4ksd", PROCESSOR_4KC, 33, 0 }, | |
714 | ||
715 | { "24kc", PROCESSOR_24KC, 33, 0 }, | |
716 | { "24kf2_1", PROCESSOR_24KF2_1, 33, 0 }, | |
717 | { "24kf", PROCESSOR_24KF2_1, 33, 0 }, | |
718 | { "24kf1_1", PROCESSOR_24KF1_1, 33, 0 }, | |
719 | { "24kfx", PROCESSOR_24KF1_1, 33, 0 }, | |
720 | { "24kx", PROCESSOR_24KF1_1, 33, 0 }, | |
721 | ||
65239d20 | 722 | { "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */ |
0da4c1ea RS |
723 | { "24kef2_1", PROCESSOR_24KF2_1, 33, 0 }, |
724 | { "24kef", PROCESSOR_24KF2_1, 33, 0 }, | |
725 | { "24kef1_1", PROCESSOR_24KF1_1, 33, 0 }, | |
726 | { "24kefx", PROCESSOR_24KF1_1, 33, 0 }, | |
727 | { "24kex", PROCESSOR_24KF1_1, 33, 0 }, | |
728 | ||
65239d20 | 729 | { "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */ |
0da4c1ea RS |
730 | { "34kf2_1", PROCESSOR_24KF2_1, 33, 0 }, |
731 | { "34kf", PROCESSOR_24KF2_1, 33, 0 }, | |
732 | { "34kf1_1", PROCESSOR_24KF1_1, 33, 0 }, | |
733 | { "34kfx", PROCESSOR_24KF1_1, 33, 0 }, | |
734 | { "34kx", PROCESSOR_24KF1_1, 33, 0 }, | |
735 | ||
65239d20 | 736 | { "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */ |
0da4c1ea RS |
737 | { "74kf2_1", PROCESSOR_74KF2_1, 33, 0 }, |
738 | { "74kf", PROCESSOR_74KF2_1, 33, 0 }, | |
739 | { "74kf1_1", PROCESSOR_74KF1_1, 33, 0 }, | |
740 | { "74kfx", PROCESSOR_74KF1_1, 33, 0 }, | |
741 | { "74kx", PROCESSOR_74KF1_1, 33, 0 }, | |
742 | { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 }, | |
a27fb29b | 743 | |
5dce6dbd SL |
744 | { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */ |
745 | { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 }, | |
746 | { "1004kf", PROCESSOR_24KF2_1, 33, 0 }, | |
747 | { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 }, | |
748 | ||
65239d20 | 749 | /* MIPS64 processors. */ |
0da4c1ea RS |
750 | { "5kc", PROCESSOR_5KC, 64, 0 }, |
751 | { "5kf", PROCESSOR_5KF, 64, 0 }, | |
752 | { "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY }, | |
753 | { "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY }, | |
754 | { "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY }, | |
755 | { "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY }, | |
d97e6aca AN |
756 | { "xlr", PROCESSOR_XLR, 64, 0 }, |
757 | ||
758 | /* MIPS64 Release 2 processors. */ | |
759 | { "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY } | |
a27fb29b | 760 | }; |
c1bd2d66 | 761 | |
65239d20 | 762 | /* Default costs. If these are used for a processor we should look |
ff5c4582 | 763 | up the actual costs. */ |
c1bd2d66 EC |
764 | #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \ |
765 | COSTS_N_INSNS (7), /* fp_mult_sf */ \ | |
766 | COSTS_N_INSNS (8), /* fp_mult_df */ \ | |
767 | COSTS_N_INSNS (23), /* fp_div_sf */ \ | |
768 | COSTS_N_INSNS (36), /* fp_div_df */ \ | |
769 | COSTS_N_INSNS (10), /* int_mult_si */ \ | |
770 | COSTS_N_INSNS (10), /* int_mult_di */ \ | |
771 | COSTS_N_INSNS (69), /* int_div_si */ \ | |
772 | COSTS_N_INSNS (69), /* int_div_di */ \ | |
773 | 2, /* branch_cost */ \ | |
774 | 4 /* memory_latency */ | |
775 | ||
65239d20 RS |
776 | /* Floating-point costs for processors without an FPU. Just assume that |
777 | all floating-point libcalls are very expensive. */ | |
c1bd2d66 EC |
778 | #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \ |
779 | COSTS_N_INSNS (256), /* fp_mult_sf */ \ | |
780 | COSTS_N_INSNS (256), /* fp_mult_df */ \ | |
781 | COSTS_N_INSNS (256), /* fp_div_sf */ \ | |
782 | COSTS_N_INSNS (256) /* fp_div_df */ | |
783 | ||
65239d20 RS |
784 | /* Costs to use when optimizing for size. */ |
785 | static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = { | |
786 | COSTS_N_INSNS (1), /* fp_add */ | |
787 | COSTS_N_INSNS (1), /* fp_mult_sf */ | |
788 | COSTS_N_INSNS (1), /* fp_mult_df */ | |
789 | COSTS_N_INSNS (1), /* fp_div_sf */ | |
790 | COSTS_N_INSNS (1), /* fp_div_df */ | |
791 | COSTS_N_INSNS (1), /* int_mult_si */ | |
792 | COSTS_N_INSNS (1), /* int_mult_di */ | |
793 | COSTS_N_INSNS (1), /* int_div_si */ | |
794 | COSTS_N_INSNS (1), /* int_div_di */ | |
795 | 2, /* branch_cost */ | |
796 | 4 /* memory_latency */ | |
797 | }; | |
798 | ||
799 | /* Costs to use when optimizing for speed, indexed by processor. */ | |
800 | static const struct mips_rtx_cost_data mips_rtx_cost_data[PROCESSOR_MAX] = { | |
801 | { /* R3000 */ | |
802 | COSTS_N_INSNS (2), /* fp_add */ | |
803 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
804 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
805 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
806 | COSTS_N_INSNS (19), /* fp_div_df */ | |
807 | COSTS_N_INSNS (12), /* int_mult_si */ | |
808 | COSTS_N_INSNS (12), /* int_mult_di */ | |
809 | COSTS_N_INSNS (35), /* int_div_si */ | |
810 | COSTS_N_INSNS (35), /* int_div_di */ | |
811 | 1, /* branch_cost */ | |
812 | 4 /* memory_latency */ | |
813 | }, | |
814 | { /* 4KC */ | |
815 | SOFT_FP_COSTS, | |
816 | COSTS_N_INSNS (6), /* int_mult_si */ | |
817 | COSTS_N_INSNS (6), /* int_mult_di */ | |
818 | COSTS_N_INSNS (36), /* int_div_si */ | |
819 | COSTS_N_INSNS (36), /* int_div_di */ | |
820 | 1, /* branch_cost */ | |
821 | 4 /* memory_latency */ | |
822 | }, | |
823 | { /* 4KP */ | |
824 | SOFT_FP_COSTS, | |
825 | COSTS_N_INSNS (36), /* int_mult_si */ | |
826 | COSTS_N_INSNS (36), /* int_mult_di */ | |
827 | COSTS_N_INSNS (37), /* int_div_si */ | |
828 | COSTS_N_INSNS (37), /* int_div_di */ | |
829 | 1, /* branch_cost */ | |
830 | 4 /* memory_latency */ | |
831 | }, | |
832 | { /* 5KC */ | |
833 | SOFT_FP_COSTS, | |
834 | COSTS_N_INSNS (4), /* int_mult_si */ | |
835 | COSTS_N_INSNS (11), /* int_mult_di */ | |
836 | COSTS_N_INSNS (36), /* int_div_si */ | |
837 | COSTS_N_INSNS (68), /* int_div_di */ | |
838 | 1, /* branch_cost */ | |
839 | 4 /* memory_latency */ | |
840 | }, | |
841 | { /* 5KF */ | |
842 | COSTS_N_INSNS (4), /* fp_add */ | |
843 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
844 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
845 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
846 | COSTS_N_INSNS (32), /* fp_div_df */ | |
847 | COSTS_N_INSNS (4), /* int_mult_si */ | |
848 | COSTS_N_INSNS (11), /* int_mult_di */ | |
849 | COSTS_N_INSNS (36), /* int_div_si */ | |
850 | COSTS_N_INSNS (68), /* int_div_di */ | |
851 | 1, /* branch_cost */ | |
852 | 4 /* memory_latency */ | |
853 | }, | |
854 | { /* 20KC */ | |
855 | COSTS_N_INSNS (4), /* fp_add */ | |
856 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
857 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
858 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
859 | COSTS_N_INSNS (32), /* fp_div_df */ | |
860 | COSTS_N_INSNS (4), /* int_mult_si */ | |
861 | COSTS_N_INSNS (7), /* int_mult_di */ | |
862 | COSTS_N_INSNS (42), /* int_div_si */ | |
863 | COSTS_N_INSNS (72), /* int_div_di */ | |
864 | 1, /* branch_cost */ | |
865 | 4 /* memory_latency */ | |
866 | }, | |
867 | { /* 24KC */ | |
868 | SOFT_FP_COSTS, | |
869 | COSTS_N_INSNS (5), /* int_mult_si */ | |
870 | COSTS_N_INSNS (5), /* int_mult_di */ | |
871 | COSTS_N_INSNS (41), /* int_div_si */ | |
872 | COSTS_N_INSNS (41), /* int_div_di */ | |
873 | 1, /* branch_cost */ | |
874 | 4 /* memory_latency */ | |
875 | }, | |
876 | { /* 24KF2_1 */ | |
877 | COSTS_N_INSNS (8), /* fp_add */ | |
878 | COSTS_N_INSNS (8), /* fp_mult_sf */ | |
879 | COSTS_N_INSNS (10), /* fp_mult_df */ | |
880 | COSTS_N_INSNS (34), /* fp_div_sf */ | |
881 | COSTS_N_INSNS (64), /* fp_div_df */ | |
882 | COSTS_N_INSNS (5), /* int_mult_si */ | |
883 | COSTS_N_INSNS (5), /* int_mult_di */ | |
884 | COSTS_N_INSNS (41), /* int_div_si */ | |
885 | COSTS_N_INSNS (41), /* int_div_di */ | |
886 | 1, /* branch_cost */ | |
887 | 4 /* memory_latency */ | |
888 | }, | |
889 | { /* 24KF1_1 */ | |
890 | COSTS_N_INSNS (4), /* fp_add */ | |
891 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
892 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
893 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
894 | COSTS_N_INSNS (32), /* fp_div_df */ | |
895 | COSTS_N_INSNS (5), /* int_mult_si */ | |
896 | COSTS_N_INSNS (5), /* int_mult_di */ | |
897 | COSTS_N_INSNS (41), /* int_div_si */ | |
898 | COSTS_N_INSNS (41), /* int_div_di */ | |
899 | 1, /* branch_cost */ | |
900 | 4 /* memory_latency */ | |
901 | }, | |
902 | { /* 74KC */ | |
903 | SOFT_FP_COSTS, | |
904 | COSTS_N_INSNS (5), /* int_mult_si */ | |
905 | COSTS_N_INSNS (5), /* int_mult_di */ | |
906 | COSTS_N_INSNS (41), /* int_div_si */ | |
907 | COSTS_N_INSNS (41), /* int_div_di */ | |
908 | 1, /* branch_cost */ | |
909 | 4 /* memory_latency */ | |
910 | }, | |
911 | { /* 74KF2_1 */ | |
912 | COSTS_N_INSNS (8), /* fp_add */ | |
913 | COSTS_N_INSNS (8), /* fp_mult_sf */ | |
914 | COSTS_N_INSNS (10), /* fp_mult_df */ | |
915 | COSTS_N_INSNS (34), /* fp_div_sf */ | |
916 | COSTS_N_INSNS (64), /* fp_div_df */ | |
917 | COSTS_N_INSNS (5), /* int_mult_si */ | |
918 | COSTS_N_INSNS (5), /* int_mult_di */ | |
919 | COSTS_N_INSNS (41), /* int_div_si */ | |
920 | COSTS_N_INSNS (41), /* int_div_di */ | |
921 | 1, /* branch_cost */ | |
922 | 4 /* memory_latency */ | |
923 | }, | |
924 | { /* 74KF1_1 */ | |
925 | COSTS_N_INSNS (4), /* fp_add */ | |
926 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
927 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
928 | COSTS_N_INSNS (17), /* fp_div_sf */ | |
929 | COSTS_N_INSNS (32), /* fp_div_df */ | |
930 | COSTS_N_INSNS (5), /* int_mult_si */ | |
931 | COSTS_N_INSNS (5), /* int_mult_di */ | |
932 | COSTS_N_INSNS (41), /* int_div_si */ | |
933 | COSTS_N_INSNS (41), /* int_div_di */ | |
934 | 1, /* branch_cost */ | |
935 | 4 /* memory_latency */ | |
936 | }, | |
937 | { /* 74KF3_2 */ | |
938 | COSTS_N_INSNS (6), /* fp_add */ | |
939 | COSTS_N_INSNS (6), /* fp_mult_sf */ | |
940 | COSTS_N_INSNS (7), /* fp_mult_df */ | |
941 | COSTS_N_INSNS (25), /* fp_div_sf */ | |
942 | COSTS_N_INSNS (48), /* fp_div_df */ | |
943 | COSTS_N_INSNS (5), /* int_mult_si */ | |
944 | COSTS_N_INSNS (5), /* int_mult_di */ | |
945 | COSTS_N_INSNS (41), /* int_div_si */ | |
946 | COSTS_N_INSNS (41), /* int_div_di */ | |
947 | 1, /* branch_cost */ | |
948 | 4 /* memory_latency */ | |
949 | }, | |
33db2060 MS |
950 | { /* Loongson-2E */ |
951 | DEFAULT_COSTS | |
952 | }, | |
953 | { /* Loongson-2F */ | |
954 | DEFAULT_COSTS | |
955 | }, | |
65239d20 RS |
956 | { /* M4k */ |
957 | DEFAULT_COSTS | |
d97e6aca AN |
958 | }, |
959 | /* Octeon */ | |
960 | { | |
961 | SOFT_FP_COSTS, | |
962 | COSTS_N_INSNS (5), /* int_mult_si */ | |
963 | COSTS_N_INSNS (5), /* int_mult_di */ | |
964 | COSTS_N_INSNS (72), /* int_div_si */ | |
965 | COSTS_N_INSNS (72), /* int_div_di */ | |
966 | 1, /* branch_cost */ | |
967 | 4 /* memory_latency */ | |
65239d20 RS |
968 | }, |
969 | { /* R3900 */ | |
970 | COSTS_N_INSNS (2), /* fp_add */ | |
971 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
972 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
973 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
974 | COSTS_N_INSNS (19), /* fp_div_df */ | |
975 | COSTS_N_INSNS (2), /* int_mult_si */ | |
976 | COSTS_N_INSNS (2), /* int_mult_di */ | |
977 | COSTS_N_INSNS (35), /* int_div_si */ | |
978 | COSTS_N_INSNS (35), /* int_div_di */ | |
979 | 1, /* branch_cost */ | |
980 | 4 /* memory_latency */ | |
981 | }, | |
982 | { /* R6000 */ | |
983 | COSTS_N_INSNS (3), /* fp_add */ | |
984 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
985 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
986 | COSTS_N_INSNS (15), /* fp_div_sf */ | |
987 | COSTS_N_INSNS (16), /* fp_div_df */ | |
988 | COSTS_N_INSNS (17), /* int_mult_si */ | |
989 | COSTS_N_INSNS (17), /* int_mult_di */ | |
990 | COSTS_N_INSNS (38), /* int_div_si */ | |
991 | COSTS_N_INSNS (38), /* int_div_di */ | |
992 | 2, /* branch_cost */ | |
993 | 6 /* memory_latency */ | |
994 | }, | |
995 | { /* R4000 */ | |
996 | COSTS_N_INSNS (6), /* fp_add */ | |
997 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
998 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
999 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
1000 | COSTS_N_INSNS (36), /* fp_div_df */ | |
1001 | COSTS_N_INSNS (10), /* int_mult_si */ | |
1002 | COSTS_N_INSNS (10), /* int_mult_di */ | |
1003 | COSTS_N_INSNS (69), /* int_div_si */ | |
1004 | COSTS_N_INSNS (69), /* int_div_di */ | |
1005 | 2, /* branch_cost */ | |
1006 | 6 /* memory_latency */ | |
1007 | }, | |
1008 | { /* R4100 */ | |
1009 | DEFAULT_COSTS | |
1010 | }, | |
1011 | { /* R4111 */ | |
1012 | DEFAULT_COSTS | |
1013 | }, | |
1014 | { /* R4120 */ | |
1015 | DEFAULT_COSTS | |
1016 | }, | |
1017 | { /* R4130 */ | |
1018 | /* The only costs that appear to be updated here are | |
1019 | integer multiplication. */ | |
1020 | SOFT_FP_COSTS, | |
1021 | COSTS_N_INSNS (4), /* int_mult_si */ | |
1022 | COSTS_N_INSNS (6), /* int_mult_di */ | |
1023 | COSTS_N_INSNS (69), /* int_div_si */ | |
1024 | COSTS_N_INSNS (69), /* int_div_di */ | |
1025 | 1, /* branch_cost */ | |
1026 | 4 /* memory_latency */ | |
1027 | }, | |
1028 | { /* R4300 */ | |
1029 | DEFAULT_COSTS | |
1030 | }, | |
1031 | { /* R4600 */ | |
1032 | DEFAULT_COSTS | |
1033 | }, | |
1034 | { /* R4650 */ | |
1035 | DEFAULT_COSTS | |
1036 | }, | |
1037 | { /* R5000 */ | |
1038 | COSTS_N_INSNS (6), /* fp_add */ | |
1039 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1040 | COSTS_N_INSNS (5), /* fp_mult_df */ | |
1041 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
1042 | COSTS_N_INSNS (36), /* fp_div_df */ | |
1043 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1044 | COSTS_N_INSNS (5), /* int_mult_di */ | |
1045 | COSTS_N_INSNS (36), /* int_div_si */ | |
1046 | COSTS_N_INSNS (36), /* int_div_di */ | |
1047 | 1, /* branch_cost */ | |
1048 | 4 /* memory_latency */ | |
1049 | }, | |
1050 | { /* R5400 */ | |
1051 | COSTS_N_INSNS (6), /* fp_add */ | |
1052 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
1053 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
1054 | COSTS_N_INSNS (30), /* fp_div_sf */ | |
1055 | COSTS_N_INSNS (59), /* fp_div_df */ | |
1056 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1057 | COSTS_N_INSNS (4), /* int_mult_di */ | |
1058 | COSTS_N_INSNS (42), /* int_div_si */ | |
1059 | COSTS_N_INSNS (74), /* int_div_di */ | |
1060 | 1, /* branch_cost */ | |
1061 | 4 /* memory_latency */ | |
1062 | }, | |
1063 | { /* R5500 */ | |
1064 | COSTS_N_INSNS (6), /* fp_add */ | |
1065 | COSTS_N_INSNS (5), /* fp_mult_sf */ | |
1066 | COSTS_N_INSNS (6), /* fp_mult_df */ | |
1067 | COSTS_N_INSNS (30), /* fp_div_sf */ | |
1068 | COSTS_N_INSNS (59), /* fp_div_df */ | |
1069 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1070 | COSTS_N_INSNS (9), /* int_mult_di */ | |
1071 | COSTS_N_INSNS (42), /* int_div_si */ | |
1072 | COSTS_N_INSNS (74), /* int_div_di */ | |
1073 | 1, /* branch_cost */ | |
1074 | 4 /* memory_latency */ | |
1075 | }, | |
1076 | { /* R7000 */ | |
1077 | /* The only costs that are changed here are | |
1078 | integer multiplication. */ | |
1079 | COSTS_N_INSNS (6), /* fp_add */ | |
1080 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
1081 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
1082 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
1083 | COSTS_N_INSNS (36), /* fp_div_df */ | |
1084 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1085 | COSTS_N_INSNS (9), /* int_mult_di */ | |
1086 | COSTS_N_INSNS (69), /* int_div_si */ | |
1087 | COSTS_N_INSNS (69), /* int_div_di */ | |
1088 | 1, /* branch_cost */ | |
1089 | 4 /* memory_latency */ | |
1090 | }, | |
1091 | { /* R8000 */ | |
1092 | DEFAULT_COSTS | |
1093 | }, | |
1094 | { /* R9000 */ | |
1095 | /* The only costs that are changed here are | |
1096 | integer multiplication. */ | |
1097 | COSTS_N_INSNS (6), /* fp_add */ | |
1098 | COSTS_N_INSNS (7), /* fp_mult_sf */ | |
1099 | COSTS_N_INSNS (8), /* fp_mult_df */ | |
1100 | COSTS_N_INSNS (23), /* fp_div_sf */ | |
1101 | COSTS_N_INSNS (36), /* fp_div_df */ | |
1102 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1103 | COSTS_N_INSNS (8), /* int_mult_di */ | |
1104 | COSTS_N_INSNS (69), /* int_div_si */ | |
1105 | COSTS_N_INSNS (69), /* int_div_di */ | |
1106 | 1, /* branch_cost */ | |
1107 | 4 /* memory_latency */ | |
1108 | }, | |
7a3446ec JK |
1109 | { /* R1x000 */ |
1110 | COSTS_N_INSNS (2), /* fp_add */ | |
1111 | COSTS_N_INSNS (2), /* fp_mult_sf */ | |
1112 | COSTS_N_INSNS (2), /* fp_mult_df */ | |
1113 | COSTS_N_INSNS (12), /* fp_div_sf */ | |
1114 | COSTS_N_INSNS (19), /* fp_div_df */ | |
1115 | COSTS_N_INSNS (5), /* int_mult_si */ | |
1116 | COSTS_N_INSNS (9), /* int_mult_di */ | |
1117 | COSTS_N_INSNS (34), /* int_div_si */ | |
1118 | COSTS_N_INSNS (66), /* int_div_di */ | |
1119 | 1, /* branch_cost */ | |
1120 | 4 /* memory_latency */ | |
1121 | }, | |
65239d20 RS |
1122 | { /* SB1 */ |
1123 | /* These costs are the same as the SB-1A below. */ | |
1124 | COSTS_N_INSNS (4), /* fp_add */ | |
1125 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1126 | COSTS_N_INSNS (4), /* fp_mult_df */ | |
1127 | COSTS_N_INSNS (24), /* fp_div_sf */ | |
1128 | COSTS_N_INSNS (32), /* fp_div_df */ | |
1129 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1130 | COSTS_N_INSNS (4), /* int_mult_di */ | |
1131 | COSTS_N_INSNS (36), /* int_div_si */ | |
1132 | COSTS_N_INSNS (68), /* int_div_di */ | |
1133 | 1, /* branch_cost */ | |
1134 | 4 /* memory_latency */ | |
1135 | }, | |
1136 | { /* SB1-A */ | |
1137 | /* These costs are the same as the SB-1 above. */ | |
1138 | COSTS_N_INSNS (4), /* fp_add */ | |
1139 | COSTS_N_INSNS (4), /* fp_mult_sf */ | |
1140 | COSTS_N_INSNS (4), /* fp_mult_df */ | |
1141 | COSTS_N_INSNS (24), /* fp_div_sf */ | |
1142 | COSTS_N_INSNS (32), /* fp_div_df */ | |
1143 | COSTS_N_INSNS (3), /* int_mult_si */ | |
1144 | COSTS_N_INSNS (4), /* int_mult_di */ | |
1145 | COSTS_N_INSNS (36), /* int_div_si */ | |
1146 | COSTS_N_INSNS (68), /* int_div_di */ | |
1147 | 1, /* branch_cost */ | |
1148 | 4 /* memory_latency */ | |
1149 | }, | |
1150 | { /* SR71000 */ | |
1151 | DEFAULT_COSTS | |
1152 | }, | |
d0ae31b0 | 1153 | { /* XLR */ |
0051ef59 | 1154 | SOFT_FP_COSTS, |
d0ae31b0 SM |
1155 | COSTS_N_INSNS (8), /* int_mult_si */ |
1156 | COSTS_N_INSNS (8), /* int_mult_di */ | |
1157 | COSTS_N_INSNS (72), /* int_div_si */ | |
1158 | COSTS_N_INSNS (72), /* int_div_di */ | |
1159 | 1, /* branch_cost */ | |
1160 | 4 /* memory_latency */ | |
1161 | } | |
65239d20 | 1162 | }; |
a27fb29b | 1163 | \f |
b53da244 AN |
1164 | static rtx mips_find_pic_call_symbol (rtx, rtx); |
1165 | \f | |
65239d20 | 1166 | /* This hash table keeps track of implicit "mips16" and "nomips16" attributes |
ab77a036 | 1167 | for -mflip_mips16. It maps decl names onto a boolean mode setting. */ |
d1b38208 | 1168 | struct GTY (()) mflip_mips16_entry { |
ab77a036 RS |
1169 | const char *name; |
1170 | bool mips16_p; | |
1171 | }; | |
1172 | static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab; | |
4dbdb061 | 1173 | |
ab77a036 | 1174 | /* Hash table callbacks for mflip_mips16_htab. */ |
4dbdb061 | 1175 | |
ab77a036 RS |
1176 | static hashval_t |
1177 | mflip_mips16_htab_hash (const void *entry) | |
1178 | { | |
1179 | return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name); | |
1180 | } | |
912f2dac | 1181 | |
ab77a036 RS |
1182 | static int |
1183 | mflip_mips16_htab_eq (const void *entry, const void *name) | |
1184 | { | |
1185 | return strcmp (((const struct mflip_mips16_entry *) entry)->name, | |
1186 | (const char *) name) == 0; | |
1187 | } | |
ea462dd0 | 1188 | |
65239d20 RS |
1189 | /* True if -mflip-mips16 should next add an attribute for the default MIPS16 |
1190 | mode, false if it should next add an attribute for the opposite mode. */ | |
1191 | static GTY(()) bool mips16_flipper; | |
cd3a59b3 | 1192 | |
ab77a036 RS |
1193 | /* DECL is a function that needs a default "mips16" or "nomips16" attribute |
1194 | for -mflip-mips16. Return true if it should use "mips16" and false if | |
1195 | it should use "nomips16". */ | |
a44380d2 | 1196 | |
ab77a036 RS |
1197 | static bool |
1198 | mflip_mips16_use_mips16_p (tree decl) | |
1199 | { | |
1200 | struct mflip_mips16_entry *entry; | |
1201 | const char *name; | |
1202 | hashval_t hash; | |
1203 | void **slot; | |
076a5ce6 | 1204 | |
ab77a036 RS |
1205 | /* Use the opposite of the command-line setting for anonymous decls. */ |
1206 | if (!DECL_NAME (decl)) | |
1207 | return !mips_base_mips16; | |
cd3a59b3 | 1208 | |
ab77a036 RS |
1209 | if (!mflip_mips16_htab) |
1210 | mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash, | |
1211 | mflip_mips16_htab_eq, NULL); | |
cd3a59b3 | 1212 | |
ab77a036 RS |
1213 | name = IDENTIFIER_POINTER (DECL_NAME (decl)); |
1214 | hash = htab_hash_string (name); | |
1215 | slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT); | |
1216 | entry = (struct mflip_mips16_entry *) *slot; | |
1217 | if (!entry) | |
1218 | { | |
1219 | mips16_flipper = !mips16_flipper; | |
a9429e29 | 1220 | entry = ggc_alloc_mflip_mips16_entry (); |
ab77a036 RS |
1221 | entry->name = name; |
1222 | entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16; | |
1223 | *slot = entry; | |
1224 | } | |
1225 | return entry->mips16_p; | |
1226 | } | |
1227 | \f | |
cd3a59b3 SL |
1228 | /* Predicates to test for presence of "near" and "far"/"long_call" |
1229 | attributes on the given TYPE. */ | |
1230 | ||
1231 | static bool | |
3101faab | 1232 | mips_near_type_p (const_tree type) |
cd3a59b3 SL |
1233 | { |
1234 | return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL; | |
1235 | } | |
1236 | ||
1237 | static bool | |
3101faab | 1238 | mips_far_type_p (const_tree type) |
cd3a59b3 SL |
1239 | { |
1240 | return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL | |
1241 | || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL); | |
1242 | } | |
1243 | ||
65239d20 | 1244 | /* Similar predicates for "mips16"/"nomips16" function attributes. */ |
f9e4a411 SL |
1245 | |
1246 | static bool | |
9a6dfb47 | 1247 | mips_mips16_decl_p (const_tree decl) |
f9e4a411 | 1248 | { |
9a6dfb47 | 1249 | return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL; |
f9e4a411 SL |
1250 | } |
1251 | ||
1252 | static bool | |
9a6dfb47 | 1253 | mips_nomips16_decl_p (const_tree decl) |
f9e4a411 | 1254 | { |
9a6dfb47 | 1255 | return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL; |
f9e4a411 | 1256 | } |
cd3a59b3 | 1257 | |
e19da24c CF |
1258 | /* Check if the interrupt attribute is set for a function. */ |
1259 | ||
1260 | static bool | |
1261 | mips_interrupt_type_p (tree type) | |
1262 | { | |
1263 | return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL; | |
1264 | } | |
1265 | ||
1266 | /* Check if the attribute to use shadow register set is set for a function. */ | |
1267 | ||
1268 | static bool | |
1269 | mips_use_shadow_register_set_p (tree type) | |
1270 | { | |
1271 | return lookup_attribute ("use_shadow_register_set", | |
1272 | TYPE_ATTRIBUTES (type)) != NULL; | |
1273 | } | |
1274 | ||
1275 | /* Check if the attribute to keep interrupts masked is set for a function. */ | |
1276 | ||
1277 | static bool | |
1278 | mips_keep_interrupts_masked_p (tree type) | |
1279 | { | |
1280 | return lookup_attribute ("keep_interrupts_masked", | |
1281 | TYPE_ATTRIBUTES (type)) != NULL; | |
1282 | } | |
1283 | ||
1284 | /* Check if the attribute to use debug exception return is set for | |
1285 | a function. */ | |
1286 | ||
1287 | static bool | |
1288 | mips_use_debug_exception_return_p (tree type) | |
1289 | { | |
1290 | return lookup_attribute ("use_debug_exception_return", | |
1291 | TYPE_ATTRIBUTES (type)) != NULL; | |
1292 | } | |
1293 | ||
ab77a036 RS |
1294 | /* Return true if function DECL is a MIPS16 function. Return the ambient |
1295 | setting if DECL is null. */ | |
cd3a59b3 | 1296 | |
ab77a036 RS |
1297 | static bool |
1298 | mips_use_mips16_mode_p (tree decl) | |
cd3a59b3 | 1299 | { |
ab77a036 RS |
1300 | if (decl) |
1301 | { | |
1302 | /* Nested functions must use the same frame pointer as their | |
1303 | parent and must therefore use the same ISA mode. */ | |
1304 | tree parent = decl_function_context (decl); | |
1305 | if (parent) | |
1306 | decl = parent; | |
1307 | if (mips_mips16_decl_p (decl)) | |
1308 | return true; | |
1309 | if (mips_nomips16_decl_p (decl)) | |
1310 | return false; | |
1311 | } | |
1312 | return mips_base_mips16; | |
1313 | } | |
1314 | ||
65239d20 | 1315 | /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */ |
ab77a036 RS |
1316 | |
1317 | static int | |
1318 | mips_comp_type_attributes (const_tree type1, const_tree type2) | |
1319 | { | |
cd3a59b3 SL |
1320 | /* Disallow mixed near/far attributes. */ |
1321 | if (mips_far_type_p (type1) && mips_near_type_p (type2)) | |
1322 | return 0; | |
1323 | if (mips_near_type_p (type1) && mips_far_type_p (type2)) | |
1324 | return 0; | |
cd3a59b3 SL |
1325 | return 1; |
1326 | } | |
ab77a036 RS |
1327 | |
1328 | /* Implement TARGET_INSERT_ATTRIBUTES. */ | |
1329 | ||
1330 | static void | |
1331 | mips_insert_attributes (tree decl, tree *attributes) | |
1332 | { | |
1333 | const char *name; | |
1334 | bool mips16_p, nomips16_p; | |
1335 | ||
1336 | /* Check for "mips16" and "nomips16" attributes. */ | |
1337 | mips16_p = lookup_attribute ("mips16", *attributes) != NULL; | |
1338 | nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL; | |
1339 | if (TREE_CODE (decl) != FUNCTION_DECL) | |
1340 | { | |
1341 | if (mips16_p) | |
1342 | error ("%qs attribute only applies to functions", "mips16"); | |
1343 | if (nomips16_p) | |
1344 | error ("%qs attribute only applies to functions", "nomips16"); | |
1345 | } | |
1346 | else | |
1347 | { | |
1348 | mips16_p |= mips_mips16_decl_p (decl); | |
1349 | nomips16_p |= mips_nomips16_decl_p (decl); | |
1350 | if (mips16_p || nomips16_p) | |
1351 | { | |
65239d20 | 1352 | /* DECL cannot be simultaneously "mips16" and "nomips16". */ |
ab77a036 | 1353 | if (mips16_p && nomips16_p) |
29d08eba | 1354 | error ("%qE cannot have both %<mips16%> and " |
ab77a036 | 1355 | "%<nomips16%> attributes", |
29d08eba | 1356 | DECL_NAME (decl)); |
ab77a036 RS |
1357 | } |
1358 | else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl)) | |
1359 | { | |
1360 | /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a | |
1361 | "mips16" attribute, arbitrarily pick one. We must pick the same | |
1362 | setting for duplicate declarations of a function. */ | |
1363 | name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16"; | |
1364 | *attributes = tree_cons (get_identifier (name), NULL, *attributes); | |
1365 | } | |
1366 | } | |
1367 | } | |
1368 | ||
1369 | /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */ | |
1370 | ||
1371 | static tree | |
1372 | mips_merge_decl_attributes (tree olddecl, tree newdecl) | |
1373 | { | |
1374 | /* The decls' "mips16" and "nomips16" attributes must match exactly. */ | |
1375 | if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl)) | |
29d08eba JM |
1376 | error ("%qE redeclared with conflicting %qs attributes", |
1377 | DECL_NAME (newdecl), "mips16"); | |
ab77a036 | 1378 | if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl)) |
29d08eba JM |
1379 | error ("%qE redeclared with conflicting %qs attributes", |
1380 | DECL_NAME (newdecl), "nomips16"); | |
ab77a036 RS |
1381 | |
1382 | return merge_attributes (DECL_ATTRIBUTES (olddecl), | |
1383 | DECL_ATTRIBUTES (newdecl)); | |
1384 | } | |
cee98a59 | 1385 | \f |
e1260576 RS |
1386 | /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR |
1387 | and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */ | |
1388 | ||
1389 | static void | |
1390 | mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr) | |
1391 | { | |
47ac44d6 | 1392 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) |
e1260576 RS |
1393 | { |
1394 | *base_ptr = XEXP (x, 0); | |
1395 | *offset_ptr = INTVAL (XEXP (x, 1)); | |
1396 | } | |
1397 | else | |
1398 | { | |
1399 | *base_ptr = x; | |
1400 | *offset_ptr = 0; | |
1401 | } | |
1402 | } | |
1403 | \f | |
ab77a036 RS |
1404 | static unsigned int mips_build_integer (struct mips_integer_op *, |
1405 | unsigned HOST_WIDE_INT); | |
1406 | ||
65239d20 | 1407 | /* A subroutine of mips_build_integer, with the same interface. |
ab77a036 RS |
1408 | Assume that the final action in the sequence should be a left shift. */ |
1409 | ||
1410 | static unsigned int | |
1411 | mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value) | |
1412 | { | |
1413 | unsigned int i, shift; | |
1414 | ||
1415 | /* Shift VALUE right until its lowest bit is set. Shift arithmetically | |
1416 | since signed numbers are easier to load than unsigned ones. */ | |
1417 | shift = 0; | |
1418 | while ((value & 1) == 0) | |
1419 | value /= 2, shift++; | |
1420 | ||
1421 | i = mips_build_integer (codes, value); | |
1422 | codes[i].code = ASHIFT; | |
1423 | codes[i].value = shift; | |
1424 | return i + 1; | |
1425 | } | |
1426 | ||
ab77a036 RS |
1427 | /* As for mips_build_shift, but assume that the final action will be |
1428 | an IOR or PLUS operation. */ | |
1429 | ||
1430 | static unsigned int | |
1431 | mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value) | |
1432 | { | |
1433 | unsigned HOST_WIDE_INT high; | |
1434 | unsigned int i; | |
1435 | ||
1436 | high = value & ~(unsigned HOST_WIDE_INT) 0xffff; | |
1437 | if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000) | |
1438 | { | |
65239d20 RS |
1439 | /* The constant is too complex to load with a simple LUI/ORI pair, |
1440 | so we want to give the recursive call as many trailing zeros as | |
1441 | possible. In this case, we know bit 16 is set and that the | |
1442 | low 16 bits form a negative number. If we subtract that number | |
1443 | from VALUE, we will clear at least the lowest 17 bits, maybe more. */ | |
ab77a036 RS |
1444 | i = mips_build_integer (codes, CONST_HIGH_PART (value)); |
1445 | codes[i].code = PLUS; | |
1446 | codes[i].value = CONST_LOW_PART (value); | |
1447 | } | |
1448 | else | |
1449 | { | |
65239d20 RS |
1450 | /* Either this is a simple LUI/ORI pair, or clearing the lowest 16 |
1451 | bits gives a value with at least 17 trailing zeros. */ | |
ab77a036 RS |
1452 | i = mips_build_integer (codes, high); |
1453 | codes[i].code = IOR; | |
1454 | codes[i].value = value & 0xffff; | |
1455 | } | |
1456 | return i + 1; | |
1457 | } | |
1458 | ||
ab77a036 RS |
1459 | /* Fill CODES with a sequence of rtl operations to load VALUE. |
1460 | Return the number of operations needed. */ | |
1461 | ||
1462 | static unsigned int | |
1463 | mips_build_integer (struct mips_integer_op *codes, | |
1464 | unsigned HOST_WIDE_INT value) | |
1465 | { | |
1466 | if (SMALL_OPERAND (value) | |
1467 | || SMALL_OPERAND_UNSIGNED (value) | |
1468 | || LUI_OPERAND (value)) | |
1469 | { | |
1470 | /* The value can be loaded with a single instruction. */ | |
1471 | codes[0].code = UNKNOWN; | |
1472 | codes[0].value = value; | |
1473 | return 1; | |
1474 | } | |
1475 | else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value))) | |
1476 | { | |
1477 | /* Either the constant is a simple LUI/ORI combination or its | |
1478 | lowest bit is set. We don't want to shift in this case. */ | |
1479 | return mips_build_lower (codes, value); | |
1480 | } | |
1481 | else if ((value & 0xffff) == 0) | |
1482 | { | |
1483 | /* The constant will need at least three actions. The lowest | |
1484 | 16 bits are clear, so the final action will be a shift. */ | |
1485 | return mips_build_shift (codes, value); | |
1486 | } | |
1487 | else | |
1488 | { | |
1489 | /* The final action could be a shift, add or inclusive OR. | |
1490 | Rather than use a complex condition to select the best | |
1491 | approach, try both mips_build_shift and mips_build_lower | |
1492 | and pick the one that gives the shortest sequence. | |
1493 | Note that this case is only used once per constant. */ | |
1494 | struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS]; | |
1495 | unsigned int cost, alt_cost; | |
1496 | ||
1497 | cost = mips_build_shift (codes, value); | |
1498 | alt_cost = mips_build_lower (alt_codes, value); | |
1499 | if (alt_cost < cost) | |
1500 | { | |
1501 | memcpy (codes, alt_codes, alt_cost * sizeof (codes[0])); | |
1502 | cost = alt_cost; | |
1503 | } | |
1504 | return cost; | |
1505 | } | |
1506 | } | |
1507 | \f | |
08d0963a RS |
1508 | /* Return true if symbols of type TYPE require a GOT access. */ |
1509 | ||
1510 | static bool | |
1511 | mips_got_symbol_type_p (enum mips_symbol_type type) | |
1512 | { | |
1513 | switch (type) | |
1514 | { | |
1515 | case SYMBOL_GOT_PAGE_OFST: | |
1516 | case SYMBOL_GOT_DISP: | |
1517 | return true; | |
1518 | ||
1519 | default: | |
1520 | return false; | |
1521 | } | |
1522 | } | |
1523 | ||
ab77a036 RS |
1524 | /* Return true if X is a thread-local symbol. */ |
1525 | ||
1526 | static bool | |
65239d20 | 1527 | mips_tls_symbol_p (rtx x) |
ab77a036 RS |
1528 | { |
1529 | return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; | |
1530 | } | |
1531 | ||
08e7ceb3 RS |
1532 | /* Return true if SYMBOL_REF X is associated with a global symbol |
1533 | (in the STB_GLOBAL sense). */ | |
1534 | ||
1535 | static bool | |
3101faab | 1536 | mips_global_symbol_p (const_rtx x) |
08e7ceb3 | 1537 | { |
65239d20 | 1538 | const_tree decl = SYMBOL_REF_DECL (x); |
08e7ceb3 | 1539 | |
08e7ceb3 | 1540 | if (!decl) |
08d0963a | 1541 | return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x); |
08e7ceb3 RS |
1542 | |
1543 | /* Weakref symbols are not TREE_PUBLIC, but their targets are global | |
1544 | or weak symbols. Relocations in the object file will be against | |
1545 | the target symbol, so it's that symbol's binding that matters here. */ | |
1546 | return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl)); | |
1547 | } | |
1548 | ||
08d0963a RS |
1549 | /* Return true if function X is a libgcc MIPS16 stub function. */ |
1550 | ||
1551 | static bool | |
1552 | mips16_stub_function_p (const_rtx x) | |
1553 | { | |
1554 | return (GET_CODE (x) == SYMBOL_REF | |
1555 | && strncmp (XSTR (x, 0), "__mips16_", 9) == 0); | |
1556 | } | |
1557 | ||
1558 | /* Return true if function X is a locally-defined and locally-binding | |
1559 | MIPS16 function. */ | |
1560 | ||
1561 | static bool | |
1562 | mips16_local_function_p (const_rtx x) | |
1563 | { | |
1564 | return (GET_CODE (x) == SYMBOL_REF | |
1565 | && SYMBOL_REF_LOCAL_P (x) | |
1566 | && !SYMBOL_REF_EXTERNAL_P (x) | |
1567 | && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x))); | |
1568 | } | |
1569 | ||
08e7ceb3 RS |
1570 | /* Return true if SYMBOL_REF X binds locally. */ |
1571 | ||
1572 | static bool | |
3101faab | 1573 | mips_symbol_binds_local_p (const_rtx x) |
08e7ceb3 RS |
1574 | { |
1575 | return (SYMBOL_REF_DECL (x) | |
1576 | ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) | |
1577 | : SYMBOL_REF_LOCAL_P (x)); | |
1578 | } | |
1579 | ||
a318179e RS |
1580 | /* Return true if rtx constants of mode MODE should be put into a small |
1581 | data section. */ | |
1582 | ||
1583 | static bool | |
1584 | mips_rtx_constant_in_small_data_p (enum machine_mode mode) | |
1585 | { | |
1586 | return (!TARGET_EMBEDDED_DATA | |
1587 | && TARGET_LOCAL_SDATA | |
65239d20 | 1588 | && GET_MODE_SIZE (mode) <= mips_small_data_threshold); |
a318179e RS |
1589 | } |
1590 | ||
ab77a036 RS |
1591 | /* Return true if X should not be moved directly into register $25. |
1592 | We need this because many versions of GAS will treat "la $25,foo" as | |
1593 | part of a call sequence and so allow a global "foo" to be lazily bound. */ | |
1594 | ||
1595 | bool | |
1596 | mips_dangerous_for_la25_p (rtx x) | |
1597 | { | |
1598 | return (!TARGET_EXPLICIT_RELOCS | |
1599 | && TARGET_USE_GOT | |
1600 | && GET_CODE (x) == SYMBOL_REF | |
1601 | && mips_global_symbol_p (x)); | |
1602 | } | |
1603 | ||
08d0963a RS |
1604 | /* Return true if calls to X might need $25 to be valid on entry. */ |
1605 | ||
1606 | bool | |
1607 | mips_use_pic_fn_addr_reg_p (const_rtx x) | |
1608 | { | |
1609 | if (!TARGET_USE_PIC_FN_ADDR_REG) | |
1610 | return false; | |
1611 | ||
1612 | /* MIPS16 stub functions are guaranteed not to use $25. */ | |
1613 | if (mips16_stub_function_p (x)) | |
1614 | return false; | |
1615 | ||
e21d5757 DJ |
1616 | if (GET_CODE (x) == SYMBOL_REF) |
1617 | { | |
1618 | /* If PLTs and copy relocations are available, the static linker | |
1619 | will make sure that $25 is valid on entry to the target function. */ | |
1620 | if (TARGET_ABICALLS_PIC0) | |
1621 | return false; | |
1622 | ||
1623 | /* Locally-defined functions use absolute accesses to set up | |
1624 | the global pointer. */ | |
1625 | if (TARGET_ABSOLUTE_ABICALLS | |
1626 | && mips_symbol_binds_local_p (x) | |
1627 | && !SYMBOL_REF_EXTERNAL_P (x)) | |
1628 | return false; | |
1629 | } | |
08d0963a RS |
1630 | |
1631 | return true; | |
1632 | } | |
1633 | ||
280fcbfa RS |
1634 | /* Return the method that should be used to access SYMBOL_REF or |
1635 | LABEL_REF X in context CONTEXT. */ | |
cafe096b EC |
1636 | |
1637 | static enum mips_symbol_type | |
3101faab | 1638 | mips_classify_symbol (const_rtx x, enum mips_symbol_context context) |
cee98a59 | 1639 | { |
8cb6400c RS |
1640 | if (TARGET_RTP_PIC) |
1641 | return SYMBOL_GOT_DISP; | |
1642 | ||
cafe096b | 1643 | if (GET_CODE (x) == LABEL_REF) |
76cbf5bf | 1644 | { |
c93c5160 RS |
1645 | /* LABEL_REFs are used for jump tables as well as text labels. |
1646 | Only return SYMBOL_PC_RELATIVE if we know the label is in | |
1647 | the text section. */ | |
1648 | if (TARGET_MIPS16_SHORT_JUMP_TABLES) | |
67da85da | 1649 | return SYMBOL_PC_RELATIVE; |
65239d20 | 1650 | |
d9870b7e | 1651 | if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) |
08e7ceb3 | 1652 | return SYMBOL_GOT_PAGE_OFST; |
65239d20 | 1653 | |
67da85da | 1654 | return SYMBOL_ABSOLUTE; |
76cbf5bf | 1655 | } |
cee98a59 | 1656 | |
7ad769fe | 1657 | gcc_assert (GET_CODE (x) == SYMBOL_REF); |
2bcb2ab3 | 1658 | |
69229b81 DJ |
1659 | if (SYMBOL_REF_TLS_MODEL (x)) |
1660 | return SYMBOL_TLS; | |
1661 | ||
cafe096b EC |
1662 | if (CONSTANT_POOL_ADDRESS_P (x)) |
1663 | { | |
c93c5160 RS |
1664 | if (TARGET_MIPS16_TEXT_LOADS) |
1665 | return SYMBOL_PC_RELATIVE; | |
1666 | ||
1667 | if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM) | |
67da85da | 1668 | return SYMBOL_PC_RELATIVE; |
cee98a59 | 1669 | |
a318179e | 1670 | if (mips_rtx_constant_in_small_data_p (get_pool_mode (x))) |
67da85da | 1671 | return SYMBOL_GP_RELATIVE; |
cafe096b EC |
1672 | } |
1673 | ||
3ac25120 RS |
1674 | /* Do not use small-data accesses for weak symbols; they may end up |
1675 | being zero. */ | |
65239d20 | 1676 | if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x)) |
67da85da | 1677 | return SYMBOL_GP_RELATIVE; |
b8898790 | 1678 | |
e06e2776 RS |
1679 | /* Don't use GOT accesses for locally-binding symbols when -mno-shared |
1680 | is in effect. */ | |
e21d5757 | 1681 | if (TARGET_ABICALLS_PIC2 |
e06e2776 | 1682 | && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x))) |
f6149877 | 1683 | { |
08e7ceb3 RS |
1684 | /* There are three cases to consider: |
1685 | ||
1686 | - o32 PIC (either with or without explicit relocs) | |
1687 | - n32/n64 PIC without explicit relocs | |
1688 | - n32/n64 PIC with explicit relocs | |
1689 | ||
1690 | In the first case, both local and global accesses will use an | |
1691 | R_MIPS_GOT16 relocation. We must correctly predict which of | |
1692 | the two semantics (local or global) the assembler and linker | |
1693 | will apply. The choice depends on the symbol's binding rather | |
1694 | than its visibility. | |
f6149877 | 1695 | |
08e7ceb3 RS |
1696 | In the second case, the assembler will not use R_MIPS_GOT16 |
1697 | relocations, but it chooses between local and global accesses | |
1698 | in the same way as for o32 PIC. | |
1699 | ||
1700 | In the third case we have more freedom since both forms of | |
1701 | access will work for any kind of symbol. However, there seems | |
1702 | little point in doing things differently. */ | |
1703 | if (mips_global_symbol_p (x)) | |
1704 | return SYMBOL_GOT_DISP; | |
1705 | ||
1706 | return SYMBOL_GOT_PAGE_OFST; | |
f6149877 | 1707 | } |
cafe096b | 1708 | |
c93c5160 | 1709 | if (TARGET_MIPS16_PCREL_LOADS && context != SYMBOL_CONTEXT_CALL) |
e06e2776 | 1710 | return SYMBOL_FORCE_TO_MEM; |
65239d20 | 1711 | |
67da85da | 1712 | return SYMBOL_ABSOLUTE; |
cee98a59 MM |
1713 | } |
1714 | ||
65239d20 RS |
1715 | /* Classify the base of symbolic expression X, given that X appears in |
1716 | context CONTEXT. */ | |
6d992de0 RS |
1717 | |
1718 | static enum mips_symbol_type | |
1719 | mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context) | |
1720 | { | |
1721 | rtx offset; | |
1722 | ||
1723 | split_const (x, &x, &offset); | |
1724 | if (UNSPEC_ADDRESS_P (x)) | |
1725 | return UNSPEC_ADDRESS_TYPE (x); | |
1726 | ||
1727 | return mips_classify_symbol (x, context); | |
1728 | } | |
1729 | ||
6de36441 | 1730 | /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN |
65239d20 | 1731 | is the alignment in bytes of SYMBOL_REF X. */ |
8b5fb3a3 DD |
1732 | |
1733 | static bool | |
1734 | mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset) | |
1735 | { | |
65239d20 | 1736 | HOST_WIDE_INT align; |
8b5fb3a3 | 1737 | |
65239d20 RS |
1738 | align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1; |
1739 | return IN_RANGE (offset, 0, align - 1); | |
8b5fb3a3 DD |
1740 | } |
1741 | ||
280fcbfa RS |
1742 | /* Return true if X is a symbolic constant that can be used in context |
1743 | CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */ | |
108b61d5 | 1744 | |
96a30b18 | 1745 | bool |
280fcbfa RS |
1746 | mips_symbolic_constant_p (rtx x, enum mips_symbol_context context, |
1747 | enum mips_symbol_type *symbol_type) | |
108b61d5 | 1748 | { |
7ffb5e78 | 1749 | rtx offset; |
108b61d5 | 1750 | |
7ffb5e78 | 1751 | split_const (x, &x, &offset); |
108b61d5 | 1752 | if (UNSPEC_ADDRESS_P (x)) |
8b5fb3a3 DD |
1753 | { |
1754 | *symbol_type = UNSPEC_ADDRESS_TYPE (x); | |
1755 | x = UNSPEC_ADDRESS (x); | |
1756 | } | |
108b61d5 | 1757 | else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) |
69229b81 | 1758 | { |
280fcbfa | 1759 | *symbol_type = mips_classify_symbol (x, context); |
69229b81 DJ |
1760 | if (*symbol_type == SYMBOL_TLS) |
1761 | return false; | |
1762 | } | |
108b61d5 RS |
1763 | else |
1764 | return false; | |
1765 | ||
7ffb5e78 | 1766 | if (offset == const0_rtx) |
108b61d5 RS |
1767 | return true; |
1768 | ||
1769 | /* Check whether a nonzero offset is valid for the underlying | |
1770 | relocations. */ | |
1771 | switch (*symbol_type) | |
1772 | { | |
67da85da | 1773 | case SYMBOL_ABSOLUTE: |
e06e2776 | 1774 | case SYMBOL_FORCE_TO_MEM: |
c93c5160 | 1775 | case SYMBOL_32_HIGH: |
e245bd81 RS |
1776 | case SYMBOL_64_HIGH: |
1777 | case SYMBOL_64_MID: | |
1778 | case SYMBOL_64_LOW: | |
62973ffe RS |
1779 | /* If the target has 64-bit pointers and the object file only |
1780 | supports 32-bit symbols, the values of those symbols will be | |
1781 | sign-extended. In this case we can't allow an arbitrary offset | |
1782 | in case the 32-bit value X + OFFSET has a different sign from X. */ | |
1783 | if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS) | |
7ffb5e78 | 1784 | return offset_within_block_p (x, INTVAL (offset)); |
62973ffe RS |
1785 | |
1786 | /* In other cases the relocations can handle any offset. */ | |
108b61d5 RS |
1787 | return true; |
1788 | ||
67da85da | 1789 | case SYMBOL_PC_RELATIVE: |
76cbf5bf RS |
1790 | /* Allow constant pool references to be converted to LABEL+CONSTANT. |
1791 | In this case, we no longer have access to the underlying constant, | |
1792 | but the original symbol-based access was known to be valid. */ | |
1793 | if (GET_CODE (x) == LABEL_REF) | |
1794 | return true; | |
1795 | ||
1796 | /* Fall through. */ | |
1797 | ||
67da85da | 1798 | case SYMBOL_GP_RELATIVE: |
62973ffe | 1799 | /* Make sure that the offset refers to something within the |
7ffb5e78 | 1800 | same object block. This should guarantee that the final |
62973ffe | 1801 | PC- or GP-relative offset is within the 16-bit limit. */ |
7ffb5e78 | 1802 | return offset_within_block_p (x, INTVAL (offset)); |
108b61d5 | 1803 | |
08e7ceb3 | 1804 | case SYMBOL_GOT_PAGE_OFST: |
108b61d5 | 1805 | case SYMBOL_GOTOFF_PAGE: |
08e7ceb3 RS |
1806 | /* If the symbol is global, the GOT entry will contain the symbol's |
1807 | address, and we will apply a 16-bit offset after loading it. | |
1808 | If the symbol is local, the linker should provide enough local | |
1809 | GOT entries for a 16-bit offset, but larger offsets may lead | |
1810 | to GOT overflow. */ | |
7ffb5e78 | 1811 | return SMALL_INT (offset); |
108b61d5 | 1812 | |
8b5fb3a3 DD |
1813 | case SYMBOL_TPREL: |
1814 | case SYMBOL_DTPREL: | |
1815 | /* There is no carry between the HI and LO REL relocations, so the | |
1816 | offset is only valid if we know it won't lead to such a carry. */ | |
1817 | return mips_offset_within_alignment_p (x, INTVAL (offset)); | |
1818 | ||
08e7ceb3 RS |
1819 | case SYMBOL_GOT_DISP: |
1820 | case SYMBOL_GOTOFF_DISP: | |
108b61d5 RS |
1821 | case SYMBOL_GOTOFF_CALL: |
1822 | case SYMBOL_GOTOFF_LOADGP: | |
69229b81 DJ |
1823 | case SYMBOL_TLSGD: |
1824 | case SYMBOL_TLSLDM: | |
69229b81 DJ |
1825 | case SYMBOL_GOTTPREL: |
1826 | case SYMBOL_TLS: | |
8cb6400c | 1827 | case SYMBOL_HALF: |
108b61d5 RS |
1828 | return false; |
1829 | } | |
7ad769fe | 1830 | gcc_unreachable (); |
108b61d5 | 1831 | } |
ab77a036 RS |
1832 | \f |
1833 | /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a | |
1834 | single instruction. We rely on the fact that, in the worst case, | |
1835 | all instructions involved in a MIPS16 address calculation are usually | |
1836 | extended ones. */ | |
108b61d5 | 1837 | |
ab77a036 RS |
1838 | static int |
1839 | mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode) | |
cee98a59 | 1840 | { |
ab77a036 | 1841 | switch (type) |
bcbc6b7f | 1842 | { |
ab77a036 RS |
1843 | case SYMBOL_ABSOLUTE: |
1844 | /* When using 64-bit symbols, we need 5 preparatory instructions, | |
1845 | such as: | |
bcbc6b7f | 1846 | |
ab77a036 RS |
1847 | lui $at,%highest(symbol) |
1848 | daddiu $at,$at,%higher(symbol) | |
1849 | dsll $at,$at,16 | |
1850 | daddiu $at,$at,%hi(symbol) | |
1851 | dsll $at,$at,16 | |
bcbc6b7f | 1852 | |
ab77a036 | 1853 | The final address is then $at + %lo(symbol). With 32-bit |
65239d20 RS |
1854 | symbols we just need a preparatory LUI for normal mode and |
1855 | a preparatory LI and SLL for MIPS16. */ | |
ab77a036 | 1856 | return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2; |
bcbc6b7f | 1857 | |
ab77a036 RS |
1858 | case SYMBOL_GP_RELATIVE: |
1859 | /* Treat GP-relative accesses as taking a single instruction on | |
1860 | MIPS16 too; the copy of $gp can often be shared. */ | |
1861 | return 1; | |
b8eb88d0 | 1862 | |
67da85da | 1863 | case SYMBOL_PC_RELATIVE: |
65239d20 RS |
1864 | /* PC-relative constants can be only be used with ADDIUPC, |
1865 | DADDIUPC, LWPC and LDPC. */ | |
fbb96ac5 RS |
1866 | if (mode == MAX_MACHINE_MODE |
1867 | || GET_MODE_SIZE (mode) == 4 | |
1868 | || GET_MODE_SIZE (mode) == 8) | |
1869 | return 1; | |
1870 | ||
65239d20 | 1871 | /* The constant must be loaded using ADDIUPC or DADDIUPC first. */ |
fbb96ac5 | 1872 | return 0; |
b8eb88d0 | 1873 | |
e06e2776 | 1874 | case SYMBOL_FORCE_TO_MEM: |
206c2d7a RS |
1875 | /* LEAs will be converted into constant-pool references by |
1876 | mips_reorg. */ | |
1877 | if (mode == MAX_MACHINE_MODE) | |
1878 | return 1; | |
1879 | ||
65239d20 | 1880 | /* The constant must be loaded and then dereferenced. */ |
e06e2776 RS |
1881 | return 0; |
1882 | ||
08e7ceb3 | 1883 | case SYMBOL_GOT_DISP: |
fbb96ac5 RS |
1884 | /* The constant will have to be loaded from the GOT before it |
1885 | is used in an address. */ | |
1886 | if (mode != MAX_MACHINE_MODE) | |
1887 | return 0; | |
1888 | ||
1889 | /* Fall through. */ | |
1890 | ||
1891 | case SYMBOL_GOT_PAGE_OFST: | |
65239d20 RS |
1892 | /* Unless -funit-at-a-time is in effect, we can't be sure whether the |
1893 | local/global classification is accurate. The worst cases are: | |
2bcb2ab3 | 1894 | |
f6149877 RS |
1895 | (1) For local symbols when generating o32 or o64 code. The assembler |
1896 | will use: | |
108b61d5 | 1897 | |
f6149877 RS |
1898 | lw $at,%got(symbol) |
1899 | nop | |
108b61d5 | 1900 | |
f6149877 | 1901 | ...and the final address will be $at + %lo(symbol). |
108b61d5 | 1902 | |
f6149877 RS |
1903 | (2) For global symbols when -mxgot. The assembler will use: |
1904 | ||
1905 | lui $at,%got_hi(symbol) | |
1906 | (d)addu $at,$at,$gp | |
1907 | ||
1908 | ...and the final address will be $at + %got_lo(symbol). */ | |
1909 | return 3; | |
108b61d5 RS |
1910 | |
1911 | case SYMBOL_GOTOFF_PAGE: | |
08e7ceb3 | 1912 | case SYMBOL_GOTOFF_DISP: |
108b61d5 RS |
1913 | case SYMBOL_GOTOFF_CALL: |
1914 | case SYMBOL_GOTOFF_LOADGP: | |
c93c5160 | 1915 | case SYMBOL_32_HIGH: |
e245bd81 RS |
1916 | case SYMBOL_64_HIGH: |
1917 | case SYMBOL_64_MID: | |
1918 | case SYMBOL_64_LOW: | |
69229b81 DJ |
1919 | case SYMBOL_TLSGD: |
1920 | case SYMBOL_TLSLDM: | |
1921 | case SYMBOL_DTPREL: | |
1922 | case SYMBOL_GOTTPREL: | |
1923 | case SYMBOL_TPREL: | |
fbb96ac5 RS |
1924 | case SYMBOL_HALF: |
1925 | /* A 16-bit constant formed by a single relocation, or a 32-bit | |
1926 | constant formed from a high 16-bit relocation and a low 16-bit | |
65239d20 RS |
1927 | relocation. Use mips_split_p to determine which. 32-bit |
1928 | constants need an "lui; addiu" sequence for normal mode and | |
1929 | an "li; sll; addiu" sequence for MIPS16 mode. */ | |
c93c5160 | 1930 | return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2; |
69229b81 DJ |
1931 | |
1932 | case SYMBOL_TLS: | |
1933 | /* We don't treat a bare TLS symbol as a constant. */ | |
1934 | return 0; | |
2bcb2ab3 | 1935 | } |
7ad769fe | 1936 | gcc_unreachable (); |
cafe096b | 1937 | } |
2bcb2ab3 | 1938 | |
fbb96ac5 RS |
1939 | /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed |
1940 | to load symbols of type TYPE into a register. Return 0 if the given | |
1941 | type of symbol cannot be used as an immediate operand. | |
1942 | ||
1943 | Otherwise, return the number of instructions needed to load or store | |
1944 | values of mode MODE to or from addresses of type TYPE. Return 0 if | |
1945 | the given type of symbol is not valid in addresses. | |
1946 | ||
1947 | In both cases, treat extended MIPS16 instructions as two instructions. */ | |
1948 | ||
1949 | static int | |
1950 | mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode) | |
1951 | { | |
1952 | return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1); | |
1953 | } | |
65239d20 RS |
1954 | \f |
1955 | /* A for_each_rtx callback. Stop the search if *X references a | |
1956 | thread-local symbol. */ | |
96a30b18 | 1957 | |
ab77a036 RS |
1958 | static int |
1959 | mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED) | |
96a30b18 | 1960 | { |
65239d20 | 1961 | return mips_tls_symbol_p (*x); |
96a30b18 | 1962 | } |
2bcb2ab3 | 1963 | |
65239d20 | 1964 | /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ |
cee98a59 | 1965 | |
cafe096b | 1966 | static bool |
ab77a036 | 1967 | mips_cannot_force_const_mem (rtx x) |
cee98a59 | 1968 | { |
08d0963a | 1969 | enum mips_symbol_type type; |
ab77a036 RS |
1970 | rtx base, offset; |
1971 | ||
08d0963a RS |
1972 | /* There is no assembler syntax for expressing an address-sized |
1973 | high part. */ | |
1974 | if (GET_CODE (x) == HIGH) | |
1975 | return true; | |
1976 | ||
1977 | /* As an optimization, reject constants that mips_legitimize_move | |
1978 | can expand inline. | |
1979 | ||
1980 | Suppose we have a multi-instruction sequence that loads constant C | |
1981 | into register R. If R does not get allocated a hard register, and | |
1982 | R is used in an operand that allows both registers and memory | |
1983 | references, reload will consider forcing C into memory and using | |
1984 | one of the instruction's memory alternatives. Returning false | |
1985 | here will force it to use an input reload instead. */ | |
47ac44d6 | 1986 | if (CONST_INT_P (x) && LEGITIMATE_CONSTANT_P (x)) |
08d0963a | 1987 | return true; |
ab77a036 | 1988 | |
08d0963a RS |
1989 | split_const (x, &base, &offset); |
1990 | if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type) | |
1991 | && type != SYMBOL_FORCE_TO_MEM) | |
1992 | { | |
1993 | /* The same optimization as for CONST_INT. */ | |
1994 | if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0) | |
ab77a036 RS |
1995 | return true; |
1996 | ||
08d0963a RS |
1997 | /* If MIPS16 constant pools live in the text section, they should |
1998 | not refer to anything that might need run-time relocation. */ | |
1999 | if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type)) | |
ab77a036 | 2000 | return true; |
cafe096b | 2001 | } |
ab77a036 | 2002 | |
65239d20 RS |
2003 | /* TLS symbols must be computed by mips_legitimize_move. */ |
2004 | if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL)) | |
ab77a036 RS |
2005 | return true; |
2006 | ||
cafe096b EC |
2007 | return false; |
2008 | } | |
cee98a59 | 2009 | |
ab77a036 RS |
2010 | /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for |
2011 | constants when we're using a per-function constant pool. */ | |
cee98a59 | 2012 | |
ab77a036 RS |
2013 | static bool |
2014 | mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, | |
2015 | const_rtx x ATTRIBUTE_UNUSED) | |
2016 | { | |
2017 | return !TARGET_MIPS16_PCREL_LOADS; | |
2018 | } | |
2019 | \f | |
65239d20 RS |
2020 | /* Return true if register REGNO is a valid base register for mode MODE. |
2021 | STRICT_P is true if REG_OK_STRICT is in effect. */ | |
cee98a59 | 2022 | |
cafe096b | 2023 | int |
65239d20 RS |
2024 | mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode, |
2025 | bool strict_p) | |
cafe096b | 2026 | { |
ab77a036 RS |
2027 | if (!HARD_REGISTER_NUM_P (regno)) |
2028 | { | |
65239d20 | 2029 | if (!strict_p) |
ab77a036 RS |
2030 | return true; |
2031 | regno = reg_renumber[regno]; | |
2032 | } | |
cafe096b | 2033 | |
ab77a036 RS |
2034 | /* These fake registers will be eliminated to either the stack or |
2035 | hard frame pointer, both of which are usually valid base registers. | |
2036 | Reload deals with the cases where the eliminated form isn't valid. */ | |
2037 | if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) | |
2038 | return true; | |
2039 | ||
65239d20 | 2040 | /* In MIPS16 mode, the stack pointer can only address word and doubleword |
ab77a036 RS |
2041 | values, nothing smaller. There are two problems here: |
2042 | ||
2043 | (a) Instantiating virtual registers can introduce new uses of the | |
2044 | stack pointer. If these virtual registers are valid addresses, | |
2045 | the stack pointer should be too. | |
2046 | ||
2047 | (b) Most uses of the stack pointer are not made explicit until | |
2048 | FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated. | |
2049 | We don't know until that stage whether we'll be eliminating to the | |
2050 | stack pointer (which needs the restriction) or the hard frame | |
2051 | pointer (which doesn't). | |
2052 | ||
2053 | All in all, it seems more consistent to only enforce this restriction | |
2054 | during and after reload. */ | |
2055 | if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM) | |
65239d20 | 2056 | return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8; |
ab77a036 RS |
2057 | |
2058 | return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno); | |
2059 | } | |
2060 | ||
65239d20 RS |
2061 | /* Return true if X is a valid base register for mode MODE. |
2062 | STRICT_P is true if REG_OK_STRICT is in effect. */ | |
ab77a036 RS |
2063 | |
2064 | static bool | |
65239d20 | 2065 | mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p) |
ab77a036 | 2066 | { |
65239d20 | 2067 | if (!strict_p && GET_CODE (x) == SUBREG) |
ab77a036 RS |
2068 | x = SUBREG_REG (x); |
2069 | ||
2070 | return (REG_P (x) | |
65239d20 | 2071 | && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p)); |
ab77a036 RS |
2072 | } |
2073 | ||
fa21a761 RS |
2074 | /* Return true if, for every base register BASE_REG, (plus BASE_REG X) |
2075 | can address a value of mode MODE. */ | |
2076 | ||
2077 | static bool | |
2078 | mips_valid_offset_p (rtx x, enum machine_mode mode) | |
2079 | { | |
2080 | /* Check that X is a signed 16-bit number. */ | |
2081 | if (!const_arith_operand (x, Pmode)) | |
2082 | return false; | |
2083 | ||
2084 | /* We may need to split multiword moves, so make sure that every word | |
2085 | is accessible. */ | |
2086 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
2087 | && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD)) | |
2088 | return false; | |
2089 | ||
2090 | return true; | |
2091 | } | |
2092 | ||
2093 | /* Return true if a LO_SUM can address a value of mode MODE when the | |
2094 | LO_SUM symbol has type SYMBOL_TYPE. */ | |
2095 | ||
2096 | static bool | |
2097 | mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode) | |
2098 | { | |
2099 | /* Check that symbols of type SYMBOL_TYPE can be used to access values | |
2100 | of mode MODE. */ | |
2101 | if (mips_symbol_insns (symbol_type, mode) == 0) | |
2102 | return false; | |
2103 | ||
2104 | /* Check that there is a known low-part relocation. */ | |
2105 | if (mips_lo_relocs[symbol_type] == NULL) | |
2106 | return false; | |
2107 | ||
2108 | /* We may need to split multiword moves, so make sure that each word | |
2109 | can be accessed without inducing a carry. This is mainly needed | |
2110 | for o64, which has historically only guaranteed 64-bit alignment | |
2111 | for 128-bit types. */ | |
2112 | if (GET_MODE_SIZE (mode) > UNITS_PER_WORD | |
2113 | && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode)) | |
2114 | return false; | |
2115 | ||
2116 | return true; | |
2117 | } | |
2118 | ||
ab77a036 | 2119 | /* Return true if X is a valid address for machine mode MODE. If it is, |
65239d20 RS |
2120 | fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in |
2121 | effect. */ | |
ab77a036 RS |
2122 | |
2123 | static bool | |
2124 | mips_classify_address (struct mips_address_info *info, rtx x, | |
65239d20 | 2125 | enum machine_mode mode, bool strict_p) |
ab77a036 RS |
2126 | { |
2127 | switch (GET_CODE (x)) | |
2128 | { | |
2129 | case REG: | |
2130 | case SUBREG: | |
2131 | info->type = ADDRESS_REG; | |
2132 | info->reg = x; | |
2133 | info->offset = const0_rtx; | |
65239d20 | 2134 | return mips_valid_base_register_p (info->reg, mode, strict_p); |
ab77a036 RS |
2135 | |
2136 | case PLUS: | |
2137 | info->type = ADDRESS_REG; | |
2138 | info->reg = XEXP (x, 0); | |
2139 | info->offset = XEXP (x, 1); | |
65239d20 | 2140 | return (mips_valid_base_register_p (info->reg, mode, strict_p) |
fa21a761 | 2141 | && mips_valid_offset_p (info->offset, mode)); |
ab77a036 RS |
2142 | |
2143 | case LO_SUM: | |
2144 | info->type = ADDRESS_LO_SUM; | |
2145 | info->reg = XEXP (x, 0); | |
2146 | info->offset = XEXP (x, 1); | |
2147 | /* We have to trust the creator of the LO_SUM to do something vaguely | |
2148 | sane. Target-independent code that creates a LO_SUM should also | |
2149 | create and verify the matching HIGH. Target-independent code that | |
2150 | adds an offset to a LO_SUM must prove that the offset will not | |
2151 | induce a carry. Failure to do either of these things would be | |
2152 | a bug, and we are not required to check for it here. The MIPS | |
2153 | backend itself should only create LO_SUMs for valid symbolic | |
2154 | constants, with the high part being either a HIGH or a copy | |
2155 | of _gp. */ | |
2156 | info->symbol_type | |
2157 | = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM); | |
65239d20 | 2158 | return (mips_valid_base_register_p (info->reg, mode, strict_p) |
fa21a761 | 2159 | && mips_valid_lo_sum_p (info->symbol_type, mode)); |
ab77a036 RS |
2160 | |
2161 | case CONST_INT: | |
2162 | /* Small-integer addresses don't occur very often, but they | |
2163 | are legitimate if $0 is a valid base register. */ | |
2164 | info->type = ADDRESS_CONST_INT; | |
2165 | return !TARGET_MIPS16 && SMALL_INT (x); | |
2166 | ||
2167 | case CONST: | |
2168 | case LABEL_REF: | |
2169 | case SYMBOL_REF: | |
2170 | info->type = ADDRESS_SYMBOLIC; | |
2171 | return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM, | |
2172 | &info->symbol_type) | |
2173 | && mips_symbol_insns (info->symbol_type, mode) > 0 | |
2174 | && !mips_split_p[info->symbol_type]); | |
2175 | ||
2176 | default: | |
2177 | return false; | |
2178 | } | |
2179 | } | |
2180 | ||
c6c3dba9 | 2181 | /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ |
ab77a036 | 2182 | |
c6c3dba9 | 2183 | static bool |
65239d20 | 2184 | mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p) |
ab77a036 RS |
2185 | { |
2186 | struct mips_address_info addr; | |
2187 | ||
65239d20 | 2188 | return mips_classify_address (&addr, x, mode, strict_p); |
ab77a036 RS |
2189 | } |
2190 | ||
2191 | /* Return true if X is a legitimate $sp-based address for mode MDOE. */ | |
2192 | ||
2193 | bool | |
2194 | mips_stack_address_p (rtx x, enum machine_mode mode) | |
2195 | { | |
2196 | struct mips_address_info addr; | |
2197 | ||
2198 | return (mips_classify_address (&addr, x, mode, false) | |
2199 | && addr.type == ADDRESS_REG | |
2200 | && addr.reg == stack_pointer_rtx); | |
2201 | } | |
2202 | ||
65239d20 RS |
2203 | /* Return true if ADDR matches the pattern for the LWXS load scaled indexed |
2204 | address instruction. Note that such addresses are not considered | |
331d9186 | 2205 | legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use |
65239d20 | 2206 | is so restricted. */ |
ab77a036 RS |
2207 | |
2208 | static bool | |
2209 | mips_lwxs_address_p (rtx addr) | |
2210 | { | |
2211 | if (ISA_HAS_LWXS | |
2212 | && GET_CODE (addr) == PLUS | |
2213 | && REG_P (XEXP (addr, 1))) | |
2214 | { | |
2215 | rtx offset = XEXP (addr, 0); | |
2216 | if (GET_CODE (offset) == MULT | |
2217 | && REG_P (XEXP (offset, 0)) | |
47ac44d6 | 2218 | && CONST_INT_P (XEXP (offset, 1)) |
ab77a036 RS |
2219 | && INTVAL (XEXP (offset, 1)) == 4) |
2220 | return true; | |
2221 | } | |
2222 | return false; | |
2223 | } | |
65239d20 RS |
2224 | \f |
2225 | /* Return true if a value at OFFSET bytes from base register BASE can be | |
2226 | accessed using an unextended MIPS16 instruction. MODE is the mode of | |
2227 | the value. | |
ab77a036 RS |
2228 | |
2229 | Usually the offset in an unextended instruction is a 5-bit field. | |
65239d20 RS |
2230 | The offset is unsigned and shifted left once for LH and SH, twice |
2231 | for LW and SW, and so on. An exception is LWSP and SWSP, which have | |
2232 | an 8-bit immediate field that's shifted left twice. */ | |
ab77a036 RS |
2233 | |
2234 | static bool | |
65239d20 RS |
2235 | mips16_unextended_reference_p (enum machine_mode mode, rtx base, |
2236 | unsigned HOST_WIDE_INT offset) | |
ab77a036 | 2237 | { |
65239d20 | 2238 | if (offset % GET_MODE_SIZE (mode) == 0) |
ab77a036 RS |
2239 | { |
2240 | if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx) | |
65239d20 RS |
2241 | return offset < 256U * GET_MODE_SIZE (mode); |
2242 | return offset < 32U * GET_MODE_SIZE (mode); | |
ab77a036 RS |
2243 | } |
2244 | return false; | |
2245 | } | |
2246 | ||
ab77a036 | 2247 | /* Return the number of instructions needed to load or store a value |
65239d20 RS |
2248 | of mode MODE at address X. Return 0 if X isn't valid for MODE. |
2249 | Assume that multiword moves may need to be split into word moves | |
2250 | if MIGHT_SPLIT_P, otherwise assume that a single load or store is | |
2251 | enough. | |
ab77a036 | 2252 | |
65239d20 | 2253 | For MIPS16 code, count extended instructions as two instructions. */ |
ab77a036 RS |
2254 | |
2255 | int | |
2256 | mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p) | |
2257 | { | |
2258 | struct mips_address_info addr; | |
2259 | int factor; | |
2260 | ||
2261 | /* BLKmode is used for single unaligned loads and stores and should | |
2262 | not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty | |
2263 | meaningless, so we have to single it out as a special case one way | |
2264 | or the other.) */ | |
5955b0a3 | 2265 | if (mode != BLKmode && might_split_p) |
656f37ee | 2266 | factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; |
5955b0a3 RS |
2267 | else |
2268 | factor = 1; | |
656f37ee | 2269 | |
108b61d5 RS |
2270 | if (mips_classify_address (&addr, x, mode, false)) |
2271 | switch (addr.type) | |
2272 | { | |
2273 | case ADDRESS_REG: | |
2274 | if (TARGET_MIPS16 | |
65239d20 RS |
2275 | && !mips16_unextended_reference_p (mode, addr.reg, |
2276 | UINTVAL (addr.offset))) | |
108b61d5 RS |
2277 | return factor * 2; |
2278 | return factor; | |
cafe096b | 2279 | |
108b61d5 | 2280 | case ADDRESS_LO_SUM: |
65239d20 | 2281 | return TARGET_MIPS16 ? factor * 2 : factor; |
4fef83a7 | 2282 | |
108b61d5 RS |
2283 | case ADDRESS_CONST_INT: |
2284 | return factor; | |
cafe096b | 2285 | |
108b61d5 | 2286 | case ADDRESS_SYMBOLIC: |
fbb96ac5 | 2287 | return factor * mips_symbol_insns (addr.symbol_type, mode); |
108b61d5 RS |
2288 | } |
2289 | return 0; | |
cafe096b EC |
2290 | } |
2291 | ||
65239d20 RS |
2292 | /* Return the number of instructions needed to load constant X. |
2293 | Return 0 if X isn't a valid constant. */ | |
cafe096b EC |
2294 | |
2295 | int | |
b4966b1b | 2296 | mips_const_insns (rtx x) |
cafe096b | 2297 | { |
b259a9a6 | 2298 | struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; |
108b61d5 | 2299 | enum mips_symbol_type symbol_type; |
7ffb5e78 | 2300 | rtx offset; |
cafe096b EC |
2301 | |
2302 | switch (GET_CODE (x)) | |
2303 | { | |
cafe096b | 2304 | case HIGH: |
c93c5160 RS |
2305 | if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA, |
2306 | &symbol_type) | |
108b61d5 RS |
2307 | || !mips_split_p[symbol_type]) |
2308 | return 0; | |
2309 | ||
65239d20 RS |
2310 | /* This is simply an LUI for normal mode. It is an extended |
2311 | LI followed by an extended SLL for MIPS16. */ | |
c93c5160 | 2312 | return TARGET_MIPS16 ? 4 : 1; |
cee98a59 MM |
2313 | |
2314 | case CONST_INT: | |
2bcb2ab3 | 2315 | if (TARGET_MIPS16) |
cafe096b EC |
2316 | /* Unsigned 8-bit constants can be loaded using an unextended |
2317 | LI instruction. Unsigned 16-bit constants can be loaded | |
2318 | using an extended LI. Negative constants must be loaded | |
2319 | using LI and then negated. */ | |
65239d20 | 2320 | return (IN_RANGE (INTVAL (x), 0, 255) ? 1 |
cafe096b | 2321 | : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2 |
65239d20 | 2322 | : IN_RANGE (-INTVAL (x), 0, 255) ? 2 |
cafe096b EC |
2323 | : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3 |
2324 | : 0); | |
2325 | ||
b259a9a6 | 2326 | return mips_build_integer (codes, INTVAL (x)); |
cee98a59 | 2327 | |
cafe096b | 2328 | case CONST_DOUBLE: |
06a4ab70 | 2329 | case CONST_VECTOR: |
65239d20 RS |
2330 | /* Allow zeros for normal mode, where we can use $0. */ |
2331 | return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; | |
cee98a59 | 2332 | |
108b61d5 RS |
2333 | case CONST: |
2334 | if (CONST_GP_P (x)) | |
2335 | return 1; | |
2336 | ||
2337 | /* See if we can refer to X directly. */ | |
280fcbfa | 2338 | if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type)) |
fbb96ac5 | 2339 | return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE); |
108b61d5 RS |
2340 | |
2341 | /* Otherwise try splitting the constant into a base and offset. | |
08d0963a RS |
2342 | If the offset is a 16-bit value, we can load the base address |
2343 | into a register and then use (D)ADDIU to add in the offset. | |
2344 | If the offset is larger, we can load the base and offset | |
2345 | into separate registers and add them together with (D)ADDU. | |
2346 | However, the latter is only possible before reload; during | |
2347 | and after reload, we must have the option of forcing the | |
2348 | constant into the pool instead. */ | |
7ffb5e78 | 2349 | split_const (x, &x, &offset); |
108b61d5 | 2350 | if (offset != 0) |
cafe096b | 2351 | { |
108b61d5 RS |
2352 | int n = mips_const_insns (x); |
2353 | if (n != 0) | |
2354 | { | |
7ffb5e78 | 2355 | if (SMALL_INT (offset)) |
108b61d5 | 2356 | return n + 1; |
08d0963a | 2357 | else if (!targetm.cannot_force_const_mem (x)) |
7ffb5e78 | 2358 | return n + 1 + mips_build_integer (codes, INTVAL (offset)); |
108b61d5 RS |
2359 | } |
2360 | } | |
2361 | return 0; | |
cee98a59 | 2362 | |
108b61d5 RS |
2363 | case SYMBOL_REF: |
2364 | case LABEL_REF: | |
fbb96ac5 RS |
2365 | return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA), |
2366 | MAX_MACHINE_MODE); | |
cee98a59 | 2367 | |
108b61d5 RS |
2368 | default: |
2369 | return 0; | |
cafe096b EC |
2370 | } |
2371 | } | |
cee98a59 | 2372 | |
c5cb5d18 RS |
2373 | /* X is a doubleword constant that can be handled by splitting it into |
2374 | two words and loading each word separately. Return the number of | |
2375 | instructions required to do this. */ | |
2376 | ||
2377 | int | |
2378 | mips_split_const_insns (rtx x) | |
2379 | { | |
2380 | unsigned int low, high; | |
2381 | ||
2382 | low = mips_const_insns (mips_subword (x, false)); | |
2383 | high = mips_const_insns (mips_subword (x, true)); | |
2384 | gcc_assert (low > 0 && high > 0); | |
2385 | return low + high; | |
2386 | } | |
2387 | ||
5955b0a3 RS |
2388 | /* Return the number of instructions needed to implement INSN, |
2389 | given that it loads from or stores to MEM. Count extended | |
65239d20 | 2390 | MIPS16 instructions as two instructions. */ |
f5963e61 | 2391 | |
cafe096b | 2392 | int |
5955b0a3 | 2393 | mips_load_store_insns (rtx mem, rtx insn) |
cafe096b | 2394 | { |
5955b0a3 RS |
2395 | enum machine_mode mode; |
2396 | bool might_split_p; | |
2397 | rtx set; | |
2398 | ||
2399 | gcc_assert (MEM_P (mem)); | |
2400 | mode = GET_MODE (mem); | |
2401 | ||
2402 | /* Try to prove that INSN does not need to be split. */ | |
2403 | might_split_p = true; | |
2404 | if (GET_MODE_BITSIZE (mode) == 64) | |
2405 | { | |
2406 | set = single_set (insn); | |
2407 | if (set && !mips_split_64bit_move_p (SET_DEST (set), SET_SRC (set))) | |
2408 | might_split_p = false; | |
2409 | } | |
2410 | ||
2411 | return mips_address_insns (XEXP (mem, 0), mode, might_split_p); | |
cafe096b | 2412 | } |
2bcb2ab3 | 2413 | |
46490403 MR |
2414 | /* Return the number of instructions needed for an integer division. */ |
2415 | ||
2416 | int | |
2417 | mips_idiv_insns (void) | |
2418 | { | |
2419 | int count; | |
2420 | ||
2421 | count = 1; | |
2422 | if (TARGET_CHECK_ZERO_DIV) | |
9f0df97a DD |
2423 | { |
2424 | if (GENERATE_DIVIDE_TRAPS) | |
2425 | count++; | |
2426 | else | |
2427 | count += 2; | |
2428 | } | |
66083422 | 2429 | |
6ba7b547 | 2430 | if (TARGET_FIX_R4000 || TARGET_FIX_R4400) |
46490403 MR |
2431 | count++; |
2432 | return count; | |
2433 | } | |
50d32cf6 | 2434 | \f |
51e7252a RS |
2435 | /* Emit a move from SRC to DEST. Assume that the move expanders can |
2436 | handle all moves if !can_create_pseudo_p (). The distinction is | |
2437 | important because, unlike emit_move_insn, the move expanders know | |
2438 | how to force Pmode objects into the constant pool even when the | |
2439 | constant pool address is not itself legitimate. */ | |
2440 | ||
2441 | rtx | |
2442 | mips_emit_move (rtx dest, rtx src) | |
2443 | { | |
2444 | return (can_create_pseudo_p () | |
2445 | ? emit_move_insn (dest, src) | |
2446 | : emit_move_insn_1 (dest, src)); | |
2447 | } | |
108b61d5 | 2448 | |
d48a3196 CF |
2449 | /* Emit an instruction of the form (set TARGET (CODE OP0)). */ |
2450 | ||
2451 | static void | |
2452 | mips_emit_unary (enum rtx_code code, rtx target, rtx op0) | |
2453 | { | |
2454 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
2455 | gen_rtx_fmt_e (code, GET_MODE (op0), op0))); | |
2456 | } | |
2457 | ||
2458 | /* Compute (CODE OP0) and store the result in a new register of mode MODE. | |
2459 | Return that new register. */ | |
2460 | ||
2461 | static rtx | |
2462 | mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0) | |
2463 | { | |
2464 | rtx reg; | |
2465 | ||
2466 | reg = gen_reg_rtx (mode); | |
2467 | mips_emit_unary (code, reg, op0); | |
2468 | return reg; | |
2469 | } | |
2470 | ||
ab77a036 RS |
2471 | /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */ |
2472 | ||
2473 | static void | |
2474 | mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1) | |
2475 | { | |
2476 | emit_insn (gen_rtx_SET (VOIDmode, target, | |
2477 | gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1))); | |
2478 | } | |
2479 | ||
49bce30a RS |
2480 | /* Compute (CODE OP0 OP1) and store the result in a new register |
2481 | of mode MODE. Return that new register. */ | |
2482 | ||
2483 | static rtx | |
2484 | mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1) | |
2485 | { | |
2486 | rtx reg; | |
2487 | ||
2488 | reg = gen_reg_rtx (mode); | |
2489 | mips_emit_binary (code, reg, op0, op1); | |
2490 | return reg; | |
2491 | } | |
2492 | ||
65239d20 | 2493 | /* Copy VALUE to a register and return that register. If new pseudos |
108b61d5 RS |
2494 | are allowed, copy it into a new register, otherwise use DEST. */ |
2495 | ||
2496 | static rtx | |
2497 | mips_force_temporary (rtx dest, rtx value) | |
2498 | { | |
b3a13419 | 2499 | if (can_create_pseudo_p ()) |
108b61d5 RS |
2500 | return force_reg (Pmode, value); |
2501 | else | |
2502 | { | |
65239d20 | 2503 | mips_emit_move (dest, value); |
108b61d5 RS |
2504 | return dest; |
2505 | } | |
cafe096b | 2506 | } |
dbc90b65 RS |
2507 | |
2508 | /* Emit a call sequence with call pattern PATTERN and return the call | |
2509 | instruction itself (which is not necessarily the last instruction | |
08d0963a RS |
2510 | emitted). ORIG_ADDR is the original, unlegitimized address, |
2511 | ADDR is the legitimized form, and LAZY_P is true if the call | |
2512 | address is lazily-bound. */ | |
dbc90b65 RS |
2513 | |
2514 | static rtx | |
08d0963a | 2515 | mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p) |
dbc90b65 | 2516 | { |
08d0963a | 2517 | rtx insn, reg; |
dbc90b65 RS |
2518 | |
2519 | insn = emit_call_insn (pattern); | |
2520 | ||
08d0963a RS |
2521 | if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr)) |
2522 | { | |
2523 | /* MIPS16 JALRs only take MIPS16 registers. If the target | |
2524 | function requires $25 to be valid on entry, we must copy it | |
2525 | there separately. The move instruction can be put in the | |
2526 | call's delay slot. */ | |
2527 | reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
2528 | emit_insn_before (gen_move_insn (reg, addr), insn); | |
2529 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg); | |
2530 | } | |
2531 | ||
dbc90b65 | 2532 | if (lazy_p) |
08d0963a | 2533 | /* Lazy-binding stubs require $gp to be valid on entry. */ |
dbc90b65 RS |
2534 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); |
2535 | ||
2536 | if (TARGET_USE_GOT) | |
2537 | { | |
2538 | /* See the comment above load_call<mode> for details. */ | |
2539 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), | |
2540 | gen_rtx_REG (Pmode, GOT_VERSION_REGNUM)); | |
2541 | emit_insn (gen_update_got_version ()); | |
2542 | } | |
2543 | return insn; | |
2544 | } | |
65239d20 | 2545 | \f |
7462a715 RS |
2546 | /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE, |
2547 | then add CONST_INT OFFSET to the result. */ | |
2548 | ||
2549 | static rtx | |
2550 | mips_unspec_address_offset (rtx base, rtx offset, | |
2551 | enum mips_symbol_type symbol_type) | |
2552 | { | |
2553 | base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), | |
2554 | UNSPEC_ADDRESS_FIRST + symbol_type); | |
2555 | if (offset != const0_rtx) | |
2556 | base = gen_rtx_PLUS (Pmode, base, offset); | |
2557 | return gen_rtx_CONST (Pmode, base); | |
2558 | } | |
2559 | ||
2560 | /* Return an UNSPEC address with underlying address ADDRESS and symbol | |
2561 | type SYMBOL_TYPE. */ | |
2562 | ||
2563 | rtx | |
2564 | mips_unspec_address (rtx address, enum mips_symbol_type symbol_type) | |
2565 | { | |
2566 | rtx base, offset; | |
2567 | ||
2568 | split_const (address, &base, &offset); | |
2569 | return mips_unspec_address_offset (base, offset, symbol_type); | |
2570 | } | |
2571 | ||
b53da244 AN |
2572 | /* If OP is an UNSPEC address, return the address to which it refers, |
2573 | otherwise return OP itself. */ | |
2574 | ||
2575 | static rtx | |
2576 | mips_strip_unspec_address (rtx op) | |
2577 | { | |
2578 | rtx base, offset; | |
2579 | ||
2580 | split_const (op, &base, &offset); | |
2581 | if (UNSPEC_ADDRESS_P (base)) | |
2582 | op = plus_constant (UNSPEC_ADDRESS (base), INTVAL (offset)); | |
2583 | return op; | |
2584 | } | |
2585 | ||
7462a715 RS |
2586 | /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the |
2587 | high part to BASE and return the result. Just return BASE otherwise. | |
2588 | TEMP is as for mips_force_temporary. | |
2589 | ||
2590 | The returned expression can be used as the first operand to a LO_SUM. */ | |
2591 | ||
2592 | static rtx | |
2593 | mips_unspec_offset_high (rtx temp, rtx base, rtx addr, | |
2594 | enum mips_symbol_type symbol_type) | |
2595 | { | |
2596 | if (mips_split_p[symbol_type]) | |
2597 | { | |
2598 | addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type)); | |
2599 | addr = mips_force_temporary (temp, addr); | |
2600 | base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base)); | |
2601 | } | |
2602 | return base; | |
2603 | } | |
2604 | \f | |
5ca3d30c RS |
2605 | /* Return an instruction that copies $gp into register REG. We want |
2606 | GCC to treat the register's value as constant, so that its value | |
2607 | can be rematerialized on demand. */ | |
2608 | ||
2609 | static rtx | |
2610 | gen_load_const_gp (rtx reg) | |
2611 | { | |
2612 | return (Pmode == SImode | |
2613 | ? gen_load_const_gp_si (reg) | |
2614 | : gen_load_const_gp_di (reg)); | |
2615 | } | |
2616 | ||
65239d20 RS |
2617 | /* Return a pseudo register that contains the value of $gp throughout |
2618 | the current function. Such registers are needed by MIPS16 functions, | |
2619 | for which $gp itself is not a valid base register or addition operand. */ | |
ab77a036 RS |
2620 | |
2621 | static rtx | |
2622 | mips16_gp_pseudo_reg (void) | |
2623 | { | |
2624 | if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX) | |
2625 | cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode); | |
2626 | ||
65239d20 RS |
2627 | /* Don't emit an instruction to initialize the pseudo register if |
2628 | we are being called from the tree optimizers' cost-calculation | |
2629 | routines. */ | |
ab77a036 RS |
2630 | if (!cfun->machine->initialized_mips16_gp_pseudo_p |
2631 | && (current_ir_type () != IR_GIMPLE || currently_expanding_to_rtl)) | |
2632 | { | |
08d0963a RS |
2633 | rtx insn, scan; |
2634 | ||
2635 | push_topmost_sequence (); | |
2636 | ||
2637 | scan = get_insns (); | |
2638 | while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan))) | |
2639 | scan = NEXT_INSN (scan); | |
ab77a036 | 2640 | |
ab77a036 | 2641 | insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx); |
08d0963a | 2642 | emit_insn_after (insn, scan); |
ab77a036 | 2643 | |
ab77a036 RS |
2644 | pop_topmost_sequence (); |
2645 | ||
2646 | cfun->machine->initialized_mips16_gp_pseudo_p = true; | |
2647 | } | |
2648 | ||
2649 | return cfun->machine->mips16_gp_pseudo_rtx; | |
2650 | } | |
cafe096b | 2651 | |
08d0963a RS |
2652 | /* Return a base register that holds pic_offset_table_rtx. |
2653 | TEMP, if nonnull, is a scratch Pmode base register. */ | |
2654 | ||
2655 | rtx | |
2656 | mips_pic_base_register (rtx temp) | |
2657 | { | |
2658 | if (!TARGET_MIPS16) | |
2659 | return pic_offset_table_rtx; | |
2660 | ||
2661 | if (can_create_pseudo_p ()) | |
2662 | return mips16_gp_pseudo_reg (); | |
2663 | ||
2664 | if (TARGET_USE_GOT) | |
2665 | /* The first post-reload split exposes all references to $gp | |
2666 | (both uses and definitions). All references must remain | |
2667 | explicit after that point. | |
2668 | ||
2669 | It is safe to introduce uses of $gp at any time, so for | |
2670 | simplicity, we do that before the split too. */ | |
2671 | mips_emit_move (temp, pic_offset_table_rtx); | |
2672 | else | |
2673 | emit_insn (gen_load_const_gp (temp)); | |
2674 | return temp; | |
2675 | } | |
2676 | ||
b53da244 AN |
2677 | /* Return the RHS of a load_call<mode> insn. */ |
2678 | ||
2679 | static rtx | |
2680 | mips_unspec_call (rtx reg, rtx symbol) | |
2681 | { | |
2682 | rtvec vec; | |
2683 | ||
2684 | vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM)); | |
2685 | return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL); | |
2686 | } | |
2687 | ||
2688 | /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol | |
2689 | reference. Return NULL_RTX otherwise. */ | |
2690 | ||
2691 | static rtx | |
2692 | mips_strip_unspec_call (rtx src) | |
2693 | { | |
2694 | if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL) | |
2695 | return mips_strip_unspec_address (XVECEXP (src, 0, 1)); | |
2696 | return NULL_RTX; | |
2697 | } | |
2698 | ||
08d0963a RS |
2699 | /* Create and return a GOT reference of type TYPE for address ADDR. |
2700 | TEMP, if nonnull, is a scratch Pmode base register. */ | |
2701 | ||
2702 | rtx | |
2703 | mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type) | |
2704 | { | |
2705 | rtx base, high, lo_sum_symbol; | |
2706 | ||
2707 | base = mips_pic_base_register (temp); | |
2708 | ||
2709 | /* If we used the temporary register to load $gp, we can't use | |
2710 | it for the high part as well. */ | |
2711 | if (temp != NULL && reg_overlap_mentioned_p (base, temp)) | |
2712 | temp = NULL; | |
2713 | ||
2714 | high = mips_unspec_offset_high (temp, base, addr, type); | |
2715 | lo_sum_symbol = mips_unspec_address (addr, type); | |
2716 | ||
2717 | if (type == SYMBOL_GOTOFF_CALL) | |
b53da244 | 2718 | return mips_unspec_call (high, lo_sum_symbol); |
08d0963a RS |
2719 | else |
2720 | return (Pmode == SImode | |
2721 | ? gen_unspec_gotsi (high, lo_sum_symbol) | |
2722 | : gen_unspec_gotdi (high, lo_sum_symbol)); | |
2723 | } | |
2724 | ||
390ea488 RS |
2725 | /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise |
2726 | it appears in a MEM of that mode. Return true if ADDR is a legitimate | |
08d0963a RS |
2727 | constant in that context and can be split into high and low parts. |
2728 | If so, and if LOW_OUT is nonnull, emit the high part and store the | |
2729 | low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise. | |
cafe096b | 2730 | |
390ea488 | 2731 | TEMP is as for mips_force_temporary and is used to load the high |
08d0963a RS |
2732 | part into a register. |
2733 | ||
2734 | When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be | |
2735 | a legitimize SET_SRC for an .md pattern, otherwise the low part | |
2736 | is guaranteed to be a legitimate address for mode MODE. */ | |
390ea488 RS |
2737 | |
2738 | bool | |
08d0963a | 2739 | mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out) |
cafe096b | 2740 | { |
390ea488 RS |
2741 | enum mips_symbol_context context; |
2742 | enum mips_symbol_type symbol_type; | |
108b61d5 | 2743 | rtx high; |
cafe096b | 2744 | |
390ea488 RS |
2745 | context = (mode == MAX_MACHINE_MODE |
2746 | ? SYMBOL_CONTEXT_LEA | |
2747 | : SYMBOL_CONTEXT_MEM); | |
08d0963a | 2748 | if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA) |
1732457d | 2749 | { |
08d0963a RS |
2750 | addr = XEXP (addr, 0); |
2751 | if (mips_symbolic_constant_p (addr, context, &symbol_type) | |
2752 | && mips_symbol_insns (symbol_type, mode) > 0 | |
2753 | && mips_split_hi_p[symbol_type]) | |
390ea488 | 2754 | { |
08d0963a RS |
2755 | if (low_out) |
2756 | switch (symbol_type) | |
2757 | { | |
2758 | case SYMBOL_GOT_PAGE_OFST: | |
2759 | /* The high part of a page/ofst pair is loaded from the GOT. */ | |
2760 | *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE); | |
2761 | break; | |
2762 | ||
2763 | default: | |
2764 | gcc_unreachable (); | |
2765 | } | |
2766 | return true; | |
390ea488 | 2767 | } |
08d0963a RS |
2768 | } |
2769 | else | |
2770 | { | |
2771 | if (mips_symbolic_constant_p (addr, context, &symbol_type) | |
2772 | && mips_symbol_insns (symbol_type, mode) > 0 | |
2773 | && mips_split_p[symbol_type]) | |
390ea488 | 2774 | { |
08d0963a RS |
2775 | if (low_out) |
2776 | switch (symbol_type) | |
2777 | { | |
2778 | case SYMBOL_GOT_DISP: | |
2779 | /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */ | |
2780 | *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP); | |
2781 | break; | |
2782 | ||
2783 | case SYMBOL_GP_RELATIVE: | |
2784 | high = mips_pic_base_register (temp); | |
2785 | *low_out = gen_rtx_LO_SUM (Pmode, high, addr); | |
2786 | break; | |
2787 | ||
2788 | default: | |
2789 | high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); | |
2790 | high = mips_force_temporary (temp, high); | |
2791 | *low_out = gen_rtx_LO_SUM (Pmode, high, addr); | |
2792 | break; | |
2793 | } | |
2794 | return true; | |
390ea488 | 2795 | } |
1732457d | 2796 | } |
08d0963a | 2797 | return false; |
cafe096b EC |
2798 | } |
2799 | ||
b73ce23b RS |
2800 | /* Return a legitimate address for REG + OFFSET. TEMP is as for |
2801 | mips_force_temporary; it is only needed when OFFSET is not a | |
2802 | SMALL_OPERAND. */ | |
cafe096b | 2803 | |
108b61d5 | 2804 | static rtx |
b73ce23b | 2805 | mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) |
cafe096b | 2806 | { |
108b61d5 | 2807 | if (!SMALL_OPERAND (offset)) |
b73ce23b RS |
2808 | { |
2809 | rtx high; | |
65239d20 | 2810 | |
b73ce23b RS |
2811 | if (TARGET_MIPS16) |
2812 | { | |
2813 | /* Load the full offset into a register so that we can use | |
2814 | an unextended instruction for the address itself. */ | |
2815 | high = GEN_INT (offset); | |
2816 | offset = 0; | |
2817 | } | |
2818 | else | |
2819 | { | |
6d8f135b JW |
2820 | /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. |
2821 | The addition inside the macro CONST_HIGH_PART may cause an | |
2822 | overflow, so we need to force a sign-extension check. */ | |
2823 | high = gen_int_mode (CONST_HIGH_PART (offset), Pmode); | |
b73ce23b RS |
2824 | offset = CONST_LOW_PART (offset); |
2825 | } | |
2826 | high = mips_force_temporary (temp, high); | |
2827 | reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg)); | |
2828 | } | |
2829 | return plus_constant (reg, offset); | |
cafe096b | 2830 | } |
65239d20 RS |
2831 | \f |
2832 | /* The __tls_get_attr symbol. */ | |
69229b81 DJ |
2833 | static GTY(()) rtx mips_tls_symbol; |
2834 | ||
65239d20 RS |
2835 | /* Return an instruction sequence that calls __tls_get_addr. SYM is |
2836 | the TLS symbol we are referencing and TYPE is the symbol type to use | |
2837 | (either global dynamic or local dynamic). V0 is an RTX for the | |
2838 | return value location. */ | |
2839 | ||
69229b81 DJ |
2840 | static rtx |
2841 | mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0) | |
2842 | { | |
dbc90b65 | 2843 | rtx insn, loc, a0; |
69229b81 DJ |
2844 | |
2845 | a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST); | |
2846 | ||
2847 | if (!mips_tls_symbol) | |
2848 | mips_tls_symbol = init_one_libfunc ("__tls_get_addr"); | |
2849 | ||
2850 | loc = mips_unspec_address (sym, type); | |
2851 | ||
2852 | start_sequence (); | |
2853 | ||
2854 | emit_insn (gen_rtx_SET (Pmode, a0, | |
2855 | gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc))); | |
08d0963a RS |
2856 | insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol, |
2857 | const0_rtx, NULL_RTX, false); | |
becfd6e5 | 2858 | RTL_CONST_CALL_P (insn) = 1; |
69229b81 DJ |
2859 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); |
2860 | insn = get_insns (); | |
2861 | ||
2862 | end_sequence (); | |
2863 | ||
2864 | return insn; | |
2865 | } | |
2866 | ||
256f27f1 RS |
2867 | /* Return a pseudo register that contains the current thread pointer. */ |
2868 | ||
2869 | static rtx | |
2870 | mips_get_tp (void) | |
2871 | { | |
2872 | rtx tp; | |
2873 | ||
2874 | tp = gen_reg_rtx (Pmode); | |
2875 | if (Pmode == DImode) | |
2876 | emit_insn (gen_tls_get_tp_di (tp)); | |
2877 | else | |
2878 | emit_insn (gen_tls_get_tp_si (tp)); | |
2879 | return tp; | |
2880 | } | |
2881 | ||
65239d20 RS |
2882 | /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return |
2883 | its address. The return value will be both a valid address and a valid | |
2884 | SET_SRC (either a REG or a LO_SUM). */ | |
69229b81 DJ |
2885 | |
2886 | static rtx | |
2887 | mips_legitimize_tls_address (rtx loc) | |
2888 | { | |
256f27f1 | 2889 | rtx dest, insn, v0, tp, tmp1, tmp2, eqv; |
69229b81 DJ |
2890 | enum tls_model model; |
2891 | ||
edede024 SL |
2892 | if (TARGET_MIPS16) |
2893 | { | |
2894 | sorry ("MIPS16 TLS"); | |
2895 | return gen_reg_rtx (Pmode); | |
2896 | } | |
2897 | ||
69229b81 | 2898 | model = SYMBOL_REF_TLS_MODEL (loc); |
4afa41f1 RS |
2899 | /* Only TARGET_ABICALLS code can have more than one module; other |
2900 | code must be be static and should not use a GOT. All TLS models | |
2901 | reduce to local exec in this situation. */ | |
2902 | if (!TARGET_ABICALLS) | |
2903 | model = TLS_MODEL_LOCAL_EXEC; | |
69229b81 DJ |
2904 | |
2905 | switch (model) | |
2906 | { | |
2907 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
65239d20 | 2908 | v0 = gen_rtx_REG (Pmode, GP_RETURN); |
69229b81 DJ |
2909 | insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0); |
2910 | dest = gen_reg_rtx (Pmode); | |
2911 | emit_libcall_block (insn, dest, v0, loc); | |
2912 | break; | |
2913 | ||
2914 | case TLS_MODEL_LOCAL_DYNAMIC: | |
65239d20 | 2915 | v0 = gen_rtx_REG (Pmode, GP_RETURN); |
69229b81 DJ |
2916 | insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0); |
2917 | tmp1 = gen_reg_rtx (Pmode); | |
2918 | ||
2919 | /* Attach a unique REG_EQUIV, to allow the RTL optimizers to | |
2920 | share the LDM result with other LD model accesses. */ | |
2921 | eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), | |
2922 | UNSPEC_TLS_LDM); | |
2923 | emit_libcall_block (insn, tmp1, v0, eqv); | |
2924 | ||
2925 | tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL); | |
2926 | dest = gen_rtx_LO_SUM (Pmode, tmp2, | |
2927 | mips_unspec_address (loc, SYMBOL_DTPREL)); | |
2928 | break; | |
2929 | ||
2930 | case TLS_MODEL_INITIAL_EXEC: | |
256f27f1 | 2931 | tp = mips_get_tp (); |
69229b81 DJ |
2932 | tmp1 = gen_reg_rtx (Pmode); |
2933 | tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL); | |
2934 | if (Pmode == DImode) | |
256f27f1 | 2935 | emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2)); |
69229b81 | 2936 | else |
256f27f1 | 2937 | emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2)); |
69229b81 | 2938 | dest = gen_reg_rtx (Pmode); |
256f27f1 | 2939 | emit_insn (gen_add3_insn (dest, tmp1, tp)); |
69229b81 DJ |
2940 | break; |
2941 | ||
2942 | case TLS_MODEL_LOCAL_EXEC: | |
256f27f1 RS |
2943 | tp = mips_get_tp (); |
2944 | tmp1 = mips_unspec_offset_high (NULL, tp, loc, SYMBOL_TPREL); | |
69229b81 DJ |
2945 | dest = gen_rtx_LO_SUM (Pmode, tmp1, |
2946 | mips_unspec_address (loc, SYMBOL_TPREL)); | |
2947 | break; | |
2948 | ||
2949 | default: | |
107a4b41 | 2950 | gcc_unreachable (); |
69229b81 | 2951 | } |
69229b81 DJ |
2952 | return dest; |
2953 | } | |
65239d20 | 2954 | \f |
fa21a761 RS |
2955 | /* If X is not a valid address for mode MODE, force it into a register. */ |
2956 | ||
2957 | static rtx | |
2958 | mips_force_address (rtx x, enum machine_mode mode) | |
2959 | { | |
2960 | if (!mips_legitimate_address_p (mode, x, false)) | |
2961 | x = force_reg (Pmode, x); | |
2962 | return x; | |
2963 | } | |
2964 | ||
506d7b68 | 2965 | /* This function is used to implement LEGITIMIZE_ADDRESS. If X can |
cafe096b | 2966 | be legitimized in a way that the generic machinery might not expect, |
506d7b68 | 2967 | return a new address, otherwise return NULL. MODE is the mode of |
cafe096b | 2968 | the memory being accessed. */ |
910628b8 | 2969 | |
506d7b68 PB |
2970 | static rtx |
2971 | mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, | |
2972 | enum machine_mode mode) | |
7dac2f89 | 2973 | { |
fa21a761 | 2974 | rtx base, addr; |
65239d20 RS |
2975 | HOST_WIDE_INT offset; |
2976 | ||
506d7b68 PB |
2977 | if (mips_tls_symbol_p (x)) |
2978 | return mips_legitimize_tls_address (x); | |
69229b81 | 2979 | |
108b61d5 | 2980 | /* See if the address can split into a high part and a LO_SUM. */ |
506d7b68 PB |
2981 | if (mips_split_symbol (NULL, x, mode, &addr)) |
2982 | return mips_force_address (addr, mode); | |
910628b8 | 2983 | |
65239d20 | 2984 | /* Handle BASE + OFFSET using mips_add_offset. */ |
506d7b68 | 2985 | mips_split_plus (x, &base, &offset); |
65239d20 | 2986 | if (offset != 0) |
cafe096b | 2987 | { |
65239d20 RS |
2988 | if (!mips_valid_base_register_p (base, mode, false)) |
2989 | base = copy_to_mode_reg (Pmode, base); | |
fa21a761 | 2990 | addr = mips_add_offset (NULL, base, offset); |
506d7b68 | 2991 | return mips_force_address (addr, mode); |
cafe096b | 2992 | } |
506d7b68 PB |
2993 | |
2994 | return x; | |
50c0000c | 2995 | } |
c94c9817 | 2996 | |
65239d20 | 2997 | /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */ |
b259a9a6 | 2998 | |
ea462dd0 | 2999 | void |
65239d20 | 3000 | mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value) |
b259a9a6 RS |
3001 | { |
3002 | struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS]; | |
3003 | enum machine_mode mode; | |
65239d20 | 3004 | unsigned int i, num_ops; |
b259a9a6 RS |
3005 | rtx x; |
3006 | ||
3007 | mode = GET_MODE (dest); | |
65239d20 | 3008 | num_ops = mips_build_integer (codes, value); |
b259a9a6 RS |
3009 | |
3010 | /* Apply each binary operation to X. Invariant: X is a legitimate | |
3011 | source operand for a SET pattern. */ | |
3012 | x = GEN_INT (codes[0].value); | |
65239d20 | 3013 | for (i = 1; i < num_ops; i++) |
b259a9a6 | 3014 | { |
b3a13419 | 3015 | if (!can_create_pseudo_p ()) |
ea462dd0 RS |
3016 | { |
3017 | emit_insn (gen_rtx_SET (VOIDmode, temp, x)); | |
3018 | x = temp; | |
3019 | } | |
b259a9a6 RS |
3020 | else |
3021 | x = force_reg (mode, x); | |
3022 | x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); | |
3023 | } | |
3024 | ||
3025 | emit_insn (gen_rtx_SET (VOIDmode, dest, x)); | |
3026 | } | |
3027 | ||
cafe096b EC |
3028 | /* Subroutine of mips_legitimize_move. Move constant SRC into register |
3029 | DEST given that SRC satisfies immediate_operand but doesn't satisfy | |
3030 | move_operand. */ | |
3031 | ||
3032 | static void | |
b4966b1b | 3033 | mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src) |
c94c9817 | 3034 | { |
7ffb5e78 | 3035 | rtx base, offset; |
cafe096b | 3036 | |
ea462dd0 RS |
3037 | /* Split moves of big integers into smaller pieces. */ |
3038 | if (splittable_const_int_operand (src, mode)) | |
b259a9a6 | 3039 | { |
ea462dd0 | 3040 | mips_move_integer (dest, dest, INTVAL (src)); |
b259a9a6 RS |
3041 | return; |
3042 | } | |
3043 | ||
ea462dd0 | 3044 | /* Split moves of symbolic constants into high/low pairs. */ |
390ea488 | 3045 | if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src)) |
69229b81 | 3046 | { |
390ea488 | 3047 | emit_insn (gen_rtx_SET (VOIDmode, dest, src)); |
69229b81 DJ |
3048 | return; |
3049 | } | |
3050 | ||
65239d20 RS |
3051 | /* Generate the appropriate access sequences for TLS symbols. */ |
3052 | if (mips_tls_symbol_p (src)) | |
cafe096b | 3053 | { |
51e7252a | 3054 | mips_emit_move (dest, mips_legitimize_tls_address (src)); |
cafe096b EC |
3055 | return; |
3056 | } | |
3057 | ||
edede024 SL |
3058 | /* If we have (const (plus symbol offset)), and that expression cannot |
3059 | be forced into memory, load the symbol first and add in the offset. | |
3060 | In non-MIPS16 mode, prefer to do this even if the constant _can_ be | |
3061 | forced into memory, as it usually produces better code. */ | |
7ffb5e78 | 3062 | split_const (src, &base, &offset); |
edede024 SL |
3063 | if (offset != const0_rtx |
3064 | && (targetm.cannot_force_const_mem (src) | |
3065 | || (!TARGET_MIPS16 && can_create_pseudo_p ()))) | |
cafe096b | 3066 | { |
108b61d5 | 3067 | base = mips_force_temporary (dest, base); |
65239d20 | 3068 | mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset))); |
cafe096b EC |
3069 | return; |
3070 | } | |
3071 | ||
3072 | src = force_const_mem (mode, src); | |
3073 | ||
3074 | /* When using explicit relocs, constant pool references are sometimes | |
108b61d5 | 3075 | not legitimate addresses. */ |
390ea488 | 3076 | mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0)); |
51e7252a | 3077 | mips_emit_move (dest, src); |
c94c9817 MM |
3078 | } |
3079 | ||
65239d20 | 3080 | /* If (set DEST SRC) is not a valid move instruction, emit an equivalent |
cafe096b EC |
3081 | sequence that is valid. */ |
3082 | ||
3083 | bool | |
b4966b1b | 3084 | mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src) |
c94c9817 | 3085 | { |
cafe096b | 3086 | if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) |
7dac2f89 | 3087 | { |
51e7252a | 3088 | mips_emit_move (dest, force_reg (mode, src)); |
cafe096b | 3089 | return true; |
7dac2f89 EC |
3090 | } |
3091 | ||
fc31c7ca | 3092 | /* We need to deal with constants that would be legitimate |
65239d20 | 3093 | immediate_operands but aren't legitimate move_operands. */ |
fc31c7ca | 3094 | if (CONSTANT_P (src) && !move_operand (src, mode)) |
cafe096b EC |
3095 | { |
3096 | mips_legitimize_const_move (mode, dest, src); | |
3097 | set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); | |
3098 | return true; | |
3099 | } | |
3100 | return false; | |
3101 | } | |
cee98a59 | 3102 | \f |
65239d20 RS |
3103 | /* Return true if value X in context CONTEXT is a small-data address |
3104 | that can be rewritten as a LO_SUM. */ | |
ab77a036 RS |
3105 | |
3106 | static bool | |
3107 | mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context) | |
3108 | { | |
3109 | enum mips_symbol_type symbol_type; | |
3110 | ||
08d0963a RS |
3111 | return (mips_lo_relocs[SYMBOL_GP_RELATIVE] |
3112 | && !mips_split_p[SYMBOL_GP_RELATIVE] | |
ab77a036 RS |
3113 | && mips_symbolic_constant_p (x, context, &symbol_type) |
3114 | && symbol_type == SYMBOL_GP_RELATIVE); | |
3115 | } | |
3116 | ||
ab77a036 RS |
3117 | /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the |
3118 | containing MEM, or null if none. */ | |
3119 | ||
3120 | static int | |
3121 | mips_small_data_pattern_1 (rtx *loc, void *data) | |
3122 | { | |
3123 | enum mips_symbol_context context; | |
3124 | ||
3125 | if (GET_CODE (*loc) == LO_SUM) | |
3126 | return -1; | |
3127 | ||
3128 | if (MEM_P (*loc)) | |
3129 | { | |
3130 | if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc)) | |
3131 | return 1; | |
3132 | return -1; | |
3133 | } | |
3134 | ||
3135 | context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA; | |
3136 | return mips_rewrite_small_data_p (*loc, context); | |
3137 | } | |
3138 | ||
3139 | /* Return true if OP refers to small data symbols directly, not through | |
3140 | a LO_SUM. */ | |
3141 | ||
3142 | bool | |
3143 | mips_small_data_pattern_p (rtx op) | |
3144 | { | |
65239d20 | 3145 | return for_each_rtx (&op, mips_small_data_pattern_1, NULL); |
ab77a036 | 3146 | } |
65239d20 | 3147 | |
ab77a036 RS |
3148 | /* A for_each_rtx callback, used by mips_rewrite_small_data. |
3149 | DATA is the containing MEM, or null if none. */ | |
3150 | ||
3151 | static int | |
3152 | mips_rewrite_small_data_1 (rtx *loc, void *data) | |
3153 | { | |
3154 | enum mips_symbol_context context; | |
3155 | ||
3156 | if (MEM_P (*loc)) | |
3157 | { | |
3158 | for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc); | |
3159 | return -1; | |
3160 | } | |
3161 | ||
3162 | context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA; | |
3163 | if (mips_rewrite_small_data_p (*loc, context)) | |
3164 | *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc); | |
3165 | ||
3166 | if (GET_CODE (*loc) == LO_SUM) | |
3167 | return -1; | |
3168 | ||
3169 | return 0; | |
3170 | } | |
3171 | ||
65239d20 RS |
3172 | /* Rewrite instruction pattern PATTERN so that it refers to small data |
3173 | using explicit relocations. */ | |
ab77a036 RS |
3174 | |
3175 | rtx | |
65239d20 | 3176 | mips_rewrite_small_data (rtx pattern) |
ab77a036 | 3177 | { |
65239d20 RS |
3178 | pattern = copy_insn (pattern); |
3179 | for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL); | |
3180 | return pattern; | |
ab77a036 RS |
3181 | } |
3182 | \f | |
65239d20 RS |
3183 | /* We need a lot of little routines to check the range of MIPS16 immediate |
3184 | operands. */ | |
2bcb2ab3 GK |
3185 | |
3186 | static int | |
b4966b1b | 3187 | m16_check_op (rtx op, int low, int high, int mask) |
2bcb2ab3 | 3188 | { |
47ac44d6 | 3189 | return (CONST_INT_P (op) |
65239d20 | 3190 | && IN_RANGE (INTVAL (op), low, high) |
2bcb2ab3 GK |
3191 | && (INTVAL (op) & mask) == 0); |
3192 | } | |
3193 | ||
3194 | int | |
b4966b1b | 3195 | m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 GK |
3196 | { |
3197 | return m16_check_op (op, 0x1, 0x8, 0); | |
3198 | } | |
3199 | ||
3200 | int | |
b4966b1b | 3201 | m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3202 | { |
65239d20 | 3203 | return m16_check_op (op, -0x8, 0x7, 0); |
2bcb2ab3 GK |
3204 | } |
3205 | ||
3206 | int | |
b4966b1b | 3207 | m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3208 | { |
65239d20 | 3209 | return m16_check_op (op, -0x7, 0x8, 0); |
2bcb2ab3 GK |
3210 | } |
3211 | ||
3212 | int | |
b4966b1b | 3213 | m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3214 | { |
65239d20 | 3215 | return m16_check_op (op, -0x10, 0xf, 0); |
2bcb2ab3 GK |
3216 | } |
3217 | ||
3218 | int | |
b4966b1b | 3219 | m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3220 | { |
65239d20 | 3221 | return m16_check_op (op, -0xf, 0x10, 0); |
2bcb2ab3 GK |
3222 | } |
3223 | ||
3224 | int | |
b4966b1b | 3225 | m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3226 | { |
65239d20 | 3227 | return m16_check_op (op, -0x10 << 2, 0xf << 2, 3); |
2bcb2ab3 GK |
3228 | } |
3229 | ||
3230 | int | |
b4966b1b | 3231 | m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3232 | { |
65239d20 | 3233 | return m16_check_op (op, -0xf << 2, 0x10 << 2, 3); |
2bcb2ab3 GK |
3234 | } |
3235 | ||
3236 | int | |
b4966b1b | 3237 | m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3238 | { |
65239d20 | 3239 | return m16_check_op (op, -0x80, 0x7f, 0); |
2bcb2ab3 GK |
3240 | } |
3241 | ||
3242 | int | |
b4966b1b | 3243 | m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3244 | { |
65239d20 | 3245 | return m16_check_op (op, -0x7f, 0x80, 0); |
2bcb2ab3 GK |
3246 | } |
3247 | ||
3248 | int | |
b4966b1b | 3249 | m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 GK |
3250 | { |
3251 | return m16_check_op (op, 0x0, 0xff, 0); | |
3252 | } | |
3253 | ||
3254 | int | |
b4966b1b | 3255 | m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3256 | { |
65239d20 | 3257 | return m16_check_op (op, -0xff, 0x0, 0); |
2bcb2ab3 GK |
3258 | } |
3259 | ||
3260 | int | |
b4966b1b | 3261 | m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3262 | { |
65239d20 | 3263 | return m16_check_op (op, -0x1, 0xfe, 0); |
2bcb2ab3 GK |
3264 | } |
3265 | ||
3266 | int | |
b4966b1b | 3267 | m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 GK |
3268 | { |
3269 | return m16_check_op (op, 0x0, 0xff << 2, 3); | |
3270 | } | |
3271 | ||
3272 | int | |
b4966b1b | 3273 | m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3274 | { |
65239d20 | 3275 | return m16_check_op (op, -0xff << 2, 0x0, 3); |
2bcb2ab3 GK |
3276 | } |
3277 | ||
3278 | int | |
b4966b1b | 3279 | m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3280 | { |
65239d20 | 3281 | return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7); |
2bcb2ab3 GK |
3282 | } |
3283 | ||
3284 | int | |
b4966b1b | 3285 | m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) |
2bcb2ab3 | 3286 | { |
65239d20 | 3287 | return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7); |
2bcb2ab3 | 3288 | } |
cee98a59 | 3289 | \f |
8144a1a8 RS |
3290 | /* The cost of loading values from the constant pool. It should be |
3291 | larger than the cost of any constant we want to synthesize inline. */ | |
8144a1a8 RS |
3292 | #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8) |
3293 | ||
3294 | /* Return the cost of X when used as an operand to the MIPS16 instruction | |
3295 | that implements CODE. Return -1 if there is no such instruction, or if | |
3296 | X is not a valid immediate operand for it. */ | |
3297 | ||
3298 | static int | |
3299 | mips16_constant_cost (int code, HOST_WIDE_INT x) | |
3300 | { | |
3301 | switch (code) | |
3302 | { | |
3303 | case ASHIFT: | |
3304 | case ASHIFTRT: | |
3305 | case LSHIFTRT: | |
3306 | /* Shifts by between 1 and 8 bits (inclusive) are unextended, | |
3307 | other shifts are extended. The shift patterns truncate the shift | |
3308 | count to the right size, so there are no out-of-range values. */ | |
3309 | if (IN_RANGE (x, 1, 8)) | |
3310 | return 0; | |
3311 | return COSTS_N_INSNS (1); | |
3312 | ||
3313 | case PLUS: | |
3314 | if (IN_RANGE (x, -128, 127)) | |
3315 | return 0; | |
3316 | if (SMALL_OPERAND (x)) | |
3317 | return COSTS_N_INSNS (1); | |
3318 | return -1; | |
3319 | ||
3320 | case LEU: | |
3321 | /* Like LE, but reject the always-true case. */ | |
3322 | if (x == -1) | |
3323 | return -1; | |
3324 | case LE: | |
3325 | /* We add 1 to the immediate and use SLT. */ | |
3326 | x += 1; | |
3327 | case XOR: | |
3328 | /* We can use CMPI for an xor with an unsigned 16-bit X. */ | |
3329 | case LT: | |
3330 | case LTU: | |
3331 | if (IN_RANGE (x, 0, 255)) | |
3332 | return 0; | |
3333 | if (SMALL_OPERAND_UNSIGNED (x)) | |
3334 | return COSTS_N_INSNS (1); | |
3335 | return -1; | |
3336 | ||
3337 | case EQ: | |
3338 | case NE: | |
3339 | /* Equality comparisons with 0 are cheap. */ | |
3340 | if (x == 0) | |
3341 | return 0; | |
3342 | return -1; | |
3343 | ||
3344 | default: | |
3345 | return -1; | |
3346 | } | |
3347 | } | |
3348 | ||
3349 | /* Return true if there is a non-MIPS16 instruction that implements CODE | |
3350 | and if that instruction accepts X as an immediate operand. */ | |
3351 | ||
3352 | static int | |
3353 | mips_immediate_operand_p (int code, HOST_WIDE_INT x) | |
3354 | { | |
3355 | switch (code) | |
3356 | { | |
3357 | case ASHIFT: | |
3358 | case ASHIFTRT: | |
3359 | case LSHIFTRT: | |
3360 | /* All shift counts are truncated to a valid constant. */ | |
3361 | return true; | |
3362 | ||
3363 | case ROTATE: | |
3364 | case ROTATERT: | |
3365 | /* Likewise rotates, if the target supports rotates at all. */ | |
3366 | return ISA_HAS_ROR; | |
3367 | ||
3368 | case AND: | |
3369 | case IOR: | |
3370 | case XOR: | |
3371 | /* These instructions take 16-bit unsigned immediates. */ | |
3372 | return SMALL_OPERAND_UNSIGNED (x); | |
3373 | ||
3374 | case PLUS: | |
3375 | case LT: | |
3376 | case LTU: | |
3377 | /* These instructions take 16-bit signed immediates. */ | |
3378 | return SMALL_OPERAND (x); | |
3379 | ||
3380 | case EQ: | |
3381 | case NE: | |
3382 | case GT: | |
3383 | case GTU: | |
3384 | /* The "immediate" forms of these instructions are really | |
3385 | implemented as comparisons with register 0. */ | |
3386 | return x == 0; | |
3387 | ||
3388 | case GE: | |
3389 | case GEU: | |
3390 | /* Likewise, meaning that the only valid immediate operand is 1. */ | |
3391 | return x == 1; | |
3392 | ||
3393 | case LE: | |
3394 | /* We add 1 to the immediate and use SLT. */ | |
3395 | return SMALL_OPERAND (x + 1); | |
3396 | ||
3397 | case LEU: | |
3398 | /* Likewise SLTU, but reject the always-true case. */ | |
3399 | return SMALL_OPERAND (x + 1) && x + 1 != 0; | |
3400 | ||
3401 | case SIGN_EXTRACT: | |
3402 | case ZERO_EXTRACT: | |
3403 | /* The bit position and size are immediate operands. */ | |
3404 | return ISA_HAS_EXT_INS; | |
3405 | ||
3406 | default: | |
3407 | /* By default assume that $0 can be used for 0. */ | |
3408 | return x == 0; | |
3409 | } | |
3410 | } | |
3411 | ||
3412 | /* Return the cost of binary operation X, given that the instruction | |
3413 | sequence for a word-sized or smaller operation has cost SINGLE_COST | |
53d66977 AN |
3414 | and that the sequence of a double-word operation has cost DOUBLE_COST. |
3415 | If SPEED is true, optimize for speed otherwise optimize for size. */ | |
8144a1a8 RS |
3416 | |
3417 | static int | |
53d66977 | 3418 | mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed) |
8144a1a8 RS |
3419 | { |
3420 | int cost; | |
3421 | ||
3422 | if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2) | |
3423 | cost = double_cost; | |
3424 | else | |
3425 | cost = single_cost; | |
3426 | return (cost | |
53d66977 AN |
3427 | + rtx_cost (XEXP (x, 0), SET, speed) |
3428 | + rtx_cost (XEXP (x, 1), GET_CODE (x), speed)); | |
8144a1a8 RS |
3429 | } |
3430 | ||
3431 | /* Return the cost of floating-point multiplications of mode MODE. */ | |
3432 | ||
3433 | static int | |
3434 | mips_fp_mult_cost (enum machine_mode mode) | |
3435 | { | |
3436 | return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf; | |
3437 | } | |
3438 | ||
3439 | /* Return the cost of floating-point divisions of mode MODE. */ | |
3440 | ||
3441 | static int | |
3442 | mips_fp_div_cost (enum machine_mode mode) | |
3443 | { | |
3444 | return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf; | |
3445 | } | |
3446 | ||
3447 | /* Return the cost of sign-extending OP to mode MODE, not including the | |
3448 | cost of OP itself. */ | |
3449 | ||
3450 | static int | |
3451 | mips_sign_extend_cost (enum machine_mode mode, rtx op) | |
3452 | { | |
3453 | if (MEM_P (op)) | |
3454 | /* Extended loads are as cheap as unextended ones. */ | |
3455 | return 0; | |
3456 | ||
3457 | if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) | |
3458 | /* A sign extension from SImode to DImode in 64-bit mode is free. */ | |
3459 | return 0; | |
3460 | ||
3461 | if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E) | |
3462 | /* We can use SEB or SEH. */ | |
3463 | return COSTS_N_INSNS (1); | |
3464 | ||
3465 | /* We need to use a shift left and a shift right. */ | |
3466 | return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2); | |
3467 | } | |
3468 | ||
3469 | /* Return the cost of zero-extending OP to mode MODE, not including the | |
3470 | cost of OP itself. */ | |
3471 | ||
3472 | static int | |
3473 | mips_zero_extend_cost (enum machine_mode mode, rtx op) | |
3474 | { | |
3475 | if (MEM_P (op)) | |
3476 | /* Extended loads are as cheap as unextended ones. */ | |
3477 | return 0; | |
3478 | ||
3479 | if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode) | |
3480 | /* We need a shift left by 32 bits and a shift right by 32 bits. */ | |
3481 | return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2); | |
3482 | ||
3483 | if (GENERATE_MIPS16E) | |
3484 | /* We can use ZEB or ZEH. */ | |
3485 | return COSTS_N_INSNS (1); | |
3486 | ||
3487 | if (TARGET_MIPS16) | |
3488 | /* We need to load 0xff or 0xffff into a register and use AND. */ | |
3489 | return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3); | |
3490 | ||
3491 | /* We can use ANDI. */ | |
3492 | return COSTS_N_INSNS (1); | |
3493 | } | |
3494 | ||
3495 | /* Implement TARGET_RTX_COSTS. */ | |
3496 | ||
cafe096b | 3497 | static bool |
53d66977 | 3498 | mips_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed) |
cafe096b EC |
3499 | { |
3500 | enum machine_mode mode = GET_MODE (x); | |
c1bd2d66 | 3501 | bool float_mode_p = FLOAT_MODE_P (mode); |
8144a1a8 RS |
3502 | int cost; |
3503 | rtx addr; | |
3504 | ||
3505 | /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't | |
3506 | appear in the instruction stream, and the cost of a comparison is | |
3507 | really the cost of the branch or scc condition. At the time of | |
65239d20 | 3508 | writing, GCC only uses an explicit outer COMPARE code when optabs |
8144a1a8 RS |
3509 | is testing whether a constant is expensive enough to force into a |
3510 | register. We want optabs to pass such constants through the MIPS | |
3511 | expanders instead, so make all constants very cheap here. */ | |
3512 | if (outer_code == COMPARE) | |
3513 | { | |
3514 | gcc_assert (CONSTANT_P (x)); | |
3515 | *total = 0; | |
3516 | return true; | |
3517 | } | |
c1bd2d66 | 3518 | |
cafe096b EC |
3519 | switch (code) |
3520 | { | |
3521 | case CONST_INT: | |
8144a1a8 RS |
3522 | /* Treat *clear_upper32-style ANDs as having zero cost in the |
3523 | second operand. The cost is entirely in the first operand. | |
3524 | ||
3525 | ??? This is needed because we would otherwise try to CSE | |
3526 | the constant operand. Although that's the right thing for | |
3527 | instructions that continue to be a register operation throughout | |
3528 | compilation, it is disastrous for instructions that could | |
3529 | later be converted into a memory operation. */ | |
3530 | if (TARGET_64BIT | |
3531 | && outer_code == AND | |
3532 | && UINTVAL (x) == 0xffffffff) | |
3533 | { | |
3534 | *total = 0; | |
3535 | return true; | |
3536 | } | |
cafe096b | 3537 | |
8144a1a8 RS |
3538 | if (TARGET_MIPS16) |
3539 | { | |
3540 | cost = mips16_constant_cost (outer_code, INTVAL (x)); | |
3541 | if (cost >= 0) | |
c1bd2d66 | 3542 | { |
8144a1a8 | 3543 | *total = cost; |
c1bd2d66 EC |
3544 | return true; |
3545 | } | |
8144a1a8 RS |
3546 | } |
3547 | else | |
3548 | { | |
3549 | /* When not optimizing for size, we care more about the cost | |
3550 | of hot code, and hot code is often in a loop. If a constant | |
3551 | operand needs to be forced into a register, we will often be | |
3552 | able to hoist the constant load out of the loop, so the load | |
3553 | should not contribute to the cost. */ | |
53d66977 | 3554 | if (speed || mips_immediate_operand_p (outer_code, INTVAL (x))) |
c1bd2d66 EC |
3555 | { |
3556 | *total = 0; | |
3557 | return true; | |
3558 | } | |
3559 | } | |
8144a1a8 | 3560 | /* Fall through. */ |
cafe096b EC |
3561 | |
3562 | case CONST: | |
3563 | case SYMBOL_REF: | |
3564 | case LABEL_REF: | |
3565 | case CONST_DOUBLE: | |
206c2d7a RS |
3566 | if (force_to_mem_operand (x, VOIDmode)) |
3567 | { | |
3568 | *total = COSTS_N_INSNS (1); | |
3569 | return true; | |
3570 | } | |
8144a1a8 RS |
3571 | cost = mips_const_insns (x); |
3572 | if (cost > 0) | |
108b61d5 | 3573 | { |
8144a1a8 RS |
3574 | /* If the constant is likely to be stored in a GPR, SETs of |
3575 | single-insn constants are as cheap as register sets; we | |
3576 | never want to CSE them. | |
3577 | ||
3578 | Don't reduce the cost of storing a floating-point zero in | |
3579 | FPRs. If we have a zero in an FPR for other reasons, we | |
3580 | can get better cfg-cleanup and delayed-branch results by | |
3581 | using it consistently, rather than using $0 sometimes and | |
3582 | an FPR at other times. Also, moves between floating-point | |
3583 | registers are sometimes cheaper than (D)MTC1 $0. */ | |
3584 | if (cost == 1 | |
3585 | && outer_code == SET | |
3586 | && !(float_mode_p && TARGET_HARD_FLOAT)) | |
3587 | cost = 0; | |
3588 | /* When non-MIPS16 code loads a constant N>1 times, we rarely | |
3589 | want to CSE the constant itself. It is usually better to | |
3590 | have N copies of the last operation in the sequence and one | |
3591 | shared copy of the other operations. (Note that this is | |
3592 | not true for MIPS16 code, where the final operation in the | |
3593 | sequence is often an extended instruction.) | |
3594 | ||
3595 | Also, if we have a CONST_INT, we don't know whether it is | |
3596 | for a word or doubleword operation, so we cannot rely on | |
3597 | the result of mips_build_integer. */ | |
3598 | else if (!TARGET_MIPS16 | |
3599 | && (outer_code == SET || mode == VOIDmode)) | |
3600 | cost = 1; | |
3601 | *total = COSTS_N_INSNS (cost); | |
108b61d5 RS |
3602 | return true; |
3603 | } | |
8144a1a8 RS |
3604 | /* The value will need to be fetched from the constant pool. */ |
3605 | *total = CONSTANT_POOL_COST; | |
3606 | return true; | |
3607 | ||
3608 | case MEM: | |
3609 | /* If the address is legitimate, return the number of | |
3610 | instructions it needs. */ | |
3611 | addr = XEXP (x, 0); | |
3612 | cost = mips_address_insns (addr, mode, true); | |
3613 | if (cost > 0) | |
108b61d5 | 3614 | { |
8144a1a8 | 3615 | *total = COSTS_N_INSNS (cost + 1); |
108b61d5 RS |
3616 | return true; |
3617 | } | |
8144a1a8 RS |
3618 | /* Check for a scaled indexed address. */ |
3619 | if (mips_lwxs_address_p (addr)) | |
3620 | { | |
3621 | *total = COSTS_N_INSNS (2); | |
3622 | return true; | |
3623 | } | |
3624 | /* Otherwise use the default handling. */ | |
3625 | return false; | |
cafe096b EC |
3626 | |
3627 | case FFS: | |
3628 | *total = COSTS_N_INSNS (6); | |
8144a1a8 | 3629 | return false; |
cafe096b EC |
3630 | |
3631 | case NOT: | |
8144a1a8 RS |
3632 | *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1); |
3633 | return false; | |
cafe096b EC |
3634 | |
3635 | case AND: | |
8144a1a8 RS |
3636 | /* Check for a *clear_upper32 pattern and treat it like a zero |
3637 | extension. See the pattern's comment for details. */ | |
3638 | if (TARGET_64BIT | |
3639 | && mode == DImode | |
3640 | && CONST_INT_P (XEXP (x, 1)) | |
3641 | && UINTVAL (XEXP (x, 1)) == 0xffffffff) | |
3642 | { | |
3643 | *total = (mips_zero_extend_cost (mode, XEXP (x, 0)) | |
bbbbb16a | 3644 | + rtx_cost (XEXP (x, 0), SET, speed)); |
8144a1a8 RS |
3645 | return true; |
3646 | } | |
3647 | /* Fall through. */ | |
3648 | ||
cafe096b EC |
3649 | case IOR: |
3650 | case XOR: | |
8144a1a8 | 3651 | /* Double-word operations use two single-word operations. */ |
53d66977 AN |
3652 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2), |
3653 | speed); | |
8144a1a8 | 3654 | return true; |
cafe096b EC |
3655 | |
3656 | case ASHIFT: | |
3657 | case ASHIFTRT: | |
3658 | case LSHIFTRT: | |
8144a1a8 RS |
3659 | case ROTATE: |
3660 | case ROTATERT: | |
3661 | if (CONSTANT_P (XEXP (x, 1))) | |
53d66977 AN |
3662 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), |
3663 | speed); | |
8144a1a8 | 3664 | else |
53d66977 AN |
3665 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12), |
3666 | speed); | |
8144a1a8 | 3667 | return true; |
cafe096b EC |
3668 | |
3669 | case ABS: | |
c1bd2d66 | 3670 | if (float_mode_p) |
8144a1a8 | 3671 | *total = mips_cost->fp_add; |
cafe096b EC |
3672 | else |
3673 | *total = COSTS_N_INSNS (4); | |
8144a1a8 | 3674 | return false; |
cafe096b EC |
3675 | |
3676 | case LO_SUM: | |
8144a1a8 RS |
3677 | /* Low-part immediates need an extended MIPS16 instruction. */ |
3678 | *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1) | |
bbbbb16a | 3679 | + rtx_cost (XEXP (x, 0), SET, speed)); |
8144a1a8 RS |
3680 | return true; |
3681 | ||
3682 | case LT: | |
3683 | case LTU: | |
3684 | case LE: | |
3685 | case LEU: | |
3686 | case GT: | |
3687 | case GTU: | |
3688 | case GE: | |
3689 | case GEU: | |
3690 | case EQ: | |
3691 | case NE: | |
3692 | case UNORDERED: | |
3693 | case LTGT: | |
3694 | /* Branch comparisons have VOIDmode, so use the first operand's | |
3695 | mode instead. */ | |
3696 | mode = GET_MODE (XEXP (x, 0)); | |
3697 | if (FLOAT_MODE_P (mode)) | |
3698 | { | |
3699 | *total = mips_cost->fp_add; | |
3700 | return false; | |
3701 | } | |
53d66977 AN |
3702 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4), |
3703 | speed); | |
cafe096b EC |
3704 | return true; |
3705 | ||
cafe096b | 3706 | case MINUS: |
8144a1a8 | 3707 | if (float_mode_p |
b51469a5 | 3708 | && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode)) |
8144a1a8 RS |
3709 | && TARGET_FUSED_MADD |
3710 | && !HONOR_NANS (mode) | |
3711 | && !HONOR_SIGNED_ZEROS (mode)) | |
3712 | { | |
3713 | /* See if we can use NMADD or NMSUB. See mips.md for the | |
3714 | associated patterns. */ | |
3715 | rtx op0 = XEXP (x, 0); | |
3716 | rtx op1 = XEXP (x, 1); | |
3717 | if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG) | |
3718 | { | |
3719 | *total = (mips_fp_mult_cost (mode) | |
bbbbb16a ILT |
3720 | + rtx_cost (XEXP (XEXP (op0, 0), 0), SET, speed) |
3721 | + rtx_cost (XEXP (op0, 1), SET, speed) | |
3722 | + rtx_cost (op1, SET, speed)); | |
8144a1a8 RS |
3723 | return true; |
3724 | } | |
3725 | if (GET_CODE (op1) == MULT) | |
3726 | { | |
3727 | *total = (mips_fp_mult_cost (mode) | |
bbbbb16a ILT |
3728 | + rtx_cost (op0, SET, speed) |
3729 | + rtx_cost (XEXP (op1, 0), SET, speed) | |
3730 | + rtx_cost (XEXP (op1, 1), SET, speed)); | |
8144a1a8 RS |
3731 | return true; |
3732 | } | |
3733 | } | |
3734 | /* Fall through. */ | |
3735 | ||
3736 | case PLUS: | |
c1bd2d66 EC |
3737 | if (float_mode_p) |
3738 | { | |
65239d20 RS |
3739 | /* If this is part of a MADD or MSUB, treat the PLUS as |
3740 | being free. */ | |
8144a1a8 RS |
3741 | if (ISA_HAS_FP4 |
3742 | && TARGET_FUSED_MADD | |
3743 | && GET_CODE (XEXP (x, 0)) == MULT) | |
3744 | *total = 0; | |
3745 | else | |
3746 | *total = mips_cost->fp_add; | |
3747 | return false; | |
c1bd2d66 EC |
3748 | } |
3749 | ||
8144a1a8 RS |
3750 | /* Double-word operations require three single-word operations and |
3751 | an SLTU. The MIPS16 version then needs to move the result of | |
3752 | the SLTU from $24 to a MIPS16 register. */ | |
3753 | *total = mips_binary_cost (x, COSTS_N_INSNS (1), | |
53d66977 AN |
3754 | COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4), |
3755 | speed); | |
8144a1a8 | 3756 | return true; |
cafe096b EC |
3757 | |
3758 | case NEG: | |
8144a1a8 | 3759 | if (float_mode_p |
b51469a5 | 3760 | && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode)) |
8144a1a8 RS |
3761 | && TARGET_FUSED_MADD |
3762 | && !HONOR_NANS (mode) | |
3763 | && HONOR_SIGNED_ZEROS (mode)) | |
3764 | { | |
3765 | /* See if we can use NMADD or NMSUB. See mips.md for the | |
3766 | associated patterns. */ | |
3767 | rtx op = XEXP (x, 0); | |
3768 | if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) | |
3769 | && GET_CODE (XEXP (op, 0)) == MULT) | |
3770 | { | |
3771 | *total = (mips_fp_mult_cost (mode) | |
bbbbb16a ILT |
3772 | + rtx_cost (XEXP (XEXP (op, 0), 0), SET, speed) |
3773 | + rtx_cost (XEXP (XEXP (op, 0), 1), SET, speed) | |
3774 | + rtx_cost (XEXP (op, 1), SET, speed)); | |
8144a1a8 RS |
3775 | return true; |
3776 | } | |
3777 | } | |
3778 | ||
3779 | if (float_mode_p) | |
3780 | *total = mips_cost->fp_add; | |
3781 | else | |
3782 | *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1); | |
cafe096b EC |
3783 | return false; |
3784 | ||
3785 | case MULT: | |
8144a1a8 RS |
3786 | if (float_mode_p) |
3787 | *total = mips_fp_mult_cost (mode); | |
3788 | else if (mode == DImode && !TARGET_64BIT) | |
3789 | /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions, | |
3790 | where the mulsidi3 always includes an MFHI and an MFLO. */ | |
53d66977 AN |
3791 | *total = (speed |
3792 | ? mips_cost->int_mult_si * 3 + 6 | |
3793 | : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9)); | |
3794 | else if (!speed) | |
8144a1a8 RS |
3795 | *total = (ISA_HAS_MUL3 ? 1 : 2); |
3796 | else if (mode == DImode) | |
c1bd2d66 | 3797 | *total = mips_cost->int_mult_di; |
8144a1a8 RS |
3798 | else |
3799 | *total = mips_cost->int_mult_si; | |
3800 | return false; | |
cafe096b EC |
3801 | |
3802 | case DIV: | |
8144a1a8 | 3803 | /* Check for a reciprocal. */ |
a1569a0e RS |
3804 | if (float_mode_p |
3805 | && ISA_HAS_FP4 | |
3806 | && flag_unsafe_math_optimizations | |
3807 | && XEXP (x, 0) == CONST1_RTX (mode)) | |
8144a1a8 | 3808 | { |
a1569a0e RS |
3809 | if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT) |
3810 | /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the | |
3811 | division as being free. */ | |
bbbbb16a | 3812 | *total = rtx_cost (XEXP (x, 1), SET, speed); |
a1569a0e | 3813 | else |
bbbbb16a ILT |
3814 | *total = (mips_fp_div_cost (mode) |
3815 | + rtx_cost (XEXP (x, 1), SET, speed)); | |
a1569a0e | 3816 | return true; |
8144a1a8 RS |
3817 | } |
3818 | /* Fall through. */ | |
3819 | ||
3820 | case SQRT: | |
cafe096b | 3821 | case MOD: |
c1bd2d66 EC |
3822 | if (float_mode_p) |
3823 | { | |
8144a1a8 RS |
3824 | *total = mips_fp_div_cost (mode); |
3825 | return false; | |
c1bd2d66 | 3826 | } |
031a26c5 | 3827 | /* Fall through. */ |
cafe096b EC |
3828 | |
3829 | case UDIV: | |
3830 | case UMOD: | |
53d66977 | 3831 | if (!speed) |
8144a1a8 RS |
3832 | { |
3833 | /* It is our responsibility to make division by a power of 2 | |
3834 | as cheap as 2 register additions if we want the division | |
3835 | expanders to be used for such operations; see the setting | |
3836 | of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16 | |
3837 | should always produce shorter code than using | |
3838 | expand_sdiv2_pow2. */ | |
3839 | if (TARGET_MIPS16 | |
3840 | && CONST_INT_P (XEXP (x, 1)) | |
3841 | && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) | |
3842 | { | |
bbbbb16a | 3843 | *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), SET, speed); |
8144a1a8 RS |
3844 | return true; |
3845 | } | |
3846 | *total = COSTS_N_INSNS (mips_idiv_insns ()); | |
3847 | } | |
3848 | else if (mode == DImode) | |
c1bd2d66 | 3849 | *total = mips_cost->int_div_di; |
cafe096b | 3850 | else |
c1bd2d66 | 3851 | *total = mips_cost->int_div_si; |
8144a1a8 | 3852 | return false; |
cafe096b EC |
3853 | |
3854 | case SIGN_EXTEND: | |
8144a1a8 RS |
3855 | *total = mips_sign_extend_cost (mode, XEXP (x, 0)); |
3856 | return false; | |
cafe096b EC |
3857 | |
3858 | case ZERO_EXTEND: | |
8144a1a8 RS |
3859 | *total = mips_zero_extend_cost (mode, XEXP (x, 0)); |
3860 | return false; | |
cafe096b | 3861 | |
c1bd2d66 EC |
3862 | case FLOAT: |
3863 | case UNSIGNED_FLOAT: | |
3864 | case FIX: | |
3865 | case FLOAT_EXTEND: | |
3866 | case FLOAT_TRUNCATE: | |
c1bd2d66 | 3867 | *total = mips_cost->fp_add; |
8144a1a8 | 3868 | return false; |
c1bd2d66 | 3869 | |
cafe096b EC |
3870 | default: |
3871 | return false; | |
3872 | } | |
3873 | } | |
3874 | ||
65239d20 | 3875 | /* Implement TARGET_ADDRESS_COST. */ |
cafe096b EC |
3876 | |
3877 | static int | |
f40751dd | 3878 | mips_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED) |
cafe096b | 3879 | { |
5955b0a3 | 3880 | return mips_address_insns (addr, SImode, false); |
cafe096b | 3881 | } |
cee98a59 | 3882 | \f |
6f5a62e9 RS |
3883 | /* Information about a single instruction in a multi-instruction |
3884 | asm sequence. */ | |
3885 | struct mips_multi_member { | |
3886 | /* True if this is a label, false if it is code. */ | |
3887 | bool is_label_p; | |
3888 | ||
3889 | /* The output_asm_insn format of the instruction. */ | |
3890 | const char *format; | |
3891 | ||
3892 | /* The operands to the instruction. */ | |
3893 | rtx operands[MAX_RECOG_OPERANDS]; | |
3894 | }; | |
3895 | typedef struct mips_multi_member mips_multi_member; | |
3896 | ||
3897 | /* Vector definitions for the above. */ | |
3898 | DEF_VEC_O(mips_multi_member); | |
3899 | DEF_VEC_ALLOC_O(mips_multi_member, heap); | |
3900 | ||
3901 | /* The instructions that make up the current multi-insn sequence. */ | |
3902 | static VEC (mips_multi_member, heap) *mips_multi_members; | |
3903 | ||
3904 | /* How many instructions (as opposed to labels) are in the current | |
3905 | multi-insn sequence. */ | |
3906 | static unsigned int mips_multi_num_insns; | |
3907 | ||
3908 | /* Start a new multi-insn sequence. */ | |
3909 | ||
3910 | static void | |
3911 | mips_multi_start (void) | |
3912 | { | |
3913 | VEC_truncate (mips_multi_member, mips_multi_members, 0); | |
3914 | mips_multi_num_insns = 0; | |
3915 | } | |
3916 | ||
3917 | /* Add a new, uninitialized member to the current multi-insn sequence. */ | |
3918 | ||
3919 | static struct mips_multi_member * | |
3920 | mips_multi_add (void) | |
3921 | { | |
3922 | return VEC_safe_push (mips_multi_member, heap, mips_multi_members, 0); | |
3923 | } | |
3924 | ||
3925 | /* Add a normal insn with the given asm format to the current multi-insn | |
3926 | sequence. The other arguments are a null-terminated list of operands. */ | |
3927 | ||
3928 | static void | |
3929 | mips_multi_add_insn (const char *format, ...) | |
3930 | { | |
3931 | struct mips_multi_member *member; | |
3932 | va_list ap; | |
3933 | unsigned int i; | |
3934 | rtx op; | |
3935 | ||
3936 | member = mips_multi_add (); | |
3937 | member->is_label_p = false; | |
3938 | member->format = format; | |
3939 | va_start (ap, format); | |
3940 | i = 0; | |
3941 | while ((op = va_arg (ap, rtx))) | |
3942 | member->operands[i++] = op; | |
3943 | va_end (ap); | |
3944 | mips_multi_num_insns++; | |
3945 | } | |
3946 | ||
3947 | /* Add the given label definition to the current multi-insn sequence. | |
3948 | The definition should include the colon. */ | |
3949 | ||
3950 | static void | |
3951 | mips_multi_add_label (const char *label) | |
3952 | { | |
3953 | struct mips_multi_member *member; | |
3954 | ||
3955 | member = mips_multi_add (); | |
3956 | member->is_label_p = true; | |
3957 | member->format = label; | |
3958 | } | |
3959 | ||
3960 | /* Return the index of the last member of the current multi-insn sequence. */ | |
3961 | ||
3962 | static unsigned int | |
3963 | mips_multi_last_index (void) | |
3964 | { | |
3965 | return VEC_length (mips_multi_member, mips_multi_members) - 1; | |
3966 | } | |
3967 | ||
3968 | /* Add a copy of an existing instruction to the current multi-insn | |
3969 | sequence. I is the index of the instruction that should be copied. */ | |
3970 | ||
3971 | static void | |
3972 | mips_multi_copy_insn (unsigned int i) | |
3973 | { | |
3974 | struct mips_multi_member *member; | |
3975 | ||
3976 | member = mips_multi_add (); | |
3977 | memcpy (member, VEC_index (mips_multi_member, mips_multi_members, i), | |
3978 | sizeof (*member)); | |
3979 | gcc_assert (!member->is_label_p); | |
3980 | } | |
3981 | ||
3982 | /* Change the operand of an existing instruction in the current | |
3983 | multi-insn sequence. I is the index of the instruction, | |
3984 | OP is the index of the operand, and X is the new value. */ | |
3985 | ||
3986 | static void | |
3987 | mips_multi_set_operand (unsigned int i, unsigned int op, rtx x) | |
3988 | { | |
3989 | VEC_index (mips_multi_member, mips_multi_members, i)->operands[op] = x; | |
3990 | } | |
3991 | ||
3992 | /* Write out the asm code for the current multi-insn sequence. */ | |
3993 | ||
3994 | static void | |
3995 | mips_multi_write (void) | |
3996 | { | |
3997 | struct mips_multi_member *member; | |
3998 | unsigned int i; | |
3999 | ||
4000 | for (i = 0; | |
4001 | VEC_iterate (mips_multi_member, mips_multi_members, i, member); | |
4002 | i++) | |
4003 | if (member->is_label_p) | |
4004 | fprintf (asm_out_file, "%s\n", member->format); | |
4005 | else | |
4006 | output_asm_insn (member->format, member->operands); | |
4007 | } | |
4008 | \f | |
5b0f0db6 RS |
4009 | /* Return one word of double-word value OP, taking into account the fixed |
4010 | endianness of certain registers. HIGH_P is true to select the high part, | |
4011 | false to select the low part. */ | |
92544bdf | 4012 | |
5b0f0db6 | 4013 | rtx |
65239d20 | 4014 | mips_subword (rtx op, bool high_p) |
5b0f0db6 | 4015 | { |
0064fbe9 | 4016 | unsigned int byte, offset; |
5b0f0db6 | 4017 | enum machine_mode mode; |
cee98a59 | 4018 | |
5b0f0db6 RS |
4019 | mode = GET_MODE (op); |
4020 | if (mode == VOIDmode) | |
21dfc6dc | 4021 | mode = TARGET_64BIT ? TImode : DImode; |
cee98a59 | 4022 | |
5b0f0db6 RS |
4023 | if (TARGET_BIG_ENDIAN ? !high_p : high_p) |
4024 | byte = UNITS_PER_WORD; | |
4025 | else | |
4026 | byte = 0; | |
cee98a59 | 4027 | |
48156a39 | 4028 | if (FP_REG_RTX_P (op)) |
0064fbe9 RS |
4029 | { |
4030 | /* Paired FPRs are always ordered little-endian. */ | |
4031 | offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0); | |
4032 | return gen_rtx_REG (word_mode, REGNO (op) + offset); | |
4033 | } | |
cee98a59 | 4034 | |
66083422 | 4035 | if (MEM_P (op)) |
108b61d5 | 4036 | return mips_rewrite_small_data (adjust_address (op, word_mode, byte)); |
b8eb88d0 | 4037 | |
5b0f0db6 RS |
4038 | return simplify_gen_subreg (word_mode, op, mode, byte); |
4039 | } | |
cee98a59 | 4040 | |
5b0f0db6 | 4041 | /* Return true if a 64-bit move from SRC to DEST should be split into two. */ |
cee98a59 | 4042 | |
5b0f0db6 | 4043 | bool |
b4966b1b | 4044 | mips_split_64bit_move_p (rtx dest, rtx src) |
5b0f0db6 RS |
4045 | { |
4046 | if (TARGET_64BIT) | |
4047 | return false; | |
cee98a59 | 4048 | |
65239d20 RS |
4049 | /* FPR-to-FPR moves can be done in a single instruction, if they're |
4050 | allowed at all. */ | |
5b0f0db6 RS |
4051 | if (FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) |
4052 | return false; | |
cee98a59 | 4053 | |
f457938f RS |
4054 | /* Check for floating-point loads and stores. */ |
4055 | if (ISA_HAS_LDC1_SDC1) | |
5b0f0db6 | 4056 | { |
66083422 | 4057 | if (FP_REG_RTX_P (dest) && MEM_P (src)) |
5b0f0db6 | 4058 | return false; |
66083422 | 4059 | if (FP_REG_RTX_P (src) && MEM_P (dest)) |
5b0f0db6 RS |
4060 | return false; |
4061 | } | |
4062 | return true; | |
4063 | } | |
b8eb88d0 | 4064 | |
0064fbe9 RS |
4065 | /* Split a doubleword move from SRC to DEST. On 32-bit targets, |
4066 | this function handles 64-bit moves for which mips_split_64bit_move_p | |
4067 | holds. For 64-bit targets, this function handles 128-bit moves. */ | |
cee98a59 | 4068 | |
5b0f0db6 | 4069 | void |
0064fbe9 | 4070 | mips_split_doubleword_move (rtx dest, rtx src) |
5b0f0db6 | 4071 | { |
21dfc6dc RS |
4072 | rtx low_dest; |
4073 | ||
0064fbe9 | 4074 | if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src)) |
5b0f0db6 | 4075 | { |
0064fbe9 RS |
4076 | if (!TARGET_64BIT && GET_MODE (dest) == DImode) |
4077 | emit_insn (gen_move_doubleword_fprdi (dest, src)); | |
4078 | else if (!TARGET_64BIT && GET_MODE (dest) == DFmode) | |
4079 | emit_insn (gen_move_doubleword_fprdf (dest, src)); | |
e5a2b69d RS |
4080 | else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode) |
4081 | emit_insn (gen_move_doubleword_fprv2sf (dest, src)); | |
93581857 MS |
4082 | else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode) |
4083 | emit_insn (gen_move_doubleword_fprv2si (dest, src)); | |
4084 | else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode) | |
4085 | emit_insn (gen_move_doubleword_fprv4hi (dest, src)); | |
4086 | else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode) | |
4087 | emit_insn (gen_move_doubleword_fprv8qi (dest, src)); | |
0064fbe9 RS |
4088 | else if (TARGET_64BIT && GET_MODE (dest) == TFmode) |
4089 | emit_insn (gen_move_doubleword_fprtf (dest, src)); | |
6f428062 | 4090 | else |
0064fbe9 | 4091 | gcc_unreachable (); |
5b0f0db6 | 4092 | } |
21dfc6dc RS |
4093 | else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST) |
4094 | { | |
4095 | low_dest = mips_subword (dest, false); | |
4096 | mips_emit_move (low_dest, mips_subword (src, false)); | |
4097 | if (TARGET_64BIT) | |
4098 | emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest)); | |
4099 | else | |
4100 | emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest)); | |
4101 | } | |
4102 | else if (REG_P (src) && REGNO (src) == MD_REG_FIRST) | |
4103 | { | |
4104 | mips_emit_move (mips_subword (dest, false), mips_subword (src, false)); | |
4105 | if (TARGET_64BIT) | |
4106 | emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src)); | |
4107 | else | |
4108 | emit_insn (gen_mfhisi_di (mips_subword (dest, true), src)); | |
4109 | } | |
5b0f0db6 RS |
4110 | else |
4111 | { | |
4112 | /* The operation can be split into two normal moves. Decide in | |
4113 | which order to do them. */ | |
65239d20 | 4114 | low_dest = mips_subword (dest, false); |
66083422 | 4115 | if (REG_P (low_dest) |
5b0f0db6 | 4116 | && reg_overlap_mentioned_p (low_dest, src)) |
cee98a59 | 4117 | { |
65239d20 RS |
4118 | mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); |
4119 | mips_emit_move (low_dest, mips_subword (src, false)); | |
cee98a59 | 4120 | } |
5b0f0db6 | 4121 | else |
cee98a59 | 4122 | { |
65239d20 RS |
4123 | mips_emit_move (low_dest, mips_subword (src, false)); |
4124 | mips_emit_move (mips_subword (dest, true), mips_subword (src, true)); | |
cee98a59 | 4125 | } |
5b0f0db6 RS |
4126 | } |
4127 | } | |
4128 | \f | |
4129 | /* Return the appropriate instructions to move SRC into DEST. Assume | |
4130 | that SRC is operand 1 and DEST is operand 0. */ | |
cee98a59 | 4131 | |
5b0f0db6 | 4132 | const char * |
b4966b1b | 4133 | mips_output_move (rtx dest, rtx src) |
5b0f0db6 RS |
4134 | { |
4135 | enum rtx_code dest_code, src_code; | |
65239d20 | 4136 | enum machine_mode mode; |
c93c5160 | 4137 | enum mips_symbol_type symbol_type; |
5b0f0db6 | 4138 | bool dbl_p; |
cee98a59 | 4139 | |
5b0f0db6 RS |
4140 | dest_code = GET_CODE (dest); |
4141 | src_code = GET_CODE (src); | |
65239d20 RS |
4142 | mode = GET_MODE (dest); |
4143 | dbl_p = (GET_MODE_SIZE (mode) == 8); | |
cee98a59 | 4144 | |
5b0f0db6 RS |
4145 | if (dbl_p && mips_split_64bit_move_p (dest, src)) |
4146 | return "#"; | |
910628b8 | 4147 | |
5b0f0db6 | 4148 | if ((src_code == REG && GP_REG_P (REGNO (src))) |
65239d20 | 4149 | || (!TARGET_MIPS16 && src == CONST0_RTX (mode))) |
5b0f0db6 RS |
4150 | { |
4151 | if (dest_code == REG) | |
910628b8 | 4152 | { |
5b0f0db6 | 4153 | if (GP_REG_P (REGNO (dest))) |
245115a4 | 4154 | return "move\t%0,%z1"; |
cafe096b | 4155 | |
21dfc6dc RS |
4156 | /* Moves to HI are handled by special .md insns. */ |
4157 | if (REGNO (dest) == LO_REGNUM) | |
4158 | return "mtlo\t%z1"; | |
cafe096b | 4159 | |
118ea793 CF |
4160 | if (DSP_ACC_REG_P (REGNO (dest))) |
4161 | { | |
4162 | static char retval[] = "mt__\t%z1,%q0"; | |
65239d20 | 4163 | |
118ea793 CF |
4164 | retval[2] = reg_names[REGNO (dest)][4]; |
4165 | retval[3] = reg_names[REGNO (dest)][5]; | |
4166 | return retval; | |
4167 | } | |
4168 | ||
5b0f0db6 | 4169 | if (FP_REG_P (REGNO (dest))) |
65239d20 | 4170 | return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0"; |
cafe096b | 4171 | |
5b0f0db6 RS |
4172 | if (ALL_COP_REG_P (REGNO (dest))) |
4173 | { | |
4174 | static char retval[] = "dmtc_\t%z1,%0"; | |
cafe096b | 4175 | |
5b0f0db6 | 4176 | retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); |
65239d20 | 4177 | return dbl_p ? retval : retval + 1; |
5b0f0db6 RS |
4178 | } |
4179 | } | |
4180 | if (dest_code == MEM) | |
21dfc6dc RS |
4181 | switch (GET_MODE_SIZE (mode)) |
4182 | { | |
4183 | case 1: return "sb\t%z1,%0"; | |
4184 | case 2: return "sh\t%z1,%0"; | |
4185 | case 4: return "sw\t%z1,%0"; | |
4186 | case 8: return "sd\t%z1,%0"; | |
4187 | } | |
cee98a59 | 4188 | } |
5b0f0db6 | 4189 | if (dest_code == REG && GP_REG_P (REGNO (dest))) |
cee98a59 | 4190 | { |
5b0f0db6 | 4191 | if (src_code == REG) |
cee98a59 | 4192 | { |
21dfc6dc RS |
4193 | /* Moves from HI are handled by special .md insns. */ |
4194 | if (REGNO (src) == LO_REGNUM) | |
4195 | { | |
4196 | /* When generating VR4120 or VR4130 code, we use MACC and | |
4197 | DMACC instead of MFLO. This avoids both the normal | |
4198 | MIPS III HI/LO hazards and the errata related to | |
4199 | -mfix-vr4130. */ | |
4200 | if (ISA_HAS_MACCHI) | |
4201 | return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%."; | |
4202 | return "mflo\t%0"; | |
4203 | } | |
65239d20 | 4204 | |
118ea793 CF |
4205 | if (DSP_ACC_REG_P (REGNO (src))) |
4206 | { | |
4207 | static char retval[] = "mf__\t%0,%q1"; | |
65239d20 | 4208 | |
118ea793 CF |
4209 | retval[2] = reg_names[REGNO (src)][4]; |
4210 | retval[3] = reg_names[REGNO (src)][5]; | |
4211 | return retval; | |
4212 | } | |
4213 | ||
5b0f0db6 | 4214 | if (FP_REG_P (REGNO (src))) |
65239d20 | 4215 | return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1"; |
cee98a59 | 4216 | |
5b0f0db6 | 4217 | if (ALL_COP_REG_P (REGNO (src))) |
d604bca3 | 4218 | { |
5b0f0db6 | 4219 | static char retval[] = "dmfc_\t%0,%1"; |
d604bca3 | 4220 | |
5b0f0db6 | 4221 | retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); |
65239d20 | 4222 | return dbl_p ? retval : retval + 1; |
d604bca3 | 4223 | } |
65239d20 RS |
4224 | |
4225 | if (ST_REG_P (REGNO (src)) && ISA_HAS_8CC) | |
4226 | return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1"; | |
cee98a59 MM |
4227 | } |
4228 | ||
5b0f0db6 | 4229 | if (src_code == MEM) |
21dfc6dc RS |
4230 | switch (GET_MODE_SIZE (mode)) |
4231 | { | |
4232 | case 1: return "lbu\t%0,%1"; | |
4233 | case 2: return "lhu\t%0,%1"; | |
4234 | case 4: return "lw\t%0,%1"; | |
4235 | case 8: return "ld\t%0,%1"; | |
4236 | } | |
cee98a59 | 4237 | |
5b0f0db6 | 4238 | if (src_code == CONST_INT) |
cee98a59 | 4239 | { |
65239d20 RS |
4240 | /* Don't use the X format for the operand itself, because that |
4241 | will give out-of-range numbers for 64-bit hosts and 32-bit | |
4242 | targets. */ | |
5b0f0db6 RS |
4243 | if (!TARGET_MIPS16) |
4244 | return "li\t%0,%1\t\t\t# %X1"; | |
4245 | ||
65239d20 | 4246 | if (SMALL_OPERAND_UNSIGNED (INTVAL (src))) |
5b0f0db6 RS |
4247 | return "li\t%0,%1"; |
4248 | ||
65239d20 | 4249 | if (SMALL_OPERAND_UNSIGNED (-INTVAL (src))) |
bb732af8 | 4250 | return "#"; |
cee98a59 MM |
4251 | } |
4252 | ||
5b0f0db6 | 4253 | if (src_code == HIGH) |
c93c5160 | 4254 | return TARGET_MIPS16 ? "#" : "lui\t%0,%h1"; |
5b0f0db6 | 4255 | |
108b61d5 RS |
4256 | if (CONST_GP_P (src)) |
4257 | return "move\t%0,%1"; | |
7dac2f89 | 4258 | |
c93c5160 RS |
4259 | if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type) |
4260 | && mips_lo_relocs[symbol_type] != 0) | |
4261 | { | |
4262 | /* A signed 16-bit constant formed by applying a relocation | |
4263 | operator to a symbolic address. */ | |
4264 | gcc_assert (!mips_split_p[symbol_type]); | |
4265 | return "li\t%0,%R1"; | |
4266 | } | |
4267 | ||
108b61d5 | 4268 | if (symbolic_operand (src, VOIDmode)) |
c93c5160 RS |
4269 | { |
4270 | gcc_assert (TARGET_MIPS16 | |
4271 | ? TARGET_MIPS16_TEXT_LOADS | |
4272 | : !TARGET_EXPLICIT_RELOCS); | |
65239d20 | 4273 | return dbl_p ? "dla\t%0,%1" : "la\t%0,%1"; |
c93c5160 | 4274 | } |
cee98a59 | 4275 | } |
5b0f0db6 RS |
4276 | if (src_code == REG && FP_REG_P (REGNO (src))) |
4277 | { | |
4278 | if (dest_code == REG && FP_REG_P (REGNO (dest))) | |
06a4ab70 CF |
4279 | { |
4280 | if (GET_MODE (dest) == V2SFmode) | |
4281 | return "mov.ps\t%0,%1"; | |
4282 | else | |
65239d20 | 4283 | return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1"; |
06a4ab70 | 4284 | } |
cee98a59 | 4285 | |
5b0f0db6 | 4286 | if (dest_code == MEM) |
65239d20 | 4287 | return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0"; |
5b0f0db6 RS |
4288 | } |
4289 | if (dest_code == REG && FP_REG_P (REGNO (dest))) | |
cee98a59 | 4290 | { |
5b0f0db6 | 4291 | if (src_code == MEM) |
65239d20 | 4292 | return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1"; |
cee98a59 | 4293 | } |
5b0f0db6 RS |
4294 | if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM) |
4295 | { | |
4296 | static char retval[] = "l_c_\t%0,%1"; | |
cee98a59 | 4297 | |
5b0f0db6 RS |
4298 | retval[1] = (dbl_p ? 'd' : 'w'); |
4299 | retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest)); | |
4300 | return retval; | |
4301 | } | |
4302 | if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src))) | |
4303 | { | |
4304 | static char retval[] = "s_c_\t%1,%0"; | |
cee98a59 | 4305 | |
5b0f0db6 RS |
4306 | retval[1] = (dbl_p ? 'd' : 'w'); |
4307 | retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src)); | |
4308 | return retval; | |
4309 | } | |
7ad769fe | 4310 | gcc_unreachable (); |
cee98a59 | 4311 | } |
b2471838 | 4312 | \f |
65239d20 RS |
4313 | /* Return true if CMP1 is a suitable second operand for integer ordering |
4314 | test CODE. See also the *sCC patterns in mips.md. */ | |
34b650b3 | 4315 | |
a012718f | 4316 | static bool |
65239d20 | 4317 | mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1) |
a012718f RS |
4318 | { |
4319 | switch (code) | |
34b650b3 | 4320 | { |
a012718f RS |
4321 | case GT: |
4322 | case GTU: | |
4323 | return reg_or_0_operand (cmp1, VOIDmode); | |
34b650b3 | 4324 | |
a012718f RS |
4325 | case GE: |
4326 | case GEU: | |
4327 | return !TARGET_MIPS16 && cmp1 == const1_rtx; | |
34b650b3 | 4328 | |
a012718f RS |
4329 | case LT: |
4330 | case LTU: | |
4331 | return arith_operand (cmp1, VOIDmode); | |
34b650b3 | 4332 | |
a012718f RS |
4333 | case LE: |
4334 | return sle_operand (cmp1, VOIDmode); | |
34b650b3 | 4335 | |
a012718f RS |
4336 | case LEU: |
4337 | return sleu_operand (cmp1, VOIDmode); | |
34b650b3 | 4338 | |
a012718f | 4339 | default: |
7ad769fe | 4340 | gcc_unreachable (); |
34b650b3 | 4341 | } |
a012718f | 4342 | } |
34b650b3 | 4343 | |
65239d20 RS |
4344 | /* Return true if *CMP1 (of mode MODE) is a valid second operand for |
4345 | integer ordering test *CODE, or if an equivalent combination can | |
4346 | be formed by adjusting *CODE and *CMP1. When returning true, update | |
4347 | *CODE and *CMP1 with the chosen code and operand, otherwise leave | |
4348 | them alone. */ | |
ecd48505 EC |
4349 | |
4350 | static bool | |
65239d20 RS |
4351 | mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1, |
4352 | enum machine_mode mode) | |
ecd48505 | 4353 | { |
213ce6f2 | 4354 | HOST_WIDE_INT plus_one; |
ecd48505 | 4355 | |
65239d20 | 4356 | if (mips_int_order_operand_ok_p (*code, *cmp1)) |
213ce6f2 | 4357 | return true; |
d8934cf1 | 4358 | |
47ac44d6 | 4359 | if (CONST_INT_P (*cmp1)) |
213ce6f2 RS |
4360 | switch (*code) |
4361 | { | |
4362 | case LE: | |
4363 | plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); | |
4364 | if (INTVAL (*cmp1) < plus_one) | |
4365 | { | |
4366 | *code = LT; | |
4367 | *cmp1 = force_reg (mode, GEN_INT (plus_one)); | |
4368 | return true; | |
4369 | } | |
4370 | break; | |
4371 | ||
4372 | case LEU: | |
4373 | plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); | |
4374 | if (plus_one != 0) | |
4375 | { | |
4376 | *code = LTU; | |
4377 | *cmp1 = force_reg (mode, GEN_INT (plus_one)); | |
4378 | return true; | |
4379 | } | |
4380 | break; | |
4381 | ||
4382 | default: | |
4383 | break; | |
4384 | } | |
ecd48505 | 4385 | return false; |
ecd48505 EC |
4386 | } |
4387 | ||
65239d20 | 4388 | /* Compare CMP0 and CMP1 using ordering test CODE and store the result |
5fb79e4c AN |
4389 | in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR |
4390 | is nonnull, it's OK to set TARGET to the inverse of the result and | |
4391 | flip *INVERT_PTR instead. */ | |
f5963e61 | 4392 | |
a012718f | 4393 | static void |
65239d20 | 4394 | mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr, |
a012718f RS |
4395 | rtx target, rtx cmp0, rtx cmp1) |
4396 | { | |
65239d20 RS |
4397 | enum machine_mode mode; |
4398 | ||
213ce6f2 RS |
4399 | /* First see if there is a MIPS instruction that can do this operation. |
4400 | If not, try doing the same for the inverse operation. If that also | |
4401 | fails, force CMP1 into a register and try again. */ | |
5fb79e4c | 4402 | mode = GET_MODE (cmp0); |
65239d20 | 4403 | if (mips_canonicalize_int_order_test (&code, &cmp1, mode)) |
ecd48505 | 4404 | mips_emit_binary (code, target, cmp0, cmp1); |
bbdb5552 MM |
4405 | else |
4406 | { | |
a012718f | 4407 | enum rtx_code inv_code = reverse_condition (code); |
65239d20 | 4408 | if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode)) |
a012718f | 4409 | { |
65239d20 RS |
4410 | cmp1 = force_reg (mode, cmp1); |
4411 | mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1); | |
a012718f RS |
4412 | } |
4413 | else if (invert_ptr == 0) | |
2bcb2ab3 | 4414 | { |
49bce30a RS |
4415 | rtx inv_target; |
4416 | ||
4417 | inv_target = mips_force_binary (GET_MODE (target), | |
4418 | inv_code, cmp0, cmp1); | |
a012718f | 4419 | mips_emit_binary (XOR, target, inv_target, const1_rtx); |
2bcb2ab3 GK |
4420 | } |
4421 | else | |
4422 | { | |
a012718f RS |
4423 | *invert_ptr = !*invert_ptr; |
4424 | mips_emit_binary (inv_code, target, cmp0, cmp1); | |
2bcb2ab3 | 4425 | } |
34b650b3 | 4426 | } |
a012718f | 4427 | } |
34b650b3 | 4428 | |
a012718f RS |
4429 | /* Return a register that is zero iff CMP0 and CMP1 are equal. |
4430 | The register will have the same mode as CMP0. */ | |
34b650b3 | 4431 | |
a012718f RS |
4432 | static rtx |
4433 | mips_zero_if_equal (rtx cmp0, rtx cmp1) | |
4434 | { | |
4435 | if (cmp1 == const0_rtx) | |
4436 | return cmp0; | |
2bcb2ab3 | 4437 | |
f1286257 RS |
4438 | if (uns_arith_operand (cmp1, VOIDmode)) |
4439 | return expand_binop (GET_MODE (cmp0), xor_optab, | |
4440 | cmp0, cmp1, 0, 0, OPTAB_DIRECT); | |
4441 | ||
4442 | return expand_binop (GET_MODE (cmp0), sub_optab, | |
a012718f RS |
4443 | cmp0, cmp1, 0, 0, OPTAB_DIRECT); |
4444 | } | |
4445 | ||
ec4fc7ed | 4446 | /* Convert *CODE into a code that can be used in a floating-point |
65239d20 | 4447 | scc instruction (C.cond.fmt). Return true if the values of |
ec4fc7ed RS |
4448 | the condition code registers will be inverted, with 0 indicating |
4449 | that the condition holds. */ | |
4450 | ||
4451 | static bool | |
65239d20 | 4452 | mips_reversed_fp_cond (enum rtx_code *code) |
ec4fc7ed RS |
4453 | { |
4454 | switch (*code) | |
4455 | { | |
4456 | case NE: | |
4457 | case LTGT: | |
4458 | case ORDERED: | |
4459 | *code = reverse_condition_maybe_unordered (*code); | |
4460 | return true; | |
4461 | ||
4462 | default: | |
4463 | return false; | |
4464 | } | |
4465 | } | |
4466 | ||
bb592806 | 4467 | /* Convert a comparison into something that can be used in a branch or |
f90b7a5a PB |
4468 | conditional move. On entry, *OP0 and *OP1 are the values being |
4469 | compared and *CODE is the code used to compare them. | |
bb592806 RS |
4470 | |
4471 | Update *CODE, *OP0 and *OP1 so that they describe the final comparison. | |
65239d20 | 4472 | If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible, |
bb592806 RS |
4473 | otherwise any standard branch condition can be used. The standard branch |
4474 | conditions are: | |
4475 | ||
65239d20 | 4476 | - EQ or NE between two registers. |
bb592806 RS |
4477 | - any comparison between a register and zero. */ |
4478 | ||
4479 | static void | |
4480 | mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p) | |
4481 | { | |
f90b7a5a PB |
4482 | rtx cmp_op0 = *op0; |
4483 | rtx cmp_op1 = *op1; | |
4484 | ||
4485 | if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT) | |
bb592806 | 4486 | { |
f90b7a5a PB |
4487 | if (!need_eq_ne_p && *op1 == const0_rtx) |
4488 | ; | |
bb592806 RS |
4489 | else if (*code == EQ || *code == NE) |
4490 | { | |
4491 | if (need_eq_ne_p) | |
4492 | { | |
f90b7a5a | 4493 | *op0 = mips_zero_if_equal (cmp_op0, cmp_op1); |
bb592806 RS |
4494 | *op1 = const0_rtx; |
4495 | } | |
4496 | else | |
f90b7a5a | 4497 | *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1); |
bb592806 RS |
4498 | } |
4499 | else | |
4500 | { | |
4501 | /* The comparison needs a separate scc instruction. Store the | |
4502 | result of the scc in *OP0 and compare it against zero. */ | |
4503 | bool invert = false; | |
f90b7a5a PB |
4504 | *op0 = gen_reg_rtx (GET_MODE (cmp_op0)); |
4505 | mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1); | |
bb592806 | 4506 | *code = (invert ? EQ : NE); |
65239d20 | 4507 | *op1 = const0_rtx; |
bb592806 RS |
4508 | } |
4509 | } | |
f90b7a5a | 4510 | else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0))) |
9fc777ad CF |
4511 | { |
4512 | *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM); | |
f90b7a5a | 4513 | mips_emit_binary (*code, *op0, cmp_op0, cmp_op1); |
9fc777ad CF |
4514 | *code = NE; |
4515 | *op1 = const0_rtx; | |
4516 | } | |
bb592806 RS |
4517 | else |
4518 | { | |
4519 | enum rtx_code cmp_code; | |
4520 | ||
65239d20 | 4521 | /* Floating-point tests use a separate C.cond.fmt comparison to |
bb592806 RS |
4522 | set a condition code register. The branch or conditional move |
4523 | will then compare that register against zero. | |
4524 | ||
4525 | Set CMP_CODE to the code of the comparison instruction and | |
4526 | *CODE to the code that the branch or move should use. */ | |
ec4fc7ed | 4527 | cmp_code = *code; |
65239d20 | 4528 | *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE; |
bb592806 RS |
4529 | *op0 = (ISA_HAS_8CC |
4530 | ? gen_reg_rtx (CCmode) | |
4531 | : gen_rtx_REG (CCmode, FPSW_REGNUM)); | |
4532 | *op1 = const0_rtx; | |
f90b7a5a | 4533 | mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1); |
bb592806 RS |
4534 | } |
4535 | } | |
4536 | \f | |
f90b7a5a PB |
4537 | /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2] |
4538 | and OPERAND[3]. Store the result in OPERANDS[0]. | |
a012718f | 4539 | |
f90b7a5a PB |
4540 | On 64-bit targets, the mode of the comparison and target will always be |
4541 | SImode, thus possibly narrower than that of the comparison's operands. */ | |
34b650b3 | 4542 | |
f90b7a5a PB |
4543 | void |
4544 | mips_expand_scc (rtx operands[]) | |
a012718f | 4545 | { |
f90b7a5a PB |
4546 | rtx target = operands[0]; |
4547 | enum rtx_code code = GET_CODE (operands[1]); | |
4548 | rtx op0 = operands[2]; | |
4549 | rtx op1 = operands[3]; | |
4550 | ||
4551 | gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT); | |
a012718f | 4552 | |
a012718f RS |
4553 | if (code == EQ || code == NE) |
4554 | { | |
5299815b | 4555 | if (ISA_HAS_SEQ_SNE |
f90b7a5a PB |
4556 | && reg_imm10_operand (op1, GET_MODE (op1))) |
4557 | mips_emit_binary (code, target, op0, op1); | |
5299815b AN |
4558 | else |
4559 | { | |
f90b7a5a | 4560 | rtx zie = mips_zero_if_equal (op0, op1); |
5299815b AN |
4561 | mips_emit_binary (code, target, zie, const0_rtx); |
4562 | } | |
a012718f RS |
4563 | } |
4564 | else | |
f90b7a5a | 4565 | mips_emit_int_order_test (code, 0, target, op0, op1); |
34b650b3 | 4566 | } |
8ab907e8 | 4567 | |
f90b7a5a PB |
4568 | /* Compare OPERANDS[1] with OPERANDS[2] using comparison code |
4569 | CODE and jump to OPERANDS[3] if the condition holds. */ | |
cee98a59 MM |
4570 | |
4571 | void | |
f90b7a5a | 4572 | mips_expand_conditional_branch (rtx *operands) |
cee98a59 | 4573 | { |
f90b7a5a PB |
4574 | enum rtx_code code = GET_CODE (operands[0]); |
4575 | rtx op0 = operands[1]; | |
4576 | rtx op1 = operands[2]; | |
4577 | rtx condition; | |
f5963e61 | 4578 | |
bb592806 | 4579 | mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16); |
a8c1d5f8 | 4580 | condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); |
f90b7a5a | 4581 | emit_jump_insn (gen_condjump (condition, operands[3])); |
b8eb88d0 | 4582 | } |
34b650b3 | 4583 | |
ec4fc7ed RS |
4584 | /* Implement: |
4585 | ||
4586 | (set temp (COND:CCV2 CMP_OP0 CMP_OP1)) | |
4587 | (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */ | |
4588 | ||
4589 | void | |
4590 | mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src, | |
4591 | enum rtx_code cond, rtx cmp_op0, rtx cmp_op1) | |
4592 | { | |
4593 | rtx cmp_result; | |
4594 | bool reversed_p; | |
4595 | ||
65239d20 | 4596 | reversed_p = mips_reversed_fp_cond (&cond); |
ec4fc7ed RS |
4597 | cmp_result = gen_reg_rtx (CCV2mode); |
4598 | emit_insn (gen_scc_ps (cmp_result, | |
4599 | gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1))); | |
4600 | if (reversed_p) | |
4601 | emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src, | |
4602 | cmp_result)); | |
4603 | else | |
4604 | emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src, | |
4605 | cmp_result)); | |
4606 | } | |
4607 | ||
f90b7a5a PB |
4608 | /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0] |
4609 | if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */ | |
cee98a59 | 4610 | |
b8eb88d0 | 4611 | void |
65239d20 | 4612 | mips_expand_conditional_move (rtx *operands) |
b8eb88d0 | 4613 | { |
f90b7a5a PB |
4614 | rtx cond; |
4615 | enum rtx_code code = GET_CODE (operands[1]); | |
4616 | rtx op0 = XEXP (operands[1], 0); | |
4617 | rtx op1 = XEXP (operands[1], 1); | |
c5c76735 | 4618 | |
bb592806 | 4619 | mips_emit_compare (&code, &op0, &op1, true); |
f90b7a5a | 4620 | cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); |
bb592806 | 4621 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], |
65239d20 | 4622 | gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond, |
c5c76735 | 4623 | operands[2], operands[3]))); |
b8eb88d0 | 4624 | } |
a0b6cdee | 4625 | |
f90b7a5a | 4626 | /* Perform the comparison in COMPARISON, then trap if the condition holds. */ |
a0b6cdee GM |
4627 | |
4628 | void | |
f90b7a5a | 4629 | mips_expand_conditional_trap (rtx comparison) |
a0b6cdee GM |
4630 | { |
4631 | rtx op0, op1; | |
65239d20 | 4632 | enum machine_mode mode; |
f90b7a5a | 4633 | enum rtx_code code; |
a0b6cdee | 4634 | |
65239d20 RS |
4635 | /* MIPS conditional trap instructions don't have GT or LE flavors, |
4636 | so we must swap the operands and convert to LT and GE respectively. */ | |
f90b7a5a | 4637 | code = GET_CODE (comparison); |
65239d20 | 4638 | switch (code) |
a0b6cdee | 4639 | { |
65239d20 RS |
4640 | case GT: |
4641 | case LE: | |
4642 | case GTU: | |
4643 | case LEU: | |
4644 | code = swap_condition (code); | |
f90b7a5a PB |
4645 | op0 = XEXP (comparison, 1); |
4646 | op1 = XEXP (comparison, 0); | |
65239d20 RS |
4647 | break; |
4648 | ||
4649 | default: | |
f90b7a5a PB |
4650 | op0 = XEXP (comparison, 0); |
4651 | op1 = XEXP (comparison, 1); | |
65239d20 | 4652 | break; |
a0b6cdee | 4653 | } |
65239d20 | 4654 | |
f90b7a5a | 4655 | mode = GET_MODE (XEXP (comparison, 0)); |
886ce862 RS |
4656 | op0 = force_reg (mode, op0); |
4657 | if (!arith_operand (op1, mode)) | |
a0b6cdee GM |
4658 | op1 = force_reg (mode, op1); |
4659 | ||
4660 | emit_insn (gen_rtx_TRAP_IF (VOIDmode, | |
65239d20 RS |
4661 | gen_rtx_fmt_ee (code, mode, op0, op1), |
4662 | const0_rtx)); | |
a0b6cdee | 4663 | } |
cee98a59 | 4664 | \f |
65239d20 | 4665 | /* Initialize *CUM for a call to a function of type FNTYPE. */ |
ab77a036 RS |
4666 | |
4667 | void | |
65239d20 | 4668 | mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype) |
9a6dfb47 | 4669 | { |
65239d20 RS |
4670 | memset (cum, 0, sizeof (*cum)); |
4671 | cum->prototype = (fntype && prototype_p (fntype)); | |
4672 | cum->gp_reg_found = (cum->prototype && stdarg_p (fntype)); | |
9a6dfb47 RS |
4673 | } |
4674 | ||
ab77a036 RS |
4675 | /* Fill INFO with information about a single argument. CUM is the |
4676 | cumulative state for earlier arguments. MODE is the mode of this | |
4677 | argument and TYPE is its type (if known). NAMED is true if this | |
4678 | is a named (fixed) argument rather than a variable one. */ | |
4679 | ||
4680 | static void | |
65239d20 RS |
4681 | mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum, |
4682 | enum machine_mode mode, tree type, int named) | |
08e7ceb3 | 4683 | { |
ab77a036 RS |
4684 | bool doubleword_aligned_p; |
4685 | unsigned int num_bytes, num_words, max_regs; | |
08e7ceb3 | 4686 | |
ab77a036 RS |
4687 | /* Work out the size of the argument. */ |
4688 | num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); | |
4689 | num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
b85aed9e | 4690 | |
ab77a036 RS |
4691 | /* Decide whether it should go in a floating-point register, assuming |
4692 | one is free. Later code checks for availability. | |
b85aed9e | 4693 | |
ab77a036 RS |
4694 | The checks against UNITS_PER_FPVALUE handle the soft-float and |
4695 | single-float cases. */ | |
4696 | switch (mips_abi) | |
e8b7a137 | 4697 | { |
ab77a036 RS |
4698 | case ABI_EABI: |
4699 | /* The EABI conventions have traditionally been defined in terms | |
4700 | of TYPE_MODE, regardless of the actual type. */ | |
4701 | info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT | |
4702 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
4703 | && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); | |
4704 | break; | |
b85aed9e | 4705 | |
ab77a036 RS |
4706 | case ABI_32: |
4707 | case ABI_O64: | |
4708 | /* Only leading floating-point scalars are passed in | |
4709 | floating-point registers. We also handle vector floats the same | |
4710 | say, which is OK because they are not covered by the standard ABI. */ | |
4711 | info->fpr_p = (!cum->gp_reg_found | |
4712 | && cum->arg_number < 2 | |
65239d20 RS |
4713 | && (type == 0 |
4714 | || SCALAR_FLOAT_TYPE_P (type) | |
ab77a036 RS |
4715 | || VECTOR_FLOAT_TYPE_P (type)) |
4716 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4717 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
4718 | && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE); | |
4719 | break; | |
cafe096b | 4720 | |
ab77a036 RS |
4721 | case ABI_N32: |
4722 | case ABI_64: | |
65239d20 RS |
4723 | /* Scalar, complex and vector floating-point types are passed in |
4724 | floating-point registers, as long as this is a named rather | |
4725 | than a variable argument. */ | |
ab77a036 RS |
4726 | info->fpr_p = (named |
4727 | && (type == 0 || FLOAT_TYPE_P (type)) | |
4728 | && (GET_MODE_CLASS (mode) == MODE_FLOAT | |
4729 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
4730 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT) | |
4731 | && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE); | |
3c53850d | 4732 | |
ab77a036 RS |
4733 | /* ??? According to the ABI documentation, the real and imaginary |
4734 | parts of complex floats should be passed in individual registers. | |
4735 | The real and imaginary parts of stack arguments are supposed | |
4736 | to be contiguous and there should be an extra word of padding | |
4737 | at the end. | |
cafe096b | 4738 | |
ab77a036 RS |
4739 | This has two problems. First, it makes it impossible to use a |
4740 | single "void *" va_list type, since register and stack arguments | |
4741 | are passed differently. (At the time of writing, MIPSpro cannot | |
4742 | handle complex float varargs correctly.) Second, it's unclear | |
4743 | what should happen when there is only one register free. | |
3c53850d | 4744 | |
ab77a036 RS |
4745 | For now, we assume that named complex floats should go into FPRs |
4746 | if there are two FPRs free, otherwise they should be passed in the | |
4747 | same way as a struct containing two floats. */ | |
4748 | if (info->fpr_p | |
4749 | && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT | |
4750 | && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE) | |
4751 | { | |
4752 | if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1) | |
4753 | info->fpr_p = false; | |
4754 | else | |
4755 | num_words = 2; | |
4756 | } | |
4757 | break; | |
cafe096b | 4758 | |
ab77a036 RS |
4759 | default: |
4760 | gcc_unreachable (); | |
cafe096b | 4761 | } |
3c53850d | 4762 | |
ab77a036 RS |
4763 | /* See whether the argument has doubleword alignment. */ |
4764 | doubleword_aligned_p = FUNCTION_ARG_BOUNDARY (mode, type) > BITS_PER_WORD; | |
3c53850d | 4765 | |
ab77a036 RS |
4766 | /* Set REG_OFFSET to the register count we're interested in. |
4767 | The EABI allocates the floating-point registers separately, | |
4768 | but the other ABIs allocate them like integer registers. */ | |
4769 | info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p | |
4770 | ? cum->num_fprs | |
4771 | : cum->num_gprs); | |
cafe096b | 4772 | |
ab77a036 RS |
4773 | /* Advance to an even register if the argument is doubleword-aligned. */ |
4774 | if (doubleword_aligned_p) | |
4775 | info->reg_offset += info->reg_offset & 1; | |
cafe096b | 4776 | |
ab77a036 RS |
4777 | /* Work out the offset of a stack argument. */ |
4778 | info->stack_offset = cum->stack_words; | |
4779 | if (doubleword_aligned_p) | |
4780 | info->stack_offset += info->stack_offset & 1; | |
cafe096b | 4781 | |
ab77a036 | 4782 | max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset; |
f9e4a411 | 4783 | |
ab77a036 RS |
4784 | /* Partition the argument between registers and stack. */ |
4785 | info->reg_words = MIN (num_words, max_regs); | |
4786 | info->stack_words = num_words - info->reg_words; | |
4787 | } | |
f9e4a411 | 4788 | |
65239d20 RS |
4789 | /* INFO describes a register argument that has the normal format for the |
4790 | argument's mode. Return the register it uses, assuming that FPRs are | |
4791 | available if HARD_FLOAT_P. */ | |
1ec3b87b | 4792 | |
ab77a036 RS |
4793 | static unsigned int |
4794 | mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p) | |
4795 | { | |
4796 | if (!info->fpr_p || !hard_float_p) | |
4797 | return GP_ARG_FIRST + info->reg_offset; | |
4798 | else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0) | |
4799 | /* In o32, the second argument is always passed in $f14 | |
4800 | for TARGET_DOUBLE_FLOAT, regardless of whether the | |
4801 | first argument was a word or doubleword. */ | |
4802 | return FP_ARG_FIRST + 2; | |
4803 | else | |
4804 | return FP_ARG_FIRST + info->reg_offset; | |
cafe096b | 4805 | } |
d12b8c85 | 4806 | |
65239d20 RS |
4807 | /* Implement TARGET_STRICT_ARGUMENT_NAMING. */ |
4808 | ||
ab77a036 RS |
4809 | static bool |
4810 | mips_strict_argument_naming (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED) | |
4811 | { | |
4812 | return !TARGET_OLDABI; | |
4813 | } | |
d12b8c85 | 4814 | |
ab77a036 | 4815 | /* Implement FUNCTION_ARG. */ |
d12b8c85 | 4816 | |
65239d20 RS |
4817 | rtx |
4818 | mips_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
4819 | tree type, int named) | |
d12b8c85 | 4820 | { |
ab77a036 | 4821 | struct mips_arg_info info; |
d12b8c85 | 4822 | |
ab77a036 | 4823 | /* We will be called with a mode of VOIDmode after the last argument |
65239d20 RS |
4824 | has been seen. Whatever we return will be passed to the call expander. |
4825 | If we need a MIPS16 fp_code, return a REG with the code stored as | |
4826 | the mode. */ | |
ab77a036 RS |
4827 | if (mode == VOIDmode) |
4828 | { | |
4829 | if (TARGET_MIPS16 && cum->fp_code != 0) | |
4830 | return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0); | |
ab77a036 | 4831 | else |
65239d20 | 4832 | return NULL; |
ab77a036 | 4833 | } |
d12b8c85 | 4834 | |
65239d20 | 4835 | mips_get_arg_info (&info, cum, mode, type, named); |
b2471838 | 4836 | |
ab77a036 RS |
4837 | /* Return straight away if the whole argument is passed on the stack. */ |
4838 | if (info.reg_offset == MAX_ARGS_IN_REGISTERS) | |
65239d20 | 4839 | return NULL; |
b2471838 | 4840 | |
65239d20 RS |
4841 | /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure |
4842 | contains a double in its entirety, then that 64-bit chunk is passed | |
4843 | in a floating-point register. */ | |
4844 | if (TARGET_NEWABI | |
4845 | && TARGET_HARD_FLOAT | |
4846 | && named | |
4847 | && type != 0 | |
ab77a036 | 4848 | && TREE_CODE (type) == RECORD_TYPE |
ab77a036 | 4849 | && TYPE_SIZE_UNIT (type) |
65239d20 | 4850 | && host_integerp (TYPE_SIZE_UNIT (type), 1)) |
ab77a036 | 4851 | { |
ab77a036 | 4852 | tree field; |
b2471838 | 4853 | |
ab77a036 RS |
4854 | /* First check to see if there is any such field. */ |
4855 | for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) | |
4856 | if (TREE_CODE (field) == FIELD_DECL | |
65239d20 | 4857 | && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) |
ab77a036 RS |
4858 | && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD |
4859 | && host_integerp (bit_position (field), 0) | |
4860 | && int_bit_position (field) % BITS_PER_WORD == 0) | |
4861 | break; | |
cee98a59 | 4862 | |
ab77a036 RS |
4863 | if (field != 0) |
4864 | { | |
4865 | /* Now handle the special case by returning a PARALLEL | |
4866 | indicating where each 64-bit chunk goes. INFO.REG_WORDS | |
4867 | chunks are passed in registers. */ | |
4868 | unsigned int i; | |
4869 | HOST_WIDE_INT bitpos; | |
4870 | rtx ret; | |
730cf822 | 4871 | |
ab77a036 RS |
4872 | /* assign_parms checks the mode of ENTRY_PARM, so we must |
4873 | use the actual mode here. */ | |
4874 | ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words)); | |
cee98a59 | 4875 | |
ab77a036 RS |
4876 | bitpos = 0; |
4877 | field = TYPE_FIELDS (type); | |
4878 | for (i = 0; i < info.reg_words; i++) | |
4879 | { | |
4880 | rtx reg; | |
cee98a59 | 4881 | |
ab77a036 RS |
4882 | for (; field; field = TREE_CHAIN (field)) |
4883 | if (TREE_CODE (field) == FIELD_DECL | |
4884 | && int_bit_position (field) >= bitpos) | |
4885 | break; | |
cee98a59 | 4886 | |
ab77a036 RS |
4887 | if (field |
4888 | && int_bit_position (field) == bitpos | |
65239d20 | 4889 | && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)) |
ab77a036 RS |
4890 | && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD) |
4891 | reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i); | |
4892 | else | |
4893 | reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i); | |
4894 | ||
4895 | XVECEXP (ret, 0, i) | |
4896 | = gen_rtx_EXPR_LIST (VOIDmode, reg, | |
4897 | GEN_INT (bitpos / BITS_PER_UNIT)); | |
4898 | ||
4899 | bitpos += BITS_PER_WORD; | |
4900 | } | |
4901 | return ret; | |
4902 | } | |
4903 | } | |
4904 | ||
4905 | /* Handle the n32/n64 conventions for passing complex floating-point | |
4906 | arguments in FPR pairs. The real part goes in the lower register | |
4907 | and the imaginary part goes in the upper register. */ | |
4908 | if (TARGET_NEWABI | |
4909 | && info.fpr_p | |
4910 | && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
cee98a59 | 4911 | { |
ab77a036 RS |
4912 | rtx real, imag; |
4913 | enum machine_mode inner; | |
65239d20 | 4914 | unsigned int regno; |
ab77a036 RS |
4915 | |
4916 | inner = GET_MODE_INNER (mode); | |
65239d20 | 4917 | regno = FP_ARG_FIRST + info.reg_offset; |
ab77a036 RS |
4918 | if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner)) |
4919 | { | |
4920 | /* Real part in registers, imaginary part on stack. */ | |
4921 | gcc_assert (info.stack_words == info.reg_words); | |
65239d20 | 4922 | return gen_rtx_REG (inner, regno); |
ab77a036 | 4923 | } |
e0ec4c3b RS |
4924 | else |
4925 | { | |
ab77a036 RS |
4926 | gcc_assert (info.stack_words == 0); |
4927 | real = gen_rtx_EXPR_LIST (VOIDmode, | |
65239d20 | 4928 | gen_rtx_REG (inner, regno), |
ab77a036 RS |
4929 | const0_rtx); |
4930 | imag = gen_rtx_EXPR_LIST (VOIDmode, | |
4931 | gen_rtx_REG (inner, | |
65239d20 | 4932 | regno + info.reg_words / 2), |
ab77a036 RS |
4933 | GEN_INT (GET_MODE_SIZE (inner))); |
4934 | return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag)); | |
e0ec4c3b | 4935 | } |
730cf822 | 4936 | } |
f5963e61 | 4937 | |
ab77a036 | 4938 | return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT)); |
cee98a59 | 4939 | } |
cee98a59 | 4940 | |
ab77a036 | 4941 | /* Implement FUNCTION_ARG_ADVANCE. */ |
cee98a59 | 4942 | |
ab77a036 | 4943 | void |
65239d20 RS |
4944 | mips_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
4945 | tree type, int named) | |
842eb20e | 4946 | { |
ab77a036 | 4947 | struct mips_arg_info info; |
842eb20e | 4948 | |
65239d20 | 4949 | mips_get_arg_info (&info, cum, mode, type, named); |
842eb20e | 4950 | |
ab77a036 RS |
4951 | if (!info.fpr_p) |
4952 | cum->gp_reg_found = true; | |
910628b8 | 4953 | |
65239d20 RS |
4954 | /* See the comment above the CUMULATIVE_ARGS structure in mips.h for |
4955 | an explanation of what this code does. It assumes that we're using | |
4956 | either the o32 or the o64 ABI, both of which pass at most 2 arguments | |
4957 | in FPRs. */ | |
ab77a036 RS |
4958 | if (cum->arg_number < 2 && info.fpr_p) |
4959 | cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2); | |
910628b8 | 4960 | |
65239d20 RS |
4961 | /* Advance the register count. This has the effect of setting |
4962 | num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned | |
4963 | argument required us to skip the final GPR and pass the whole | |
4964 | argument on the stack. */ | |
ab77a036 RS |
4965 | if (mips_abi != ABI_EABI || !info.fpr_p) |
4966 | cum->num_gprs = info.reg_offset + info.reg_words; | |
4967 | else if (info.reg_words > 0) | |
4968 | cum->num_fprs += MAX_FPRS_PER_FMT; | |
910628b8 | 4969 | |
65239d20 | 4970 | /* Advance the stack word count. */ |
ab77a036 RS |
4971 | if (info.stack_words > 0) |
4972 | cum->stack_words = info.stack_offset + info.stack_words; | |
842eb20e | 4973 | |
ab77a036 RS |
4974 | cum->arg_number++; |
4975 | } | |
842eb20e | 4976 | |
ab77a036 | 4977 | /* Implement TARGET_ARG_PARTIAL_BYTES. */ |
842eb20e | 4978 | |
ab77a036 RS |
4979 | static int |
4980 | mips_arg_partial_bytes (CUMULATIVE_ARGS *cum, | |
4981 | enum machine_mode mode, tree type, bool named) | |
4982 | { | |
4983 | struct mips_arg_info info; | |
f5963e61 | 4984 | |
65239d20 | 4985 | mips_get_arg_info (&info, cum, mode, type, named); |
ab77a036 RS |
4986 | return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0; |
4987 | } | |
147255d8 | 4988 | |
ab77a036 RS |
4989 | /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least |
4990 | PARM_BOUNDARY bits of alignment, but will be given anything up | |
4991 | to STACK_BOUNDARY bits if the type requires it. */ | |
f5963e61 | 4992 | |
ab77a036 | 4993 | int |
65239d20 | 4994 | mips_function_arg_boundary (enum machine_mode mode, tree type) |
ab77a036 RS |
4995 | { |
4996 | unsigned int alignment; | |
4997 | ||
4998 | alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); | |
4999 | if (alignment < PARM_BOUNDARY) | |
5000 | alignment = PARM_BOUNDARY; | |
5001 | if (alignment > STACK_BOUNDARY) | |
5002 | alignment = STACK_BOUNDARY; | |
5003 | return alignment; | |
730cf822 | 5004 | } |
df770e04 | 5005 | |
ab77a036 RS |
5006 | /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return |
5007 | upward rather than downward. In other words, return true if the | |
5008 | first byte of the stack slot has useful data, false if the last | |
5009 | byte does. */ | |
df770e04 | 5010 | |
ab77a036 RS |
5011 | bool |
5012 | mips_pad_arg_upward (enum machine_mode mode, const_tree type) | |
df770e04 | 5013 | { |
ab77a036 RS |
5014 | /* On little-endian targets, the first byte of every stack argument |
5015 | is passed in the first byte of the stack slot. */ | |
5016 | if (!BYTES_BIG_ENDIAN) | |
5017 | return true; | |
df770e04 | 5018 | |
ab77a036 RS |
5019 | /* Otherwise, integral types are padded downward: the last byte of a |
5020 | stack argument is passed in the last byte of the stack slot. */ | |
5021 | if (type != 0 | |
5022 | ? (INTEGRAL_TYPE_P (type) | |
5023 | || POINTER_TYPE_P (type) | |
5024 | || FIXED_POINT_TYPE_P (type)) | |
65239d20 | 5025 | : (SCALAR_INT_MODE_P (mode) |
ab77a036 RS |
5026 | || ALL_SCALAR_FIXED_POINT_MODE_P (mode))) |
5027 | return false; | |
df770e04 | 5028 | |
ab77a036 RS |
5029 | /* Big-endian o64 pads floating-point arguments downward. */ |
5030 | if (mips_abi == ABI_O64) | |
5031 | if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5032 | return false; | |
df770e04 | 5033 | |
ab77a036 RS |
5034 | /* Other types are padded upward for o32, o64, n32 and n64. */ |
5035 | if (mips_abi != ABI_EABI) | |
5036 | return true; | |
df770e04 | 5037 | |
ab77a036 RS |
5038 | /* Arguments smaller than a stack slot are padded downward. */ |
5039 | if (mode != BLKmode) | |
65239d20 | 5040 | return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY; |
ab77a036 | 5041 | else |
65239d20 | 5042 | return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT); |
ab77a036 | 5043 | } |
df770e04 | 5044 | |
ab77a036 RS |
5045 | /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN |
5046 | if the least significant byte of the register has useful data. Return | |
5047 | the opposite if the most significant byte does. */ | |
0cebb05d | 5048 | |
730cf822 | 5049 | bool |
ab77a036 | 5050 | mips_pad_reg_upward (enum machine_mode mode, tree type) |
730cf822 | 5051 | { |
ab77a036 RS |
5052 | /* No shifting is required for floating-point arguments. */ |
5053 | if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5054 | return !BYTES_BIG_ENDIAN; | |
5055 | ||
5056 | /* Otherwise, apply the same padding to register arguments as we do | |
5057 | to stack arguments. */ | |
5058 | return mips_pad_arg_upward (mode, type); | |
842eb20e | 5059 | } |
cee98a59 | 5060 | |
ab77a036 | 5061 | /* Return nonzero when an argument must be passed by reference. */ |
cee98a59 | 5062 | |
ab77a036 RS |
5063 | static bool |
5064 | mips_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
5065 | enum machine_mode mode, const_tree type, | |
5066 | bool named ATTRIBUTE_UNUSED) | |
5067 | { | |
5068 | if (mips_abi == ABI_EABI) | |
5069 | { | |
5070 | int size; | |
cee98a59 | 5071 | |
ab77a036 RS |
5072 | /* ??? How should SCmode be handled? */ |
5073 | if (mode == DImode || mode == DFmode | |
5074 | || mode == DQmode || mode == UDQmode | |
5075 | || mode == DAmode || mode == UDAmode) | |
5076 | return 0; | |
cee98a59 | 5077 | |
ab77a036 RS |
5078 | size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); |
5079 | return size == -1 || size > UNITS_PER_WORD; | |
5080 | } | |
5081 | else | |
cee98a59 | 5082 | { |
ab77a036 RS |
5083 | /* If we have a variable-sized parameter, we have no choice. */ |
5084 | return targetm.calls.must_pass_in_stack (mode, type); | |
cee98a59 | 5085 | } |
cee98a59 MM |
5086 | } |
5087 | ||
65239d20 RS |
5088 | /* Implement TARGET_CALLEE_COPIES. */ |
5089 | ||
ab77a036 RS |
5090 | static bool |
5091 | mips_callee_copies (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, | |
5092 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
5093 | const_tree type ATTRIBUTE_UNUSED, bool named) | |
5094 | { | |
5095 | return mips_abi == ABI_EABI && named; | |
5096 | } | |
5097 | \f | |
5098 | /* See whether VALTYPE is a record whose fields should be returned in | |
5099 | floating-point registers. If so, return the number of fields and | |
5100 | list them in FIELDS (which should have two elements). Return 0 | |
5101 | otherwise. | |
b4966b1b | 5102 | |
ab77a036 RS |
5103 | For n32 & n64, a structure with one or two fields is returned in |
5104 | floating-point registers as long as every field has a floating-point | |
5105 | type. */ | |
b4966b1b | 5106 | |
ab77a036 RS |
5107 | static int |
5108 | mips_fpr_return_fields (const_tree valtype, tree *fields) | |
4d72536e | 5109 | { |
ab77a036 RS |
5110 | tree field; |
5111 | int i; | |
4d72536e | 5112 | |
ab77a036 RS |
5113 | if (!TARGET_NEWABI) |
5114 | return 0; | |
4d72536e | 5115 | |
ab77a036 RS |
5116 | if (TREE_CODE (valtype) != RECORD_TYPE) |
5117 | return 0; | |
4d72536e | 5118 | |
ab77a036 RS |
5119 | i = 0; |
5120 | for (field = TYPE_FIELDS (valtype); field != 0; field = TREE_CHAIN (field)) | |
ae043003 | 5121 | { |
ab77a036 RS |
5122 | if (TREE_CODE (field) != FIELD_DECL) |
5123 | continue; | |
ae043003 | 5124 | |
a3d97724 | 5125 | if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))) |
ab77a036 | 5126 | return 0; |
ae043003 | 5127 | |
ab77a036 RS |
5128 | if (i == 2) |
5129 | return 0; | |
ae043003 | 5130 | |
ab77a036 RS |
5131 | fields[i++] = field; |
5132 | } | |
5133 | return i; | |
5134 | } | |
ae043003 | 5135 | |
ab77a036 RS |
5136 | /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return |
5137 | a value in the most significant part of $2/$3 if: | |
ae043003 | 5138 | |
ab77a036 | 5139 | - the target is big-endian; |
ae043003 | 5140 | |
ab77a036 RS |
5141 | - the value has a structure or union type (we generalize this to |
5142 | cover aggregates from other languages too); and | |
4d72536e | 5143 | |
ab77a036 | 5144 | - the structure is not returned in floating-point registers. */ |
4d72536e | 5145 | |
ab77a036 RS |
5146 | static bool |
5147 | mips_return_in_msb (const_tree valtype) | |
5148 | { | |
5149 | tree fields[2]; | |
4d72536e | 5150 | |
ab77a036 RS |
5151 | return (TARGET_NEWABI |
5152 | && TARGET_BIG_ENDIAN | |
5153 | && AGGREGATE_TYPE_P (valtype) | |
5154 | && mips_fpr_return_fields (valtype, fields) == 0); | |
4d72536e RS |
5155 | } |
5156 | ||
ab77a036 RS |
5157 | /* Return true if the function return value MODE will get returned in a |
5158 | floating-point register. */ | |
a38e0142 | 5159 | |
ab77a036 RS |
5160 | static bool |
5161 | mips_return_mode_in_fpr_p (enum machine_mode mode) | |
a38e0142 | 5162 | { |
ab77a036 RS |
5163 | return ((GET_MODE_CLASS (mode) == MODE_FLOAT |
5164 | || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT | |
5165 | || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
5166 | && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE); | |
a38e0142 SL |
5167 | } |
5168 | ||
fd0d4c1f RS |
5169 | /* Return the representation of an FPR return register when the |
5170 | value being returned in FP_RETURN has mode VALUE_MODE and the | |
5171 | return type itself has mode TYPE_MODE. On NewABI targets, | |
5172 | the two modes may be different for structures like: | |
5173 | ||
5174 | struct __attribute__((packed)) foo { float f; } | |
5175 | ||
5176 | where we return the SFmode value of "f" in FP_RETURN, but where | |
5177 | the structure itself has mode BLKmode. */ | |
5178 | ||
5179 | static rtx | |
5180 | mips_return_fpr_single (enum machine_mode type_mode, | |
5181 | enum machine_mode value_mode) | |
5182 | { | |
5183 | rtx x; | |
5184 | ||
5185 | x = gen_rtx_REG (value_mode, FP_RETURN); | |
5186 | if (type_mode != value_mode) | |
5187 | { | |
5188 | x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx); | |
5189 | x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x)); | |
5190 | } | |
5191 | return x; | |
5192 | } | |
5193 | ||
ab77a036 RS |
5194 | /* Return a composite value in a pair of floating-point registers. |
5195 | MODE1 and OFFSET1 are the mode and byte offset for the first value, | |
5196 | likewise MODE2 and OFFSET2 for the second. MODE is the mode of the | |
5197 | complete value. | |
cee98a59 | 5198 | |
ab77a036 RS |
5199 | For n32 & n64, $f0 always holds the first value and $f2 the second. |
5200 | Otherwise the values are packed together as closely as possible. */ | |
cee98a59 | 5201 | |
ab77a036 RS |
5202 | static rtx |
5203 | mips_return_fpr_pair (enum machine_mode mode, | |
5204 | enum machine_mode mode1, HOST_WIDE_INT offset1, | |
5205 | enum machine_mode mode2, HOST_WIDE_INT offset2) | |
5206 | { | |
5207 | int inc; | |
cee98a59 | 5208 | |
ab77a036 RS |
5209 | inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT); |
5210 | return gen_rtx_PARALLEL | |
5211 | (mode, | |
5212 | gen_rtvec (2, | |
5213 | gen_rtx_EXPR_LIST (VOIDmode, | |
5214 | gen_rtx_REG (mode1, FP_RETURN), | |
5215 | GEN_INT (offset1)), | |
5216 | gen_rtx_EXPR_LIST (VOIDmode, | |
5217 | gen_rtx_REG (mode2, FP_RETURN + inc), | |
5218 | GEN_INT (offset2)))); | |
cee98a59 | 5219 | |
cee98a59 MM |
5220 | } |
5221 | ||
ab77a036 RS |
5222 | /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls, |
5223 | VALTYPE is the return type and MODE is VOIDmode. For libcalls, | |
5224 | VALTYPE is null and MODE is the mode of the return value. */ | |
cee98a59 | 5225 | |
ab77a036 | 5226 | rtx |
cde0f3fd | 5227 | mips_function_value (const_tree valtype, const_tree func, enum machine_mode mode) |
ab77a036 RS |
5228 | { |
5229 | if (valtype) | |
cee98a59 | 5230 | { |
ab77a036 | 5231 | tree fields[2]; |
65239d20 | 5232 | int unsigned_p; |
cee98a59 | 5233 | |
ab77a036 | 5234 | mode = TYPE_MODE (valtype); |
65239d20 | 5235 | unsigned_p = TYPE_UNSIGNED (valtype); |
4d72536e | 5236 | |
cde0f3fd PB |
5237 | /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes, |
5238 | return values, promote the mode here too. */ | |
5239 | mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1); | |
0e5a4ad8 | 5240 | |
ab77a036 RS |
5241 | /* Handle structures whose fields are returned in $f0/$f2. */ |
5242 | switch (mips_fpr_return_fields (valtype, fields)) | |
a20b7b05 | 5243 | { |
ab77a036 | 5244 | case 1: |
fd0d4c1f RS |
5245 | return mips_return_fpr_single (mode, |
5246 | TYPE_MODE (TREE_TYPE (fields[0]))); | |
4d72536e | 5247 | |
ab77a036 RS |
5248 | case 2: |
5249 | return mips_return_fpr_pair (mode, | |
5250 | TYPE_MODE (TREE_TYPE (fields[0])), | |
5251 | int_byte_position (fields[0]), | |
5252 | TYPE_MODE (TREE_TYPE (fields[1])), | |
5253 | int_byte_position (fields[1])); | |
5254 | } | |
4d72536e | 5255 | |
ab77a036 RS |
5256 | /* If a value is passed in the most significant part of a register, see |
5257 | whether we have to round the mode up to a whole number of words. */ | |
5258 | if (mips_return_in_msb (valtype)) | |
5259 | { | |
5260 | HOST_WIDE_INT size = int_size_in_bytes (valtype); | |
5261 | if (size % UNITS_PER_WORD != 0) | |
a20b7b05 | 5262 | { |
ab77a036 RS |
5263 | size += UNITS_PER_WORD - size % UNITS_PER_WORD; |
5264 | mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); | |
4d72536e | 5265 | } |
3f1f8d8c | 5266 | } |
ab77a036 RS |
5267 | |
5268 | /* For EABI, the class of return register depends entirely on MODE. | |
5269 | For example, "struct { some_type x; }" and "union { some_type x; }" | |
5270 | are returned in the same way as a bare "some_type" would be. | |
5271 | Other ABIs only use FPRs for scalar, complex or vector types. */ | |
5272 | if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype)) | |
5273 | return gen_rtx_REG (mode, GP_RETURN); | |
3f1f8d8c MM |
5274 | } |
5275 | ||
ab77a036 | 5276 | if (!TARGET_MIPS16) |
ae043003 | 5277 | { |
ab77a036 RS |
5278 | /* Handle long doubles for n32 & n64. */ |
5279 | if (mode == TFmode) | |
5280 | return mips_return_fpr_pair (mode, | |
5281 | DImode, 0, | |
5282 | DImode, GET_MODE_SIZE (mode) / 2); | |
ae043003 | 5283 | |
ab77a036 | 5284 | if (mips_return_mode_in_fpr_p (mode)) |
0882b52e | 5285 | { |
ab77a036 RS |
5286 | if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) |
5287 | return mips_return_fpr_pair (mode, | |
5288 | GET_MODE_INNER (mode), 0, | |
5289 | GET_MODE_INNER (mode), | |
5290 | GET_MODE_SIZE (mode) / 2); | |
5291 | else | |
5292 | return gen_rtx_REG (mode, FP_RETURN); | |
0882b52e | 5293 | } |
ae043003 RS |
5294 | } |
5295 | ||
ab77a036 | 5296 | return gen_rtx_REG (mode, GP_RETURN); |
cee98a59 MM |
5297 | } |
5298 | ||
65239d20 RS |
5299 | /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs, |
5300 | all BLKmode objects are returned in memory. Under the n32, n64 | |
5301 | and embedded ABIs, small structures are returned in a register. | |
ab77a036 RS |
5302 | Objects with varying size must still be returned in memory, of |
5303 | course. */ | |
b4966b1b | 5304 | |
ab77a036 RS |
5305 | static bool |
5306 | mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) | |
648bb159 | 5307 | { |
65239d20 RS |
5308 | return (TARGET_OLDABI |
5309 | ? TYPE_MODE (type) == BLKmode | |
5310 | : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD)); | |
648bb159 | 5311 | } |
4d72536e | 5312 | \f |
65239d20 RS |
5313 | /* Implement TARGET_SETUP_INCOMING_VARARGS. */ |
5314 | ||
0c8da560 KH |
5315 | static void |
5316 | mips_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
4001cd89 RS |
5317 | tree type, int *pretend_size ATTRIBUTE_UNUSED, |
5318 | int no_rtl) | |
4d72536e RS |
5319 | { |
5320 | CUMULATIVE_ARGS local_cum; | |
5321 | int gp_saved, fp_saved; | |
cee98a59 | 5322 | |
4d72536e RS |
5323 | /* The caller has advanced CUM up to, but not beyond, the last named |
5324 | argument. Advance a local copy of CUM past the last "real" named | |
6c535c69 | 5325 | argument, to find out how many registers are left over. */ |
4d72536e | 5326 | local_cum = *cum; |
65239d20 | 5327 | FUNCTION_ARG_ADVANCE (local_cum, mode, type, true); |
4d72536e RS |
5328 | |
5329 | /* Found out how many registers we need to save. */ | |
bb63e5a0 | 5330 | gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; |
4d72536e | 5331 | fp_saved = (EABI_FLOAT_VARARGS_P |
bb63e5a0 | 5332 | ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs |
4d72536e | 5333 | : 0); |
cee98a59 | 5334 | |
4d72536e | 5335 | if (!no_rtl) |
cee98a59 | 5336 | { |
4d72536e RS |
5337 | if (gp_saved > 0) |
5338 | { | |
5339 | rtx ptr, mem; | |
5340 | ||
4001cd89 RS |
5341 | ptr = plus_constant (virtual_incoming_args_rtx, |
5342 | REG_PARM_STACK_SPACE (cfun->decl) | |
5343 | - gp_saved * UNITS_PER_WORD); | |
8d0e1e43 | 5344 | mem = gen_frame_mem (BLKmode, ptr); |
520d96c6 | 5345 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
4d72536e | 5346 | |
520d96c6 RS |
5347 | move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, |
5348 | mem, gp_saved); | |
4d72536e RS |
5349 | } |
5350 | if (fp_saved > 0) | |
5351 | { | |
5352 | /* We can't use move_block_from_reg, because it will use | |
031a26c5 | 5353 | the wrong mode. */ |
4d72536e RS |
5354 | enum machine_mode mode; |
5355 | int off, i; | |
cee98a59 | 5356 | |
4d72536e | 5357 | /* Set OFF to the offset from virtual_incoming_args_rtx of |
71cc389b | 5358 | the first float register. The FP save area lies below |
4d72536e | 5359 | the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */ |
65239d20 | 5360 | off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE; |
4d72536e | 5361 | off -= fp_saved * UNITS_PER_FPREG; |
cee98a59 | 5362 | |
4d72536e RS |
5363 | mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode; |
5364 | ||
e8ab09c1 SL |
5365 | for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; |
5366 | i += MAX_FPRS_PER_FMT) | |
4d72536e | 5367 | { |
520d96c6 RS |
5368 | rtx ptr, mem; |
5369 | ||
5370 | ptr = plus_constant (virtual_incoming_args_rtx, off); | |
8d0e1e43 | 5371 | mem = gen_frame_mem (mode, ptr); |
520d96c6 | 5372 | set_mem_alias_set (mem, get_varargs_alias_set ()); |
51e7252a | 5373 | mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i)); |
8a381273 | 5374 | off += UNITS_PER_HWFPVALUE; |
4d72536e RS |
5375 | } |
5376 | } | |
5377 | } | |
4001cd89 RS |
5378 | if (REG_PARM_STACK_SPACE (cfun->decl) == 0) |
5379 | cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD | |
5380 | + fp_saved * UNITS_PER_FPREG); | |
cee98a59 | 5381 | } |
4d72536e | 5382 | |
65239d20 | 5383 | /* Implement TARGET_BUILTIN_VA_LIST. */ |
4fe12442 | 5384 | |
c35d187f RH |
5385 | static tree |
5386 | mips_build_builtin_va_list (void) | |
5d3f2bd5 | 5387 | { |
4d72536e | 5388 | if (EABI_FLOAT_VARARGS_P) |
5d3f2bd5 | 5389 | { |
65239d20 RS |
5390 | /* We keep 3 pointers, and two offsets. |
5391 | ||
5392 | Two pointers are to the overflow area, which starts at the CFA. | |
5393 | One of these is constant, for addressing into the GPR save area | |
5394 | below it. The other is advanced up the stack through the | |
5395 | overflow region. | |
5396 | ||
5397 | The third pointer is to the bottom of the GPR save area. | |
5398 | Since the FPR save area is just below it, we can address | |
5399 | FPR slots off this pointer. | |
5400 | ||
5401 | We also keep two one-byte offsets, which are to be subtracted | |
5402 | from the constant pointers to yield addresses in the GPR and | |
5403 | FPR save areas. These are downcounted as float or non-float | |
5404 | arguments are used, and when they get to zero, the argument | |
5405 | must be obtained from the overflow region. */ | |
7a0ec607 CD |
5406 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record; |
5407 | tree array, index; | |
5d3f2bd5 | 5408 | |
65239d20 | 5409 | record = lang_hooks.types.make_type (RECORD_TYPE); |
5d3f2bd5 | 5410 | |
4c4bde29 AH |
5411 | f_ovfl = build_decl (BUILTINS_LOCATION, |
5412 | FIELD_DECL, get_identifier ("__overflow_argptr"), | |
65239d20 | 5413 | ptr_type_node); |
4c4bde29 AH |
5414 | f_gtop = build_decl (BUILTINS_LOCATION, |
5415 | FIELD_DECL, get_identifier ("__gpr_top"), | |
65239d20 | 5416 | ptr_type_node); |
4c4bde29 AH |
5417 | f_ftop = build_decl (BUILTINS_LOCATION, |
5418 | FIELD_DECL, get_identifier ("__fpr_top"), | |
65239d20 | 5419 | ptr_type_node); |
4c4bde29 AH |
5420 | f_goff = build_decl (BUILTINS_LOCATION, |
5421 | FIELD_DECL, get_identifier ("__gpr_offset"), | |
65239d20 | 5422 | unsigned_char_type_node); |
4c4bde29 AH |
5423 | f_foff = build_decl (BUILTINS_LOCATION, |
5424 | FIELD_DECL, get_identifier ("__fpr_offset"), | |
65239d20 | 5425 | unsigned_char_type_node); |
7a0ec607 CD |
5426 | /* Explicitly pad to the size of a pointer, so that -Wpadded won't |
5427 | warn on every user file. */ | |
7d60be94 | 5428 | index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1); |
7a0ec607 CD |
5429 | array = build_array_type (unsigned_char_type_node, |
5430 | build_index_type (index)); | |
4c4bde29 AH |
5431 | f_res = build_decl (BUILTINS_LOCATION, |
5432 | FIELD_DECL, get_identifier ("__reserved"), array); | |
5d3f2bd5 | 5433 | |
4fe12442 DL |
5434 | DECL_FIELD_CONTEXT (f_ovfl) = record; |
5435 | DECL_FIELD_CONTEXT (f_gtop) = record; | |
5436 | DECL_FIELD_CONTEXT (f_ftop) = record; | |
5437 | DECL_FIELD_CONTEXT (f_goff) = record; | |
5438 | DECL_FIELD_CONTEXT (f_foff) = record; | |
7a0ec607 | 5439 | DECL_FIELD_CONTEXT (f_res) = record; |
5d3f2bd5 | 5440 | |
4fe12442 DL |
5441 | TYPE_FIELDS (record) = f_ovfl; |
5442 | TREE_CHAIN (f_ovfl) = f_gtop; | |
5443 | TREE_CHAIN (f_gtop) = f_ftop; | |
5444 | TREE_CHAIN (f_ftop) = f_goff; | |
5445 | TREE_CHAIN (f_goff) = f_foff; | |
7a0ec607 | 5446 | TREE_CHAIN (f_foff) = f_res; |
5d3f2bd5 | 5447 | |
4fe12442 | 5448 | layout_type (record); |
5d3f2bd5 RH |
5449 | return record; |
5450 | } | |
9aaa1ee8 | 5451 | else if (TARGET_IRIX6) |
4f1cad00 RH |
5452 | /* On IRIX 6, this type is 'char *'. */ |
5453 | return build_pointer_type (char_type_node); | |
5d3f2bd5 | 5454 | else |
4f1cad00 RH |
5455 | /* Otherwise, we use 'void *'. */ |
5456 | return ptr_type_node; | |
5d3f2bd5 RH |
5457 | } |
5458 | ||
d7bd8aeb | 5459 | /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ |
5d3f2bd5 | 5460 | |
d7bd8aeb | 5461 | static void |
b4966b1b | 5462 | mips_va_start (tree valist, rtx nextarg) |
5d3f2bd5 | 5463 | { |
4001cd89 | 5464 | if (EABI_FLOAT_VARARGS_P) |
5d3f2bd5 | 5465 | { |
4001cd89 RS |
5466 | const CUMULATIVE_ARGS *cum; |
5467 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; | |
5468 | tree ovfl, gtop, ftop, goff, foff; | |
5469 | tree t; | |
4fe12442 | 5470 | int gpr_save_area_size; |
4001cd89 RS |
5471 | int fpr_save_area_size; |
5472 | int fpr_offset; | |
4fe12442 | 5473 | |
38173d38 | 5474 | cum = &crtl->args.info; |
4d72536e | 5475 | gpr_save_area_size |
bb63e5a0 | 5476 | = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD; |
4001cd89 RS |
5477 | fpr_save_area_size |
5478 | = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG; | |
4d72536e | 5479 | |
4001cd89 RS |
5480 | f_ovfl = TYPE_FIELDS (va_list_type_node); |
5481 | f_gtop = TREE_CHAIN (f_ovfl); | |
5482 | f_ftop = TREE_CHAIN (f_gtop); | |
5483 | f_goff = TREE_CHAIN (f_ftop); | |
5484 | f_foff = TREE_CHAIN (f_goff); | |
5485 | ||
47a25a46 RG |
5486 | ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, |
5487 | NULL_TREE); | |
5488 | gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop, | |
5489 | NULL_TREE); | |
5490 | ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop, | |
5491 | NULL_TREE); | |
5492 | goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff, | |
5493 | NULL_TREE); | |
5494 | foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff, | |
5495 | NULL_TREE); | |
4001cd89 RS |
5496 | |
5497 | /* Emit code to initialize OVFL, which points to the next varargs | |
5498 | stack argument. CUM->STACK_WORDS gives the number of stack | |
5499 | words used by named arguments. */ | |
5500 | t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx); | |
5501 | if (cum->stack_words > 0) | |
5be014d5 AP |
5502 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), t, |
5503 | size_int (cum->stack_words * UNITS_PER_WORD)); | |
726a989a | 5504 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t); |
4001cd89 RS |
5505 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5506 | ||
5507 | /* Emit code to initialize GTOP, the top of the GPR save area. */ | |
5508 | t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx); | |
726a989a | 5509 | t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t); |
4001cd89 RS |
5510 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5511 | ||
5512 | /* Emit code to initialize FTOP, the top of the FPR save area. | |
5513 | This address is gpr_save_area_bytes below GTOP, rounded | |
5514 | down to the next fp-aligned boundary. */ | |
5515 | t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx); | |
5516 | fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1; | |
65239d20 | 5517 | fpr_offset &= -UNITS_PER_FPVALUE; |
4001cd89 | 5518 | if (fpr_offset) |
5be014d5 AP |
5519 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ftop), t, |
5520 | size_int (-fpr_offset)); | |
726a989a | 5521 | t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t); |
4001cd89 RS |
5522 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5523 | ||
5524 | /* Emit code to initialize GOFF, the offset from GTOP of the | |
5525 | next GPR argument. */ | |
726a989a | 5526 | t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff, |
e0681eaa | 5527 | build_int_cst (TREE_TYPE (goff), gpr_save_area_size)); |
4001cd89 RS |
5528 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5529 | ||
5530 | /* Likewise emit code to initialize FOFF, the offset from FTOP | |
5531 | of the next FPR argument. */ | |
726a989a | 5532 | t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff, |
e0681eaa | 5533 | build_int_cst (TREE_TYPE (foff), fpr_save_area_size)); |
4001cd89 | 5534 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); |
5d3f2bd5 RH |
5535 | } |
5536 | else | |
4001cd89 RS |
5537 | { |
5538 | nextarg = plus_constant (nextarg, -cfun->machine->varargs_size); | |
5539 | std_expand_builtin_va_start (valist, nextarg); | |
5540 | } | |
5d3f2bd5 | 5541 | } |
65239d20 RS |
5542 | |
5543 | /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */ | |
5d3f2bd5 | 5544 | |
0310e537 | 5545 | static tree |
726a989a RB |
5546 | mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, |
5547 | gimple_seq *post_p) | |
5d3f2bd5 | 5548 | { |
0310e537 | 5549 | tree addr; |
65239d20 | 5550 | bool indirect_p; |
0310e537 | 5551 | |
65239d20 RS |
5552 | indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0); |
5553 | if (indirect_p) | |
0310e537 | 5554 | type = build_pointer_type (type); |
5d3f2bd5 | 5555 | |
65239d20 | 5556 | if (!EABI_FLOAT_VARARGS_P) |
0310e537 RH |
5557 | addr = std_gimplify_va_arg_expr (valist, type, pre_p, post_p); |
5558 | else | |
5d3f2bd5 | 5559 | { |
0310e537 RH |
5560 | tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff; |
5561 | tree ovfl, top, off, align; | |
65239d20 | 5562 | HOST_WIDE_INT size, rsize, osize; |
0310e537 RH |
5563 | tree t, u; |
5564 | ||
5565 | f_ovfl = TYPE_FIELDS (va_list_type_node); | |
5566 | f_gtop = TREE_CHAIN (f_ovfl); | |
5567 | f_ftop = TREE_CHAIN (f_gtop); | |
5568 | f_goff = TREE_CHAIN (f_ftop); | |
5569 | f_foff = TREE_CHAIN (f_goff); | |
5570 | ||
65239d20 | 5571 | /* Let: |
0310e537 | 5572 | |
65239d20 | 5573 | TOP be the top of the GPR or FPR save area; |
0310e537 RH |
5574 | OFF be the offset from TOP of the next register; |
5575 | ADDR_RTX be the address of the argument; | |
65239d20 | 5576 | SIZE be the number of bytes in the argument type; |
0310e537 | 5577 | RSIZE be the number of bytes used to store the argument |
65239d20 | 5578 | when it's in the register save area; and |
0310e537 | 5579 | OSIZE be the number of bytes used to store it when it's |
65239d20 | 5580 | in the stack overflow area. |
0310e537 RH |
5581 | |
5582 | The code we want is: | |
5583 | ||
5584 | 1: off &= -rsize; // round down | |
5585 | 2: if (off != 0) | |
5586 | 3: { | |
65239d20 RS |
5587 | 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0); |
5588 | 5: off -= rsize; | |
0310e537 RH |
5589 | 6: } |
5590 | 7: else | |
5591 | 8: { | |
65239d20 RS |
5592 | 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize; |
5593 | 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0); | |
5594 | 11: ovfl += osize; | |
5595 | 14: } | |
0310e537 RH |
5596 | |
5597 | [1] and [9] can sometimes be optimized away. */ | |
5598 | ||
47a25a46 RG |
5599 | ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl, |
5600 | NULL_TREE); | |
65239d20 | 5601 | size = int_size_in_bytes (type); |
0310e537 RH |
5602 | |
5603 | if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT | |
5604 | && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE) | |
5d3f2bd5 | 5605 | { |
6d8d5435 RS |
5606 | top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), |
5607 | unshare_expr (valist), f_ftop, NULL_TREE); | |
5608 | off = build3 (COMPONENT_REF, TREE_TYPE (f_foff), | |
5609 | unshare_expr (valist), f_foff, NULL_TREE); | |
0310e537 | 5610 | |
65239d20 RS |
5611 | /* When va_start saves FPR arguments to the stack, each slot |
5612 | takes up UNITS_PER_HWFPVALUE bytes, regardless of the | |
5613 | argument's precision. */ | |
0310e537 RH |
5614 | rsize = UNITS_PER_HWFPVALUE; |
5615 | ||
5616 | /* Overflow arguments are padded to UNITS_PER_WORD bytes | |
5617 | (= PARM_BOUNDARY bits). This can be different from RSIZE | |
5618 | in two cases: | |
5619 | ||
5620 | (1) On 32-bit targets when TYPE is a structure such as: | |
5621 | ||
5622 | struct s { float f; }; | |
5623 | ||
5624 | Such structures are passed in paired FPRs, so RSIZE | |
5625 | will be 8 bytes. However, the structure only takes | |
5626 | up 4 bytes of memory, so OSIZE will only be 4. | |
5627 | ||
5628 | (2) In combinations such as -mgp64 -msingle-float | |
65239d20 RS |
5629 | -fshort-double. Doubles passed in registers will then take |
5630 | up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the | |
5631 | stack take up UNITS_PER_WORD bytes. */ | |
0310e537 | 5632 | osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD); |
5d3f2bd5 | 5633 | } |
4d72536e RS |
5634 | else |
5635 | { | |
6d8d5435 RS |
5636 | top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), |
5637 | unshare_expr (valist), f_gtop, NULL_TREE); | |
5638 | off = build3 (COMPONENT_REF, TREE_TYPE (f_goff), | |
5639 | unshare_expr (valist), f_goff, NULL_TREE); | |
65239d20 | 5640 | rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD; |
0310e537 | 5641 | if (rsize > UNITS_PER_WORD) |
4fe12442 | 5642 | { |
0310e537 | 5643 | /* [1] Emit code for: off &= -rsize. */ |
6d8d5435 | 5644 | t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off), |
3179cf8c | 5645 | build_int_cst (TREE_TYPE (off), -rsize)); |
6d8d5435 | 5646 | gimplify_assign (unshare_expr (off), t, pre_p); |
4d72536e | 5647 | } |
0310e537 RH |
5648 | osize = rsize; |
5649 | } | |
a85cd407 | 5650 | |
0310e537 | 5651 | /* [2] Emit code to branch if off == 0. */ |
47a25a46 RG |
5652 | t = build2 (NE_EXPR, boolean_type_node, off, |
5653 | build_int_cst (TREE_TYPE (off), 0)); | |
5654 | addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE); | |
0310e537 RH |
5655 | |
5656 | /* [5] Emit code for: off -= rsize. We do this as a form of | |
65239d20 | 5657 | post-decrement not available to C. */ |
7d60be94 | 5658 | t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize)); |
47a25a46 | 5659 | t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t); |
65239d20 RS |
5660 | |
5661 | /* [4] Emit code for: | |
5662 | addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */ | |
0310e537 | 5663 | t = fold_convert (sizetype, t); |
5be014d5 | 5664 | t = fold_build1 (NEGATE_EXPR, sizetype, t); |
5be014d5 | 5665 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (top), top, t); |
0310e537 RH |
5666 | if (BYTES_BIG_ENDIAN && rsize > size) |
5667 | { | |
5be014d5 AP |
5668 | u = size_int (rsize - size); |
5669 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u); | |
0310e537 RH |
5670 | } |
5671 | COND_EXPR_THEN (addr) = t; | |
a85cd407 | 5672 | |
0310e537 RH |
5673 | if (osize > UNITS_PER_WORD) |
5674 | { | |
65239d20 | 5675 | /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */ |
5be014d5 | 5676 | u = size_int (osize - 1); |
6d8d5435 RS |
5677 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovfl), |
5678 | unshare_expr (ovfl), u); | |
5be014d5 AP |
5679 | t = fold_convert (sizetype, t); |
5680 | u = size_int (-osize); | |
5681 | t = build2 (BIT_AND_EXPR, sizetype, t, u); | |
5682 | t = fold_convert (TREE_TYPE (ovfl), t); | |
6d8d5435 RS |
5683 | align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), |
5684 | unshare_expr (ovfl), t); | |
4d72536e | 5685 | } |
0310e537 RH |
5686 | else |
5687 | align = NULL; | |
5688 | ||
65239d20 RS |
5689 | /* [10, 11] Emit code for: |
5690 | addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0) | |
5691 | ovfl += osize. */ | |
5692 | u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize)); | |
47a25a46 | 5693 | t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u); |
0310e537 | 5694 | if (BYTES_BIG_ENDIAN && osize > size) |
4d72536e | 5695 | { |
5be014d5 AP |
5696 | u = size_int (osize - size); |
5697 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, u); | |
5d3f2bd5 | 5698 | } |
5d3f2bd5 | 5699 | |
65239d20 | 5700 | /* String [9] and [10, 11] together. */ |
0310e537 | 5701 | if (align) |
47a25a46 | 5702 | t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t); |
0310e537 | 5703 | COND_EXPR_ELSE (addr) = t; |
5d3f2bd5 | 5704 | |
0310e537 | 5705 | addr = fold_convert (build_pointer_type (type), addr); |
d6e9821f | 5706 | addr = build_va_arg_indirect_ref (addr); |
0310e537 | 5707 | } |
e72ed4a7 | 5708 | |
65239d20 | 5709 | if (indirect_p) |
d6e9821f | 5710 | addr = build_va_arg_indirect_ref (addr); |
5d3f2bd5 | 5711 | |
0310e537 | 5712 | return addr; |
5d3f2bd5 RH |
5713 | } |
5714 | \f | |
b2b61607 RS |
5715 | /* Start a definition of function NAME. MIPS16_P indicates whether the |
5716 | function contains MIPS16 code. */ | |
5717 | ||
5718 | static void | |
5719 | mips_start_function_definition (const char *name, bool mips16_p) | |
5720 | { | |
5721 | if (mips16_p) | |
5722 | fprintf (asm_out_file, "\t.set\tmips16\n"); | |
5723 | else | |
5724 | fprintf (asm_out_file, "\t.set\tnomips16\n"); | |
5725 | ||
5726 | if (!flag_inhibit_size_directive) | |
5727 | { | |
5728 | fputs ("\t.ent\t", asm_out_file); | |
5729 | assemble_name (asm_out_file, name); | |
5730 | fputs ("\n", asm_out_file); | |
5731 | } | |
5732 | ||
5733 | ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function"); | |
5734 | ||
5735 | /* Start the definition proper. */ | |
5736 | assemble_name (asm_out_file, name); | |
5737 | fputs (":\n", asm_out_file); | |
5738 | } | |
5739 | ||
5740 | /* End a function definition started by mips_start_function_definition. */ | |
5741 | ||
5742 | static void | |
5743 | mips_end_function_definition (const char *name) | |
5744 | { | |
5745 | if (!flag_inhibit_size_directive) | |
5746 | { | |
5747 | fputs ("\t.end\t", asm_out_file); | |
5748 | assemble_name (asm_out_file, name); | |
5749 | fputs ("\n", asm_out_file); | |
5750 | } | |
5751 | } | |
5752 | \f | |
7462a715 RS |
5753 | /* Return true if calls to X can use R_MIPS_CALL* relocations. */ |
5754 | ||
5755 | static bool | |
5756 | mips_ok_for_lazy_binding_p (rtx x) | |
5757 | { | |
5758 | return (TARGET_USE_GOT | |
5759 | && GET_CODE (x) == SYMBOL_REF | |
08d0963a | 5760 | && !SYMBOL_REF_BIND_NOW_P (x) |
7462a715 RS |
5761 | && !mips_symbol_binds_local_p (x)); |
5762 | } | |
5763 | ||
08d0963a RS |
5764 | /* Load function address ADDR into register DEST. TYPE is as for |
5765 | mips_expand_call. Return true if we used an explicit lazy-binding | |
5766 | sequence. */ | |
7462a715 RS |
5767 | |
5768 | static bool | |
08d0963a | 5769 | mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr) |
7462a715 RS |
5770 | { |
5771 | /* If we're generating PIC, and this call is to a global function, | |
5772 | try to allow its address to be resolved lazily. This isn't | |
5773 | possible for sibcalls when $gp is call-saved because the value | |
5774 | of $gp on entry to the stub would be our caller's gp, not ours. */ | |
5775 | if (TARGET_EXPLICIT_RELOCS | |
08d0963a | 5776 | && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP) |
7462a715 RS |
5777 | && mips_ok_for_lazy_binding_p (addr)) |
5778 | { | |
08d0963a RS |
5779 | addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL); |
5780 | emit_insn (gen_rtx_SET (VOIDmode, dest, addr)); | |
7462a715 RS |
5781 | return true; |
5782 | } | |
5783 | else | |
5784 | { | |
5785 | mips_emit_move (dest, addr); | |
5786 | return false; | |
5787 | } | |
5788 | } | |
5789 | \f | |
08d0963a RS |
5790 | /* Each locally-defined hard-float MIPS16 function has a local symbol |
5791 | associated with it. This hash table maps the function symbol (FUNC) | |
5792 | to the local symbol (LOCAL). */ | |
d1b38208 | 5793 | struct GTY(()) mips16_local_alias { |
08d0963a RS |
5794 | rtx func; |
5795 | rtx local; | |
5796 | }; | |
5797 | static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases; | |
5798 | ||
5799 | /* Hash table callbacks for mips16_local_aliases. */ | |
5800 | ||
5801 | static hashval_t | |
5802 | mips16_local_aliases_hash (const void *entry) | |
5803 | { | |
5804 | const struct mips16_local_alias *alias; | |
5805 | ||
5806 | alias = (const struct mips16_local_alias *) entry; | |
5807 | return htab_hash_string (XSTR (alias->func, 0)); | |
5808 | } | |
5809 | ||
5810 | static int | |
5811 | mips16_local_aliases_eq (const void *entry1, const void *entry2) | |
5812 | { | |
5813 | const struct mips16_local_alias *alias1, *alias2; | |
5814 | ||
5815 | alias1 = (const struct mips16_local_alias *) entry1; | |
5816 | alias2 = (const struct mips16_local_alias *) entry2; | |
5817 | return rtx_equal_p (alias1->func, alias2->func); | |
5818 | } | |
5819 | ||
5820 | /* FUNC is the symbol for a locally-defined hard-float MIPS16 function. | |
5821 | Return a local alias for it, creating a new one if necessary. */ | |
5822 | ||
5823 | static rtx | |
5824 | mips16_local_alias (rtx func) | |
5825 | { | |
5826 | struct mips16_local_alias *alias, tmp_alias; | |
5827 | void **slot; | |
5828 | ||
5829 | /* Create the hash table if this is the first call. */ | |
5830 | if (mips16_local_aliases == NULL) | |
5831 | mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash, | |
5832 | mips16_local_aliases_eq, NULL); | |
5833 | ||
5834 | /* Look up the function symbol, creating a new entry if need be. */ | |
5835 | tmp_alias.func = func; | |
5836 | slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT); | |
5837 | gcc_assert (slot != NULL); | |
5838 | ||
5839 | alias = (struct mips16_local_alias *) *slot; | |
5840 | if (alias == NULL) | |
5841 | { | |
5842 | const char *func_name, *local_name; | |
5843 | rtx local; | |
5844 | ||
5845 | /* Create a new SYMBOL_REF for the local symbol. The choice of | |
5846 | __fn_local_* is based on the __fn_stub_* names that we've | |
5847 | traditionally used for the non-MIPS16 stub. */ | |
5848 | func_name = targetm.strip_name_encoding (XSTR (func, 0)); | |
5849 | local_name = ACONCAT (("__fn_local_", func_name, NULL)); | |
5850 | local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name)); | |
5851 | SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL; | |
5852 | ||
5853 | /* Create a new structure to represent the mapping. */ | |
a9429e29 | 5854 | alias = ggc_alloc_mips16_local_alias (); |
08d0963a RS |
5855 | alias->func = func; |
5856 | alias->local = local; | |
5857 | *slot = alias; | |
5858 | } | |
5859 | return alias->local; | |
5860 | } | |
5861 | \f | |
65239d20 RS |
5862 | /* A chained list of functions for which mips16_build_call_stub has already |
5863 | generated a stub. NAME is the name of the function and FP_RET_P is true | |
5864 | if the function returns a value in floating-point registers. */ | |
5865 | struct mips16_stub { | |
ab77a036 RS |
5866 | struct mips16_stub *next; |
5867 | char *name; | |
65239d20 | 5868 | bool fp_ret_p; |
ab77a036 | 5869 | }; |
ab77a036 | 5870 | static struct mips16_stub *mips16_stubs; |
b4966b1b | 5871 | |
08d0963a RS |
5872 | /* Return a SYMBOL_REF for a MIPS16 function called NAME. */ |
5873 | ||
5874 | static rtx | |
5875 | mips16_stub_function (const char *name) | |
5876 | { | |
5877 | rtx x; | |
5878 | ||
5879 | x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); | |
5880 | SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION); | |
5881 | return x; | |
5882 | } | |
5883 | ||
65239d20 RS |
5884 | /* Return the two-character string that identifies floating-point |
5885 | return mode MODE in the name of a MIPS16 function stub. */ | |
b4966b1b | 5886 | |
ab77a036 RS |
5887 | static const char * |
5888 | mips16_call_stub_mode_suffix (enum machine_mode mode) | |
5889 | { | |
5890 | if (mode == SFmode) | |
5891 | return "sf"; | |
5892 | else if (mode == DFmode) | |
5893 | return "df"; | |
5894 | else if (mode == SCmode) | |
5895 | return "sc"; | |
5896 | else if (mode == DCmode) | |
5897 | return "dc"; | |
5898 | else if (mode == V2SFmode) | |
5899 | return "df"; | |
5900 | else | |
5901 | gcc_unreachable (); | |
5902 | } | |
b4966b1b | 5903 | |
5b372d33 RS |
5904 | /* Write instructions to move a 32-bit value between general register |
5905 | GPREG and floating-point register FPREG. DIRECTION is 't' to move | |
5906 | from GPREG to FPREG and 'f' to move in the opposite direction. */ | |
5907 | ||
5908 | static void | |
5909 | mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg) | |
5910 | { | |
5911 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
5912 | reg_names[gpreg], reg_names[fpreg]); | |
5913 | } | |
5914 | ||
5915 | /* Likewise for 64-bit values. */ | |
5916 | ||
5917 | static void | |
5918 | mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg) | |
5919 | { | |
5920 | if (TARGET_64BIT) | |
5921 | fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction, | |
5922 | reg_names[gpreg], reg_names[fpreg]); | |
5923 | else if (TARGET_FLOAT64) | |
5924 | { | |
5925 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
5926 | reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]); | |
5927 | fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction, | |
5928 | reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]); | |
5929 | } | |
5930 | else | |
5931 | { | |
5932 | /* Move the least-significant word. */ | |
5933 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
5934 | reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]); | |
5935 | /* ...then the most significant word. */ | |
5936 | fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction, | |
5937 | reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]); | |
5938 | } | |
5939 | } | |
5940 | ||
5941 | /* Write out code to move floating-point arguments into or out of | |
23fdf75c | 5942 | general registers. FP_CODE is the code describing which arguments |
5b372d33 RS |
5943 | are present (see the comment above the definition of CUMULATIVE_ARGS |
5944 | in mips.h). DIRECTION is as for mips_output_32bit_xfer. */ | |
b4966b1b | 5945 | |
ab77a036 | 5946 | static void |
5b372d33 | 5947 | mips_output_args_xfer (int fp_code, char direction) |
ab77a036 | 5948 | { |
5b372d33 | 5949 | unsigned int gparg, fparg, f; |
ab77a036 | 5950 | CUMULATIVE_ARGS cum; |
b4966b1b | 5951 | |
65239d20 | 5952 | /* This code only works for o32 and o64. */ |
ab77a036 | 5953 | gcc_assert (TARGET_OLDABI); |
b4966b1b | 5954 | |
65239d20 | 5955 | mips_init_cumulative_args (&cum, NULL); |
b4966b1b | 5956 | |
ab77a036 RS |
5957 | for (f = (unsigned int) fp_code; f != 0; f >>= 2) |
5958 | { | |
5959 | enum machine_mode mode; | |
5960 | struct mips_arg_info info; | |
b4966b1b | 5961 | |
ab77a036 RS |
5962 | if ((f & 3) == 1) |
5963 | mode = SFmode; | |
5964 | else if ((f & 3) == 2) | |
5965 | mode = DFmode; | |
5966 | else | |
5967 | gcc_unreachable (); | |
b4966b1b | 5968 | |
65239d20 | 5969 | mips_get_arg_info (&info, &cum, mode, NULL, true); |
ab77a036 RS |
5970 | gparg = mips_arg_regno (&info, false); |
5971 | fparg = mips_arg_regno (&info, true); | |
b4966b1b | 5972 | |
ab77a036 | 5973 | if (mode == SFmode) |
5b372d33 | 5974 | mips_output_32bit_xfer (direction, gparg, fparg); |
ab77a036 | 5975 | else |
5b372d33 | 5976 | mips_output_64bit_xfer (direction, gparg, fparg); |
b4966b1b | 5977 | |
65239d20 | 5978 | mips_function_arg_advance (&cum, mode, NULL, true); |
b4966b1b | 5979 | } |
b4966b1b RS |
5980 | } |
5981 | ||
65239d20 RS |
5982 | /* Write a MIPS16 stub for the current function. This stub is used |
5983 | for functions which take arguments in the floating-point registers. | |
5984 | It is normal-mode code that moves the floating-point arguments | |
5985 | into the general registers and then jumps to the MIPS16 code. */ | |
b4966b1b | 5986 | |
ab77a036 | 5987 | static void |
65239d20 | 5988 | mips16_build_function_stub (void) |
b4966b1b | 5989 | { |
08d0963a | 5990 | const char *fnname, *alias_name, *separator; |
ab77a036 | 5991 | char *secname, *stubname; |
65239d20 | 5992 | tree stubdecl; |
ab77a036 | 5993 | unsigned int f; |
08d0963a | 5994 | rtx symbol, alias; |
b4966b1b | 5995 | |
65239d20 | 5996 | /* Create the name of the stub, and its unique section. */ |
08d0963a RS |
5997 | symbol = XEXP (DECL_RTL (current_function_decl), 0); |
5998 | alias = mips16_local_alias (symbol); | |
5999 | ||
6000 | fnname = targetm.strip_name_encoding (XSTR (symbol, 0)); | |
6001 | alias_name = targetm.strip_name_encoding (XSTR (alias, 0)); | |
65239d20 RS |
6002 | secname = ACONCAT ((".mips16.fn.", fnname, NULL)); |
6003 | stubname = ACONCAT (("__fn_stub_", fnname, NULL)); | |
6004 | ||
6005 | /* Build a decl for the stub. */ | |
4c4bde29 AH |
6006 | stubdecl = build_decl (BUILTINS_LOCATION, |
6007 | FUNCTION_DECL, get_identifier (stubname), | |
ab77a036 RS |
6008 | build_function_type (void_type_node, NULL_TREE)); |
6009 | DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); | |
4c4bde29 AH |
6010 | DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION, |
6011 | RESULT_DECL, NULL_TREE, void_type_node); | |
b4966b1b | 6012 | |
65239d20 | 6013 | /* Output a comment. */ |
23fdf75c RS |
6014 | fprintf (asm_out_file, "\t# Stub function for %s (", |
6015 | current_function_name ()); | |
65239d20 | 6016 | separator = ""; |
38173d38 | 6017 | for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2) |
b4966b1b | 6018 | { |
65239d20 | 6019 | fprintf (asm_out_file, "%s%s", separator, |
ab77a036 | 6020 | (f & 3) == 1 ? "float" : "double"); |
65239d20 | 6021 | separator = ", "; |
b4966b1b | 6022 | } |
23fdf75c | 6023 | fprintf (asm_out_file, ")\n"); |
9226543b | 6024 | |
b2b61607 RS |
6025 | /* Start the function definition. */ |
6026 | assemble_start_function (stubdecl, stubname); | |
6027 | mips_start_function_definition (stubname, false); | |
e689b870 | 6028 | |
e21d5757 DJ |
6029 | /* If generating pic2 code, either set up the global pointer or |
6030 | switch to pic0. */ | |
6031 | if (TARGET_ABICALLS_PIC2) | |
08d0963a | 6032 | { |
e21d5757 DJ |
6033 | if (TARGET_ABSOLUTE_ABICALLS) |
6034 | fprintf (asm_out_file, "\t.option\tpic0\n"); | |
6035 | else | |
6036 | { | |
6037 | output_asm_insn ("%(.cpload\t%^%)", NULL); | |
6038 | /* Emit an R_MIPS_NONE relocation to tell the linker what the | |
6039 | target function is. Use a local GOT access when loading the | |
6040 | symbol, to cut down on the number of unnecessary GOT entries | |
6041 | for stubs that aren't needed. */ | |
6042 | output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol); | |
6043 | symbol = alias; | |
6044 | } | |
08d0963a RS |
6045 | } |
6046 | ||
e21d5757 | 6047 | /* Load the address of the MIPS16 function into $25. Do this first so |
6a68a258 RS |
6048 | that targets with coprocessor interlocks can use an MFC1 to fill the |
6049 | delay slot. */ | |
e21d5757 | 6050 | output_asm_insn ("la\t%^,%0", &symbol); |
e689b870 | 6051 | |
65239d20 | 6052 | /* Move the arguments from floating-point registers to general registers. */ |
38173d38 | 6053 | mips_output_args_xfer (crtl->args.info.fp_code, 'f'); |
e689b870 | 6054 | |
65239d20 | 6055 | /* Jump to the MIPS16 function. */ |
e21d5757 | 6056 | output_asm_insn ("jr\t%^", NULL); |
d8934cf1 | 6057 | |
e21d5757 | 6058 | if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS) |
08d0963a RS |
6059 | fprintf (asm_out_file, "\t.option\tpic2\n"); |
6060 | ||
b2b61607 | 6061 | mips_end_function_definition (stubname); |
e689b870 | 6062 | |
08d0963a RS |
6063 | /* If the linker needs to create a dynamic symbol for the target |
6064 | function, it will associate the symbol with the stub (which, | |
6065 | unlike the target function, follows the proper calling conventions). | |
6066 | It is therefore useful to have a local alias for the target function, | |
6067 | so that it can still be identified as MIPS16 code. As an optimization, | |
6068 | this symbol can also be used for indirect MIPS16 references from | |
6069 | within this file. */ | |
6070 | ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname); | |
6071 | ||
ab77a036 | 6072 | switch_to_section (function_section (current_function_decl)); |
e689b870 DU |
6073 | } |
6074 | ||
5f5fe6d9 RS |
6075 | /* The current function is a MIPS16 function that returns a value in an FPR. |
6076 | Copy the return value from its soft-float to its hard-float location. | |
6077 | libgcc2 has special non-MIPS16 helper functions for each case. */ | |
6078 | ||
6079 | static void | |
6080 | mips16_copy_fpr_return_value (void) | |
6081 | { | |
08d0963a RS |
6082 | rtx fn, insn, retval; |
6083 | tree return_type; | |
5f5fe6d9 | 6084 | enum machine_mode return_mode; |
08d0963a | 6085 | const char *name; |
5f5fe6d9 RS |
6086 | |
6087 | return_type = DECL_RESULT (current_function_decl); | |
6088 | return_mode = DECL_MODE (return_type); | |
6089 | ||
08d0963a RS |
6090 | name = ACONCAT (("__mips16_ret_", |
6091 | mips16_call_stub_mode_suffix (return_mode), | |
6092 | NULL)); | |
6093 | fn = mips16_stub_function (name); | |
6094 | ||
6095 | /* The function takes arguments in $2 (and possibly $3), so calls | |
6096 | to it cannot be lazily bound. */ | |
6097 | SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW; | |
6098 | ||
6099 | /* Model the call as something that takes the GPR return value as | |
6100 | argument and returns an "updated" value. */ | |
6101 | retval = gen_rtx_REG (return_mode, GP_RETURN); | |
6102 | insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn, | |
6103 | const0_rtx, NULL_RTX, false); | |
6104 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval); | |
5f5fe6d9 RS |
6105 | } |
6106 | ||
08d0963a | 6107 | /* Consider building a stub for a MIPS16 call to function *FN_PTR. |
65239d20 RS |
6108 | RETVAL is the location of the return value, or null if this is |
6109 | a "call" rather than a "call_value". ARGS_SIZE is the size of the | |
6110 | arguments and FP_CODE is the code built by mips_function_arg; | |
b53da244 | 6111 | see the comment before the fp_code field in CUMULATIVE_ARGS for details. |
d33289b2 | 6112 | |
08d0963a RS |
6113 | There are three alternatives: |
6114 | ||
6115 | - If a stub was needed, emit the call and return the call insn itself. | |
6116 | ||
6117 | - If we can avoid using a stub by redirecting the call, set *FN_PTR | |
6118 | to the new target and return null. | |
6119 | ||
6120 | - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR | |
6121 | unmodified. | |
f9e4a411 | 6122 | |
65239d20 RS |
6123 | A stub is needed for calls to functions that, in normal mode, |
6124 | receive arguments in FPRs or return values in FPRs. The stub | |
6125 | copies the arguments from their soft-float positions to their | |
6126 | hard-float positions, calls the real function, then copies the | |
6127 | return value from its hard-float position to its soft-float | |
6128 | position. | |
f9e4a411 | 6129 | |
08d0963a RS |
6130 | We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub. |
6131 | If *FN_PTR turns out to be to a non-MIPS16 function, the linker | |
6132 | automatically redirects the JAL to the stub, otherwise the JAL | |
6133 | continues to call FN directly. */ | |
65239d20 | 6134 | |
dbc90b65 | 6135 | static rtx |
08d0963a | 6136 | mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code) |
f9e4a411 | 6137 | { |
ab77a036 | 6138 | const char *fnname; |
65239d20 | 6139 | bool fp_ret_p; |
ab77a036 | 6140 | struct mips16_stub *l; |
08d0963a | 6141 | rtx insn, fn; |
f9e4a411 | 6142 | |
65239d20 | 6143 | /* We don't need to do anything if we aren't in MIPS16 mode, or if |
ab77a036 RS |
6144 | we were invoked with the -msoft-float option. */ |
6145 | if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI) | |
dbc90b65 | 6146 | return NULL_RTX; |
f9e4a411 | 6147 | |
65239d20 | 6148 | /* Figure out whether the value might come back in a floating-point |
ab77a036 | 6149 | register. */ |
65239d20 | 6150 | fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval)); |
f9e4a411 | 6151 | |
65239d20 RS |
6152 | /* We don't need to do anything if there were no floating-point |
6153 | arguments and the value will not be returned in a floating-point | |
ab77a036 | 6154 | register. */ |
65239d20 | 6155 | if (fp_code == 0 && !fp_ret_p) |
dbc90b65 | 6156 | return NULL_RTX; |
f9e4a411 | 6157 | |
ab77a036 | 6158 | /* We don't need to do anything if this is a call to a special |
65239d20 | 6159 | MIPS16 support function. */ |
08d0963a RS |
6160 | fn = *fn_ptr; |
6161 | if (mips16_stub_function_p (fn)) | |
dbc90b65 | 6162 | return NULL_RTX; |
f9e4a411 | 6163 | |
ab77a036 RS |
6164 | /* This code will only work for o32 and o64 abis. The other ABI's |
6165 | require more sophisticated support. */ | |
6166 | gcc_assert (TARGET_OLDABI); | |
f9e4a411 | 6167 | |
65239d20 RS |
6168 | /* If we're calling via a function pointer, use one of the magic |
6169 | libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination. | |
6170 | Each stub expects the function address to arrive in register $2. */ | |
08d0963a RS |
6171 | if (GET_CODE (fn) != SYMBOL_REF |
6172 | || !call_insn_operand (fn, VOIDmode)) | |
f9e4a411 | 6173 | { |
ab77a036 | 6174 | char buf[30]; |
08d0963a RS |
6175 | rtx stub_fn, insn, addr; |
6176 | bool lazy_p; | |
6177 | ||
6178 | /* If this is a locally-defined and locally-binding function, | |
6179 | avoid the stub by calling the local alias directly. */ | |
6180 | if (mips16_local_function_p (fn)) | |
6181 | { | |
6182 | *fn_ptr = mips16_local_alias (fn); | |
6183 | return NULL_RTX; | |
6184 | } | |
f9e4a411 | 6185 | |
65239d20 RS |
6186 | /* Create a SYMBOL_REF for the libgcc.a function. */ |
6187 | if (fp_ret_p) | |
ab77a036 RS |
6188 | sprintf (buf, "__mips16_call_stub_%s_%d", |
6189 | mips16_call_stub_mode_suffix (GET_MODE (retval)), | |
6190 | fp_code); | |
f9e4a411 | 6191 | else |
65239d20 | 6192 | sprintf (buf, "__mips16_call_stub_%d", fp_code); |
08d0963a RS |
6193 | stub_fn = mips16_stub_function (buf); |
6194 | ||
6195 | /* The function uses $2 as an argument, so calls to it | |
6196 | cannot be lazily bound. */ | |
6197 | SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW; | |
f9e4a411 | 6198 | |
65239d20 | 6199 | /* Load the target function into $2. */ |
08d0963a RS |
6200 | addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2); |
6201 | lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn); | |
f9e4a411 | 6202 | |
65239d20 | 6203 | /* Emit the call. */ |
08d0963a RS |
6204 | insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn, |
6205 | args_size, NULL_RTX, lazy_p); | |
f9e4a411 | 6206 | |
65239d20 | 6207 | /* Tell GCC that this call does indeed use the value of $2. */ |
08d0963a | 6208 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr); |
f9e4a411 | 6209 | |
65239d20 | 6210 | /* If we are handling a floating-point return value, we need to |
ab77a036 RS |
6211 | save $18 in the function prologue. Putting a note on the |
6212 | call will mean that df_regs_ever_live_p ($18) will be true if the | |
6213 | call is not eliminated, and we can check that in the prologue | |
6214 | code. */ | |
65239d20 | 6215 | if (fp_ret_p) |
ab77a036 RS |
6216 | CALL_INSN_FUNCTION_USAGE (insn) = |
6217 | gen_rtx_EXPR_LIST (VOIDmode, | |
08d0963a RS |
6218 | gen_rtx_CLOBBER (VOIDmode, |
6219 | gen_rtx_REG (word_mode, 18)), | |
ab77a036 | 6220 | CALL_INSN_FUNCTION_USAGE (insn)); |
f9e4a411 | 6221 | |
dbc90b65 | 6222 | return insn; |
ab77a036 | 6223 | } |
f9e4a411 | 6224 | |
ab77a036 RS |
6225 | /* We know the function we are going to call. If we have already |
6226 | built a stub, we don't need to do anything further. */ | |
ab77a036 RS |
6227 | fnname = targetm.strip_name_encoding (XSTR (fn, 0)); |
6228 | for (l = mips16_stubs; l != NULL; l = l->next) | |
6229 | if (strcmp (l->name, fnname) == 0) | |
6230 | break; | |
d33289b2 | 6231 | |
ab77a036 | 6232 | if (l == NULL) |
f9e4a411 | 6233 | { |
65239d20 RS |
6234 | const char *separator; |
6235 | char *secname, *stubname; | |
6236 | tree stubid, stubdecl; | |
6237 | unsigned int f; | |
8d1d0dee | 6238 | |
65239d20 | 6239 | /* If the function does not return in FPRs, the special stub |
ab77a036 | 6240 | section is named |
65239d20 RS |
6241 | .mips16.call.FNNAME |
6242 | ||
6243 | If the function does return in FPRs, the stub section is named | |
ab77a036 | 6244 | .mips16.call.fp.FNNAME |
f9e4a411 | 6245 | |
65239d20 RS |
6246 | Build a decl for the stub. */ |
6247 | secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "", | |
6248 | fnname, NULL)); | |
6249 | stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "", | |
6250 | fnname, NULL)); | |
ab77a036 | 6251 | stubid = get_identifier (stubname); |
4c4bde29 AH |
6252 | stubdecl = build_decl (BUILTINS_LOCATION, |
6253 | FUNCTION_DECL, stubid, | |
ab77a036 RS |
6254 | build_function_type (void_type_node, NULL_TREE)); |
6255 | DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname); | |
4c4bde29 AH |
6256 | DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION, |
6257 | RESULT_DECL, NULL_TREE, | |
65239d20 | 6258 | void_type_node); |
9a6dfb47 | 6259 | |
65239d20 | 6260 | /* Output a comment. */ |
ab77a036 | 6261 | fprintf (asm_out_file, "\t# Stub function to call %s%s (", |
65239d20 | 6262 | (fp_ret_p |
ab77a036 RS |
6263 | ? (GET_MODE (retval) == SFmode ? "float " : "double ") |
6264 | : ""), | |
6265 | fnname); | |
65239d20 | 6266 | separator = ""; |
ab77a036 RS |
6267 | for (f = (unsigned int) fp_code; f != 0; f >>= 2) |
6268 | { | |
65239d20 | 6269 | fprintf (asm_out_file, "%s%s", separator, |
ab77a036 | 6270 | (f & 3) == 1 ? "float" : "double"); |
65239d20 | 6271 | separator = ", "; |
ab77a036 RS |
6272 | } |
6273 | fprintf (asm_out_file, ")\n"); | |
f9e4a411 | 6274 | |
b2b61607 | 6275 | /* Start the function definition. */ |
ab77a036 | 6276 | assemble_start_function (stubdecl, stubname); |
b2b61607 | 6277 | mips_start_function_definition (stubname, false); |
8ce4afa3 | 6278 | |
65239d20 | 6279 | if (!fp_ret_p) |
ab77a036 | 6280 | { |
e21d5757 | 6281 | /* Load the address of the MIPS16 function into $25. Do this |
6a68a258 RS |
6282 | first so that targets with coprocessor interlocks can use |
6283 | an MFC1 to fill the delay slot. */ | |
08d0963a RS |
6284 | if (TARGET_EXPLICIT_RELOCS) |
6285 | { | |
6286 | output_asm_insn ("lui\t%^,%%hi(%0)", &fn); | |
6287 | output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn); | |
6288 | } | |
6289 | else | |
6290 | output_asm_insn ("la\t%^,%0", &fn); | |
6a68a258 RS |
6291 | } |
6292 | ||
65239d20 RS |
6293 | /* Move the arguments from general registers to floating-point |
6294 | registers. */ | |
6a68a258 RS |
6295 | mips_output_args_xfer (fp_code, 't'); |
6296 | ||
65239d20 | 6297 | if (!fp_ret_p) |
6a68a258 RS |
6298 | { |
6299 | /* Jump to the previously-loaded address. */ | |
08d0963a | 6300 | output_asm_insn ("jr\t%^", NULL); |
ab77a036 RS |
6301 | } |
6302 | else | |
6303 | { | |
65239d20 RS |
6304 | /* Save the return address in $18 and call the non-MIPS16 function. |
6305 | The stub's caller knows that $18 might be clobbered, even though | |
6306 | $18 is usually a call-saved register. */ | |
ab77a036 | 6307 | fprintf (asm_out_file, "\tmove\t%s,%s\n", |
293593b1 | 6308 | reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]); |
b53da244 | 6309 | output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn); |
65239d20 RS |
6310 | |
6311 | /* Move the result from floating-point registers to | |
6312 | general registers. */ | |
ab77a036 RS |
6313 | switch (GET_MODE (retval)) |
6314 | { | |
6315 | case SCmode: | |
5b372d33 RS |
6316 | mips_output_32bit_xfer ('f', GP_RETURN + 1, |
6317 | FP_REG_FIRST + MAX_FPRS_PER_FMT); | |
ab77a036 RS |
6318 | /* Fall though. */ |
6319 | case SFmode: | |
5b372d33 | 6320 | mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST); |
ab77a036 RS |
6321 | if (GET_MODE (retval) == SCmode && TARGET_64BIT) |
6322 | { | |
6323 | /* On 64-bit targets, complex floats are returned in | |
6324 | a single GPR, such that "sd" on a suitably-aligned | |
6325 | target would store the value correctly. */ | |
6326 | fprintf (asm_out_file, "\tdsll\t%s,%s,32\n", | |
5b372d33 RS |
6327 | reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN], |
6328 | reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]); | |
ab77a036 | 6329 | fprintf (asm_out_file, "\tor\t%s,%s,%s\n", |
5b372d33 RS |
6330 | reg_names[GP_RETURN], |
6331 | reg_names[GP_RETURN], | |
6332 | reg_names[GP_RETURN + 1]); | |
ab77a036 RS |
6333 | } |
6334 | break; | |
f9e4a411 | 6335 | |
ab77a036 | 6336 | case DCmode: |
5b372d33 RS |
6337 | mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD), |
6338 | FP_REG_FIRST + MAX_FPRS_PER_FMT); | |
ab77a036 RS |
6339 | /* Fall though. */ |
6340 | case DFmode: | |
6341 | case V2SFmode: | |
5b372d33 | 6342 | mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST); |
ab77a036 | 6343 | break; |
9a6dfb47 | 6344 | |
ab77a036 RS |
6345 | default: |
6346 | gcc_unreachable (); | |
6347 | } | |
65239d20 | 6348 | fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]); |
ab77a036 | 6349 | } |
9a6dfb47 | 6350 | |
ab77a036 RS |
6351 | #ifdef ASM_DECLARE_FUNCTION_SIZE |
6352 | ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl); | |
6353 | #endif | |
9a6dfb47 | 6354 | |
b2b61607 | 6355 | mips_end_function_definition (stubname); |
9a6dfb47 | 6356 | |
ab77a036 | 6357 | /* Record this stub. */ |
65239d20 | 6358 | l = XNEW (struct mips16_stub); |
ab77a036 | 6359 | l->name = xstrdup (fnname); |
65239d20 | 6360 | l->fp_ret_p = fp_ret_p; |
ab77a036 RS |
6361 | l->next = mips16_stubs; |
6362 | mips16_stubs = l; | |
6363 | } | |
9a6dfb47 | 6364 | |
65239d20 | 6365 | /* If we expect a floating-point return value, but we've built a |
ab77a036 | 6366 | stub which does not expect one, then we're in trouble. We can't |
65239d20 | 6367 | use the existing stub, because it won't handle the floating-point |
ab77a036 RS |
6368 | value. We can't build a new stub, because the linker won't know |
6369 | which stub to use for the various calls in this object file. | |
6370 | Fortunately, this case is illegal, since it means that a function | |
6371 | was declared in two different ways in a single compilation. */ | |
65239d20 | 6372 | if (fp_ret_p && !l->fp_ret_p) |
ab77a036 | 6373 | error ("cannot handle inconsistent calls to %qs", fnname); |
9a6dfb47 | 6374 | |
ab77a036 | 6375 | if (retval == NULL_RTX) |
65239d20 | 6376 | insn = gen_call_internal_direct (fn, args_size); |
ab77a036 | 6377 | else |
65239d20 | 6378 | insn = gen_call_value_internal_direct (retval, fn, args_size); |
08d0963a | 6379 | insn = mips_emit_call_insn (insn, fn, fn, false); |
9a6dfb47 | 6380 | |
65239d20 RS |
6381 | /* If we are calling a stub which handles a floating-point return |
6382 | value, we need to arrange to save $18 in the prologue. We do this | |
6383 | by marking the function call as using the register. The prologue | |
6384 | will later see that it is used, and emit code to save it. */ | |
6385 | if (fp_ret_p) | |
ab77a036 RS |
6386 | CALL_INSN_FUNCTION_USAGE (insn) = |
6387 | gen_rtx_EXPR_LIST (VOIDmode, | |
08d0963a RS |
6388 | gen_rtx_CLOBBER (VOIDmode, |
6389 | gen_rtx_REG (word_mode, 18)), | |
ab77a036 | 6390 | CALL_INSN_FUNCTION_USAGE (insn)); |
9a6dfb47 | 6391 | |
dbc90b65 | 6392 | return insn; |
9a6dfb47 | 6393 | } |
ab77a036 | 6394 | \f |
08d0963a RS |
6395 | /* Expand a call of type TYPE. RESULT is where the result will go (null |
6396 | for "call"s and "sibcall"s), ADDR is the address of the function, | |
6397 | ARGS_SIZE is the size of the arguments and AUX is the value passed | |
6398 | to us by mips_function_arg. LAZY_P is true if this call already | |
6399 | involves a lazily-bound function address (such as when calling | |
6400 | functions through a MIPS16 hard-float stub). | |
f9e4a411 | 6401 | |
dbc90b65 RS |
6402 | Return the call itself. */ |
6403 | ||
6404 | rtx | |
08d0963a RS |
6405 | mips_expand_call (enum mips_call_type type, rtx result, rtx addr, |
6406 | rtx args_size, rtx aux, bool lazy_p) | |
f9e4a411 | 6407 | { |
ab77a036 | 6408 | rtx orig_addr, pattern, insn; |
08d0963a | 6409 | int fp_code; |
d522e7a2 | 6410 | |
08d0963a RS |
6411 | fp_code = aux == 0 ? 0 : (int) GET_MODE (aux); |
6412 | insn = mips16_build_call_stub (result, &addr, args_size, fp_code); | |
6413 | if (insn) | |
6414 | { | |
6415 | gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL); | |
6416 | return insn; | |
6417 | } | |
6418 | ; | |
ab77a036 | 6419 | orig_addr = addr; |
ab77a036 | 6420 | if (!call_insn_operand (addr, VOIDmode)) |
d522e7a2 | 6421 | { |
08d0963a RS |
6422 | if (type == MIPS_CALL_EPILOGUE) |
6423 | addr = MIPS_EPILOGUE_TEMP (Pmode); | |
6424 | else | |
6425 | addr = gen_reg_rtx (Pmode); | |
6426 | lazy_p |= mips_load_call_address (type, addr, orig_addr); | |
ab77a036 | 6427 | } |
d522e7a2 | 6428 | |
08d0963a | 6429 | if (result == 0) |
65239d20 | 6430 | { |
08d0963a | 6431 | rtx (*fn) (rtx, rtx); |
d522e7a2 | 6432 | |
0c433c31 | 6433 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
6434 | fn = gen_sibcall_internal; |
6435 | else | |
6436 | fn = gen_call_internal; | |
6437 | ||
6438 | pattern = fn (addr, args_size); | |
6439 | } | |
ab77a036 RS |
6440 | else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2) |
6441 | { | |
fd0d4c1f | 6442 | /* Handle return values created by mips_return_fpr_pair. */ |
08d0963a | 6443 | rtx (*fn) (rtx, rtx, rtx, rtx); |
ab77a036 | 6444 | rtx reg1, reg2; |
d522e7a2 | 6445 | |
0c433c31 | 6446 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
6447 | fn = gen_sibcall_value_multiple_internal; |
6448 | else | |
6449 | fn = gen_call_value_multiple_internal; | |
6450 | ||
ab77a036 RS |
6451 | reg1 = XEXP (XVECEXP (result, 0, 0), 0); |
6452 | reg2 = XEXP (XVECEXP (result, 0, 1), 0); | |
08d0963a | 6453 | pattern = fn (reg1, addr, args_size, reg2); |
ab77a036 RS |
6454 | } |
6455 | else | |
fd0d4c1f | 6456 | { |
08d0963a RS |
6457 | rtx (*fn) (rtx, rtx, rtx); |
6458 | ||
0c433c31 | 6459 | if (type == MIPS_CALL_SIBCALL) |
08d0963a RS |
6460 | fn = gen_sibcall_value_internal; |
6461 | else | |
6462 | fn = gen_call_value_internal; | |
6463 | ||
fd0d4c1f RS |
6464 | /* Handle return values created by mips_return_fpr_single. */ |
6465 | if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1) | |
6466 | result = XEXP (XVECEXP (result, 0, 0), 0); | |
08d0963a | 6467 | pattern = fn (result, addr, args_size); |
fd0d4c1f | 6468 | } |
d522e7a2 | 6469 | |
08d0963a RS |
6470 | return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p); |
6471 | } | |
6472 | ||
6473 | /* Split call instruction INSN into a $gp-clobbering call and | |
6474 | (where necessary) an instruction to restore $gp from its save slot. | |
6475 | CALL_PATTERN is the pattern of the new call. */ | |
6476 | ||
6477 | void | |
6478 | mips_split_call (rtx insn, rtx call_pattern) | |
6479 | { | |
6480 | rtx new_insn; | |
6481 | ||
6482 | new_insn = emit_call_insn (call_pattern); | |
6483 | CALL_INSN_FUNCTION_USAGE (new_insn) | |
6484 | = copy_rtx (CALL_INSN_FUNCTION_USAGE (insn)); | |
6485 | if (!find_reg_note (insn, REG_NORETURN, 0)) | |
6486 | /* Pick a temporary register that is suitable for both MIPS16 and | |
6487 | non-MIPS16 code. $4 and $5 are used for returning complex double | |
6488 | values in soft-float code, so $6 is the first suitable candidate. */ | |
0c433c31 | 6489 | mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2)); |
d522e7a2 | 6490 | } |
a27fb29b | 6491 | |
ab77a036 RS |
6492 | /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */ |
6493 | ||
6494 | static bool | |
6495 | mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) | |
cee98a59 | 6496 | { |
ab77a036 RS |
6497 | if (!TARGET_SIBCALLS) |
6498 | return false; | |
cee98a59 | 6499 | |
e19da24c CF |
6500 | /* Interrupt handlers need special epilogue code and therefore can't |
6501 | use sibcalls. */ | |
6502 | if (mips_interrupt_type_p (TREE_TYPE (current_function_decl))) | |
6503 | return false; | |
6504 | ||
ab77a036 RS |
6505 | /* We can't do a sibcall if the called function is a MIPS16 function |
6506 | because there is no direct "jx" instruction equivalent to "jalx" to | |
9be10a79 RS |
6507 | switch the ISA mode. We only care about cases where the sibling |
6508 | and normal calls would both be direct. */ | |
cf900097 RS |
6509 | if (decl |
6510 | && mips_use_mips16_mode_p (decl) | |
9be10a79 | 6511 | && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)) |
ab77a036 | 6512 | return false; |
d1138d8e | 6513 | |
0b6e1647 RS |
6514 | /* When -minterlink-mips16 is in effect, assume that non-locally-binding |
6515 | functions could be MIPS16 ones unless an attribute explicitly tells | |
6516 | us otherwise. */ | |
ab77a036 RS |
6517 | if (TARGET_INTERLINK_MIPS16 |
6518 | && decl | |
dd748704 | 6519 | && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl)) |
ab77a036 RS |
6520 | && !mips_nomips16_decl_p (decl) |
6521 | && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)) | |
6522 | return false; | |
cee98a59 | 6523 | |
ab77a036 RS |
6524 | /* Otherwise OK. */ |
6525 | return true; | |
6526 | } | |
6527 | \f | |
6528 | /* Emit code to move general operand SRC into condition-code | |
65239d20 | 6529 | register DEST given that SCRATCH is a scratch TFmode FPR. |
ab77a036 | 6530 | The sequence is: |
147255d8 | 6531 | |
ab77a036 RS |
6532 | FP1 = SRC |
6533 | FP2 = 0.0f | |
6534 | DEST = FP2 < FP1 | |
5ae590d7 | 6535 | |
65239d20 | 6536 | where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */ |
f5963e61 | 6537 | |
ab77a036 | 6538 | void |
65239d20 | 6539 | mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch) |
ab77a036 RS |
6540 | { |
6541 | rtx fp1, fp2; | |
ade6c319 | 6542 | |
ab77a036 RS |
6543 | /* Change the source to SFmode. */ |
6544 | if (MEM_P (src)) | |
6545 | src = adjust_address (src, SFmode, 0); | |
6546 | else if (REG_P (src) || GET_CODE (src) == SUBREG) | |
6547 | src = gen_rtx_REG (SFmode, true_regnum (src)); | |
1bd9166e | 6548 | |
ab77a036 RS |
6549 | fp1 = gen_rtx_REG (SFmode, REGNO (scratch)); |
6550 | fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT); | |
f1d5187e | 6551 | |
ab77a036 RS |
6552 | mips_emit_move (copy_rtx (fp1), src); |
6553 | mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode)); | |
6554 | emit_insn (gen_slt_sf (dest, fp2, fp1)); | |
6555 | } | |
6556 | \f | |
6557 | /* Emit straight-line code to move LENGTH bytes from SRC to DEST. | |
6558 | Assume that the areas do not overlap. */ | |
7dac2f89 | 6559 | |
ab77a036 RS |
6560 | static void |
6561 | mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) | |
6562 | { | |
6563 | HOST_WIDE_INT offset, delta; | |
6564 | unsigned HOST_WIDE_INT bits; | |
6565 | int i; | |
6566 | enum machine_mode mode; | |
6567 | rtx *regs; | |
6568 | ||
6569 | /* Work out how many bits to move at a time. If both operands have | |
6570 | half-word alignment, it is usually better to move in half words. | |
6571 | For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr | |
6572 | and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr. | |
6573 | Otherwise move word-sized chunks. */ | |
6574 | if (MEM_ALIGN (src) == BITS_PER_WORD / 2 | |
6575 | && MEM_ALIGN (dest) == BITS_PER_WORD / 2) | |
6576 | bits = BITS_PER_WORD / 2; | |
d81ecf52 | 6577 | else |
ab77a036 | 6578 | bits = BITS_PER_WORD; |
c1bd2d66 | 6579 | |
ab77a036 RS |
6580 | mode = mode_for_size (bits, MODE_INT, 0); |
6581 | delta = bits / BITS_PER_UNIT; | |
a05bea76 | 6582 | |
ab77a036 | 6583 | /* Allocate a buffer for the temporary registers. */ |
5ead67f6 | 6584 | regs = XALLOCAVEC (rtx, length / delta); |
ab77a036 RS |
6585 | |
6586 | /* Load as many BITS-sized chunks as possible. Use a normal load if | |
6587 | the source has enough alignment, otherwise use left/right pairs. */ | |
6588 | for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) | |
cee98a59 | 6589 | { |
ab77a036 RS |
6590 | regs[i] = gen_reg_rtx (mode); |
6591 | if (MEM_ALIGN (src) >= bits) | |
6592 | mips_emit_move (regs[i], adjust_address (src, mode, offset)); | |
7dac2f89 | 6593 | else |
ab77a036 RS |
6594 | { |
6595 | rtx part = adjust_address (src, BLKmode, offset); | |
65239d20 | 6596 | if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0)) |
ab77a036 RS |
6597 | gcc_unreachable (); |
6598 | } | |
a27fb29b | 6599 | } |
cee98a59 | 6600 | |
ab77a036 RS |
6601 | /* Copy the chunks to the destination. */ |
6602 | for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) | |
6603 | if (MEM_ALIGN (dest) >= bits) | |
6604 | mips_emit_move (adjust_address (dest, mode, offset), regs[i]); | |
6605 | else | |
6606 | { | |
6607 | rtx part = adjust_address (dest, BLKmode, offset); | |
65239d20 | 6608 | if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0)) |
ab77a036 RS |
6609 | gcc_unreachable (); |
6610 | } | |
6611 | ||
6612 | /* Mop up any left-over bytes. */ | |
6613 | if (offset < length) | |
a27fb29b | 6614 | { |
ab77a036 RS |
6615 | src = adjust_address (src, BLKmode, offset); |
6616 | dest = adjust_address (dest, BLKmode, offset); | |
6617 | move_by_pieces (dest, src, length - offset, | |
6618 | MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0); | |
cee98a59 | 6619 | } |
ab77a036 | 6620 | } |
f8151871 | 6621 | |
ab77a036 RS |
6622 | /* Helper function for doing a loop-based block operation on memory |
6623 | reference MEM. Each iteration of the loop will operate on LENGTH | |
6624 | bytes of MEM. | |
cee98a59 | 6625 | |
ab77a036 RS |
6626 | Create a new base register for use within the loop and point it to |
6627 | the start of MEM. Create a new memory reference that uses this | |
6628 | register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ | |
33563487 | 6629 | |
ab77a036 RS |
6630 | static void |
6631 | mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length, | |
6632 | rtx *loop_reg, rtx *loop_mem) | |
6633 | { | |
6634 | *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); | |
af34e51e | 6635 | |
ab77a036 RS |
6636 | /* Although the new mem does not refer to a known location, |
6637 | it does keep up to LENGTH bytes of alignment. */ | |
6638 | *loop_mem = change_address (mem, BLKmode, *loop_reg); | |
6639 | set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT)); | |
6640 | } | |
142ee136 | 6641 | |
a1c6b246 RS |
6642 | /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER |
6643 | bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that | |
6644 | the memory regions do not overlap. */ | |
d9870b7e | 6645 | |
ab77a036 | 6646 | static void |
a1c6b246 RS |
6647 | mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, |
6648 | HOST_WIDE_INT bytes_per_iter) | |
ab77a036 | 6649 | { |
f90b7a5a | 6650 | rtx label, src_reg, dest_reg, final_src, test; |
ab77a036 | 6651 | HOST_WIDE_INT leftover; |
8cb6400c | 6652 | |
a1c6b246 | 6653 | leftover = length % bytes_per_iter; |
ab77a036 | 6654 | length -= leftover; |
dc884a86 | 6655 | |
ab77a036 | 6656 | /* Create registers and memory references for use within the loop. */ |
a1c6b246 RS |
6657 | mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src); |
6658 | mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest); | |
cfa31150 | 6659 | |
ab77a036 RS |
6660 | /* Calculate the value that SRC_REG should have after the last iteration |
6661 | of the loop. */ | |
6662 | final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), | |
6663 | 0, 0, OPTAB_WIDEN); | |
6664 | ||
6665 | /* Emit the start of the loop. */ | |
6666 | label = gen_label_rtx (); | |
6667 | emit_label (label); | |
6668 | ||
6669 | /* Emit the loop body. */ | |
a1c6b246 | 6670 | mips_block_move_straight (dest, src, bytes_per_iter); |
ab77a036 RS |
6671 | |
6672 | /* Move on to the next block. */ | |
a1c6b246 RS |
6673 | mips_emit_move (src_reg, plus_constant (src_reg, bytes_per_iter)); |
6674 | mips_emit_move (dest_reg, plus_constant (dest_reg, bytes_per_iter)); | |
ab77a036 RS |
6675 | |
6676 | /* Emit the loop condition. */ | |
f90b7a5a | 6677 | test = gen_rtx_NE (VOIDmode, src_reg, final_src); |
ab77a036 | 6678 | if (Pmode == DImode) |
f90b7a5a | 6679 | emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label)); |
ab77a036 | 6680 | else |
f90b7a5a | 6681 | emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label)); |
ab77a036 RS |
6682 | |
6683 | /* Mop up any left-over bytes. */ | |
6684 | if (leftover) | |
6685 | mips_block_move_straight (dest, src, leftover); | |
6686 | } | |
6687 | ||
65239d20 RS |
6688 | /* Expand a movmemsi instruction, which copies LENGTH bytes from |
6689 | memory reference SRC to memory reference DEST. */ | |
ab77a036 RS |
6690 | |
6691 | bool | |
6692 | mips_expand_block_move (rtx dest, rtx src, rtx length) | |
6693 | { | |
47ac44d6 | 6694 | if (CONST_INT_P (length)) |
a318179e | 6695 | { |
a1c6b246 | 6696 | if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT) |
a318179e | 6697 | { |
ab77a036 RS |
6698 | mips_block_move_straight (dest, src, INTVAL (length)); |
6699 | return true; | |
a318179e | 6700 | } |
ab77a036 | 6701 | else if (optimize) |
a318179e | 6702 | { |
a1c6b246 RS |
6703 | mips_block_move_loop (dest, src, INTVAL (length), |
6704 | MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER); | |
ab77a036 | 6705 | return true; |
a318179e RS |
6706 | } |
6707 | } | |
ab77a036 RS |
6708 | return false; |
6709 | } | |
6710 | \f | |
ab77a036 | 6711 | /* Expand a loop of synci insns for the address range [BEGIN, END). */ |
cafe096b | 6712 | |
ab77a036 RS |
6713 | void |
6714 | mips_expand_synci_loop (rtx begin, rtx end) | |
6715 | { | |
d48a3196 CF |
6716 | rtx inc, label, end_label, cmp_result, mask, length; |
6717 | ||
6718 | /* Create end_label. */ | |
6719 | end_label = gen_label_rtx (); | |
6720 | ||
6721 | /* Check if begin equals end. */ | |
6722 | cmp_result = gen_rtx_EQ (VOIDmode, begin, end); | |
6723 | emit_jump_insn (gen_condjump (cmp_result, end_label)); | |
06a4ab70 | 6724 | |
65239d20 | 6725 | /* Load INC with the cache line size (rdhwr INC,$1). */ |
9d50ba21 AN |
6726 | inc = gen_reg_rtx (Pmode); |
6727 | emit_insn (Pmode == SImode | |
6728 | ? gen_rdhwr_synci_step_si (inc) | |
6729 | : gen_rdhwr_synci_step_di (inc)); | |
06a4ab70 | 6730 | |
d48a3196 CF |
6731 | /* Check if inc is 0. */ |
6732 | cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx); | |
6733 | emit_jump_insn (gen_condjump (cmp_result, end_label)); | |
6734 | ||
6735 | /* Calculate mask. */ | |
6736 | mask = mips_force_unary (Pmode, NEG, inc); | |
6737 | ||
6738 | /* Mask out begin by mask. */ | |
6739 | begin = mips_force_binary (Pmode, AND, begin, mask); | |
6740 | ||
6741 | /* Calculate length. */ | |
6742 | length = mips_force_binary (Pmode, MINUS, end, begin); | |
6743 | ||
ab77a036 RS |
6744 | /* Loop back to here. */ |
6745 | label = gen_label_rtx (); | |
6746 | emit_label (label); | |
06a4ab70 | 6747 | |
ab77a036 | 6748 | emit_insn (gen_synci (begin)); |
06a4ab70 | 6749 | |
d48a3196 CF |
6750 | /* Update length. */ |
6751 | mips_emit_binary (MINUS, length, length, inc); | |
32041385 | 6752 | |
d48a3196 | 6753 | /* Update begin. */ |
ab77a036 | 6754 | mips_emit_binary (PLUS, begin, begin, inc); |
cee98a59 | 6755 | |
d48a3196 CF |
6756 | /* Check if length is greater than 0. */ |
6757 | cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx); | |
ab77a036 | 6758 | emit_jump_insn (gen_condjump (cmp_result, label)); |
d48a3196 CF |
6759 | |
6760 | emit_label (end_label); | |
ab77a036 RS |
6761 | } |
6762 | \f | |
06d19617 DD |
6763 | /* Expand a QI or HI mode atomic memory operation. |
6764 | ||
6765 | GENERATOR contains a pointer to the gen_* function that generates | |
6766 | the SI mode underlying atomic operation using masks that we | |
6767 | calculate. | |
6768 | ||
6769 | RESULT is the return register for the operation. Its value is NULL | |
6770 | if unused. | |
6771 | ||
6772 | MEM is the location of the atomic access. | |
6773 | ||
6774 | OLDVAL is the first operand for the operation. | |
6775 | ||
6776 | NEWVAL is the optional second operand for the operation. Its value | |
6777 | is NULL if unused. */ | |
49bce30a RS |
6778 | |
6779 | void | |
06d19617 DD |
6780 | mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator, |
6781 | rtx result, rtx mem, rtx oldval, rtx newval) | |
49bce30a RS |
6782 | { |
6783 | rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask; | |
06d19617 DD |
6784 | rtx unshifted_mask_reg, mask, inverted_mask, si_op; |
6785 | rtx res = NULL; | |
977502ff DD |
6786 | enum machine_mode mode; |
6787 | ||
6788 | mode = GET_MODE (mem); | |
49bce30a RS |
6789 | |
6790 | /* Compute the address of the containing SImode value. */ | |
6791 | orig_addr = force_reg (Pmode, XEXP (mem, 0)); | |
6792 | memsi_addr = mips_force_binary (Pmode, AND, orig_addr, | |
6793 | force_reg (Pmode, GEN_INT (-4))); | |
6794 | ||
6795 | /* Create a memory reference for it. */ | |
6796 | memsi = gen_rtx_MEM (SImode, memsi_addr); | |
6797 | set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER); | |
6798 | MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem); | |
6799 | ||
6800 | /* Work out the byte offset of the QImode or HImode value, | |
6801 | counting from the least significant byte. */ | |
6802 | shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3)); | |
6803 | if (TARGET_BIG_ENDIAN) | |
977502ff | 6804 | mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2)); |
49bce30a RS |
6805 | |
6806 | /* Multiply by eight to convert the shift value from bytes to bits. */ | |
6807 | mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3)); | |
6808 | ||
6809 | /* Make the final shift an SImode value, so that it can be used in | |
6810 | SImode operations. */ | |
6811 | shiftsi = force_reg (SImode, gen_lowpart (SImode, shift)); | |
6812 | ||
6813 | /* Set MASK to an inclusive mask of the QImode or HImode value. */ | |
977502ff DD |
6814 | unshifted_mask = GEN_INT (GET_MODE_MASK (mode)); |
6815 | unshifted_mask_reg = force_reg (SImode, unshifted_mask); | |
6816 | mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi); | |
49bce30a RS |
6817 | |
6818 | /* Compute the equivalent exclusive mask. */ | |
6819 | inverted_mask = gen_reg_rtx (SImode); | |
6820 | emit_insn (gen_rtx_SET (VOIDmode, inverted_mask, | |
6821 | gen_rtx_NOT (SImode, mask))); | |
6822 | ||
6823 | /* Shift the old value into place. */ | |
977502ff DD |
6824 | if (oldval != const0_rtx) |
6825 | { | |
6826 | oldval = convert_modes (SImode, mode, oldval, true); | |
6827 | oldval = force_reg (SImode, oldval); | |
6828 | oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi); | |
6829 | } | |
49bce30a RS |
6830 | |
6831 | /* Do the same for the new value. */ | |
06d19617 | 6832 | if (newval && newval != const0_rtx) |
977502ff DD |
6833 | { |
6834 | newval = convert_modes (SImode, mode, newval, true); | |
6835 | newval = force_reg (SImode, newval); | |
6836 | newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi); | |
6837 | } | |
49bce30a RS |
6838 | |
6839 | /* Do the SImode atomic access. */ | |
06d19617 DD |
6840 | if (result) |
6841 | res = gen_reg_rtx (SImode); | |
6842 | if (newval) | |
6843 | si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval); | |
6844 | else if (result) | |
6845 | si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval); | |
6846 | else | |
6847 | si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval); | |
6848 | ||
6849 | emit_insn (si_op); | |
6850 | ||
6851 | if (result) | |
6852 | { | |
6853 | /* Shift and convert the result. */ | |
6854 | mips_emit_binary (AND, res, res, mask); | |
6855 | mips_emit_binary (LSHIFTRT, res, res, shiftsi); | |
6856 | mips_emit_move (result, gen_lowpart (GET_MODE (result), res)); | |
6857 | } | |
49bce30a RS |
6858 | } |
6859 | ||
ab77a036 RS |
6860 | /* Return true if it is possible to use left/right accesses for a |
6861 | bitfield of WIDTH bits starting BITPOS bits into *OP. When | |
6862 | returning true, update *OP, *LEFT and *RIGHT as follows: | |
cee98a59 | 6863 | |
ab77a036 | 6864 | *OP is a BLKmode reference to the whole field. |
cee98a59 | 6865 | |
ab77a036 RS |
6866 | *LEFT is a QImode reference to the first byte if big endian or |
6867 | the last byte if little endian. This address can be used in the | |
65239d20 | 6868 | left-side instructions (LWL, SWL, LDL, SDL). |
cee98a59 | 6869 | |
ab77a036 RS |
6870 | *RIGHT is a QImode reference to the opposite end of the field and |
6871 | can be used in the patterning right-side instruction. */ | |
cee98a59 | 6872 | |
ab77a036 | 6873 | static bool |
65239d20 | 6874 | mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos, |
ab77a036 RS |
6875 | rtx *left, rtx *right) |
6876 | { | |
6877 | rtx first, last; | |
77d4f3a4 | 6878 | |
ab77a036 RS |
6879 | /* Check that the operand really is a MEM. Not all the extv and |
6880 | extzv predicates are checked. */ | |
6881 | if (!MEM_P (*op)) | |
6882 | return false; | |
cee98a59 | 6883 | |
ab77a036 RS |
6884 | /* Check that the size is valid. */ |
6885 | if (width != 32 && (!TARGET_64BIT || width != 64)) | |
6886 | return false; | |
cee98a59 | 6887 | |
ab77a036 RS |
6888 | /* We can only access byte-aligned values. Since we are always passed |
6889 | a reference to the first byte of the field, it is not necessary to | |
6890 | do anything with BITPOS after this check. */ | |
6891 | if (bitpos % BITS_PER_UNIT != 0) | |
6892 | return false; | |
34b650b3 | 6893 | |
ab77a036 RS |
6894 | /* Reject aligned bitfields: we want to use a normal load or store |
6895 | instead of a left/right pair. */ | |
6896 | if (MEM_ALIGN (*op) >= width) | |
6897 | return false; | |
06a4ab70 | 6898 | |
ab77a036 RS |
6899 | /* Adjust *OP to refer to the whole field. This also has the effect |
6900 | of legitimizing *OP's address for BLKmode, possibly simplifying it. */ | |
6901 | *op = adjust_address (*op, BLKmode, 0); | |
6902 | set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT)); | |
06a4ab70 | 6903 | |
ab77a036 RS |
6904 | /* Get references to both ends of the field. We deliberately don't |
6905 | use the original QImode *OP for FIRST since the new BLKmode one | |
6906 | might have a simpler address. */ | |
6907 | first = adjust_address (*op, QImode, 0); | |
6908 | last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1); | |
cee98a59 | 6909 | |
ab77a036 | 6910 | /* Allocate to LEFT and RIGHT according to endianness. LEFT should |
65239d20 | 6911 | correspond to the MSB and RIGHT to the LSB. */ |
ab77a036 RS |
6912 | if (TARGET_BIG_ENDIAN) |
6913 | *left = first, *right = last; | |
6914 | else | |
6915 | *left = last, *right = first; | |
cee98a59 | 6916 | |
ab77a036 RS |
6917 | return true; |
6918 | } | |
cee98a59 | 6919 | |
65239d20 RS |
6920 | /* Try to use left/right loads to expand an "extv" or "extzv" pattern. |
6921 | DEST, SRC, WIDTH and BITPOS are the operands passed to the expander; | |
6922 | the operation is the equivalent of: | |
6923 | ||
6924 | (set DEST (*_extract SRC WIDTH BITPOS)) | |
cee98a59 | 6925 | |
65239d20 | 6926 | Return true on success. */ |
cee98a59 | 6927 | |
ab77a036 | 6928 | bool |
65239d20 RS |
6929 | mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width, |
6930 | HOST_WIDE_INT bitpos) | |
ab77a036 RS |
6931 | { |
6932 | rtx left, right, temp; | |
6933 | ||
65239d20 RS |
6934 | /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will |
6935 | be a paradoxical word_mode subreg. This is the only case in which | |
ab77a036 RS |
6936 | we allow the destination to be larger than the source. */ |
6937 | if (GET_CODE (dest) == SUBREG | |
6938 | && GET_MODE (dest) == DImode | |
ab77a036 RS |
6939 | && GET_MODE (SUBREG_REG (dest)) == SImode) |
6940 | dest = SUBREG_REG (dest); | |
6941 | ||
6942 | /* After the above adjustment, the destination must be the same | |
6943 | width as the source. */ | |
6944 | if (GET_MODE_BITSIZE (GET_MODE (dest)) != width) | |
6945 | return false; | |
6946 | ||
6947 | if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right)) | |
6948 | return false; | |
6949 | ||
6950 | temp = gen_reg_rtx (GET_MODE (dest)); | |
6951 | if (GET_MODE (dest) == DImode) | |
6952 | { | |
6953 | emit_insn (gen_mov_ldl (temp, src, left)); | |
6954 | emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp)); | |
6955 | } | |
6956 | else | |
6957 | { | |
6958 | emit_insn (gen_mov_lwl (temp, src, left)); | |
6959 | emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp)); | |
cee98a59 | 6960 | } |
ab77a036 RS |
6961 | return true; |
6962 | } | |
bfed8dac | 6963 | |
65239d20 RS |
6964 | /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH, |
6965 | BITPOS and SRC are the operands passed to the expander; the operation | |
6966 | is the equivalent of: | |
6967 | ||
6968 | (set (zero_extract DEST WIDTH BITPOS) SRC) | |
efa3896a | 6969 | |
65239d20 | 6970 | Return true on success. */ |
cafe096b | 6971 | |
ab77a036 | 6972 | bool |
65239d20 RS |
6973 | mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width, |
6974 | HOST_WIDE_INT bitpos) | |
ab77a036 RS |
6975 | { |
6976 | rtx left, right; | |
6977 | enum machine_mode mode; | |
6ba7b547 | 6978 | |
ab77a036 RS |
6979 | if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right)) |
6980 | return false; | |
f9e4a411 | 6981 | |
ab77a036 RS |
6982 | mode = mode_for_size (width, MODE_INT, 0); |
6983 | src = gen_lowpart (mode, src); | |
ab77a036 RS |
6984 | if (mode == DImode) |
6985 | { | |
6986 | emit_insn (gen_mov_sdl (dest, src, left)); | |
6987 | emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right)); | |
6988 | } | |
6989 | else | |
6990 | { | |
6991 | emit_insn (gen_mov_swl (dest, src, left)); | |
6992 | emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right)); | |
6993 | } | |
6994 | return true; | |
c8d1b2b7 AO |
6995 | } |
6996 | ||
ab77a036 | 6997 | /* Return true if X is a MEM with the same size as MODE. */ |
48156a39 | 6998 | |
ab77a036 RS |
6999 | bool |
7000 | mips_mem_fits_mode_p (enum machine_mode mode, rtx x) | |
48156a39 | 7001 | { |
ab77a036 | 7002 | rtx size; |
48156a39 | 7003 | |
ab77a036 RS |
7004 | if (!MEM_P (x)) |
7005 | return false; | |
48156a39 | 7006 | |
ab77a036 RS |
7007 | size = MEM_SIZE (x); |
7008 | return size && INTVAL (size) == GET_MODE_SIZE (mode); | |
48156a39 NS |
7009 | } |
7010 | ||
65239d20 | 7011 | /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the |
ab77a036 RS |
7012 | source of an "ext" instruction or the destination of an "ins" |
7013 | instruction. OP must be a register operand and the following | |
7014 | conditions must hold: | |
ac8ab9fe | 7015 | |
65239d20 RS |
7016 | 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op)) |
7017 | 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op)) | |
7018 | 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op)) | |
ab77a036 RS |
7019 | |
7020 | Also reject lengths equal to a word as they are better handled | |
7021 | by the move patterns. */ | |
7022 | ||
7023 | bool | |
65239d20 | 7024 | mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos) |
ac8ab9fe | 7025 | { |
ab77a036 RS |
7026 | if (!ISA_HAS_EXT_INS |
7027 | || !register_operand (op, VOIDmode) | |
7028 | || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD) | |
7029 | return false; | |
ac8ab9fe | 7030 | |
65239d20 RS |
7031 | if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1)) |
7032 | return false; | |
ac8ab9fe | 7033 | |
65239d20 | 7034 | if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op))) |
ab77a036 RS |
7035 | return false; |
7036 | ||
7037 | return true; | |
ac8ab9fe | 7038 | } |
49912bcd AN |
7039 | |
7040 | /* Check if MASK and SHIFT are valid in mask-low-and-shift-left | |
7041 | operation if MAXLEN is the maxium length of consecutive bits that | |
7042 | can make up MASK. MODE is the mode of the operation. See | |
7043 | mask_low_and_shift_len for the actual definition. */ | |
7044 | ||
7045 | bool | |
7046 | mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen) | |
7047 | { | |
7048 | return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen); | |
7049 | } | |
7050 | ||
b2c9d70f AN |
7051 | /* Return true iff OP1 and OP2 are valid operands together for the |
7052 | *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider, | |
7053 | see the table in the comment before the pattern. */ | |
7054 | ||
7055 | bool | |
7056 | and_operands_ok (enum machine_mode mode, rtx op1, rtx op2) | |
7057 | { | |
7058 | return (memory_operand (op1, mode) | |
7059 | ? and_load_operand (op2, mode) | |
7060 | : and_reg_operand (op2, mode)); | |
7061 | } | |
7062 | ||
49912bcd AN |
7063 | /* The canonical form of a mask-low-and-shift-left operation is |
7064 | (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits | |
7065 | cleared. Thus we need to shift MASK to the right before checking if it | |
7066 | is a valid mask value. MODE is the mode of the operation. If true | |
7067 | return the length of the mask, otherwise return -1. */ | |
7068 | ||
7069 | int | |
7070 | mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift) | |
7071 | { | |
7072 | HOST_WIDE_INT shval; | |
7073 | ||
7074 | shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1); | |
7075 | return exact_log2 ((UINTVAL (mask) >> shval) + 1); | |
7076 | } | |
ab77a036 | 7077 | \f |
65239d20 | 7078 | /* Return true if -msplit-addresses is selected and should be honored. |
ac8ab9fe | 7079 | |
65239d20 RS |
7080 | -msplit-addresses is a half-way house between explicit relocations |
7081 | and the traditional assembler macros. It can split absolute 32-bit | |
7082 | symbolic constants into a high/lo_sum pair but uses macros for other | |
7083 | sorts of access. | |
ab77a036 RS |
7084 | |
7085 | Like explicit relocation support for REL targets, it relies | |
7086 | on GNU extensions in the assembler and the linker. | |
7087 | ||
7088 | Although this code should work for -O0, it has traditionally | |
7089 | been treated as an optimization. */ | |
7090 | ||
65239d20 RS |
7091 | static bool |
7092 | mips_split_addresses_p (void) | |
c8d1b2b7 | 7093 | { |
65239d20 RS |
7094 | return (TARGET_SPLIT_ADDRESSES |
7095 | && optimize | |
7096 | && !TARGET_MIPS16 | |
7097 | && !flag_pic | |
7098 | && !ABI_HAS_64BIT_SYMBOLS); | |
cee98a59 MM |
7099 | } |
7100 | ||
65239d20 | 7101 | /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */ |
2bcb2ab3 | 7102 | |
ab77a036 RS |
7103 | static void |
7104 | mips_init_relocs (void) | |
2bcb2ab3 | 7105 | { |
ab77a036 | 7106 | memset (mips_split_p, '\0', sizeof (mips_split_p)); |
08d0963a | 7107 | memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p)); |
ab77a036 RS |
7108 | memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs)); |
7109 | memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs)); | |
2bcb2ab3 | 7110 | |
ab77a036 RS |
7111 | if (ABI_HAS_64BIT_SYMBOLS) |
7112 | { | |
7113 | if (TARGET_EXPLICIT_RELOCS) | |
7114 | { | |
7115 | mips_split_p[SYMBOL_64_HIGH] = true; | |
7116 | mips_hi_relocs[SYMBOL_64_HIGH] = "%highest("; | |
7117 | mips_lo_relocs[SYMBOL_64_HIGH] = "%higher("; | |
7118 | ||
7119 | mips_split_p[SYMBOL_64_MID] = true; | |
7120 | mips_hi_relocs[SYMBOL_64_MID] = "%higher("; | |
7121 | mips_lo_relocs[SYMBOL_64_MID] = "%hi("; | |
7122 | ||
7123 | mips_split_p[SYMBOL_64_LOW] = true; | |
7124 | mips_hi_relocs[SYMBOL_64_LOW] = "%hi("; | |
7125 | mips_lo_relocs[SYMBOL_64_LOW] = "%lo("; | |
7126 | ||
7127 | mips_split_p[SYMBOL_ABSOLUTE] = true; | |
7128 | mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; | |
7129 | } | |
7130 | } | |
7131 | else | |
7132 | { | |
65239d20 | 7133 | if (TARGET_EXPLICIT_RELOCS || mips_split_addresses_p () || TARGET_MIPS16) |
ab77a036 RS |
7134 | { |
7135 | mips_split_p[SYMBOL_ABSOLUTE] = true; | |
7136 | mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi("; | |
7137 | mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo("; | |
7138 | ||
7139 | mips_lo_relocs[SYMBOL_32_HIGH] = "%hi("; | |
7140 | } | |
7141 | } | |
2bcb2ab3 GK |
7142 | |
7143 | if (TARGET_MIPS16) | |
7144 | { | |
ab77a036 RS |
7145 | /* The high part is provided by a pseudo copy of $gp. */ |
7146 | mips_split_p[SYMBOL_GP_RELATIVE] = true; | |
7147 | mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel("; | |
2bcb2ab3 | 7148 | } |
08d0963a RS |
7149 | else if (TARGET_EXPLICIT_RELOCS) |
7150 | /* Small data constants are kept whole until after reload, | |
7151 | then lowered by mips_rewrite_small_data. */ | |
7152 | mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel("; | |
2bcb2ab3 | 7153 | |
ab77a036 RS |
7154 | if (TARGET_EXPLICIT_RELOCS) |
7155 | { | |
ab77a036 RS |
7156 | mips_split_p[SYMBOL_GOT_PAGE_OFST] = true; |
7157 | if (TARGET_NEWABI) | |
7158 | { | |
7159 | mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page("; | |
7160 | mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst("; | |
7161 | } | |
7162 | else | |
7163 | { | |
7164 | mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got("; | |
7165 | mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo("; | |
7166 | } | |
08d0963a RS |
7167 | if (TARGET_MIPS16) |
7168 | /* Expose the use of $28 as soon as possible. */ | |
7169 | mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true; | |
cee98a59 | 7170 | |
ab77a036 RS |
7171 | if (TARGET_XGOT) |
7172 | { | |
7173 | /* The HIGH and LO_SUM are matched by special .md patterns. */ | |
7174 | mips_split_p[SYMBOL_GOT_DISP] = true; | |
cee98a59 | 7175 | |
ab77a036 RS |
7176 | mips_split_p[SYMBOL_GOTOFF_DISP] = true; |
7177 | mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi("; | |
7178 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo("; | |
c831afd5 | 7179 | |
ab77a036 RS |
7180 | mips_split_p[SYMBOL_GOTOFF_CALL] = true; |
7181 | mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi("; | |
7182 | mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo("; | |
7183 | } | |
7184 | else | |
7185 | { | |
7186 | if (TARGET_NEWABI) | |
7187 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp("; | |
7188 | else | |
7189 | mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got("; | |
7190 | mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16("; | |
08d0963a RS |
7191 | if (TARGET_MIPS16) |
7192 | /* Expose the use of $28 as soon as possible. */ | |
7193 | mips_split_p[SYMBOL_GOT_DISP] = true; | |
ab77a036 RS |
7194 | } |
7195 | } | |
a50f2a09 | 7196 | |
ab77a036 RS |
7197 | if (TARGET_NEWABI) |
7198 | { | |
7199 | mips_split_p[SYMBOL_GOTOFF_LOADGP] = true; | |
7200 | mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel("; | |
7201 | mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel("; | |
c831afd5 | 7202 | } |
f5963e61 | 7203 | |
ab77a036 RS |
7204 | mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd("; |
7205 | mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm("; | |
65239d20 RS |
7206 | |
7207 | mips_split_p[SYMBOL_DTPREL] = true; | |
ab77a036 RS |
7208 | mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi("; |
7209 | mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo("; | |
65239d20 | 7210 | |
ab77a036 | 7211 | mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel("; |
65239d20 RS |
7212 | |
7213 | mips_split_p[SYMBOL_TPREL] = true; | |
ab77a036 RS |
7214 | mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi("; |
7215 | mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo("; | |
cee98a59 | 7216 | |
ab77a036 | 7217 | mips_lo_relocs[SYMBOL_HALF] = "%half("; |
cee98a59 | 7218 | } |
ab77a036 | 7219 | |
ab77a036 RS |
7220 | /* Print symbolic operand OP, which is part of a HIGH or LO_SUM |
7221 | in context CONTEXT. RELOCS is the array of relocations to use. */ | |
7222 | ||
7223 | static void | |
65239d20 RS |
7224 | mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context, |
7225 | const char **relocs) | |
ab77a036 RS |
7226 | { |
7227 | enum mips_symbol_type symbol_type; | |
7228 | const char *p; | |
7229 | ||
7230 | symbol_type = mips_classify_symbolic_expression (op, context); | |
65239d20 | 7231 | gcc_assert (relocs[symbol_type]); |
ab77a036 RS |
7232 | |
7233 | fputs (relocs[symbol_type], file); | |
7234 | output_addr_const (file, mips_strip_unspec_address (op)); | |
7235 | for (p = relocs[symbol_type]; *p != 0; p++) | |
7236 | if (*p == '(') | |
7237 | fputc (')', file); | |
7238 | } | |
7239 | ||
cf5fb4b0 RS |
7240 | /* Start a new block with the given asm switch enabled. If we need |
7241 | to print a directive, emit PREFIX before it and SUFFIX after it. */ | |
7242 | ||
7243 | static void | |
7244 | mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch, | |
7245 | const char *prefix, const char *suffix) | |
7246 | { | |
7247 | if (asm_switch->nesting_level == 0) | |
7248 | fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix); | |
7249 | asm_switch->nesting_level++; | |
7250 | } | |
7251 | ||
7252 | /* Likewise, but end a block. */ | |
7253 | ||
7254 | static void | |
7255 | mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch, | |
7256 | const char *prefix, const char *suffix) | |
7257 | { | |
7258 | gcc_assert (asm_switch->nesting_level); | |
7259 | asm_switch->nesting_level--; | |
7260 | if (asm_switch->nesting_level == 0) | |
7261 | fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix); | |
7262 | } | |
7263 | ||
7264 | /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1 | |
7265 | that either print a complete line or print nothing. */ | |
7266 | ||
7267 | void | |
7268 | mips_push_asm_switch (struct mips_asm_switch *asm_switch) | |
7269 | { | |
7270 | mips_push_asm_switch_1 (asm_switch, "\t", "\n"); | |
7271 | } | |
7272 | ||
7273 | void | |
7274 | mips_pop_asm_switch (struct mips_asm_switch *asm_switch) | |
7275 | { | |
7276 | mips_pop_asm_switch_1 (asm_switch, "\t", "\n"); | |
7277 | } | |
7278 | ||
07045266 | 7279 | /* Print the text for PRINT_OPERAND punctation character CH to FILE. |
dfad12b5 RS |
7280 | The punctuation characters are: |
7281 | ||
07045266 RS |
7282 | '(' Start a nested ".set noreorder" block. |
7283 | ')' End a nested ".set noreorder" block. | |
7284 | '[' Start a nested ".set noat" block. | |
7285 | ']' End a nested ".set noat" block. | |
7286 | '<' Start a nested ".set nomacro" block. | |
7287 | '>' End a nested ".set nomacro" block. | |
7288 | '*' Behave like %(%< if generating a delayed-branch sequence. | |
7289 | '#' Print a nop if in a ".set noreorder" block. | |
7290 | '/' Like '#', but do nothing within a delayed-branch sequence. | |
7291 | '?' Print "l" if mips_branch_likely is true | |
ee9a72e5 | 7292 | '~' Print a nop if mips_branch_likely is true |
ffa9d0b1 | 7293 | '.' Print the name of the register with a hard-wired zero (zero or $0). |
07045266 | 7294 | '@' Print the name of the assembler temporary register (at or $1). |
2bcb2ab3 | 7295 | '^' Print the name of the pic call-through register (t9 or $25). |
f833ffd4 | 7296 | '+' Print the name of the gp register (usually gp or $28). |
07045266 | 7297 | '$' Print the name of the stack pointer register (sp or $29). |
cee98a59 | 7298 | |
07045266 | 7299 | See also mips_init_print_operand_pucnt. */ |
cee98a59 | 7300 | |
07045266 RS |
7301 | static void |
7302 | mips_print_operand_punctuation (FILE *file, int ch) | |
7303 | { | |
7304 | switch (ch) | |
cee98a59 | 7305 | { |
07045266 | 7306 | case '(': |
cf5fb4b0 | 7307 | mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t"); |
07045266 | 7308 | break; |
cee98a59 | 7309 | |
07045266 | 7310 | case ')': |
cf5fb4b0 | 7311 | mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", ""); |
07045266 | 7312 | break; |
cee98a59 | 7313 | |
07045266 | 7314 | case '[': |
cf5fb4b0 | 7315 | mips_push_asm_switch_1 (&mips_noat, "", "\n\t"); |
07045266 | 7316 | break; |
ffa9d0b1 | 7317 | |
07045266 | 7318 | case ']': |
cf5fb4b0 | 7319 | mips_pop_asm_switch_1 (&mips_noat, "\n\t", ""); |
07045266 | 7320 | break; |
cee98a59 | 7321 | |
07045266 | 7322 | case '<': |
cf5fb4b0 | 7323 | mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t"); |
07045266 | 7324 | break; |
2bcb2ab3 | 7325 | |
07045266 | 7326 | case '>': |
cf5fb4b0 | 7327 | mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", ""); |
07045266 | 7328 | break; |
2bcb2ab3 | 7329 | |
07045266 RS |
7330 | case '*': |
7331 | if (final_sequence != 0) | |
7332 | { | |
7333 | mips_print_operand_punctuation (file, '('); | |
7334 | mips_print_operand_punctuation (file, '<'); | |
7335 | } | |
7336 | break; | |
cee98a59 | 7337 | |
07045266 | 7338 | case '#': |
cf5fb4b0 | 7339 | if (mips_noreorder.nesting_level > 0) |
07045266 RS |
7340 | fputs ("\n\tnop", file); |
7341 | break; | |
cee98a59 | 7342 | |
07045266 RS |
7343 | case '/': |
7344 | /* Print an extra newline so that the delayed insn is separated | |
7345 | from the following ones. This looks neater and is consistent | |
7346 | with non-nop delayed sequences. */ | |
cf5fb4b0 | 7347 | if (mips_noreorder.nesting_level > 0 && final_sequence == 0) |
07045266 RS |
7348 | fputs ("\n\tnop\n", file); |
7349 | break; | |
cee98a59 | 7350 | |
07045266 RS |
7351 | case '?': |
7352 | if (mips_branch_likely) | |
7353 | putc ('l', file); | |
7354 | break; | |
cee98a59 | 7355 | |
ee9a72e5 JK |
7356 | case '~': |
7357 | if (mips_branch_likely) | |
7358 | fputs ("\n\tnop", file); | |
7359 | break; | |
7360 | ||
07045266 RS |
7361 | case '.': |
7362 | fputs (reg_names[GP_REG_FIRST + 0], file); | |
7363 | break; | |
cee98a59 | 7364 | |
07045266 | 7365 | case '@': |
293593b1 | 7366 | fputs (reg_names[AT_REGNUM], file); |
07045266 | 7367 | break; |
6f2993e5 | 7368 | |
07045266 RS |
7369 | case '^': |
7370 | fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file); | |
7371 | break; | |
cee98a59 | 7372 | |
07045266 RS |
7373 | case '+': |
7374 | fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file); | |
7375 | break; | |
cee98a59 | 7376 | |
07045266 RS |
7377 | case '$': |
7378 | fputs (reg_names[STACK_POINTER_REGNUM], file); | |
7379 | break; | |
cee98a59 | 7380 | |
07045266 RS |
7381 | default: |
7382 | gcc_unreachable (); | |
7383 | break; | |
7384 | } | |
7385 | } | |
cee98a59 | 7386 | |
07045266 | 7387 | /* Initialize mips_print_operand_punct. */ |
cee98a59 | 7388 | |
07045266 RS |
7389 | static void |
7390 | mips_init_print_operand_punct (void) | |
7391 | { | |
7392 | const char *p; | |
cee98a59 | 7393 | |
6f5a62e9 | 7394 | for (p = "()[]<>*#/?~.@^+$"; *p; p++) |
07045266 RS |
7395 | mips_print_operand_punct[(unsigned char) *p] = true; |
7396 | } | |
cee98a59 | 7397 | |
07045266 RS |
7398 | /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction |
7399 | associated with condition CODE. Print the condition part of the | |
7400 | opcode to FILE. */ | |
cee98a59 | 7401 | |
07045266 RS |
7402 | static void |
7403 | mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter) | |
7404 | { | |
7405 | switch (code) | |
7406 | { | |
7407 | case EQ: | |
7408 | case NE: | |
7409 | case GT: | |
7410 | case GE: | |
7411 | case LT: | |
7412 | case LE: | |
7413 | case GTU: | |
7414 | case GEU: | |
7415 | case LTU: | |
7416 | case LEU: | |
7417 | /* Conveniently, the MIPS names for these conditions are the same | |
7418 | as their RTL equivalents. */ | |
7419 | fputs (GET_RTX_NAME (code), file); | |
7420 | break; | |
cee98a59 | 7421 | |
07045266 RS |
7422 | default: |
7423 | output_operand_lossage ("'%%%c' is not a valid operand prefix", letter); | |
7424 | break; | |
7425 | } | |
7426 | } | |
cee98a59 | 7427 | |
07045266 | 7428 | /* Likewise floating-point branches. */ |
f5963e61 | 7429 | |
07045266 RS |
7430 | static void |
7431 | mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter) | |
7432 | { | |
7433 | switch (code) | |
7434 | { | |
7435 | case EQ: | |
7436 | fputs ("c1f", file); | |
7437 | break; | |
efa3896a | 7438 | |
07045266 RS |
7439 | case NE: |
7440 | fputs ("c1t", file); | |
7441 | break; | |
66471b47 | 7442 | |
07045266 RS |
7443 | default: |
7444 | output_operand_lossage ("'%%%c' is not a valid operand prefix", letter); | |
7445 | break; | |
7446 | } | |
7447 | } | |
66471b47 | 7448 | |
6e9e0126 NF |
7449 | /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ |
7450 | ||
7451 | static bool | |
7452 | mips_print_operand_punct_valid_p (unsigned char code) | |
7453 | { | |
7454 | return mips_print_operand_punct[code]; | |
7455 | } | |
7456 | ||
7457 | /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are: | |
f5963e61 | 7458 | |
07045266 RS |
7459 | 'X' Print CONST_INT OP in hexadecimal format. |
7460 | 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format. | |
7461 | 'd' Print CONST_INT OP in decimal. | |
49912bcd | 7462 | 'm' Print one less than CONST_INT OP in decimal. |
07045266 RS |
7463 | 'h' Print the high-part relocation associated with OP, after stripping |
7464 | any outermost HIGH. | |
7465 | 'R' Print the low-part relocation associated with OP. | |
7466 | 'C' Print the integer branch condition for comparison OP. | |
7467 | 'N' Print the inverse of the integer branch condition for comparison OP. | |
7468 | 'F' Print the FPU branch condition for comparison OP. | |
7469 | 'W' Print the inverse of the FPU branch condition for comparison OP. | |
7470 | 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...), | |
7471 | 'z' for (eq:?I ...), 'n' for (ne:?I ...). | |
7472 | 't' Like 'T', but with the EQ/NE cases reversed | |
7473 | 'Y' Print mips_fp_conditions[INTVAL (OP)] | |
7474 | 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing. | |
7475 | 'q' Print a DSP accumulator register. | |
7476 | 'D' Print the second part of a double-word register or memory operand. | |
7477 | 'L' Print the low-order register in a double-word register operand. | |
7478 | 'M' Print high-order register in a double-word register operand. | |
7479 | 'z' Print $0 if OP is zero, otherwise print OP normally. */ | |
7480 | ||
6e9e0126 | 7481 | static void |
65239d20 | 7482 | mips_print_operand (FILE *file, rtx op, int letter) |
07045266 RS |
7483 | { |
7484 | enum rtx_code code; | |
cee98a59 | 7485 | |
6e9e0126 | 7486 | if (mips_print_operand_punct_valid_p (letter)) |
cee98a59 | 7487 | { |
07045266 | 7488 | mips_print_operand_punctuation (file, letter); |
cee98a59 MM |
7489 | return; |
7490 | } | |
7491 | ||
07045266 | 7492 | gcc_assert (op); |
cee98a59 | 7493 | code = GET_CODE (op); |
2a0b0bf5 | 7494 | |
07045266 RS |
7495 | switch (letter) |
7496 | { | |
7497 | case 'X': | |
47ac44d6 | 7498 | if (CONST_INT_P (op)) |
07045266 RS |
7499 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op)); |
7500 | else | |
7501 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7502 | break; | |
cee98a59 | 7503 | |
07045266 | 7504 | case 'x': |
47ac44d6 | 7505 | if (CONST_INT_P (op)) |
07045266 RS |
7506 | fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff); |
7507 | else | |
7508 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7509 | break; | |
0ff83799 | 7510 | |
07045266 | 7511 | case 'd': |
47ac44d6 | 7512 | if (CONST_INT_P (op)) |
07045266 RS |
7513 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op)); |
7514 | else | |
7515 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7516 | break; | |
0ff83799 | 7517 | |
49912bcd | 7518 | case 'm': |
47ac44d6 | 7519 | if (CONST_INT_P (op)) |
49912bcd AN |
7520 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1); |
7521 | else | |
7522 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
7523 | break; | |
7524 | ||
07045266 RS |
7525 | case 'h': |
7526 | if (code == HIGH) | |
108b61d5 | 7527 | op = XEXP (op, 0); |
65239d20 | 7528 | mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs); |
07045266 RS |
7529 | break; |
7530 | ||
7531 | case 'R': | |
65239d20 | 7532 | mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs); |
07045266 | 7533 | break; |
108b61d5 | 7534 | |
07045266 RS |
7535 | case 'C': |
7536 | mips_print_int_branch_condition (file, code, letter); | |
7537 | break; | |
108b61d5 | 7538 | |
07045266 RS |
7539 | case 'N': |
7540 | mips_print_int_branch_condition (file, reverse_condition (code), letter); | |
7541 | break; | |
7542 | ||
7543 | case 'F': | |
7544 | mips_print_float_branch_condition (file, code, letter); | |
7545 | break; | |
7546 | ||
7547 | case 'W': | |
7548 | mips_print_float_branch_condition (file, reverse_condition (code), | |
7549 | letter); | |
7550 | break; | |
7551 | ||
7552 | case 'T': | |
7553 | case 't': | |
7554 | { | |
7555 | int truth = (code == NE) == (letter == 'T'); | |
7556 | fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file); | |
7557 | } | |
7558 | break; | |
7559 | ||
7560 | case 'Y': | |
7561 | if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions)) | |
7562 | fputs (mips_fp_conditions[UINTVAL (op)], file); | |
308cd611 | 7563 | else |
07045266 RS |
7564 | output_operand_lossage ("'%%%c' is not a valid operand prefix", |
7565 | letter); | |
7566 | break; | |
06a4ab70 | 7567 | |
07045266 | 7568 | case 'Z': |
308cd611 RS |
7569 | if (ISA_HAS_8CC) |
7570 | { | |
65239d20 | 7571 | mips_print_operand (file, op, 0); |
308cd611 RS |
7572 | fputc (',', file); |
7573 | } | |
07045266 | 7574 | break; |
118ea793 | 7575 | |
07045266 RS |
7576 | case 'q': |
7577 | if (code == REG && MD_REG_P (REGNO (op))) | |
118ea793 | 7578 | fprintf (file, "$ac0"); |
07045266 RS |
7579 | else if (code == REG && DSP_ACC_REG_P (REGNO (op))) |
7580 | fprintf (file, "$ac%c", reg_names[REGNO (op)][3]); | |
51c6b247 | 7581 | else |
07045266 RS |
7582 | output_operand_lossage ("invalid use of '%%%c'", letter); |
7583 | break; | |
cee98a59 | 7584 | |
07045266 RS |
7585 | default: |
7586 | switch (code) | |
7587 | { | |
7588 | case REG: | |
7589 | { | |
7590 | unsigned int regno = REGNO (op); | |
7591 | if ((letter == 'M' && TARGET_LITTLE_ENDIAN) | |
7592 | || (letter == 'L' && TARGET_BIG_ENDIAN) | |
7593 | || letter == 'D') | |
7594 | regno++; | |
b0907a6c AN |
7595 | else if (letter && letter != 'z' && letter != 'M' && letter != 'L') |
7596 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
e19da24c CF |
7597 | /* We need to print $0 .. $31 for COP0 registers. */ |
7598 | if (COP0_REG_P (regno)) | |
7599 | fprintf (file, "$%s", ®_names[regno][4]); | |
7600 | else | |
7601 | fprintf (file, "%s", reg_names[regno]); | |
07045266 RS |
7602 | } |
7603 | break; | |
cee98a59 | 7604 | |
07045266 RS |
7605 | case MEM: |
7606 | if (letter == 'D') | |
7607 | output_address (plus_constant (XEXP (op, 0), 4)); | |
b0907a6c AN |
7608 | else if (letter && letter != 'z') |
7609 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
07045266 RS |
7610 | else |
7611 | output_address (XEXP (op, 0)); | |
7612 | break; | |
cee98a59 | 7613 | |
07045266 RS |
7614 | default: |
7615 | if (letter == 'z' && op == CONST0_RTX (GET_MODE (op))) | |
7616 | fputs (reg_names[GP_REG_FIRST], file); | |
b0907a6c AN |
7617 | else if (letter && letter != 'z') |
7618 | output_operand_lossage ("invalid use of '%%%c'", letter); | |
07045266 RS |
7619 | else if (CONST_GP_P (op)) |
7620 | fputs (reg_names[GLOBAL_POINTER_REGNUM], file); | |
7621 | else | |
7622 | output_addr_const (file, mips_strip_unspec_address (op)); | |
7623 | break; | |
7624 | } | |
b3c90666 | 7625 | } |
108b61d5 | 7626 | } |
07045266 | 7627 | |
6e9e0126 | 7628 | /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ |
cee98a59 | 7629 | |
6e9e0126 | 7630 | static void |
65239d20 | 7631 | mips_print_operand_address (FILE *file, rtx x) |
cafe096b EC |
7632 | { |
7633 | struct mips_address_info addr; | |
cee98a59 | 7634 | |
108b61d5 RS |
7635 | if (mips_classify_address (&addr, x, word_mode, true)) |
7636 | switch (addr.type) | |
7637 | { | |
7638 | case ADDRESS_REG: | |
65239d20 | 7639 | mips_print_operand (file, addr.offset, 0); |
108b61d5 RS |
7640 | fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); |
7641 | return; | |
7642 | ||
7643 | case ADDRESS_LO_SUM: | |
65239d20 RS |
7644 | mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM, |
7645 | mips_lo_relocs); | |
108b61d5 RS |
7646 | fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); |
7647 | return; | |
7648 | ||
7649 | case ADDRESS_CONST_INT: | |
4767c570 | 7650 | output_addr_const (file, x); |
65239d20 | 7651 | fprintf (file, "(%s)", reg_names[GP_REG_FIRST]); |
4767c570 RS |
7652 | return; |
7653 | ||
108b61d5 | 7654 | case ADDRESS_SYMBOLIC: |
c93c5160 | 7655 | output_addr_const (file, mips_strip_unspec_address (x)); |
108b61d5 RS |
7656 | return; |
7657 | } | |
7ad769fe | 7658 | gcc_unreachable (); |
cee98a59 | 7659 | } |
301d03af | 7660 | \f |
65239d20 | 7661 | /* Implement TARGET_ENCODE_SECTION_INFO. */ |
ab77a036 RS |
7662 | |
7663 | static void | |
7664 | mips_encode_section_info (tree decl, rtx rtl, int first) | |
7665 | { | |
7666 | default_encode_section_info (decl, rtl, first); | |
7667 | ||
7668 | if (TREE_CODE (decl) == FUNCTION_DECL) | |
7669 | { | |
7670 | rtx symbol = XEXP (rtl, 0); | |
7671 | tree type = TREE_TYPE (decl); | |
7672 | ||
65239d20 | 7673 | /* Encode whether the symbol is short or long. */ |
ab77a036 RS |
7674 | if ((TARGET_LONG_CALLS && !mips_near_type_p (type)) |
7675 | || mips_far_type_p (type)) | |
7676 | SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL; | |
7677 | } | |
7678 | } | |
7679 | ||
7680 | /* Implement TARGET_SELECT_RTX_SECTION. */ | |
7681 | ||
7682 | static section * | |
7683 | mips_select_rtx_section (enum machine_mode mode, rtx x, | |
7684 | unsigned HOST_WIDE_INT align) | |
7685 | { | |
7686 | /* ??? Consider using mergeable small data sections. */ | |
7687 | if (mips_rtx_constant_in_small_data_p (mode)) | |
7688 | return get_named_section (NULL, ".sdata", 0); | |
7689 | ||
7690 | return default_elf_select_rtx_section (mode, x, align); | |
7691 | } | |
7692 | ||
7693 | /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION. | |
7694 | ||
7695 | The complication here is that, with the combination TARGET_ABICALLS | |
e21d5757 DJ |
7696 | && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use |
7697 | absolute addresses, and should therefore not be included in the | |
7698 | read-only part of a DSO. Handle such cases by selecting a normal | |
7699 | data section instead of a read-only one. The logic apes that in | |
7700 | default_function_rodata_section. */ | |
ab77a036 RS |
7701 | |
7702 | static section * | |
7703 | mips_function_rodata_section (tree decl) | |
7704 | { | |
e21d5757 | 7705 | if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD) |
ab77a036 RS |
7706 | return default_function_rodata_section (decl); |
7707 | ||
7708 | if (decl && DECL_SECTION_NAME (decl)) | |
7709 | { | |
7710 | const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
7711 | if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0) | |
7712 | { | |
7713 | char *rname = ASTRDUP (name); | |
7714 | rname[14] = 'd'; | |
7715 | return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl); | |
7716 | } | |
65239d20 RS |
7717 | else if (flag_function_sections |
7718 | && flag_data_sections | |
ab77a036 RS |
7719 | && strncmp (name, ".text.", 6) == 0) |
7720 | { | |
7721 | char *rname = ASTRDUP (name); | |
7722 | memcpy (rname + 1, "data", 4); | |
7723 | return get_section (rname, SECTION_WRITE, decl); | |
7724 | } | |
7725 | } | |
7726 | return data_section; | |
7727 | } | |
7728 | ||
65239d20 | 7729 | /* Implement TARGET_IN_SMALL_DATA_P. */ |
ab77a036 RS |
7730 | |
7731 | static bool | |
7732 | mips_in_small_data_p (const_tree decl) | |
7733 | { | |
65239d20 | 7734 | unsigned HOST_WIDE_INT size; |
ab77a036 RS |
7735 | |
7736 | if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL) | |
7737 | return false; | |
7738 | ||
65239d20 RS |
7739 | /* We don't yet generate small-data references for -mabicalls |
7740 | or VxWorks RTP code. See the related -G handling in | |
7741 | mips_override_options. */ | |
ab77a036 RS |
7742 | if (TARGET_ABICALLS || TARGET_VXWORKS_RTP) |
7743 | return false; | |
7744 | ||
7745 | if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0) | |
7746 | { | |
7747 | const char *name; | |
7748 | ||
7749 | /* Reject anything that isn't in a known small-data section. */ | |
7750 | name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); | |
7751 | if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0) | |
7752 | return false; | |
7753 | ||
7754 | /* If a symbol is defined externally, the assembler will use the | |
7755 | usual -G rules when deciding how to implement macros. */ | |
7756 | if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl)) | |
7757 | return true; | |
7758 | } | |
7759 | else if (TARGET_EMBEDDED_DATA) | |
7760 | { | |
7761 | /* Don't put constants into the small data section: we want them | |
7762 | to be in ROM rather than RAM. */ | |
7763 | if (TREE_CODE (decl) != VAR_DECL) | |
7764 | return false; | |
7765 | ||
7766 | if (TREE_READONLY (decl) | |
7767 | && !TREE_SIDE_EFFECTS (decl) | |
7768 | && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl)))) | |
7769 | return false; | |
7770 | } | |
7771 | ||
7772 | /* Enforce -mlocal-sdata. */ | |
7773 | if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl)) | |
7774 | return false; | |
7775 | ||
7776 | /* Enforce -mextern-sdata. */ | |
7777 | if (!TARGET_EXTERN_SDATA && DECL_P (decl)) | |
7778 | { | |
7779 | if (DECL_EXTERNAL (decl)) | |
7780 | return false; | |
7781 | if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL) | |
7782 | return false; | |
7783 | } | |
7784 | ||
2a4430a6 RS |
7785 | /* We have traditionally not treated zero-sized objects as small data, |
7786 | so this is now effectively part of the ABI. */ | |
ab77a036 | 7787 | size = int_size_in_bytes (TREE_TYPE (decl)); |
2a4430a6 | 7788 | return size > 0 && size <= mips_small_data_threshold; |
ab77a036 RS |
7789 | } |
7790 | ||
7791 | /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use | |
7792 | anchors for small data: the GP register acts as an anchor in that | |
7793 | case. We also don't want to use them for PC-relative accesses, | |
7794 | where the PC acts as an anchor. */ | |
7795 | ||
7796 | static bool | |
7797 | mips_use_anchors_for_symbol_p (const_rtx symbol) | |
7798 | { | |
7799 | switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM)) | |
7800 | { | |
7801 | case SYMBOL_PC_RELATIVE: | |
7802 | case SYMBOL_GP_RELATIVE: | |
7803 | return false; | |
7804 | ||
7805 | default: | |
7806 | return default_use_anchors_for_symbol_p (symbol); | |
7807 | } | |
7808 | } | |
7809 | \f | |
7810 | /* The MIPS debug format wants all automatic variables and arguments | |
7811 | to be in terms of the virtual frame pointer (stack pointer before | |
7812 | any adjustment in the function), while the MIPS 3.0 linker wants | |
7813 | the frame pointer to be the stack pointer after the initial | |
7814 | adjustment. So, we do the adjustment here. The arg pointer (which | |
7815 | is eliminated) points to the virtual frame pointer, while the frame | |
7816 | pointer (which may be eliminated) points to the stack pointer after | |
7817 | the initial adjustments. */ | |
7818 | ||
7819 | HOST_WIDE_INT | |
7820 | mips_debugger_offset (rtx addr, HOST_WIDE_INT offset) | |
7821 | { | |
7822 | rtx offset2 = const0_rtx; | |
7823 | rtx reg = eliminate_constant_term (addr, &offset2); | |
7824 | ||
7825 | if (offset == 0) | |
7826 | offset = INTVAL (offset2); | |
7827 | ||
65239d20 RS |
7828 | if (reg == stack_pointer_rtx |
7829 | || reg == frame_pointer_rtx | |
ab77a036 RS |
7830 | || reg == hard_frame_pointer_rtx) |
7831 | { | |
f374e413 RS |
7832 | offset -= cfun->machine->frame.total_size; |
7833 | if (reg == hard_frame_pointer_rtx) | |
7834 | offset += cfun->machine->frame.hard_frame_pointer_offset; | |
ab77a036 RS |
7835 | } |
7836 | ||
7837 | /* sdbout_parms does not want this to crash for unrecognized cases. */ | |
7838 | #if 0 | |
7839 | else if (reg != arg_pointer_rtx) | |
7840 | fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer", | |
7841 | addr); | |
7842 | #endif | |
7843 | ||
7844 | return offset; | |
7845 | } | |
7846 | \f | |
65239d20 | 7847 | /* Implement ASM_OUTPUT_EXTERNAL. */ |
cee98a59 | 7848 | |
f8fdb503 L |
7849 | void |
7850 | mips_output_external (FILE *file, tree decl, const char *name) | |
5619cc87 | 7851 | { |
f8fdb503 | 7852 | default_elf_asm_output_external (file, decl, name); |
5619cc87 | 7853 | |
f8fdb503 L |
7854 | /* We output the name if and only if TREE_SYMBOL_REFERENCED is |
7855 | set in order to avoid putting out names that are never really | |
7856 | used. */ | |
7857 | if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))) | |
6773a41c | 7858 | { |
f8fdb503 L |
7859 | if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl)) |
7860 | { | |
65239d20 RS |
7861 | /* When using assembler macros, emit .extern directives for |
7862 | all small-data externs so that the assembler knows how | |
7863 | big they are. | |
7864 | ||
7865 | In most cases it would be safe (though pointless) to emit | |
7866 | .externs for other symbols too. One exception is when an | |
7867 | object is within the -G limit but declared by the user to | |
7868 | be in a section other than .sbss or .sdata. */ | |
f8fdb503 L |
7869 | fputs ("\t.extern\t", file); |
7870 | assemble_name (file, name); | |
7871 | fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n", | |
7872 | int_size_in_bytes (TREE_TYPE (decl))); | |
7873 | } | |
6773a41c | 7874 | } |
cee98a59 | 7875 | } |
65239d20 RS |
7876 | |
7877 | /* Implement ASM_OUTPUT_SOURCE_FILENAME. */ | |
cee98a59 MM |
7878 | |
7879 | void | |
b4966b1b | 7880 | mips_output_filename (FILE *stream, const char *name) |
cee98a59 | 7881 | { |
8b0397a6 DJ |
7882 | /* If we are emitting DWARF-2, let dwarf2out handle the ".file" |
7883 | directives. */ | |
7884 | if (write_symbols == DWARF2_DEBUG) | |
7885 | return; | |
cafe096b | 7886 | else if (mips_output_filename_first_time) |
cee98a59 | 7887 | { |
cafe096b | 7888 | mips_output_filename_first_time = 0; |
82563d35 | 7889 | num_source_filenames += 1; |
cee98a59 | 7890 | current_function_file = name; |
3e487b21 ZW |
7891 | fprintf (stream, "\t.file\t%d ", num_source_filenames); |
7892 | output_quoted_string (stream, name); | |
7893 | putc ('\n', stream); | |
cee98a59 | 7894 | } |
3e487b21 ZW |
7895 | /* If we are emitting stabs, let dbxout.c handle this (except for |
7896 | the mips_output_filename_first_time case). */ | |
2bacb292 | 7897 | else if (write_symbols == DBX_DEBUG) |
3e487b21 | 7898 | return; |
cee98a59 | 7899 | else if (name != current_function_file |
d82783b6 | 7900 | && strcmp (name, current_function_file) != 0) |
cee98a59 | 7901 | { |
82563d35 | 7902 | num_source_filenames += 1; |
d82783b6 | 7903 | current_function_file = name; |
3e487b21 ZW |
7904 | fprintf (stream, "\t.file\t%d ", num_source_filenames); |
7905 | output_quoted_string (stream, name); | |
7906 | putc ('\n', stream); | |
cee98a59 MM |
7907 | } |
7908 | } | |
ab77a036 | 7909 | |
65239d20 | 7910 | /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */ |
ab77a036 | 7911 | |
9a4a025a | 7912 | static void ATTRIBUTE_UNUSED |
ab77a036 RS |
7913 | mips_output_dwarf_dtprel (FILE *file, int size, rtx x) |
7914 | { | |
7915 | switch (size) | |
7916 | { | |
7917 | case 4: | |
7918 | fputs ("\t.dtprelword\t", file); | |
7919 | break; | |
7920 | ||
7921 | case 8: | |
7922 | fputs ("\t.dtpreldword\t", file); | |
7923 | break; | |
7924 | ||
7925 | default: | |
7926 | gcc_unreachable (); | |
7927 | } | |
7928 | output_addr_const (file, x); | |
7929 | fputs ("+0x8000", file); | |
7930 | } | |
7931 | ||
7932 | /* Implement TARGET_DWARF_REGISTER_SPAN. */ | |
7933 | ||
7934 | static rtx | |
7935 | mips_dwarf_register_span (rtx reg) | |
7936 | { | |
7937 | rtx high, low; | |
7938 | enum machine_mode mode; | |
7939 | ||
7940 | /* By default, GCC maps increasing register numbers to increasing | |
7941 | memory locations, but paired FPRs are always little-endian, | |
7942 | regardless of the prevailing endianness. */ | |
7943 | mode = GET_MODE (reg); | |
7944 | if (FP_REG_P (REGNO (reg)) | |
7945 | && TARGET_BIG_ENDIAN | |
7946 | && MAX_FPRS_PER_FMT > 1 | |
7947 | && GET_MODE_SIZE (mode) > UNITS_PER_FPREG) | |
7948 | { | |
7949 | gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE); | |
7950 | high = mips_subword (reg, true); | |
7951 | low = mips_subword (reg, false); | |
7952 | return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low)); | |
7953 | } | |
7954 | ||
7955 | return NULL_RTX; | |
7956 | } | |
65239d20 RS |
7957 | |
7958 | /* Implement ASM_OUTPUT_ASCII. */ | |
b3276c7a | 7959 | |
7dac2f89 | 7960 | void |
65239d20 | 7961 | mips_output_ascii (FILE *stream, const char *string, size_t len) |
b3276c7a GK |
7962 | { |
7963 | size_t i; | |
65239d20 | 7964 | int cur_pos; |
b3276c7a | 7965 | |
65239d20 RS |
7966 | cur_pos = 17; |
7967 | fprintf (stream, "\t.ascii\t\""); | |
7dac2f89 EC |
7968 | for (i = 0; i < len; i++) |
7969 | { | |
65239d20 | 7970 | int c; |
7dac2f89 | 7971 | |
65239d20 | 7972 | c = (unsigned char) string[i]; |
c5ff069d | 7973 | if (ISPRINT (c)) |
7dac2f89 | 7974 | { |
c5ff069d | 7975 | if (c == '\\' || c == '\"') |
7dac2f89 | 7976 | { |
c5ff069d | 7977 | putc ('\\', stream); |
7dac2f89 EC |
7978 | cur_pos++; |
7979 | } | |
c5ff069d ZW |
7980 | putc (c, stream); |
7981 | cur_pos++; | |
7982 | } | |
7983 | else | |
7984 | { | |
7985 | fprintf (stream, "\\%03o", c); | |
7986 | cur_pos += 4; | |
7dac2f89 EC |
7987 | } |
7988 | ||
7989 | if (cur_pos > 72 && i+1 < len) | |
7990 | { | |
7991 | cur_pos = 17; | |
65239d20 | 7992 | fprintf (stream, "\"\n\t.ascii\t\""); |
7dac2f89 EC |
7993 | } |
7994 | } | |
7995 | fprintf (stream, "\"\n"); | |
b3276c7a | 7996 | } |
65239d20 | 7997 | |
ab77a036 | 7998 | /* Emit either a label, .comm, or .lcomm directive. When using assembler |
65239d20 RS |
7999 | macros, mark the symbol as written so that mips_asm_output_external |
8000 | won't emit an .extern for it. STREAM is the output file, NAME is the | |
8001 | name of the symbol, INIT_STRING is the string that should be written | |
8002 | before the symbol and FINAL_STRING is the string that should be | |
8003 | written after it. FINAL_STRING is a printf format that consumes the | |
8004 | remaining arguments. */ | |
35f5add9 RS |
8005 | |
8006 | void | |
ab77a036 RS |
8007 | mips_declare_object (FILE *stream, const char *name, const char *init_string, |
8008 | const char *final_string, ...) | |
35f5add9 | 8009 | { |
ab77a036 | 8010 | va_list ap; |
35f5add9 | 8011 | |
ab77a036 RS |
8012 | fputs (init_string, stream); |
8013 | assemble_name (stream, name); | |
8014 | va_start (ap, final_string); | |
8015 | vfprintf (stream, final_string, ap); | |
8016 | va_end (ap); | |
8017 | ||
8018 | if (!TARGET_EXPLICIT_RELOCS) | |
8019 | { | |
8020 | tree name_tree = get_identifier (name); | |
8021 | TREE_ASM_WRITTEN (name_tree) = 1; | |
35f5add9 | 8022 | } |
48b2e0a7 RS |
8023 | } |
8024 | ||
8025 | /* Declare a common object of SIZE bytes using asm directive INIT_STRING. | |
8026 | NAME is the name of the object and ALIGN is the required alignment | |
8027 | in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third | |
8028 | alignment argument. */ | |
8029 | ||
8030 | void | |
8031 | mips_declare_common_object (FILE *stream, const char *name, | |
8032 | const char *init_string, | |
8033 | unsigned HOST_WIDE_INT size, | |
8034 | unsigned int align, bool takes_alignment_p) | |
8035 | { | |
8036 | if (!takes_alignment_p) | |
35f5add9 | 8037 | { |
35f5add9 RS |
8038 | size += (align / BITS_PER_UNIT) - 1; |
8039 | size -= size % (align / BITS_PER_UNIT); | |
48b2e0a7 | 8040 | mips_declare_object (stream, name, init_string, |
35f5add9 RS |
8041 | "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size); |
8042 | } | |
8043 | else | |
48b2e0a7 | 8044 | mips_declare_object (stream, name, init_string, |
35f5add9 RS |
8045 | "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n", |
8046 | size, align / BITS_PER_UNIT); | |
8047 | } | |
8048 | ||
ab77a036 RS |
8049 | /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the |
8050 | elfos.h version, but we also need to handle -muninit-const-in-rodata. */ | |
9987501f MM |
8051 | |
8052 | void | |
ab77a036 RS |
8053 | mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name, |
8054 | unsigned HOST_WIDE_INT size, | |
8055 | unsigned int align) | |
9987501f | 8056 | { |
ab77a036 RS |
8057 | /* If the target wants uninitialized const declarations in |
8058 | .rdata then don't put them in .comm. */ | |
65239d20 RS |
8059 | if (TARGET_EMBEDDED_DATA |
8060 | && TARGET_UNINIT_CONST_IN_RODATA | |
8061 | && TREE_CODE (decl) == VAR_DECL | |
8062 | && TREE_READONLY (decl) | |
ab77a036 | 8063 | && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node)) |
9987501f | 8064 | { |
ab77a036 RS |
8065 | if (TREE_PUBLIC (decl) && DECL_NAME (decl)) |
8066 | targetm.asm_out.globalize_label (stream, name); | |
8067 | ||
8068 | switch_to_section (readonly_data_section); | |
8069 | ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT)); | |
8070 | mips_declare_object (stream, name, "", | |
8071 | ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", | |
8072 | size); | |
9987501f | 8073 | } |
ab77a036 RS |
8074 | else |
8075 | mips_declare_common_object (stream, name, "\n\t.comm\t", | |
8076 | size, align, true); | |
9987501f | 8077 | } |
c1115ccd RS |
8078 | |
8079 | #ifdef ASM_OUTPUT_SIZE_DIRECTIVE | |
8080 | extern int size_directive_output; | |
8081 | ||
8082 | /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF | |
65239d20 | 8083 | definitions except that it uses mips_declare_object to emit the label. */ |
c1115ccd RS |
8084 | |
8085 | void | |
b4966b1b RS |
8086 | mips_declare_object_name (FILE *stream, const char *name, |
8087 | tree decl ATTRIBUTE_UNUSED) | |
c1115ccd RS |
8088 | { |
8089 | #ifdef ASM_OUTPUT_TYPE_DIRECTIVE | |
82563d35 | 8090 | ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object"); |
c1115ccd RS |
8091 | #endif |
8092 | ||
82563d35 RS |
8093 | size_directive_output = 0; |
8094 | if (!flag_inhibit_size_directive && DECL_SIZE (decl)) | |
8095 | { | |
8096 | HOST_WIDE_INT size; | |
c1115ccd | 8097 | |
82563d35 RS |
8098 | size_directive_output = 1; |
8099 | size = int_size_in_bytes (TREE_TYPE (decl)); | |
8100 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
c1115ccd RS |
8101 | } |
8102 | ||
99a3237a | 8103 | mips_declare_object (stream, name, "", ":\n"); |
c1115ccd RS |
8104 | } |
8105 | ||
8106 | /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */ | |
8107 | ||
8108 | void | |
b4966b1b | 8109 | mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end) |
c1115ccd RS |
8110 | { |
8111 | const char *name; | |
8112 | ||
8113 | name = XSTR (XEXP (DECL_RTL (decl), 0), 0); | |
82563d35 | 8114 | if (!flag_inhibit_size_directive |
c1115ccd | 8115 | && DECL_SIZE (decl) != 0 |
65239d20 RS |
8116 | && !at_end |
8117 | && top_level | |
c1115ccd RS |
8118 | && DECL_INITIAL (decl) == error_mark_node |
8119 | && !size_directive_output) | |
8120 | { | |
8121 | HOST_WIDE_INT size; | |
8122 | ||
8123 | size_directive_output = 1; | |
8124 | size = int_size_in_bytes (TREE_TYPE (decl)); | |
8125 | ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size); | |
8126 | } | |
8127 | } | |
8128 | #endif | |
dbe9742d | 8129 | \f |
5f5fe6d9 RS |
8130 | /* Return the FOO in the name of the ".mdebug.FOO" section associated |
8131 | with the current ABI. */ | |
8132 | ||
8133 | static const char * | |
8134 | mips_mdebug_abi_name (void) | |
8135 | { | |
8136 | switch (mips_abi) | |
8137 | { | |
8138 | case ABI_32: | |
8139 | return "abi32"; | |
8140 | case ABI_O64: | |
8141 | return "abiO64"; | |
8142 | case ABI_N32: | |
8143 | return "abiN32"; | |
8144 | case ABI_64: | |
63553059 | 8145 | return "abi64"; |
5f5fe6d9 RS |
8146 | case ABI_EABI: |
8147 | return TARGET_64BIT ? "eabi64" : "eabi32"; | |
8148 | default: | |
8149 | gcc_unreachable (); | |
8150 | } | |
8151 | } | |
8152 | ||
ab77a036 | 8153 | /* Implement TARGET_ASM_FILE_START. */ |
108b61d5 | 8154 | |
ab77a036 RS |
8155 | static void |
8156 | mips_file_start (void) | |
108b61d5 | 8157 | { |
ab77a036 | 8158 | default_file_start (); |
108b61d5 | 8159 | |
65239d20 RS |
8160 | /* Generate a special section to describe the ABI switches used to |
8161 | produce the resultant binary. This is unnecessary on IRIX and | |
8162 | causes unwanted warnings from the native linker. */ | |
9aaa1ee8 | 8163 | if (!TARGET_IRIX6) |
ab77a036 | 8164 | { |
65239d20 RS |
8165 | /* Record the ABI itself. Modern versions of binutils encode |
8166 | this information in the ELF header flags, but GDB needs the | |
8167 | information in order to correctly debug binaries produced by | |
8168 | older binutils. See the function mips_gdbarch_init in | |
8169 | gdb/mips-tdep.c. */ | |
ab77a036 | 8170 | fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n", |
5f5fe6d9 | 8171 | mips_mdebug_abi_name ()); |
280fcbfa | 8172 | |
ab77a036 RS |
8173 | /* There is no ELF header flag to distinguish long32 forms of the |
8174 | EABI from long64 forms. Emit a special section to help tools | |
8175 | such as GDB. Do the same for o64, which is sometimes used with | |
8176 | -mlong64. */ | |
8177 | if (mips_abi == ABI_EABI || mips_abi == ABI_O64) | |
8178 | fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n" | |
8179 | "\t.previous\n", TARGET_LONG64 ? 64 : 32); | |
108b61d5 | 8180 | |
ab77a036 | 8181 | #ifdef HAVE_AS_GNU_ATTRIBUTE |
9f946bc1 RS |
8182 | { |
8183 | int attr; | |
8184 | ||
8185 | /* No floating-point operations, -mno-float. */ | |
8186 | if (TARGET_NO_FLOAT) | |
8187 | attr = 0; | |
8188 | /* Soft-float code, -msoft-float. */ | |
8189 | else if (!TARGET_HARD_FLOAT_ABI) | |
8190 | attr = 3; | |
8191 | /* Single-float code, -msingle-float. */ | |
8192 | else if (!TARGET_DOUBLE_FLOAT) | |
8193 | attr = 2; | |
8194 | /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */ | |
8195 | else if (!TARGET_64BIT && TARGET_FLOAT64) | |
8196 | attr = 4; | |
8197 | /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */ | |
8198 | else | |
8199 | attr = 1; | |
8200 | ||
8201 | fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr); | |
8202 | } | |
ab77a036 | 8203 | #endif |
280fcbfa RS |
8204 | } |
8205 | ||
65239d20 | 8206 | /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */ |
ab77a036 | 8207 | if (TARGET_ABICALLS) |
e21d5757 DJ |
8208 | { |
8209 | fprintf (asm_out_file, "\t.abicalls\n"); | |
8210 | if (TARGET_ABICALLS_PIC0) | |
8211 | fprintf (asm_out_file, "\t.option\tpic0\n"); | |
8212 | } | |
108b61d5 | 8213 | |
ab77a036 RS |
8214 | if (flag_verbose_asm) |
8215 | fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n", | |
8216 | ASM_COMMENT_START, | |
65239d20 | 8217 | mips_small_data_threshold, mips_arch_info->name, mips_isa); |
108b61d5 RS |
8218 | } |
8219 | \f | |
65239d20 | 8220 | /* Make the last instruction frame-related and note that it performs |
ab77a036 | 8221 | the operation described by FRAME_PATTERN. */ |
108b61d5 | 8222 | |
ab77a036 RS |
8223 | static void |
8224 | mips_set_frame_expr (rtx frame_pattern) | |
108b61d5 | 8225 | { |
ab77a036 | 8226 | rtx insn; |
280fcbfa | 8227 | |
ab77a036 RS |
8228 | insn = get_last_insn (); |
8229 | RTX_FRAME_RELATED_P (insn) = 1; | |
8230 | REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, | |
8231 | frame_pattern, | |
8232 | REG_NOTES (insn)); | |
8233 | } | |
280fcbfa | 8234 | |
ab77a036 RS |
8235 | /* Return a frame-related rtx that stores REG at MEM. |
8236 | REG must be a single register. */ | |
108b61d5 | 8237 | |
ab77a036 RS |
8238 | static rtx |
8239 | mips_frame_set (rtx mem, rtx reg) | |
8240 | { | |
8241 | rtx set; | |
108b61d5 | 8242 | |
65239d20 | 8243 | /* If we're saving the return address register and the DWARF return |
ab77a036 RS |
8244 | address column differs from the hard register number, adjust the |
8245 | note reg to refer to the former. */ | |
293593b1 RS |
8246 | if (REGNO (reg) == RETURN_ADDR_REGNUM |
8247 | && DWARF_FRAME_RETURN_COLUMN != RETURN_ADDR_REGNUM) | |
ab77a036 | 8248 | reg = gen_rtx_REG (GET_MODE (reg), DWARF_FRAME_RETURN_COLUMN); |
a38e0142 | 8249 | |
ab77a036 RS |
8250 | set = gen_rtx_SET (VOIDmode, mem, reg); |
8251 | RTX_FRAME_RELATED_P (set) = 1; | |
a38e0142 | 8252 | |
ab77a036 | 8253 | return set; |
a38e0142 | 8254 | } |
ab77a036 RS |
8255 | \f |
8256 | /* If a MIPS16e SAVE or RESTORE instruction saves or restores register | |
8257 | mips16e_s2_s8_regs[X], it must also save the registers in indexes | |
8258 | X + 1 onwards. Likewise mips16e_a0_a3_regs. */ | |
8259 | static const unsigned char mips16e_s2_s8_regs[] = { | |
8260 | 30, 23, 22, 21, 20, 19, 18 | |
8261 | }; | |
8262 | static const unsigned char mips16e_a0_a3_regs[] = { | |
8263 | 4, 5, 6, 7 | |
8264 | }; | |
a38e0142 | 8265 | |
ab77a036 RS |
8266 | /* A list of the registers that can be saved by the MIPS16e SAVE instruction, |
8267 | ordered from the uppermost in memory to the lowest in memory. */ | |
8268 | static const unsigned char mips16e_save_restore_regs[] = { | |
8269 | 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4 | |
8270 | }; | |
f833ffd4 | 8271 | |
e1260576 RS |
8272 | /* Return the index of the lowest X in the range [0, SIZE) for which |
8273 | bit REGS[X] is set in MASK. Return SIZE if there is no such X. */ | |
8274 | ||
8275 | static unsigned int | |
8276 | mips16e_find_first_register (unsigned int mask, const unsigned char *regs, | |
8277 | unsigned int size) | |
8278 | { | |
8279 | unsigned int i; | |
8280 | ||
8281 | for (i = 0; i < size; i++) | |
8282 | if (BITSET_P (mask, regs[i])) | |
8283 | break; | |
8284 | ||
8285 | return i; | |
8286 | } | |
8287 | ||
37017f4d RS |
8288 | /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR |
8289 | is the number of set bits. If *MASK_PTR contains REGS[X] for some X | |
8290 | in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same | |
8291 | is true for all indexes (X, SIZE). */ | |
e1260576 RS |
8292 | |
8293 | static void | |
8294 | mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs, | |
37017f4d | 8295 | unsigned int size, unsigned int *num_regs_ptr) |
e1260576 RS |
8296 | { |
8297 | unsigned int i; | |
8298 | ||
8299 | i = mips16e_find_first_register (*mask_ptr, regs, size); | |
8300 | for (i++; i < size; i++) | |
8301 | if (!BITSET_P (*mask_ptr, regs[i])) | |
8302 | { | |
37017f4d | 8303 | *num_regs_ptr += 1; |
e1260576 RS |
8304 | *mask_ptr |= 1 << regs[i]; |
8305 | } | |
8306 | } | |
f833ffd4 | 8307 | |
ab77a036 RS |
8308 | /* Return a simplified form of X using the register values in REG_VALUES. |
8309 | REG_VALUES[R] is the last value assigned to hard register R, or null | |
8310 | if R has not been modified. | |
cee98a59 | 8311 | |
ab77a036 | 8312 | This function is rather limited, but is good enough for our purposes. */ |
cee98a59 | 8313 | |
ab77a036 RS |
8314 | static rtx |
8315 | mips16e_collect_propagate_value (rtx x, rtx *reg_values) | |
cee98a59 | 8316 | { |
ab77a036 | 8317 | x = avoid_constant_pool_reference (x); |
cee98a59 | 8318 | |
ab77a036 | 8319 | if (UNARY_P (x)) |
9e800206 | 8320 | { |
65239d20 | 8321 | rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values); |
ab77a036 RS |
8322 | return simplify_gen_unary (GET_CODE (x), GET_MODE (x), |
8323 | x0, GET_MODE (XEXP (x, 0))); | |
9e800206 RH |
8324 | } |
8325 | ||
ab77a036 | 8326 | if (ARITHMETIC_P (x)) |
e1260576 | 8327 | { |
65239d20 RS |
8328 | rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values); |
8329 | rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values); | |
ab77a036 | 8330 | return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1); |
e1260576 RS |
8331 | } |
8332 | ||
ab77a036 RS |
8333 | if (REG_P (x) |
8334 | && reg_values[REGNO (x)] | |
8335 | && !rtx_unstable_p (reg_values[REGNO (x)])) | |
8336 | return reg_values[REGNO (x)]; | |
cee98a59 | 8337 | |
ab77a036 RS |
8338 | return x; |
8339 | } | |
33563487 | 8340 | |
ab77a036 RS |
8341 | /* Return true if (set DEST SRC) stores an argument register into its |
8342 | caller-allocated save slot, storing the number of that argument | |
8343 | register in *REGNO_PTR if so. REG_VALUES is as for | |
8344 | mips16e_collect_propagate_value. */ | |
cee98a59 | 8345 | |
ab77a036 RS |
8346 | static bool |
8347 | mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values, | |
8348 | unsigned int *regno_ptr) | |
8349 | { | |
8350 | unsigned int argno, regno; | |
8351 | HOST_WIDE_INT offset, required_offset; | |
8352 | rtx addr, base; | |
2bcb2ab3 | 8353 | |
ab77a036 RS |
8354 | /* Check that this is a word-mode store. */ |
8355 | if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode) | |
8356 | return false; | |
258d81a8 | 8357 | |
ab77a036 RS |
8358 | /* Check that the register being saved is an unmodified argument |
8359 | register. */ | |
8360 | regno = REGNO (src); | |
65239d20 | 8361 | if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno]) |
ab77a036 RS |
8362 | return false; |
8363 | argno = regno - GP_ARG_FIRST; | |
e88fb323 | 8364 | |
65239d20 RS |
8365 | /* Check whether the address is an appropriate stack-pointer or |
8366 | frame-pointer access. */ | |
ab77a036 RS |
8367 | addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values); |
8368 | mips_split_plus (addr, &base, &offset); | |
8369 | required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD; | |
8370 | if (base == hard_frame_pointer_rtx) | |
f374e413 | 8371 | required_offset -= cfun->machine->frame.hard_frame_pointer_offset; |
ab77a036 RS |
8372 | else if (base != stack_pointer_rtx) |
8373 | return false; | |
8374 | if (offset != required_offset) | |
8375 | return false; | |
cee98a59 | 8376 | |
ab77a036 RS |
8377 | *regno_ptr = regno; |
8378 | return true; | |
cee98a59 | 8379 | } |
b2471838 | 8380 | |
ab77a036 RS |
8381 | /* A subroutine of mips_expand_prologue, called only when generating |
8382 | MIPS16e SAVE instructions. Search the start of the function for any | |
8383 | instructions that save argument registers into their caller-allocated | |
8384 | save slots. Delete such instructions and return a value N such that | |
8385 | saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted | |
8386 | instructions redundant. */ | |
b2471838 | 8387 | |
ab77a036 RS |
8388 | static unsigned int |
8389 | mips16e_collect_argument_saves (void) | |
8390 | { | |
8391 | rtx reg_values[FIRST_PSEUDO_REGISTER]; | |
8392 | rtx insn, next, set, dest, src; | |
8393 | unsigned int nargs, regno; | |
84879759 | 8394 | |
ab77a036 RS |
8395 | push_topmost_sequence (); |
8396 | nargs = 0; | |
8397 | memset (reg_values, 0, sizeof (reg_values)); | |
8398 | for (insn = get_insns (); insn; insn = next) | |
b2471838 | 8399 | { |
ab77a036 | 8400 | next = NEXT_INSN (insn); |
006b29ab | 8401 | if (NOTE_P (insn) || DEBUG_INSN_P (insn)) |
ab77a036 | 8402 | continue; |
b2471838 | 8403 | |
ab77a036 RS |
8404 | if (!INSN_P (insn)) |
8405 | break; | |
b2471838 | 8406 | |
ab77a036 RS |
8407 | set = PATTERN (insn); |
8408 | if (GET_CODE (set) != SET) | |
8409 | break; | |
8410 | ||
8411 | dest = SET_DEST (set); | |
8412 | src = SET_SRC (set); | |
8413 | if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no)) | |
8414 | { | |
8415 | if (!BITSET_P (cfun->machine->frame.mask, regno)) | |
8416 | { | |
8417 | delete_insn (insn); | |
8418 | nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1); | |
8419 | } | |
8420 | } | |
8421 | else if (REG_P (dest) && GET_MODE (dest) == word_mode) | |
8422 | reg_values[REGNO (dest)] | |
8423 | = mips16e_collect_propagate_value (src, reg_values); | |
8424 | else | |
8425 | break; | |
b2471838 | 8426 | } |
ab77a036 | 8427 | pop_topmost_sequence (); |
b2471838 | 8428 | |
ab77a036 RS |
8429 | return nargs; |
8430 | } | |
b2471838 | 8431 | |
ab77a036 RS |
8432 | /* Return a move between register REGNO and memory location SP + OFFSET. |
8433 | Make the move a load if RESTORE_P, otherwise make it a frame-related | |
8434 | store. */ | |
67070ffe | 8435 | |
ab77a036 RS |
8436 | static rtx |
8437 | mips16e_save_restore_reg (bool restore_p, HOST_WIDE_INT offset, | |
8438 | unsigned int regno) | |
67070ffe | 8439 | { |
ab77a036 | 8440 | rtx reg, mem; |
1cbfdb1f | 8441 | |
ab77a036 RS |
8442 | mem = gen_frame_mem (SImode, plus_constant (stack_pointer_rtx, offset)); |
8443 | reg = gen_rtx_REG (SImode, regno); | |
8444 | return (restore_p | |
8445 | ? gen_rtx_SET (VOIDmode, reg, mem) | |
8446 | : mips_frame_set (mem, reg)); | |
1cbfdb1f RS |
8447 | } |
8448 | ||
ab77a036 RS |
8449 | /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which. |
8450 | The instruction must: | |
1cbfdb1f | 8451 | |
ab77a036 RS |
8452 | - Allocate or deallocate SIZE bytes in total; SIZE is known |
8453 | to be nonzero. | |
cee98a59 | 8454 | |
ab77a036 RS |
8455 | - Save or restore as many registers in *MASK_PTR as possible. |
8456 | The instruction saves the first registers at the top of the | |
8457 | allocated area, with the other registers below it. | |
cee98a59 | 8458 | |
ab77a036 | 8459 | - Save NARGS argument registers above the allocated area. |
b85aed9e | 8460 | |
ab77a036 | 8461 | (NARGS is always zero if RESTORE_P.) |
b85aed9e | 8462 | |
ab77a036 RS |
8463 | The SAVE and RESTORE instructions cannot save and restore all general |
8464 | registers, so there may be some registers left over for the caller to | |
8465 | handle. Destructively modify *MASK_PTR so that it contains the registers | |
8466 | that still need to be saved or restored. The caller can save these | |
8467 | registers in the memory immediately below *OFFSET_PTR, which is a | |
8468 | byte offset from the bottom of the allocated stack area. */ | |
d9870b7e | 8469 | |
ab77a036 RS |
8470 | static rtx |
8471 | mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr, | |
8472 | HOST_WIDE_INT *offset_ptr, unsigned int nargs, | |
8473 | HOST_WIDE_INT size) | |
d9870b7e | 8474 | { |
ab77a036 RS |
8475 | rtx pattern, set; |
8476 | HOST_WIDE_INT offset, top_offset; | |
8477 | unsigned int i, regno; | |
8478 | int n; | |
8cb6400c | 8479 | |
ddc4af9c | 8480 | gcc_assert (cfun->machine->frame.num_fp == 0); |
d9870b7e | 8481 | |
ab77a036 RS |
8482 | /* Calculate the number of elements in the PARALLEL. We need one element |
8483 | for the stack adjustment, one for each argument register save, and one | |
8484 | for each additional register move. */ | |
8485 | n = 1 + nargs; | |
8486 | for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++) | |
8487 | if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i])) | |
8488 | n++; | |
d9870b7e | 8489 | |
ab77a036 RS |
8490 | /* Create the final PARALLEL. */ |
8491 | pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n)); | |
8492 | n = 0; | |
d9870b7e | 8493 | |
ab77a036 RS |
8494 | /* Add the stack pointer adjustment. */ |
8495 | set = gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
8496 | plus_constant (stack_pointer_rtx, | |
8497 | restore_p ? size : -size)); | |
8498 | RTX_FRAME_RELATED_P (set) = 1; | |
8499 | XVECEXP (pattern, 0, n++) = set; | |
d9870b7e | 8500 | |
ab77a036 RS |
8501 | /* Stack offsets in the PARALLEL are relative to the old stack pointer. */ |
8502 | top_offset = restore_p ? size : 0; | |
b85aed9e | 8503 | |
ab77a036 RS |
8504 | /* Save the arguments. */ |
8505 | for (i = 0; i < nargs; i++) | |
8506 | { | |
6e75e6e3 | 8507 | offset = top_offset + i * UNITS_PER_WORD; |
ab77a036 RS |
8508 | set = mips16e_save_restore_reg (restore_p, offset, GP_ARG_FIRST + i); |
8509 | XVECEXP (pattern, 0, n++) = set; | |
8510 | } | |
d9870b7e | 8511 | |
ab77a036 RS |
8512 | /* Then fill in the other register moves. */ |
8513 | offset = top_offset; | |
8514 | for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++) | |
b85aed9e | 8515 | { |
ab77a036 RS |
8516 | regno = mips16e_save_restore_regs[i]; |
8517 | if (BITSET_P (*mask_ptr, regno)) | |
d9870b7e | 8518 | { |
ab77a036 RS |
8519 | offset -= UNITS_PER_WORD; |
8520 | set = mips16e_save_restore_reg (restore_p, offset, regno); | |
8521 | XVECEXP (pattern, 0, n++) = set; | |
8522 | *mask_ptr &= ~(1 << regno); | |
d9870b7e | 8523 | } |
ab77a036 | 8524 | } |
b85aed9e | 8525 | |
ab77a036 | 8526 | /* Tell the caller what offset it should use for the remaining registers. */ |
b87bc4e8 | 8527 | *offset_ptr = size + (offset - top_offset); |
d9870b7e | 8528 | |
ab77a036 | 8529 | gcc_assert (n == XVECLEN (pattern, 0)); |
8cb6400c | 8530 | |
ab77a036 | 8531 | return pattern; |
b85aed9e RS |
8532 | } |
8533 | ||
ab77a036 RS |
8534 | /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack |
8535 | pointer. Return true if PATTERN matches the kind of instruction | |
8536 | generated by mips16e_build_save_restore. If INFO is nonnull, | |
8537 | initialize it when returning true. */ | |
cee98a59 | 8538 | |
ab77a036 RS |
8539 | bool |
8540 | mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust, | |
8541 | struct mips16e_save_restore_info *info) | |
cee98a59 | 8542 | { |
37017f4d RS |
8543 | unsigned int i, nargs, mask, extra; |
8544 | HOST_WIDE_INT top_offset, save_offset, offset; | |
ab77a036 RS |
8545 | rtx set, reg, mem, base; |
8546 | int n; | |
cee98a59 | 8547 | |
ab77a036 RS |
8548 | if (!GENERATE_MIPS16E_SAVE_RESTORE) |
8549 | return false; | |
2bcb2ab3 | 8550 | |
ab77a036 RS |
8551 | /* Stack offsets in the PARALLEL are relative to the old stack pointer. */ |
8552 | top_offset = adjust > 0 ? adjust : 0; | |
f9e4a411 | 8553 | |
ab77a036 | 8554 | /* Interpret all other members of the PARALLEL. */ |
6e75e6e3 | 8555 | save_offset = top_offset - UNITS_PER_WORD; |
ab77a036 RS |
8556 | mask = 0; |
8557 | nargs = 0; | |
8558 | i = 0; | |
8559 | for (n = 1; n < XVECLEN (pattern, 0); n++) | |
e9a25f70 | 8560 | { |
ab77a036 RS |
8561 | /* Check that we have a SET. */ |
8562 | set = XVECEXP (pattern, 0, n); | |
8563 | if (GET_CODE (set) != SET) | |
8564 | return false; | |
3c7404d3 | 8565 | |
ab77a036 RS |
8566 | /* Check that the SET is a load (if restoring) or a store |
8567 | (if saving). */ | |
8568 | mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set); | |
8569 | if (!MEM_P (mem)) | |
8570 | return false; | |
3c7404d3 | 8571 | |
ab77a036 RS |
8572 | /* Check that the address is the sum of the stack pointer and a |
8573 | possibly-zero constant offset. */ | |
8574 | mips_split_plus (XEXP (mem, 0), &base, &offset); | |
8575 | if (base != stack_pointer_rtx) | |
8576 | return false; | |
82563d35 | 8577 | |
ab77a036 RS |
8578 | /* Check that SET's other operand is a register. */ |
8579 | reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set); | |
8580 | if (!REG_P (reg)) | |
8581 | return false; | |
e9a25f70 | 8582 | |
ab77a036 | 8583 | /* Check for argument saves. */ |
6e75e6e3 | 8584 | if (offset == top_offset + nargs * UNITS_PER_WORD |
ab77a036 RS |
8585 | && REGNO (reg) == GP_ARG_FIRST + nargs) |
8586 | nargs++; | |
8587 | else if (offset == save_offset) | |
8588 | { | |
8589 | while (mips16e_save_restore_regs[i++] != REGNO (reg)) | |
8590 | if (i == ARRAY_SIZE (mips16e_save_restore_regs)) | |
8591 | return false; | |
a50f2a09 | 8592 | |
ab77a036 | 8593 | mask |= 1 << REGNO (reg); |
6e75e6e3 | 8594 | save_offset -= UNITS_PER_WORD; |
ab77a036 RS |
8595 | } |
8596 | else | |
8597 | return false; | |
e9a25f70 | 8598 | } |
ffa9d0b1 | 8599 | |
ab77a036 RS |
8600 | /* Check that the restrictions on register ranges are met. */ |
8601 | extra = 0; | |
8602 | mips16e_mask_registers (&mask, mips16e_s2_s8_regs, | |
8603 | ARRAY_SIZE (mips16e_s2_s8_regs), &extra); | |
8604 | mips16e_mask_registers (&mask, mips16e_a0_a3_regs, | |
8605 | ARRAY_SIZE (mips16e_a0_a3_regs), &extra); | |
8606 | if (extra != 0) | |
8607 | return false; | |
8608 | ||
8609 | /* Make sure that the topmost argument register is not saved twice. | |
8610 | The checks above ensure that the same is then true for the other | |
8611 | argument registers. */ | |
8612 | if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1)) | |
8613 | return false; | |
8614 | ||
8615 | /* Pass back information, if requested. */ | |
8616 | if (info) | |
6f2993e5 | 8617 | { |
ab77a036 RS |
8618 | info->nargs = nargs; |
8619 | info->mask = mask; | |
8620 | info->size = (adjust > 0 ? adjust : -adjust); | |
6f2993e5 | 8621 | } |
b85aed9e | 8622 | |
ab77a036 | 8623 | return true; |
f833ffd4 | 8624 | } |
be763023 | 8625 | |
ab77a036 RS |
8626 | /* Add a MIPS16e SAVE or RESTORE register-range argument to string S |
8627 | for the register range [MIN_REG, MAX_REG]. Return a pointer to | |
8628 | the null terminator. */ | |
be763023 | 8629 | |
ab77a036 RS |
8630 | static char * |
8631 | mips16e_add_register_range (char *s, unsigned int min_reg, | |
8632 | unsigned int max_reg) | |
8633 | { | |
8634 | if (min_reg != max_reg) | |
8635 | s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]); | |
8636 | else | |
8637 | s += sprintf (s, ",%s", reg_names[min_reg]); | |
8638 | return s; | |
be763023 RS |
8639 | } |
8640 | ||
ab77a036 RS |
8641 | /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction. |
8642 | PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */ | |
be763023 | 8643 | |
ab77a036 RS |
8644 | const char * |
8645 | mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust) | |
be763023 | 8646 | { |
ab77a036 | 8647 | static char buffer[300]; |
1de2bc2a | 8648 | |
ab77a036 RS |
8649 | struct mips16e_save_restore_info info; |
8650 | unsigned int i, end; | |
8651 | char *s; | |
1de2bc2a | 8652 | |
ab77a036 RS |
8653 | /* Parse the pattern. */ |
8654 | if (!mips16e_save_restore_pattern_p (pattern, adjust, &info)) | |
8655 | gcc_unreachable (); | |
be763023 | 8656 | |
ab77a036 RS |
8657 | /* Add the mnemonic. */ |
8658 | s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t"); | |
8659 | s += strlen (s); | |
be763023 | 8660 | |
ab77a036 RS |
8661 | /* Save the arguments. */ |
8662 | if (info.nargs > 1) | |
8663 | s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST], | |
8664 | reg_names[GP_ARG_FIRST + info.nargs - 1]); | |
8665 | else if (info.nargs == 1) | |
8666 | s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]); | |
be763023 | 8667 | |
ab77a036 RS |
8668 | /* Emit the amount of stack space to allocate or deallocate. */ |
8669 | s += sprintf (s, "%d", (int) info.size); | |
be763023 | 8670 | |
ab77a036 RS |
8671 | /* Save or restore $16. */ |
8672 | if (BITSET_P (info.mask, 16)) | |
8673 | s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]); | |
936b1317 | 8674 | |
ab77a036 RS |
8675 | /* Save or restore $17. */ |
8676 | if (BITSET_P (info.mask, 17)) | |
8677 | s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]); | |
be763023 | 8678 | |
ab77a036 RS |
8679 | /* Save or restore registers in the range $s2...$s8, which |
8680 | mips16e_s2_s8_regs lists in decreasing order. Note that this | |
8681 | is a software register range; the hardware registers are not | |
8682 | numbered consecutively. */ | |
8683 | end = ARRAY_SIZE (mips16e_s2_s8_regs); | |
8684 | i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end); | |
8685 | if (i < end) | |
8686 | s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1], | |
8687 | mips16e_s2_s8_regs[i]); | |
be763023 | 8688 | |
ab77a036 RS |
8689 | /* Save or restore registers in the range $a0...$a3. */ |
8690 | end = ARRAY_SIZE (mips16e_a0_a3_regs); | |
8691 | i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end); | |
8692 | if (i < end) | |
8693 | s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i], | |
8694 | mips16e_a0_a3_regs[end - 1]); | |
e1260576 | 8695 | |
ab77a036 | 8696 | /* Save or restore $31. */ |
293593b1 RS |
8697 | if (BITSET_P (info.mask, RETURN_ADDR_REGNUM)) |
8698 | s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]); | |
e1260576 | 8699 | |
ab77a036 | 8700 | return buffer; |
e1260576 | 8701 | } |
ab77a036 | 8702 | \f |
0c433c31 RS |
8703 | /* Return true if the current function returns its value in a floating-point |
8704 | register in MIPS16 mode. */ | |
e1260576 | 8705 | |
ab77a036 | 8706 | static bool |
0c433c31 | 8707 | mips16_cfun_returns_in_fpr_p (void) |
ab77a036 | 8708 | { |
0c433c31 RS |
8709 | tree return_type = DECL_RESULT (current_function_decl); |
8710 | return (TARGET_MIPS16 | |
8711 | && TARGET_HARD_FLOAT_ABI | |
8712 | && !aggregate_value_p (return_type, current_function_decl) | |
8713 | && mips_return_mode_in_fpr_p (DECL_MODE (return_type))); | |
8714 | } | |
e1260576 | 8715 | |
0c433c31 RS |
8716 | /* Return true if predicate PRED is true for at least one instruction. |
8717 | Cache the result in *CACHE, and assume that the result is true | |
8718 | if *CACHE is already true. */ | |
8719 | ||
8720 | static bool | |
8721 | mips_find_gp_ref (bool *cache, bool (*pred) (rtx)) | |
8722 | { | |
8723 | rtx insn; | |
8724 | ||
8725 | if (!*cache) | |
8726 | { | |
ab77a036 RS |
8727 | push_topmost_sequence (); |
8728 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
0c433c31 | 8729 | if (USEFUL_INSN_P (insn) && pred (insn)) |
65239d20 | 8730 | { |
0c433c31 | 8731 | *cache = true; |
65239d20 RS |
8732 | break; |
8733 | } | |
ab77a036 | 8734 | pop_topmost_sequence (); |
ab77a036 | 8735 | } |
0c433c31 | 8736 | return *cache; |
ab77a036 | 8737 | } |
e1260576 | 8738 | |
0c433c31 RS |
8739 | /* Return true if INSN refers to the global pointer in an "inflexible" way. |
8740 | See mips_cfun_has_inflexible_gp_ref_p for details. */ | |
7462a715 RS |
8741 | |
8742 | static bool | |
0c433c31 | 8743 | mips_insn_has_inflexible_gp_ref_p (rtx insn) |
7462a715 | 8744 | { |
0c433c31 RS |
8745 | /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE |
8746 | indicate that the target could be a traditional MIPS | |
8747 | lazily-binding stub. */ | |
8748 | return find_reg_fusage (insn, USE, pic_offset_table_rtx); | |
8749 | } | |
8750 | ||
8751 | /* Return true if the current function refers to the global pointer | |
8752 | in a way that forces $28 to be valid. This means that we can't | |
8753 | change the choice of global pointer, even for NewABI code. | |
8754 | ||
8755 | One example of this (and one which needs several checks) is that | |
8756 | $28 must be valid when calling traditional MIPS lazy-binding stubs. | |
8757 | (This restriction does not apply to PLTs.) */ | |
8758 | ||
8759 | static bool | |
8760 | mips_cfun_has_inflexible_gp_ref_p (void) | |
8761 | { | |
8762 | /* If the function has a nonlocal goto, $28 must hold the correct | |
8763 | global pointer for the target function. That is, the target | |
8764 | of the goto implicitly uses $28. */ | |
8765 | if (crtl->has_nonlocal_goto) | |
8766 | return true; | |
8767 | ||
8768 | if (TARGET_ABICALLS_PIC2) | |
8769 | { | |
8770 | /* Symbolic accesses implicitly use the global pointer unless | |
8771 | -mexplicit-relocs is in effect. JAL macros to symbolic addresses | |
8772 | might go to traditional MIPS lazy-binding stubs. */ | |
8773 | if (!TARGET_EXPLICIT_RELOCS) | |
8774 | return true; | |
8775 | ||
8776 | /* FUNCTION_PROFILER includes a JAL to _mcount, which again | |
8777 | can be lazily-bound. */ | |
8778 | if (crtl->profile) | |
8779 | return true; | |
8780 | ||
8781 | /* MIPS16 functions that return in FPRs need to call an | |
8782 | external libgcc routine. This call is only made explict | |
8783 | during mips_expand_epilogue, and it too might be lazily bound. */ | |
8784 | if (mips16_cfun_returns_in_fpr_p ()) | |
8785 | return true; | |
8786 | } | |
8787 | ||
8788 | return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p, | |
8789 | mips_insn_has_inflexible_gp_ref_p); | |
8790 | } | |
8791 | ||
8792 | /* Return true if INSN refers to the global pointer in a "flexible" way. | |
8793 | See mips_cfun_has_flexible_gp_ref_p for details. */ | |
8794 | ||
8795 | static bool | |
8796 | mips_insn_has_flexible_gp_ref_p (rtx insn) | |
8797 | { | |
8798 | return (get_attr_got (insn) != GOT_UNSET | |
8799 | || mips_small_data_pattern_p (PATTERN (insn)) | |
8800 | || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn))); | |
8801 | } | |
8802 | ||
8803 | /* Return true if the current function references the global pointer, | |
8804 | but if those references do not inherently require the global pointer | |
8805 | to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */ | |
8806 | ||
8807 | static bool | |
8808 | mips_cfun_has_flexible_gp_ref_p (void) | |
8809 | { | |
8810 | /* Reload can sometimes introduce constant pool references | |
8811 | into a function that otherwise didn't need them. For example, | |
8812 | suppose we have an instruction like: | |
8813 | ||
8814 | (set (reg:DF R1) (float:DF (reg:SI R2))) | |
8815 | ||
8816 | If R2 turns out to be a constant such as 1, the instruction may | |
8817 | have a REG_EQUAL note saying that R1 == 1.0. Reload then has | |
8818 | the option of using this constant if R2 doesn't get allocated | |
8819 | to a register. | |
8820 | ||
8821 | In cases like these, reload will have added the constant to the | |
8822 | pool but no instruction will yet refer to it. */ | |
8823 | if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool) | |
8824 | return true; | |
8825 | ||
8826 | return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p, | |
8827 | mips_insn_has_flexible_gp_ref_p); | |
7462a715 RS |
8828 | } |
8829 | ||
ab77a036 | 8830 | /* Return the register that should be used as the global pointer |
8d9d9172 RS |
8831 | within this function. Return INVALID_REGNUM if the function |
8832 | doesn't need a global pointer. */ | |
e1260576 | 8833 | |
ab77a036 RS |
8834 | static unsigned int |
8835 | mips_global_pointer (void) | |
e1260576 | 8836 | { |
ab77a036 | 8837 | unsigned int regno; |
e1260576 | 8838 | |
ab77a036 RS |
8839 | /* $gp is always available unless we're using a GOT. */ |
8840 | if (!TARGET_USE_GOT) | |
8841 | return GLOBAL_POINTER_REGNUM; | |
e1260576 | 8842 | |
0c433c31 RS |
8843 | /* If there are inflexible references to $gp, we must use the |
8844 | standard register. */ | |
8845 | if (mips_cfun_has_inflexible_gp_ref_p ()) | |
ab77a036 | 8846 | return GLOBAL_POINTER_REGNUM; |
e1260576 | 8847 | |
0c433c31 RS |
8848 | /* If there are no current references to $gp, then the only uses |
8849 | we can introduce later are those involved in long branches. */ | |
8850 | if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ()) | |
8851 | return INVALID_REGNUM; | |
e21d5757 | 8852 | |
0c433c31 RS |
8853 | /* If the global pointer is call-saved, try to use a call-clobbered |
8854 | alternative. */ | |
ab77a036 RS |
8855 | if (TARGET_CALL_SAVED_GP && current_function_is_leaf) |
8856 | for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) | |
8857 | if (!df_regs_ever_live_p (regno) | |
8858 | && call_really_used_regs[regno] | |
8859 | && !fixed_regs[regno] | |
8860 | && regno != PIC_FUNCTION_ADDR_REGNUM) | |
8861 | return regno; | |
e1260576 | 8862 | |
ab77a036 | 8863 | return GLOBAL_POINTER_REGNUM; |
e1260576 RS |
8864 | } |
8865 | ||
293593b1 | 8866 | /* Return true if the current function's prologue must load the global |
0c433c31 RS |
8867 | pointer value into pic_offset_table_rtx and store the same value in |
8868 | the function's cprestore slot (if any). | |
8869 | ||
8870 | One problem we have to deal with is that, when emitting GOT-based | |
8871 | position independent code, long-branch sequences will need to load | |
8872 | the address of the branch target from the GOT. We don't know until | |
8873 | the very end of compilation whether (and where) the function needs | |
8874 | long branches, so we must ensure that _any_ branch can access the | |
8875 | global pointer in some form. However, we do not want to pessimize | |
8876 | the usual case in which all branches are short. | |
8877 | ||
8878 | We handle this as follows: | |
8879 | ||
8880 | (1) During reload, we set cfun->machine->global_pointer to | |
8881 | INVALID_REGNUM if we _know_ that the current function | |
8882 | doesn't need a global pointer. This is only valid if | |
8883 | long branches don't need the GOT. | |
8884 | ||
8885 | Otherwise, we assume that we might need a global pointer | |
8886 | and pick an appropriate register. | |
8887 | ||
8888 | (2) If cfun->machine->global_pointer != INVALID_REGNUM, | |
8889 | we ensure that the global pointer is available at every | |
8890 | block boundary bar entry and exit. We do this in one of two ways: | |
8891 | ||
8892 | - If the function has a cprestore slot, we ensure that this | |
8893 | slot is valid at every branch. However, as explained in | |
8894 | point (6) below, there is no guarantee that pic_offset_table_rtx | |
8895 | itself is valid if new uses of the global pointer are introduced | |
8896 | after the first post-epilogue split. | |
8897 | ||
8898 | We guarantee that the cprestore slot is valid by loading it | |
8899 | into a fake register, CPRESTORE_SLOT_REGNUM. We then make | |
8900 | this register live at every block boundary bar function entry | |
8901 | and exit. It is then invalid to move the load (and thus the | |
8902 | preceding store) across a block boundary. | |
8903 | ||
8904 | - If the function has no cprestore slot, we guarantee that | |
8905 | pic_offset_table_rtx itself is valid at every branch. | |
8906 | ||
8907 | See mips_eh_uses for the handling of the register liveness. | |
8908 | ||
8909 | (3) During prologue and epilogue generation, we emit "ghost" | |
8910 | placeholder instructions to manipulate the global pointer. | |
8911 | ||
8912 | (4) During prologue generation, we set cfun->machine->must_initialize_gp_p | |
8913 | and cfun->machine->must_restore_gp_when_clobbered_p if we already know | |
8914 | that the function needs a global pointer. (There is no need to set | |
8915 | them earlier than this, and doing it as late as possible leads to | |
8916 | fewer false positives.) | |
8917 | ||
8918 | (5) If cfun->machine->must_initialize_gp_p is true during a | |
8919 | split_insns pass, we split the ghost instructions into real | |
8920 | instructions. These split instructions can then be optimized in | |
8921 | the usual way. Otherwise, we keep the ghost instructions intact, | |
8922 | and optimize for the case where they aren't needed. We still | |
8923 | have the option of splitting them later, if we need to introduce | |
8924 | new uses of the global pointer. | |
8925 | ||
8926 | For example, the scheduler ignores a ghost instruction that | |
8927 | stores $28 to the stack, but it handles the split form of | |
8928 | the ghost instruction as an ordinary store. | |
8929 | ||
8930 | (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p | |
8931 | is true during the first post-epilogue split_insns pass, we split | |
8932 | calls and restore_gp patterns into instructions that explicitly | |
8933 | load pic_offset_table_rtx from the cprestore slot. Otherwise, | |
8934 | we split these patterns into instructions that _don't_ load from | |
8935 | the cprestore slot. | |
8936 | ||
8937 | If cfun->machine->must_restore_gp_when_clobbered_p is true at the | |
8938 | time of the split, then any instructions that exist at that time | |
8939 | can make free use of pic_offset_table_rtx. However, if we want | |
8940 | to introduce new uses of the global pointer after the split, | |
8941 | we must explicitly load the value from the cprestore slot, since | |
8942 | pic_offset_table_rtx itself might not be valid at a given point | |
8943 | in the function. | |
8944 | ||
8945 | The idea is that we want to be able to delete redundant | |
8946 | loads from the cprestore slot in the usual case where no | |
8947 | long branches are needed. | |
8948 | ||
8949 | (7) If cfun->machine->must_initialize_gp_p is still false at the end | |
8950 | of md_reorg, we decide whether the global pointer is needed for | |
8951 | long branches. If so, we set cfun->machine->must_initialize_gp_p | |
8952 | to true and split the ghost instructions into real instructions | |
8953 | at that stage. | |
8954 | ||
8955 | Note that the ghost instructions must have a zero length for three reasons: | |
8956 | ||
8957 | - Giving the length of the underlying $gp sequence might cause | |
8958 | us to use long branches in cases where they aren't really needed. | |
8959 | ||
8960 | - They would perturb things like alignment calculations. | |
8961 | ||
8962 | - More importantly, the hazard detection in md_reorg relies on | |
8963 | empty instructions having a zero length. | |
8964 | ||
8965 | If we find a long branch and split the ghost instructions at the | |
8966 | end of md_reorg, the split could introduce more long branches. | |
8967 | That isn't a problem though, because we still do the split before | |
8968 | the final shorten_branches pass. | |
8969 | ||
8970 | This is extremely ugly, but it seems like the best compromise between | |
8971 | correctness and efficiency. */ | |
8972 | ||
8973 | bool | |
8974 | mips_must_initialize_gp_p (void) | |
8975 | { | |
8976 | return cfun->machine->must_initialize_gp_p; | |
8977 | } | |
8978 | ||
e19da24c CF |
8979 | /* Return true if REGNO is a register that is ordinarily call-clobbered |
8980 | but must nevertheless be preserved by an interrupt handler. */ | |
8981 | ||
8982 | static bool | |
8983 | mips_interrupt_extra_call_saved_reg_p (unsigned int regno) | |
8984 | { | |
8985 | if (MD_REG_P (regno)) | |
8986 | return true; | |
8987 | ||
8988 | if (TARGET_DSP && DSP_ACC_REG_P (regno)) | |
8989 | return true; | |
8990 | ||
8991 | if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p) | |
8992 | { | |
8993 | /* $0 is hard-wired. */ | |
8994 | if (regno == GP_REG_FIRST) | |
8995 | return false; | |
8996 | ||
8997 | /* The interrupt handler can treat kernel registers as | |
8998 | scratch registers. */ | |
8999 | if (KERNEL_REG_P (regno)) | |
9000 | return false; | |
9001 | ||
9002 | /* The function will return the stack pointer to its original value | |
9003 | anyway. */ | |
9004 | if (regno == STACK_POINTER_REGNUM) | |
9005 | return false; | |
9006 | ||
9007 | /* Otherwise, return true for registers that aren't ordinarily | |
9008 | call-clobbered. */ | |
9009 | return call_really_used_regs[regno]; | |
9010 | } | |
9011 | ||
9012 | return false; | |
9013 | } | |
9014 | ||
7cc003b5 RS |
9015 | /* Return true if the current function should treat register REGNO |
9016 | as call-saved. */ | |
e1260576 | 9017 | |
ab77a036 | 9018 | static bool |
7cc003b5 RS |
9019 | mips_cfun_call_saved_reg_p (unsigned int regno) |
9020 | { | |
e19da24c CF |
9021 | /* Interrupt handlers need to save extra registers. */ |
9022 | if (cfun->machine->interrupt_handler_p | |
9023 | && mips_interrupt_extra_call_saved_reg_p (regno)) | |
9024 | return true; | |
9025 | ||
7cc003b5 RS |
9026 | /* call_insns preserve $28 unless they explicitly say otherwise, |
9027 | so call_really_used_regs[] treats $28 as call-saved. However, | |
9028 | we want the ABI property rather than the default call_insn | |
9029 | property here. */ | |
9030 | return (regno == GLOBAL_POINTER_REGNUM | |
9031 | ? TARGET_CALL_SAVED_GP | |
9032 | : !call_really_used_regs[regno]); | |
9033 | } | |
9034 | ||
9035 | /* Return true if the function body might clobber register REGNO. | |
9036 | We know that REGNO is call-saved. */ | |
9037 | ||
9038 | static bool | |
9039 | mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno) | |
ab77a036 | 9040 | { |
7cc003b5 RS |
9041 | /* Some functions should be treated as clobbering all call-saved |
9042 | registers. */ | |
9043 | if (crtl->saves_all_registers) | |
4817c43b | 9044 | return true; |
e1260576 | 9045 | |
7cc003b5 RS |
9046 | /* DF handles cases where a register is explicitly referenced in |
9047 | the rtl. Incoming values are passed in call-clobbered registers, | |
9048 | so we can assume that any live call-saved register is set within | |
9049 | the function. */ | |
9050 | if (df_regs_ever_live_p (regno)) | |
ab77a036 | 9051 | return true; |
e1260576 | 9052 | |
7cc003b5 RS |
9053 | /* Check for registers that are clobbered by FUNCTION_PROFILER. |
9054 | These clobbers are not explicit in the rtl. */ | |
9055 | if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno)) | |
9056 | return true; | |
9057 | ||
9058 | /* If we're using a call-saved global pointer, the function's | |
9059 | prologue will need to set it up. */ | |
9060 | if (cfun->machine->global_pointer == regno) | |
ab77a036 | 9061 | return true; |
106b3d40 | 9062 | |
7cc003b5 RS |
9063 | /* The function's prologue will need to set the frame pointer if |
9064 | frame_pointer_needed. */ | |
ab77a036 RS |
9065 | if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) |
9066 | return true; | |
e1260576 | 9067 | |
7cc003b5 RS |
9068 | /* If a MIPS16 function returns a value in FPRs, its epilogue |
9069 | will need to call an external libgcc routine. This yet-to-be | |
9070 | generated call_insn will clobber $31. */ | |
293593b1 | 9071 | if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ()) |
ab77a036 | 9072 | return true; |
e1260576 | 9073 | |
e19da24c CF |
9074 | /* If REGNO is ordinarily call-clobbered, we must assume that any |
9075 | called function could modify it. */ | |
9076 | if (cfun->machine->interrupt_handler_p | |
9077 | && !current_function_is_leaf | |
9078 | && mips_interrupt_extra_call_saved_reg_p (regno)) | |
9079 | return true; | |
9080 | ||
7cc003b5 RS |
9081 | return false; |
9082 | } | |
9083 | ||
9084 | /* Return true if the current function must save register REGNO. */ | |
9085 | ||
9086 | static bool | |
9087 | mips_save_reg_p (unsigned int regno) | |
9088 | { | |
9089 | if (mips_cfun_call_saved_reg_p (regno)) | |
9090 | { | |
9091 | if (mips_cfun_might_clobber_call_saved_reg_p (regno)) | |
9092 | return true; | |
9093 | ||
9094 | /* Save both registers in an FPR pair if either one is used. This is | |
9095 | needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd | |
9096 | register to be used without the even register. */ | |
9097 | if (FP_REG_P (regno) | |
9098 | && MAX_FPRS_PER_FMT == 2 | |
9099 | && mips_cfun_might_clobber_call_saved_reg_p (regno + 1)) | |
9100 | return true; | |
9101 | } | |
9102 | ||
9103 | /* We need to save the incoming return address if __builtin_eh_return | |
9104 | is being used to set a different return address. */ | |
293593b1 | 9105 | if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return) |
ab77a036 | 9106 | return true; |
e1260576 | 9107 | |
ab77a036 | 9108 | return false; |
e1260576 RS |
9109 | } |
9110 | ||
16dc5c28 | 9111 | /* Populate the current function's mips_frame_info structure. |
e1260576 | 9112 | |
ab77a036 | 9113 | MIPS stack frames look like: |
e1260576 | 9114 | |
37017f4d RS |
9115 | +-------------------------------+ |
9116 | | | | |
9117 | | incoming stack arguments | | |
9118 | | | | |
9119 | +-------------------------------+ | |
9120 | | | | |
9121 | | caller-allocated save area | | |
9122 | A | for register arguments | | |
9123 | | | | |
9124 | +-------------------------------+ <-- incoming stack pointer | |
9125 | | | | |
9126 | | callee-allocated save area | | |
9127 | B | for arguments that are | | |
9128 | | split between registers and | | |
9129 | | the stack | | |
9130 | | | | |
9131 | +-------------------------------+ <-- arg_pointer_rtx | |
9132 | | | | |
9133 | C | callee-allocated save area | | |
9134 | | for register varargs | | |
9135 | | | | |
e19da24c CF |
9136 | +-------------------------------+ <-- frame_pointer_rtx |
9137 | | | + cop0_sp_offset | |
9138 | | COP0 reg save area | + UNITS_PER_WORD | |
9139 | | | | |
9140 | +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset | |
9141 | | | + UNITS_PER_WORD | |
9142 | | accumulator save area | | |
9143 | | | | |
ba6adec4 | 9144 | +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset |
37017f4d RS |
9145 | | | + UNITS_PER_HWFPVALUE |
9146 | | FPR save area | | |
9147 | | | | |
ba6adec4 | 9148 | +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset |
37017f4d RS |
9149 | | | + UNITS_PER_WORD |
9150 | | GPR save area | | |
9151 | | | | |
ba6adec4 AN |
9152 | +-------------------------------+ <-- frame_pointer_rtx with |
9153 | | | \ -fstack-protector | |
37017f4d RS |
9154 | | local variables | | var_size |
9155 | | | / | |
9156 | +-------------------------------+ | |
9157 | | | \ | |
9158 | | $gp save area | | cprestore_size | |
9159 | | | / | |
9160 | P +-------------------------------+ <-- hard_frame_pointer_rtx for | |
ba6adec4 AN |
9161 | | | \ MIPS16 code |
9162 | | outgoing stack arguments | | | |
9163 | | | | | |
9164 | +-------------------------------+ | args_size | |
9165 | | | | | |
9166 | | caller-allocated save area | | | |
9167 | | for register arguments | | | |
9168 | | | / | |
37017f4d | 9169 | +-------------------------------+ <-- stack_pointer_rtx |
ba6adec4 AN |
9170 | frame_pointer_rtx without |
9171 | -fstack-protector | |
37017f4d RS |
9172 | hard_frame_pointer_rtx for |
9173 | non-MIPS16 code. | |
9174 | ||
9175 | At least two of A, B and C will be empty. | |
9176 | ||
9177 | Dynamic stack allocations such as alloca insert data at point P. | |
9178 | They decrease stack_pointer_rtx but leave frame_pointer_rtx and | |
9179 | hard_frame_pointer_rtx unchanged. */ | |
e1260576 | 9180 | |
16dc5c28 RS |
9181 | static void |
9182 | mips_compute_frame_info (void) | |
ab77a036 | 9183 | { |
37017f4d | 9184 | struct mips_frame_info *frame; |
16dc5c28 | 9185 | HOST_WIDE_INT offset, size; |
37017f4d | 9186 | unsigned int regno, i; |
e1260576 | 9187 | |
e19da24c CF |
9188 | /* Set this function's interrupt properties. */ |
9189 | if (mips_interrupt_type_p (TREE_TYPE (current_function_decl))) | |
9190 | { | |
9191 | if (!ISA_MIPS32R2) | |
9192 | error ("the %<interrupt%> attribute requires a MIPS32r2 processor"); | |
9193 | else if (TARGET_HARD_FLOAT) | |
9194 | error ("the %<interrupt%> attribute requires %<-msoft-float%>"); | |
9195 | else if (TARGET_MIPS16) | |
9196 | error ("interrupt handlers cannot be MIPS16 functions"); | |
9197 | else | |
9198 | { | |
9199 | cfun->machine->interrupt_handler_p = true; | |
9200 | cfun->machine->use_shadow_register_set_p = | |
9201 | mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl)); | |
9202 | cfun->machine->keep_interrupts_masked_p = | |
9203 | mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl)); | |
9204 | cfun->machine->use_debug_exception_return_p = | |
9205 | mips_use_debug_exception_return_p (TREE_TYPE | |
9206 | (current_function_decl)); | |
9207 | } | |
9208 | } | |
9209 | ||
37017f4d RS |
9210 | frame = &cfun->machine->frame; |
9211 | memset (frame, 0, sizeof (*frame)); | |
16dc5c28 | 9212 | size = get_frame_size (); |
e1260576 | 9213 | |
37017f4d | 9214 | cfun->machine->global_pointer = mips_global_pointer (); |
e1260576 | 9215 | |
ba6adec4 AN |
9216 | /* The first two blocks contain the outgoing argument area and the $gp save |
9217 | slot. This area isn't needed in leaf functions, but if the | |
9218 | target-independent frame size is nonzero, we have already committed to | |
9219 | allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */ | |
9220 | if ((size == 0 || FRAME_GROWS_DOWNWARD) && current_function_is_leaf) | |
37017f4d RS |
9221 | { |
9222 | /* The MIPS 3.0 linker does not like functions that dynamically | |
9223 | allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it | |
9224 | looks like we are trying to create a second frame pointer to the | |
9225 | function, so allocate some stack space to make it happy. */ | |
e3b5732b | 9226 | if (cfun->calls_alloca) |
37017f4d RS |
9227 | frame->args_size = REG_PARM_STACK_SPACE (cfun->decl); |
9228 | else | |
9229 | frame->args_size = 0; | |
9230 | frame->cprestore_size = 0; | |
9231 | } | |
9232 | else | |
9233 | { | |
38173d38 | 9234 | frame->args_size = crtl->outgoing_args_size; |
ba6adec4 | 9235 | frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE; |
37017f4d RS |
9236 | } |
9237 | offset = frame->args_size + frame->cprestore_size; | |
e1260576 | 9238 | |
37017f4d RS |
9239 | /* Move above the local variables. */ |
9240 | frame->var_size = MIPS_STACK_ALIGN (size); | |
9241 | offset += frame->var_size; | |
e1260576 | 9242 | |
37017f4d | 9243 | /* Find out which GPRs we need to save. */ |
ab77a036 RS |
9244 | for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) |
9245 | if (mips_save_reg_p (regno)) | |
9246 | { | |
37017f4d RS |
9247 | frame->num_gp++; |
9248 | frame->mask |= 1 << (regno - GP_REG_FIRST); | |
ab77a036 | 9249 | } |
e1260576 | 9250 | |
37017f4d RS |
9251 | /* If this function calls eh_return, we must also save and restore the |
9252 | EH data registers. */ | |
e3b5732b | 9253 | if (crtl->calls_eh_return) |
37017f4d RS |
9254 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++) |
9255 | { | |
9256 | frame->num_gp++; | |
9257 | frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST); | |
9258 | } | |
e1260576 | 9259 | |
ab77a036 RS |
9260 | /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers: |
9261 | $a3-$a0 and $s2-$s8. If we save one register in the range, we must | |
9262 | save all later registers too. */ | |
9263 | if (GENERATE_MIPS16E_SAVE_RESTORE) | |
9264 | { | |
37017f4d RS |
9265 | mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs, |
9266 | ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp); | |
9267 | mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs, | |
9268 | ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp); | |
9269 | } | |
9270 | ||
9271 | /* Move above the GPR save area. */ | |
9272 | if (frame->num_gp > 0) | |
9273 | { | |
ddc4af9c | 9274 | offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD); |
37017f4d | 9275 | frame->gp_sp_offset = offset - UNITS_PER_WORD; |
ab77a036 | 9276 | } |
e1260576 | 9277 | |
37017f4d | 9278 | /* Find out which FPRs we need to save. This loop must iterate over |
e19da24c | 9279 | the same space as its companion in mips_for_each_saved_gpr_and_fpr. */ |
ab77a036 | 9280 | if (TARGET_HARD_FLOAT) |
37017f4d | 9281 | for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT) |
ab77a036 RS |
9282 | if (mips_save_reg_p (regno)) |
9283 | { | |
37017f4d RS |
9284 | frame->num_fp += MAX_FPRS_PER_FMT; |
9285 | frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST); | |
ab77a036 | 9286 | } |
e1260576 | 9287 | |
37017f4d RS |
9288 | /* Move above the FPR save area. */ |
9289 | if (frame->num_fp > 0) | |
e1260576 | 9290 | { |
ddc4af9c | 9291 | offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG); |
37017f4d | 9292 | frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE; |
e1260576 RS |
9293 | } |
9294 | ||
e19da24c CF |
9295 | /* Add in space for the interrupt context information. */ |
9296 | if (cfun->machine->interrupt_handler_p) | |
9297 | { | |
9298 | /* Check HI/LO. */ | |
9299 | if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM)) | |
9300 | { | |
9301 | frame->num_acc++; | |
9302 | frame->acc_mask |= (1 << 0); | |
9303 | } | |
9304 | ||
9305 | /* Check accumulators 1, 2, 3. */ | |
9306 | for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2) | |
9307 | if (mips_save_reg_p (i) || mips_save_reg_p (i + 1)) | |
9308 | { | |
9309 | frame->num_acc++; | |
9310 | frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1); | |
9311 | } | |
9312 | ||
9313 | /* All interrupt context functions need space to preserve STATUS. */ | |
9314 | frame->num_cop0_regs++; | |
9315 | ||
9316 | /* If we don't keep interrupts masked, we need to save EPC. */ | |
9317 | if (!cfun->machine->keep_interrupts_masked_p) | |
9318 | frame->num_cop0_regs++; | |
9319 | } | |
9320 | ||
9321 | /* Move above the accumulator save area. */ | |
9322 | if (frame->num_acc > 0) | |
9323 | { | |
9324 | /* Each accumulator needs 2 words. */ | |
9325 | offset += frame->num_acc * 2 * UNITS_PER_WORD; | |
9326 | frame->acc_sp_offset = offset - UNITS_PER_WORD; | |
9327 | } | |
9328 | ||
9329 | /* Move above the COP0 register save area. */ | |
9330 | if (frame->num_cop0_regs > 0) | |
9331 | { | |
9332 | offset += frame->num_cop0_regs * UNITS_PER_WORD; | |
9333 | frame->cop0_sp_offset = offset - UNITS_PER_WORD; | |
9334 | } | |
9335 | ||
37017f4d RS |
9336 | /* Move above the callee-allocated varargs save area. */ |
9337 | offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size); | |
f374e413 | 9338 | frame->arg_pointer_offset = offset; |
e1260576 | 9339 | |
37017f4d | 9340 | /* Move above the callee-allocated area for pretend stack arguments. */ |
38173d38 | 9341 | offset += crtl->args.pretend_args_size; |
37017f4d RS |
9342 | frame->total_size = offset; |
9343 | ||
9344 | /* Work out the offsets of the save areas from the top of the frame. */ | |
9345 | if (frame->gp_sp_offset > 0) | |
9346 | frame->gp_save_offset = frame->gp_sp_offset - offset; | |
9347 | if (frame->fp_sp_offset > 0) | |
9348 | frame->fp_save_offset = frame->fp_sp_offset - offset; | |
e19da24c CF |
9349 | if (frame->acc_sp_offset > 0) |
9350 | frame->acc_save_offset = frame->acc_sp_offset - offset; | |
9351 | if (frame->num_cop0_regs > 0) | |
9352 | frame->cop0_save_offset = frame->cop0_sp_offset - offset; | |
ab77a036 | 9353 | |
f374e413 RS |
9354 | /* MIPS16 code offsets the frame pointer by the size of the outgoing |
9355 | arguments. This tends to increase the chances of using unextended | |
9356 | instructions for local variables and incoming arguments. */ | |
9357 | if (TARGET_MIPS16) | |
9358 | frame->hard_frame_pointer_offset = frame->args_size; | |
e1260576 RS |
9359 | } |
9360 | ||
ab77a036 RS |
9361 | /* Return the style of GP load sequence that is being used for the |
9362 | current function. */ | |
e1260576 | 9363 | |
ab77a036 RS |
9364 | enum mips_loadgp_style |
9365 | mips_current_loadgp_style (void) | |
e1260576 | 9366 | { |
8d9d9172 | 9367 | if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM) |
ab77a036 | 9368 | return LOADGP_NONE; |
e1260576 | 9369 | |
ab77a036 RS |
9370 | if (TARGET_RTP_PIC) |
9371 | return LOADGP_RTP; | |
e1260576 | 9372 | |
ab77a036 RS |
9373 | if (TARGET_ABSOLUTE_ABICALLS) |
9374 | return LOADGP_ABSOLUTE; | |
e1260576 | 9375 | |
ab77a036 RS |
9376 | return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI; |
9377 | } | |
65239d20 | 9378 | |
b52b1749 | 9379 | /* Implement TARGET_FRAME_POINTER_REQUIRED. */ |
29c4d304 | 9380 | |
b52b1749 | 9381 | static bool |
29c4d304 RS |
9382 | mips_frame_pointer_required (void) |
9383 | { | |
9384 | /* If the function contains dynamic stack allocations, we need to | |
9385 | use the frame pointer to access the static parts of the frame. */ | |
e3b5732b | 9386 | if (cfun->calls_alloca) |
29c4d304 RS |
9387 | return true; |
9388 | ||
9389 | /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise, | |
9390 | reload may be unable to compute the address of a local variable, | |
9391 | since there is no way to add a large constant to the stack pointer | |
9392 | without using a second temporary register. */ | |
9393 | if (TARGET_MIPS16) | |
9394 | { | |
16dc5c28 | 9395 | mips_compute_frame_info (); |
29c4d304 RS |
9396 | if (!SMALL_OPERAND (cfun->machine->frame.total_size)) |
9397 | return true; | |
9398 | } | |
9399 | ||
9400 | return false; | |
9401 | } | |
9402 | ||
7b5cbb57 AS |
9403 | /* Make sure that we're not trying to eliminate to the wrong hard frame |
9404 | pointer. */ | |
9405 | ||
9406 | static bool | |
9407 | mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) | |
9408 | { | |
9409 | return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); | |
9410 | } | |
9411 | ||
65239d20 RS |
9412 | /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer |
9413 | or argument pointer. TO is either the stack pointer or hard frame | |
9414 | pointer. */ | |
e1260576 | 9415 | |
ab77a036 RS |
9416 | HOST_WIDE_INT |
9417 | mips_initial_elimination_offset (int from, int to) | |
9418 | { | |
9419 | HOST_WIDE_INT offset; | |
9420 | ||
16dc5c28 | 9421 | mips_compute_frame_info (); |
ab77a036 | 9422 | |
ba6adec4 | 9423 | /* Set OFFSET to the offset from the end-of-prologue stack pointer. */ |
ab77a036 RS |
9424 | switch (from) |
9425 | { | |
9426 | case FRAME_POINTER_REGNUM: | |
ba6adec4 AN |
9427 | if (FRAME_GROWS_DOWNWARD) |
9428 | offset = (cfun->machine->frame.args_size | |
9429 | + cfun->machine->frame.cprestore_size | |
9430 | + cfun->machine->frame.var_size); | |
9431 | else | |
9432 | offset = 0; | |
ab77a036 RS |
9433 | break; |
9434 | ||
9435 | case ARG_POINTER_REGNUM: | |
f374e413 | 9436 | offset = cfun->machine->frame.arg_pointer_offset; |
ab77a036 RS |
9437 | break; |
9438 | ||
9439 | default: | |
9440 | gcc_unreachable (); | |
9441 | } | |
9442 | ||
f374e413 RS |
9443 | if (to == HARD_FRAME_POINTER_REGNUM) |
9444 | offset -= cfun->machine->frame.hard_frame_pointer_offset; | |
ab77a036 RS |
9445 | |
9446 | return offset; | |
e1260576 | 9447 | } |
ab77a036 | 9448 | \f |
dbc90b65 | 9449 | /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */ |
e1260576 | 9450 | |
ab77a036 RS |
9451 | static void |
9452 | mips_extra_live_on_entry (bitmap regs) | |
9453 | { | |
dbc90b65 RS |
9454 | if (TARGET_USE_GOT) |
9455 | { | |
9456 | /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up | |
9457 | the global pointer. */ | |
9458 | if (!TARGET_ABSOLUTE_ABICALLS) | |
9459 | bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM); | |
9460 | ||
08d0963a RS |
9461 | /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of |
9462 | the global pointer. */ | |
9463 | if (TARGET_MIPS16) | |
9464 | bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM); | |
9465 | ||
dbc90b65 RS |
9466 | /* See the comment above load_call<mode> for details. */ |
9467 | bitmap_set_bit (regs, GOT_VERSION_REGNUM); | |
9468 | } | |
ab77a036 | 9469 | } |
e1260576 | 9470 | |
65239d20 RS |
9471 | /* Implement RETURN_ADDR_RTX. We do not support moving back to a |
9472 | previous frame. */ | |
ab77a036 RS |
9473 | |
9474 | rtx | |
9475 | mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) | |
e1260576 | 9476 | { |
ab77a036 RS |
9477 | if (count != 0) |
9478 | return const0_rtx; | |
e1260576 | 9479 | |
293593b1 | 9480 | return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); |
ab77a036 | 9481 | } |
e1260576 | 9482 | |
ab77a036 RS |
9483 | /* Emit code to change the current function's return address to |
9484 | ADDRESS. SCRATCH is available as a scratch register, if needed. | |
9485 | ADDRESS and SCRATCH are both word-mode GPRs. */ | |
e1260576 | 9486 | |
ab77a036 RS |
9487 | void |
9488 | mips_set_return_address (rtx address, rtx scratch) | |
9489 | { | |
9490 | rtx slot_address; | |
e1260576 | 9491 | |
293593b1 | 9492 | gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM)); |
ab77a036 RS |
9493 | slot_address = mips_add_offset (scratch, stack_pointer_rtx, |
9494 | cfun->machine->frame.gp_sp_offset); | |
8d0e1e43 | 9495 | mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address); |
e1260576 | 9496 | } |
be763023 | 9497 | |
0c433c31 | 9498 | /* Return true if the current function has a cprestore slot. */ |
0fb5ac6f | 9499 | |
0c433c31 RS |
9500 | bool |
9501 | mips_cfun_has_cprestore_slot_p (void) | |
9502 | { | |
9503 | return (cfun->machine->global_pointer != INVALID_REGNUM | |
9504 | && cfun->machine->frame.cprestore_size > 0); | |
9505 | } | |
9506 | ||
9507 | /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the | |
9508 | cprestore slot. LOAD_P is true if the caller wants to load from | |
9509 | the cprestore slot; it is false if the caller wants to store to | |
9510 | the slot. */ | |
9511 | ||
9512 | static void | |
9513 | mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset, | |
9514 | bool load_p) | |
0fb5ac6f | 9515 | { |
08d0963a | 9516 | const struct mips_frame_info *frame; |
0fb5ac6f | 9517 | |
08d0963a | 9518 | frame = &cfun->machine->frame; |
0c433c31 RS |
9519 | /* .cprestore always uses the stack pointer instead of the frame pointer. |
9520 | We have a free choice for direct stores for non-MIPS16 functions, | |
9521 | and for MIPS16 functions whose cprestore slot is in range of the | |
9522 | stack pointer. Using the stack pointer would sometimes give more | |
9523 | (early) scheduling freedom, but using the frame pointer would | |
9524 | sometimes give more (late) scheduling freedom. It's hard to | |
9525 | predict which applies to a given function, so let's keep things | |
9526 | simple. | |
9527 | ||
9528 | Loads must always use the frame pointer in functions that call | |
9529 | alloca, and there's little benefit to using the stack pointer | |
9530 | otherwise. */ | |
9531 | if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p)) | |
9532 | { | |
9533 | *base = hard_frame_pointer_rtx; | |
9534 | *offset = frame->args_size - frame->hard_frame_pointer_offset; | |
08d0963a RS |
9535 | } |
9536 | else | |
9537 | { | |
0c433c31 RS |
9538 | *base = stack_pointer_rtx; |
9539 | *offset = frame->args_size; | |
08d0963a | 9540 | } |
0c433c31 RS |
9541 | } |
9542 | ||
9543 | /* Return true if X is the load or store address of the cprestore slot; | |
9544 | LOAD_P says which. */ | |
9545 | ||
9546 | bool | |
9547 | mips_cprestore_address_p (rtx x, bool load_p) | |
9548 | { | |
9549 | rtx given_base, required_base; | |
9550 | HOST_WIDE_INT given_offset, required_offset; | |
9551 | ||
9552 | mips_split_plus (x, &given_base, &given_offset); | |
9553 | mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p); | |
9554 | return given_base == required_base && given_offset == required_offset; | |
9555 | } | |
9556 | ||
9557 | /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are | |
9558 | going to load from it, false if we are going to store to it. | |
9559 | Use TEMP as a temporary register if need be. */ | |
9560 | ||
9561 | static rtx | |
9562 | mips_cprestore_slot (rtx temp, bool load_p) | |
9563 | { | |
9564 | rtx base; | |
9565 | HOST_WIDE_INT offset; | |
9566 | ||
9567 | mips_get_cprestore_base_and_offset (&base, &offset, load_p); | |
08d0963a RS |
9568 | return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset)); |
9569 | } | |
9570 | ||
0c433c31 RS |
9571 | /* Emit instructions to save global pointer value GP into cprestore |
9572 | slot MEM. OFFSET is the offset that MEM applies to the base register. | |
9573 | ||
9574 | MEM may not be a legitimate address. If it isn't, TEMP is a | |
9575 | temporary register that can be used, otherwise it is a SCRATCH. */ | |
9576 | ||
9577 | void | |
9578 | mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp) | |
9579 | { | |
9580 | if (TARGET_CPRESTORE_DIRECTIVE) | |
9581 | { | |
9582 | gcc_assert (gp == pic_offset_table_rtx); | |
9583 | emit_insn (gen_cprestore (mem, offset)); | |
9584 | } | |
9585 | else | |
9586 | mips_emit_move (mips_cprestore_slot (temp, false), gp); | |
9587 | } | |
9588 | ||
08d0963a | 9589 | /* Restore $gp from its save slot, using TEMP as a temporary base register |
0c433c31 RS |
9590 | if need be. This function is for o32 and o64 abicalls only. |
9591 | ||
9592 | See mips_must_initialize_gp_p for details about how we manage the | |
9593 | global pointer. */ | |
08d0963a RS |
9594 | |
9595 | void | |
0c433c31 | 9596 | mips_restore_gp_from_cprestore_slot (rtx temp) |
08d0963a | 9597 | { |
0c433c31 | 9598 | gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed); |
f833ffd4 | 9599 | |
0c433c31 | 9600 | if (!cfun->machine->must_restore_gp_when_clobbered_p) |
c870c233 RS |
9601 | { |
9602 | emit_note (NOTE_INSN_DELETED); | |
9603 | return; | |
9604 | } | |
e21d5757 | 9605 | |
08d0963a RS |
9606 | if (TARGET_MIPS16) |
9607 | { | |
0c433c31 | 9608 | mips_emit_move (temp, mips_cprestore_slot (temp, true)); |
08d0963a RS |
9609 | mips_emit_move (pic_offset_table_rtx, temp); |
9610 | } | |
9611 | else | |
0c433c31 | 9612 | mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true)); |
ab77a036 RS |
9613 | if (!TARGET_EXPLICIT_RELOCS) |
9614 | emit_insn (gen_blockage ()); | |
9615 | } | |
9616 | \f | |
9617 | /* A function to save or store a register. The first argument is the | |
9618 | register and the second is the stack slot. */ | |
9619 | typedef void (*mips_save_restore_fn) (rtx, rtx); | |
cee98a59 | 9620 | |
ab77a036 RS |
9621 | /* Use FN to save or restore register REGNO. MODE is the register's |
9622 | mode and OFFSET is the offset of its save slot from the current | |
9623 | stack pointer. */ | |
e1260576 | 9624 | |
ab77a036 RS |
9625 | static void |
9626 | mips_save_restore_reg (enum machine_mode mode, int regno, | |
9627 | HOST_WIDE_INT offset, mips_save_restore_fn fn) | |
9628 | { | |
9629 | rtx mem; | |
e1260576 | 9630 | |
ab77a036 | 9631 | mem = gen_frame_mem (mode, plus_constant (stack_pointer_rtx, offset)); |
ab77a036 RS |
9632 | fn (gen_rtx_REG (mode, regno), mem); |
9633 | } | |
e1260576 | 9634 | |
e19da24c CF |
9635 | /* Call FN for each accumlator that is saved by the current function. |
9636 | SP_OFFSET is the offset of the current stack pointer from the start | |
9637 | of the frame. */ | |
9638 | ||
9639 | static void | |
9640 | mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn) | |
9641 | { | |
9642 | HOST_WIDE_INT offset; | |
9643 | int regno; | |
9644 | ||
9645 | offset = cfun->machine->frame.acc_sp_offset - sp_offset; | |
9646 | if (BITSET_P (cfun->machine->frame.acc_mask, 0)) | |
9647 | { | |
9648 | mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn); | |
9649 | offset -= UNITS_PER_WORD; | |
9650 | mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn); | |
9651 | offset -= UNITS_PER_WORD; | |
9652 | } | |
9653 | ||
9654 | for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++) | |
9655 | if (BITSET_P (cfun->machine->frame.acc_mask, | |
9656 | ((regno - DSP_ACC_REG_FIRST) / 2) + 1)) | |
9657 | { | |
9658 | mips_save_restore_reg (word_mode, regno, offset, fn); | |
9659 | offset -= UNITS_PER_WORD; | |
9660 | } | |
9661 | } | |
9662 | ||
ab77a036 RS |
9663 | /* Call FN for each register that is saved by the current function. |
9664 | SP_OFFSET is the offset of the current stack pointer from the start | |
9665 | of the frame. */ | |
a94dbf2c | 9666 | |
ab77a036 | 9667 | static void |
e19da24c CF |
9668 | mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset, |
9669 | mips_save_restore_fn fn) | |
ab77a036 RS |
9670 | { |
9671 | enum machine_mode fpr_mode; | |
9672 | HOST_WIDE_INT offset; | |
9673 | int regno; | |
2bcb2ab3 | 9674 | |
ab77a036 RS |
9675 | /* Save registers starting from high to low. The debuggers prefer at least |
9676 | the return register be stored at func+4, and also it allows us not to | |
9677 | need a nop in the epilogue if at least one register is reloaded in | |
9678 | addition to return address. */ | |
9679 | offset = cfun->machine->frame.gp_sp_offset - sp_offset; | |
9680 | for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--) | |
9681 | if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) | |
9682 | { | |
c376dbfb DD |
9683 | /* Record the ra offset for use by mips_function_profiler. */ |
9684 | if (regno == RETURN_ADDR_REGNUM) | |
9685 | cfun->machine->frame.ra_fp_offset = offset + sp_offset; | |
6e75e6e3 RS |
9686 | mips_save_restore_reg (word_mode, regno, offset, fn); |
9687 | offset -= UNITS_PER_WORD; | |
ab77a036 RS |
9688 | } |
9689 | ||
9690 | /* This loop must iterate over the same space as its companion in | |
16dc5c28 | 9691 | mips_compute_frame_info. */ |
ab77a036 RS |
9692 | offset = cfun->machine->frame.fp_sp_offset - sp_offset; |
9693 | fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode); | |
65239d20 | 9694 | for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1; |
ab77a036 RS |
9695 | regno >= FP_REG_FIRST; |
9696 | regno -= MAX_FPRS_PER_FMT) | |
9697 | if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) | |
9698 | { | |
9699 | mips_save_restore_reg (fpr_mode, regno, offset, fn); | |
9700 | offset -= GET_MODE_SIZE (fpr_mode); | |
9701 | } | |
9702 | } | |
0c433c31 RS |
9703 | |
9704 | /* Return true if a move between register REGNO and its save slot (MEM) | |
9705 | can be done in a single move. LOAD_P is true if we are loading | |
9706 | from the slot, false if we are storing to it. */ | |
9707 | ||
9708 | static bool | |
9709 | mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p) | |
9710 | { | |
9711 | /* There is a specific MIPS16 instruction for saving $31 to the stack. */ | |
293593b1 | 9712 | if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM) |
0c433c31 RS |
9713 | return false; |
9714 | ||
9715 | return mips_secondary_reload_class (REGNO_REG_CLASS (regno), | |
9716 | GET_MODE (mem), mem, load_p) == NO_REGS; | |
9717 | } | |
9718 | ||
9719 | /* Emit a move from SRC to DEST, given that one of them is a register | |
9720 | save slot and that the other is a register. TEMP is a temporary | |
9721 | GPR of the same mode that is available if need be. */ | |
9722 | ||
9723 | void | |
9724 | mips_emit_save_slot_move (rtx dest, rtx src, rtx temp) | |
9725 | { | |
9726 | unsigned int regno; | |
9727 | rtx mem; | |
9728 | ||
9729 | if (REG_P (src)) | |
9730 | { | |
9731 | regno = REGNO (src); | |
9732 | mem = dest; | |
9733 | } | |
9734 | else | |
9735 | { | |
9736 | regno = REGNO (dest); | |
9737 | mem = src; | |
9738 | } | |
9739 | ||
9740 | if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ()) | |
9741 | { | |
9742 | /* We don't yet know whether we'll need this instruction or not. | |
9743 | Postpone the decision by emitting a ghost move. This move | |
9744 | is specifically not frame-related; only the split version is. */ | |
9745 | if (TARGET_64BIT) | |
9746 | emit_insn (gen_move_gpdi (dest, src)); | |
9747 | else | |
9748 | emit_insn (gen_move_gpsi (dest, src)); | |
9749 | return; | |
9750 | } | |
9751 | ||
9752 | if (regno == HI_REGNUM) | |
9753 | { | |
9754 | if (REG_P (dest)) | |
9755 | { | |
9756 | mips_emit_move (temp, src); | |
9757 | if (TARGET_64BIT) | |
9758 | emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST), | |
9759 | temp, gen_rtx_REG (DImode, LO_REGNUM))); | |
9760 | else | |
9761 | emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST), | |
9762 | temp, gen_rtx_REG (SImode, LO_REGNUM))); | |
9763 | } | |
9764 | else | |
9765 | { | |
9766 | if (TARGET_64BIT) | |
9767 | emit_insn (gen_mfhidi_ti (temp, | |
9768 | gen_rtx_REG (TImode, MD_REG_FIRST))); | |
9769 | else | |
9770 | emit_insn (gen_mfhisi_di (temp, | |
9771 | gen_rtx_REG (DImode, MD_REG_FIRST))); | |
9772 | mips_emit_move (dest, temp); | |
9773 | } | |
9774 | } | |
9775 | else if (mips_direct_save_slot_move_p (regno, mem, mem == src)) | |
9776 | mips_emit_move (dest, src); | |
9777 | else | |
9778 | { | |
9779 | gcc_assert (!reg_overlap_mentioned_p (dest, temp)); | |
9780 | mips_emit_move (temp, src); | |
9781 | mips_emit_move (dest, temp); | |
9782 | } | |
9783 | if (MEM_P (dest)) | |
9784 | mips_set_frame_expr (mips_frame_set (dest, src)); | |
9785 | } | |
ab77a036 RS |
9786 | \f |
9787 | /* If we're generating n32 or n64 abicalls, and the current function | |
9788 | does not use $28 as its global pointer, emit a cplocal directive. | |
9789 | Use pic_offset_table_rtx as the argument to the directive. */ | |
9790 | ||
9791 | static void | |
9792 | mips_output_cplocal (void) | |
9793 | { | |
9794 | if (!TARGET_EXPLICIT_RELOCS | |
0c433c31 | 9795 | && mips_must_initialize_gp_p () |
ab77a036 RS |
9796 | && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM) |
9797 | output_asm_insn (".cplocal %+", 0); | |
9798 | } | |
9799 | ||
65239d20 | 9800 | /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */ |
ab77a036 RS |
9801 | |
9802 | static void | |
9803 | mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
9804 | { | |
9805 | const char *fnname; | |
ab77a036 RS |
9806 | |
9807 | #ifdef SDB_DEBUGGING_INFO | |
9808 | if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG) | |
9809 | SDB_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl)); | |
9810 | #endif | |
9811 | ||
65239d20 RS |
9812 | /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle |
9813 | floating-point arguments. */ | |
ab77a036 RS |
9814 | if (TARGET_MIPS16 |
9815 | && TARGET_HARD_FLOAT_ABI | |
38173d38 | 9816 | && crtl->args.info.fp_code != 0) |
65239d20 | 9817 | mips16_build_function_stub (); |
ab77a036 | 9818 | |
b2b61607 RS |
9819 | /* Get the function name the same way that toplev.c does before calling |
9820 | assemble_start_function. This is needed so that the name used here | |
9821 | exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ | |
9822 | fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
9823 | mips_start_function_definition (fnname, TARGET_MIPS16); | |
f833ffd4 | 9824 | |
65239d20 | 9825 | /* Output MIPS-specific frame information. */ |
ab77a036 RS |
9826 | if (!flag_inhibit_size_directive) |
9827 | { | |
65239d20 RS |
9828 | const struct mips_frame_info *frame; |
9829 | ||
9830 | frame = &cfun->machine->frame; | |
9831 | ||
9832 | /* .frame FRAMEREG, FRAMESIZE, RETREG. */ | |
ab77a036 RS |
9833 | fprintf (file, |
9834 | "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t" | |
65239d20 RS |
9835 | "# vars= " HOST_WIDE_INT_PRINT_DEC |
9836 | ", regs= %d/%d" | |
ab77a036 RS |
9837 | ", args= " HOST_WIDE_INT_PRINT_DEC |
9838 | ", gp= " HOST_WIDE_INT_PRINT_DEC "\n", | |
65239d20 RS |
9839 | reg_names[frame_pointer_needed |
9840 | ? HARD_FRAME_POINTER_REGNUM | |
9841 | : STACK_POINTER_REGNUM], | |
f374e413 | 9842 | (frame_pointer_needed |
65239d20 RS |
9843 | ? frame->total_size - frame->hard_frame_pointer_offset |
9844 | : frame->total_size), | |
293593b1 | 9845 | reg_names[RETURN_ADDR_REGNUM], |
65239d20 RS |
9846 | frame->var_size, |
9847 | frame->num_gp, frame->num_fp, | |
9848 | frame->args_size, | |
9849 | frame->cprestore_size); | |
be763023 | 9850 | |
65239d20 | 9851 | /* .mask MASK, OFFSET. */ |
ab77a036 | 9852 | fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", |
65239d20 | 9853 | frame->mask, frame->gp_save_offset); |
d8d5b1e1 | 9854 | |
65239d20 RS |
9855 | /* .fmask MASK, OFFSET. */ |
9856 | fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n", | |
9857 | frame->fmask, frame->fp_save_offset); | |
ab77a036 RS |
9858 | } |
9859 | ||
65239d20 RS |
9860 | /* Handle the initialization of $gp for SVR4 PIC, if applicable. |
9861 | Also emit the ".set noreorder; .set nomacro" sequence for functions | |
9862 | that need it. */ | |
0c433c31 RS |
9863 | if (mips_must_initialize_gp_p () |
9864 | && mips_current_loadgp_style () == LOADGP_OLDABI) | |
ab77a036 | 9865 | { |
08d0963a RS |
9866 | if (TARGET_MIPS16) |
9867 | { | |
9868 | /* This is a fixed-form sequence. The position of the | |
9869 | first two instructions is important because of the | |
9870 | way _gp_disp is defined. */ | |
9871 | output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0); | |
9872 | output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0); | |
9873 | output_asm_insn ("sll\t$2,16", 0); | |
9874 | output_asm_insn ("addu\t$2,$3", 0); | |
9875 | } | |
ab77a036 | 9876 | else |
cf5fb4b0 RS |
9877 | { |
9878 | /* .cpload must be in a .set noreorder but not a | |
9879 | .set nomacro block. */ | |
9880 | mips_push_asm_switch (&mips_noreorder); | |
9881 | output_asm_insn (".cpload\t%^", 0); | |
9882 | if (!cfun->machine->all_noreorder_p) | |
9883 | mips_pop_asm_switch (&mips_noreorder); | |
9884 | else | |
9885 | mips_push_asm_switch (&mips_nomacro); | |
9886 | } | |
ab77a036 RS |
9887 | } |
9888 | else if (cfun->machine->all_noreorder_p) | |
cf5fb4b0 RS |
9889 | { |
9890 | mips_push_asm_switch (&mips_noreorder); | |
9891 | mips_push_asm_switch (&mips_nomacro); | |
9892 | } | |
ab77a036 RS |
9893 | |
9894 | /* Tell the assembler which register we're using as the global | |
9895 | pointer. This is needed for thunks, since they can use either | |
9896 | explicit relocs or assembler macros. */ | |
9897 | mips_output_cplocal (); | |
cee98a59 | 9898 | } |
ab77a036 | 9899 | |
65239d20 | 9900 | /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */ |
b5e9dd03 | 9901 | |
08c148a8 | 9902 | static void |
b4966b1b RS |
9903 | mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, |
9904 | HOST_WIDE_INT size ATTRIBUTE_UNUSED) | |
cee98a59 | 9905 | { |
b2b61607 RS |
9906 | const char *fnname; |
9907 | ||
b85aed9e | 9908 | /* Reinstate the normal $gp. */ |
6fb5fa3c | 9909 | SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM); |
b85aed9e RS |
9910 | mips_output_cplocal (); |
9911 | ||
6f2993e5 RS |
9912 | if (cfun->machine->all_noreorder_p) |
9913 | { | |
cf5fb4b0 RS |
9914 | mips_pop_asm_switch (&mips_nomacro); |
9915 | mips_pop_asm_switch (&mips_noreorder); | |
6f2993e5 RS |
9916 | } |
9917 | ||
b2b61607 RS |
9918 | /* Get the function name the same way that toplev.c does before calling |
9919 | assemble_start_function. This is needed so that the name used here | |
9920 | exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */ | |
9921 | fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); | |
9922 | mips_end_function_definition (fnname); | |
cee98a59 | 9923 | } |
0fb5ac6f | 9924 | \f |
ab77a036 | 9925 | /* Save register REG to MEM. Make the instruction frame-related. */ |
be763023 RS |
9926 | |
9927 | static void | |
ab77a036 | 9928 | mips_save_reg (rtx reg, rtx mem) |
be763023 | 9929 | { |
ab77a036 | 9930 | if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64) |
be763023 | 9931 | { |
ab77a036 RS |
9932 | rtx x1, x2; |
9933 | ||
9934 | if (mips_split_64bit_move_p (mem, reg)) | |
9935 | mips_split_doubleword_move (mem, reg); | |
9936 | else | |
9937 | mips_emit_move (mem, reg); | |
9938 | ||
65239d20 RS |
9939 | x1 = mips_frame_set (mips_subword (mem, false), |
9940 | mips_subword (reg, false)); | |
9941 | x2 = mips_frame_set (mips_subword (mem, true), | |
9942 | mips_subword (reg, true)); | |
ab77a036 | 9943 | mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2))); |
be763023 RS |
9944 | } |
9945 | else | |
0c433c31 | 9946 | mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg))); |
be763023 RS |
9947 | } |
9948 | ||
ab77a036 | 9949 | /* The __gnu_local_gp symbol. */ |
be763023 | 9950 | |
ab77a036 | 9951 | static GTY(()) rtx mips_gnu_local_gp; |
0fb5ac6f | 9952 | |
ab77a036 RS |
9953 | /* If we're generating n32 or n64 abicalls, emit instructions |
9954 | to set up the global pointer. */ | |
0fb5ac6f | 9955 | |
ab77a036 RS |
9956 | static void |
9957 | mips_emit_loadgp (void) | |
9958 | { | |
5557aad2 | 9959 | rtx addr, offset, incoming_address, base, index, pic_reg; |
d33289b2 | 9960 | |
08d0963a | 9961 | pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx; |
ab77a036 | 9962 | switch (mips_current_loadgp_style ()) |
a38e0142 | 9963 | { |
ab77a036 RS |
9964 | case LOADGP_ABSOLUTE: |
9965 | if (mips_gnu_local_gp == NULL) | |
9966 | { | |
9967 | mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp"); | |
9968 | SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL; | |
9969 | } | |
5557aad2 RS |
9970 | emit_insn (Pmode == SImode |
9971 | ? gen_loadgp_absolute_si (pic_reg, mips_gnu_local_gp) | |
9972 | : gen_loadgp_absolute_di (pic_reg, mips_gnu_local_gp)); | |
ab77a036 | 9973 | break; |
a38e0142 | 9974 | |
08d0963a RS |
9975 | case LOADGP_OLDABI: |
9976 | /* Added by mips_output_function_prologue. */ | |
9977 | break; | |
9978 | ||
ab77a036 RS |
9979 | case LOADGP_NEWABI: |
9980 | addr = XEXP (DECL_RTL (current_function_decl), 0); | |
9981 | offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP); | |
9982 | incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
5557aad2 RS |
9983 | emit_insn (Pmode == SImode |
9984 | ? gen_loadgp_newabi_si (pic_reg, offset, incoming_address) | |
9985 | : gen_loadgp_newabi_di (pic_reg, offset, incoming_address)); | |
ab77a036 | 9986 | break; |
a38e0142 | 9987 | |
ab77a036 RS |
9988 | case LOADGP_RTP: |
9989 | base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE)); | |
9990 | index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX)); | |
5557aad2 RS |
9991 | emit_insn (Pmode == SImode |
9992 | ? gen_loadgp_rtp_si (pic_reg, base, index) | |
9993 | : gen_loadgp_rtp_di (pic_reg, base, index)); | |
ab77a036 RS |
9994 | break; |
9995 | ||
9996 | default: | |
de9f679d | 9997 | return; |
ab77a036 | 9998 | } |
08d0963a RS |
9999 | |
10000 | if (TARGET_MIPS16) | |
10001 | emit_insn (gen_copygp_mips16 (pic_offset_table_rtx, pic_reg)); | |
10002 | ||
de9f679d RS |
10003 | /* Emit a blockage if there are implicit uses of the GP register. |
10004 | This includes profiled functions, because FUNCTION_PROFILE uses | |
10005 | a jal macro. */ | |
10006 | if (!TARGET_EXPLICIT_RELOCS || crtl->profile) | |
10007 | emit_insn (gen_loadgp_blockage ()); | |
ab77a036 RS |
10008 | } |
10009 | ||
e19da24c CF |
10010 | /* A for_each_rtx callback. Stop the search if *X is a kernel register. */ |
10011 | ||
10012 | static int | |
10013 | mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED) | |
10014 | { | |
47ac44d6 | 10015 | return REG_P (*x) && KERNEL_REG_P (REGNO (*x)); |
e19da24c CF |
10016 | } |
10017 | ||
65239d20 | 10018 | /* Expand the "prologue" pattern. */ |
ab77a036 RS |
10019 | |
10020 | void | |
10021 | mips_expand_prologue (void) | |
10022 | { | |
65239d20 | 10023 | const struct mips_frame_info *frame; |
ab77a036 RS |
10024 | HOST_WIDE_INT size; |
10025 | unsigned int nargs; | |
10026 | rtx insn; | |
10027 | ||
8d9d9172 | 10028 | if (cfun->machine->global_pointer != INVALID_REGNUM) |
0c433c31 RS |
10029 | { |
10030 | /* Check whether an insn uses pic_offset_table_rtx, either explicitly | |
10031 | or implicitly. If so, we can commit to using a global pointer | |
10032 | straight away, otherwise we need to defer the decision. */ | |
10033 | if (mips_cfun_has_inflexible_gp_ref_p () | |
10034 | || mips_cfun_has_flexible_gp_ref_p ()) | |
10035 | { | |
10036 | cfun->machine->must_initialize_gp_p = true; | |
10037 | cfun->machine->must_restore_gp_when_clobbered_p = true; | |
10038 | } | |
10039 | ||
10040 | SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer); | |
10041 | } | |
ab77a036 | 10042 | |
65239d20 RS |
10043 | frame = &cfun->machine->frame; |
10044 | size = frame->total_size; | |
ab77a036 RS |
10045 | |
10046 | /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP | |
10047 | bytes beforehand; this is enough to cover the register save area | |
10048 | without going out of range. */ | |
e19da24c CF |
10049 | if (((frame->mask | frame->fmask | frame->acc_mask) != 0) |
10050 | || frame->num_cop0_regs > 0) | |
ab77a036 RS |
10051 | { |
10052 | HOST_WIDE_INT step1; | |
10053 | ||
10054 | step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP); | |
ab77a036 RS |
10055 | if (GENERATE_MIPS16E_SAVE_RESTORE) |
10056 | { | |
10057 | HOST_WIDE_INT offset; | |
10058 | unsigned int mask, regno; | |
10059 | ||
10060 | /* Try to merge argument stores into the save instruction. */ | |
10061 | nargs = mips16e_collect_argument_saves (); | |
10062 | ||
10063 | /* Build the save instruction. */ | |
65239d20 | 10064 | mask = frame->mask; |
ab77a036 RS |
10065 | insn = mips16e_build_save_restore (false, &mask, &offset, |
10066 | nargs, step1); | |
10067 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
10068 | size -= step1; | |
10069 | ||
10070 | /* Check if we need to save other registers. */ | |
10071 | for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++) | |
10072 | if (BITSET_P (mask, regno - GP_REG_FIRST)) | |
10073 | { | |
6e75e6e3 RS |
10074 | offset -= UNITS_PER_WORD; |
10075 | mips_save_restore_reg (word_mode, regno, | |
10076 | offset, mips_save_reg); | |
ab77a036 RS |
10077 | } |
10078 | } | |
10079 | else | |
10080 | { | |
e19da24c CF |
10081 | if (cfun->machine->interrupt_handler_p) |
10082 | { | |
10083 | HOST_WIDE_INT offset; | |
10084 | rtx mem; | |
10085 | ||
10086 | /* If this interrupt is using a shadow register set, we need to | |
10087 | get the stack pointer from the previous register set. */ | |
10088 | if (cfun->machine->use_shadow_register_set_p) | |
10089 | emit_insn (gen_mips_rdpgpr (stack_pointer_rtx, | |
10090 | stack_pointer_rtx)); | |
10091 | ||
10092 | if (!cfun->machine->keep_interrupts_masked_p) | |
10093 | { | |
10094 | /* Move from COP0 Cause to K0. */ | |
10095 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM), | |
10096 | gen_rtx_REG (SImode, | |
10097 | COP0_CAUSE_REG_NUM))); | |
10098 | /* Move from COP0 EPC to K1. */ | |
10099 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM), | |
10100 | gen_rtx_REG (SImode, | |
10101 | COP0_EPC_REG_NUM))); | |
10102 | } | |
10103 | ||
10104 | /* Allocate the first part of the frame. */ | |
10105 | insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, | |
10106 | GEN_INT (-step1)); | |
10107 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
10108 | size -= step1; | |
10109 | ||
10110 | /* Start at the uppermost location for saving. */ | |
10111 | offset = frame->cop0_sp_offset - size; | |
10112 | if (!cfun->machine->keep_interrupts_masked_p) | |
10113 | { | |
10114 | /* Push EPC into its stack slot. */ | |
10115 | mem = gen_frame_mem (word_mode, | |
10116 | plus_constant (stack_pointer_rtx, | |
10117 | offset)); | |
10118 | mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM)); | |
10119 | offset -= UNITS_PER_WORD; | |
10120 | } | |
10121 | ||
10122 | /* Move from COP0 Status to K1. */ | |
10123 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM), | |
10124 | gen_rtx_REG (SImode, | |
10125 | COP0_STATUS_REG_NUM))); | |
10126 | ||
10127 | /* Right justify the RIPL in k0. */ | |
10128 | if (!cfun->machine->keep_interrupts_masked_p) | |
10129 | emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM), | |
10130 | gen_rtx_REG (SImode, K0_REG_NUM), | |
10131 | GEN_INT (CAUSE_IPL))); | |
10132 | ||
10133 | /* Push Status into its stack slot. */ | |
10134 | mem = gen_frame_mem (word_mode, | |
10135 | plus_constant (stack_pointer_rtx, offset)); | |
10136 | mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM)); | |
10137 | offset -= UNITS_PER_WORD; | |
10138 | ||
10139 | /* Insert the RIPL into our copy of SR (k1) as the new IPL. */ | |
10140 | if (!cfun->machine->keep_interrupts_masked_p) | |
10141 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
10142 | GEN_INT (6), | |
10143 | GEN_INT (SR_IPL), | |
10144 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
10145 | ||
10146 | if (!cfun->machine->keep_interrupts_masked_p) | |
10147 | /* Enable interrupts by clearing the KSU ERL and EXL bits. | |
10148 | IE is already the correct value, so we don't have to do | |
10149 | anything explicit. */ | |
10150 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
10151 | GEN_INT (4), | |
10152 | GEN_INT (SR_EXL), | |
10153 | gen_rtx_REG (SImode, GP_REG_FIRST))); | |
10154 | else | |
10155 | /* Disable interrupts by clearing the KSU, ERL, EXL, | |
10156 | and IE bits. */ | |
10157 | emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM), | |
10158 | GEN_INT (5), | |
10159 | GEN_INT (SR_IE), | |
10160 | gen_rtx_REG (SImode, GP_REG_FIRST))); | |
10161 | } | |
10162 | else | |
10163 | { | |
10164 | insn = gen_add3_insn (stack_pointer_rtx, | |
10165 | stack_pointer_rtx, | |
10166 | GEN_INT (-step1)); | |
10167 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
10168 | size -= step1; | |
10169 | } | |
10170 | mips_for_each_saved_acc (size, mips_save_reg); | |
10171 | mips_for_each_saved_gpr_and_fpr (size, mips_save_reg); | |
ab77a036 RS |
10172 | } |
10173 | } | |
10174 | ||
10175 | /* Allocate the rest of the frame. */ | |
10176 | if (size > 0) | |
10177 | { | |
10178 | if (SMALL_OPERAND (-size)) | |
10179 | RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx, | |
10180 | stack_pointer_rtx, | |
10181 | GEN_INT (-size)))) = 1; | |
10182 | else | |
10183 | { | |
10184 | mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size)); | |
10185 | if (TARGET_MIPS16) | |
10186 | { | |
10187 | /* There are no instructions to add or subtract registers | |
10188 | from the stack pointer, so use the frame pointer as a | |
10189 | temporary. We should always be using a frame pointer | |
10190 | in this case anyway. */ | |
10191 | gcc_assert (frame_pointer_needed); | |
10192 | mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); | |
10193 | emit_insn (gen_sub3_insn (hard_frame_pointer_rtx, | |
10194 | hard_frame_pointer_rtx, | |
10195 | MIPS_PROLOGUE_TEMP (Pmode))); | |
10196 | mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx); | |
10197 | } | |
10198 | else | |
10199 | emit_insn (gen_sub3_insn (stack_pointer_rtx, | |
10200 | stack_pointer_rtx, | |
10201 | MIPS_PROLOGUE_TEMP (Pmode))); | |
10202 | ||
10203 | /* Describe the combined effect of the previous instructions. */ | |
10204 | mips_set_frame_expr | |
10205 | (gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
10206 | plus_constant (stack_pointer_rtx, -size))); | |
10207 | } | |
10208 | } | |
10209 | ||
f374e413 | 10210 | /* Set up the frame pointer, if we're using one. */ |
ab77a036 RS |
10211 | if (frame_pointer_needed) |
10212 | { | |
f374e413 RS |
10213 | HOST_WIDE_INT offset; |
10214 | ||
65239d20 | 10215 | offset = frame->hard_frame_pointer_offset; |
f374e413 | 10216 | if (offset == 0) |
ab77a036 | 10217 | { |
f374e413 RS |
10218 | insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); |
10219 | RTX_FRAME_RELATED_P (insn) = 1; | |
10220 | } | |
10221 | else if (SMALL_OPERAND (offset)) | |
10222 | { | |
10223 | insn = gen_add3_insn (hard_frame_pointer_rtx, | |
10224 | stack_pointer_rtx, GEN_INT (offset)); | |
10225 | RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; | |
ab77a036 RS |
10226 | } |
10227 | else | |
f374e413 RS |
10228 | { |
10229 | mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset)); | |
10230 | mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx); | |
10231 | emit_insn (gen_add3_insn (hard_frame_pointer_rtx, | |
10232 | hard_frame_pointer_rtx, | |
10233 | MIPS_PROLOGUE_TEMP (Pmode))); | |
10234 | mips_set_frame_expr | |
10235 | (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, | |
10236 | plus_constant (stack_pointer_rtx, offset))); | |
10237 | } | |
ab77a036 RS |
10238 | } |
10239 | ||
10240 | mips_emit_loadgp (); | |
10241 | ||
65239d20 | 10242 | /* Initialize the $gp save slot. */ |
0c433c31 | 10243 | if (mips_cfun_has_cprestore_slot_p ()) |
08d0963a | 10244 | { |
0c433c31 RS |
10245 | rtx base, mem, gp, temp; |
10246 | HOST_WIDE_INT offset; | |
10247 | ||
10248 | mips_get_cprestore_base_and_offset (&base, &offset, false); | |
10249 | mem = gen_frame_mem (Pmode, plus_constant (base, offset)); | |
10250 | gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx; | |
10251 | temp = (SMALL_OPERAND (offset) | |
10252 | ? gen_rtx_SCRATCH (Pmode) | |
10253 | : MIPS_PROLOGUE_TEMP (Pmode)); | |
10254 | emit_insn (gen_potential_cprestore (mem, GEN_INT (offset), gp, temp)); | |
10255 | ||
10256 | mips_get_cprestore_base_and_offset (&base, &offset, true); | |
10257 | mem = gen_frame_mem (Pmode, plus_constant (base, offset)); | |
10258 | emit_insn (gen_use_cprestore (mem)); | |
08d0963a | 10259 | } |
ab77a036 | 10260 | |
e19da24c CF |
10261 | /* We need to search back to the last use of K0 or K1. */ |
10262 | if (cfun->machine->interrupt_handler_p) | |
10263 | { | |
10264 | for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn)) | |
10265 | if (INSN_P (insn) | |
10266 | && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL)) | |
10267 | break; | |
10268 | /* Emit a move from K1 to COP0 Status after insn. */ | |
10269 | gcc_assert (insn != NULL_RTX); | |
10270 | emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM), | |
10271 | gen_rtx_REG (SImode, K1_REG_NUM)), | |
10272 | insn); | |
10273 | } | |
10274 | ||
ab77a036 RS |
10275 | /* If we are profiling, make sure no instructions are scheduled before |
10276 | the call to mcount. */ | |
e3b5732b | 10277 | if (crtl->profile) |
ab77a036 RS |
10278 | emit_insn (gen_blockage ()); |
10279 | } | |
10280 | \f | |
10281 | /* Emit instructions to restore register REG from slot MEM. */ | |
10282 | ||
10283 | static void | |
10284 | mips_restore_reg (rtx reg, rtx mem) | |
10285 | { | |
65239d20 | 10286 | /* There's no MIPS16 instruction to load $31 directly. Load into |
ab77a036 | 10287 | $7 instead and adjust the return insn appropriately. */ |
293593b1 | 10288 | if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM) |
65239d20 | 10289 | reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7); |
ab77a036 | 10290 | |
0c433c31 | 10291 | mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg))); |
ab77a036 RS |
10292 | } |
10293 | ||
2f7e2abb RS |
10294 | /* Emit any instructions needed before a return. */ |
10295 | ||
10296 | void | |
10297 | mips_expand_before_return (void) | |
10298 | { | |
10299 | /* When using a call-clobbered gp, we start out with unified call | |
10300 | insns that include instructions to restore the gp. We then split | |
10301 | these unified calls after reload. These split calls explicitly | |
10302 | clobber gp, so there is no need to define | |
10303 | PIC_OFFSET_TABLE_REG_CALL_CLOBBERED. | |
10304 | ||
10305 | For consistency, we should also insert an explicit clobber of $28 | |
10306 | before return insns, so that the post-reload optimizers know that | |
10307 | the register is not live on exit. */ | |
10308 | if (TARGET_CALL_CLOBBERED_GP) | |
10309 | emit_clobber (pic_offset_table_rtx); | |
10310 | } | |
10311 | ||
65239d20 RS |
10312 | /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P |
10313 | says which. */ | |
ab77a036 RS |
10314 | |
10315 | void | |
65239d20 | 10316 | mips_expand_epilogue (bool sibcall_p) |
ab77a036 | 10317 | { |
65239d20 | 10318 | const struct mips_frame_info *frame; |
ab77a036 | 10319 | HOST_WIDE_INT step1, step2; |
e19da24c | 10320 | rtx base, target, insn; |
ab77a036 RS |
10321 | |
10322 | if (!sibcall_p && mips_can_use_return_insn ()) | |
10323 | { | |
10324 | emit_jump_insn (gen_return ()); | |
10325 | return; | |
10326 | } | |
10327 | ||
65239d20 | 10328 | /* In MIPS16 mode, if the return value should go into a floating-point |
ab77a036 RS |
10329 | register, we need to call a helper routine to copy it over. */ |
10330 | if (mips16_cfun_returns_in_fpr_p ()) | |
5f5fe6d9 | 10331 | mips16_copy_fpr_return_value (); |
1f2d8f51 | 10332 | |
be763023 RS |
10333 | /* Split the frame into two. STEP1 is the amount of stack we should |
10334 | deallocate before restoring the registers. STEP2 is the amount we | |
10335 | should deallocate afterwards. | |
10336 | ||
10337 | Start off by assuming that no registers need to be restored. */ | |
65239d20 RS |
10338 | frame = &cfun->machine->frame; |
10339 | step1 = frame->total_size; | |
be763023 RS |
10340 | step2 = 0; |
10341 | ||
f374e413 | 10342 | /* Work out which register holds the frame address. */ |
be763023 RS |
10343 | if (!frame_pointer_needed) |
10344 | base = stack_pointer_rtx; | |
10345 | else | |
0fb5ac6f | 10346 | { |
be763023 | 10347 | base = hard_frame_pointer_rtx; |
65239d20 | 10348 | step1 -= frame->hard_frame_pointer_offset; |
0fb5ac6f MM |
10349 | } |
10350 | ||
be763023 RS |
10351 | /* If we need to restore registers, deallocate as much stack as |
10352 | possible in the second step without going out of range. */ | |
e19da24c CF |
10353 | if ((frame->mask | frame->fmask | frame->acc_mask) != 0 |
10354 | || frame->num_cop0_regs > 0) | |
0fb5ac6f | 10355 | { |
be763023 RS |
10356 | step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP); |
10357 | step1 -= step2; | |
10358 | } | |
f5963e61 | 10359 | |
be763023 RS |
10360 | /* Set TARGET to BASE + STEP1. */ |
10361 | target = base; | |
10362 | if (step1 > 0) | |
10363 | { | |
10364 | rtx adjust; | |
2bcb2ab3 | 10365 | |
be763023 RS |
10366 | /* Get an rtx for STEP1 that we can add to BASE. */ |
10367 | adjust = GEN_INT (step1); | |
10368 | if (!SMALL_OPERAND (step1)) | |
9e800206 | 10369 | { |
51e7252a | 10370 | mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust); |
be763023 | 10371 | adjust = MIPS_EPILOGUE_TEMP (Pmode); |
9e800206 RH |
10372 | } |
10373 | ||
be763023 RS |
10374 | /* Normal mode code can copy the result straight into $sp. */ |
10375 | if (!TARGET_MIPS16) | |
10376 | target = stack_pointer_rtx; | |
9e800206 | 10377 | |
be763023 RS |
10378 | emit_insn (gen_add3_insn (target, base, adjust)); |
10379 | } | |
282cb01b | 10380 | |
be763023 RS |
10381 | /* Copy TARGET into the stack pointer. */ |
10382 | if (target != stack_pointer_rtx) | |
51e7252a | 10383 | mips_emit_move (stack_pointer_rtx, target); |
282cb01b | 10384 | |
14976818 RS |
10385 | /* If we're using addressing macros, $gp is implicitly used by all |
10386 | SYMBOL_REFs. We must emit a blockage insn before restoring $gp | |
10387 | from the stack. */ | |
10388 | if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS) | |
be763023 | 10389 | emit_insn (gen_blockage ()); |
282cb01b | 10390 | |
65239d20 | 10391 | if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0) |
e1260576 RS |
10392 | { |
10393 | unsigned int regno, mask; | |
10394 | HOST_WIDE_INT offset; | |
10395 | rtx restore; | |
10396 | ||
10397 | /* Generate the restore instruction. */ | |
65239d20 | 10398 | mask = frame->mask; |
e1260576 RS |
10399 | restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2); |
10400 | ||
10401 | /* Restore any other registers manually. */ | |
10402 | for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++) | |
10403 | if (BITSET_P (mask, regno - GP_REG_FIRST)) | |
10404 | { | |
6e75e6e3 RS |
10405 | offset -= UNITS_PER_WORD; |
10406 | mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg); | |
e1260576 | 10407 | } |
be763023 | 10408 | |
e1260576 RS |
10409 | /* Restore the remaining registers and deallocate the final bit |
10410 | of the frame. */ | |
10411 | emit_insn (restore); | |
10412 | } | |
10413 | else | |
10414 | { | |
10415 | /* Restore the registers. */ | |
e19da24c CF |
10416 | mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg); |
10417 | mips_for_each_saved_gpr_and_fpr (frame->total_size - step2, | |
10418 | mips_restore_reg); | |
e1260576 | 10419 | |
e19da24c CF |
10420 | if (cfun->machine->interrupt_handler_p) |
10421 | { | |
10422 | HOST_WIDE_INT offset; | |
10423 | rtx mem; | |
10424 | ||
10425 | offset = frame->cop0_sp_offset - (frame->total_size - step2); | |
10426 | if (!cfun->machine->keep_interrupts_masked_p) | |
10427 | { | |
10428 | /* Restore the original EPC. */ | |
10429 | mem = gen_frame_mem (word_mode, | |
10430 | plus_constant (stack_pointer_rtx, offset)); | |
10431 | mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem); | |
10432 | offset -= UNITS_PER_WORD; | |
10433 | ||
10434 | /* Move to COP0 EPC. */ | |
10435 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM), | |
10436 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
10437 | } | |
10438 | ||
10439 | /* Restore the original Status. */ | |
10440 | mem = gen_frame_mem (word_mode, | |
10441 | plus_constant (stack_pointer_rtx, offset)); | |
10442 | mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem); | |
10443 | offset -= UNITS_PER_WORD; | |
10444 | ||
10445 | /* If we don't use shoadow register set, we need to update SP. */ | |
10446 | if (!cfun->machine->use_shadow_register_set_p && step2 > 0) | |
10447 | emit_insn (gen_add3_insn (stack_pointer_rtx, | |
10448 | stack_pointer_rtx, | |
10449 | GEN_INT (step2))); | |
10450 | ||
10451 | /* Move to COP0 Status. */ | |
10452 | emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM), | |
10453 | gen_rtx_REG (SImode, K0_REG_NUM))); | |
10454 | } | |
10455 | else | |
10456 | { | |
10457 | /* Deallocate the final bit of the frame. */ | |
10458 | if (step2 > 0) | |
10459 | emit_insn (gen_add3_insn (stack_pointer_rtx, | |
10460 | stack_pointer_rtx, | |
10461 | GEN_INT (step2))); | |
10462 | } | |
e1260576 | 10463 | } |
91e01231 | 10464 | |
71cc389b | 10465 | /* Add in the __builtin_eh_return stack adjustment. We need to |
65239d20 | 10466 | use a temporary in MIPS16 code. */ |
e3b5732b | 10467 | if (crtl->calls_eh_return) |
be763023 RS |
10468 | { |
10469 | if (TARGET_MIPS16) | |
10470 | { | |
51e7252a | 10471 | mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx); |
be763023 RS |
10472 | emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode), |
10473 | MIPS_EPILOGUE_TEMP (Pmode), | |
10474 | EH_RETURN_STACKADJ_RTX)); | |
51e7252a | 10475 | mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode)); |
9e800206 | 10476 | } |
be763023 RS |
10477 | else |
10478 | emit_insn (gen_add3_insn (stack_pointer_rtx, | |
10479 | stack_pointer_rtx, | |
10480 | EH_RETURN_STACKADJ_RTX)); | |
0fb5ac6f | 10481 | } |
be763023 | 10482 | |
cafe096b EC |
10483 | if (!sibcall_p) |
10484 | { | |
2f7e2abb | 10485 | mips_expand_before_return (); |
e19da24c CF |
10486 | if (cfun->machine->interrupt_handler_p) |
10487 | { | |
10488 | /* Interrupt handlers generate eret or deret. */ | |
10489 | if (cfun->machine->use_debug_exception_return_p) | |
10490 | emit_jump_insn (gen_mips_deret ()); | |
10491 | else | |
10492 | emit_jump_insn (gen_mips_eret ()); | |
10493 | } | |
10494 | else | |
10495 | { | |
10496 | unsigned int regno; | |
10497 | ||
10498 | /* When generating MIPS16 code, the normal | |
10499 | mips_for_each_saved_gpr_and_fpr path will restore the return | |
10500 | address into $7 rather than $31. */ | |
10501 | if (TARGET_MIPS16 | |
10502 | && !GENERATE_MIPS16E_SAVE_RESTORE | |
293593b1 | 10503 | && BITSET_P (frame->mask, RETURN_ADDR_REGNUM)) |
e19da24c CF |
10504 | regno = GP_REG_FIRST + 7; |
10505 | else | |
293593b1 | 10506 | regno = RETURN_ADDR_REGNUM; |
e19da24c CF |
10507 | emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno))); |
10508 | } | |
10509 | } | |
10510 | ||
10511 | /* Search from the beginning to the first use of K0 or K1. */ | |
10512 | if (cfun->machine->interrupt_handler_p | |
10513 | && !cfun->machine->keep_interrupts_masked_p) | |
10514 | { | |
10515 | for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn)) | |
10516 | if (INSN_P (insn) | |
10517 | && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL)) | |
10518 | break; | |
10519 | gcc_assert (insn != NULL_RTX); | |
10520 | /* Insert disable interrupts before the first use of K0 or K1. */ | |
10521 | emit_insn_before (gen_mips_di (), insn); | |
10522 | emit_insn_before (gen_mips_ehb (), insn); | |
cafe096b | 10523 | } |
cee98a59 | 10524 | } |
cee98a59 | 10525 | \f |
f5963e61 | 10526 | /* Return nonzero if this function is known to have a null epilogue. |
cee98a59 MM |
10527 | This allows the optimizer to omit jumps to jumps if no stack |
10528 | was created. */ | |
10529 | ||
65239d20 | 10530 | bool |
b4966b1b | 10531 | mips_can_use_return_insn (void) |
cee98a59 | 10532 | { |
e19da24c CF |
10533 | /* Interrupt handlers need to go through the epilogue. */ |
10534 | if (cfun->machine->interrupt_handler_p) | |
10535 | return false; | |
10536 | ||
65239d20 RS |
10537 | if (!reload_completed) |
10538 | return false; | |
cee98a59 | 10539 | |
e3b5732b | 10540 | if (crtl->profile) |
65239d20 | 10541 | return false; |
1f2d8f51 | 10542 | |
65239d20 RS |
10543 | /* In MIPS16 mode, a function that returns a floating-point value |
10544 | needs to arrange to copy the return value into the floating-point | |
2bcb2ab3 | 10545 | registers. */ |
a38e0142 | 10546 | if (mips16_cfun_returns_in_fpr_p ()) |
65239d20 | 10547 | return false; |
2bcb2ab3 | 10548 | |
16dc5c28 | 10549 | return cfun->machine->frame.total_size == 0; |
cee98a59 | 10550 | } |
9753d4e4 | 10551 | \f |
5f5fe6d9 RS |
10552 | /* Return true if register REGNO can store a value of mode MODE. |
10553 | The result of this function is cached in mips_hard_regno_mode_ok. */ | |
10554 | ||
10555 | static bool | |
10556 | mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode) | |
10557 | { | |
10558 | unsigned int size; | |
0a2aaacc | 10559 | enum mode_class mclass; |
5f5fe6d9 RS |
10560 | |
10561 | if (mode == CCV2mode) | |
10562 | return (ISA_HAS_8CC | |
10563 | && ST_REG_P (regno) | |
10564 | && (regno - ST_REG_FIRST) % 2 == 0); | |
10565 | ||
10566 | if (mode == CCV4mode) | |
10567 | return (ISA_HAS_8CC | |
10568 | && ST_REG_P (regno) | |
10569 | && (regno - ST_REG_FIRST) % 4 == 0); | |
10570 | ||
10571 | if (mode == CCmode) | |
10572 | { | |
10573 | if (!ISA_HAS_8CC) | |
10574 | return regno == FPSW_REGNUM; | |
10575 | ||
10576 | return (ST_REG_P (regno) | |
10577 | || GP_REG_P (regno) | |
10578 | || FP_REG_P (regno)); | |
10579 | } | |
10580 | ||
10581 | size = GET_MODE_SIZE (mode); | |
0a2aaacc | 10582 | mclass = GET_MODE_CLASS (mode); |
5f5fe6d9 RS |
10583 | |
10584 | if (GP_REG_P (regno)) | |
10585 | return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD; | |
10586 | ||
10587 | if (FP_REG_P (regno) | |
10588 | && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0 | |
10589 | || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG))) | |
10590 | { | |
10591 | /* Allow TFmode for CCmode reloads. */ | |
10592 | if (mode == TFmode && ISA_HAS_8CC) | |
10593 | return true; | |
10594 | ||
93581857 MS |
10595 | /* Allow 64-bit vector modes for Loongson-2E/2F. */ |
10596 | if (TARGET_LOONGSON_VECTORS | |
10597 | && (mode == V2SImode | |
10598 | || mode == V4HImode | |
10599 | || mode == V8QImode | |
10600 | || mode == DImode)) | |
10601 | return true; | |
10602 | ||
0a2aaacc KG |
10603 | if (mclass == MODE_FLOAT |
10604 | || mclass == MODE_COMPLEX_FLOAT | |
10605 | || mclass == MODE_VECTOR_FLOAT) | |
5f5fe6d9 RS |
10606 | return size <= UNITS_PER_FPVALUE; |
10607 | ||
10608 | /* Allow integer modes that fit into a single register. We need | |
10609 | to put integers into FPRs when using instructions like CVT | |
10610 | and TRUNC. There's no point allowing sizes smaller than a word, | |
10611 | because the FPU has no appropriate load/store instructions. */ | |
0a2aaacc | 10612 | if (mclass == MODE_INT) |
5f5fe6d9 RS |
10613 | return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG; |
10614 | } | |
10615 | ||
10616 | if (ACC_REG_P (regno) | |
10617 | && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode))) | |
10618 | { | |
21dfc6dc RS |
10619 | if (MD_REG_P (regno)) |
10620 | { | |
10621 | /* After a multiplication or division, clobbering HI makes | |
10622 | the value of LO unpredictable, and vice versa. This means | |
10623 | that, for all interesting cases, HI and LO are effectively | |
10624 | a single register. | |
10625 | ||
10626 | We model this by requiring that any value that uses HI | |
10627 | also uses LO. */ | |
10628 | if (size <= UNITS_PER_WORD * 2) | |
10629 | return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST); | |
10630 | } | |
10631 | else | |
10632 | { | |
10633 | /* DSP accumulators do not have the same restrictions as | |
10634 | HI and LO, so we can treat them as normal doubleword | |
10635 | registers. */ | |
10636 | if (size <= UNITS_PER_WORD) | |
10637 | return true; | |
5f5fe6d9 | 10638 | |
21dfc6dc RS |
10639 | if (size <= UNITS_PER_WORD * 2 |
10640 | && ((regno - DSP_ACC_REG_FIRST) & 1) == 0) | |
10641 | return true; | |
10642 | } | |
5f5fe6d9 RS |
10643 | } |
10644 | ||
10645 | if (ALL_COP_REG_P (regno)) | |
0a2aaacc | 10646 | return mclass == MODE_INT && size <= UNITS_PER_WORD; |
5f5fe6d9 | 10647 | |
dbc90b65 RS |
10648 | if (regno == GOT_VERSION_REGNUM) |
10649 | return mode == SImode; | |
10650 | ||
5f5fe6d9 RS |
10651 | return false; |
10652 | } | |
10653 | ||
c862c910 | 10654 | /* Implement HARD_REGNO_NREGS. */ |
b85aed9e | 10655 | |
ab77a036 RS |
10656 | unsigned int |
10657 | mips_hard_regno_nregs (int regno, enum machine_mode mode) | |
b85aed9e | 10658 | { |
ab77a036 | 10659 | if (ST_REG_P (regno)) |
c862c910 RS |
10660 | /* The size of FP status registers is always 4, because they only hold |
10661 | CCmode values, and CCmode is always considered to be 4 bytes wide. */ | |
10662 | return (GET_MODE_SIZE (mode) + 3) / 4; | |
b85aed9e | 10663 | |
c862c910 RS |
10664 | if (FP_REG_P (regno)) |
10665 | return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG; | |
e440de0e | 10666 | |
c862c910 RS |
10667 | /* All other registers are word-sized. */ |
10668 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
10669 | } | |
6fb5fa3c | 10670 | |
c862c910 RS |
10671 | /* Implement CLASS_MAX_NREGS, taking the maximum of the cases |
10672 | in mips_hard_regno_nregs. */ | |
f5678792 | 10673 | |
ab77a036 | 10674 | int |
0a2aaacc | 10675 | mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode) |
ab77a036 | 10676 | { |
c862c910 RS |
10677 | int size; |
10678 | HARD_REG_SET left; | |
10679 | ||
10680 | size = 0x8000; | |
0a2aaacc | 10681 | COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]); |
c862c910 RS |
10682 | if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS])) |
10683 | { | |
10684 | size = MIN (size, 4); | |
10685 | AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]); | |
10686 | } | |
10687 | if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS])) | |
10688 | { | |
10689 | size = MIN (size, UNITS_PER_FPREG); | |
10690 | AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]); | |
10691 | } | |
10692 | if (!hard_reg_set_empty_p (left)) | |
10693 | size = MIN (size, UNITS_PER_WORD); | |
10694 | return (GET_MODE_SIZE (mode) + size - 1) / size; | |
ab77a036 | 10695 | } |
b85aed9e | 10696 | |
65239d20 | 10697 | /* Implement CANNOT_CHANGE_MODE_CLASS. */ |
b85aed9e | 10698 | |
ab77a036 RS |
10699 | bool |
10700 | mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED, | |
10701 | enum machine_mode to ATTRIBUTE_UNUSED, | |
0a2aaacc | 10702 | enum reg_class rclass) |
ab77a036 RS |
10703 | { |
10704 | /* There are several problems with changing the modes of values | |
10705 | in floating-point registers: | |
b85aed9e | 10706 | |
ab77a036 RS |
10707 | - When a multi-word value is stored in paired floating-point |
10708 | registers, the first register always holds the low word. | |
10709 | We therefore can't allow FPRs to change between single-word | |
10710 | and multi-word modes on big-endian targets. | |
b85aed9e | 10711 | |
ab77a036 RS |
10712 | - GCC assumes that each word of a multiword register can be accessed |
10713 | individually using SUBREGs. This is not true for floating-point | |
10714 | registers if they are bigger than a word. | |
b85aed9e | 10715 | |
ab77a036 RS |
10716 | - Loading a 32-bit value into a 64-bit floating-point register |
10717 | will not sign-extend the value, despite what LOAD_EXTEND_OP says. | |
10718 | We can't allow FPRs to change from SImode to to a wider mode on | |
10719 | 64-bit targets. | |
b85aed9e | 10720 | |
ab77a036 RS |
10721 | - If the FPU has already interpreted a value in one format, we must |
10722 | not ask it to treat the value as having a different format. | |
b85aed9e | 10723 | |
43029c10 | 10724 | We therefore disallow all mode changes involving FPRs. */ |
0a2aaacc | 10725 | return reg_classes_intersect_p (FP_REGS, rclass); |
ab77a036 | 10726 | } |
b85aed9e | 10727 | |
42db504c SB |
10728 | /* Implement target hook small_register_classes_for_mode_p. */ |
10729 | ||
10730 | static bool | |
10731 | mips_small_register_classes_for_mode_p (enum machine_mode mode | |
10732 | ATTRIBUTE_UNUSED) | |
10733 | { | |
10734 | return TARGET_MIPS16; | |
10735 | } | |
10736 | ||
ab77a036 | 10737 | /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */ |
b85aed9e | 10738 | |
ab77a036 RS |
10739 | static bool |
10740 | mips_mode_ok_for_mov_fmt_p (enum machine_mode mode) | |
10741 | { | |
10742 | switch (mode) | |
b85aed9e | 10743 | { |
ab77a036 RS |
10744 | case SFmode: |
10745 | return TARGET_HARD_FLOAT; | |
b85aed9e | 10746 | |
ab77a036 RS |
10747 | case DFmode: |
10748 | return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT; | |
b85aed9e | 10749 | |
ab77a036 RS |
10750 | case V2SFmode: |
10751 | return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT; | |
b85aed9e | 10752 | |
ab77a036 RS |
10753 | default: |
10754 | return false; | |
b85aed9e | 10755 | } |
b85aed9e | 10756 | } |
9753d4e4 | 10757 | |
e5a2b69d RS |
10758 | /* Implement MODES_TIEABLE_P. */ |
10759 | ||
10760 | bool | |
10761 | mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) | |
10762 | { | |
10763 | /* FPRs allow no mode punning, so it's not worth tying modes if we'd | |
10764 | prefer to put one of them in FPRs. */ | |
10765 | return (mode1 == mode2 | |
10766 | || (!mips_mode_ok_for_mov_fmt_p (mode1) | |
10767 | && !mips_mode_ok_for_mov_fmt_p (mode2))); | |
10768 | } | |
10769 | ||
ab77a036 | 10770 | /* Implement PREFERRED_RELOAD_CLASS. */ |
7dac2f89 | 10771 | |
ab77a036 | 10772 | enum reg_class |
0a2aaacc | 10773 | mips_preferred_reload_class (rtx x, enum reg_class rclass) |
ab77a036 | 10774 | { |
0a2aaacc | 10775 | if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass)) |
ab77a036 | 10776 | return LEA_REGS; |
9753d4e4 | 10777 | |
0a2aaacc | 10778 | if (reg_class_subset_p (FP_REGS, rclass) |
ab77a036 RS |
10779 | && mips_mode_ok_for_mov_fmt_p (GET_MODE (x))) |
10780 | return FP_REGS; | |
94b9aa66 | 10781 | |
0a2aaacc KG |
10782 | if (reg_class_subset_p (GR_REGS, rclass)) |
10783 | rclass = GR_REGS; | |
94b9aa66 | 10784 | |
0a2aaacc KG |
10785 | if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass)) |
10786 | rclass = M16_REGS; | |
d6b5193b | 10787 | |
0a2aaacc | 10788 | return rclass; |
94b9aa66 RS |
10789 | } |
10790 | ||
aea8cb37 RS |
10791 | /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation. |
10792 | Return a "canonical" class to represent it in later calculations. */ | |
91455597 | 10793 | |
aea8cb37 RS |
10794 | static enum reg_class |
10795 | mips_canonicalize_move_class (enum reg_class rclass) | |
ab77a036 | 10796 | { |
aea8cb37 RS |
10797 | /* All moves involving accumulator registers have the same cost. */ |
10798 | if (reg_class_subset_p (rclass, ACC_REGS)) | |
10799 | rclass = ACC_REGS; | |
10800 | ||
10801 | /* Likewise promote subclasses of general registers to the most | |
10802 | interesting containing class. */ | |
10803 | if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS)) | |
10804 | rclass = M16_REGS; | |
10805 | else if (reg_class_subset_p (rclass, GENERAL_REGS)) | |
10806 | rclass = GENERAL_REGS; | |
10807 | ||
10808 | return rclass; | |
10809 | } | |
10810 | ||
10811 | /* Return the cost of moving a value of mode MODE from a register of | |
10812 | class FROM to a GPR. Return 0 for classes that are unions of other | |
10813 | classes handled by this function. */ | |
10814 | ||
10815 | static int | |
10816 | mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED, | |
10817 | enum reg_class from) | |
10818 | { | |
10819 | switch (from) | |
9753d4e4 | 10820 | { |
aea8cb37 RS |
10821 | case GENERAL_REGS: |
10822 | /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */ | |
10823 | return 2; | |
10824 | ||
10825 | case ACC_REGS: | |
10826 | /* MFLO and MFHI. */ | |
10827 | return 6; | |
10828 | ||
10829 | case FP_REGS: | |
10830 | /* MFC1, etc. */ | |
10831 | return 4; | |
10832 | ||
10833 | case ST_REGS: | |
10834 | /* LUI followed by MOVF. */ | |
10835 | return 4; | |
10836 | ||
10837 | case COP0_REGS: | |
10838 | case COP2_REGS: | |
10839 | case COP3_REGS: | |
10840 | /* This choice of value is historical. */ | |
10841 | return 5; | |
10842 | ||
10843 | default: | |
10844 | return 0; | |
9753d4e4 | 10845 | } |
aea8cb37 RS |
10846 | } |
10847 | ||
10848 | /* Return the cost of moving a value of mode MODE from a GPR to a | |
10849 | register of class TO. Return 0 for classes that are unions of | |
10850 | other classes handled by this function. */ | |
10851 | ||
10852 | static int | |
10853 | mips_move_from_gpr_cost (enum machine_mode mode, enum reg_class to) | |
10854 | { | |
10855 | switch (to) | |
9753d4e4 | 10856 | { |
aea8cb37 RS |
10857 | case GENERAL_REGS: |
10858 | /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */ | |
10859 | return 2; | |
10860 | ||
10861 | case ACC_REGS: | |
10862 | /* MTLO and MTHI. */ | |
10863 | return 6; | |
10864 | ||
10865 | case FP_REGS: | |
10866 | /* MTC1, etc. */ | |
10867 | return 4; | |
10868 | ||
10869 | case ST_REGS: | |
10870 | /* A secondary reload through an FPR scratch. */ | |
10871 | return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS) | |
10872 | + mips_register_move_cost (mode, FP_REGS, ST_REGS)); | |
10873 | ||
10874 | case COP0_REGS: | |
10875 | case COP2_REGS: | |
10876 | case COP3_REGS: | |
10877 | /* This choice of value is historical. */ | |
10878 | return 5; | |
10879 | ||
10880 | default: | |
10881 | return 0; | |
9753d4e4 | 10882 | } |
aea8cb37 RS |
10883 | } |
10884 | ||
10885 | /* Implement REGISTER_MOVE_COST. Return 0 for classes that are the | |
10886 | maximum of the move costs for subclasses; regclass will work out | |
10887 | the maximum for us. */ | |
10888 | ||
10889 | int | |
10890 | mips_register_move_cost (enum machine_mode mode, | |
10891 | enum reg_class from, enum reg_class to) | |
10892 | { | |
10893 | enum reg_class dregs; | |
10894 | int cost1, cost2; | |
10895 | ||
10896 | from = mips_canonicalize_move_class (from); | |
10897 | to = mips_canonicalize_move_class (to); | |
10898 | ||
10899 | /* Handle moves that can be done without using general-purpose registers. */ | |
10900 | if (from == FP_REGS) | |
a318179e | 10901 | { |
aea8cb37 RS |
10902 | if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode)) |
10903 | /* MOV.FMT. */ | |
ab77a036 | 10904 | return 4; |
aea8cb37 RS |
10905 | if (to == ST_REGS) |
10906 | /* The sequence generated by mips_expand_fcc_reload. */ | |
10907 | return 8; | |
ab77a036 | 10908 | } |
aea8cb37 RS |
10909 | |
10910 | /* Handle cases in which only one class deviates from the ideal. */ | |
10911 | dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS; | |
10912 | if (from == dregs) | |
10913 | return mips_move_from_gpr_cost (mode, to); | |
10914 | if (to == dregs) | |
10915 | return mips_move_to_gpr_cost (mode, from); | |
10916 | ||
10917 | /* Handles cases that require a GPR temporary. */ | |
10918 | cost1 = mips_move_to_gpr_cost (mode, from); | |
10919 | if (cost1 != 0) | |
ab77a036 | 10920 | { |
aea8cb37 RS |
10921 | cost2 = mips_move_from_gpr_cost (mode, to); |
10922 | if (cost2 != 0) | |
10923 | return cost1 + cost2; | |
a318179e RS |
10924 | } |
10925 | ||
aea8cb37 | 10926 | return 0; |
9753d4e4 | 10927 | } |
ea462dd0 | 10928 | |
5c0a2e3a RS |
10929 | /* Implement TARGET_IRA_COVER_CLASSES. */ |
10930 | ||
10931 | static const enum reg_class * | |
10932 | mips_ira_cover_classes (void) | |
10933 | { | |
10934 | static const enum reg_class acc_classes[] = { | |
10935 | GR_AND_ACC_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS, | |
10936 | ST_REGS, LIM_REG_CLASSES | |
10937 | }; | |
10938 | static const enum reg_class no_acc_classes[] = { | |
10939 | GR_REGS, FP_REGS, COP0_REGS, COP2_REGS, COP3_REGS, | |
10940 | ST_REGS, LIM_REG_CLASSES | |
10941 | }; | |
10942 | ||
10943 | /* Don't allow the register allocators to use LO and HI in MIPS16 mode, | |
e08be11c RS |
10944 | which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS |
10945 | as a cover class only works well when we keep per-register costs. | |
10946 | Using it when not optimizing can cause us to think accumulators | |
10947 | have the same cost as GPRs in cases where GPRs are actually much | |
10948 | cheaper. */ | |
10949 | return TARGET_MIPS16 || !optimize ? no_acc_classes : acc_classes; | |
5c0a2e3a RS |
10950 | } |
10951 | ||
65239d20 | 10952 | /* Return the register class required for a secondary register when |
0a2aaacc | 10953 | copying between one of the registers in RCLASS and value X, which |
65239d20 RS |
10954 | has mode MODE. X is the source of the move if IN_P, otherwise it |
10955 | is the destination. Return NO_REGS if no secondary register is | |
10956 | needed. */ | |
ea462dd0 | 10957 | |
ab77a036 | 10958 | enum reg_class |
0a2aaacc | 10959 | mips_secondary_reload_class (enum reg_class rclass, |
65239d20 | 10960 | enum machine_mode mode, rtx x, bool in_p) |
ea462dd0 | 10961 | { |
ab77a036 | 10962 | int regno; |
ea462dd0 | 10963 | |
ab77a036 RS |
10964 | /* If X is a constant that cannot be loaded into $25, it must be loaded |
10965 | into some other GPR. No other register class allows a direct move. */ | |
10966 | if (mips_dangerous_for_la25_p (x)) | |
0a2aaacc | 10967 | return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS; |
c988af2b | 10968 | |
ab77a036 RS |
10969 | regno = true_regnum (x); |
10970 | if (TARGET_MIPS16) | |
10971 | { | |
10972 | /* In MIPS16 mode, every move must involve a member of M16_REGS. */ | |
0a2aaacc | 10973 | if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno)) |
ab77a036 | 10974 | return M16_REGS; |
c988af2b | 10975 | |
ab77a036 RS |
10976 | return NO_REGS; |
10977 | } | |
c988af2b | 10978 | |
ab77a036 RS |
10979 | /* Copying from accumulator registers to anywhere other than a general |
10980 | register requires a temporary general register. */ | |
0a2aaacc | 10981 | if (reg_class_subset_p (rclass, ACC_REGS)) |
ab77a036 RS |
10982 | return GP_REG_P (regno) ? NO_REGS : GR_REGS; |
10983 | if (ACC_REG_P (regno)) | |
0a2aaacc | 10984 | return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; |
c988af2b | 10985 | |
ab77a036 | 10986 | /* We can only copy a value to a condition code register from a |
65239d20 RS |
10987 | floating-point register, and even then we require a scratch |
10988 | floating-point register. We can only copy a value out of a | |
10989 | condition-code register into a general register. */ | |
0a2aaacc | 10990 | if (reg_class_subset_p (rclass, ST_REGS)) |
c988af2b | 10991 | { |
ab77a036 RS |
10992 | if (in_p) |
10993 | return FP_REGS; | |
10994 | return GP_REG_P (regno) ? NO_REGS : GR_REGS; | |
10995 | } | |
10996 | if (ST_REG_P (regno)) | |
10997 | { | |
10998 | if (!in_p) | |
10999 | return FP_REGS; | |
0a2aaacc | 11000 | return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; |
ab77a036 | 11001 | } |
c988af2b | 11002 | |
0a2aaacc | 11003 | if (reg_class_subset_p (rclass, FP_REGS)) |
ab77a036 RS |
11004 | { |
11005 | if (MEM_P (x) | |
11006 | && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8)) | |
11007 | /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use | |
11008 | pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */ | |
11009 | return NO_REGS; | |
c988af2b | 11010 | |
ab77a036 RS |
11011 | if (GP_REG_P (regno) || x == CONST0_RTX (mode)) |
11012 | /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */ | |
11013 | return NO_REGS; | |
c988af2b | 11014 | |
ab77a036 RS |
11015 | if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (x)) |
11016 | /* We can force the constant to memory and use lwc1 | |
11017 | and ldc1. As above, we will use pairs of lwc1s if | |
11018 | ldc1 is not supported. */ | |
11019 | return NO_REGS; | |
11020 | ||
11021 | if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode)) | |
11022 | /* In this case we can use mov.fmt. */ | |
11023 | return NO_REGS; | |
11024 | ||
11025 | /* Otherwise, we need to reload through an integer register. */ | |
11026 | return GR_REGS; | |
c988af2b | 11027 | } |
ab77a036 | 11028 | if (FP_REG_P (regno)) |
0a2aaacc | 11029 | return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS; |
ab77a036 RS |
11030 | |
11031 | return NO_REGS; | |
c988af2b RS |
11032 | } |
11033 | ||
65239d20 | 11034 | /* Implement TARGET_MODE_REP_EXTENDED. */ |
c988af2b | 11035 | |
ab77a036 RS |
11036 | static int |
11037 | mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep) | |
11038 | { | |
65239d20 | 11039 | /* On 64-bit targets, SImode register values are sign-extended to DImode. */ |
ab77a036 RS |
11040 | if (TARGET_64BIT && mode == SImode && mode_rep == DImode) |
11041 | return SIGN_EXTEND; | |
c988af2b | 11042 | |
ab77a036 RS |
11043 | return UNKNOWN; |
11044 | } | |
65239d20 RS |
11045 | \f |
11046 | /* Implement TARGET_VALID_POINTER_MODE. */ | |
c988af2b | 11047 | |
ab77a036 RS |
11048 | static bool |
11049 | mips_valid_pointer_mode (enum machine_mode mode) | |
11050 | { | |
65239d20 | 11051 | return mode == SImode || (TARGET_64BIT && mode == DImode); |
ab77a036 | 11052 | } |
c988af2b | 11053 | |
65239d20 | 11054 | /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */ |
c988af2b RS |
11055 | |
11056 | static bool | |
ab77a036 | 11057 | mips_vector_mode_supported_p (enum machine_mode mode) |
c988af2b | 11058 | { |
ab77a036 RS |
11059 | switch (mode) |
11060 | { | |
11061 | case V2SFmode: | |
11062 | return TARGET_PAIRED_SINGLE_FLOAT; | |
c988af2b | 11063 | |
ab77a036 RS |
11064 | case V2HImode: |
11065 | case V4QImode: | |
11066 | case V2HQmode: | |
11067 | case V2UHQmode: | |
11068 | case V2HAmode: | |
11069 | case V2UHAmode: | |
11070 | case V4QQmode: | |
11071 | case V4UQQmode: | |
11072 | return TARGET_DSP; | |
c988af2b | 11073 | |
93581857 MS |
11074 | case V2SImode: |
11075 | case V4HImode: | |
11076 | case V8QImode: | |
11077 | return TARGET_LOONGSON_VECTORS; | |
11078 | ||
ab77a036 RS |
11079 | default: |
11080 | return false; | |
11081 | } | |
11082 | } | |
c988af2b | 11083 | |
ab77a036 | 11084 | /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */ |
c988af2b | 11085 | |
ab77a036 RS |
11086 | static bool |
11087 | mips_scalar_mode_supported_p (enum machine_mode mode) | |
c988af2b | 11088 | { |
ab77a036 RS |
11089 | if (ALL_FIXED_POINT_MODE_P (mode) |
11090 | && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD) | |
11091 | return true; | |
c988af2b | 11092 | |
ab77a036 | 11093 | return default_scalar_mode_supported_p (mode); |
c988af2b | 11094 | } |
65239d20 RS |
11095 | \f |
11096 | /* Implement TARGET_INIT_LIBFUNCS. */ | |
c988af2b | 11097 | |
ab77a036 | 11098 | #include "config/gofast.h" |
33563487 | 11099 | |
ab77a036 RS |
11100 | static void |
11101 | mips_init_libfuncs (void) | |
33563487 | 11102 | { |
ab77a036 | 11103 | if (TARGET_FIX_VR4120) |
c6e6f5c1 | 11104 | { |
65239d20 RS |
11105 | /* Register the special divsi3 and modsi3 functions needed to work |
11106 | around VR4120 division errata. */ | |
ab77a036 RS |
11107 | set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3"); |
11108 | set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3"); | |
33563487 JW |
11109 | } |
11110 | ||
ab77a036 | 11111 | if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI) |
a38e0142 | 11112 | { |
65239d20 | 11113 | /* Register the MIPS16 -mhard-float stubs. */ |
ab77a036 RS |
11114 | set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3"); |
11115 | set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3"); | |
11116 | set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3"); | |
11117 | set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3"); | |
c988af2b | 11118 | |
ab77a036 RS |
11119 | set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2"); |
11120 | set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2"); | |
11121 | set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2"); | |
11122 | set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2"); | |
11123 | set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2"); | |
11124 | set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2"); | |
11125 | set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2"); | |
c988af2b | 11126 | |
ab77a036 RS |
11127 | set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi"); |
11128 | set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf"); | |
11129 | set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf"); | |
293a36eb | 11130 | |
ab77a036 RS |
11131 | if (TARGET_DOUBLE_FLOAT) |
11132 | { | |
11133 | set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3"); | |
11134 | set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3"); | |
11135 | set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3"); | |
11136 | set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3"); | |
293a36eb | 11137 | |
ab77a036 RS |
11138 | set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2"); |
11139 | set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2"); | |
11140 | set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2"); | |
11141 | set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2"); | |
11142 | set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2"); | |
11143 | set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2"); | |
11144 | set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2"); | |
293a36eb | 11145 | |
65239d20 RS |
11146 | set_conv_libfunc (sext_optab, DFmode, SFmode, |
11147 | "__mips16_extendsfdf2"); | |
11148 | set_conv_libfunc (trunc_optab, SFmode, DFmode, | |
11149 | "__mips16_truncdfsf2"); | |
11150 | set_conv_libfunc (sfix_optab, SImode, DFmode, | |
11151 | "__mips16_fix_truncdfsi"); | |
11152 | set_conv_libfunc (sfloat_optab, DFmode, SImode, | |
11153 | "__mips16_floatsidf"); | |
11154 | set_conv_libfunc (ufloat_optab, DFmode, SImode, | |
11155 | "__mips16_floatunsidf"); | |
ab77a036 | 11156 | } |
0310e537 RH |
11157 | } |
11158 | else | |
65239d20 | 11159 | /* Register the gofast functions if selected using --enable-gofast. */ |
ab77a036 | 11160 | gofast_maybe_init_libfuncs (); |
e2ff10a9 RS |
11161 | |
11162 | /* The MIPS16 ISA does not have an encoding for "sync", so we rely | |
11163 | on an external non-MIPS16 routine to implement __sync_synchronize. */ | |
11164 | if (TARGET_MIPS16) | |
11165 | synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); | |
6cdd5672 RH |
11166 | } |
11167 | ||
0c433c31 RS |
11168 | /* Build up a multi-insn sequence that loads label TARGET into $AT. */ |
11169 | ||
11170 | static void | |
11171 | mips_process_load_label (rtx target) | |
11172 | { | |
11173 | rtx base, gp, intop; | |
11174 | HOST_WIDE_INT offset; | |
11175 | ||
11176 | mips_multi_start (); | |
11177 | switch (mips_abi) | |
11178 | { | |
11179 | case ABI_N32: | |
11180 | mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0); | |
11181 | mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0); | |
11182 | break; | |
11183 | ||
11184 | case ABI_64: | |
11185 | mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0); | |
11186 | mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0); | |
11187 | break; | |
11188 | ||
11189 | default: | |
11190 | gp = pic_offset_table_rtx; | |
11191 | if (mips_cfun_has_cprestore_slot_p ()) | |
11192 | { | |
11193 | gp = gen_rtx_REG (Pmode, AT_REGNUM); | |
11194 | mips_get_cprestore_base_and_offset (&base, &offset, true); | |
11195 | if (!SMALL_OPERAND (offset)) | |
11196 | { | |
11197 | intop = GEN_INT (CONST_HIGH_PART (offset)); | |
11198 | mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0); | |
11199 | mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0); | |
11200 | ||
11201 | base = gp; | |
11202 | offset = CONST_LOW_PART (offset); | |
11203 | } | |
11204 | intop = GEN_INT (offset); | |
11205 | if (ISA_HAS_LOAD_DELAY) | |
11206 | mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0); | |
11207 | else | |
11208 | mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0); | |
11209 | } | |
11210 | if (ISA_HAS_LOAD_DELAY) | |
11211 | mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0); | |
11212 | else | |
11213 | mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0); | |
11214 | mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0); | |
11215 | break; | |
11216 | } | |
11217 | } | |
11218 | ||
11219 | /* Return the number of instructions needed to load a label into $AT. */ | |
11220 | ||
11221 | static unsigned int | |
11222 | mips_load_label_length (void) | |
11223 | { | |
11224 | if (cfun->machine->load_label_length == 0) | |
11225 | { | |
11226 | mips_process_load_label (pc_rtx); | |
11227 | cfun->machine->load_label_length = mips_multi_num_insns; | |
11228 | } | |
11229 | return cfun->machine->load_label_length; | |
11230 | } | |
11231 | ||
11232 | /* Emit an asm sequence to start a noat block and load the address | |
11233 | of a label into $1. */ | |
11234 | ||
11235 | void | |
11236 | mips_output_load_label (rtx target) | |
11237 | { | |
11238 | mips_push_asm_switch (&mips_noat); | |
11239 | if (TARGET_EXPLICIT_RELOCS) | |
11240 | { | |
11241 | mips_process_load_label (target); | |
11242 | mips_multi_write (); | |
11243 | } | |
11244 | else | |
11245 | { | |
11246 | if (Pmode == DImode) | |
11247 | output_asm_insn ("dla\t%@,%0", &target); | |
11248 | else | |
11249 | output_asm_insn ("la\t%@,%0", &target); | |
11250 | } | |
11251 | } | |
11252 | ||
ab77a036 RS |
11253 | /* Return the length of INSN. LENGTH is the initial length computed by |
11254 | attributes in the machine-description file. */ | |
97ab1175 | 11255 | |
ab77a036 RS |
11256 | int |
11257 | mips_adjust_insn_length (rtx insn, int length) | |
cff9f8d5 | 11258 | { |
0c433c31 RS |
11259 | /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length |
11260 | of a PIC long-branch sequence. Substitute the correct value. */ | |
11261 | if (length == MAX_PIC_BRANCH_LENGTH | |
11262 | && INSN_CODE (insn) >= 0 | |
11263 | && get_attr_type (insn) == TYPE_BRANCH) | |
11264 | { | |
11265 | /* Add the branch-over instruction and its delay slot, if this | |
11266 | is a conditional branch. */ | |
11267 | length = simplejump_p (insn) ? 0 : 8; | |
11268 | ||
11269 | /* Load the label into $AT and jump to it. Ignore the delay | |
11270 | slot of the jump. */ | |
11271 | length += mips_load_label_length () + 4; | |
11272 | } | |
11273 | ||
ab77a036 RS |
11274 | /* A unconditional jump has an unfilled delay slot if it is not part |
11275 | of a sequence. A conditional jump normally has a delay slot, but | |
11276 | does not on MIPS16. */ | |
11277 | if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn))) | |
11278 | length += 4; | |
6f428062 | 11279 | |
ab77a036 RS |
11280 | /* See how many nops might be needed to avoid hardware hazards. */ |
11281 | if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0) | |
11282 | switch (get_attr_hazard (insn)) | |
11283 | { | |
11284 | case HAZARD_NONE: | |
11285 | break; | |
6f428062 | 11286 | |
ab77a036 RS |
11287 | case HAZARD_DELAY: |
11288 | length += 4; | |
11289 | break; | |
6f428062 | 11290 | |
ab77a036 RS |
11291 | case HAZARD_HILO: |
11292 | length += 8; | |
11293 | break; | |
11294 | } | |
3d30741b | 11295 | |
65239d20 RS |
11296 | /* In order to make it easier to share MIPS16 and non-MIPS16 patterns, |
11297 | the .md file length attributes are 4-based for both modes. | |
11298 | Adjust the MIPS16 ones here. */ | |
ab77a036 RS |
11299 | if (TARGET_MIPS16) |
11300 | length /= 2; | |
3d30741b | 11301 | |
ab77a036 | 11302 | return length; |
cff9f8d5 AH |
11303 | } |
11304 | ||
ab77a036 | 11305 | /* Return the assembly code for INSN, which has the operands given by |
0c433c31 RS |
11306 | OPERANDS, and which branches to OPERANDS[0] if some condition is true. |
11307 | BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0] | |
ab77a036 RS |
11308 | is in range of a direct branch. BRANCH_IF_FALSE is an inverted |
11309 | version of BRANCH_IF_TRUE. */ | |
a6008bd8 | 11310 | |
ab77a036 RS |
11311 | const char * |
11312 | mips_output_conditional_branch (rtx insn, rtx *operands, | |
11313 | const char *branch_if_true, | |
11314 | const char *branch_if_false) | |
a6008bd8 | 11315 | { |
ab77a036 RS |
11316 | unsigned int length; |
11317 | rtx taken, not_taken; | |
a6008bd8 | 11318 | |
0c433c31 | 11319 | gcc_assert (LABEL_P (operands[0])); |
4cba945d | 11320 | |
ab77a036 RS |
11321 | length = get_attr_length (insn); |
11322 | if (length <= 8) | |
11323 | { | |
11324 | /* Just a simple conditional branch. */ | |
11325 | mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn)); | |
11326 | return branch_if_true; | |
11327 | } | |
a6008bd8 | 11328 | |
ab77a036 RS |
11329 | /* Generate a reversed branch around a direct jump. This fallback does |
11330 | not use branch-likely instructions. */ | |
11331 | mips_branch_likely = false; | |
11332 | not_taken = gen_label_rtx (); | |
0c433c31 | 11333 | taken = operands[0]; |
2bcb2ab3 | 11334 | |
ab77a036 | 11335 | /* Generate the reversed branch to NOT_TAKEN. */ |
0c433c31 | 11336 | operands[0] = not_taken; |
ab77a036 | 11337 | output_asm_insn (branch_if_false, operands); |
3d30741b | 11338 | |
ab77a036 RS |
11339 | /* If INSN has a delay slot, we must provide delay slots for both the |
11340 | branch to NOT_TAKEN and the conditional jump. We must also ensure | |
11341 | that INSN's delay slot is executed in the appropriate cases. */ | |
11342 | if (final_sequence) | |
a6008bd8 | 11343 | { |
ab77a036 RS |
11344 | /* This first delay slot will always be executed, so use INSN's |
11345 | delay slot if is not annulled. */ | |
11346 | if (!INSN_ANNULLED_BRANCH_P (insn)) | |
11347 | { | |
11348 | final_scan_insn (XVECEXP (final_sequence, 0, 1), | |
11349 | asm_out_file, optimize, 1, NULL); | |
11350 | INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1; | |
11351 | } | |
11352 | else | |
11353 | output_asm_insn ("nop", 0); | |
11354 | fprintf (asm_out_file, "\n"); | |
a6008bd8 | 11355 | } |
cafe096b | 11356 | |
ab77a036 | 11357 | /* Output the unconditional branch to TAKEN. */ |
0c433c31 RS |
11358 | if (TARGET_ABSOLUTE_JUMPS) |
11359 | output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken); | |
ab77a036 | 11360 | else |
b8eb88d0 | 11361 | { |
0c433c31 | 11362 | mips_output_load_label (taken); |
ab77a036 | 11363 | output_asm_insn ("jr\t%@%]%/", 0); |
b8eb88d0 ILT |
11364 | } |
11365 | ||
ab77a036 RS |
11366 | /* Now deal with its delay slot; see above. */ |
11367 | if (final_sequence) | |
8214bf98 | 11368 | { |
ab77a036 RS |
11369 | /* This delay slot will only be executed if the branch is taken. |
11370 | Use INSN's delay slot if is annulled. */ | |
11371 | if (INSN_ANNULLED_BRANCH_P (insn)) | |
11372 | { | |
11373 | final_scan_insn (XVECEXP (final_sequence, 0, 1), | |
11374 | asm_out_file, optimize, 1, NULL); | |
11375 | INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1; | |
11376 | } | |
11377 | else | |
11378 | output_asm_insn ("nop", 0); | |
11379 | fprintf (asm_out_file, "\n"); | |
2bcb2ab3 GK |
11380 | } |
11381 | ||
ab77a036 | 11382 | /* Output NOT_TAKEN. */ |
65239d20 RS |
11383 | targetm.asm_out.internal_label (asm_out_file, "L", |
11384 | CODE_LABEL_NUMBER (not_taken)); | |
ab77a036 | 11385 | return ""; |
46299de9 | 11386 | } |
d604bca3 | 11387 | |
0c433c31 | 11388 | /* Return the assembly code for INSN, which branches to OPERANDS[0] |
65239d20 | 11389 | if some ordering condition is true. The condition is given by |
0c433c31 RS |
11390 | OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of |
11391 | OPERANDS[1]. OPERANDS[2] is the comparison's first operand; | |
ab77a036 | 11392 | its second is always zero. */ |
4977bab6 | 11393 | |
ab77a036 RS |
11394 | const char * |
11395 | mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p) | |
4977bab6 | 11396 | { |
ab77a036 | 11397 | const char *branch[2]; |
62d9f2e9 | 11398 | |
0c433c31 | 11399 | /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true. |
ab77a036 | 11400 | Make BRANCH[0] branch on the inverse condition. */ |
0c433c31 | 11401 | switch (GET_CODE (operands[1])) |
118ea793 | 11402 | { |
ab77a036 RS |
11403 | /* These cases are equivalent to comparisons against zero. */ |
11404 | case LEU: | |
11405 | inverted_p = !inverted_p; | |
11406 | /* Fall through. */ | |
11407 | case GTU: | |
0c433c31 RS |
11408 | branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0"); |
11409 | branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0"); | |
ab77a036 | 11410 | break; |
118ea793 | 11411 | |
ab77a036 RS |
11412 | /* These cases are always true or always false. */ |
11413 | case LTU: | |
11414 | inverted_p = !inverted_p; | |
11415 | /* Fall through. */ | |
11416 | case GEU: | |
0c433c31 RS |
11417 | branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0"); |
11418 | branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0"); | |
ab77a036 | 11419 | break; |
118ea793 CF |
11420 | |
11421 | default: | |
0c433c31 RS |
11422 | branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0"); |
11423 | branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0"); | |
ab77a036 | 11424 | break; |
118ea793 | 11425 | } |
ab77a036 | 11426 | return mips_output_conditional_branch (insn, operands, branch[1], branch[0]); |
06a4ab70 | 11427 | } |
ab77a036 | 11428 | \f |
6f5a62e9 RS |
11429 | /* Start a block of code that needs access to the LL, SC and SYNC |
11430 | instructions. */ | |
11431 | ||
11432 | static void | |
11433 | mips_start_ll_sc_sync_block (void) | |
11434 | { | |
11435 | if (!ISA_HAS_LL_SC) | |
11436 | { | |
11437 | output_asm_insn (".set\tpush", 0); | |
11438 | output_asm_insn (".set\tmips2", 0); | |
11439 | } | |
11440 | } | |
11441 | ||
11442 | /* End a block started by mips_start_ll_sc_sync_block. */ | |
11443 | ||
11444 | static void | |
11445 | mips_end_ll_sc_sync_block (void) | |
11446 | { | |
11447 | if (!ISA_HAS_LL_SC) | |
11448 | output_asm_insn (".set\tpop", 0); | |
11449 | } | |
11450 | ||
11451 | /* Output and/or return the asm template for a sync instruction. */ | |
ee9a72e5 JK |
11452 | |
11453 | const char * | |
6f5a62e9 | 11454 | mips_output_sync (void) |
ee9a72e5 | 11455 | { |
6f5a62e9 RS |
11456 | mips_start_ll_sc_sync_block (); |
11457 | output_asm_insn ("sync", 0); | |
11458 | mips_end_ll_sc_sync_block (); | |
11459 | return ""; | |
11460 | } | |
40a4a37b | 11461 | |
6f5a62e9 RS |
11462 | /* Return the asm template associated with sync_insn1 value TYPE. |
11463 | IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */ | |
068ca03a | 11464 | |
6f5a62e9 RS |
11465 | static const char * |
11466 | mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p) | |
11467 | { | |
11468 | switch (type) | |
11469 | { | |
11470 | case SYNC_INSN1_MOVE: | |
11471 | return "move\t%0,%z2"; | |
11472 | case SYNC_INSN1_LI: | |
11473 | return "li\t%0,%2"; | |
11474 | case SYNC_INSN1_ADDU: | |
11475 | return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2"; | |
11476 | case SYNC_INSN1_ADDIU: | |
11477 | return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2"; | |
11478 | case SYNC_INSN1_SUBU: | |
11479 | return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2"; | |
11480 | case SYNC_INSN1_AND: | |
11481 | return "and\t%0,%1,%z2"; | |
11482 | case SYNC_INSN1_ANDI: | |
11483 | return "andi\t%0,%1,%2"; | |
11484 | case SYNC_INSN1_OR: | |
11485 | return "or\t%0,%1,%z2"; | |
11486 | case SYNC_INSN1_ORI: | |
11487 | return "ori\t%0,%1,%2"; | |
11488 | case SYNC_INSN1_XOR: | |
11489 | return "xor\t%0,%1,%z2"; | |
11490 | case SYNC_INSN1_XORI: | |
11491 | return "xori\t%0,%1,%2"; | |
11492 | } | |
11493 | gcc_unreachable (); | |
11494 | } | |
11495 | ||
11496 | /* Return the asm template associated with sync_insn2 value TYPE. */ | |
11497 | ||
11498 | static const char * | |
11499 | mips_sync_insn2_template (enum attr_sync_insn2 type) | |
11500 | { | |
11501 | switch (type) | |
11502 | { | |
11503 | case SYNC_INSN2_NOP: | |
11504 | gcc_unreachable (); | |
11505 | case SYNC_INSN2_AND: | |
11506 | return "and\t%0,%1,%z2"; | |
11507 | case SYNC_INSN2_XOR: | |
11508 | return "xor\t%0,%1,%z2"; | |
11509 | case SYNC_INSN2_NOT: | |
11510 | return "nor\t%0,%1,%."; | |
11511 | } | |
11512 | gcc_unreachable (); | |
11513 | } | |
11514 | ||
11515 | /* OPERANDS are the operands to a sync loop instruction and INDEX is | |
11516 | the value of the one of the sync_* attributes. Return the operand | |
11517 | referred to by the attribute, or DEFAULT_VALUE if the insn doesn't | |
11518 | have the associated attribute. */ | |
11519 | ||
11520 | static rtx | |
11521 | mips_get_sync_operand (rtx *operands, int index, rtx default_value) | |
11522 | { | |
11523 | if (index > 0) | |
11524 | default_value = operands[index - 1]; | |
11525 | return default_value; | |
11526 | } | |
11527 | ||
11528 | /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn | |
11529 | sequence for it. */ | |
11530 | ||
11531 | static void | |
11532 | mips_process_sync_loop (rtx insn, rtx *operands) | |
11533 | { | |
11534 | rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask; | |
11535 | rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3; | |
11536 | unsigned int tmp3_insn; | |
11537 | enum attr_sync_insn1 insn1; | |
11538 | enum attr_sync_insn2 insn2; | |
11539 | bool is_64bit_p; | |
11540 | ||
11541 | /* Read an operand from the sync_WHAT attribute and store it in | |
11542 | variable WHAT. DEFAULT is the default value if no attribute | |
11543 | is specified. */ | |
11544 | #define READ_OPERAND(WHAT, DEFAULT) \ | |
11545 | WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \ | |
11546 | DEFAULT) | |
11547 | ||
11548 | /* Read the memory. */ | |
11549 | READ_OPERAND (mem, 0); | |
11550 | gcc_assert (mem); | |
11551 | is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64); | |
11552 | ||
11553 | /* Read the other attributes. */ | |
11554 | at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM); | |
11555 | READ_OPERAND (oldval, at); | |
11556 | READ_OPERAND (newval, at); | |
11557 | READ_OPERAND (inclusive_mask, 0); | |
11558 | READ_OPERAND (exclusive_mask, 0); | |
11559 | READ_OPERAND (required_oldval, 0); | |
11560 | READ_OPERAND (insn1_op2, 0); | |
11561 | insn1 = get_attr_sync_insn1 (insn); | |
11562 | insn2 = get_attr_sync_insn2 (insn); | |
11563 | ||
11564 | mips_multi_start (); | |
11565 | ||
11566 | /* Output the release side of the memory barrier. */ | |
11567 | if (get_attr_sync_release_barrier (insn) == SYNC_RELEASE_BARRIER_YES) | |
916e9b31 DD |
11568 | { |
11569 | if (required_oldval == 0 && TARGET_OCTEON) | |
11570 | { | |
11571 | /* Octeon doesn't reorder reads, so a full barrier can be | |
11572 | created by using SYNCW to order writes combined with the | |
11573 | write from the following SC. When the SC successfully | |
11574 | completes, we know that all preceding writes are also | |
11575 | committed to the coherent memory system. It is possible | |
11576 | for a single SYNCW to fail, but a pair of them will never | |
11577 | fail, so we use two. */ | |
11578 | mips_multi_add_insn ("syncw", NULL); | |
11579 | mips_multi_add_insn ("syncw", NULL); | |
11580 | } | |
11581 | else | |
11582 | mips_multi_add_insn ("sync", NULL); | |
11583 | } | |
6f5a62e9 RS |
11584 | |
11585 | /* Output the branch-back label. */ | |
11586 | mips_multi_add_label ("1:"); | |
11587 | ||
11588 | /* OLDVAL = *MEM. */ | |
11589 | mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1", | |
11590 | oldval, mem, NULL); | |
11591 | ||
11592 | /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */ | |
11593 | if (required_oldval) | |
11594 | { | |
11595 | if (inclusive_mask == 0) | |
11596 | tmp1 = oldval; | |
11597 | else | |
11598 | { | |
11599 | gcc_assert (oldval != at); | |
11600 | mips_multi_add_insn ("and\t%0,%1,%2", | |
11601 | at, oldval, inclusive_mask, NULL); | |
11602 | tmp1 = at; | |
11603 | } | |
11604 | mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL); | |
11605 | } | |
11606 | ||
11607 | /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */ | |
11608 | if (exclusive_mask == 0) | |
11609 | tmp1 = const0_rtx; | |
11610 | else | |
11611 | { | |
11612 | gcc_assert (oldval != at); | |
11613 | mips_multi_add_insn ("and\t%0,%1,%z2", | |
11614 | at, oldval, exclusive_mask, NULL); | |
11615 | tmp1 = at; | |
11616 | } | |
11617 | ||
11618 | /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2). | |
11619 | ||
11620 | We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit | |
11621 | at least one instruction in that case. */ | |
11622 | if (insn1 == SYNC_INSN1_MOVE | |
11623 | && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP)) | |
11624 | tmp2 = insn1_op2; | |
11625 | else | |
068ca03a | 11626 | { |
6f5a62e9 RS |
11627 | mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p), |
11628 | newval, oldval, insn1_op2, NULL); | |
11629 | tmp2 = newval; | |
068ca03a | 11630 | } |
6f5a62e9 RS |
11631 | |
11632 | /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */ | |
11633 | if (insn2 == SYNC_INSN2_NOP) | |
11634 | tmp3 = tmp2; | |
11635 | else | |
11636 | { | |
11637 | mips_multi_add_insn (mips_sync_insn2_template (insn2), | |
11638 | newval, tmp2, inclusive_mask, NULL); | |
11639 | tmp3 = newval; | |
11640 | } | |
11641 | tmp3_insn = mips_multi_last_index (); | |
11642 | ||
11643 | /* $AT = $TMP1 | $TMP3. */ | |
11644 | if (tmp1 == const0_rtx || tmp3 == const0_rtx) | |
11645 | { | |
11646 | mips_multi_set_operand (tmp3_insn, 0, at); | |
11647 | tmp3 = at; | |
11648 | } | |
11649 | else | |
11650 | { | |
11651 | gcc_assert (tmp1 != tmp3); | |
11652 | mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL); | |
11653 | } | |
11654 | ||
11655 | /* if (!commit (*MEM = $AT)) goto 1. | |
11656 | ||
11657 | This will sometimes be a delayed branch; see the write code below | |
11658 | for details. */ | |
11659 | mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL); | |
11660 | mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL); | |
11661 | ||
11662 | /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */ | |
11663 | if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval) | |
11664 | { | |
11665 | mips_multi_copy_insn (tmp3_insn); | |
11666 | mips_multi_set_operand (mips_multi_last_index (), 0, newval); | |
11667 | } | |
11668 | else | |
11669 | mips_multi_add_insn ("nop", NULL); | |
11670 | ||
11671 | /* Output the acquire side of the memory barrier. */ | |
11672 | if (TARGET_SYNC_AFTER_SC) | |
11673 | mips_multi_add_insn ("sync", NULL); | |
11674 | ||
11675 | /* Output the exit label, if needed. */ | |
11676 | if (required_oldval) | |
11677 | mips_multi_add_label ("2:"); | |
11678 | ||
11679 | #undef READ_OPERAND | |
11680 | } | |
11681 | ||
11682 | /* Output and/or return the asm template for sync loop INSN, which has | |
11683 | the operands given by OPERANDS. */ | |
11684 | ||
11685 | const char * | |
11686 | mips_output_sync_loop (rtx insn, rtx *operands) | |
11687 | { | |
11688 | mips_process_sync_loop (insn, operands); | |
11689 | ||
11690 | /* Use branch-likely instructions to work around the LL/SC R10000 | |
11691 | errata. */ | |
11692 | mips_branch_likely = TARGET_FIX_R10000; | |
11693 | ||
11694 | mips_push_asm_switch (&mips_noreorder); | |
11695 | mips_push_asm_switch (&mips_nomacro); | |
11696 | mips_push_asm_switch (&mips_noat); | |
11697 | mips_start_ll_sc_sync_block (); | |
11698 | ||
11699 | mips_multi_write (); | |
11700 | ||
11701 | mips_end_ll_sc_sync_block (); | |
11702 | mips_pop_asm_switch (&mips_noat); | |
11703 | mips_pop_asm_switch (&mips_nomacro); | |
11704 | mips_pop_asm_switch (&mips_noreorder); | |
11705 | ||
11706 | return ""; | |
11707 | } | |
11708 | ||
11709 | /* Return the number of individual instructions in sync loop INSN, | |
11710 | which has the operands given by OPERANDS. */ | |
11711 | ||
11712 | unsigned int | |
11713 | mips_sync_loop_insns (rtx insn, rtx *operands) | |
11714 | { | |
11715 | mips_process_sync_loop (insn, operands); | |
11716 | return mips_multi_num_insns; | |
ee9a72e5 JK |
11717 | } |
11718 | \f | |
65239d20 RS |
11719 | /* Return the assembly code for DIV or DDIV instruction DIVISION, which has |
11720 | the operands given by OPERANDS. Add in a divide-by-zero check if needed. | |
9fc777ad | 11721 | |
ab77a036 RS |
11722 | When working around R4000 and R4400 errata, we need to make sure that |
11723 | the division is not immediately followed by a shift[1][2]. We also | |
11724 | need to stop the division from being put into a branch delay slot[3]. | |
11725 | The easiest way to avoid both problems is to add a nop after the | |
11726 | division. When a divide-by-zero check is needed, this nop can be | |
11727 | used to fill the branch delay slot. | |
9fc777ad | 11728 | |
ab77a036 RS |
11729 | [1] If a double-word or a variable shift executes immediately |
11730 | after starting an integer division, the shift may give an | |
11731 | incorrect result. See quotations of errata #16 and #28 from | |
11732 | "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" | |
11733 | in mips.md for details. | |
9fc777ad | 11734 | |
ab77a036 RS |
11735 | [2] A similar bug to [1] exists for all revisions of the |
11736 | R4000 and the R4400 when run in an MC configuration. | |
11737 | From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0": | |
d34053ed | 11738 | |
ab77a036 | 11739 | "19. In this following sequence: |
2bcb2ab3 | 11740 | |
ab77a036 RS |
11741 | ddiv (or ddivu or div or divu) |
11742 | dsll32 (or dsrl32, dsra32) | |
d6076cee | 11743 | |
ab77a036 RS |
11744 | if an MPT stall occurs, while the divide is slipping the cpu |
11745 | pipeline, then the following double shift would end up with an | |
11746 | incorrect result. | |
2bcb2ab3 | 11747 | |
ab77a036 RS |
11748 | Workaround: The compiler needs to avoid generating any |
11749 | sequence with divide followed by extended double shift." | |
2bcb2ab3 | 11750 | |
ab77a036 RS |
11751 | This erratum is also present in "MIPS R4400MC Errata, Processor |
11752 | Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0 | |
11753 | & 3.0" as errata #10 and #4, respectively. | |
2bcb2ab3 | 11754 | |
ab77a036 RS |
11755 | [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" |
11756 | (also valid for MIPS R4000MC processors): | |
2bcb2ab3 | 11757 | |
ab77a036 | 11758 | "52. R4000SC: This bug does not apply for the R4000PC. |
2bcb2ab3 | 11759 | |
ab77a036 | 11760 | There are two flavors of this bug: |
2bcb2ab3 | 11761 | |
ab77a036 RS |
11762 | 1) If the instruction just after divide takes an RF exception |
11763 | (tlb-refill, tlb-invalid) and gets an instruction cache | |
11764 | miss (both primary and secondary) and the line which is | |
11765 | currently in secondary cache at this index had the first | |
11766 | data word, where the bits 5..2 are set, then R4000 would | |
11767 | get a wrong result for the div. | |
a38e0142 | 11768 | |
ab77a036 RS |
11769 | ##1 |
11770 | nop | |
11771 | div r8, r9 | |
11772 | ------------------- # end-of page. -tlb-refill | |
11773 | nop | |
11774 | ##2 | |
11775 | nop | |
11776 | div r8, r9 | |
11777 | ------------------- # end-of page. -tlb-invalid | |
11778 | nop | |
a38e0142 | 11779 | |
ab77a036 RS |
11780 | 2) If the divide is in the taken branch delay slot, where the |
11781 | target takes RF exception and gets an I-cache miss for the | |
11782 | exception vector or where I-cache miss occurs for the | |
11783 | target address, under the above mentioned scenarios, the | |
11784 | div would get wrong results. | |
a38e0142 | 11785 | |
ab77a036 RS |
11786 | ##1 |
11787 | j r2 # to next page mapped or unmapped | |
11788 | div r8,r9 # this bug would be there as long | |
11789 | # as there is an ICache miss and | |
11790 | nop # the "data pattern" is present | |
2bcb2ab3 | 11791 | |
ab77a036 RS |
11792 | ##2 |
11793 | beq r0, r0, NextPage # to Next page | |
11794 | div r8,r9 | |
11795 | nop | |
a38e0142 | 11796 | |
ab77a036 RS |
11797 | This bug is present for div, divu, ddiv, and ddivu |
11798 | instructions. | |
a38e0142 | 11799 | |
ab77a036 RS |
11800 | Workaround: For item 1), OS could make sure that the next page |
11801 | after the divide instruction is also mapped. For item 2), the | |
11802 | compiler could make sure that the divide instruction is not in | |
11803 | the branch delay slot." | |
2bcb2ab3 | 11804 | |
ab77a036 RS |
11805 | These processors have PRId values of 0x00004220 and 0x00004300 for |
11806 | the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */ | |
2bcb2ab3 | 11807 | |
ab77a036 RS |
11808 | const char * |
11809 | mips_output_division (const char *division, rtx *operands) | |
2bcb2ab3 | 11810 | { |
ab77a036 | 11811 | const char *s; |
2bcb2ab3 | 11812 | |
ab77a036 RS |
11813 | s = division; |
11814 | if (TARGET_FIX_R4000 || TARGET_FIX_R4400) | |
2bcb2ab3 | 11815 | { |
ab77a036 RS |
11816 | output_asm_insn (s, operands); |
11817 | s = "nop"; | |
2bcb2ab3 | 11818 | } |
ab77a036 | 11819 | if (TARGET_CHECK_ZERO_DIV) |
3c7404d3 | 11820 | { |
ab77a036 RS |
11821 | if (TARGET_MIPS16) |
11822 | { | |
11823 | output_asm_insn (s, operands); | |
11824 | s = "bnez\t%2,1f\n\tbreak\t7\n1:"; | |
11825 | } | |
11826 | else if (GENERATE_DIVIDE_TRAPS) | |
67e67979 DU |
11827 | { |
11828 | /* Avoid long replay penalty on load miss by putting the trap before | |
11829 | the divide. */ | |
11830 | if (TUNE_74K) | |
11831 | output_asm_insn ("teq\t%2,%.,7", operands); | |
11832 | else | |
11833 | { | |
11834 | output_asm_insn (s, operands); | |
11835 | s = "teq\t%2,%.,7"; | |
11836 | } | |
11837 | } | |
ab77a036 RS |
11838 | else |
11839 | { | |
11840 | output_asm_insn ("%(bne\t%2,%.,1f", operands); | |
11841 | output_asm_insn (s, operands); | |
11842 | s = "break\t7%)\n1:"; | |
11843 | } | |
3c7404d3 | 11844 | } |
ab77a036 RS |
11845 | return s; |
11846 | } | |
11847 | \f | |
65239d20 RS |
11848 | /* Return true if IN_INSN is a multiply-add or multiply-subtract |
11849 | instruction and if OUT_INSN assigns to the accumulator operand. */ | |
2bcb2ab3 | 11850 | |
ab77a036 | 11851 | bool |
65239d20 | 11852 | mips_linked_madd_p (rtx out_insn, rtx in_insn) |
ab77a036 RS |
11853 | { |
11854 | rtx x; | |
2bcb2ab3 | 11855 | |
65239d20 | 11856 | x = single_set (in_insn); |
ab77a036 RS |
11857 | if (x == 0) |
11858 | return false; | |
2bcb2ab3 | 11859 | |
ab77a036 | 11860 | x = SET_SRC (x); |
2bcb2ab3 | 11861 | |
ab77a036 RS |
11862 | if (GET_CODE (x) == PLUS |
11863 | && GET_CODE (XEXP (x, 0)) == MULT | |
65239d20 | 11864 | && reg_set_p (XEXP (x, 1), out_insn)) |
ab77a036 | 11865 | return true; |
2bcb2ab3 | 11866 | |
ab77a036 RS |
11867 | if (GET_CODE (x) == MINUS |
11868 | && GET_CODE (XEXP (x, 1)) == MULT | |
65239d20 | 11869 | && reg_set_p (XEXP (x, 0), out_insn)) |
ab77a036 | 11870 | return true; |
2bcb2ab3 | 11871 | |
ab77a036 | 11872 | return false; |
2bcb2ab3 GK |
11873 | } |
11874 | ||
65239d20 RS |
11875 | /* True if the dependency between OUT_INSN and IN_INSN is on the store |
11876 | data rather than the address. We need this because the cprestore | |
11877 | pattern is type "store", but is defined using an UNSPEC_VOLATILE, | |
11878 | which causes the default routine to abort. We just return false | |
11879 | for that case. */ | |
2bcb2ab3 | 11880 | |
65239d20 | 11881 | bool |
ab77a036 | 11882 | mips_store_data_bypass_p (rtx out_insn, rtx in_insn) |
2bcb2ab3 | 11883 | { |
ab77a036 RS |
11884 | if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE) |
11885 | return false; | |
2bcb2ab3 | 11886 | |
65239d20 | 11887 | return !store_data_bypass_p (out_insn, in_insn); |
ab77a036 RS |
11888 | } |
11889 | \f | |
58684fa0 MK |
11890 | |
11891 | /* Variables and flags used in scheduler hooks when tuning for | |
11892 | Loongson 2E/2F. */ | |
11893 | static struct | |
11894 | { | |
11895 | /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch | |
11896 | strategy. */ | |
11897 | ||
11898 | /* If true, then next ALU1/2 instruction will go to ALU1. */ | |
11899 | bool alu1_turn_p; | |
11900 | ||
11901 | /* If true, then next FALU1/2 unstruction will go to FALU1. */ | |
11902 | bool falu1_turn_p; | |
11903 | ||
11904 | /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */ | |
11905 | int alu1_core_unit_code; | |
11906 | int alu2_core_unit_code; | |
11907 | int falu1_core_unit_code; | |
11908 | int falu2_core_unit_code; | |
11909 | ||
11910 | /* True if current cycle has a multi instruction. | |
11911 | This flag is used in mips_ls2_dfa_post_advance_cycle. */ | |
11912 | bool cycle_has_multi_p; | |
11913 | ||
11914 | /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units. | |
11915 | These are used in mips_ls2_dfa_post_advance_cycle to initialize | |
11916 | DFA state. | |
11917 | E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2 | |
11918 | instruction to go ALU1. */ | |
11919 | rtx alu1_turn_enabled_insn; | |
11920 | rtx alu2_turn_enabled_insn; | |
11921 | rtx falu1_turn_enabled_insn; | |
11922 | rtx falu2_turn_enabled_insn; | |
11923 | } mips_ls2; | |
11924 | ||
ab77a036 RS |
11925 | /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output |
11926 | dependencies have no cost, except on the 20Kc where output-dependence | |
11927 | is treated like input-dependence. */ | |
2bcb2ab3 | 11928 | |
ab77a036 RS |
11929 | static int |
11930 | mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link, | |
11931 | rtx dep ATTRIBUTE_UNUSED, int cost) | |
11932 | { | |
11933 | if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT | |
11934 | && TUNE_20KC) | |
11935 | return cost; | |
11936 | if (REG_NOTE_KIND (link) != 0) | |
11937 | return 0; | |
11938 | return cost; | |
11939 | } | |
a38e0142 | 11940 | |
ab77a036 RS |
11941 | /* Return the number of instructions that can be issued per cycle. */ |
11942 | ||
11943 | static int | |
11944 | mips_issue_rate (void) | |
a38e0142 | 11945 | { |
ab77a036 | 11946 | switch (mips_tune) |
a38e0142 | 11947 | { |
ab77a036 RS |
11948 | case PROCESSOR_74KC: |
11949 | case PROCESSOR_74KF2_1: | |
11950 | case PROCESSOR_74KF1_1: | |
11951 | case PROCESSOR_74KF3_2: | |
11952 | /* The 74k is not strictly quad-issue cpu, but can be seen as one | |
11953 | by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns, | |
65239d20 RS |
11954 | but in reality only a maximum of 3 insns can be issued as |
11955 | floating-point loads and stores also require a slot in the | |
11956 | AGEN pipe. */ | |
7a3446ec JK |
11957 | case PROCESSOR_R10000: |
11958 | /* All R10K Processors are quad-issue (being the first MIPS | |
11959 | processors to support this feature). */ | |
11960 | return 4; | |
ab77a036 RS |
11961 | |
11962 | case PROCESSOR_20KC: | |
11963 | case PROCESSOR_R4130: | |
11964 | case PROCESSOR_R5400: | |
11965 | case PROCESSOR_R5500: | |
11966 | case PROCESSOR_R7000: | |
11967 | case PROCESSOR_R9000: | |
ce00be9e | 11968 | case PROCESSOR_OCTEON: |
ab77a036 RS |
11969 | return 2; |
11970 | ||
11971 | case PROCESSOR_SB1: | |
11972 | case PROCESSOR_SB1A: | |
11973 | /* This is actually 4, but we get better performance if we claim 3. | |
11974 | This is partly because of unwanted speculative code motion with the | |
11975 | larger number, and partly because in most common cases we can't | |
11976 | reach the theoretical max of 4. */ | |
11977 | return 3; | |
11978 | ||
58684fa0 MK |
11979 | case PROCESSOR_LOONGSON_2E: |
11980 | case PROCESSOR_LOONGSON_2F: | |
11981 | return 4; | |
11982 | ||
ab77a036 RS |
11983 | default: |
11984 | return 1; | |
a38e0142 SL |
11985 | } |
11986 | } | |
11987 | ||
58684fa0 MK |
11988 | /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */ |
11989 | ||
11990 | static void | |
11991 | mips_ls2_init_dfa_post_cycle_insn (void) | |
11992 | { | |
11993 | start_sequence (); | |
11994 | emit_insn (gen_ls2_alu1_turn_enabled_insn ()); | |
11995 | mips_ls2.alu1_turn_enabled_insn = get_insns (); | |
11996 | end_sequence (); | |
11997 | ||
11998 | start_sequence (); | |
11999 | emit_insn (gen_ls2_alu2_turn_enabled_insn ()); | |
12000 | mips_ls2.alu2_turn_enabled_insn = get_insns (); | |
12001 | end_sequence (); | |
12002 | ||
12003 | start_sequence (); | |
12004 | emit_insn (gen_ls2_falu1_turn_enabled_insn ()); | |
12005 | mips_ls2.falu1_turn_enabled_insn = get_insns (); | |
12006 | end_sequence (); | |
12007 | ||
12008 | start_sequence (); | |
12009 | emit_insn (gen_ls2_falu2_turn_enabled_insn ()); | |
12010 | mips_ls2.falu2_turn_enabled_insn = get_insns (); | |
12011 | end_sequence (); | |
12012 | ||
12013 | mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core"); | |
12014 | mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core"); | |
12015 | mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core"); | |
12016 | mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core"); | |
12017 | } | |
12018 | ||
12019 | /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook. | |
12020 | Init data used in mips_dfa_post_advance_cycle. */ | |
12021 | ||
12022 | static void | |
12023 | mips_init_dfa_post_cycle_insn (void) | |
12024 | { | |
12025 | if (TUNE_LOONGSON_2EF) | |
12026 | mips_ls2_init_dfa_post_cycle_insn (); | |
12027 | } | |
12028 | ||
12029 | /* Initialize STATE when scheduling for Loongson 2E/2F. | |
12030 | Support round-robin dispatch scheme by enabling only one of | |
12031 | ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions | |
12032 | respectively. */ | |
12033 | ||
12034 | static void | |
12035 | mips_ls2_dfa_post_advance_cycle (state_t state) | |
12036 | { | |
12037 | if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code)) | |
12038 | { | |
12039 | /* Though there are no non-pipelined ALU1 insns, | |
12040 | we can get an instruction of type 'multi' before reload. */ | |
12041 | gcc_assert (mips_ls2.cycle_has_multi_p); | |
12042 | mips_ls2.alu1_turn_p = false; | |
12043 | } | |
12044 | ||
12045 | mips_ls2.cycle_has_multi_p = false; | |
12046 | ||
12047 | if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code)) | |
12048 | /* We have a non-pipelined alu instruction in the core, | |
12049 | adjust round-robin counter. */ | |
12050 | mips_ls2.alu1_turn_p = true; | |
12051 | ||
12052 | if (mips_ls2.alu1_turn_p) | |
12053 | { | |
12054 | if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0) | |
12055 | gcc_unreachable (); | |
12056 | } | |
12057 | else | |
12058 | { | |
12059 | if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0) | |
12060 | gcc_unreachable (); | |
12061 | } | |
12062 | ||
12063 | if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code)) | |
12064 | { | |
12065 | /* There are no non-pipelined FALU1 insns. */ | |
12066 | gcc_unreachable (); | |
12067 | mips_ls2.falu1_turn_p = false; | |
12068 | } | |
12069 | ||
12070 | if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code)) | |
12071 | /* We have a non-pipelined falu instruction in the core, | |
12072 | adjust round-robin counter. */ | |
12073 | mips_ls2.falu1_turn_p = true; | |
12074 | ||
12075 | if (mips_ls2.falu1_turn_p) | |
12076 | { | |
12077 | if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0) | |
12078 | gcc_unreachable (); | |
12079 | } | |
12080 | else | |
12081 | { | |
12082 | if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0) | |
12083 | gcc_unreachable (); | |
12084 | } | |
12085 | } | |
12086 | ||
12087 | /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE. | |
12088 | This hook is being called at the start of each cycle. */ | |
12089 | ||
12090 | static void | |
12091 | mips_dfa_post_advance_cycle (void) | |
12092 | { | |
12093 | if (TUNE_LOONGSON_2EF) | |
12094 | mips_ls2_dfa_post_advance_cycle (curr_state); | |
12095 | } | |
12096 | ||
65239d20 | 12097 | /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should |
ab77a036 | 12098 | be as wide as the scheduling freedom in the DFA. */ |
2bcb2ab3 | 12099 | |
ab77a036 RS |
12100 | static int |
12101 | mips_multipass_dfa_lookahead (void) | |
12102 | { | |
12103 | /* Can schedule up to 4 of the 6 function units in any one cycle. */ | |
12104 | if (TUNE_SB1) | |
12105 | return 4; | |
2bcb2ab3 | 12106 | |
58684fa0 MK |
12107 | if (TUNE_LOONGSON_2EF) |
12108 | return 4; | |
12109 | ||
ce00be9e AN |
12110 | if (TUNE_OCTEON) |
12111 | return 2; | |
12112 | ||
ab77a036 RS |
12113 | return 0; |
12114 | } | |
12115 | \f | |
12116 | /* Remove the instruction at index LOWER from ready queue READY and | |
12117 | reinsert it in front of the instruction at index HIGHER. LOWER must | |
12118 | be <= HIGHER. */ | |
2bcb2ab3 | 12119 | |
ab77a036 RS |
12120 | static void |
12121 | mips_promote_ready (rtx *ready, int lower, int higher) | |
2bcb2ab3 | 12122 | { |
ab77a036 RS |
12123 | rtx new_head; |
12124 | int i; | |
2bcb2ab3 | 12125 | |
ab77a036 RS |
12126 | new_head = ready[lower]; |
12127 | for (i = lower; i < higher; i++) | |
12128 | ready[i] = ready[i + 1]; | |
12129 | ready[i] = new_head; | |
12130 | } | |
2bcb2ab3 | 12131 | |
ab77a036 RS |
12132 | /* If the priority of the instruction at POS2 in the ready queue READY |
12133 | is within LIMIT units of that of the instruction at POS1, swap the | |
12134 | instructions if POS2 is not already less than POS1. */ | |
2bcb2ab3 | 12135 | |
ab77a036 RS |
12136 | static void |
12137 | mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit) | |
12138 | { | |
12139 | if (pos1 < pos2 | |
12140 | && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2])) | |
12141 | { | |
12142 | rtx temp; | |
65239d20 | 12143 | |
ab77a036 RS |
12144 | temp = ready[pos1]; |
12145 | ready[pos1] = ready[pos2]; | |
12146 | ready[pos2] = temp; | |
12147 | } | |
12148 | } | |
12149 | \f | |
12150 | /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction | |
12151 | that may clobber hi or lo. */ | |
ab77a036 | 12152 | static rtx mips_macc_chains_last_hilo; |
2bcb2ab3 | 12153 | |
ab77a036 RS |
12154 | /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has |
12155 | been scheduled, updating mips_macc_chains_last_hilo appropriately. */ | |
2bcb2ab3 | 12156 | |
ab77a036 RS |
12157 | static void |
12158 | mips_macc_chains_record (rtx insn) | |
12159 | { | |
12160 | if (get_attr_may_clobber_hilo (insn)) | |
12161 | mips_macc_chains_last_hilo = insn; | |
12162 | } | |
2bcb2ab3 | 12163 | |
ab77a036 RS |
12164 | /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which |
12165 | has NREADY elements, looking for a multiply-add or multiply-subtract | |
12166 | instruction that is cumulative with mips_macc_chains_last_hilo. | |
12167 | If there is one, promote it ahead of anything else that might | |
12168 | clobber hi or lo. */ | |
2bcb2ab3 | 12169 | |
ab77a036 RS |
12170 | static void |
12171 | mips_macc_chains_reorder (rtx *ready, int nready) | |
12172 | { | |
12173 | int i, j; | |
2bcb2ab3 | 12174 | |
ab77a036 RS |
12175 | if (mips_macc_chains_last_hilo != 0) |
12176 | for (i = nready - 1; i >= 0; i--) | |
12177 | if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i])) | |
12178 | { | |
12179 | for (j = nready - 1; j > i; j--) | |
12180 | if (recog_memoized (ready[j]) >= 0 | |
12181 | && get_attr_may_clobber_hilo (ready[j])) | |
12182 | { | |
12183 | mips_promote_ready (ready, i, j); | |
12184 | break; | |
12185 | } | |
12186 | break; | |
12187 | } | |
12188 | } | |
12189 | \f | |
12190 | /* The last instruction to be scheduled. */ | |
ab77a036 | 12191 | static rtx vr4130_last_insn; |
2bcb2ab3 | 12192 | |
ab77a036 RS |
12193 | /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA |
12194 | points to an rtx that is initially an instruction. Nullify the rtx | |
12195 | if the instruction uses the value of register X. */ | |
2bcb2ab3 | 12196 | |
ab77a036 | 12197 | static void |
65239d20 RS |
12198 | vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, |
12199 | void *data) | |
ab77a036 | 12200 | { |
65239d20 RS |
12201 | rtx *insn_ptr; |
12202 | ||
12203 | insn_ptr = (rtx *) data; | |
ab77a036 RS |
12204 | if (REG_P (x) |
12205 | && *insn_ptr != 0 | |
12206 | && reg_referenced_p (x, PATTERN (*insn_ptr))) | |
12207 | *insn_ptr = 0; | |
12208 | } | |
2bcb2ab3 | 12209 | |
ab77a036 RS |
12210 | /* Return true if there is true register dependence between vr4130_last_insn |
12211 | and INSN. */ | |
2bcb2ab3 | 12212 | |
ab77a036 RS |
12213 | static bool |
12214 | vr4130_true_reg_dependence_p (rtx insn) | |
12215 | { | |
12216 | note_stores (PATTERN (vr4130_last_insn), | |
12217 | vr4130_true_reg_dependence_p_1, &insn); | |
12218 | return insn == 0; | |
12219 | } | |
2bcb2ab3 | 12220 | |
ab77a036 RS |
12221 | /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of |
12222 | the ready queue and that INSN2 is the instruction after it, return | |
12223 | true if it is worth promoting INSN2 ahead of INSN1. Look for cases | |
12224 | in which INSN1 and INSN2 can probably issue in parallel, but for | |
12225 | which (INSN2, INSN1) should be less sensitive to instruction | |
12226 | alignment than (INSN1, INSN2). See 4130.md for more details. */ | |
2bcb2ab3 | 12227 | |
ab77a036 RS |
12228 | static bool |
12229 | vr4130_swap_insns_p (rtx insn1, rtx insn2) | |
12230 | { | |
12231 | sd_iterator_def sd_it; | |
12232 | dep_t dep; | |
2bcb2ab3 | 12233 | |
ab77a036 | 12234 | /* Check for the following case: |
2bcb2ab3 | 12235 | |
ab77a036 RS |
12236 | 1) there is some other instruction X with an anti dependence on INSN1; |
12237 | 2) X has a higher priority than INSN2; and | |
12238 | 3) X is an arithmetic instruction (and thus has no unit restrictions). | |
2bcb2ab3 | 12239 | |
ab77a036 RS |
12240 | If INSN1 is the last instruction blocking X, it would better to |
12241 | choose (INSN1, X) over (INSN2, INSN1). */ | |
12242 | FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep) | |
12243 | if (DEP_TYPE (dep) == REG_DEP_ANTI | |
12244 | && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2) | |
12245 | && recog_memoized (DEP_CON (dep)) >= 0 | |
12246 | && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU) | |
12247 | return false; | |
2bcb2ab3 | 12248 | |
ab77a036 RS |
12249 | if (vr4130_last_insn != 0 |
12250 | && recog_memoized (insn1) >= 0 | |
12251 | && recog_memoized (insn2) >= 0) | |
12252 | { | |
12253 | /* See whether INSN1 and INSN2 use different execution units, | |
12254 | or if they are both ALU-type instructions. If so, they can | |
12255 | probably execute in parallel. */ | |
12256 | enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1); | |
12257 | enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2); | |
12258 | if (class1 != class2 || class1 == VR4130_CLASS_ALU) | |
2bcb2ab3 | 12259 | { |
ab77a036 RS |
12260 | /* If only one of the instructions has a dependence on |
12261 | vr4130_last_insn, prefer to schedule the other one first. */ | |
65239d20 RS |
12262 | bool dep1_p = vr4130_true_reg_dependence_p (insn1); |
12263 | bool dep2_p = vr4130_true_reg_dependence_p (insn2); | |
12264 | if (dep1_p != dep2_p) | |
12265 | return dep1_p; | |
2bcb2ab3 | 12266 | |
ab77a036 RS |
12267 | /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn |
12268 | is not an ALU-type instruction and if INSN1 uses the same | |
12269 | execution unit. (Note that if this condition holds, we already | |
12270 | know that INSN2 uses a different execution unit.) */ | |
12271 | if (class1 != VR4130_CLASS_ALU | |
12272 | && recog_memoized (vr4130_last_insn) >= 0 | |
12273 | && class1 == get_attr_vr4130_class (vr4130_last_insn)) | |
12274 | return true; | |
12275 | } | |
12276 | } | |
12277 | return false; | |
12278 | } | |
2bcb2ab3 | 12279 | |
ab77a036 RS |
12280 | /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready |
12281 | queue with at least two instructions. Swap the first two if | |
12282 | vr4130_swap_insns_p says that it could be worthwhile. */ | |
2bcb2ab3 | 12283 | |
ab77a036 RS |
12284 | static void |
12285 | vr4130_reorder (rtx *ready, int nready) | |
12286 | { | |
12287 | if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2])) | |
12288 | mips_promote_ready (ready, nready - 2, nready - 1); | |
12289 | } | |
12290 | \f | |
12291 | /* Record whether last 74k AGEN instruction was a load or store. */ | |
ab77a036 | 12292 | static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN; |
2bcb2ab3 | 12293 | |
ab77a036 RS |
12294 | /* Initialize mips_last_74k_agen_insn from INSN. A null argument |
12295 | resets to TYPE_UNKNOWN state. */ | |
2bcb2ab3 | 12296 | |
ab77a036 RS |
12297 | static void |
12298 | mips_74k_agen_init (rtx insn) | |
12299 | { | |
006b29ab | 12300 | if (!insn || CALL_P (insn) || JUMP_P (insn)) |
ab77a036 | 12301 | mips_last_74k_agen_insn = TYPE_UNKNOWN; |
65239d20 | 12302 | else |
ab77a036 RS |
12303 | { |
12304 | enum attr_type type = get_attr_type (insn); | |
12305 | if (type == TYPE_LOAD || type == TYPE_STORE) | |
12306 | mips_last_74k_agen_insn = type; | |
12307 | } | |
12308 | } | |
2bcb2ab3 | 12309 | |
ab77a036 RS |
12310 | /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple |
12311 | loads to be grouped together, and multiple stores to be grouped | |
12312 | together. Swap things around in the ready queue to make this happen. */ | |
30244df3 | 12313 | |
ab77a036 RS |
12314 | static void |
12315 | mips_74k_agen_reorder (rtx *ready, int nready) | |
12316 | { | |
12317 | int i; | |
12318 | int store_pos, load_pos; | |
30244df3 | 12319 | |
ab77a036 RS |
12320 | store_pos = -1; |
12321 | load_pos = -1; | |
2bcb2ab3 | 12322 | |
ab77a036 RS |
12323 | for (i = nready - 1; i >= 0; i--) |
12324 | { | |
12325 | rtx insn = ready[i]; | |
12326 | if (USEFUL_INSN_P (insn)) | |
12327 | switch (get_attr_type (insn)) | |
12328 | { | |
12329 | case TYPE_STORE: | |
12330 | if (store_pos == -1) | |
12331 | store_pos = i; | |
12332 | break; | |
2bcb2ab3 | 12333 | |
ab77a036 RS |
12334 | case TYPE_LOAD: |
12335 | if (load_pos == -1) | |
12336 | load_pos = i; | |
12337 | break; | |
2bcb2ab3 | 12338 | |
ab77a036 RS |
12339 | default: |
12340 | break; | |
12341 | } | |
12342 | } | |
2bcb2ab3 | 12343 | |
ab77a036 RS |
12344 | if (load_pos == -1 || store_pos == -1) |
12345 | return; | |
2bcb2ab3 | 12346 | |
ab77a036 | 12347 | switch (mips_last_74k_agen_insn) |
76cbf5bf | 12348 | { |
ab77a036 RS |
12349 | case TYPE_UNKNOWN: |
12350 | /* Prefer to schedule loads since they have a higher latency. */ | |
12351 | case TYPE_LOAD: | |
12352 | /* Swap loads to the front of the queue. */ | |
12353 | mips_maybe_swap_ready (ready, load_pos, store_pos, 4); | |
12354 | break; | |
12355 | case TYPE_STORE: | |
12356 | /* Swap stores to the front of the queue. */ | |
12357 | mips_maybe_swap_ready (ready, store_pos, load_pos, 4); | |
12358 | break; | |
12359 | default: | |
12360 | break; | |
76cbf5bf | 12361 | } |
ab77a036 RS |
12362 | } |
12363 | \f | |
12364 | /* Implement TARGET_SCHED_INIT. */ | |
76cbf5bf | 12365 | |
ab77a036 RS |
12366 | static void |
12367 | mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12368 | int max_ready ATTRIBUTE_UNUSED) | |
12369 | { | |
12370 | mips_macc_chains_last_hilo = 0; | |
12371 | vr4130_last_insn = 0; | |
12372 | mips_74k_agen_init (NULL_RTX); | |
58684fa0 MK |
12373 | |
12374 | /* When scheduling for Loongson2, branch instructions go to ALU1, | |
12375 | therefore basic block is most likely to start with round-robin counter | |
12376 | pointed to ALU2. */ | |
12377 | mips_ls2.alu1_turn_p = false; | |
12378 | mips_ls2.falu1_turn_p = true; | |
2bcb2ab3 GK |
12379 | } |
12380 | ||
65239d20 | 12381 | /* Implement TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */ |
76cbf5bf | 12382 | |
ab77a036 RS |
12383 | static int |
12384 | mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12385 | rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED) | |
76cbf5bf | 12386 | { |
ab77a036 RS |
12387 | if (!reload_completed |
12388 | && TUNE_MACC_CHAINS | |
12389 | && *nreadyp > 0) | |
12390 | mips_macc_chains_reorder (ready, *nreadyp); | |
65239d20 | 12391 | |
ab77a036 RS |
12392 | if (reload_completed |
12393 | && TUNE_MIPS4130 | |
12394 | && !TARGET_VR4130_ALIGN | |
12395 | && *nreadyp > 1) | |
12396 | vr4130_reorder (ready, *nreadyp); | |
65239d20 | 12397 | |
ab77a036 RS |
12398 | if (TUNE_74K) |
12399 | mips_74k_agen_reorder (ready, *nreadyp); | |
65239d20 | 12400 | |
ab77a036 RS |
12401 | return mips_issue_rate (); |
12402 | } | |
76cbf5bf | 12403 | |
58684fa0 MK |
12404 | /* Update round-robin counters for ALU1/2 and FALU1/2. */ |
12405 | ||
12406 | static void | |
12407 | mips_ls2_variable_issue (rtx insn) | |
12408 | { | |
12409 | if (mips_ls2.alu1_turn_p) | |
12410 | { | |
12411 | if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code)) | |
12412 | mips_ls2.alu1_turn_p = false; | |
12413 | } | |
12414 | else | |
12415 | { | |
12416 | if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code)) | |
12417 | mips_ls2.alu1_turn_p = true; | |
12418 | } | |
12419 | ||
12420 | if (mips_ls2.falu1_turn_p) | |
12421 | { | |
12422 | if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code)) | |
12423 | mips_ls2.falu1_turn_p = false; | |
12424 | } | |
12425 | else | |
12426 | { | |
12427 | if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code)) | |
12428 | mips_ls2.falu1_turn_p = true; | |
12429 | } | |
12430 | ||
12431 | if (recog_memoized (insn) >= 0) | |
12432 | mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI); | |
12433 | } | |
12434 | ||
ab77a036 | 12435 | /* Implement TARGET_SCHED_VARIABLE_ISSUE. */ |
76cbf5bf | 12436 | |
ab77a036 RS |
12437 | static int |
12438 | mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
12439 | rtx insn, int more) | |
12440 | { | |
65239d20 RS |
12441 | /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */ |
12442 | if (USEFUL_INSN_P (insn)) | |
f2531eb6 | 12443 | { |
0c433c31 RS |
12444 | if (get_attr_type (insn) != TYPE_GHOST) |
12445 | more--; | |
ab77a036 RS |
12446 | if (!reload_completed && TUNE_MACC_CHAINS) |
12447 | mips_macc_chains_record (insn); | |
12448 | vr4130_last_insn = insn; | |
65239d20 RS |
12449 | if (TUNE_74K) |
12450 | mips_74k_agen_init (insn); | |
58684fa0 MK |
12451 | else if (TUNE_LOONGSON_2EF) |
12452 | mips_ls2_variable_issue (insn); | |
76cbf5bf | 12453 | } |
58684fa0 MK |
12454 | |
12455 | /* Instructions of type 'multi' should all be split before | |
12456 | the second scheduling pass. */ | |
12457 | gcc_assert (!reload_completed | |
12458 | || recog_memoized (insn) < 0 | |
12459 | || get_attr_type (insn) != TYPE_MULTI); | |
12460 | ||
ab77a036 | 12461 | return more; |
76cbf5bf | 12462 | } |
ab77a036 RS |
12463 | \f |
12464 | /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY), | |
65239d20 | 12465 | return the first operand of the associated PREF or PREFX insn. */ |
76cbf5bf | 12466 | |
ab77a036 RS |
12467 | rtx |
12468 | mips_prefetch_cookie (rtx write, rtx locality) | |
12469 | { | |
12470 | /* store_streamed / load_streamed. */ | |
12471 | if (INTVAL (locality) <= 0) | |
12472 | return GEN_INT (INTVAL (write) + 4); | |
76cbf5bf | 12473 | |
ab77a036 RS |
12474 | /* store / load. */ |
12475 | if (INTVAL (locality) <= 2) | |
12476 | return write; | |
2bcb2ab3 | 12477 | |
ab77a036 RS |
12478 | /* store_retained / load_retained. */ |
12479 | return GEN_INT (INTVAL (write) + 6); | |
12480 | } | |
12481 | \f | |
fd0eb897 RS |
12482 | /* Flags that indicate when a built-in function is available. |
12483 | ||
12484 | BUILTIN_AVAIL_NON_MIPS16 | |
12485 | The function is available on the current target, but only | |
12486 | in non-MIPS16 mode. */ | |
12487 | #define BUILTIN_AVAIL_NON_MIPS16 1 | |
12488 | ||
12489 | /* Declare an availability predicate for built-in functions that | |
12490 | require non-MIPS16 mode and also require COND to be true. | |
12491 | NAME is the main part of the predicate's name. */ | |
12492 | #define AVAIL_NON_MIPS16(NAME, COND) \ | |
12493 | static unsigned int \ | |
12494 | mips_builtin_avail_##NAME (void) \ | |
12495 | { \ | |
12496 | return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \ | |
12497 | } | |
12498 | ||
65239d20 RS |
12499 | /* This structure describes a single built-in function. */ |
12500 | struct mips_builtin_description { | |
ab77a036 RS |
12501 | /* The code of the main .md file instruction. See mips_builtin_type |
12502 | for more information. */ | |
12503 | enum insn_code icode; | |
2bcb2ab3 | 12504 | |
ab77a036 RS |
12505 | /* The floating-point comparison code to use with ICODE, if any. */ |
12506 | enum mips_fp_condition cond; | |
2bcb2ab3 | 12507 | |
65239d20 | 12508 | /* The name of the built-in function. */ |
ab77a036 | 12509 | const char *name; |
2bcb2ab3 | 12510 | |
ab77a036 RS |
12511 | /* Specifies how the function should be expanded. */ |
12512 | enum mips_builtin_type builtin_type; | |
2bcb2ab3 | 12513 | |
ab77a036 RS |
12514 | /* The function's prototype. */ |
12515 | enum mips_function_type function_type; | |
2bcb2ab3 | 12516 | |
fd0eb897 RS |
12517 | /* Whether the function is available. */ |
12518 | unsigned int (*avail) (void); | |
ab77a036 | 12519 | }; |
76cbf5bf | 12520 | |
fd0eb897 RS |
12521 | AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT) |
12522 | AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT) | |
12523 | AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D) | |
12524 | AVAIL_NON_MIPS16 (dsp, TARGET_DSP) | |
12525 | AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2) | |
12526 | AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP) | |
12527 | AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2) | |
93581857 | 12528 | AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS) |
4d210b07 | 12529 | AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN) |
fd0eb897 RS |
12530 | |
12531 | /* Construct a mips_builtin_description from the given arguments. | |
12532 | ||
12533 | INSN is the name of the associated instruction pattern, without the | |
12534 | leading CODE_FOR_mips_. | |
12535 | ||
12536 | CODE is the floating-point condition code associated with the | |
12537 | function. It can be 'f' if the field is not applicable. | |
12538 | ||
12539 | NAME is the name of the function itself, without the leading | |
12540 | "__builtin_mips_". | |
12541 | ||
12542 | BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields. | |
12543 | ||
12544 | AVAIL is the name of the availability predicate, without the leading | |
12545 | mips_builtin_avail_. */ | |
12546 | #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \ | |
12547 | FUNCTION_TYPE, AVAIL) \ | |
12548 | { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \ | |
12549 | "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \ | |
12550 | mips_builtin_avail_ ## AVAIL } | |
12551 | ||
12552 | /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function | |
12553 | mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL | |
12554 | are as for MIPS_BUILTIN. */ | |
12555 | #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ | |
12556 | MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL) | |
206c2d7a | 12557 | |
65239d20 | 12558 | /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which |
fd0eb897 RS |
12559 | are subject to mips_builtin_avail_<AVAIL>. */ |
12560 | #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \ | |
12561 | MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \ | |
12562 | MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \ | |
12563 | MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \ | |
12564 | MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL) | |
206c2d7a | 12565 | |
ab77a036 | 12566 | /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps. |
fd0eb897 RS |
12567 | The lower and upper forms are subject to mips_builtin_avail_<AVAIL> |
12568 | while the any and all forms are subject to mips_builtin_avail_mips3d. */ | |
12569 | #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \ | |
12570 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \ | |
12571 | MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12572 | mips3d), \ | |
12573 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \ | |
12574 | MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12575 | mips3d), \ | |
12576 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \ | |
12577 | MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12578 | AVAIL), \ | |
12579 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \ | |
12580 | MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \ | |
12581 | AVAIL) | |
206c2d7a | 12582 | |
ab77a036 | 12583 | /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions |
fd0eb897 | 12584 | are subject to mips_builtin_avail_mips3d. */ |
ab77a036 | 12585 | #define CMP_4S_BUILTINS(INSN, COND) \ |
fd0eb897 RS |
12586 | MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \ |
12587 | MIPS_BUILTIN_CMP_ANY, \ | |
12588 | MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \ | |
12589 | MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \ | |
12590 | MIPS_BUILTIN_CMP_ALL, \ | |
12591 | MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d) | |
206c2d7a | 12592 | |
ab77a036 | 12593 | /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison |
fd0eb897 RS |
12594 | instruction requires mips_builtin_avail_<AVAIL>. */ |
12595 | #define MOVTF_BUILTINS(INSN, COND, AVAIL) \ | |
12596 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \ | |
12597 | MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ | |
12598 | AVAIL), \ | |
12599 | MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \ | |
12600 | MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \ | |
12601 | AVAIL) | |
2bcb2ab3 | 12602 | |
65239d20 | 12603 | /* Define all the built-in functions related to C.cond.fmt condition COND. */ |
ab77a036 | 12604 | #define CMP_BUILTINS(COND) \ |
fd0eb897 RS |
12605 | MOVTF_BUILTINS (c, COND, paired_single), \ |
12606 | MOVTF_BUILTINS (cabs, COND, mips3d), \ | |
12607 | CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \ | |
12608 | CMP_PS_BUILTINS (c, COND, paired_single), \ | |
12609 | CMP_PS_BUILTINS (cabs, COND, mips3d), \ | |
ab77a036 RS |
12610 | CMP_4S_BUILTINS (c, COND), \ |
12611 | CMP_4S_BUILTINS (cabs, COND) | |
18dbd950 | 12612 | |
fd0eb897 RS |
12613 | /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET |
12614 | function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE | |
12615 | and AVAIL are as for MIPS_BUILTIN. */ | |
12616 | #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \ | |
12617 | MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \ | |
12618 | FUNCTION_TYPE, AVAIL) | |
2bcb2ab3 | 12619 | |
fd0eb897 RS |
12620 | /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP |
12621 | branch instruction. AVAIL is as for MIPS_BUILTIN. */ | |
12622 | #define BPOSGE_BUILTIN(VALUE, AVAIL) \ | |
12623 | MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \ | |
12624 | MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL) | |
dc884a86 | 12625 | |
93581857 MS |
12626 | /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME> |
12627 | for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a | |
12628 | builtin_description field. */ | |
12629 | #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \ | |
81f40b79 ILT |
12630 | { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \ |
12631 | "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \ | |
12632 | FUNCTION_TYPE, mips_builtin_avail_loongson } | |
93581857 MS |
12633 | |
12634 | /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN> | |
12635 | for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a | |
12636 | builtin_description field. */ | |
12637 | #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \ | |
12638 | LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE) | |
12639 | ||
12640 | /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name. | |
12641 | We use functions of this form when the same insn can be usefully applied | |
12642 | to more than one datatype. */ | |
12643 | #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \ | |
12644 | LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE) | |
12645 | ||
ab77a036 | 12646 | #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2 |
ab77a036 RS |
12647 | #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3 |
12648 | #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3 | |
12649 | #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3 | |
12650 | #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3 | |
12651 | #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3 | |
dc884a86 | 12652 | |
93581857 MS |
12653 | #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si |
12654 | #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi | |
12655 | #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi | |
12656 | #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3 | |
12657 | #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3 | |
12658 | #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3 | |
12659 | #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3 | |
12660 | #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3 | |
12661 | #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3 | |
12662 | #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3 | |
12663 | #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3 | |
12664 | #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3 | |
12665 | #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3 | |
12666 | #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3 | |
12667 | #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart | |
12668 | #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart | |
93581857 MS |
12669 | #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3 |
12670 | #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3 | |
12671 | #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3 | |
12672 | #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3 | |
12673 | #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3 | |
12674 | #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3 | |
12675 | #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3 | |
12676 | #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi | |
12677 | #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi | |
12678 | #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si | |
12679 | #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi | |
12680 | #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi | |
12681 | #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si | |
12682 | ||
fd0eb897 RS |
12683 | static const struct mips_builtin_description mips_builtins[] = { |
12684 | DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
12685 | DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
12686 | DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
12687 | DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single), | |
12688 | DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single), | |
12689 | DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single), | |
12690 | DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single), | |
12691 | DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single), | |
12692 | ||
12693 | DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single), | |
12694 | DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
12695 | DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
12696 | DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
12697 | DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
12698 | ||
12699 | DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d), | |
12700 | DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d), | |
12701 | DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
12702 | DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d), | |
12703 | DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d), | |
12704 | DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
12705 | ||
12706 | DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d), | |
12707 | DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d), | |
12708 | DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d), | |
12709 | DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d), | |
12710 | DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d), | |
12711 | DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d), | |
12712 | ||
12713 | MIPS_FP_CONDITIONS (CMP_BUILTINS), | |
12714 | ||
12715 | /* Built-in functions for the SB-1 processor. */ | |
12716 | DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single), | |
12717 | ||
12718 | /* Built-in functions for the DSP ASE (32-bit and 64-bit). */ | |
12719 | DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12720 | DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12721 | DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
12722 | DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
12723 | DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
12724 | DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12725 | DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12726 | DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
12727 | DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
12728 | DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
12729 | DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp), | |
12730 | DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp), | |
12731 | DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp), | |
12732 | DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp), | |
12733 | DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp), | |
12734 | DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp), | |
12735 | DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), | |
12736 | DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), | |
12737 | DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp), | |
12738 | DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp), | |
12739 | DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp), | |
12740 | DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp), | |
12741 | DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12742 | DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12743 | DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12744 | DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12745 | DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12746 | DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12747 | DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12748 | DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp), | |
12749 | DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), | |
12750 | DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
12751 | DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
12752 | DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
12753 | DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp), | |
12754 | DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
12755 | DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp), | |
12756 | DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp), | |
12757 | DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), | |
12758 | DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp), | |
12759 | DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12760 | DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp), | |
12761 | DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp), | |
12762 | DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp), | |
12763 | DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp), | |
12764 | DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp), | |
12765 | DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp), | |
12766 | DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
12767 | DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
12768 | DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp), | |
12769 | DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
12770 | DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
12771 | DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp), | |
12772 | DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
12773 | DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
12774 | DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp), | |
12775 | DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp), | |
12776 | DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12777 | DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp), | |
12778 | DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp), | |
12779 | DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp), | |
12780 | DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
12781 | DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
12782 | DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp), | |
12783 | BPOSGE_BUILTIN (32, dsp), | |
12784 | ||
12785 | /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */ | |
12786 | DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2), | |
12787 | DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12788 | DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12789 | DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
12790 | DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
12791 | DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
12792 | DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
12793 | DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
12794 | DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
12795 | DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2), | |
12796 | DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12797 | DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12798 | DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12799 | DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12800 | DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12801 | DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2), | |
12802 | DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), | |
12803 | DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2), | |
12804 | DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2), | |
12805 | DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), | |
12806 | DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2), | |
12807 | DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2), | |
12808 | DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12809 | DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12810 | DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
12811 | DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2), | |
12812 | DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12813 | DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12814 | DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12815 | DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12816 | DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12817 | DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2), | |
12818 | DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12819 | DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2), | |
12820 | ||
12821 | /* Built-in functions for the DSP ASE (32-bit only). */ | |
12822 | DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
12823 | DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
12824 | DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
12825 | DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32), | |
12826 | DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12827 | DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12828 | DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12829 | DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), | |
12830 | DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32), | |
12831 | DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12832 | DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12833 | DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12834 | DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32), | |
12835 | DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12836 | DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12837 | DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12838 | DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12839 | DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12840 | DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32), | |
12841 | DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32), | |
12842 | DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32), | |
12843 | ||
12844 | /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */ | |
12845 | DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
12846 | DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
12847 | DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32), | |
12848 | DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32), | |
12849 | DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dspr2_32), | |
12850 | DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dspr2_32), | |
12851 | DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
12852 | DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dspr2_32), | |
12853 | DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dspr2_32), | |
12854 | DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
12855 | DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
12856 | DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
12857 | DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
12858 | DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), | |
93581857 MS |
12859 | DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32), |
12860 | ||
12861 | /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */ | |
12862 | LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI), | |
12863 | LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI), | |
12864 | LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI), | |
12865 | LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12866 | LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12867 | LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12868 | LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12869 | LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12870 | LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12871 | LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI), | |
12872 | LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI), | |
12873 | LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12874 | LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12875 | LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12876 | LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12877 | LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI), | |
12878 | LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12879 | LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12880 | LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12881 | LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI), | |
12882 | LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12883 | LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12884 | LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12885 | LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12886 | LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12887 | LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12888 | LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12889 | LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12890 | LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12891 | LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12892 | LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12893 | LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12894 | LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12895 | LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12896 | LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12897 | LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12898 | LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12899 | LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI), | |
12900 | LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI), | |
12901 | LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12902 | LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12903 | LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12904 | LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12905 | LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12906 | LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12907 | LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12908 | LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12909 | LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI), | |
12910 | LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12911 | LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12912 | LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12913 | LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12914 | LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI), | |
12915 | LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI), | |
12916 | LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12917 | LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12918 | LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12919 | LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI), | |
12920 | LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12921 | LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI), | |
12922 | LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI), | |
12923 | LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI), | |
12924 | LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI), | |
12925 | LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), | |
12926 | LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
12927 | LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
12928 | LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
12929 | LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), | |
12930 | LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
12931 | LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
12932 | LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
12933 | LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI), | |
12934 | LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI), | |
12935 | LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI), | |
12936 | LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI), | |
12937 | LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12938 | LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12939 | LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12940 | LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12941 | LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12942 | LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12943 | LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI), | |
12944 | LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI), | |
12945 | LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12946 | LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12947 | LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12948 | LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12949 | LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12950 | LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12951 | LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12952 | LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12953 | LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
12954 | LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI), | |
12955 | LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI), | |
12956 | LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI), | |
12957 | LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI), | |
12958 | LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI), | |
12959 | LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI), | |
4d210b07 RS |
12960 | LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI), |
12961 | ||
12962 | /* Sundry other built-in functions. */ | |
12963 | DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache) | |
ab77a036 | 12964 | }; |
dc884a86 | 12965 | |
41030557 RS |
12966 | /* MODE is a vector mode whose elements have type TYPE. Return the type |
12967 | of the vector itself. */ | |
dc884a86 | 12968 | |
41030557 RS |
12969 | static tree |
12970 | mips_builtin_vector_type (tree type, enum machine_mode mode) | |
dc884a86 | 12971 | { |
93581857 MS |
12972 | static tree types[2 * (int) MAX_MACHINE_MODE]; |
12973 | int mode_index; | |
dc884a86 | 12974 | |
93581857 MS |
12975 | mode_index = (int) mode; |
12976 | ||
12977 | if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type)) | |
12978 | mode_index += MAX_MACHINE_MODE; | |
12979 | ||
12980 | if (types[mode_index] == NULL_TREE) | |
12981 | types[mode_index] = build_vector_type_for_mode (type, mode); | |
12982 | return types[mode_index]; | |
41030557 | 12983 | } |
dc884a86 | 12984 | |
4d210b07 RS |
12985 | /* Return a type for 'const volatile void *'. */ |
12986 | ||
12987 | static tree | |
12988 | mips_build_cvpointer_type (void) | |
12989 | { | |
12990 | static tree cache; | |
12991 | ||
12992 | if (cache == NULL_TREE) | |
12993 | cache = build_pointer_type (build_qualified_type | |
12994 | (void_type_node, | |
12995 | TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE)); | |
12996 | return cache; | |
12997 | } | |
12998 | ||
41030557 RS |
12999 | /* Source-level argument types. */ |
13000 | #define MIPS_ATYPE_VOID void_type_node | |
13001 | #define MIPS_ATYPE_INT integer_type_node | |
13002 | #define MIPS_ATYPE_POINTER ptr_type_node | |
4d210b07 | 13003 | #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type () |
dc884a86 | 13004 | |
41030557 | 13005 | /* Standard mode-based argument types. */ |
93581857 | 13006 | #define MIPS_ATYPE_UQI unsigned_intQI_type_node |
41030557 RS |
13007 | #define MIPS_ATYPE_SI intSI_type_node |
13008 | #define MIPS_ATYPE_USI unsigned_intSI_type_node | |
13009 | #define MIPS_ATYPE_DI intDI_type_node | |
93581857 | 13010 | #define MIPS_ATYPE_UDI unsigned_intDI_type_node |
41030557 RS |
13011 | #define MIPS_ATYPE_SF float_type_node |
13012 | #define MIPS_ATYPE_DF double_type_node | |
dc884a86 | 13013 | |
41030557 RS |
13014 | /* Vector argument types. */ |
13015 | #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode) | |
13016 | #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode) | |
93581857 | 13017 | #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode) |
41030557 | 13018 | #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode) |
93581857 MS |
13019 | #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode) |
13020 | #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode) | |
13021 | #define MIPS_ATYPE_UV2SI \ | |
13022 | mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode) | |
13023 | #define MIPS_ATYPE_UV4HI \ | |
13024 | mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode) | |
13025 | #define MIPS_ATYPE_UV8QI \ | |
13026 | mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode) | |
dc884a86 | 13027 | |
41030557 RS |
13028 | /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists |
13029 | their associated MIPS_ATYPEs. */ | |
13030 | #define MIPS_FTYPE_ATYPES1(A, B) \ | |
13031 | MIPS_ATYPE_##A, MIPS_ATYPE_##B | |
dc884a86 | 13032 | |
41030557 RS |
13033 | #define MIPS_FTYPE_ATYPES2(A, B, C) \ |
13034 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C | |
dc884a86 | 13035 | |
41030557 RS |
13036 | #define MIPS_FTYPE_ATYPES3(A, B, C, D) \ |
13037 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D | |
dc884a86 | 13038 | |
41030557 RS |
13039 | #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \ |
13040 | MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \ | |
13041 | MIPS_ATYPE_##E | |
dc884a86 | 13042 | |
41030557 | 13043 | /* Return the function type associated with function prototype TYPE. */ |
dc884a86 | 13044 | |
41030557 RS |
13045 | static tree |
13046 | mips_build_function_type (enum mips_function_type type) | |
13047 | { | |
13048 | static tree types[(int) MIPS_MAX_FTYPE_MAX]; | |
dc884a86 | 13049 | |
41030557 RS |
13050 | if (types[(int) type] == NULL_TREE) |
13051 | switch (type) | |
13052 | { | |
13053 | #define DEF_MIPS_FTYPE(NUM, ARGS) \ | |
13054 | case MIPS_FTYPE_NAME##NUM ARGS: \ | |
13055 | types[(int) type] \ | |
13056 | = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \ | |
13057 | NULL_TREE); \ | |
13058 | break; | |
13059 | #include "config/mips/mips-ftypes.def" | |
13060 | #undef DEF_MIPS_FTYPE | |
13061 | default: | |
13062 | gcc_unreachable (); | |
13063 | } | |
dc884a86 | 13064 | |
41030557 RS |
13065 | return types[(int) type]; |
13066 | } | |
6f2993e5 | 13067 | |
65239d20 | 13068 | /* Implement TARGET_INIT_BUILTINS. */ |
41030557 RS |
13069 | |
13070 | static void | |
13071 | mips_init_builtins (void) | |
13072 | { | |
65239d20 | 13073 | const struct mips_builtin_description *d; |
fd0eb897 | 13074 | unsigned int i; |
6f2993e5 | 13075 | |
ab77a036 RS |
13076 | /* Iterate through all of the bdesc arrays, initializing all of the |
13077 | builtin functions. */ | |
fd0eb897 | 13078 | for (i = 0; i < ARRAY_SIZE (mips_builtins); i++) |
ab77a036 | 13079 | { |
fd0eb897 RS |
13080 | d = &mips_builtins[i]; |
13081 | if (d->avail ()) | |
13082 | add_builtin_function (d->name, | |
13083 | mips_build_function_type (d->function_type), | |
13084 | i, BUILT_IN_MD, NULL, NULL); | |
ab77a036 RS |
13085 | } |
13086 | } | |
6f2993e5 | 13087 | |
65239d20 RS |
13088 | /* Take argument ARGNO from EXP's argument list and convert it into a |
13089 | form suitable for input operand OPNO of instruction ICODE. Return the | |
13090 | value. */ | |
987a3c2b | 13091 | |
ab77a036 RS |
13092 | static rtx |
13093 | mips_prepare_builtin_arg (enum insn_code icode, | |
65239d20 | 13094 | unsigned int opno, tree exp, unsigned int argno) |
ab77a036 | 13095 | { |
26b69f64 | 13096 | tree arg; |
ab77a036 RS |
13097 | rtx value; |
13098 | enum machine_mode mode; | |
6f2993e5 | 13099 | |
26b69f64 RS |
13100 | arg = CALL_EXPR_ARG (exp, argno); |
13101 | value = expand_normal (arg); | |
65239d20 RS |
13102 | mode = insn_data[icode].operand[opno].mode; |
13103 | if (!insn_data[icode].operand[opno].predicate (value, mode)) | |
ab77a036 | 13104 | { |
26b69f64 RS |
13105 | /* We need to get the mode from ARG for two reasons: |
13106 | ||
13107 | - to cope with address operands, where MODE is the mode of the | |
13108 | memory, rather than of VALUE itself. | |
13109 | ||
13110 | - to cope with special predicates like pmode_register_operand, | |
13111 | where MODE is VOIDmode. */ | |
13112 | value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value); | |
4d210b07 | 13113 | |
ab77a036 | 13114 | /* Check the predicate again. */ |
65239d20 | 13115 | if (!insn_data[icode].operand[opno].predicate (value, mode)) |
ab77a036 | 13116 | { |
65239d20 | 13117 | error ("invalid argument to built-in function"); |
ab77a036 RS |
13118 | return const0_rtx; |
13119 | } | |
13120 | } | |
0ac40e7a | 13121 | |
ab77a036 RS |
13122 | return value; |
13123 | } | |
0ac40e7a | 13124 | |
ab77a036 RS |
13125 | /* Return an rtx suitable for output operand OP of instruction ICODE. |
13126 | If TARGET is non-null, try to use it where possible. */ | |
0ac40e7a | 13127 | |
ab77a036 RS |
13128 | static rtx |
13129 | mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target) | |
13130 | { | |
13131 | enum machine_mode mode; | |
6f2993e5 | 13132 | |
ab77a036 RS |
13133 | mode = insn_data[icode].operand[op].mode; |
13134 | if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode)) | |
13135 | target = gen_reg_rtx (mode); | |
6f2993e5 | 13136 | |
ab77a036 | 13137 | return target; |
6f2993e5 RS |
13138 | } |
13139 | ||
65239d20 RS |
13140 | /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function; |
13141 | HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function | |
13142 | and ICODE is the code of the associated .md pattern. TARGET, if nonnull, | |
13143 | suggests a good place to put the result. */ | |
6f2993e5 | 13144 | |
ab77a036 RS |
13145 | static rtx |
13146 | mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp, | |
65239d20 | 13147 | bool has_target_p) |
6f2993e5 | 13148 | { |
ab77a036 | 13149 | rtx ops[MAX_RECOG_OPERANDS]; |
65239d20 | 13150 | int opno, argno; |
c15c90bb | 13151 | |
65239d20 RS |
13152 | /* Map any target to operand 0. */ |
13153 | opno = 0; | |
13154 | if (has_target_p) | |
c235ddf2 | 13155 | { |
aaeee6d6 RS |
13156 | target = mips_prepare_builtin_target (icode, opno, target); |
13157 | ops[opno] = target; | |
65239d20 | 13158 | opno++; |
c235ddf2 DD |
13159 | } |
13160 | ||
65239d20 RS |
13161 | /* Map the arguments to the other operands. The n_operands value |
13162 | for an expander includes match_dups and match_scratches as well as | |
13163 | match_operands, so n_operands is only an upper bound on the number | |
13164 | of arguments to the expander function. */ | |
13165 | gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands); | |
13166 | for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++) | |
13167 | ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno); | |
c15c90bb | 13168 | |
65239d20 | 13169 | switch (opno) |
ab77a036 RS |
13170 | { |
13171 | case 2: | |
13172 | emit_insn (GEN_FCN (icode) (ops[0], ops[1])); | |
13173 | break; | |
c15c90bb | 13174 | |
ab77a036 RS |
13175 | case 3: |
13176 | emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2])); | |
13177 | break; | |
c15c90bb | 13178 | |
ab77a036 RS |
13179 | case 4: |
13180 | emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3])); | |
13181 | break; | |
c15c90bb | 13182 | |
ab77a036 RS |
13183 | default: |
13184 | gcc_unreachable (); | |
c15c90bb | 13185 | } |
ab77a036 | 13186 | return target; |
c15c90bb | 13187 | } |
6f2993e5 | 13188 | |
65239d20 RS |
13189 | /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps |
13190 | function; TYPE says which. EXP is the CALL_EXPR that calls the | |
ab77a036 RS |
13191 | function, ICODE is the instruction that should be used to compare |
13192 | the first two arguments, and COND is the condition it should test. | |
13193 | TARGET, if nonnull, suggests a good place to put the result. */ | |
d604bca3 | 13194 | |
ab77a036 RS |
13195 | static rtx |
13196 | mips_expand_builtin_movtf (enum mips_builtin_type type, | |
13197 | enum insn_code icode, enum mips_fp_condition cond, | |
13198 | rtx target, tree exp) | |
13199 | { | |
13200 | rtx cmp_result, op0, op1; | |
d604bca3 | 13201 | |
ab77a036 RS |
13202 | cmp_result = mips_prepare_builtin_target (icode, 0, 0); |
13203 | op0 = mips_prepare_builtin_arg (icode, 1, exp, 0); | |
13204 | op1 = mips_prepare_builtin_arg (icode, 2, exp, 1); | |
13205 | emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond))); | |
d604bca3 | 13206 | |
ab77a036 RS |
13207 | icode = CODE_FOR_mips_cond_move_tf_ps; |
13208 | target = mips_prepare_builtin_target (icode, 0, target); | |
13209 | if (type == MIPS_BUILTIN_MOVT) | |
d604bca3 | 13210 | { |
ab77a036 RS |
13211 | op1 = mips_prepare_builtin_arg (icode, 2, exp, 2); |
13212 | op0 = mips_prepare_builtin_arg (icode, 1, exp, 3); | |
c1bd2d66 | 13213 | } |
ab77a036 | 13214 | else |
d604bca3 | 13215 | { |
ab77a036 RS |
13216 | op0 = mips_prepare_builtin_arg (icode, 1, exp, 2); |
13217 | op1 = mips_prepare_builtin_arg (icode, 2, exp, 3); | |
c1bd2d66 | 13218 | } |
ab77a036 RS |
13219 | emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result)); |
13220 | return target; | |
d604bca3 MH |
13221 | } |
13222 | ||
ab77a036 RS |
13223 | /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE |
13224 | into TARGET otherwise. Return TARGET. */ | |
0ff83799 | 13225 | |
ab77a036 RS |
13226 | static rtx |
13227 | mips_builtin_branch_and_move (rtx condition, rtx target, | |
13228 | rtx value_if_true, rtx value_if_false) | |
0ff83799 | 13229 | { |
ab77a036 | 13230 | rtx true_label, done_label; |
0ff83799 | 13231 | |
ab77a036 RS |
13232 | true_label = gen_label_rtx (); |
13233 | done_label = gen_label_rtx (); | |
21c9500d | 13234 | |
ab77a036 RS |
13235 | /* First assume that CONDITION is false. */ |
13236 | mips_emit_move (target, value_if_false); | |
21c9500d | 13237 | |
ab77a036 RS |
13238 | /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */ |
13239 | emit_jump_insn (gen_condjump (condition, true_label)); | |
13240 | emit_jump_insn (gen_jump (done_label)); | |
13241 | emit_barrier (); | |
21c9500d | 13242 | |
ab77a036 RS |
13243 | /* Fix TARGET if CONDITION is true. */ |
13244 | emit_label (true_label); | |
13245 | mips_emit_move (target, value_if_true); | |
0ff83799 | 13246 | |
ab77a036 RS |
13247 | emit_label (done_label); |
13248 | return target; | |
0ff83799 MM |
13249 | } |
13250 | ||
65239d20 RS |
13251 | /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is |
13252 | the CALL_EXPR that calls the function, ICODE is the code of the | |
13253 | comparison instruction, and COND is the condition it should test. | |
13254 | TARGET, if nonnull, suggests a good place to put the boolean result. */ | |
c8520e56 | 13255 | |
ab77a036 RS |
13256 | static rtx |
13257 | mips_expand_builtin_compare (enum mips_builtin_type builtin_type, | |
13258 | enum insn_code icode, enum mips_fp_condition cond, | |
13259 | rtx target, tree exp) | |
c8520e56 | 13260 | { |
65239d20 RS |
13261 | rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS]; |
13262 | int argno; | |
c8520e56 | 13263 | |
ab77a036 RS |
13264 | if (target == 0 || GET_MODE (target) != SImode) |
13265 | target = gen_reg_rtx (SImode); | |
c8520e56 | 13266 | |
65239d20 RS |
13267 | /* The instruction should have a target operand, an operand for each |
13268 | argument, and an operand for COND. */ | |
13269 | gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands); | |
13270 | ||
ab77a036 RS |
13271 | /* Prepare the operands to the comparison. */ |
13272 | cmp_result = mips_prepare_builtin_target (icode, 0, 0); | |
65239d20 RS |
13273 | for (argno = 0; argno < call_expr_nargs (exp); argno++) |
13274 | args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno); | |
ab77a036 RS |
13275 | |
13276 | switch (insn_data[icode].n_operands) | |
c8520e56 | 13277 | { |
ab77a036 | 13278 | case 4: |
65239d20 RS |
13279 | emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1], |
13280 | GEN_INT (cond))); | |
ab77a036 | 13281 | break; |
c8520e56 | 13282 | |
ab77a036 | 13283 | case 6: |
65239d20 RS |
13284 | emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1], |
13285 | args[2], args[3], GEN_INT (cond))); | |
ab77a036 | 13286 | break; |
c8520e56 | 13287 | |
ab77a036 RS |
13288 | default: |
13289 | gcc_unreachable (); | |
13290 | } | |
0ff83799 | 13291 | |
ab77a036 RS |
13292 | /* If the comparison sets more than one register, we define the result |
13293 | to be 0 if all registers are false and -1 if all registers are true. | |
13294 | The value of the complete result is indeterminate otherwise. */ | |
13295 | switch (builtin_type) | |
a8c1d5f8 | 13296 | { |
ab77a036 RS |
13297 | case MIPS_BUILTIN_CMP_ALL: |
13298 | condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx); | |
13299 | return mips_builtin_branch_and_move (condition, target, | |
13300 | const0_rtx, const1_rtx); | |
13301 | ||
13302 | case MIPS_BUILTIN_CMP_UPPER: | |
13303 | case MIPS_BUILTIN_CMP_LOWER: | |
13304 | offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER); | |
13305 | condition = gen_single_cc (cmp_result, offset); | |
13306 | return mips_builtin_branch_and_move (condition, target, | |
13307 | const1_rtx, const0_rtx); | |
13308 | ||
13309 | default: | |
13310 | condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx); | |
13311 | return mips_builtin_branch_and_move (condition, target, | |
13312 | const1_rtx, const0_rtx); | |
a8c1d5f8 | 13313 | } |
ab77a036 | 13314 | } |
0ff83799 | 13315 | |
65239d20 RS |
13316 | /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET, |
13317 | if nonnull, suggests a good place to put the boolean result. */ | |
0ff83799 | 13318 | |
ab77a036 RS |
13319 | static rtx |
13320 | mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target) | |
13321 | { | |
13322 | rtx condition, cmp_result; | |
13323 | int cmp_value; | |
0ff83799 | 13324 | |
ab77a036 RS |
13325 | if (target == 0 || GET_MODE (target) != SImode) |
13326 | target = gen_reg_rtx (SImode); | |
0ff83799 | 13327 | |
ab77a036 RS |
13328 | cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM); |
13329 | ||
13330 | if (builtin_type == MIPS_BUILTIN_BPOSGE32) | |
13331 | cmp_value = 32; | |
a8c1d5f8 | 13332 | else |
ab77a036 RS |
13333 | gcc_assert (0); |
13334 | ||
13335 | condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value)); | |
13336 | return mips_builtin_branch_and_move (condition, target, | |
13337 | const1_rtx, const0_rtx); | |
13338 | } | |
13339 | ||
65239d20 | 13340 | /* Implement TARGET_EXPAND_BUILTIN. */ |
ab77a036 RS |
13341 | |
13342 | static rtx | |
13343 | mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, | |
0767b03f | 13344 | enum machine_mode mode, int ignore) |
ab77a036 | 13345 | { |
ab77a036 | 13346 | tree fndecl; |
fd0eb897 RS |
13347 | unsigned int fcode, avail; |
13348 | const struct mips_builtin_description *d; | |
ab77a036 RS |
13349 | |
13350 | fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
13351 | fcode = DECL_FUNCTION_CODE (fndecl); | |
fd0eb897 RS |
13352 | gcc_assert (fcode < ARRAY_SIZE (mips_builtins)); |
13353 | d = &mips_builtins[fcode]; | |
13354 | avail = d->avail (); | |
13355 | gcc_assert (avail != 0); | |
ab77a036 | 13356 | if (TARGET_MIPS16) |
a8c1d5f8 | 13357 | { |
29d08eba JM |
13358 | error ("built-in function %qE not supported for MIPS16", |
13359 | DECL_NAME (fndecl)); | |
0767b03f | 13360 | return ignore ? const0_rtx : CONST0_RTX (mode); |
a8c1d5f8 | 13361 | } |
fd0eb897 | 13362 | switch (d->builtin_type) |
0ff83799 | 13363 | { |
fd0eb897 RS |
13364 | case MIPS_BUILTIN_DIRECT: |
13365 | return mips_expand_builtin_direct (d->icode, target, exp, true); | |
13366 | ||
13367 | case MIPS_BUILTIN_DIRECT_NO_TARGET: | |
13368 | return mips_expand_builtin_direct (d->icode, target, exp, false); | |
13369 | ||
13370 | case MIPS_BUILTIN_MOVT: | |
13371 | case MIPS_BUILTIN_MOVF: | |
13372 | return mips_expand_builtin_movtf (d->builtin_type, d->icode, | |
13373 | d->cond, target, exp); | |
13374 | ||
13375 | case MIPS_BUILTIN_CMP_ANY: | |
13376 | case MIPS_BUILTIN_CMP_ALL: | |
13377 | case MIPS_BUILTIN_CMP_UPPER: | |
13378 | case MIPS_BUILTIN_CMP_LOWER: | |
13379 | case MIPS_BUILTIN_CMP_SINGLE: | |
13380 | return mips_expand_builtin_compare (d->builtin_type, d->icode, | |
13381 | d->cond, target, exp); | |
13382 | ||
13383 | case MIPS_BUILTIN_BPOSGE32: | |
13384 | return mips_expand_builtin_bposge (d->builtin_type, target); | |
a8c1d5f8 | 13385 | } |
5f5fe6d9 | 13386 | gcc_unreachable (); |
0ff83799 | 13387 | } |
a27fb29b | 13388 | \f |
65239d20 | 13389 | /* An entry in the MIPS16 constant pool. VALUE is the pool constant, |
ab77a036 | 13390 | MODE is its mode, and LABEL is the CODE_LABEL associated with it. */ |
ab77a036 RS |
13391 | struct mips16_constant { |
13392 | struct mips16_constant *next; | |
13393 | rtx value; | |
13394 | rtx label; | |
13395 | enum machine_mode mode; | |
13396 | }; | |
6ba7b547 | 13397 | |
65239d20 | 13398 | /* Information about an incomplete MIPS16 constant pool. FIRST is the |
ab77a036 RS |
13399 | first constant, HIGHEST_ADDRESS is the highest address that the first |
13400 | byte of the pool can have, and INSN_ADDRESS is the current instruction | |
13401 | address. */ | |
ab77a036 RS |
13402 | struct mips16_constant_pool { |
13403 | struct mips16_constant *first; | |
13404 | int highest_address; | |
13405 | int insn_address; | |
13406 | }; | |
6ba7b547 | 13407 | |
ab77a036 RS |
13408 | /* Add constant VALUE to POOL and return its label. MODE is the |
13409 | value's mode (used for CONST_INTs, etc.). */ | |
6ba7b547 | 13410 | |
ab77a036 | 13411 | static rtx |
65239d20 RS |
13412 | mips16_add_constant (struct mips16_constant_pool *pool, |
13413 | rtx value, enum machine_mode mode) | |
ab77a036 RS |
13414 | { |
13415 | struct mips16_constant **p, *c; | |
13416 | bool first_of_size_p; | |
6ba7b547 | 13417 | |
ab77a036 RS |
13418 | /* See whether the constant is already in the pool. If so, return the |
13419 | existing label, otherwise leave P pointing to the place where the | |
13420 | constant should be added. | |
6ba7b547 | 13421 | |
ab77a036 RS |
13422 | Keep the pool sorted in increasing order of mode size so that we can |
13423 | reduce the number of alignments needed. */ | |
13424 | first_of_size_p = true; | |
13425 | for (p = &pool->first; *p != 0; p = &(*p)->next) | |
13426 | { | |
13427 | if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value)) | |
13428 | return (*p)->label; | |
13429 | if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode)) | |
13430 | break; | |
13431 | if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode)) | |
13432 | first_of_size_p = false; | |
13433 | } | |
6ba7b547 | 13434 | |
ab77a036 RS |
13435 | /* In the worst case, the constant needed by the earliest instruction |
13436 | will end up at the end of the pool. The entire pool must then be | |
13437 | accessible from that instruction. | |
6ba7b547 | 13438 | |
ab77a036 RS |
13439 | When adding the first constant, set the pool's highest address to |
13440 | the address of the first out-of-range byte. Adjust this address | |
13441 | downwards each time a new constant is added. */ | |
13442 | if (pool->first == 0) | |
65239d20 RS |
13443 | /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address |
13444 | of the instruction with the lowest two bits clear. The base PC | |
13445 | value for LDPC has the lowest three bits clear. Assume the worst | |
13446 | case here; namely that the PC-relative instruction occupies the | |
13447 | last 2 bytes in an aligned word. */ | |
ab77a036 RS |
13448 | pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000; |
13449 | pool->highest_address -= GET_MODE_SIZE (mode); | |
13450 | if (first_of_size_p) | |
13451 | /* Take into account the worst possible padding due to alignment. */ | |
13452 | pool->highest_address -= GET_MODE_SIZE (mode) - 1; | |
6ba7b547 | 13453 | |
ab77a036 | 13454 | /* Create a new entry. */ |
65239d20 | 13455 | c = XNEW (struct mips16_constant); |
ab77a036 RS |
13456 | c->value = value; |
13457 | c->mode = mode; | |
13458 | c->label = gen_label_rtx (); | |
13459 | c->next = *p; | |
13460 | *p = c; | |
6ba7b547 | 13461 | |
ab77a036 RS |
13462 | return c->label; |
13463 | } | |
6ba7b547 | 13464 | |
ab77a036 RS |
13465 | /* Output constant VALUE after instruction INSN and return the last |
13466 | instruction emitted. MODE is the mode of the constant. */ | |
6ba7b547 | 13467 | |
ab77a036 | 13468 | static rtx |
65239d20 | 13469 | mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn) |
ab77a036 | 13470 | { |
65239d20 | 13471 | if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode)) |
ab77a036 RS |
13472 | { |
13473 | rtx size = GEN_INT (GET_MODE_SIZE (mode)); | |
13474 | return emit_insn_after (gen_consttable_int (value, size), insn); | |
13475 | } | |
6ba7b547 | 13476 | |
ab77a036 RS |
13477 | if (SCALAR_FLOAT_MODE_P (mode)) |
13478 | return emit_insn_after (gen_consttable_float (value), insn); | |
6ba7b547 | 13479 | |
ab77a036 RS |
13480 | if (VECTOR_MODE_P (mode)) |
13481 | { | |
13482 | int i; | |
6ba7b547 | 13483 | |
ab77a036 | 13484 | for (i = 0; i < CONST_VECTOR_NUNITS (value); i++) |
65239d20 RS |
13485 | insn = mips16_emit_constants_1 (GET_MODE_INNER (mode), |
13486 | CONST_VECTOR_ELT (value, i), insn); | |
ab77a036 RS |
13487 | return insn; |
13488 | } | |
6ba7b547 | 13489 | |
ab77a036 RS |
13490 | gcc_unreachable (); |
13491 | } | |
6ba7b547 | 13492 | |
ab77a036 | 13493 | /* Dump out the constants in CONSTANTS after INSN. */ |
32ad6a47 | 13494 | |
ab77a036 | 13495 | static void |
65239d20 | 13496 | mips16_emit_constants (struct mips16_constant *constants, rtx insn) |
32ad6a47 | 13497 | { |
ab77a036 RS |
13498 | struct mips16_constant *c, *next; |
13499 | int align; | |
46490403 | 13500 | |
ab77a036 RS |
13501 | align = 0; |
13502 | for (c = constants; c != NULL; c = next) | |
32ad6a47 | 13503 | { |
ab77a036 RS |
13504 | /* If necessary, increase the alignment of PC. */ |
13505 | if (align < GET_MODE_SIZE (c->mode)) | |
c9e0ce37 | 13506 | { |
ab77a036 RS |
13507 | int align_log = floor_log2 (GET_MODE_SIZE (c->mode)); |
13508 | insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn); | |
c9e0ce37 | 13509 | } |
ab77a036 | 13510 | align = GET_MODE_SIZE (c->mode); |
a27fb29b | 13511 | |
ab77a036 | 13512 | insn = emit_label_after (c->label, insn); |
65239d20 | 13513 | insn = mips16_emit_constants_1 (c->mode, c->value, insn); |
d07d525a | 13514 | |
ab77a036 RS |
13515 | next = c->next; |
13516 | free (c); | |
13517 | } | |
7dac2f89 | 13518 | |
ab77a036 | 13519 | emit_barrier_after (insn); |
a27fb29b | 13520 | } |
7dac2f89 | 13521 | |
ab77a036 | 13522 | /* Return the length of instruction INSN. */ |
f41a6bf1 | 13523 | |
ab77a036 RS |
13524 | static int |
13525 | mips16_insn_length (rtx insn) | |
13526 | { | |
13527 | if (JUMP_P (insn)) | |
13528 | { | |
13529 | rtx body = PATTERN (insn); | |
13530 | if (GET_CODE (body) == ADDR_VEC) | |
13531 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0); | |
13532 | if (GET_CODE (body) == ADDR_DIFF_VEC) | |
13533 | return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1); | |
13534 | } | |
13535 | return get_attr_length (insn); | |
13536 | } | |
7dac2f89 | 13537 | |
ab77a036 RS |
13538 | /* If *X is a symbolic constant that refers to the constant pool, add |
13539 | the constant to POOL and rewrite *X to use the constant's label. */ | |
7dac2f89 | 13540 | |
ab77a036 RS |
13541 | static void |
13542 | mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x) | |
a27fb29b | 13543 | { |
ab77a036 | 13544 | rtx base, offset, label; |
7dac2f89 | 13545 | |
ab77a036 RS |
13546 | split_const (*x, &base, &offset); |
13547 | if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base)) | |
13548 | { | |
65239d20 RS |
13549 | label = mips16_add_constant (pool, get_pool_constant (base), |
13550 | get_pool_mode (base)); | |
ab77a036 RS |
13551 | base = gen_rtx_LABEL_REF (Pmode, label); |
13552 | *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE); | |
13553 | } | |
a27fb29b | 13554 | } |
7dac2f89 | 13555 | |
ab77a036 RS |
13556 | /* This structure is used to communicate with mips16_rewrite_pool_refs. |
13557 | INSN is the instruction we're rewriting and POOL points to the current | |
13558 | constant pool. */ | |
13559 | struct mips16_rewrite_pool_refs_info { | |
13560 | rtx insn; | |
13561 | struct mips16_constant_pool *pool; | |
13562 | }; | |
7dac2f89 | 13563 | |
ab77a036 RS |
13564 | /* Rewrite *X so that constant pool references refer to the constant's |
13565 | label instead. DATA points to a mips16_rewrite_pool_refs_info | |
13566 | structure. */ | |
a27fb29b | 13567 | |
ab77a036 RS |
13568 | static int |
13569 | mips16_rewrite_pool_refs (rtx *x, void *data) | |
a27fb29b | 13570 | { |
5ead67f6 KG |
13571 | struct mips16_rewrite_pool_refs_info *info = |
13572 | (struct mips16_rewrite_pool_refs_info *) data; | |
7dac2f89 | 13573 | |
ab77a036 RS |
13574 | if (force_to_mem_operand (*x, Pmode)) |
13575 | { | |
13576 | rtx mem = force_const_mem (GET_MODE (*x), *x); | |
13577 | validate_change (info->insn, x, mem, false); | |
13578 | } | |
a27fb29b | 13579 | |
ab77a036 RS |
13580 | if (MEM_P (*x)) |
13581 | { | |
13582 | mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0)); | |
13583 | return -1; | |
13584 | } | |
a27fb29b | 13585 | |
ab77a036 RS |
13586 | if (TARGET_MIPS16_TEXT_LOADS) |
13587 | mips16_rewrite_pool_constant (info->pool, x); | |
a27fb29b | 13588 | |
ab77a036 | 13589 | return GET_CODE (*x) == CONST ? -1 : 0; |
7dac2f89 | 13590 | } |
7c262518 | 13591 | |
b53da244 AN |
13592 | /* Return whether CFG is used in mips_reorg. */ |
13593 | ||
13594 | static bool | |
13595 | mips_cfg_in_reorg (void) | |
13596 | { | |
13597 | return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE | |
13598 | || TARGET_RELAX_PIC_CALLS); | |
13599 | } | |
13600 | ||
ab77a036 | 13601 | /* Build MIPS16 constant pools. */ |
a27fb29b | 13602 | |
ab77a036 RS |
13603 | static void |
13604 | mips16_lay_out_constants (void) | |
a27fb29b | 13605 | { |
ab77a036 RS |
13606 | struct mips16_constant_pool pool; |
13607 | struct mips16_rewrite_pool_refs_info info; | |
13608 | rtx insn, barrier; | |
a27fb29b | 13609 | |
ab77a036 RS |
13610 | if (!TARGET_MIPS16_PCREL_LOADS) |
13611 | return; | |
a27fb29b | 13612 | |
b53da244 AN |
13613 | if (mips_cfg_in_reorg ()) |
13614 | split_all_insns (); | |
13615 | else | |
13616 | split_all_insns_noflow (); | |
ab77a036 RS |
13617 | barrier = 0; |
13618 | memset (&pool, 0, sizeof (pool)); | |
13619 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
13620 | { | |
13621 | /* Rewrite constant pool references in INSN. */ | |
006b29ab | 13622 | if (USEFUL_INSN_P (insn)) |
ab77a036 RS |
13623 | { |
13624 | info.insn = insn; | |
13625 | info.pool = &pool; | |
13626 | for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info); | |
13627 | } | |
dfad12b5 | 13628 | |
ab77a036 | 13629 | pool.insn_address += mips16_insn_length (insn); |
0e5a4ad8 | 13630 | |
ab77a036 RS |
13631 | if (pool.first != NULL) |
13632 | { | |
13633 | /* If there are no natural barriers between the first user of | |
13634 | the pool and the highest acceptable address, we'll need to | |
13635 | create a new instruction to jump around the constant pool. | |
13636 | In the worst case, this instruction will be 4 bytes long. | |
dfad12b5 | 13637 | |
ab77a036 RS |
13638 | If it's too late to do this transformation after INSN, |
13639 | do it immediately before INSN. */ | |
13640 | if (barrier == 0 && pool.insn_address + 4 > pool.highest_address) | |
13641 | { | |
13642 | rtx label, jump; | |
54401342 | 13643 | |
ab77a036 RS |
13644 | label = gen_label_rtx (); |
13645 | ||
13646 | jump = emit_jump_insn_before (gen_jump (label), insn); | |
13647 | JUMP_LABEL (jump) = label; | |
13648 | LABEL_NUSES (label) = 1; | |
13649 | barrier = emit_barrier_after (jump); | |
13650 | ||
13651 | emit_label_after (label, barrier); | |
13652 | pool.insn_address += 4; | |
13653 | } | |
13654 | ||
13655 | /* See whether the constant pool is now out of range of the first | |
13656 | user. If so, output the constants after the previous barrier. | |
13657 | Note that any instructions between BARRIER and INSN (inclusive) | |
13658 | will use negative offsets to refer to the pool. */ | |
13659 | if (pool.insn_address > pool.highest_address) | |
13660 | { | |
65239d20 | 13661 | mips16_emit_constants (pool.first, barrier); |
ab77a036 RS |
13662 | pool.first = NULL; |
13663 | barrier = 0; | |
13664 | } | |
13665 | else if (BARRIER_P (insn)) | |
13666 | barrier = insn; | |
13667 | } | |
13668 | } | |
65239d20 | 13669 | mips16_emit_constants (pool.first, get_last_insn ()); |
0c8da560 | 13670 | } |
50d32cf6 | 13671 | \f |
4d210b07 RS |
13672 | /* Return true if it is worth r10k_simplify_address's while replacing |
13673 | an address with X. We are looking for constants, and for addresses | |
13674 | at a known offset from the incoming stack pointer. */ | |
13675 | ||
13676 | static bool | |
13677 | r10k_simplified_address_p (rtx x) | |
13678 | { | |
13679 | if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) | |
13680 | x = XEXP (x, 0); | |
13681 | return x == virtual_incoming_args_rtx || CONSTANT_P (x); | |
13682 | } | |
13683 | ||
13684 | /* X is an expression that appears in INSN. Try to use the UD chains | |
13685 | to simplify it, returning the simplified form on success and the | |
13686 | original form otherwise. Replace the incoming value of $sp with | |
13687 | virtual_incoming_args_rtx (which should never occur in X otherwise). */ | |
13688 | ||
13689 | static rtx | |
13690 | r10k_simplify_address (rtx x, rtx insn) | |
13691 | { | |
13692 | rtx newx, op0, op1, set, def_insn, note; | |
57512f53 | 13693 | df_ref use, def; |
4d210b07 RS |
13694 | struct df_link *defs; |
13695 | ||
13696 | newx = NULL_RTX; | |
13697 | if (UNARY_P (x)) | |
13698 | { | |
13699 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
13700 | if (op0 != XEXP (x, 0)) | |
13701 | newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x), | |
13702 | op0, GET_MODE (XEXP (x, 0))); | |
13703 | } | |
13704 | else if (BINARY_P (x)) | |
13705 | { | |
13706 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
13707 | op1 = r10k_simplify_address (XEXP (x, 1), insn); | |
13708 | if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1)) | |
13709 | newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1); | |
13710 | } | |
13711 | else if (GET_CODE (x) == LO_SUM) | |
13712 | { | |
13713 | /* LO_SUMs can be offset from HIGHs, if we know they won't | |
13714 | overflow. See mips_classify_address for the rationale behind | |
13715 | the lax check. */ | |
13716 | op0 = r10k_simplify_address (XEXP (x, 0), insn); | |
13717 | if (GET_CODE (op0) == HIGH) | |
13718 | newx = XEXP (x, 1); | |
13719 | } | |
13720 | else if (REG_P (x)) | |
13721 | { | |
13722 | /* Uses are recorded by regno_reg_rtx, not X itself. */ | |
13723 | use = df_find_use (insn, regno_reg_rtx[REGNO (x)]); | |
13724 | gcc_assert (use); | |
13725 | defs = DF_REF_CHAIN (use); | |
13726 | ||
13727 | /* Require a single definition. */ | |
13728 | if (defs && defs->next == NULL) | |
13729 | { | |
13730 | def = defs->ref; | |
13731 | if (DF_REF_IS_ARTIFICIAL (def)) | |
13732 | { | |
13733 | /* Replace the incoming value of $sp with | |
13734 | virtual_incoming_args_rtx. */ | |
13735 | if (x == stack_pointer_rtx | |
13736 | && DF_REF_BB (def) == ENTRY_BLOCK_PTR) | |
13737 | newx = virtual_incoming_args_rtx; | |
13738 | } | |
13739 | else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use), | |
13740 | DF_REF_BB (def))) | |
13741 | { | |
13742 | /* Make sure that DEF_INSN is a single set of REG. */ | |
13743 | def_insn = DF_REF_INSN (def); | |
13744 | if (NONJUMP_INSN_P (def_insn)) | |
13745 | { | |
13746 | set = single_set (def_insn); | |
13747 | if (set && rtx_equal_p (SET_DEST (set), x)) | |
13748 | { | |
13749 | /* Prefer to use notes, since the def-use chains | |
13750 | are often shorter. */ | |
13751 | note = find_reg_equal_equiv_note (def_insn); | |
13752 | if (note) | |
13753 | newx = XEXP (note, 0); | |
13754 | else | |
13755 | newx = SET_SRC (set); | |
13756 | newx = r10k_simplify_address (newx, def_insn); | |
13757 | } | |
13758 | } | |
13759 | } | |
13760 | } | |
13761 | } | |
13762 | if (newx && r10k_simplified_address_p (newx)) | |
13763 | return newx; | |
13764 | return x; | |
13765 | } | |
13766 | ||
13767 | /* Return true if ADDRESS is known to be an uncached address | |
13768 | on R10K systems. */ | |
13769 | ||
13770 | static bool | |
13771 | r10k_uncached_address_p (unsigned HOST_WIDE_INT address) | |
13772 | { | |
13773 | unsigned HOST_WIDE_INT upper; | |
13774 | ||
13775 | /* Check for KSEG1. */ | |
13776 | if (address + 0x60000000 < 0x20000000) | |
13777 | return true; | |
13778 | ||
13779 | /* Check for uncached XKPHYS addresses. */ | |
13780 | if (Pmode == DImode) | |
13781 | { | |
13782 | upper = (address >> 40) & 0xf9ffff; | |
13783 | if (upper == 0x900000 || upper == 0xb80000) | |
13784 | return true; | |
13785 | } | |
13786 | return false; | |
13787 | } | |
13788 | ||
13789 | /* Return true if we can prove that an access to address X in instruction | |
13790 | INSN would be safe from R10K speculation. This X is a general | |
13791 | expression; it might not be a legitimate address. */ | |
13792 | ||
13793 | static bool | |
13794 | r10k_safe_address_p (rtx x, rtx insn) | |
13795 | { | |
13796 | rtx base, offset; | |
13797 | HOST_WIDE_INT offset_val; | |
13798 | ||
13799 | x = r10k_simplify_address (x, insn); | |
13800 | ||
13801 | /* Check for references to the stack frame. It doesn't really matter | |
13802 | how much of the frame has been allocated at INSN; -mr10k-cache-barrier | |
13803 | allows us to assume that accesses to any part of the eventual frame | |
13804 | is safe from speculation at any point in the function. */ | |
13805 | mips_split_plus (x, &base, &offset_val); | |
13806 | if (base == virtual_incoming_args_rtx | |
13807 | && offset_val >= -cfun->machine->frame.total_size | |
13808 | && offset_val < cfun->machine->frame.args_size) | |
13809 | return true; | |
13810 | ||
13811 | /* Check for uncached addresses. */ | |
13812 | if (CONST_INT_P (x)) | |
13813 | return r10k_uncached_address_p (INTVAL (x)); | |
13814 | ||
13815 | /* Check for accesses to a static object. */ | |
13816 | split_const (x, &base, &offset); | |
13817 | return offset_within_block_p (base, INTVAL (offset)); | |
13818 | } | |
13819 | ||
13820 | /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is | |
13821 | an in-range access to an automatic variable, or to an object with | |
13822 | a link-time-constant address. */ | |
13823 | ||
13824 | static bool | |
13825 | r10k_safe_mem_expr_p (tree expr, rtx offset) | |
13826 | { | |
13827 | if (expr == NULL_TREE | |
13828 | || offset == NULL_RTX | |
13829 | || !CONST_INT_P (offset) | |
13830 | || INTVAL (offset) < 0 | |
13831 | || INTVAL (offset) >= int_size_in_bytes (TREE_TYPE (expr))) | |
13832 | return false; | |
13833 | ||
13834 | while (TREE_CODE (expr) == COMPONENT_REF) | |
13835 | { | |
13836 | expr = TREE_OPERAND (expr, 0); | |
13837 | if (expr == NULL_TREE) | |
13838 | return false; | |
13839 | } | |
13840 | ||
13841 | return DECL_P (expr); | |
13842 | } | |
13843 | ||
13844 | /* A for_each_rtx callback for which DATA points to the instruction | |
13845 | containing *X. Stop the search if we find a MEM that is not safe | |
13846 | from R10K speculation. */ | |
13847 | ||
13848 | static int | |
13849 | r10k_needs_protection_p_1 (rtx *loc, void *data) | |
13850 | { | |
13851 | rtx mem; | |
13852 | ||
13853 | mem = *loc; | |
13854 | if (!MEM_P (mem)) | |
13855 | return 0; | |
13856 | ||
13857 | if (r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem))) | |
13858 | return -1; | |
13859 | ||
13860 | if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data)) | |
13861 | return -1; | |
13862 | ||
13863 | return 1; | |
13864 | } | |
13865 | ||
13866 | /* A note_stores callback for which DATA points to an instruction pointer. | |
13867 | If *DATA is nonnull, make it null if it X contains a MEM that is not | |
13868 | safe from R10K speculation. */ | |
13869 | ||
13870 | static void | |
13871 | r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED, | |
13872 | void *data) | |
13873 | { | |
13874 | rtx *insn_ptr; | |
13875 | ||
13876 | insn_ptr = (rtx *) data; | |
13877 | if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr)) | |
13878 | *insn_ptr = NULL_RTX; | |
13879 | } | |
13880 | ||
13881 | /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN. | |
13882 | Return nonzero if the call is not to a declared function. */ | |
13883 | ||
13884 | static int | |
13885 | r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED) | |
13886 | { | |
13887 | rtx x; | |
13888 | ||
13889 | x = *loc; | |
13890 | if (!MEM_P (x)) | |
13891 | return 0; | |
13892 | ||
13893 | x = XEXP (x, 0); | |
13894 | if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x)) | |
13895 | return -1; | |
13896 | ||
13897 | return 1; | |
13898 | } | |
13899 | ||
13900 | /* Return true if instruction INSN needs to be protected by an R10K | |
13901 | cache barrier. */ | |
13902 | ||
13903 | static bool | |
13904 | r10k_needs_protection_p (rtx insn) | |
13905 | { | |
13906 | if (CALL_P (insn)) | |
13907 | return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL); | |
13908 | ||
13909 | if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE) | |
13910 | { | |
13911 | note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn); | |
13912 | return insn == NULL_RTX; | |
13913 | } | |
13914 | ||
13915 | return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn); | |
13916 | } | |
13917 | ||
13918 | /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every | |
13919 | edge is unconditional. */ | |
13920 | ||
13921 | static bool | |
13922 | r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs) | |
13923 | { | |
13924 | edge_iterator ei; | |
13925 | edge e; | |
13926 | ||
13927 | FOR_EACH_EDGE (e, ei, bb->preds) | |
13928 | if (!single_succ_p (e->src) | |
13929 | || !TEST_BIT (protected_bbs, e->src->index) | |
13930 | || (e->flags & EDGE_COMPLEX) != 0) | |
13931 | return false; | |
13932 | return true; | |
13933 | } | |
13934 | ||
13935 | /* Implement -mr10k-cache-barrier= for the current function. */ | |
13936 | ||
13937 | static void | |
13938 | r10k_insert_cache_barriers (void) | |
13939 | { | |
13940 | int *rev_post_order; | |
13941 | unsigned int i, n; | |
13942 | basic_block bb; | |
13943 | sbitmap protected_bbs; | |
13944 | rtx insn, end, unprotected_region; | |
13945 | ||
13946 | if (TARGET_MIPS16) | |
13947 | { | |
13948 | sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier"); | |
13949 | return; | |
13950 | } | |
13951 | ||
4d210b07 RS |
13952 | /* Calculate dominators. */ |
13953 | calculate_dominance_info (CDI_DOMINATORS); | |
13954 | ||
13955 | /* Bit X of PROTECTED_BBS is set if the last operation in basic block | |
13956 | X is protected by a cache barrier. */ | |
13957 | protected_bbs = sbitmap_alloc (last_basic_block); | |
13958 | sbitmap_zero (protected_bbs); | |
13959 | ||
13960 | /* Iterate over the basic blocks in reverse post-order. */ | |
13961 | rev_post_order = XNEWVEC (int, last_basic_block); | |
13962 | n = pre_and_rev_post_order_compute (NULL, rev_post_order, false); | |
13963 | for (i = 0; i < n; i++) | |
13964 | { | |
13965 | bb = BASIC_BLOCK (rev_post_order[i]); | |
13966 | ||
13967 | /* If this block is only reached by unconditional edges, and if the | |
13968 | source of every edge is protected, the beginning of the block is | |
13969 | also protected. */ | |
13970 | if (r10k_protected_bb_p (bb, protected_bbs)) | |
13971 | unprotected_region = NULL_RTX; | |
13972 | else | |
13973 | unprotected_region = pc_rtx; | |
13974 | end = NEXT_INSN (BB_END (bb)); | |
13975 | ||
13976 | /* UNPROTECTED_REGION is: | |
13977 | ||
13978 | - null if we are processing a protected region, | |
13979 | - pc_rtx if we are processing an unprotected region but have | |
13980 | not yet found the first instruction in it | |
13981 | - the first instruction in an unprotected region otherwise. */ | |
13982 | for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn)) | |
13983 | { | |
006b29ab | 13984 | if (unprotected_region && USEFUL_INSN_P (insn)) |
4d210b07 RS |
13985 | { |
13986 | if (recog_memoized (insn) == CODE_FOR_mips_cache) | |
13987 | /* This CACHE instruction protects the following code. */ | |
13988 | unprotected_region = NULL_RTX; | |
13989 | else | |
13990 | { | |
13991 | /* See if INSN is the first instruction in this | |
13992 | unprotected region. */ | |
13993 | if (unprotected_region == pc_rtx) | |
13994 | unprotected_region = insn; | |
13995 | ||
13996 | /* See if INSN needs to be protected. If so, | |
13997 | we must insert a cache barrier somewhere between | |
13998 | PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't | |
13999 | clear which position is better performance-wise, | |
14000 | but as a tie-breaker, we assume that it is better | |
14001 | to allow delay slots to be back-filled where | |
14002 | possible, and that it is better not to insert | |
14003 | barriers in the middle of already-scheduled code. | |
14004 | We therefore insert the barrier at the beginning | |
14005 | of the region. */ | |
14006 | if (r10k_needs_protection_p (insn)) | |
14007 | { | |
14008 | emit_insn_before (gen_r10k_cache_barrier (), | |
14009 | unprotected_region); | |
14010 | unprotected_region = NULL_RTX; | |
14011 | } | |
14012 | } | |
14013 | } | |
14014 | ||
14015 | if (CALL_P (insn)) | |
14016 | /* The called function is not required to protect the exit path. | |
14017 | The code that follows a call is therefore unprotected. */ | |
14018 | unprotected_region = pc_rtx; | |
14019 | } | |
14020 | ||
14021 | /* Record whether the end of this block is protected. */ | |
14022 | if (unprotected_region == NULL_RTX) | |
14023 | SET_BIT (protected_bbs, bb->index); | |
14024 | } | |
14025 | XDELETEVEC (rev_post_order); | |
14026 | ||
14027 | sbitmap_free (protected_bbs); | |
14028 | ||
14029 | free_dominance_info (CDI_DOMINATORS); | |
b53da244 AN |
14030 | } |
14031 | \f | |
14032 | /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX | |
951771dc JW |
14033 | otherwise. If INSN has two call rtx, then store the second one in |
14034 | SECOND_CALL. */ | |
4d210b07 | 14035 | |
b53da244 | 14036 | static rtx |
951771dc | 14037 | mips_call_expr_from_insn (rtx insn, rtx *second_call) |
b53da244 AN |
14038 | { |
14039 | rtx x; | |
951771dc | 14040 | rtx x2; |
b53da244 AN |
14041 | |
14042 | if (!CALL_P (insn)) | |
14043 | return NULL_RTX; | |
4d210b07 | 14044 | |
b53da244 AN |
14045 | x = PATTERN (insn); |
14046 | if (GET_CODE (x) == PARALLEL) | |
951771dc JW |
14047 | { |
14048 | /* Calls returning complex values have two CALL rtx. Look for the second | |
14049 | one here, and return it via the SECOND_CALL arg. */ | |
14050 | x2 = XVECEXP (x, 0, 1); | |
14051 | if (GET_CODE (x2) == SET) | |
14052 | x2 = XEXP (x2, 1); | |
14053 | if (GET_CODE (x2) == CALL) | |
14054 | *second_call = x2; | |
14055 | ||
14056 | x = XVECEXP (x, 0, 0); | |
14057 | } | |
b53da244 AN |
14058 | if (GET_CODE (x) == SET) |
14059 | x = XEXP (x, 1); | |
b53da244 | 14060 | gcc_assert (GET_CODE (x) == CALL); |
951771dc | 14061 | |
b53da244 AN |
14062 | return x; |
14063 | } | |
14064 | ||
14065 | /* REG is set in DEF. See if the definition is one of the ways we load a | |
14066 | register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If | |
14067 | it is return the symbol reference of the function, otherwise return | |
14068 | NULL_RTX. */ | |
14069 | ||
14070 | static rtx | |
14071 | mips_pic_call_symbol_from_set (df_ref def, rtx reg) | |
14072 | { | |
14073 | rtx def_insn, set; | |
14074 | ||
14075 | if (DF_REF_IS_ARTIFICIAL (def)) | |
14076 | return NULL_RTX; | |
14077 | ||
14078 | def_insn = DF_REF_INSN (def); | |
14079 | set = single_set (def_insn); | |
14080 | if (set && rtx_equal_p (SET_DEST (set), reg)) | |
14081 | { | |
14082 | rtx note, src, symbol; | |
14083 | ||
14084 | /* First, look at REG_EQUAL/EQUIV notes. */ | |
14085 | note = find_reg_equal_equiv_note (def_insn); | |
14086 | if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) | |
14087 | return XEXP (note, 0); | |
14088 | ||
14089 | /* For %call16 references we don't have REG_EQUAL. */ | |
14090 | src = SET_SRC (set); | |
14091 | symbol = mips_strip_unspec_call (src); | |
14092 | if (symbol) | |
14093 | { | |
14094 | gcc_assert (GET_CODE (symbol) == SYMBOL_REF); | |
14095 | return symbol; | |
14096 | } | |
14097 | ||
14098 | /* Follow simple register copies. */ | |
14099 | if (REG_P (src)) | |
14100 | return mips_find_pic_call_symbol (def_insn, src); | |
14101 | } | |
14102 | ||
14103 | return NULL_RTX; | |
14104 | } | |
14105 | ||
14106 | /* Find the definition of the use of REG in INSN. See if the definition is | |
14107 | one of the ways we load a register with a symbol address for a | |
14108 | mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of | |
14109 | the function, otherwise return NULL_RTX. */ | |
14110 | ||
14111 | static rtx | |
14112 | mips_find_pic_call_symbol (rtx insn, rtx reg) | |
14113 | { | |
14114 | df_ref use; | |
14115 | struct df_link *defs; | |
14116 | rtx symbol; | |
14117 | ||
14118 | use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]); | |
14119 | if (!use) | |
14120 | return NULL_RTX; | |
14121 | defs = DF_REF_CHAIN (use); | |
14122 | if (!defs) | |
14123 | return NULL_RTX; | |
14124 | symbol = mips_pic_call_symbol_from_set (defs->ref, reg); | |
14125 | if (!symbol) | |
14126 | return NULL_RTX; | |
14127 | ||
14128 | /* If we have more than one definition, they need to be identical. */ | |
14129 | for (defs = defs->next; defs; defs = defs->next) | |
14130 | { | |
14131 | rtx other; | |
14132 | ||
14133 | other = mips_pic_call_symbol_from_set (defs->ref, reg); | |
14134 | if (!rtx_equal_p (symbol, other)) | |
14135 | return NULL_RTX; | |
14136 | } | |
14137 | ||
14138 | return symbol; | |
14139 | } | |
14140 | ||
14141 | /* Replace the args_size operand of the call expression CALL with the | |
14142 | call-attribute UNSPEC and fill in SYMBOL as the function symbol. */ | |
14143 | ||
14144 | static void | |
14145 | mips_annotate_pic_call_expr (rtx call, rtx symbol) | |
14146 | { | |
14147 | rtx args_size; | |
14148 | ||
14149 | args_size = XEXP (call, 1); | |
14150 | XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size), | |
14151 | gen_rtvec (2, args_size, symbol), | |
14152 | UNSPEC_CALL_ATTR); | |
14153 | } | |
14154 | ||
14155 | /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See | |
14156 | if instead of the arg_size argument it contains the call attributes. If | |
14157 | yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function | |
14158 | symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is | |
14159 | -1. */ | |
14160 | ||
14161 | bool | |
14162 | mips_get_pic_call_symbol (rtx *operands, int args_size_opno) | |
14163 | { | |
14164 | rtx args_size, symbol; | |
14165 | ||
14166 | if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1) | |
14167 | return false; | |
14168 | ||
14169 | args_size = operands[args_size_opno]; | |
14170 | if (GET_CODE (args_size) != UNSPEC) | |
14171 | return false; | |
14172 | gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR); | |
14173 | ||
14174 | symbol = XVECEXP (args_size, 0, 1); | |
14175 | gcc_assert (GET_CODE (symbol) == SYMBOL_REF); | |
14176 | ||
14177 | operands[args_size_opno] = symbol; | |
14178 | return true; | |
14179 | } | |
14180 | ||
14181 | /* Use DF to annotate PIC indirect calls with the function symbol they | |
14182 | dispatch to. */ | |
14183 | ||
14184 | static void | |
14185 | mips_annotate_pic_calls (void) | |
14186 | { | |
14187 | basic_block bb; | |
14188 | rtx insn; | |
14189 | ||
14190 | FOR_EACH_BB (bb) | |
14191 | FOR_BB_INSNS (bb, insn) | |
14192 | { | |
951771dc | 14193 | rtx call, reg, symbol, second_call; |
b53da244 | 14194 | |
951771dc JW |
14195 | second_call = 0; |
14196 | call = mips_call_expr_from_insn (insn, &second_call); | |
b53da244 AN |
14197 | if (!call) |
14198 | continue; | |
14199 | gcc_assert (MEM_P (XEXP (call, 0))); | |
14200 | reg = XEXP (XEXP (call, 0), 0); | |
14201 | if (!REG_P (reg)) | |
14202 | continue; | |
14203 | ||
14204 | symbol = mips_find_pic_call_symbol (insn, reg); | |
14205 | if (symbol) | |
951771dc JW |
14206 | { |
14207 | mips_annotate_pic_call_expr (call, symbol); | |
14208 | if (second_call) | |
14209 | mips_annotate_pic_call_expr (second_call, symbol); | |
14210 | } | |
b53da244 | 14211 | } |
4d210b07 RS |
14212 | } |
14213 | \f | |
ab77a036 RS |
14214 | /* A temporary variable used by for_each_rtx callbacks, etc. */ |
14215 | static rtx mips_sim_insn; | |
39ba1719 | 14216 | |
ab77a036 RS |
14217 | /* A structure representing the state of the processor pipeline. |
14218 | Used by the mips_sim_* family of functions. */ | |
14219 | struct mips_sim { | |
14220 | /* The maximum number of instructions that can be issued in a cycle. | |
14221 | (Caches mips_issue_rate.) */ | |
14222 | unsigned int issue_rate; | |
39ba1719 | 14223 | |
ab77a036 RS |
14224 | /* The current simulation time. */ |
14225 | unsigned int time; | |
39ba1719 | 14226 | |
ab77a036 RS |
14227 | /* How many more instructions can be issued in the current cycle. */ |
14228 | unsigned int insns_left; | |
39ba1719 | 14229 | |
ab77a036 RS |
14230 | /* LAST_SET[X].INSN is the last instruction to set register X. |
14231 | LAST_SET[X].TIME is the time at which that instruction was issued. | |
14232 | INSN is null if no instruction has yet set register X. */ | |
14233 | struct { | |
14234 | rtx insn; | |
14235 | unsigned int time; | |
14236 | } last_set[FIRST_PSEUDO_REGISTER]; | |
39ba1719 | 14237 | |
ab77a036 RS |
14238 | /* The pipeline's current DFA state. */ |
14239 | state_t dfa_state; | |
14240 | }; | |
39ba1719 | 14241 | |
ab77a036 RS |
14242 | /* Reset STATE to the initial simulation state. */ |
14243 | ||
14244 | static void | |
14245 | mips_sim_reset (struct mips_sim *state) | |
14246 | { | |
14247 | state->time = 0; | |
14248 | state->insns_left = state->issue_rate; | |
14249 | memset (&state->last_set, 0, sizeof (state->last_set)); | |
14250 | state_reset (state->dfa_state); | |
39ba1719 | 14251 | } |
39ba1719 | 14252 | |
ab77a036 RS |
14253 | /* Initialize STATE before its first use. DFA_STATE points to an |
14254 | allocated but uninitialized DFA state. */ | |
39ba1719 | 14255 | |
ab77a036 RS |
14256 | static void |
14257 | mips_sim_init (struct mips_sim *state, state_t dfa_state) | |
14258 | { | |
14259 | state->issue_rate = mips_issue_rate (); | |
14260 | state->dfa_state = dfa_state; | |
14261 | mips_sim_reset (state); | |
14262 | } | |
14263 | ||
14264 | /* Advance STATE by one clock cycle. */ | |
39ba1719 RS |
14265 | |
14266 | static void | |
ab77a036 | 14267 | mips_sim_next_cycle (struct mips_sim *state) |
39ba1719 | 14268 | { |
ab77a036 RS |
14269 | state->time++; |
14270 | state->insns_left = state->issue_rate; | |
14271 | state_transition (state->dfa_state, 0); | |
39ba1719 RS |
14272 | } |
14273 | ||
ab77a036 RS |
14274 | /* Advance simulation state STATE until instruction INSN can read |
14275 | register REG. */ | |
39ba1719 RS |
14276 | |
14277 | static void | |
ab77a036 | 14278 | mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg) |
39ba1719 | 14279 | { |
65239d20 | 14280 | unsigned int regno, end_regno; |
39ba1719 | 14281 | |
65239d20 RS |
14282 | end_regno = END_REGNO (reg); |
14283 | for (regno = REGNO (reg); regno < end_regno; regno++) | |
14284 | if (state->last_set[regno].insn != 0) | |
ab77a036 RS |
14285 | { |
14286 | unsigned int t; | |
dc884a86 | 14287 | |
65239d20 RS |
14288 | t = (state->last_set[regno].time |
14289 | + insn_latency (state->last_set[regno].insn, insn)); | |
ab77a036 RS |
14290 | while (state->time < t) |
14291 | mips_sim_next_cycle (state); | |
14292 | } | |
14293 | } | |
dc884a86 | 14294 | |
ab77a036 RS |
14295 | /* A for_each_rtx callback. If *X is a register, advance simulation state |
14296 | DATA until mips_sim_insn can read the register's value. */ | |
dc884a86 | 14297 | |
ab77a036 RS |
14298 | static int |
14299 | mips_sim_wait_regs_2 (rtx *x, void *data) | |
dc884a86 | 14300 | { |
ab77a036 | 14301 | if (REG_P (*x)) |
5ead67f6 | 14302 | mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x); |
ab77a036 | 14303 | return 0; |
dc884a86 RS |
14304 | } |
14305 | ||
ab77a036 | 14306 | /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */ |
dc884a86 | 14307 | |
ab77a036 RS |
14308 | static void |
14309 | mips_sim_wait_regs_1 (rtx *x, void *data) | |
dc884a86 | 14310 | { |
ab77a036 | 14311 | for_each_rtx (x, mips_sim_wait_regs_2, data); |
dc884a86 RS |
14312 | } |
14313 | ||
ab77a036 RS |
14314 | /* Advance simulation state STATE until all of INSN's register |
14315 | dependencies are satisfied. */ | |
dc884a86 | 14316 | |
ab77a036 RS |
14317 | static void |
14318 | mips_sim_wait_regs (struct mips_sim *state, rtx insn) | |
dc884a86 | 14319 | { |
ab77a036 RS |
14320 | mips_sim_insn = insn; |
14321 | note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state); | |
14322 | } | |
dc884a86 | 14323 | |
ab77a036 RS |
14324 | /* Advance simulation state STATE until the units required by |
14325 | instruction INSN are available. */ | |
dc884a86 | 14326 | |
ab77a036 RS |
14327 | static void |
14328 | mips_sim_wait_units (struct mips_sim *state, rtx insn) | |
14329 | { | |
14330 | state_t tmp_state; | |
dc884a86 | 14331 | |
ab77a036 RS |
14332 | tmp_state = alloca (state_size ()); |
14333 | while (state->insns_left == 0 | |
14334 | || (memcpy (tmp_state, state->dfa_state, state_size ()), | |
14335 | state_transition (tmp_state, insn) >= 0)) | |
14336 | mips_sim_next_cycle (state); | |
dc884a86 RS |
14337 | } |
14338 | ||
ab77a036 | 14339 | /* Advance simulation state STATE until INSN is ready to issue. */ |
dc884a86 RS |
14340 | |
14341 | static void | |
ab77a036 | 14342 | mips_sim_wait_insn (struct mips_sim *state, rtx insn) |
dc884a86 | 14343 | { |
ab77a036 RS |
14344 | mips_sim_wait_regs (state, insn); |
14345 | mips_sim_wait_units (state, insn); | |
dc884a86 | 14346 | } |
ab77a036 RS |
14347 | |
14348 | /* mips_sim_insn has just set X. Update the LAST_SET array | |
14349 | in simulation state DATA. */ | |
39ba1719 RS |
14350 | |
14351 | static void | |
ab77a036 | 14352 | mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) |
39ba1719 | 14353 | { |
ab77a036 | 14354 | struct mips_sim *state; |
39ba1719 | 14355 | |
5ead67f6 | 14356 | state = (struct mips_sim *) data; |
ab77a036 | 14357 | if (REG_P (x)) |
65239d20 RS |
14358 | { |
14359 | unsigned int regno, end_regno; | |
14360 | ||
14361 | end_regno = END_REGNO (x); | |
14362 | for (regno = REGNO (x); regno < end_regno; regno++) | |
14363 | { | |
14364 | state->last_set[regno].insn = mips_sim_insn; | |
14365 | state->last_set[regno].time = state->time; | |
14366 | } | |
14367 | } | |
39ba1719 RS |
14368 | } |
14369 | ||
ab77a036 RS |
14370 | /* Issue instruction INSN in scheduler state STATE. Assume that INSN |
14371 | can issue immediately (i.e., that mips_sim_wait_insn has already | |
14372 | been called). */ | |
39ba1719 | 14373 | |
174bd8ca | 14374 | static void |
ab77a036 | 14375 | mips_sim_issue_insn (struct mips_sim *state, rtx insn) |
174bd8ca | 14376 | { |
ab77a036 RS |
14377 | state_transition (state->dfa_state, insn); |
14378 | state->insns_left--; | |
174bd8ca | 14379 | |
ab77a036 RS |
14380 | mips_sim_insn = insn; |
14381 | note_stores (PATTERN (insn), mips_sim_record_set, state); | |
14382 | } | |
174bd8ca | 14383 | |
ab77a036 | 14384 | /* Simulate issuing a NOP in state STATE. */ |
174bd8ca SL |
14385 | |
14386 | static void | |
ab77a036 | 14387 | mips_sim_issue_nop (struct mips_sim *state) |
174bd8ca | 14388 | { |
ab77a036 RS |
14389 | if (state->insns_left == 0) |
14390 | mips_sim_next_cycle (state); | |
14391 | state->insns_left--; | |
174bd8ca SL |
14392 | } |
14393 | ||
ab77a036 RS |
14394 | /* Update simulation state STATE so that it's ready to accept the instruction |
14395 | after INSN. INSN should be part of the main rtl chain, not a member of a | |
14396 | SEQUENCE. */ | |
174bd8ca SL |
14397 | |
14398 | static void | |
ab77a036 | 14399 | mips_sim_finish_insn (struct mips_sim *state, rtx insn) |
39ba1719 | 14400 | { |
ab77a036 RS |
14401 | /* If INSN is a jump with an implicit delay slot, simulate a nop. */ |
14402 | if (JUMP_P (insn)) | |
14403 | mips_sim_issue_nop (state); | |
174bd8ca | 14404 | |
ab77a036 | 14405 | switch (GET_CODE (SEQ_BEGIN (insn))) |
39ba1719 | 14406 | { |
ab77a036 RS |
14407 | case CODE_LABEL: |
14408 | case CALL_INSN: | |
14409 | /* We can't predict the processor state after a call or label. */ | |
14410 | mips_sim_reset (state); | |
14411 | break; | |
d33289b2 | 14412 | |
ab77a036 RS |
14413 | case JUMP_INSN: |
14414 | /* The delay slots of branch likely instructions are only executed | |
14415 | when the branch is taken. Therefore, if the caller has simulated | |
14416 | the delay slot instruction, STATE does not really reflect the state | |
14417 | of the pipeline for the instruction after the delay slot. Also, | |
14418 | branch likely instructions tend to incur a penalty when not taken, | |
14419 | so there will probably be an extra delay between the branch and | |
14420 | the instruction after the delay slot. */ | |
14421 | if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn))) | |
14422 | mips_sim_reset (state); | |
14423 | break; | |
d33289b2 | 14424 | |
ab77a036 RS |
14425 | default: |
14426 | break; | |
dc884a86 | 14427 | } |
174bd8ca | 14428 | } |
ab77a036 RS |
14429 | \f |
14430 | /* The VR4130 pipeline issues aligned pairs of instructions together, | |
14431 | but it stalls the second instruction if it depends on the first. | |
14432 | In order to cut down the amount of logic required, this dependence | |
14433 | check is not based on a full instruction decode. Instead, any non-SPECIAL | |
14434 | instruction is assumed to modify the register specified by bits 20-16 | |
14435 | (which is usually the "rt" field). | |
174bd8ca | 14436 | |
65239d20 | 14437 | In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an |
ab77a036 RS |
14438 | input, so we can end up with a false dependence between the branch |
14439 | and its delay slot. If this situation occurs in instruction INSN, | |
14440 | try to avoid it by swapping rs and rt. */ | |
174bd8ca SL |
14441 | |
14442 | static void | |
ab77a036 | 14443 | vr4130_avoid_branch_rt_conflict (rtx insn) |
174bd8ca | 14444 | { |
ab77a036 | 14445 | rtx first, second; |
39ba1719 | 14446 | |
ab77a036 RS |
14447 | first = SEQ_BEGIN (insn); |
14448 | second = SEQ_END (insn); | |
14449 | if (JUMP_P (first) | |
14450 | && NONJUMP_INSN_P (second) | |
14451 | && GET_CODE (PATTERN (first)) == SET | |
14452 | && GET_CODE (SET_DEST (PATTERN (first))) == PC | |
14453 | && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE) | |
39ba1719 | 14454 | { |
ab77a036 RS |
14455 | /* Check for the right kind of condition. */ |
14456 | rtx cond = XEXP (SET_SRC (PATTERN (first)), 0); | |
14457 | if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE) | |
14458 | && REG_P (XEXP (cond, 0)) | |
14459 | && REG_P (XEXP (cond, 1)) | |
14460 | && reg_referenced_p (XEXP (cond, 1), PATTERN (second)) | |
14461 | && !reg_referenced_p (XEXP (cond, 0), PATTERN (second))) | |
14462 | { | |
14463 | /* SECOND mentions the rt register but not the rs register. */ | |
14464 | rtx tmp = XEXP (cond, 0); | |
14465 | XEXP (cond, 0) = XEXP (cond, 1); | |
14466 | XEXP (cond, 1) = tmp; | |
14467 | } | |
39ba1719 | 14468 | } |
39ba1719 RS |
14469 | } |
14470 | ||
ab77a036 RS |
14471 | /* Implement -mvr4130-align. Go through each basic block and simulate the |
14472 | processor pipeline. If we find that a pair of instructions could execute | |
65239d20 | 14473 | in parallel, and the first of those instructions is not 8-byte aligned, |
ab77a036 | 14474 | insert a nop to make it aligned. */ |
0c8da560 | 14475 | |
ab77a036 RS |
14476 | static void |
14477 | vr4130_align_insns (void) | |
b875d2ee | 14478 | { |
ab77a036 RS |
14479 | struct mips_sim state; |
14480 | rtx insn, subinsn, last, last2, next; | |
14481 | bool aligned_p; | |
b875d2ee | 14482 | |
ab77a036 | 14483 | dfa_start (); |
50d32cf6 | 14484 | |
ab77a036 RS |
14485 | /* LAST is the last instruction before INSN to have a nonzero length. |
14486 | LAST2 is the last such instruction before LAST. */ | |
14487 | last = 0; | |
14488 | last2 = 0; | |
54401342 | 14489 | |
ab77a036 RS |
14490 | /* ALIGNED_P is true if INSN is known to be at an aligned address. */ |
14491 | aligned_p = true; | |
50d32cf6 | 14492 | |
ab77a036 RS |
14493 | mips_sim_init (&state, alloca (state_size ())); |
14494 | for (insn = get_insns (); insn != 0; insn = next) | |
14495 | { | |
14496 | unsigned int length; | |
50d32cf6 | 14497 | |
ab77a036 | 14498 | next = NEXT_INSN (insn); |
c81d6e2a | 14499 | |
ab77a036 RS |
14500 | /* See the comment above vr4130_avoid_branch_rt_conflict for details. |
14501 | This isn't really related to the alignment pass, but we do it on | |
14502 | the fly to avoid a separate instruction walk. */ | |
14503 | vr4130_avoid_branch_rt_conflict (insn); | |
c81d6e2a | 14504 | |
ab77a036 RS |
14505 | if (USEFUL_INSN_P (insn)) |
14506 | FOR_EACH_SUBINSN (subinsn, insn) | |
14507 | { | |
14508 | mips_sim_wait_insn (&state, subinsn); | |
c81d6e2a | 14509 | |
ab77a036 RS |
14510 | /* If we want this instruction to issue in parallel with the |
14511 | previous one, make sure that the previous instruction is | |
14512 | aligned. There are several reasons why this isn't worthwhile | |
14513 | when the second instruction is a call: | |
5ce6f47b | 14514 | |
ab77a036 RS |
14515 | - Calls are less likely to be performance critical, |
14516 | - There's a good chance that the delay slot can execute | |
14517 | in parallel with the call. | |
14518 | - The return address would then be unaligned. | |
4767c570 | 14519 | |
ab77a036 RS |
14520 | In general, if we're going to insert a nop between instructions |
14521 | X and Y, it's better to insert it immediately after X. That | |
14522 | way, if the nop makes Y aligned, it will also align any labels | |
14523 | between X and Y. */ | |
14524 | if (state.insns_left != state.issue_rate | |
14525 | && !CALL_P (subinsn)) | |
14526 | { | |
14527 | if (subinsn == SEQ_BEGIN (insn) && aligned_p) | |
14528 | { | |
14529 | /* SUBINSN is the first instruction in INSN and INSN is | |
14530 | aligned. We want to align the previous instruction | |
14531 | instead, so insert a nop between LAST2 and LAST. | |
8f2e3902 | 14532 | |
ab77a036 RS |
14533 | Note that LAST could be either a single instruction |
14534 | or a branch with a delay slot. In the latter case, | |
14535 | LAST, like INSN, is already aligned, but the delay | |
14536 | slot must have some extra delay that stops it from | |
14537 | issuing at the same time as the branch. We therefore | |
14538 | insert a nop before the branch in order to align its | |
14539 | delay slot. */ | |
14540 | emit_insn_after (gen_nop (), last2); | |
14541 | aligned_p = false; | |
14542 | } | |
14543 | else if (subinsn != SEQ_BEGIN (insn) && !aligned_p) | |
14544 | { | |
14545 | /* SUBINSN is the delay slot of INSN, but INSN is | |
14546 | currently unaligned. Insert a nop between | |
14547 | LAST and INSN to align it. */ | |
14548 | emit_insn_after (gen_nop (), last); | |
14549 | aligned_p = true; | |
14550 | } | |
14551 | } | |
14552 | mips_sim_issue_insn (&state, subinsn); | |
14553 | } | |
14554 | mips_sim_finish_insn (&state, insn); | |
06a4ab70 | 14555 | |
ab77a036 RS |
14556 | /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */ |
14557 | length = get_attr_length (insn); | |
14558 | if (length > 0) | |
14559 | { | |
14560 | /* If the instruction is an asm statement or multi-instruction | |
14561 | mips.md patern, the length is only an estimate. Insert an | |
14562 | 8 byte alignment after it so that the following instructions | |
14563 | can be handled correctly. */ | |
14564 | if (NONJUMP_INSN_P (SEQ_BEGIN (insn)) | |
14565 | && (recog_memoized (insn) < 0 || length >= 8)) | |
14566 | { | |
14567 | next = emit_insn_after (gen_align (GEN_INT (3)), insn); | |
14568 | next = NEXT_INSN (next); | |
14569 | mips_sim_next_cycle (&state); | |
14570 | aligned_p = true; | |
14571 | } | |
14572 | else if (length & 4) | |
14573 | aligned_p = !aligned_p; | |
14574 | last2 = last; | |
14575 | last = insn; | |
14576 | } | |
4ca1f68f | 14577 | |
ab77a036 RS |
14578 | /* See whether INSN is an aligned label. */ |
14579 | if (LABEL_P (insn) && label_to_alignment (insn) >= 3) | |
14580 | aligned_p = true; | |
14581 | } | |
14582 | dfa_finish (); | |
14583 | } | |
14584 | \f | |
a35de342 RS |
14585 | /* This structure records that the current function has a LO_SUM |
14586 | involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is | |
14587 | the largest offset applied to BASE by all such LO_SUMs. */ | |
14588 | struct mips_lo_sum_offset { | |
14589 | rtx base; | |
14590 | HOST_WIDE_INT offset; | |
14591 | }; | |
14592 | ||
14593 | /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */ | |
14594 | ||
14595 | static hashval_t | |
14596 | mips_hash_base (rtx base) | |
14597 | { | |
14598 | int do_not_record_p; | |
14599 | ||
14600 | return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false); | |
14601 | } | |
14602 | ||
14603 | /* Hash-table callbacks for mips_lo_sum_offsets. */ | |
14604 | ||
14605 | static hashval_t | |
14606 | mips_lo_sum_offset_hash (const void *entry) | |
14607 | { | |
14608 | return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base); | |
14609 | } | |
14610 | ||
14611 | static int | |
14612 | mips_lo_sum_offset_eq (const void *entry, const void *value) | |
14613 | { | |
14614 | return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base, | |
14615 | (const_rtx) value); | |
14616 | } | |
14617 | ||
14618 | /* Look up symbolic constant X in HTAB, which is a hash table of | |
14619 | mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be | |
14620 | paired with a recorded LO_SUM, otherwise record X in the table. */ | |
14621 | ||
14622 | static bool | |
14623 | mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option) | |
14624 | { | |
14625 | rtx base, offset; | |
14626 | void **slot; | |
14627 | struct mips_lo_sum_offset *entry; | |
14628 | ||
14629 | /* Split X into a base and offset. */ | |
14630 | split_const (x, &base, &offset); | |
14631 | if (UNSPEC_ADDRESS_P (base)) | |
14632 | base = UNSPEC_ADDRESS (base); | |
14633 | ||
14634 | /* Look up the base in the hash table. */ | |
14635 | slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option); | |
14636 | if (slot == NULL) | |
14637 | return false; | |
14638 | ||
14639 | entry = (struct mips_lo_sum_offset *) *slot; | |
14640 | if (option == INSERT) | |
14641 | { | |
14642 | if (entry == NULL) | |
14643 | { | |
14644 | entry = XNEW (struct mips_lo_sum_offset); | |
14645 | entry->base = base; | |
14646 | entry->offset = INTVAL (offset); | |
14647 | *slot = entry; | |
14648 | } | |
14649 | else | |
14650 | { | |
14651 | if (INTVAL (offset) > entry->offset) | |
14652 | entry->offset = INTVAL (offset); | |
14653 | } | |
14654 | } | |
14655 | return INTVAL (offset) <= entry->offset; | |
14656 | } | |
14657 | ||
14658 | /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table. | |
14659 | Record every LO_SUM in *LOC. */ | |
14660 | ||
14661 | static int | |
14662 | mips_record_lo_sum (rtx *loc, void *data) | |
14663 | { | |
14664 | if (GET_CODE (*loc) == LO_SUM) | |
14665 | mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT); | |
14666 | return 0; | |
14667 | } | |
14668 | ||
14669 | /* Return true if INSN is a SET of an orphaned high-part relocation. | |
14670 | HTAB is a hash table of mips_lo_sum_offsets that describes all the | |
14671 | LO_SUMs in the current function. */ | |
14672 | ||
14673 | static bool | |
14674 | mips_orphaned_high_part_p (htab_t htab, rtx insn) | |
14675 | { | |
14676 | enum mips_symbol_type type; | |
14677 | rtx x, set; | |
14678 | ||
14679 | set = single_set (insn); | |
14680 | if (set) | |
14681 | { | |
14682 | /* Check for %his. */ | |
14683 | x = SET_SRC (set); | |
14684 | if (GET_CODE (x) == HIGH | |
14685 | && absolute_symbolic_operand (XEXP (x, 0), VOIDmode)) | |
14686 | return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT); | |
14687 | ||
14688 | /* Check for local %gots (and %got_pages, which is redundant but OK). */ | |
14689 | if (GET_CODE (x) == UNSPEC | |
14690 | && XINT (x, 1) == UNSPEC_LOAD_GOT | |
14691 | && mips_symbolic_constant_p (XVECEXP (x, 0, 1), | |
14692 | SYMBOL_CONTEXT_LEA, &type) | |
14693 | && type == SYMBOL_GOTOFF_PAGE) | |
14694 | return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT); | |
14695 | } | |
14696 | return false; | |
14697 | } | |
14698 | ||
14699 | /* Subroutine of mips_reorg_process_insns. If there is a hazard between | |
14700 | INSN and a previous instruction, avoid it by inserting nops after | |
ab77a036 | 14701 | instruction AFTER. |
308cd611 | 14702 | |
ab77a036 RS |
14703 | *DELAYED_REG and *HILO_DELAY describe the hazards that apply at |
14704 | this point. If *DELAYED_REG is non-null, INSN must wait a cycle | |
14705 | before using the value of that register. *HILO_DELAY counts the | |
14706 | number of instructions since the last hilo hazard (that is, | |
65239d20 | 14707 | the number of instructions since the last MFLO or MFHI). |
4ca1f68f | 14708 | |
ab77a036 RS |
14709 | After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY |
14710 | for the next instruction. | |
4ca1f68f | 14711 | |
ab77a036 | 14712 | LO_REG is an rtx for the LO register, used in dependence checking. */ |
4ca1f68f | 14713 | |
ab77a036 RS |
14714 | static void |
14715 | mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay, | |
14716 | rtx *delayed_reg, rtx lo_reg) | |
14717 | { | |
14718 | rtx pattern, set; | |
dbc90b65 | 14719 | int nops, ninsns; |
06a4ab70 | 14720 | |
ab77a036 | 14721 | pattern = PATTERN (insn); |
4ca1f68f | 14722 | |
ab77a036 RS |
14723 | /* Do not put the whole function in .set noreorder if it contains |
14724 | an asm statement. We don't know whether there will be hazards | |
14725 | between the asm statement and the gcc-generated code. */ | |
14726 | if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0) | |
14727 | cfun->machine->all_noreorder_p = false; | |
4ca1f68f | 14728 | |
ab77a036 RS |
14729 | /* Ignore zero-length instructions (barriers and the like). */ |
14730 | ninsns = get_attr_length (insn) / 4; | |
14731 | if (ninsns == 0) | |
14732 | return; | |
4ca1f68f | 14733 | |
ab77a036 RS |
14734 | /* Work out how many nops are needed. Note that we only care about |
14735 | registers that are explicitly mentioned in the instruction's pattern. | |
14736 | It doesn't matter that calls use the argument registers or that they | |
14737 | clobber hi and lo. */ | |
14738 | if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern)) | |
14739 | nops = 2 - *hilo_delay; | |
14740 | else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern)) | |
14741 | nops = 1; | |
14742 | else | |
14743 | nops = 0; | |
4ca1f68f | 14744 | |
ab77a036 RS |
14745 | /* Insert the nops between this instruction and the previous one. |
14746 | Each new nop takes us further from the last hilo hazard. */ | |
14747 | *hilo_delay += nops; | |
14748 | while (nops-- > 0) | |
14749 | emit_insn_after (gen_hazard_nop (), after); | |
4ca1f68f | 14750 | |
ab77a036 RS |
14751 | /* Set up the state for the next instruction. */ |
14752 | *hilo_delay += ninsns; | |
14753 | *delayed_reg = 0; | |
14754 | if (INSN_CODE (insn) >= 0) | |
14755 | switch (get_attr_hazard (insn)) | |
14756 | { | |
14757 | case HAZARD_NONE: | |
14758 | break; | |
21c425ee | 14759 | |
ab77a036 RS |
14760 | case HAZARD_HILO: |
14761 | *hilo_delay = 0; | |
14762 | break; | |
4ca1f68f | 14763 | |
ab77a036 | 14764 | case HAZARD_DELAY: |
dbc90b65 RS |
14765 | set = single_set (insn); |
14766 | gcc_assert (set); | |
ab77a036 RS |
14767 | *delayed_reg = SET_DEST (set); |
14768 | break; | |
14769 | } | |
14770 | } | |
4ca1f68f | 14771 | |
ab77a036 | 14772 | /* Go through the instruction stream and insert nops where necessary. |
a35de342 RS |
14773 | Also delete any high-part relocations whose partnering low parts |
14774 | are now all dead. See if the whole function can then be put into | |
14775 | .set noreorder and .set nomacro. */ | |
06a4ab70 | 14776 | |
ab77a036 | 14777 | static void |
a35de342 | 14778 | mips_reorg_process_insns (void) |
ab77a036 | 14779 | { |
a35de342 RS |
14780 | rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg; |
14781 | int hilo_delay; | |
14782 | htab_t htab; | |
1823bf53 | 14783 | |
ab77a036 RS |
14784 | /* Force all instructions to be split into their final form. */ |
14785 | split_all_insns_noflow (); | |
1823bf53 | 14786 | |
ab77a036 RS |
14787 | /* Recalculate instruction lengths without taking nops into account. */ |
14788 | cfun->machine->ignore_hazard_length_p = true; | |
14789 | shorten_branches (get_insns ()); | |
1823bf53 | 14790 | |
ab77a036 | 14791 | cfun->machine->all_noreorder_p = true; |
118ea793 | 14792 | |
08d0963a RS |
14793 | /* We don't track MIPS16 PC-relative offsets closely enough to make |
14794 | a good job of "set .noreorder" code in MIPS16 mode. */ | |
14795 | if (TARGET_MIPS16) | |
14796 | cfun->machine->all_noreorder_p = false; | |
14797 | ||
a35de342 RS |
14798 | /* Code that doesn't use explicit relocs can't be ".set nomacro". */ |
14799 | if (!TARGET_EXPLICIT_RELOCS) | |
14800 | cfun->machine->all_noreorder_p = false; | |
14801 | ||
ab77a036 RS |
14802 | /* Profiled functions can't be all noreorder because the profiler |
14803 | support uses assembler macros. */ | |
e3b5732b | 14804 | if (crtl->profile) |
ab77a036 | 14805 | cfun->machine->all_noreorder_p = false; |
118ea793 | 14806 | |
ab77a036 RS |
14807 | /* Code compiled with -mfix-vr4120 can't be all noreorder because |
14808 | we rely on the assembler to work around some errata. */ | |
14809 | if (TARGET_FIX_VR4120) | |
14810 | cfun->machine->all_noreorder_p = false; | |
118ea793 | 14811 | |
65239d20 RS |
14812 | /* The same is true for -mfix-vr4130 if we might generate MFLO or |
14813 | MFHI instructions. Note that we avoid using MFLO and MFHI if | |
14814 | the VR4130 MACC and DMACC instructions are available instead; | |
ab77a036 RS |
14815 | see the *mfhilo_{si,di}_macc patterns. */ |
14816 | if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI) | |
14817 | cfun->machine->all_noreorder_p = false; | |
118ea793 | 14818 | |
a35de342 RS |
14819 | htab = htab_create (37, mips_lo_sum_offset_hash, |
14820 | mips_lo_sum_offset_eq, free); | |
14821 | ||
14822 | /* Make a first pass over the instructions, recording all the LO_SUMs. */ | |
14823 | for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn)) | |
14824 | FOR_EACH_SUBINSN (subinsn, insn) | |
006b29ab | 14825 | if (USEFUL_INSN_P (subinsn)) |
a35de342 RS |
14826 | for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab); |
14827 | ||
ab77a036 RS |
14828 | last_insn = 0; |
14829 | hilo_delay = 2; | |
14830 | delayed_reg = 0; | |
14831 | lo_reg = gen_rtx_REG (SImode, LO_REGNUM); | |
32041385 | 14832 | |
a35de342 RS |
14833 | /* Make a second pass over the instructions. Delete orphaned |
14834 | high-part relocations or turn them into NOPs. Avoid hazards | |
14835 | by inserting NOPs. */ | |
14836 | for (insn = get_insns (); insn != 0; insn = next_insn) | |
14837 | { | |
14838 | next_insn = NEXT_INSN (insn); | |
006b29ab | 14839 | if (USEFUL_INSN_P (insn)) |
a35de342 RS |
14840 | { |
14841 | if (GET_CODE (PATTERN (insn)) == SEQUENCE) | |
14842 | { | |
14843 | /* If we find an orphaned high-part relocation in a delay | |
14844 | slot, it's easier to turn that instruction into a NOP than | |
14845 | to delete it. The delay slot will be a NOP either way. */ | |
14846 | FOR_EACH_SUBINSN (subinsn, insn) | |
14847 | if (INSN_P (subinsn)) | |
14848 | { | |
14849 | if (mips_orphaned_high_part_p (htab, subinsn)) | |
14850 | { | |
14851 | PATTERN (subinsn) = gen_nop (); | |
14852 | INSN_CODE (subinsn) = CODE_FOR_nop; | |
14853 | } | |
14854 | mips_avoid_hazard (last_insn, subinsn, &hilo_delay, | |
14855 | &delayed_reg, lo_reg); | |
14856 | } | |
14857 | last_insn = insn; | |
14858 | } | |
14859 | else | |
14860 | { | |
14861 | /* INSN is a single instruction. Delete it if it's an | |
14862 | orphaned high-part relocation. */ | |
14863 | if (mips_orphaned_high_part_p (htab, insn)) | |
14864 | delete_insn (insn); | |
4d210b07 RS |
14865 | /* Also delete cache barriers if the last instruction |
14866 | was an annulled branch. INSN will not be speculatively | |
14867 | executed. */ | |
14868 | else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier | |
14869 | && last_insn | |
14870 | && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn))) | |
14871 | delete_insn (insn); | |
a35de342 RS |
14872 | else |
14873 | { | |
14874 | mips_avoid_hazard (last_insn, insn, &hilo_delay, | |
14875 | &delayed_reg, lo_reg); | |
14876 | last_insn = insn; | |
14877 | } | |
14878 | } | |
14879 | } | |
14880 | } | |
32041385 | 14881 | |
a35de342 | 14882 | htab_delete (htab); |
ab77a036 RS |
14883 | } |
14884 | ||
0c433c31 RS |
14885 | /* If we are using a GOT, but have not decided to use a global pointer yet, |
14886 | see whether we need one to implement long branches. Convert the ghost | |
14887 | global-pointer instructions into real ones if so. */ | |
14888 | ||
14889 | static bool | |
14890 | mips_expand_ghost_gp_insns (void) | |
14891 | { | |
14892 | rtx insn; | |
14893 | int normal_length; | |
14894 | ||
14895 | /* Quick exit if we already know that we will or won't need a | |
14896 | global pointer. */ | |
14897 | if (!TARGET_USE_GOT | |
14898 | || cfun->machine->global_pointer == INVALID_REGNUM | |
14899 | || mips_must_initialize_gp_p ()) | |
14900 | return false; | |
14901 | ||
14902 | shorten_branches (get_insns ()); | |
14903 | ||
14904 | /* Look for a branch that is longer than normal. The normal length for | |
14905 | non-MIPS16 branches is 8, because the length includes the delay slot. | |
14906 | It is 4 for MIPS16, because MIPS16 branches are extended instructions, | |
14907 | but they have no delay slot. */ | |
14908 | normal_length = (TARGET_MIPS16 ? 4 : 8); | |
14909 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
14910 | if (JUMP_P (insn) | |
14911 | && USEFUL_INSN_P (insn) | |
14912 | && get_attr_length (insn) > normal_length) | |
14913 | break; | |
14914 | ||
14915 | if (insn == NULL_RTX) | |
14916 | return false; | |
14917 | ||
14918 | /* We've now established that we need $gp. */ | |
14919 | cfun->machine->must_initialize_gp_p = true; | |
14920 | split_all_insns_noflow (); | |
14921 | ||
14922 | return true; | |
14923 | } | |
14924 | ||
b53da244 AN |
14925 | /* Subroutine of mips_reorg to manage passes that require DF. */ |
14926 | ||
14927 | static void | |
14928 | mips_df_reorg (void) | |
14929 | { | |
14930 | /* Create def-use chains. */ | |
14931 | df_set_flags (DF_EQ_NOTES); | |
14932 | df_chain_add_problem (DF_UD_CHAIN); | |
14933 | df_analyze (); | |
14934 | ||
14935 | if (TARGET_RELAX_PIC_CALLS) | |
14936 | mips_annotate_pic_calls (); | |
14937 | ||
14938 | if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE) | |
14939 | r10k_insert_cache_barriers (); | |
14940 | ||
14941 | df_finish_pass (false); | |
14942 | } | |
14943 | ||
ab77a036 RS |
14944 | /* Implement TARGET_MACHINE_DEPENDENT_REORG. */ |
14945 | ||
14946 | static void | |
14947 | mips_reorg (void) | |
32041385 | 14948 | { |
b53da244 AN |
14949 | /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during |
14950 | insn splitting in mips16_lay_out_constants, DF insn info is only kept up | |
14951 | to date if the CFG is available. */ | |
14952 | if (mips_cfg_in_reorg ()) | |
14953 | compute_bb_for_insn (); | |
ab77a036 | 14954 | mips16_lay_out_constants (); |
b53da244 AN |
14955 | if (mips_cfg_in_reorg ()) |
14956 | { | |
14957 | mips_df_reorg (); | |
14958 | free_bb_for_insn (); | |
14959 | } | |
14960 | ||
c7789bfb | 14961 | if (optimize > 0 && flag_delayed_branch) |
a35de342 RS |
14962 | dbr_schedule (get_insns ()); |
14963 | mips_reorg_process_insns (); | |
08d0963a RS |
14964 | if (!TARGET_MIPS16 |
14965 | && TARGET_EXPLICIT_RELOCS | |
14966 | && TUNE_MIPS4130 | |
14967 | && TARGET_VR4130_ALIGN) | |
a35de342 | 14968 | vr4130_align_insns (); |
0c433c31 RS |
14969 | if (mips_expand_ghost_gp_insns ()) |
14970 | /* The expansion could invalidate some of the VR4130 alignment | |
14971 | optimizations, but this should be an extremely rare case anyhow. */ | |
14972 | mips_reorg_process_insns (); | |
ab77a036 RS |
14973 | } |
14974 | \f | |
14975 | /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text | |
14976 | in order to avoid duplicating too much logic from elsewhere. */ | |
32041385 | 14977 | |
ab77a036 RS |
14978 | static void |
14979 | mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, | |
14980 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
14981 | tree function) | |
14982 | { | |
0a2aaacc | 14983 | rtx this_rtx, temp1, temp2, insn, fnaddr; |
ab77a036 RS |
14984 | bool use_sibcall_p; |
14985 | ||
14986 | /* Pretend to be a post-reload pass while generating rtl. */ | |
14987 | reload_completed = 1; | |
14988 | ||
14989 | /* Mark the end of the (empty) prologue. */ | |
14990 | emit_note (NOTE_INSN_PROLOGUE_END); | |
14991 | ||
14992 | /* Determine if we can use a sibcall to call FUNCTION directly. */ | |
14993 | fnaddr = XEXP (DECL_RTL (function), 0); | |
14994 | use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL) | |
14995 | && const_call_insn_operand (fnaddr, Pmode)); | |
14996 | ||
14997 | /* Determine if we need to load FNADDR from the GOT. */ | |
08d0963a RS |
14998 | if (!use_sibcall_p |
14999 | && (mips_got_symbol_type_p | |
15000 | (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA)))) | |
15001 | { | |
15002 | /* Pick a global pointer. Use a call-clobbered register if | |
15003 | TARGET_CALL_SAVED_GP. */ | |
15004 | cfun->machine->global_pointer | |
15005 | = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM; | |
0c433c31 | 15006 | cfun->machine->must_initialize_gp_p = true; |
08d0963a | 15007 | SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer); |
ab77a036 | 15008 | |
08d0963a RS |
15009 | /* Set up the global pointer for n32 or n64 abicalls. */ |
15010 | mips_emit_loadgp (); | |
15011 | } | |
ab77a036 RS |
15012 | |
15013 | /* We need two temporary registers in some cases. */ | |
15014 | temp1 = gen_rtx_REG (Pmode, 2); | |
15015 | temp2 = gen_rtx_REG (Pmode, 3); | |
15016 | ||
15017 | /* Find out which register contains the "this" pointer. */ | |
15018 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
0a2aaacc | 15019 | this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1); |
ab77a036 | 15020 | else |
0a2aaacc | 15021 | this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST); |
ab77a036 | 15022 | |
0a2aaacc | 15023 | /* Add DELTA to THIS_RTX. */ |
ab77a036 RS |
15024 | if (delta != 0) |
15025 | { | |
15026 | rtx offset = GEN_INT (delta); | |
15027 | if (!SMALL_OPERAND (delta)) | |
15028 | { | |
15029 | mips_emit_move (temp1, offset); | |
15030 | offset = temp1; | |
15031 | } | |
0a2aaacc | 15032 | emit_insn (gen_add3_insn (this_rtx, this_rtx, offset)); |
ab77a036 RS |
15033 | } |
15034 | ||
0a2aaacc | 15035 | /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */ |
ab77a036 RS |
15036 | if (vcall_offset != 0) |
15037 | { | |
15038 | rtx addr; | |
15039 | ||
0a2aaacc KG |
15040 | /* Set TEMP1 to *THIS_RTX. */ |
15041 | mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx)); | |
ab77a036 | 15042 | |
0a2aaacc | 15043 | /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */ |
ab77a036 RS |
15044 | addr = mips_add_offset (temp2, temp1, vcall_offset); |
15045 | ||
0a2aaacc | 15046 | /* Load the offset and add it to THIS_RTX. */ |
ab77a036 | 15047 | mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr)); |
0a2aaacc | 15048 | emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1)); |
ab77a036 RS |
15049 | } |
15050 | ||
15051 | /* Jump to the target function. Use a sibcall if direct jumps are | |
15052 | allowed, otherwise load the address into a register first. */ | |
15053 | if (use_sibcall_p) | |
15054 | { | |
15055 | insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx)); | |
15056 | SIBLING_CALL_P (insn) = 1; | |
15057 | } | |
15058 | else | |
15059 | { | |
65239d20 | 15060 | /* This is messy. GAS treats "la $25,foo" as part of a call |
ab77a036 RS |
15061 | sequence and may allow a global "foo" to be lazily bound. |
15062 | The general move patterns therefore reject this combination. | |
15063 | ||
15064 | In this context, lazy binding would actually be OK | |
15065 | for TARGET_CALL_CLOBBERED_GP, but it's still wrong for | |
15066 | TARGET_CALL_SAVED_GP; see mips_load_call_address. | |
15067 | We must therefore load the address via a temporary | |
15068 | register if mips_dangerous_for_la25_p. | |
15069 | ||
08d0963a RS |
15070 | If we jump to the temporary register rather than $25, |
15071 | the assembler can use the move insn to fill the jump's | |
15072 | delay slot. | |
15073 | ||
15074 | We can use the same technique for MIPS16 code, where $25 | |
15075 | is not a valid JR register. */ | |
ab77a036 | 15076 | if (TARGET_USE_PIC_FN_ADDR_REG |
08d0963a | 15077 | && !TARGET_MIPS16 |
ab77a036 RS |
15078 | && !mips_dangerous_for_la25_p (fnaddr)) |
15079 | temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM); | |
08d0963a | 15080 | mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr); |
ab77a036 RS |
15081 | |
15082 | if (TARGET_USE_PIC_FN_ADDR_REG | |
15083 | && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM) | |
15084 | mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1); | |
15085 | emit_jump_insn (gen_indirect_jump (temp1)); | |
15086 | } | |
15087 | ||
15088 | /* Run just enough of rest_of_compilation. This sequence was | |
15089 | "borrowed" from alpha.c. */ | |
15090 | insn = get_insns (); | |
15091 | insn_locators_alloc (); | |
15092 | split_all_insns_noflow (); | |
15093 | mips16_lay_out_constants (); | |
15094 | shorten_branches (insn); | |
15095 | final_start_function (insn, file, 1); | |
15096 | final (insn, file, 1); | |
15097 | final_end_function (); | |
15098 | ||
15099 | /* Clean up the vars set above. Note that final_end_function resets | |
15100 | the global pointer for us. */ | |
15101 | reload_completed = 0; | |
15102 | } | |
15103 | \f | |
65239d20 | 15104 | /* The last argument passed to mips_set_mips16_mode, or negative if the |
60730ade RS |
15105 | function hasn't been called yet. |
15106 | ||
15107 | There are two copies of this information. One is saved and restored | |
15108 | by the PCH process while the other is specific to this compiler | |
15109 | invocation. The information calculated by mips_set_mips16_mode | |
15110 | is invalid unless the two variables are the same. */ | |
15111 | static int was_mips16_p = -1; | |
15112 | static GTY(()) int was_mips16_pch_p = -1; | |
ab77a036 RS |
15113 | |
15114 | /* Set up the target-dependent global state so that it matches the | |
15115 | current function's ISA mode. */ | |
15116 | ||
15117 | static void | |
15118 | mips_set_mips16_mode (int mips16_p) | |
15119 | { | |
60730ade RS |
15120 | if (mips16_p == was_mips16_p |
15121 | && mips16_p == was_mips16_pch_p) | |
ab77a036 RS |
15122 | return; |
15123 | ||
15124 | /* Restore base settings of various flags. */ | |
15125 | target_flags = mips_base_target_flags; | |
ab77a036 RS |
15126 | flag_schedule_insns = mips_base_schedule_insns; |
15127 | flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition; | |
15128 | flag_move_loop_invariants = mips_base_move_loop_invariants; | |
15129 | align_loops = mips_base_align_loops; | |
15130 | align_jumps = mips_base_align_jumps; | |
15131 | align_functions = mips_base_align_functions; | |
15132 | ||
15133 | if (mips16_p) | |
15134 | { | |
65239d20 | 15135 | /* Switch to MIPS16 mode. */ |
ab77a036 RS |
15136 | target_flags |= MASK_MIPS16; |
15137 | ||
15138 | /* Don't run the scheduler before reload, since it tends to | |
15139 | increase register pressure. */ | |
15140 | flag_schedule_insns = 0; | |
15141 | ||
65239d20 | 15142 | /* Don't do hot/cold partitioning. mips16_lay_out_constants expects |
ab77a036 RS |
15143 | the whole function to be in a single section. */ |
15144 | flag_reorder_blocks_and_partition = 0; | |
15145 | ||
15146 | /* Don't move loop invariants, because it tends to increase | |
15147 | register pressure. It also introduces an extra move in cases | |
15148 | where the constant is the first operand in a two-operand binary | |
15149 | instruction, or when it forms a register argument to a functon | |
15150 | call. */ | |
15151 | flag_move_loop_invariants = 0; | |
15152 | ||
08d0963a | 15153 | target_flags |= MASK_EXPLICIT_RELOCS; |
ab77a036 | 15154 | |
65239d20 RS |
15155 | /* Experiments suggest we get the best overall section-anchor |
15156 | results from using the range of an unextended LW or SW. Code | |
15157 | that makes heavy use of byte or short accesses can do better | |
15158 | with ranges of 0...31 and 0...63 respectively, but most code is | |
15159 | sensitive to the range of LW and SW instead. */ | |
ab77a036 RS |
15160 | targetm.min_anchor_offset = 0; |
15161 | targetm.max_anchor_offset = 127; | |
15162 | ||
2c5bfdf7 AN |
15163 | targetm.const_anchor = 0; |
15164 | ||
b53da244 AN |
15165 | /* MIPS16 has no BAL instruction. */ |
15166 | target_flags &= ~MASK_RELAX_PIC_CALLS; | |
15167 | ||
08d0963a RS |
15168 | if (flag_pic && !TARGET_OLDABI) |
15169 | sorry ("MIPS16 PIC for ABIs other than o32 and o64"); | |
15170 | ||
15171 | if (TARGET_XGOT) | |
15172 | sorry ("MIPS16 -mxgot code"); | |
d375fd5e RS |
15173 | |
15174 | if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI) | |
15175 | sorry ("hard-float MIPS16 code for ABIs other than o32 and o64"); | |
ab77a036 RS |
15176 | } |
15177 | else | |
15178 | { | |
65239d20 | 15179 | /* Switch to normal (non-MIPS16) mode. */ |
ab77a036 RS |
15180 | target_flags &= ~MASK_MIPS16; |
15181 | ||
ab77a036 RS |
15182 | /* Provide default values for align_* for 64-bit targets. */ |
15183 | if (TARGET_64BIT) | |
15184 | { | |
15185 | if (align_loops == 0) | |
15186 | align_loops = 8; | |
15187 | if (align_jumps == 0) | |
15188 | align_jumps = 8; | |
15189 | if (align_functions == 0) | |
15190 | align_functions = 8; | |
15191 | } | |
1823bf53 | 15192 | |
ab77a036 RS |
15193 | targetm.min_anchor_offset = -32768; |
15194 | targetm.max_anchor_offset = 32767; | |
2c5bfdf7 AN |
15195 | |
15196 | targetm.const_anchor = 0x8000; | |
ab77a036 | 15197 | } |
1823bf53 | 15198 | |
65239d20 | 15199 | /* (Re)initialize MIPS target internals for new ISA. */ |
ab77a036 | 15200 | mips_init_relocs (); |
1823bf53 | 15201 | |
60730ade | 15202 | if (was_mips16_p >= 0 || was_mips16_pch_p >= 0) |
ab77a036 RS |
15203 | /* Reinitialize target-dependent state. */ |
15204 | target_reinit (); | |
32041385 | 15205 | |
65239d20 | 15206 | was_mips16_p = mips16_p; |
60730ade | 15207 | was_mips16_pch_p = mips16_p; |
ab77a036 | 15208 | } |
1823bf53 | 15209 | |
ab77a036 RS |
15210 | /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current |
15211 | function should use the MIPS16 ISA and switch modes accordingly. */ | |
15212 | ||
15213 | static void | |
15214 | mips_set_current_function (tree fndecl) | |
1823bf53 | 15215 | { |
ab77a036 RS |
15216 | mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl)); |
15217 | } | |
15218 | \f | |
15219 | /* Allocate a chunk of memory for per-function machine-dependent data. */ | |
65239d20 | 15220 | |
ab77a036 RS |
15221 | static struct machine_function * |
15222 | mips_init_machine_status (void) | |
15223 | { | |
a9429e29 | 15224 | return ggc_alloc_cleared_machine_function (); |
ab77a036 | 15225 | } |
06a4ab70 | 15226 | |
ab77a036 RS |
15227 | /* Return the processor associated with the given ISA level, or null |
15228 | if the ISA isn't valid. */ | |
ff55fb9c | 15229 | |
ab77a036 RS |
15230 | static const struct mips_cpu_info * |
15231 | mips_cpu_info_from_isa (int isa) | |
ff55fb9c | 15232 | { |
ab77a036 | 15233 | unsigned int i; |
ff55fb9c | 15234 | |
ab77a036 RS |
15235 | for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++) |
15236 | if (mips_cpu_info_table[i].isa == isa) | |
15237 | return mips_cpu_info_table + i; | |
ff55fb9c | 15238 | |
65239d20 | 15239 | return NULL; |
ff55fb9c RS |
15240 | } |
15241 | ||
ab77a036 RS |
15242 | /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL |
15243 | with a final "000" replaced by "k". Ignore case. | |
ff55fb9c | 15244 | |
ab77a036 RS |
15245 | Note: this function is shared between GCC and GAS. */ |
15246 | ||
15247 | static bool | |
15248 | mips_strict_matching_cpu_name_p (const char *canonical, const char *given) | |
ff55fb9c | 15249 | { |
ab77a036 RS |
15250 | while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical)) |
15251 | given++, canonical++; | |
ff55fb9c | 15252 | |
ab77a036 RS |
15253 | return ((*given == 0 && *canonical == 0) |
15254 | || (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0)); | |
15255 | } | |
ff55fb9c | 15256 | |
ab77a036 RS |
15257 | /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied |
15258 | CPU name. We've traditionally allowed a lot of variation here. | |
15259 | ||
15260 | Note: this function is shared between GCC and GAS. */ | |
15261 | ||
15262 | static bool | |
15263 | mips_matching_cpu_name_p (const char *canonical, const char *given) | |
15264 | { | |
15265 | /* First see if the name matches exactly, or with a final "000" | |
15266 | turned into "k". */ | |
15267 | if (mips_strict_matching_cpu_name_p (canonical, given)) | |
15268 | return true; | |
15269 | ||
15270 | /* If not, try comparing based on numerical designation alone. | |
15271 | See if GIVEN is an unadorned number, or 'r' followed by a number. */ | |
15272 | if (TOLOWER (*given) == 'r') | |
15273 | given++; | |
15274 | if (!ISDIGIT (*given)) | |
15275 | return false; | |
15276 | ||
15277 | /* Skip over some well-known prefixes in the canonical name, | |
15278 | hoping to find a number there too. */ | |
15279 | if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r') | |
15280 | canonical += 2; | |
15281 | else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm') | |
15282 | canonical += 2; | |
15283 | else if (TOLOWER (canonical[0]) == 'r') | |
15284 | canonical += 1; | |
15285 | ||
15286 | return mips_strict_matching_cpu_name_p (canonical, given); | |
ff55fb9c RS |
15287 | } |
15288 | ||
ab77a036 RS |
15289 | /* Return the mips_cpu_info entry for the processor or ISA given |
15290 | by CPU_STRING. Return null if the string isn't recognized. | |
15291 | ||
15292 | A similar function exists in GAS. */ | |
15293 | ||
15294 | static const struct mips_cpu_info * | |
15295 | mips_parse_cpu (const char *cpu_string) | |
06a4ab70 | 15296 | { |
ab77a036 RS |
15297 | unsigned int i; |
15298 | const char *s; | |
06a4ab70 | 15299 | |
ab77a036 RS |
15300 | /* In the past, we allowed upper-case CPU names, but it doesn't |
15301 | work well with the multilib machinery. */ | |
15302 | for (s = cpu_string; *s != 0; s++) | |
15303 | if (ISUPPER (*s)) | |
15304 | { | |
65239d20 | 15305 | warning (0, "CPU names must be lower case"); |
ab77a036 RS |
15306 | break; |
15307 | } | |
1823bf53 | 15308 | |
ab77a036 RS |
15309 | /* 'from-abi' selects the most compatible architecture for the given |
15310 | ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the | |
15311 | EABIs, we have to decide whether we're using the 32-bit or 64-bit | |
65239d20 | 15312 | version. */ |
ab77a036 RS |
15313 | if (strcasecmp (cpu_string, "from-abi") == 0) |
15314 | return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1 | |
15315 | : ABI_NEEDS_64BIT_REGS ? 3 | |
15316 | : (TARGET_64BIT ? 3 : 1)); | |
15317 | ||
15318 | /* 'default' has traditionally been a no-op. Probably not very useful. */ | |
15319 | if (strcasecmp (cpu_string, "default") == 0) | |
65239d20 | 15320 | return NULL; |
ab77a036 RS |
15321 | |
15322 | for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++) | |
15323 | if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string)) | |
15324 | return mips_cpu_info_table + i; | |
15325 | ||
65239d20 | 15326 | return NULL; |
ab77a036 RS |
15327 | } |
15328 | ||
ab77a036 RS |
15329 | /* Set up globals to generate code for the ISA or processor |
15330 | described by INFO. */ | |
15331 | ||
15332 | static void | |
15333 | mips_set_architecture (const struct mips_cpu_info *info) | |
15334 | { | |
15335 | if (info != 0) | |
f9e4a411 | 15336 | { |
ab77a036 RS |
15337 | mips_arch_info = info; |
15338 | mips_arch = info->cpu; | |
15339 | mips_isa = info->isa; | |
f9e4a411 | 15340 | } |
ab77a036 | 15341 | } |
f9e4a411 | 15342 | |
ab77a036 RS |
15343 | /* Likewise for tuning. */ |
15344 | ||
15345 | static void | |
15346 | mips_set_tune (const struct mips_cpu_info *info) | |
15347 | { | |
15348 | if (info != 0) | |
1823bf53 | 15349 | { |
ab77a036 RS |
15350 | mips_tune_info = info; |
15351 | mips_tune = info->cpu; | |
1823bf53 | 15352 | } |
ab77a036 | 15353 | } |
ff55fb9c | 15354 | |
ab77a036 RS |
15355 | /* Implement TARGET_HANDLE_OPTION. */ |
15356 | ||
15357 | static bool | |
15358 | mips_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
15359 | { | |
15360 | switch (code) | |
4ca1f68f | 15361 | { |
ab77a036 RS |
15362 | case OPT_mabi_: |
15363 | if (strcmp (arg, "32") == 0) | |
15364 | mips_abi = ABI_32; | |
15365 | else if (strcmp (arg, "o64") == 0) | |
15366 | mips_abi = ABI_O64; | |
15367 | else if (strcmp (arg, "n32") == 0) | |
15368 | mips_abi = ABI_N32; | |
15369 | else if (strcmp (arg, "64") == 0) | |
15370 | mips_abi = ABI_64; | |
15371 | else if (strcmp (arg, "eabi") == 0) | |
15372 | mips_abi = ABI_EABI; | |
15373 | else | |
15374 | return false; | |
15375 | return true; | |
118ea793 | 15376 | |
ab77a036 RS |
15377 | case OPT_march_: |
15378 | case OPT_mtune_: | |
15379 | return mips_parse_cpu (arg) != 0; | |
06a4ab70 | 15380 | |
ab77a036 | 15381 | case OPT_mips: |
65239d20 RS |
15382 | mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL))); |
15383 | return mips_isa_option_info != 0; | |
4ca1f68f | 15384 | |
ab77a036 RS |
15385 | case OPT_mno_flush_func: |
15386 | mips_cache_flush_func = NULL; | |
15387 | return true; | |
06a4ab70 | 15388 | |
ab77a036 RS |
15389 | case OPT_mcode_readable_: |
15390 | if (strcmp (arg, "yes") == 0) | |
15391 | mips_code_readable = CODE_READABLE_YES; | |
15392 | else if (strcmp (arg, "pcrel") == 0) | |
15393 | mips_code_readable = CODE_READABLE_PCREL; | |
15394 | else if (strcmp (arg, "no") == 0) | |
15395 | mips_code_readable = CODE_READABLE_NO; | |
15396 | else | |
15397 | return false; | |
15398 | return true; | |
118ea793 | 15399 | |
4d210b07 RS |
15400 | case OPT_mr10k_cache_barrier_: |
15401 | if (strcmp (arg, "load-store") == 0) | |
15402 | mips_r10k_cache_barrier = R10K_CACHE_BARRIER_LOAD_STORE; | |
15403 | else if (strcmp (arg, "store") == 0) | |
15404 | mips_r10k_cache_barrier = R10K_CACHE_BARRIER_STORE; | |
15405 | else if (strcmp (arg, "none") == 0) | |
15406 | mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE; | |
15407 | else | |
15408 | return false; | |
15409 | return true; | |
15410 | ||
06a4ab70 | 15411 | default: |
ab77a036 | 15412 | return true; |
06a4ab70 | 15413 | } |
06a4ab70 CF |
15414 | } |
15415 | ||
65239d20 | 15416 | /* Implement OVERRIDE_OPTIONS. */ |
06a4ab70 CF |
15417 | |
15418 | void | |
65239d20 | 15419 | mips_override_options (void) |
06a4ab70 | 15420 | { |
65239d20 | 15421 | int i, start, regno, mode; |
06a4ab70 | 15422 | |
60730ade RS |
15423 | /* Process flags as though we were generating non-MIPS16 code. */ |
15424 | mips_base_mips16 = TARGET_MIPS16; | |
15425 | target_flags &= ~MASK_MIPS16; | |
15426 | ||
ab77a036 RS |
15427 | #ifdef SUBTARGET_OVERRIDE_OPTIONS |
15428 | SUBTARGET_OVERRIDE_OPTIONS; | |
15429 | #endif | |
06a4ab70 | 15430 | |
9f946bc1 RS |
15431 | /* -mno-float overrides -mhard-float and -msoft-float. */ |
15432 | if (TARGET_NO_FLOAT) | |
15433 | { | |
15434 | target_flags |= MASK_SOFT_FLOAT_ABI; | |
15435 | target_flags_explicit |= MASK_SOFT_FLOAT_ABI; | |
15436 | } | |
15437 | ||
65239d20 RS |
15438 | /* Set the small data limit. */ |
15439 | mips_small_data_threshold = (g_switch_set | |
15440 | ? g_switch_value | |
15441 | : MIPS_DEFAULT_GVALUE); | |
8f2e3902 | 15442 | |
ab77a036 RS |
15443 | /* The following code determines the architecture and register size. |
15444 | Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()). | |
15445 | The GAS and GCC code should be kept in sync as much as possible. */ | |
06a4ab70 | 15446 | |
ab77a036 RS |
15447 | if (mips_arch_string != 0) |
15448 | mips_set_architecture (mips_parse_cpu (mips_arch_string)); | |
06a4ab70 | 15449 | |
65239d20 | 15450 | if (mips_isa_option_info != 0) |
ab77a036 RS |
15451 | { |
15452 | if (mips_arch_info == 0) | |
65239d20 RS |
15453 | mips_set_architecture (mips_isa_option_info); |
15454 | else if (mips_arch_info->isa != mips_isa_option_info->isa) | |
15455 | error ("%<-%s%> conflicts with the other architecture options, " | |
ab77a036 | 15456 | "which specify a %s processor", |
65239d20 | 15457 | mips_isa_option_info->name, |
ab77a036 RS |
15458 | mips_cpu_info_from_isa (mips_arch_info->isa)->name); |
15459 | } | |
06a4ab70 | 15460 | |
ab77a036 RS |
15461 | if (mips_arch_info == 0) |
15462 | { | |
15463 | #ifdef MIPS_CPU_STRING_DEFAULT | |
15464 | mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT)); | |
15465 | #else | |
15466 | mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT)); | |
15467 | #endif | |
15468 | } | |
06a4ab70 | 15469 | |
ab77a036 | 15470 | if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS) |
65239d20 | 15471 | error ("%<-march=%s%> is not compatible with the selected ABI", |
ab77a036 | 15472 | mips_arch_info->name); |
06a4ab70 | 15473 | |
ab77a036 RS |
15474 | /* Optimize for mips_arch, unless -mtune selects a different processor. */ |
15475 | if (mips_tune_string != 0) | |
15476 | mips_set_tune (mips_parse_cpu (mips_tune_string)); | |
118ea793 | 15477 | |
ab77a036 RS |
15478 | if (mips_tune_info == 0) |
15479 | mips_set_tune (mips_arch_info); | |
118ea793 | 15480 | |
ab77a036 RS |
15481 | if ((target_flags_explicit & MASK_64BIT) != 0) |
15482 | { | |
15483 | /* The user specified the size of the integer registers. Make sure | |
15484 | it agrees with the ABI and ISA. */ | |
15485 | if (TARGET_64BIT && !ISA_HAS_64BIT_REGS) | |
65239d20 | 15486 | error ("%<-mgp64%> used with a 32-bit processor"); |
ab77a036 | 15487 | else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS) |
65239d20 | 15488 | error ("%<-mgp32%> used with a 64-bit ABI"); |
ab77a036 | 15489 | else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS) |
65239d20 | 15490 | error ("%<-mgp64%> used with a 32-bit ABI"); |
ab77a036 RS |
15491 | } |
15492 | else | |
15493 | { | |
15494 | /* Infer the integer register size from the ABI and processor. | |
15495 | Restrict ourselves to 32-bit registers if that's all the | |
15496 | processor has, or if the ABI cannot handle 64-bit registers. */ | |
15497 | if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS) | |
15498 | target_flags &= ~MASK_64BIT; | |
15499 | else | |
15500 | target_flags |= MASK_64BIT; | |
118ea793 CF |
15501 | } |
15502 | ||
ab77a036 | 15503 | if ((target_flags_explicit & MASK_FLOAT64) != 0) |
118ea793 | 15504 | { |
65239d20 | 15505 | if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64) |
ab77a036 | 15506 | error ("unsupported combination: %s", "-mfp64 -msingle-float"); |
65239d20 RS |
15507 | else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64) |
15508 | error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float"); | |
15509 | else if (!TARGET_64BIT && TARGET_FLOAT64) | |
15510 | { | |
15511 | if (!ISA_HAS_MXHC1) | |
15512 | error ("%<-mgp32%> and %<-mfp64%> can only be combined if" | |
15513 | " the target supports the mfhc1 and mthc1 instructions"); | |
15514 | else if (mips_abi != ABI_32) | |
15515 | error ("%<-mgp32%> and %<-mfp64%> can only be combined when using" | |
15516 | " the o32 ABI"); | |
15517 | } | |
ab77a036 RS |
15518 | } |
15519 | else | |
15520 | { | |
15521 | /* -msingle-float selects 32-bit float registers. Otherwise the | |
15522 | float registers should be the same size as the integer ones. */ | |
15523 | if (TARGET_64BIT && TARGET_DOUBLE_FLOAT) | |
15524 | target_flags |= MASK_FLOAT64; | |
15525 | else | |
15526 | target_flags &= ~MASK_FLOAT64; | |
15527 | } | |
118ea793 | 15528 | |
ab77a036 | 15529 | /* End of code shared with GAS. */ |
118ea793 | 15530 | |
65239d20 | 15531 | /* If no -mlong* option was given, infer it from the other options. */ |
ab77a036 RS |
15532 | if ((target_flags_explicit & MASK_LONG64) == 0) |
15533 | { | |
15534 | if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64) | |
15535 | target_flags |= MASK_LONG64; | |
15536 | else | |
15537 | target_flags &= ~MASK_LONG64; | |
15538 | } | |
118ea793 | 15539 | |
ab77a036 RS |
15540 | if (!TARGET_OLDABI) |
15541 | flag_pcc_struct_return = 0; | |
118ea793 | 15542 | |
65239d20 RS |
15543 | /* Decide which rtx_costs structure to use. */ |
15544 | if (optimize_size) | |
15545 | mips_cost = &mips_rtx_cost_optimize_size; | |
15546 | else | |
15547 | mips_cost = &mips_rtx_cost_data[mips_tune]; | |
15548 | ||
15549 | /* If the user hasn't specified a branch cost, use the processor's | |
15550 | default. */ | |
15551 | if (mips_branch_cost == 0) | |
15552 | mips_branch_cost = mips_cost->branch_cost; | |
15553 | ||
15554 | /* If neither -mbranch-likely nor -mno-branch-likely was given | |
15555 | on the command line, set MASK_BRANCHLIKELY based on the target | |
15556 | architecture and tuning flags. Annulled delay slots are a | |
15557 | size win, so we only consider the processor-specific tuning | |
15558 | for !optimize_size. */ | |
ab77a036 RS |
15559 | if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0) |
15560 | { | |
ab77a036 RS |
15561 | if (ISA_HAS_BRANCHLIKELY |
15562 | && (optimize_size | |
15563 | || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0)) | |
15564 | target_flags |= MASK_BRANCHLIKELY; | |
15565 | else | |
15566 | target_flags &= ~MASK_BRANCHLIKELY; | |
15567 | } | |
15568 | else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY) | |
15569 | warning (0, "the %qs architecture does not support branch-likely" | |
15570 | " instructions", mips_arch_info->name); | |
118ea793 | 15571 | |
ab77a036 RS |
15572 | /* The effect of -mabicalls isn't defined for the EABI. */ |
15573 | if (mips_abi == ABI_EABI && TARGET_ABICALLS) | |
15574 | { | |
15575 | error ("unsupported combination: %s", "-mabicalls -mabi=eabi"); | |
15576 | target_flags &= ~MASK_ABICALLS; | |
15577 | } | |
118ea793 | 15578 | |
e21d5757 | 15579 | if (TARGET_ABICALLS_PIC2) |
ab77a036 RS |
15580 | /* We need to set flag_pic for executables as well as DSOs |
15581 | because we may reference symbols that are not defined in | |
15582 | the final executable. (MIPS does not use things like | |
15583 | copy relocs, for example.) | |
118ea793 | 15584 | |
e21d5757 DJ |
15585 | There is a body of code that uses __PIC__ to distinguish |
15586 | between -mabicalls and -mno-abicalls code. The non-__PIC__ | |
15587 | variant is usually appropriate for TARGET_ABICALLS_PIC0, as | |
15588 | long as any indirect jumps use $25. */ | |
ab77a036 | 15589 | flag_pic = 1; |
118ea793 | 15590 | |
ab77a036 RS |
15591 | /* -mvr4130-align is a "speed over size" optimization: it usually produces |
15592 | faster code, but at the expense of more nops. Enable it at -O3 and | |
15593 | above. */ | |
15594 | if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0) | |
15595 | target_flags |= MASK_VR4130_ALIGN; | |
118ea793 | 15596 | |
ab77a036 RS |
15597 | /* Prefer a call to memcpy over inline code when optimizing for size, |
15598 | though see MOVE_RATIO in mips.h. */ | |
15599 | if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0) | |
15600 | target_flags |= MASK_MEMCPY; | |
118ea793 | 15601 | |
ab77a036 RS |
15602 | /* If we have a nonzero small-data limit, check that the -mgpopt |
15603 | setting is consistent with the other target flags. */ | |
65239d20 | 15604 | if (mips_small_data_threshold > 0) |
ab77a036 RS |
15605 | { |
15606 | if (!TARGET_GPOPT) | |
15607 | { | |
60730ade | 15608 | if (!TARGET_EXPLICIT_RELOCS) |
ab77a036 | 15609 | error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>"); |
118ea793 | 15610 | |
ab77a036 RS |
15611 | TARGET_LOCAL_SDATA = false; |
15612 | TARGET_EXTERN_SDATA = false; | |
15613 | } | |
15614 | else | |
15615 | { | |
15616 | if (TARGET_VXWORKS_RTP) | |
15617 | warning (0, "cannot use small-data accesses for %qs", "-mrtp"); | |
118ea793 | 15618 | |
ab77a036 RS |
15619 | if (TARGET_ABICALLS) |
15620 | warning (0, "cannot use small-data accesses for %qs", | |
15621 | "-mabicalls"); | |
15622 | } | |
15623 | } | |
118ea793 | 15624 | |
ab77a036 RS |
15625 | #ifdef MIPS_TFMODE_FORMAT |
15626 | REAL_MODE_FORMAT (TFmode) = &MIPS_TFMODE_FORMAT; | |
15627 | #endif | |
118ea793 | 15628 | |
ab77a036 RS |
15629 | /* Make sure that the user didn't turn off paired single support when |
15630 | MIPS-3D support is requested. */ | |
65239d20 RS |
15631 | if (TARGET_MIPS3D |
15632 | && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT) | |
ab77a036 | 15633 | && !TARGET_PAIRED_SINGLE_FLOAT) |
65239d20 | 15634 | error ("%<-mips3d%> requires %<-mpaired-single%>"); |
118ea793 | 15635 | |
ab77a036 RS |
15636 | /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */ |
15637 | if (TARGET_MIPS3D) | |
15638 | target_flags |= MASK_PAIRED_SINGLE_FLOAT; | |
118ea793 | 15639 | |
ab77a036 RS |
15640 | /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64 |
15641 | and TARGET_HARD_FLOAT_ABI are both true. */ | |
15642 | if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI)) | |
65239d20 RS |
15643 | error ("%qs must be used with %qs", |
15644 | TARGET_MIPS3D ? "-mips3d" : "-mpaired-single", | |
15645 | TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float"); | |
118ea793 | 15646 | |
ab77a036 RS |
15647 | /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is |
15648 | enabled. */ | |
e5a2b69d RS |
15649 | if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE) |
15650 | warning (0, "the %qs architecture does not support paired-single" | |
15651 | " instructions", mips_arch_info->name); | |
118ea793 | 15652 | |
4d210b07 RS |
15653 | if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE |
15654 | && !TARGET_CACHE_BUILTIN) | |
15655 | { | |
15656 | error ("%qs requires a target that provides the %qs instruction", | |
15657 | "-mr10k-cache-barrier", "cache"); | |
15658 | mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE; | |
15659 | } | |
15660 | ||
ab77a036 RS |
15661 | /* If TARGET_DSPR2, enable MASK_DSP. */ |
15662 | if (TARGET_DSPR2) | |
15663 | target_flags |= MASK_DSP; | |
118ea793 | 15664 | |
082d2ebb RS |
15665 | /* .eh_frame addresses should be the same width as a C pointer. |
15666 | Most MIPS ABIs support only one pointer size, so the assembler | |
15667 | will usually know exactly how big an .eh_frame address is. | |
15668 | ||
15669 | Unfortunately, this is not true of the 64-bit EABI. The ABI was | |
15670 | originally defined to use 64-bit pointers (i.e. it is LP64), and | |
15671 | this is still the default mode. However, we also support an n32-like | |
15672 | ILP32 mode, which is selected by -mlong32. The problem is that the | |
15673 | assembler has traditionally not had an -mlong option, so it has | |
15674 | traditionally not known whether we're using the ILP32 or LP64 form. | |
15675 | ||
15676 | As it happens, gas versions up to and including 2.19 use _32-bit_ | |
15677 | addresses for EABI64 .cfi_* directives. This is wrong for the | |
15678 | default LP64 mode, so we can't use the directives by default. | |
15679 | Moreover, since gas's current behavior is at odds with gcc's | |
15680 | default behavior, it seems unwise to rely on future versions | |
15681 | of gas behaving the same way. We therefore avoid using .cfi | |
15682 | directives for -mlong32 as well. */ | |
15683 | if (mips_abi == ABI_EABI && TARGET_64BIT) | |
15684 | flag_dwarf2_cfi_asm = 0; | |
15685 | ||
49576e25 RS |
15686 | /* .cfi_* directives generate a read-only section, so fall back on |
15687 | manual .eh_frame creation if we need the section to be writable. */ | |
15688 | if (TARGET_WRITABLE_EH_FRAME) | |
15689 | flag_dwarf2_cfi_asm = 0; | |
15690 | ||
07045266 | 15691 | mips_init_print_operand_punct (); |
118ea793 | 15692 | |
ab77a036 RS |
15693 | /* Set up array to map GCC register number to debug register number. |
15694 | Ignore the special purpose register numbers. */ | |
118ea793 | 15695 | |
ab77a036 RS |
15696 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
15697 | { | |
15698 | mips_dbx_regno[i] = INVALID_REGNUM; | |
15699 | if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i)) | |
15700 | mips_dwarf_regno[i] = i; | |
15701 | else | |
15702 | mips_dwarf_regno[i] = INVALID_REGNUM; | |
15703 | } | |
118ea793 | 15704 | |
ab77a036 RS |
15705 | start = GP_DBX_FIRST - GP_REG_FIRST; |
15706 | for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++) | |
15707 | mips_dbx_regno[i] = i + start; | |
118ea793 | 15708 | |
ab77a036 RS |
15709 | start = FP_DBX_FIRST - FP_REG_FIRST; |
15710 | for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++) | |
15711 | mips_dbx_regno[i] = i + start; | |
118ea793 | 15712 | |
65239d20 | 15713 | /* Accumulator debug registers use big-endian ordering. */ |
ab77a036 RS |
15714 | mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0; |
15715 | mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1; | |
15716 | mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0; | |
15717 | mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1; | |
15718 | for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2) | |
15719 | { | |
15720 | mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i; | |
15721 | mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1; | |
15722 | } | |
118ea793 | 15723 | |
5f5fe6d9 RS |
15724 | /* Set up mips_hard_regno_mode_ok. */ |
15725 | for (mode = 0; mode < MAX_MACHINE_MODE; mode++) | |
15726 | for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) | |
bbbbb16a ILT |
15727 | mips_hard_regno_mode_ok[mode][regno] |
15728 | = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode); | |
06a4ab70 | 15729 | |
ab77a036 RS |
15730 | /* Function to allocate machine-dependent function status. */ |
15731 | init_machine_status = &mips_init_machine_status; | |
4ca1f68f | 15732 | |
ab77a036 RS |
15733 | /* Default to working around R4000 errata only if the processor |
15734 | was selected explicitly. */ | |
15735 | if ((target_flags_explicit & MASK_FIX_R4000) == 0 | |
15736 | && mips_matching_cpu_name_p (mips_arch_info->name, "r4000")) | |
15737 | target_flags |= MASK_FIX_R4000; | |
4ca1f68f | 15738 | |
ab77a036 RS |
15739 | /* Default to working around R4400 errata only if the processor |
15740 | was selected explicitly. */ | |
15741 | if ((target_flags_explicit & MASK_FIX_R4400) == 0 | |
15742 | && mips_matching_cpu_name_p (mips_arch_info->name, "r4400")) | |
15743 | target_flags |= MASK_FIX_R4400; | |
4ca1f68f | 15744 | |
ee9a72e5 JK |
15745 | /* Default to working around R10000 errata only if the processor |
15746 | was selected explicitly. */ | |
15747 | if ((target_flags_explicit & MASK_FIX_R10000) == 0 | |
15748 | && mips_matching_cpu_name_p (mips_arch_info->name, "r10000")) | |
15749 | target_flags |= MASK_FIX_R10000; | |
15750 | ||
15751 | /* Make sure that branch-likely instructions available when using | |
15752 | -mfix-r10000. The instructions are not available if either: | |
15753 | ||
15754 | 1. -mno-branch-likely was passed. | |
15755 | 2. The selected ISA does not support branch-likely and | |
15756 | the command line does not include -mbranch-likely. */ | |
15757 | if (TARGET_FIX_R10000 | |
15758 | && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0 | |
15759 | ? !ISA_HAS_BRANCHLIKELY | |
15760 | : !TARGET_BRANCHLIKELY)) | |
15761 | sorry ("%qs requires branch-likely instructions", "-mfix-r10000"); | |
15762 | ||
b96c5923 DD |
15763 | if (TARGET_SYNCI && !ISA_HAS_SYNCI) |
15764 | { | |
15765 | warning (0, "the %qs architecture does not support the synci " | |
15766 | "instruction", mips_arch_info->name); | |
15767 | target_flags &= ~MASK_SYNCI; | |
15768 | } | |
15769 | ||
b53da244 AN |
15770 | /* Only optimize PIC indirect calls if they are actually required. */ |
15771 | if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS) | |
15772 | target_flags &= ~MASK_RELAX_PIC_CALLS; | |
15773 | ||
ab77a036 | 15774 | /* Save base state of options. */ |
ab77a036 | 15775 | mips_base_target_flags = target_flags; |
ab77a036 RS |
15776 | mips_base_schedule_insns = flag_schedule_insns; |
15777 | mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition; | |
15778 | mips_base_move_loop_invariants = flag_move_loop_invariants; | |
15779 | mips_base_align_loops = align_loops; | |
15780 | mips_base_align_jumps = align_jumps; | |
15781 | mips_base_align_functions = align_functions; | |
118ea793 | 15782 | |
60730ade RS |
15783 | /* Now select the ISA mode. |
15784 | ||
15785 | Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to | |
15786 | MIPS16 mode afterwards if need be. */ | |
15787 | mips_set_mips16_mode (false); | |
ab77a036 | 15788 | } |
4ca1f68f | 15789 | |
ab77a036 RS |
15790 | /* Swap the register information for registers I and I + 1, which |
15791 | currently have the wrong endianness. Note that the registers' | |
15792 | fixedness and call-clobberedness might have been set on the | |
15793 | command line. */ | |
4ca1f68f | 15794 | |
ab77a036 RS |
15795 | static void |
15796 | mips_swap_registers (unsigned int i) | |
15797 | { | |
15798 | int tmpi; | |
15799 | const char *tmps; | |
4ca1f68f | 15800 | |
ab77a036 RS |
15801 | #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi) |
15802 | #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps) | |
4ca1f68f | 15803 | |
ab77a036 RS |
15804 | SWAP_INT (fixed_regs[i], fixed_regs[i + 1]); |
15805 | SWAP_INT (call_used_regs[i], call_used_regs[i + 1]); | |
15806 | SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]); | |
15807 | SWAP_STRING (reg_names[i], reg_names[i + 1]); | |
15808 | ||
15809 | #undef SWAP_STRING | |
15810 | #undef SWAP_INT | |
06a4ab70 CF |
15811 | } |
15812 | ||
ab77a036 | 15813 | /* Implement CONDITIONAL_REGISTER_USAGE. */ |
06a4ab70 | 15814 | |
ab77a036 RS |
15815 | void |
15816 | mips_conditional_register_usage (void) | |
06a4ab70 | 15817 | { |
1e27273f CM |
15818 | |
15819 | if (ISA_HAS_DSP) | |
15820 | { | |
15821 | /* These DSP control register fields are global. */ | |
15822 | global_regs[CCDSP_PO_REGNUM] = 1; | |
15823 | global_regs[CCDSP_SC_REGNUM] = 1; | |
15824 | } | |
15825 | else | |
ab77a036 RS |
15826 | { |
15827 | int regno; | |
06a4ab70 | 15828 | |
ab77a036 RS |
15829 | for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++) |
15830 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
15831 | } | |
15832 | if (!TARGET_HARD_FLOAT) | |
15833 | { | |
15834 | int regno; | |
06a4ab70 | 15835 | |
ab77a036 RS |
15836 | for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) |
15837 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
15838 | for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) | |
15839 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
15840 | } | |
15841 | else if (! ISA_HAS_8CC) | |
ff55fb9c | 15842 | { |
ab77a036 RS |
15843 | int regno; |
15844 | ||
65239d20 RS |
15845 | /* We only have a single condition-code register. We implement |
15846 | this by fixing all the condition-code registers and generating | |
15847 | RTL that refers directly to ST_REG_FIRST. */ | |
ab77a036 RS |
15848 | for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) |
15849 | fixed_regs[regno] = call_used_regs[regno] = 1; | |
ff55fb9c | 15850 | } |
65239d20 | 15851 | /* In MIPS16 mode, we permit the $t temporary registers to be used |
ab77a036 | 15852 | for reload. We prohibit the unused $s registers, since they |
65239d20 | 15853 | are call-saved, and saving them via a MIPS16 register would |
ab77a036 RS |
15854 | probably waste more time than just reloading the value. */ |
15855 | if (TARGET_MIPS16) | |
ff55fb9c | 15856 | { |
ab77a036 RS |
15857 | fixed_regs[18] = call_used_regs[18] = 1; |
15858 | fixed_regs[19] = call_used_regs[19] = 1; | |
15859 | fixed_regs[20] = call_used_regs[20] = 1; | |
15860 | fixed_regs[21] = call_used_regs[21] = 1; | |
15861 | fixed_regs[22] = call_used_regs[22] = 1; | |
15862 | fixed_regs[23] = call_used_regs[23] = 1; | |
15863 | fixed_regs[26] = call_used_regs[26] = 1; | |
15864 | fixed_regs[27] = call_used_regs[27] = 1; | |
15865 | fixed_regs[30] = call_used_regs[30] = 1; | |
15866 | } | |
65239d20 | 15867 | /* $f20-$f23 are call-clobbered for n64. */ |
ab77a036 RS |
15868 | if (mips_abi == ABI_64) |
15869 | { | |
15870 | int regno; | |
15871 | for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++) | |
15872 | call_really_used_regs[regno] = call_used_regs[regno] = 1; | |
15873 | } | |
65239d20 RS |
15874 | /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered |
15875 | for n32. */ | |
ab77a036 RS |
15876 | if (mips_abi == ABI_N32) |
15877 | { | |
15878 | int regno; | |
15879 | for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2) | |
15880 | call_really_used_regs[regno] = call_used_regs[regno] = 1; | |
15881 | } | |
15882 | /* Make sure that double-register accumulator values are correctly | |
15883 | ordered for the current endianness. */ | |
15884 | if (TARGET_LITTLE_ENDIAN) | |
15885 | { | |
65239d20 RS |
15886 | unsigned int regno; |
15887 | ||
ab77a036 RS |
15888 | mips_swap_registers (MD_REG_FIRST); |
15889 | for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2) | |
15890 | mips_swap_registers (regno); | |
ff55fb9c | 15891 | } |
ff55fb9c | 15892 | } |
06a4ab70 | 15893 | |
93581857 MS |
15894 | /* Initialize vector TARGET to VALS. */ |
15895 | ||
15896 | void | |
15897 | mips_expand_vector_init (rtx target, rtx vals) | |
15898 | { | |
15899 | enum machine_mode mode; | |
15900 | enum machine_mode inner; | |
15901 | unsigned int i, n_elts; | |
15902 | rtx mem; | |
15903 | ||
15904 | mode = GET_MODE (target); | |
15905 | inner = GET_MODE_INNER (mode); | |
15906 | n_elts = GET_MODE_NUNITS (mode); | |
15907 | ||
15908 | gcc_assert (VECTOR_MODE_P (mode)); | |
15909 | ||
15910 | mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0); | |
15911 | for (i = 0; i < n_elts; i++) | |
15912 | emit_move_insn (adjust_address_nv (mem, inner, i * GET_MODE_SIZE (inner)), | |
15913 | XVECEXP (vals, 0, i)); | |
15914 | ||
15915 | emit_move_insn (target, mem); | |
15916 | } | |
15917 | ||
65239d20 RS |
15918 | /* When generating MIPS16 code, we want to allocate $24 (T_REG) before |
15919 | other registers for instructions for which it is possible. This | |
15920 | encourages the compiler to use CMP in cases where an XOR would | |
15921 | require some register shuffling. */ | |
a8c1d5f8 | 15922 | |
ab77a036 RS |
15923 | void |
15924 | mips_order_regs_for_local_alloc (void) | |
a8c1d5f8 | 15925 | { |
65239d20 | 15926 | int i; |
a8c1d5f8 | 15927 | |
ab77a036 RS |
15928 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) |
15929 | reg_alloc_order[i] = i; | |
a8c1d5f8 | 15930 | |
ab77a036 RS |
15931 | if (TARGET_MIPS16) |
15932 | { | |
15933 | /* It really doesn't matter where we put register 0, since it is | |
15934 | a fixed register anyhow. */ | |
15935 | reg_alloc_order[0] = 24; | |
15936 | reg_alloc_order[24] = 0; | |
15937 | } | |
a8c1d5f8 | 15938 | } |
e19da24c | 15939 | |
0c433c31 RS |
15940 | /* Implement EH_USES. */ |
15941 | ||
15942 | bool | |
15943 | mips_eh_uses (unsigned int regno) | |
15944 | { | |
15945 | if (reload_completed && !TARGET_ABSOLUTE_JUMPS) | |
15946 | { | |
15947 | /* We need to force certain registers to be live in order to handle | |
15948 | PIC long branches correctly. See mips_must_initialize_gp_p for | |
15949 | details. */ | |
15950 | if (mips_cfun_has_cprestore_slot_p ()) | |
15951 | { | |
15952 | if (regno == CPRESTORE_SLOT_REGNUM) | |
15953 | return true; | |
15954 | } | |
15955 | else | |
15956 | { | |
15957 | if (cfun->machine->global_pointer == regno) | |
15958 | return true; | |
15959 | } | |
15960 | } | |
15961 | ||
15962 | return false; | |
15963 | } | |
15964 | ||
e19da24c CF |
15965 | /* Implement EPILOGUE_USES. */ |
15966 | ||
15967 | bool | |
15968 | mips_epilogue_uses (unsigned int regno) | |
15969 | { | |
15970 | /* Say that the epilogue uses the return address register. Note that | |
15971 | in the case of sibcalls, the values "used by the epilogue" are | |
15972 | considered live at the start of the called function. */ | |
293593b1 | 15973 | if (regno == RETURN_ADDR_REGNUM) |
e19da24c CF |
15974 | return true; |
15975 | ||
15976 | /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM. | |
15977 | See the comment above load_call<mode> for details. */ | |
15978 | if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM) | |
15979 | return true; | |
15980 | ||
15981 | /* An interrupt handler must preserve some registers that are | |
15982 | ordinarily call-clobbered. */ | |
15983 | if (cfun->machine->interrupt_handler_p | |
15984 | && mips_interrupt_extra_call_saved_reg_p (regno)) | |
15985 | return true; | |
15986 | ||
15987 | return false; | |
15988 | } | |
1afc5373 CF |
15989 | |
15990 | /* A for_each_rtx callback. Stop the search if *X is an AT register. */ | |
15991 | ||
15992 | static int | |
15993 | mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED) | |
15994 | { | |
47ac44d6 | 15995 | return REG_P (*x) && REGNO (*x) == AT_REGNUM; |
1afc5373 CF |
15996 | } |
15997 | ||
cf5fb4b0 RS |
15998 | /* Return true if INSN needs to be wrapped in ".set noat". |
15999 | INSN has NOPERANDS operands, stored in OPVEC. */ | |
1afc5373 | 16000 | |
cf5fb4b0 RS |
16001 | static bool |
16002 | mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands) | |
1afc5373 CF |
16003 | { |
16004 | int i; | |
16005 | ||
1afc5373 CF |
16006 | if (recog_memoized (insn) >= 0) |
16007 | for (i = 0; i < noperands; i++) | |
16008 | if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL)) | |
cf5fb4b0 RS |
16009 | return true; |
16010 | return false; | |
16011 | } | |
16012 | ||
16013 | /* Implement FINAL_PRESCAN_INSN. */ | |
16014 | ||
16015 | void | |
16016 | mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands) | |
16017 | { | |
16018 | if (mips_need_noat_wrapper_p (insn, opvec, noperands)) | |
16019 | mips_push_asm_switch (&mips_noat); | |
1afc5373 CF |
16020 | } |
16021 | ||
16022 | /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */ | |
16023 | ||
0e097268 | 16024 | static void |
cf5fb4b0 RS |
16025 | mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn, |
16026 | rtx *opvec, int noperands) | |
1afc5373 | 16027 | { |
cf5fb4b0 RS |
16028 | if (mips_need_noat_wrapper_p (insn, opvec, noperands)) |
16029 | mips_pop_asm_switch (&mips_noat); | |
1afc5373 | 16030 | } |
a3c7bb26 AN |
16031 | |
16032 | /* Return the function that is used to expand the <u>mulsidi3 pattern. | |
16033 | EXT_CODE is the code of the extension used. Return NULL if widening | |
16034 | multiplication shouldn't be used. */ | |
16035 | ||
16036 | mulsidi3_gen_fn | |
16037 | mips_mulsidi3_gen_fn (enum rtx_code ext_code) | |
16038 | { | |
16039 | bool signed_p; | |
16040 | ||
16041 | signed_p = ext_code == SIGN_EXTEND; | |
16042 | if (TARGET_64BIT) | |
16043 | { | |
16044 | /* Don't use widening multiplication with MULT when we have DMUL. Even | |
16045 | with the extension of its input operands DMUL is faster. Note that | |
16046 | the extension is not needed for signed multiplication. In order to | |
16047 | ensure that we always remove the redundant sign-extension in this | |
16048 | case we still expand mulsidi3 for DMUL. */ | |
16049 | if (ISA_HAS_DMUL3) | |
16050 | return signed_p ? gen_mulsidi3_64bit_dmul : NULL; | |
16051 | if (TARGET_FIX_R4000) | |
16052 | return NULL; | |
16053 | return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit; | |
16054 | } | |
16055 | else | |
16056 | { | |
16057 | if (TARGET_FIX_R4000) | |
16058 | return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000; | |
16059 | if (ISA_HAS_DSPR2) | |
16060 | return signed_p ? gen_mips_mult : gen_mips_multu; | |
16061 | return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit; | |
16062 | } | |
16063 | } | |
a1d29c8c | 16064 | \f |
c640a3bd RS |
16065 | /* Return the size in bytes of the trampoline code, padded to |
16066 | TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target | |
16067 | function address immediately follow. */ | |
a1d29c8c | 16068 | |
c640a3bd RS |
16069 | int |
16070 | mips_trampoline_code_size (void) | |
16071 | { | |
16072 | if (TARGET_USE_PIC_FN_ADDR_REG) | |
16073 | return 4 * 4; | |
16074 | else if (ptr_mode == DImode) | |
16075 | return 8 * 4; | |
16076 | else if (ISA_HAS_LOAD_DELAY) | |
16077 | return 6 * 4; | |
a1d29c8c | 16078 | else |
c640a3bd | 16079 | return 4 * 4; |
a1d29c8c RH |
16080 | } |
16081 | ||
16082 | /* Implement TARGET_TRAMPOLINE_INIT. */ | |
16083 | ||
16084 | static void | |
16085 | mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) | |
16086 | { | |
c640a3bd RS |
16087 | rtx addr, end_addr, high, low, opcode, mem; |
16088 | rtx trampoline[8]; | |
16089 | unsigned int i, j; | |
16090 | HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset; | |
16091 | ||
16092 | /* Work out the offsets of the pointers from the start of the | |
16093 | trampoline code. */ | |
16094 | end_addr_offset = mips_trampoline_code_size (); | |
16095 | static_chain_offset = end_addr_offset; | |
16096 | target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); | |
a1d29c8c | 16097 | |
c640a3bd RS |
16098 | /* Get pointers to the beginning and end of the code block. */ |
16099 | addr = force_reg (Pmode, XEXP (m_tramp, 0)); | |
16100 | end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset)); | |
a1d29c8c | 16101 | |
c640a3bd | 16102 | #define OP(X) gen_int_mode (X, SImode) |
a1d29c8c | 16103 | |
c640a3bd RS |
16104 | /* Build up the code in TRAMPOLINE. */ |
16105 | i = 0; | |
16106 | if (TARGET_USE_PIC_FN_ADDR_REG) | |
16107 | { | |
16108 | /* $25 contains the address of the trampoline. Emit code of the form: | |
16109 | ||
16110 | l[wd] $1, target_function_offset($25) | |
16111 | l[wd] $static_chain, static_chain_offset($25) | |
16112 | jr $1 | |
16113 | move $25,$1. */ | |
16114 | trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM, | |
16115 | target_function_offset, | |
16116 | PIC_FUNCTION_ADDR_REGNUM)); | |
16117 | trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
16118 | static_chain_offset, | |
16119 | PIC_FUNCTION_ADDR_REGNUM)); | |
16120 | trampoline[i++] = OP (MIPS_JR (AT_REGNUM)); | |
16121 | trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM)); | |
16122 | } | |
16123 | else if (ptr_mode == DImode) | |
16124 | { | |
16125 | /* It's too cumbersome to create the full 64-bit address, so let's | |
16126 | instead use: | |
16127 | ||
16128 | move $1, $31 | |
16129 | bal 1f | |
16130 | nop | |
16131 | 1: l[wd] $25, target_function_offset - 12($31) | |
16132 | l[wd] $static_chain, static_chain_offset - 12($31) | |
16133 | jr $25 | |
16134 | move $31, $1 | |
16135 | ||
16136 | where 12 is the offset of "1:" from the start of the code block. */ | |
16137 | trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM)); | |
16138 | trampoline[i++] = OP (MIPS_BAL (1)); | |
16139 | trampoline[i++] = OP (MIPS_NOP); | |
16140 | trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM, | |
16141 | target_function_offset - 12, | |
16142 | RETURN_ADDR_REGNUM)); | |
16143 | trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
16144 | static_chain_offset - 12, | |
16145 | RETURN_ADDR_REGNUM)); | |
16146 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
16147 | trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM)); | |
16148 | } | |
16149 | else | |
16150 | { | |
16151 | /* If the target has load delays, emit: | |
16152 | ||
16153 | lui $1, %hi(end_addr) | |
16154 | lw $25, %lo(end_addr + ...)($1) | |
16155 | lw $static_chain, %lo(end_addr + ...)($1) | |
16156 | jr $25 | |
16157 | nop | |
16158 | ||
16159 | Otherwise emit: | |
16160 | ||
16161 | lui $1, %hi(end_addr) | |
16162 | lw $25, %lo(end_addr + ...)($1) | |
16163 | jr $25 | |
16164 | lw $static_chain, %lo(end_addr + ...)($1). */ | |
16165 | ||
16166 | /* Split END_ADDR into %hi and %lo values. Trampolines are aligned | |
16167 | to 64 bits, so the %lo value will have the bottom 3 bits clear. */ | |
16168 | high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000), | |
16169 | NULL, false, OPTAB_WIDEN); | |
16170 | high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16), | |
16171 | NULL, false, OPTAB_WIDEN); | |
16172 | low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true); | |
16173 | ||
16174 | /* Emit the LUI. */ | |
16175 | opcode = OP (MIPS_LUI (AT_REGNUM, 0)); | |
16176 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high, | |
16177 | NULL, false, OPTAB_WIDEN); | |
16178 | ||
16179 | /* Emit the load of the target function. */ | |
16180 | opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM, | |
16181 | target_function_offset - end_addr_offset, | |
16182 | AT_REGNUM)); | |
16183 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low, | |
16184 | NULL, false, OPTAB_WIDEN); | |
16185 | ||
16186 | /* Emit the JR here, if we can. */ | |
16187 | if (!ISA_HAS_LOAD_DELAY) | |
16188 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
16189 | ||
16190 | /* Emit the load of the static chain register. */ | |
16191 | opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM, | |
16192 | static_chain_offset - end_addr_offset, | |
16193 | AT_REGNUM)); | |
16194 | trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low, | |
16195 | NULL, false, OPTAB_WIDEN); | |
16196 | ||
16197 | /* Emit the JR, if we couldn't above. */ | |
16198 | if (ISA_HAS_LOAD_DELAY) | |
16199 | { | |
16200 | trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM)); | |
16201 | trampoline[i++] = OP (MIPS_NOP); | |
16202 | } | |
16203 | } | |
16204 | ||
16205 | #undef OP | |
16206 | ||
16207 | /* Copy the trampoline code. Leave any padding uninitialized. */ | |
16208 | for (j = 0; j < i; j++) | |
16209 | { | |
16210 | mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode)); | |
16211 | mips_emit_move (mem, trampoline[j]); | |
16212 | } | |
16213 | ||
16214 | /* Set up the static chain pointer field. */ | |
16215 | mem = adjust_address (m_tramp, ptr_mode, static_chain_offset); | |
16216 | mips_emit_move (mem, chain_value); | |
16217 | ||
16218 | /* Set up the target function field. */ | |
16219 | mem = adjust_address (m_tramp, ptr_mode, target_function_offset); | |
16220 | mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0)); | |
16221 | ||
16222 | /* Flush the code part of the trampoline. */ | |
a1d29c8c RH |
16223 | emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE))); |
16224 | emit_insn (gen_clear_cache (addr, end_addr)); | |
16225 | } | |
c376dbfb DD |
16226 | |
16227 | /* Implement FUNCTION_PROFILER. */ | |
16228 | ||
16229 | void mips_function_profiler (FILE *file) | |
16230 | { | |
16231 | if (TARGET_MIPS16) | |
16232 | sorry ("mips16 function profiling"); | |
16233 | if (TARGET_LONG_CALLS) | |
16234 | { | |
16235 | /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */ | |
16236 | if (Pmode == DImode) | |
16237 | fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]); | |
16238 | else | |
16239 | fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]); | |
16240 | } | |
16241 | mips_push_asm_switch (&mips_noat); | |
16242 | fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n", | |
16243 | reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]); | |
16244 | /* _mcount treats $2 as the static chain register. */ | |
16245 | if (cfun->static_chain_decl != NULL) | |
16246 | fprintf (file, "\tmove\t%s,%s\n", reg_names[2], | |
16247 | reg_names[STATIC_CHAIN_REGNUM]); | |
16248 | if (TARGET_MCOUNT_RA_ADDRESS) | |
16249 | { | |
16250 | /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the | |
16251 | ra save location. */ | |
16252 | if (cfun->machine->frame.ra_fp_offset == 0) | |
16253 | /* ra not saved, pass zero. */ | |
16254 | fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]); | |
16255 | else | |
16256 | fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n", | |
16257 | Pmode == DImode ? "dla" : "la", reg_names[12], | |
16258 | cfun->machine->frame.ra_fp_offset, | |
16259 | reg_names[STACK_POINTER_REGNUM]); | |
16260 | } | |
16261 | if (!TARGET_NEWABI) | |
16262 | fprintf (file, | |
16263 | "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", | |
16264 | TARGET_64BIT ? "dsubu" : "subu", | |
16265 | reg_names[STACK_POINTER_REGNUM], | |
16266 | reg_names[STACK_POINTER_REGNUM], | |
16267 | Pmode == DImode ? 16 : 8); | |
16268 | ||
16269 | if (TARGET_LONG_CALLS) | |
16270 | fprintf (file, "\tjalr\t%s\n", reg_names[3]); | |
16271 | else | |
16272 | fprintf (file, "\tjal\t_mcount\n"); | |
16273 | mips_pop_asm_switch (&mips_noat); | |
16274 | /* _mcount treats $2 as the static chain register. */ | |
16275 | if (cfun->static_chain_decl != NULL) | |
16276 | fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], | |
16277 | reg_names[2]); | |
16278 | } | |
ab77a036 RS |
16279 | \f |
16280 | /* Initialize the GCC target structure. */ | |
16281 | #undef TARGET_ASM_ALIGNED_HI_OP | |
16282 | #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" | |
16283 | #undef TARGET_ASM_ALIGNED_SI_OP | |
16284 | #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" | |
16285 | #undef TARGET_ASM_ALIGNED_DI_OP | |
16286 | #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" | |
a8c1d5f8 | 16287 | |
506d7b68 PB |
16288 | #undef TARGET_LEGITIMIZE_ADDRESS |
16289 | #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address | |
16290 | ||
ab77a036 RS |
16291 | #undef TARGET_ASM_FUNCTION_PROLOGUE |
16292 | #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue | |
16293 | #undef TARGET_ASM_FUNCTION_EPILOGUE | |
16294 | #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue | |
16295 | #undef TARGET_ASM_SELECT_RTX_SECTION | |
16296 | #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section | |
16297 | #undef TARGET_ASM_FUNCTION_RODATA_SECTION | |
16298 | #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section | |
4ca1f68f | 16299 | |
ab77a036 RS |
16300 | #undef TARGET_SCHED_INIT |
16301 | #define TARGET_SCHED_INIT mips_sched_init | |
16302 | #undef TARGET_SCHED_REORDER | |
16303 | #define TARGET_SCHED_REORDER mips_sched_reorder | |
16304 | #undef TARGET_SCHED_REORDER2 | |
16305 | #define TARGET_SCHED_REORDER2 mips_sched_reorder | |
16306 | #undef TARGET_SCHED_VARIABLE_ISSUE | |
16307 | #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue | |
16308 | #undef TARGET_SCHED_ADJUST_COST | |
16309 | #define TARGET_SCHED_ADJUST_COST mips_adjust_cost | |
16310 | #undef TARGET_SCHED_ISSUE_RATE | |
16311 | #define TARGET_SCHED_ISSUE_RATE mips_issue_rate | |
58684fa0 MK |
16312 | #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN |
16313 | #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn | |
16314 | #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE | |
16315 | #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle | |
ab77a036 RS |
16316 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD |
16317 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ | |
16318 | mips_multipass_dfa_lookahead | |
e472d6bf | 16319 | #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P |
a1c4f19f AP |
16320 | #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ |
16321 | mips_small_register_classes_for_mode_p | |
4ca1f68f | 16322 | |
ab77a036 RS |
16323 | #undef TARGET_DEFAULT_TARGET_FLAGS |
16324 | #define TARGET_DEFAULT_TARGET_FLAGS \ | |
16325 | (TARGET_DEFAULT \ | |
16326 | | TARGET_CPU_DEFAULT \ | |
16327 | | TARGET_ENDIAN_DEFAULT \ | |
16328 | | TARGET_FP_EXCEPTIONS_DEFAULT \ | |
16329 | | MASK_CHECK_ZERO_DIV \ | |
16330 | | MASK_FUSED_MADD) | |
16331 | #undef TARGET_HANDLE_OPTION | |
16332 | #define TARGET_HANDLE_OPTION mips_handle_option | |
06a4ab70 | 16333 | |
ab77a036 RS |
16334 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
16335 | #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall | |
4ca1f68f | 16336 | |
ab77a036 RS |
16337 | #undef TARGET_INSERT_ATTRIBUTES |
16338 | #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes | |
16339 | #undef TARGET_MERGE_DECL_ATTRIBUTES | |
16340 | #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes | |
16341 | #undef TARGET_SET_CURRENT_FUNCTION | |
16342 | #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function | |
06a4ab70 | 16343 | |
ab77a036 RS |
16344 | #undef TARGET_VALID_POINTER_MODE |
16345 | #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode | |
16346 | #undef TARGET_RTX_COSTS | |
16347 | #define TARGET_RTX_COSTS mips_rtx_costs | |
16348 | #undef TARGET_ADDRESS_COST | |
16349 | #define TARGET_ADDRESS_COST mips_address_cost | |
06a4ab70 | 16350 | |
ab77a036 RS |
16351 | #undef TARGET_IN_SMALL_DATA_P |
16352 | #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p | |
118ea793 | 16353 | |
ab77a036 RS |
16354 | #undef TARGET_MACHINE_DEPENDENT_REORG |
16355 | #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg | |
118ea793 | 16356 | |
ab77a036 RS |
16357 | #undef TARGET_ASM_FILE_START |
16358 | #define TARGET_ASM_FILE_START mips_file_start | |
16359 | #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE | |
16360 | #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true | |
118ea793 | 16361 | |
ab77a036 RS |
16362 | #undef TARGET_INIT_LIBFUNCS |
16363 | #define TARGET_INIT_LIBFUNCS mips_init_libfuncs | |
118ea793 | 16364 | |
ab77a036 RS |
16365 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
16366 | #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list | |
d7bd8aeb JJ |
16367 | #undef TARGET_EXPAND_BUILTIN_VA_START |
16368 | #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start | |
ab77a036 RS |
16369 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
16370 | #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr | |
118ea793 | 16371 | |
cde0f3fd PB |
16372 | #undef TARGET_PROMOTE_FUNCTION_MODE |
16373 | #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote | |
ab77a036 RS |
16374 | #undef TARGET_PROMOTE_PROTOTYPES |
16375 | #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true | |
118ea793 | 16376 | |
ab77a036 RS |
16377 | #undef TARGET_RETURN_IN_MEMORY |
16378 | #define TARGET_RETURN_IN_MEMORY mips_return_in_memory | |
16379 | #undef TARGET_RETURN_IN_MSB | |
16380 | #define TARGET_RETURN_IN_MSB mips_return_in_msb | |
4dbdb061 | 16381 | |
ab77a036 RS |
16382 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
16383 | #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk | |
16384 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
16385 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true | |
4dbdb061 | 16386 | |
6e9e0126 NF |
16387 | #undef TARGET_PRINT_OPERAND |
16388 | #define TARGET_PRINT_OPERAND mips_print_operand | |
16389 | #undef TARGET_PRINT_OPERAND_ADDRESS | |
16390 | #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address | |
16391 | #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P | |
16392 | #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p | |
16393 | ||
ab77a036 RS |
16394 | #undef TARGET_SETUP_INCOMING_VARARGS |
16395 | #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs | |
16396 | #undef TARGET_STRICT_ARGUMENT_NAMING | |
16397 | #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming | |
16398 | #undef TARGET_MUST_PASS_IN_STACK | |
16399 | #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size | |
16400 | #undef TARGET_PASS_BY_REFERENCE | |
16401 | #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference | |
16402 | #undef TARGET_CALLEE_COPIES | |
16403 | #define TARGET_CALLEE_COPIES mips_callee_copies | |
16404 | #undef TARGET_ARG_PARTIAL_BYTES | |
16405 | #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes | |
cd3a59b3 | 16406 | |
ab77a036 RS |
16407 | #undef TARGET_MODE_REP_EXTENDED |
16408 | #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended | |
912f2dac | 16409 | |
ab77a036 RS |
16410 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
16411 | #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p | |
912f2dac | 16412 | |
ab77a036 RS |
16413 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
16414 | #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p | |
912f2dac | 16415 | |
ab77a036 RS |
16416 | #undef TARGET_INIT_BUILTINS |
16417 | #define TARGET_INIT_BUILTINS mips_init_builtins | |
16418 | #undef TARGET_EXPAND_BUILTIN | |
16419 | #define TARGET_EXPAND_BUILTIN mips_expand_builtin | |
b12cbf2c | 16420 | |
ab77a036 RS |
16421 | #undef TARGET_HAVE_TLS |
16422 | #define TARGET_HAVE_TLS HAVE_AS_TLS | |
b12cbf2c | 16423 | |
ab77a036 RS |
16424 | #undef TARGET_CANNOT_FORCE_CONST_MEM |
16425 | #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem | |
a44380d2 | 16426 | |
ab77a036 RS |
16427 | #undef TARGET_ENCODE_SECTION_INFO |
16428 | #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info | |
a44380d2 | 16429 | |
ab77a036 RS |
16430 | #undef TARGET_ATTRIBUTE_TABLE |
16431 | #define TARGET_ATTRIBUTE_TABLE mips_attribute_table | |
16432 | /* All our function attributes are related to how out-of-line copies should | |
16433 | be compiled or called. They don't in themselves prevent inlining. */ | |
16434 | #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P | |
16435 | #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true | |
a44380d2 | 16436 | |
ab77a036 RS |
16437 | #undef TARGET_EXTRA_LIVE_ON_ENTRY |
16438 | #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry | |
076a5ce6 | 16439 | |
ab77a036 RS |
16440 | #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P |
16441 | #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p | |
16442 | #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P | |
16443 | #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p | |
076a5ce6 | 16444 | |
ab77a036 RS |
16445 | #undef TARGET_COMP_TYPE_ATTRIBUTES |
16446 | #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes | |
076a5ce6 | 16447 | |
ab77a036 RS |
16448 | #ifdef HAVE_AS_DTPRELWORD |
16449 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
16450 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel | |
16451 | #endif | |
16452 | #undef TARGET_DWARF_REGISTER_SPAN | |
16453 | #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span | |
076a5ce6 | 16454 | |
5c0a2e3a RS |
16455 | #undef TARGET_IRA_COVER_CLASSES |
16456 | #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes | |
16457 | ||
1afc5373 CF |
16458 | #undef TARGET_ASM_FINAL_POSTSCAN_INSN |
16459 | #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn | |
16460 | ||
c6c3dba9 PB |
16461 | #undef TARGET_LEGITIMATE_ADDRESS_P |
16462 | #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p | |
16463 | ||
b52b1749 AS |
16464 | #undef TARGET_FRAME_POINTER_REQUIRED |
16465 | #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required | |
16466 | ||
7b5cbb57 AS |
16467 | #undef TARGET_CAN_ELIMINATE |
16468 | #define TARGET_CAN_ELIMINATE mips_can_eliminate | |
16469 | ||
a1d29c8c RH |
16470 | #undef TARGET_TRAMPOLINE_INIT |
16471 | #define TARGET_TRAMPOLINE_INIT mips_trampoline_init | |
16472 | ||
ab77a036 | 16473 | struct gcc_target targetm = TARGET_INITIALIZER; |
a44380d2 | 16474 | \f |
e2500fed | 16475 | #include "gt-mips.h" |