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e75b25e7 | 1 | /* Definitions of target machine for GNU compiler. MIPS version. |
7adcbafe | 2 | Copyright (C) 1989-2022 Free Software Foundation, Inc. |
ae3e1bb4 RK |
3 | Contributed by A. Lichnewsky (lich@inria.inria.fr). |
4 | Changed by Michael Meissner (meissner@osf.org). | |
85f65093 | 5 | 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and |
ae3e1bb4 | 6 | Brendan Eich (brendan@microunity.com). |
e75b25e7 | 7 | |
7ec022b2 | 8 | This file is part of GCC. |
e75b25e7 | 9 | |
7ec022b2 | 10 | GCC is free software; you can redistribute it and/or modify |
e75b25e7 | 11 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 12 | the Free Software Foundation; either version 3, or (at your option) |
e75b25e7 MM |
13 | any later version. |
14 | ||
7ec022b2 | 15 | GCC is distributed in the hope that it will be useful, |
e75b25e7 MM |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
e75b25e7 MM |
23 | |
24 | ||
8cb6400c RS |
25 | #include "config/vxworks-dummy.h" |
26 | ||
f770d743 JM |
27 | #ifdef GENERATOR_FILE |
28 | /* This is used in some insn conditions, so needs to be declared, but | |
29 | does not need to be defined. */ | |
30 | extern int target_flags_explicit; | |
31 | #endif | |
32 | ||
e75b25e7 MM |
33 | /* MIPS external variables defined in mips.c. */ |
34 | ||
ac8ab9fe RS |
35 | /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32), |
36 | ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended | |
85f65093 | 37 | to work on a 64-bit machine. */ |
b2d8cf33 | 38 | |
04bd620d JW |
39 | #define ABI_32 0 |
40 | #define ABI_N32 1 | |
41 | #define ABI_64 2 | |
42 | #define ABI_EABI 3 | |
a53f72db | 43 | #define ABI_O64 4 |
0e5a4ad8 | 44 | |
4ecfc7e3 YS |
45 | enum mips_isa { |
46 | MIPS_ISA_MIPS1 = 1, | |
47 | MIPS_ISA_MIPS2 = 2, | |
48 | MIPS_ISA_MIPS3 = 3, | |
49 | MIPS_ISA_MIPS4 = 4, | |
50 | MIPS_ISA_MIPS32 = 32, | |
51 | MIPS_ISA_MIPS32R2 = 33, | |
52 | MIPS_ISA_MIPS32R3 = 34, | |
53 | MIPS_ISA_MIPS32R5 = 36, | |
54 | MIPS_ISA_MIPS32R6 = 37, | |
55 | MIPS_ISA_MIPS64 = 64, | |
56 | MIPS_ISA_MIPS64R2 = 65, | |
57 | MIPS_ISA_MIPS64R3 = 66, | |
58 | MIPS_ISA_MIPS64R5 = 68, | |
59 | MIPS_ISA_MIPS64R6 = 69 | |
60 | }; | |
61 | ||
0da4c1ea RS |
62 | /* Masks that affect tuning. |
63 | ||
7c507664 | 64 | PTF_AVOID_BRANCHLIKELY_SPEED |
0da4c1ea | 65 | Set if it is usually not profitable to use branch-likely instructions |
7c507664 RS |
66 | for this target when optimizing code for speed, typically because |
67 | the branches are always predicted taken and so incur a large overhead | |
68 | when not taken. | |
69 | ||
70 | PTF_AVOID_BRANCHLIKELY_SIZE | |
71 | As above but when optimizing for size. | |
72 | ||
73 | PTF_AVOID_BRANCHLIKELY_ALWAYS | |
74 | As above but regardless of whether we optimize for speed or size. | |
855e0d0b SE |
75 | |
76 | PTF_AVOID_IMADD | |
77 | Set if it is usually not profitable to use the integer MADD or MSUB | |
78 | instructions because of the overhead of getting the result out of | |
79 | the HI/LO registers. */ | |
80 | ||
7c507664 RS |
81 | #define PTF_AVOID_BRANCHLIKELY_SPEED 0x1 |
82 | #define PTF_AVOID_BRANCHLIKELY_SIZE 0x2 | |
83 | #define PTF_AVOID_BRANCHLIKELY_ALWAYS (PTF_AVOID_BRANCHLIKELY_SPEED | \ | |
84 | PTF_AVOID_BRANCHLIKELY_SIZE) | |
85 | #define PTF_AVOID_IMADD 0x4 | |
0da4c1ea | 86 | |
05713b80 | 87 | /* Information about one recognized processor. Defined here for the |
a27fb29b RS |
88 | benefit of TARGET_CPU_CPP_BUILTINS. */ |
89 | struct mips_cpu_info { | |
90 | /* The 'canonical' name of the processor as far as GCC is concerned. | |
91 | It's typically a manufacturer's prefix followed by a numerical | |
85f65093 | 92 | designation. It should be lowercase. */ |
a27fb29b RS |
93 | const char *name; |
94 | ||
95 | /* The internal processor number that most closely matches this | |
96 | entry. Several processors can have the same value, if there's no | |
97 | difference between them from GCC's point of view. */ | |
24609606 | 98 | enum processor cpu; |
a27fb29b RS |
99 | |
100 | /* The ISA level that the processor implements. */ | |
4ecfc7e3 | 101 | enum mips_isa isa; |
0da4c1ea RS |
102 | |
103 | /* A mask of PTF_* values. */ | |
104 | unsigned int tune_flags; | |
a27fb29b RS |
105 | }; |
106 | ||
3af42a7b | 107 | #include "config/mips/mips-opts.h" |
c93c5160 | 108 | |
3a6ee9f4 MM |
109 | /* Macros to silence warnings about numbers being signed in traditional |
110 | C and unsigned in ISO C when compiled on 32-bit hosts. */ | |
111 | ||
112 | #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ | |
113 | #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ | |
114 | #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ | |
115 | ||
149e4e00 MM |
116 | \f |
117 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
118 | ||
8cb6400c RS |
119 | /* True if we are generating position-independent VxWorks RTP code. */ |
120 | #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic) | |
121 | ||
22219d9b MF |
122 | /* Compact branches must not be used if the user either selects the |
123 | 'never' policy or the 'optimal' policy on a core that lacks | |
124 | compact branch instructions. */ | |
125 | #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER \ | |
126 | || (mips_cb == MIPS_CB_OPTIMAL \ | |
127 | && !ISA_HAS_COMPACT_BRANCHES)) | |
128 | ||
129 | /* Compact branches may be used if the user either selects the | |
130 | 'always' policy or the 'optimal' policy on a core that supports | |
131 | compact branch instructions. */ | |
132 | #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \ | |
133 | || (mips_cb == MIPS_CB_OPTIMAL \ | |
134 | && ISA_HAS_COMPACT_BRANCHES)) | |
135 | ||
136 | /* Compact branches must always be generated if the user selects | |
137 | the 'always' policy or the 'optimal' policy om a core that | |
138 | lacks delay slot branch instructions. */ | |
139 | #define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS \ | |
140 | || (mips_cb == MIPS_CB_OPTIMAL \ | |
141 | && !ISA_HAS_DELAY_SLOTS)) | |
142 | ||
143 | /* Special handling for JRC that exists in microMIPSR3 as well as R6 | |
144 | ISAs with full compact branch support. */ | |
145 | #define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \ | |
146 | || TARGET_MICROMIPS) \ | |
147 | && mips_cb != MIPS_CB_NEVER) | |
148 | ||
e21d5757 DJ |
149 | /* True if the output file is marked as ".abicalls; .option pic0" |
150 | (-call_nonpic). */ | |
151 | #define TARGET_ABICALLS_PIC0 \ | |
152 | (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT) | |
153 | ||
154 | /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */ | |
155 | #define TARGET_ABICALLS_PIC2 \ | |
156 | (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0) | |
157 | ||
cafe096b | 158 | /* True if the call patterns should be split into a jalr followed by |
14976818 | 159 | an instruction to restore $gp. It is only safe to split the load |
0c433c31 RS |
160 | from the call when every use of $gp is explicit. |
161 | ||
162 | See mips_must_initialize_gp_p for details about how we manage the | |
163 | global pointer. */ | |
cafe096b EC |
164 | |
165 | #define TARGET_SPLIT_CALLS \ | |
0c433c31 | 166 | (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed) |
cafe096b | 167 | |
d9870b7e RS |
168 | /* True if we're generating a form of -mabicalls in which we can use |
169 | operators like %hi and %lo to refer to locally-binding symbols. | |
170 | We can only do this for -mno-shared, and only then if we can use | |
171 | relocation operations instead of assembly macros. It isn't really | |
172 | worth using absolute sequences for 64-bit symbols because GOT | |
173 | accesses are so much shorter. */ | |
174 | ||
175 | #define TARGET_ABSOLUTE_ABICALLS \ | |
176 | (TARGET_ABICALLS \ | |
177 | && !TARGET_SHARED \ | |
178 | && TARGET_EXPLICIT_RELOCS \ | |
179 | && !ABI_HAS_64BIT_SYMBOLS) | |
180 | ||
cafe096b EC |
181 | /* True if we can optimize sibling calls. For simplicity, we only |
182 | handle cases in which call_insn_operand will reject invalid | |
183 | sibcall addresses. There are two cases in which this isn't true: | |
184 | ||
185 | - TARGET_MIPS16. call_insn_operand accepts constant addresses | |
186 | but there is no direct jump instruction. It isn't worth | |
187 | using sibling calls in this case anyway; they would usually | |
188 | be longer than normal calls. | |
189 | ||
14976818 RS |
190 | - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand |
191 | accepts global constants, but all sibcalls must be indirect. */ | |
cafe096b | 192 | #define TARGET_SIBCALLS \ |
14976818 RS |
193 | (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS)) |
194 | ||
195 | /* True if we need to use a global offset table to access some symbols. */ | |
8cb6400c | 196 | #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC) |
14976818 RS |
197 | |
198 | /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */ | |
199 | #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI) | |
200 | ||
201 | /* True if TARGET_USE_GOT and if $gp is a call-saved register. */ | |
202 | #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP) | |
203 | ||
0c433c31 RS |
204 | /* True if we should use .cprestore to store to the cprestore slot. |
205 | ||
206 | We continue to use .cprestore for explicit-reloc code so that JALs | |
207 | inside inline asms will work correctly. */ | |
208 | #define TARGET_CPRESTORE_DIRECTIVE \ | |
209 | (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16) | |
210 | ||
211 | /* True if we can use the J and JAL instructions. */ | |
212 | #define TARGET_ABSOLUTE_JUMPS \ | |
213 | (!flag_pic || TARGET_ABSOLUTE_ABICALLS) | |
214 | ||
8cb6400c RS |
215 | /* True if indirect calls must use register class PIC_FN_ADDR_REG. |
216 | This is true for both the PIC and non-PIC VxWorks RTP modes. */ | |
217 | #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP) | |
cafe096b | 218 | |
b24513a1 | 219 | /* True if .gpword or .gpdword should be used for switch tables. */ |
e21d5757 | 220 | #define TARGET_GPWORD \ |
b24513a1 | 221 | (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS) |
cafe096b | 222 | |
49576e25 RS |
223 | /* True if the output must have a writable .eh_frame. |
224 | See ASM_PREFERRED_EH_DATA_FORMAT for details. */ | |
225 | #ifdef HAVE_LD_PERSONALITY_RELAXATION | |
226 | #define TARGET_WRITABLE_EH_FRAME 0 | |
227 | #else | |
228 | #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED) | |
229 | #endif | |
230 | ||
293b77b0 CF |
231 | /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */ |
232 | #ifdef HAVE_AS_DSPR1_MULT | |
233 | #define ISA_HAS_DSP_MULT ISA_HAS_DSP | |
234 | #else | |
235 | #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2 | |
236 | #endif | |
237 | ||
954bdd58 | 238 | /* ISA has LSA available. */ |
0bc8d0b3 | 239 | #define ISA_HAS_LSA (mips_isa_rev >= 6 || ISA_HAS_MSA) |
954bdd58 MF |
240 | |
241 | /* ISA has DLSA available. */ | |
0bc8d0b3 RS |
242 | #define ISA_HAS_DLSA (TARGET_64BIT \ |
243 | && (mips_isa_rev >= 6 \ | |
244 | || ISA_HAS_MSA)) | |
954bdd58 | 245 | |
30a08286 YS |
246 | /* ISA load/store instructions can handle unaligned address */ |
247 | #define ISA_HAS_UNALIGNED_ACCESS (TARGET_UNALIGNED_ACCESS \ | |
248 | && (mips_isa_rev >= 6)) | |
249 | ||
22c4c869 CM |
250 | /* The ISA compression flags that are currently in effect. */ |
251 | #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS)) | |
252 | ||
7cc63a88 | 253 | /* Generate mips16 code */ |
40a350c9 | 254 | #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) |
f2d6ca50 | 255 | /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */ |
4ecfc7e3 | 256 | #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= MIPS_ISA_MIPS32) |
e1260576 RS |
257 | /* Generate mips16e register save/restore sequences. */ |
258 | #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32) | |
2bcb2ab3 | 259 | |
c93c5160 RS |
260 | /* True if we're generating a form of MIPS16 code in which general |
261 | text loads are allowed. */ | |
262 | #define TARGET_MIPS16_TEXT_LOADS \ | |
263 | (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES) | |
264 | ||
265 | /* True if we're generating a form of MIPS16 code in which PC-relative | |
266 | loads are allowed. */ | |
267 | #define TARGET_MIPS16_PCREL_LOADS \ | |
268 | (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL) | |
269 | ||
ce3649d2 | 270 | /* Generic ISA defines. */ |
4ecfc7e3 YS |
271 | #define ISA_MIPS1 (mips_isa == MIPS_ISA_MIPS1) |
272 | #define ISA_MIPS2 (mips_isa == MIPS_ISA_MIPS2) | |
273 | #define ISA_MIPS3 (mips_isa == MIPS_ISA_MIPS3) | |
274 | #define ISA_MIPS4 (mips_isa == MIPS_ISA_MIPS4) | |
275 | #define ISA_MIPS32 (mips_isa == MIPS_ISA_MIPS32) | |
276 | #define ISA_MIPS32R2 (mips_isa == MIPS_ISA_MIPS32R2) | |
277 | #define ISA_MIPS32R3 (mips_isa == MIPS_ISA_MIPS32R3) | |
278 | #define ISA_MIPS32R5 (mips_isa == MIPS_ISA_MIPS32R5) | |
279 | #define ISA_MIPS32R6 (mips_isa == MIPS_ISA_MIPS32R6) | |
280 | #define ISA_MIPS64 (mips_isa == MIPS_ISA_MIPS64) | |
281 | #define ISA_MIPS64R2 (mips_isa == MIPS_ISA_MIPS64R2) | |
282 | #define ISA_MIPS64R3 (mips_isa == MIPS_ISA_MIPS64R3) | |
283 | #define ISA_MIPS64R5 (mips_isa == MIPS_ISA_MIPS64R5) | |
284 | #define ISA_MIPS64R6 (mips_isa == MIPS_ISA_MIPS64R6) | |
ce3649d2 | 285 | |
7dac2f89 | 286 | /* Architecture target defines. */ |
f2d6ca50 AN |
287 | #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) |
288 | #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F) | |
289 | #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F) | |
2b94a36d | 290 | #define TARGET_GS464 (mips_arch == PROCESSOR_GS464) |
659ce7cb | 291 | #define TARGET_GS464E (mips_arch == PROCESSOR_GS464E) |
8fa1acc7 | 292 | #define TARGET_GS264E (mips_arch == PROCESSOR_GS264E) |
7dac2f89 EC |
293 | #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900) |
294 | #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000) | |
3f7967e3 | 295 | #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120) |
cf768d70 | 296 | #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130) |
5ce6f47b EC |
297 | #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400) |
298 | #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500) | |
107eea2c | 299 | #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900) |
5fe25f47 | 300 | #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000) |
e5aac417 | 301 | #define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000) |
98450f0d | 302 | #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000) |
38a53a0e | 303 | #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \ |
ed60a04b N |
304 | || mips_arch == PROCESSOR_OCTEON2 \ |
305 | || mips_arch == PROCESSOR_OCTEON3) | |
306 | #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \ | |
307 | || mips_arch == PROCESSOR_OCTEON3) | |
c81d6e2a JW |
308 | #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \ |
309 | || mips_arch == PROCESSOR_SB1A) | |
5ce6f47b | 310 | #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000) |
6399761a | 311 | #define TARGET_XLP (mips_arch == PROCESSOR_XLP) |
7dac2f89 EC |
312 | |
313 | /* Scheduling target defines. */ | |
f2d6ca50 AN |
314 | #define TUNE_20KC (mips_tune == PROCESSOR_20KC) |
315 | #define TUNE_24K (mips_tune == PROCESSOR_24KC \ | |
316 | || mips_tune == PROCESSOR_24KF2_1 \ | |
317 | || mips_tune == PROCESSOR_24KF1_1) | |
318 | #define TUNE_74K (mips_tune == PROCESSOR_74KC \ | |
319 | || mips_tune == PROCESSOR_74KF2_1 \ | |
320 | || mips_tune == PROCESSOR_74KF1_1 \ | |
321 | || mips_tune == PROCESSOR_74KF3_2) | |
322 | #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \ | |
323 | || mips_tune == PROCESSOR_LOONGSON_2F) | |
2b94a36d | 324 | #define TUNE_GS464 (mips_tune == PROCESSOR_GS464) |
659ce7cb | 325 | #define TUNE_GS464E (mips_tune == PROCESSOR_GS464E) |
8fa1acc7 | 326 | #define TUNE_GS264E (mips_tune == PROCESSOR_GS264E) |
7a38df19 EC |
327 | #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000) |
328 | #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900) | |
329 | #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000) | |
dc884a86 RS |
330 | #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120) |
331 | #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130) | |
7a38df19 | 332 | #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000) |
5ce6f47b EC |
333 | #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400) |
334 | #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500) | |
7a38df19 | 335 | #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000) |
5fe25f47 | 336 | #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000) |
98450f0d | 337 | #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000) |
38a53a0e | 338 | #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \ |
ed60a04b N |
339 | || mips_tune == PROCESSOR_OCTEON2 \ |
340 | || mips_tune == PROCESSOR_OCTEON3) | |
c81d6e2a JW |
341 | #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \ |
342 | || mips_tune == PROCESSOR_SB1A) | |
aaaa9efc | 343 | #define TUNE_P5600 (mips_tune == PROCESSOR_P5600) |
7ccb4e4e | 344 | #define TUNE_I6400 (mips_tune == PROCESSOR_I6400) |
30c0ee9c | 345 | #define TUNE_P6600 (mips_tune == PROCESSOR_P6600) |
7dac2f89 | 346 | |
39ba1719 RS |
347 | /* True if the pre-reload scheduler should try to create chains of |
348 | multiply-add or multiply-subtract instructions. For example, | |
349 | suppose we have: | |
350 | ||
351 | t1 = a * b | |
352 | t2 = t1 + c * d | |
d0cb84e9 RS |
353 | t3 = e * f |
354 | t4 = t3 - g * h | |
39ba1719 | 355 | |
d0cb84e9 | 356 | t1 will have a higher priority than t2 and t3 will have a higher |
39ba1719 RS |
357 | priority than t4. However, before reload, there is no dependence |
358 | between t1 and t3, and they can often have similar priorities. | |
359 | The scheduler will then tend to prefer: | |
360 | ||
361 | t1 = a * b | |
362 | t3 = e * f | |
363 | t2 = t1 + c * d | |
364 | t4 = t3 - g * h | |
365 | ||
366 | which stops us from making full use of macc/madd-style instructions. | |
367 | This sort of situation occurs frequently in Fourier transforms and | |
368 | in unrolled loops. | |
369 | ||
370 | To counter this, the TUNE_MACC_CHAINS code will reorder the ready | |
371 | queue so that chained multiply-add and multiply-subtract instructions | |
372 | appear ahead of any other instruction that is likely to clobber lo. | |
373 | In the example above, if t2 and t3 become ready at the same time, | |
374 | the code ensures that t2 is scheduled first. | |
375 | ||
376 | Multiply-accumulate instructions are a bigger win for some targets | |
377 | than others, so this macro is defined on an opt-in basis. */ | |
dc884a86 RS |
378 | #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \ |
379 | || TUNE_MIPS4120 \ | |
d56b9f12 | 380 | || TUNE_MIPS4130 \ |
aaaa9efc JP |
381 | || TUNE_24K \ |
382 | || TUNE_P5600) | |
39ba1719 | 383 | |
7f9be256 | 384 | #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64) |
cafe096b EC |
385 | #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64) |
386 | ||
cc4ebe7d SL |
387 | /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is |
388 | directly accessible, while the command-line options select | |
389 | TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI | |
390 | in use. */ | |
391 | #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16) | |
392 | #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16) | |
068ca03a | 393 | |
050af144 MF |
394 | /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents |
395 | -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */ | |
396 | #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX) | |
397 | ||
398 | /* TARGET_O32_FP64A_ABI represents all the conditions that form the | |
399 | o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */ | |
400 | #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \ | |
401 | && !TARGET_ODD_SPREG) | |
402 | ||
068ca03a DD |
403 | /* False if SC acts as a memory barrier with respect to itself, |
404 | otherwise a SYNC will be emitted after SC for atomic operations | |
405 | that require ordering between the SC and following loads and | |
406 | stores. It does not tell anything about ordering of loads and | |
407 | stores prior to and following the SC, only about the SC itself and | |
408 | those loads and stores follow it. */ | |
6399761a | 409 | #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP) |
068ca03a | 410 | |
a27fb29b RS |
411 | /* Define preprocessor macros for the -march and -mtune options. |
412 | PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected | |
413 | processor. If INFO's canonical name is "foo", define PREFIX to | |
414 | be "foo", and define an additional macro PREFIX_FOO. */ | |
415 | #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \ | |
416 | do \ | |
417 | { \ | |
418 | char *macro, *p; \ | |
419 | \ | |
420 | macro = concat ((PREFIX), "_", (INFO)->name, NULL); \ | |
421 | for (p = macro; *p != 0; p++) \ | |
14f2a7e2 AP |
422 | if (*p == '+') \ |
423 | *p = 'P'; \ | |
424 | else \ | |
425 | *p = TOUPPER (*p); \ | |
a27fb29b RS |
426 | \ |
427 | builtin_define (macro); \ | |
428 | builtin_define_with_value ((PREFIX), (INFO)->name, 1); \ | |
429 | free (macro); \ | |
430 | } \ | |
431 | while (0) | |
432 | ||
ce3649d2 | 433 | /* Target CPU builtins. */ |
0ea339ea NS |
434 | #define TARGET_CPU_CPP_BUILTINS() \ |
435 | do \ | |
436 | { \ | |
b24513a1 | 437 | builtin_assert ("machine=mips"); \ |
0ea339ea NS |
438 | builtin_assert ("cpu=mips"); \ |
439 | builtin_define ("__mips__"); \ | |
440 | builtin_define ("_mips"); \ | |
441 | \ | |
a7f051fe RS |
442 | /* We do this here because __mips is defined below and so we \ |
443 | can't use builtin_define_std. We don't ever want to define \ | |
444 | "mips" for VxWorks because some of the VxWorks headers \ | |
445 | construct include filenames from a root directory macro, \ | |
446 | an architecture macro and a filename, where the architecture \ | |
447 | macro expands to 'mips'. If we define 'mips' to 1, the \ | |
448 | architecture macro expands to 1 as well. */ \ | |
449 | if (!flag_iso && !TARGET_VXWORKS) \ | |
0ea339ea NS |
450 | builtin_define ("mips"); \ |
451 | \ | |
452 | if (TARGET_64BIT) \ | |
453 | builtin_define ("__mips64"); \ | |
454 | \ | |
b24513a1 RO |
455 | /* Treat _R3000 and _R4000 like register-size \ |
456 | defines, which is how they've historically \ | |
457 | been used. */ \ | |
458 | if (TARGET_64BIT) \ | |
0ea339ea | 459 | { \ |
b24513a1 RO |
460 | builtin_define_std ("R4000"); \ |
461 | builtin_define ("_R4000"); \ | |
462 | } \ | |
463 | else \ | |
464 | { \ | |
465 | builtin_define_std ("R3000"); \ | |
466 | builtin_define ("_R3000"); \ | |
0ea339ea | 467 | } \ |
b24513a1 | 468 | \ |
0ea339ea NS |
469 | if (TARGET_FLOAT64) \ |
470 | builtin_define ("__mips_fpr=64"); \ | |
050af144 MF |
471 | else if (TARGET_FLOATXX) \ |
472 | builtin_define ("__mips_fpr=0"); \ | |
0ea339ea NS |
473 | else \ |
474 | builtin_define ("__mips_fpr=32"); \ | |
475 | \ | |
22c4c869 | 476 | if (mips_base_compression_flags & MASK_MIPS16) \ |
0ea339ea NS |
477 | builtin_define ("__mips16"); \ |
478 | \ | |
479 | if (TARGET_MIPS3D) \ | |
480 | builtin_define ("__mips3d"); \ | |
481 | \ | |
482 | if (TARGET_SMARTMIPS) \ | |
483 | builtin_define ("__mips_smartmips"); \ | |
484 | \ | |
22c4c869 CM |
485 | if (mips_base_compression_flags & MASK_MICROMIPS) \ |
486 | builtin_define ("__mips_micromips"); \ | |
487 | \ | |
5cb5a23f MR |
488 | if (TARGET_MCU) \ |
489 | builtin_define ("__mips_mcu"); \ | |
490 | \ | |
44b20bb8 CM |
491 | if (TARGET_EVA) \ |
492 | builtin_define ("__mips_eva"); \ | |
493 | \ | |
0ea339ea NS |
494 | if (TARGET_DSP) \ |
495 | { \ | |
496 | builtin_define ("__mips_dsp"); \ | |
497 | if (TARGET_DSPR2) \ | |
498 | { \ | |
499 | builtin_define ("__mips_dspr2"); \ | |
500 | builtin_define ("__mips_dsp_rev=2"); \ | |
501 | } \ | |
502 | else \ | |
503 | builtin_define ("__mips_dsp_rev=1"); \ | |
504 | } \ | |
505 | \ | |
6cf538da RS |
506 | if (ISA_HAS_MSA) \ |
507 | { \ | |
508 | builtin_define ("__mips_msa"); \ | |
509 | builtin_define ("__mips_msa_width=128"); \ | |
510 | } \ | |
511 | \ | |
0ea339ea NS |
512 | MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \ |
513 | MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \ | |
514 | \ | |
515 | if (ISA_MIPS1) \ | |
516 | { \ | |
517 | builtin_define ("__mips=1"); \ | |
518 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \ | |
519 | } \ | |
520 | else if (ISA_MIPS2) \ | |
521 | { \ | |
522 | builtin_define ("__mips=2"); \ | |
523 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \ | |
524 | } \ | |
525 | else if (ISA_MIPS3) \ | |
526 | { \ | |
527 | builtin_define ("__mips=3"); \ | |
528 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \ | |
529 | } \ | |
530 | else if (ISA_MIPS4) \ | |
531 | { \ | |
532 | builtin_define ("__mips=4"); \ | |
533 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \ | |
534 | } \ | |
4ecfc7e3 YS |
535 | else if (mips_isa >= MIPS_ISA_MIPS32 \ |
536 | && mips_isa < MIPS_ISA_MIPS64) \ | |
0ea339ea NS |
537 | { \ |
538 | builtin_define ("__mips=32"); \ | |
0ea339ea NS |
539 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ |
540 | } \ | |
4ecfc7e3 | 541 | else if (mips_isa >= MIPS_ISA_MIPS64) \ |
2b3bd040 AB |
542 | { \ |
543 | builtin_define ("__mips=64"); \ | |
544 | builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ | |
545 | } \ | |
ad782bc9 RS |
546 | if (mips_isa_rev > 0) \ |
547 | builtin_define_with_int_value ("__mips_isa_rev", \ | |
548 | mips_isa_rev); \ | |
0ea339ea NS |
549 | \ |
550 | switch (mips_abi) \ | |
551 | { \ | |
552 | case ABI_32: \ | |
553 | builtin_define ("_ABIO32=1"); \ | |
554 | builtin_define ("_MIPS_SIM=_ABIO32"); \ | |
555 | break; \ | |
556 | \ | |
557 | case ABI_N32: \ | |
558 | builtin_define ("_ABIN32=2"); \ | |
559 | builtin_define ("_MIPS_SIM=_ABIN32"); \ | |
560 | break; \ | |
561 | \ | |
562 | case ABI_64: \ | |
563 | builtin_define ("_ABI64=3"); \ | |
564 | builtin_define ("_MIPS_SIM=_ABI64"); \ | |
565 | break; \ | |
566 | \ | |
567 | case ABI_O64: \ | |
568 | builtin_define ("_ABIO64=4"); \ | |
569 | builtin_define ("_MIPS_SIM=_ABIO64"); \ | |
570 | break; \ | |
571 | } \ | |
572 | \ | |
573 | builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \ | |
574 | builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \ | |
575 | builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \ | |
576 | builtin_define_with_int_value ("_MIPS_FPSET", \ | |
577 | 32 / MAX_FPRS_PER_FMT); \ | |
050af144 MF |
578 | builtin_define_with_int_value ("_MIPS_SPFPSET", \ |
579 | TARGET_ODD_SPREG ? 32 : 16); \ | |
0ea339ea NS |
580 | \ |
581 | /* These defines reflect the ABI in use, not whether the \ | |
582 | FPU is directly accessible. */ \ | |
9f946bc1 RS |
583 | if (TARGET_NO_FLOAT) \ |
584 | builtin_define ("__mips_no_float"); \ | |
585 | else if (TARGET_HARD_FLOAT_ABI) \ | |
0ea339ea NS |
586 | builtin_define ("__mips_hard_float"); \ |
587 | else \ | |
588 | builtin_define ("__mips_soft_float"); \ | |
589 | \ | |
590 | if (TARGET_SINGLE_FLOAT) \ | |
591 | builtin_define ("__mips_single_float"); \ | |
592 | \ | |
593 | if (TARGET_PAIRED_SINGLE_FLOAT) \ | |
594 | builtin_define ("__mips_paired_single_float"); \ | |
595 | \ | |
ff3f3951 MR |
596 | if (mips_abs == MIPS_IEEE_754_2008) \ |
597 | builtin_define ("__mips_abs2008"); \ | |
598 | \ | |
599 | if (mips_nan == MIPS_IEEE_754_2008) \ | |
600 | builtin_define ("__mips_nan2008"); \ | |
601 | \ | |
0ea339ea NS |
602 | if (TARGET_BIG_ENDIAN) \ |
603 | { \ | |
604 | builtin_define_std ("MIPSEB"); \ | |
605 | builtin_define ("_MIPSEB"); \ | |
606 | } \ | |
607 | else \ | |
608 | { \ | |
609 | builtin_define_std ("MIPSEL"); \ | |
610 | builtin_define ("_MIPSEL"); \ | |
611 | } \ | |
93581857 | 612 | \ |
cf51e479 RS |
613 | /* Whether calls should go through $25. The separate __PIC__ \ |
614 | macro indicates whether abicalls code might use a GOT. */ \ | |
615 | if (TARGET_ABICALLS) \ | |
616 | builtin_define ("__mips_abicalls"); \ | |
617 | \ | |
8ae8bad7 CX |
618 | /* Whether Loongson vector modes are enabled. */ \ |
619 | if (TARGET_LOONGSON_MMI) \ | |
620 | { \ | |
621 | builtin_define ("__mips_loongson_vector_rev"); \ | |
622 | builtin_define ("__mips_loongson_mmi"); \ | |
623 | } \ | |
0ea339ea | 624 | \ |
375899d9 CX |
625 | /* Whether Loongson EXT modes are enabled. */ \ |
626 | if (TARGET_LOONGSON_EXT) \ | |
627 | { \ | |
628 | builtin_define ("__mips_loongson_ext"); \ | |
d6319811 CX |
629 | if (TARGET_LOONGSON_EXT2) \ |
630 | { \ | |
631 | builtin_define ("__mips_loongson_ext2"); \ | |
632 | builtin_define ("__mips_loongson_ext_rev=2"); \ | |
633 | } \ | |
634 | else \ | |
635 | builtin_define ("__mips_loongson_ext_rev=1"); \ | |
375899d9 CX |
636 | } \ |
637 | \ | |
d97e6aca AN |
638 | /* Historical Octeon macro. */ \ |
639 | if (TARGET_OCTEON) \ | |
640 | builtin_define ("__OCTEON__"); \ | |
641 | \ | |
166c02bd RS |
642 | if (TARGET_SYNCI) \ |
643 | builtin_define ("__mips_synci"); \ | |
644 | \ | |
0ea339ea NS |
645 | /* Macros dependent on the C dialect. */ \ |
646 | if (preprocessing_asm_p ()) \ | |
647 | { \ | |
648 | builtin_define_std ("LANGUAGE_ASSEMBLY"); \ | |
649 | builtin_define ("_LANGUAGE_ASSEMBLY"); \ | |
650 | } \ | |
651 | else if (c_dialect_cxx ()) \ | |
652 | { \ | |
653 | builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \ | |
654 | builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ | |
655 | builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ | |
656 | } \ | |
657 | else \ | |
658 | { \ | |
659 | builtin_define_std ("LANGUAGE_C"); \ | |
660 | builtin_define ("_LANGUAGE_C"); \ | |
661 | } \ | |
662 | if (c_dialect_objc ()) \ | |
663 | { \ | |
664 | builtin_define ("_LANGUAGE_OBJECTIVE_C"); \ | |
665 | builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ | |
b24513a1 | 666 | /* Bizarre, but retained for backwards compatibility. */ \ |
0ea339ea NS |
667 | builtin_define_std ("LANGUAGE_C"); \ |
668 | builtin_define ("_LANGUAGE_C"); \ | |
669 | } \ | |
670 | \ | |
671 | if (mips_abi == ABI_EABI) \ | |
672 | builtin_define ("__mips_eabi"); \ | |
4d210b07 RS |
673 | \ |
674 | if (TARGET_CACHE_BUILTIN) \ | |
675 | builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \ | |
ab6b44cb MF |
676 | if (!ISA_HAS_LXC1_SXC1) \ |
677 | builtin_define ("__mips_no_lxc1_sxc1"); \ | |
d821744c MF |
678 | if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \ |
679 | builtin_define ("__mips_no_madd4"); \ | |
0ea339ea NS |
680 | } \ |
681 | while (0) | |
ce3649d2 | 682 | |
3785d2b2 | 683 | /* Target hooks for D language. */ |
b4c522fa | 684 | #define TARGET_D_CPU_VERSIONS mips_d_target_versions |
3785d2b2 | 685 | #define TARGET_D_REGISTER_CPU_TARGET_INFO mips_d_register_target_info |
b4c522fa | 686 | |
149e4e00 MM |
687 | /* Default target_flags if no switches are specified */ |
688 | ||
689 | #ifndef TARGET_DEFAULT | |
690 | #define TARGET_DEFAULT 0 | |
691 | #endif | |
692 | ||
404f986e MM |
693 | #ifndef TARGET_CPU_DEFAULT |
694 | #define TARGET_CPU_DEFAULT 0 | |
695 | #endif | |
696 | ||
96abdcb1 | 697 | #ifndef TARGET_ENDIAN_DEFAULT |
96abdcb1 | 698 | #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN |
96abdcb1 ILT |
699 | #endif |
700 | ||
996ed075 JJ |
701 | #ifdef IN_LIBGCC2 |
702 | #undef TARGET_64BIT | |
703 | /* Make this compile time constant for libgcc2 */ | |
704 | #ifdef __mips64 | |
705 | #define TARGET_64BIT 1 | |
706 | #else | |
707 | #define TARGET_64BIT 0 | |
708 | #endif | |
440927ec | 709 | #endif /* IN_LIBGCC2 */ |
996ed075 | 710 | |
56e449d3 SL |
711 | /* Force the call stack unwinders in unwind.inc not to be MIPS16 code |
712 | when compiled with hardware floating point. This is because MIPS16 | |
713 | code cannot save and restore the floating-point registers, which is | |
714 | important if in a mixed MIPS16/non-MIPS16 environment. */ | |
715 | ||
716 | #ifdef IN_LIBGCC2 | |
717 | #if __mips_hard_float | |
718 | #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__)) | |
719 | #endif | |
720 | #endif /* IN_LIBGCC2 */ | |
721 | ||
a0cfeb0f DD |
722 | #define TARGET_LIBGCC_SDATA_SECTION ".sdata" |
723 | ||
cbab8d02 | 724 | #ifndef MULTILIB_ENDIAN_DEFAULT |
7f2e00db | 725 | #if TARGET_ENDIAN_DEFAULT == 0 |
cbab8d02 | 726 | #define MULTILIB_ENDIAN_DEFAULT "EL" |
7f2e00db | 727 | #else |
cbab8d02 GRK |
728 | #define MULTILIB_ENDIAN_DEFAULT "EB" |
729 | #endif | |
7f2e00db | 730 | #endif |
cbab8d02 | 731 | |
ea09f032 | 732 | #ifndef MULTILIB_ISA_DEFAULT |
4ecfc7e3 | 733 | #if MIPS_ISA_DEFAULT == MIPS_ISA_MIPS1 |
44e88db2 | 734 | #define MULTILIB_ISA_DEFAULT "mips1" |
4ecfc7e3 | 735 | #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS2 |
44e88db2 | 736 | #define MULTILIB_ISA_DEFAULT "mips2" |
4ecfc7e3 | 737 | #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS3 |
44e88db2 | 738 | #define MULTILIB_ISA_DEFAULT "mips3" |
4ecfc7e3 | 739 | #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS4 |
44e88db2 | 740 | #define MULTILIB_ISA_DEFAULT "mips4" |
4ecfc7e3 | 741 | #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32 |
44e88db2 | 742 | #define MULTILIB_ISA_DEFAULT "mips32" |
4ecfc7e3 | 743 | #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R2 |
44e88db2 | 744 | #define MULTILIB_ISA_DEFAULT "mips32r2" |
4ecfc7e3 | 745 | #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R6 |
82f84ecb | 746 | #define MULTILIB_ISA_DEFAULT "mips32r6" |
4ecfc7e3 | 747 | #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64 |
44e88db2 | 748 | #define MULTILIB_ISA_DEFAULT "mips64" |
4ecfc7e3 | 749 | #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R2 |
44e88db2 | 750 | #define MULTILIB_ISA_DEFAULT "mips64r2" |
4ecfc7e3 | 751 | #elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R6 |
82f84ecb | 752 | #define MULTILIB_ISA_DEFAULT "mips64r6" |
44e88db2 RS |
753 | #else |
754 | #define MULTILIB_ISA_DEFAULT "mips1" | |
755 | #endif | |
ea09f032 GRK |
756 | #endif |
757 | ||
1ab8a8c2 JM |
758 | #ifndef MIPS_ABI_DEFAULT |
759 | #define MIPS_ABI_DEFAULT ABI_32 | |
760 | #endif | |
761 | ||
762 | /* Use the most portable ABI flag for the ASM specs. */ | |
763 | ||
764 | #if MIPS_ABI_DEFAULT == ABI_32 | |
765 | #define MULTILIB_ABI_DEFAULT "mabi=32" | |
44e88db2 | 766 | #elif MIPS_ABI_DEFAULT == ABI_O64 |
1ab8a8c2 | 767 | #define MULTILIB_ABI_DEFAULT "mabi=o64" |
44e88db2 | 768 | #elif MIPS_ABI_DEFAULT == ABI_N32 |
1ab8a8c2 | 769 | #define MULTILIB_ABI_DEFAULT "mabi=n32" |
44e88db2 | 770 | #elif MIPS_ABI_DEFAULT == ABI_64 |
1ab8a8c2 | 771 | #define MULTILIB_ABI_DEFAULT "mabi=64" |
44e88db2 | 772 | #elif MIPS_ABI_DEFAULT == ABI_EABI |
1ab8a8c2 JM |
773 | #define MULTILIB_ABI_DEFAULT "mabi=eabi" |
774 | #endif | |
775 | ||
cbab8d02 | 776 | #ifndef MULTILIB_DEFAULTS |
a27fb29b RS |
777 | #define MULTILIB_DEFAULTS \ |
778 | { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT } | |
7f2e00db RK |
779 | #endif |
780 | ||
34bcd7fd JW |
781 | /* We must pass -EL to the linker by default for little endian embedded |
782 | targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the | |
783 | linker will default to using big-endian output files. The OUTPUT_FORMAT | |
784 | line must be in the linker script, otherwise -EB/-EL will not work. */ | |
785 | ||
120dc6cd | 786 | #ifndef ENDIAN_SPEC |
34bcd7fd | 787 | #if TARGET_ENDIAN_DEFAULT == 0 |
ac282977 | 788 | #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}" |
34bcd7fd | 789 | #else |
ac282977 | 790 | #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}" |
34bcd7fd JW |
791 | #endif |
792 | #endif | |
793 | ||
e2c14f5d RS |
794 | /* A spec condition that matches all non-mips16 -mips arguments. */ |
795 | ||
796 | #define MIPS_ISA_LEVEL_OPTION_SPEC \ | |
797 | "mips1|mips2|mips3|mips4|mips32*|mips64*" | |
798 | ||
799 | /* A spec condition that matches all non-mips16 architecture arguments. */ | |
800 | ||
801 | #define MIPS_ARCH_OPTION_SPEC \ | |
802 | MIPS_ISA_LEVEL_OPTION_SPEC "|march=*" | |
803 | ||
fcd7669c | 804 | /* A spec that infers a -mips argument from an -march argument. */ |
e2c14f5d RS |
805 | |
806 | #define MIPS_ISA_LEVEL_SPEC \ | |
807 | "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ | |
808 | %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \ | |
809 | %{march=mips2|march=r6000:-mips2} \ | |
33db2060 | 810 | %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \ |
304b14b1 JK |
811 | %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \ |
812 | |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \ | |
9e32002f RS |
813 | %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \ |
814 | %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \ | |
8ced5d2d RS |
815 | |march=34k*|march=74k*|march=m14k*|march=1004k* \ |
816 | |march=interaptiv: -mips32r2} \ | |
2b3bd040 | 817 | %{march=mips32r3: -mips32r3} \ |
6dd74463 | 818 | %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \ |
82f84ecb | 819 | %{march=mips32r6: -mips32r6} \ |
0051ef59 | 820 | %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \ |
0c72fa78 | 821 | |march=xlr: -mips64} \ |
8fa1acc7 CX |
822 | %{march=mips64r2|march=loongson3a|march=gs464|march=gs464e|march=gs264e \ |
823 | |march=octeon|march=xlp: -mips64r2} \ | |
2b3bd040 AB |
824 | %{march=mips64r3: -mips64r3} \ |
825 | %{march=mips64r5: -mips64r5} \ | |
30c0ee9c | 826 | %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" |
fcd7669c MF |
827 | |
828 | /* A spec that injects the default multilib ISA if no architecture is | |
829 | specified. */ | |
830 | ||
831 | #define MIPS_DEFAULT_ISA_LEVEL_SPEC \ | |
832 | "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \ | |
0ea339ea NS |
833 | %{!march=*: -" MULTILIB_ISA_DEFAULT "}}" |
834 | ||
7d8bed7b RS |
835 | /* A spec that infers a -mhard-float or -msoft-float setting from an |
836 | -march argument. Note that soft-float and hard-float code are not | |
837 | link-compatible. */ | |
838 | ||
839 | #define MIPS_ARCH_FLOAT_SPEC \ | |
3df0998b | 840 | "%{mhard-float|msoft-float|mno-float|march=mips*:; \ |
7d8bed7b | 841 | march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \ |
fdd195f4 | 842 | |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \ |
6dd74463 | 843 | |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \ |
7d8bed7b RS |
844 | march=*: -mhard-float}" |
845 | ||
0ea339ea NS |
846 | /* A spec condition that matches 32-bit options. It only works if |
847 | MIPS_ISA_LEVEL_SPEC has been applied. */ | |
848 | ||
849 | #define MIPS_32BIT_OPTION_SPEC \ | |
850 | "mips1|mips2|mips32*|mgp32" | |
e2c14f5d | 851 | |
050af144 MF |
852 | /* A spec condition that matches architectures should be targeted with |
853 | o32 FPXX for compatibility reasons. */ | |
854 | #define MIPS_FPXX_OPTION_SPEC \ | |
855 | "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \ | |
856 | mips64|mips64r2|mips64r3|mips64r5" | |
857 | ||
965c1798 SE |
858 | /* Infer a -msynci setting from a -mips argument, on the assumption that |
859 | -msynci is desired where possible. */ | |
860 | #define MIPS_ISA_SYNCI_SPEC \ | |
82f84ecb MF |
861 | "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \ |
862 | |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}" | |
863 | ||
fcd7669c | 864 | /* Infer a -mnan=2008 setting from a -mips argument. */ |
82f84ecb | 865 | #define MIPS_ISA_NAN2008_SPEC \ |
6dd74463 PG |
866 | "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \ |
867 | %{!msoft-float:-mnan=2008}}" | |
965c1798 | 868 | |
44e88db2 RS |
869 | #if (MIPS_ABI_DEFAULT == ABI_O64 \ |
870 | || MIPS_ABI_DEFAULT == ABI_N32 \ | |
871 | || MIPS_ABI_DEFAULT == ABI_64) | |
1ab8a8c2 JM |
872 | #define OPT_ARCH64 "mabi=32|mgp32:;" |
873 | #define OPT_ARCH32 "mabi=32|mgp32" | |
874 | #else | |
875 | #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64" | |
876 | #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;" | |
877 | #endif | |
878 | ||
7816bea0 DJ |
879 | /* Support for a compile-time default CPU, et cetera. The rules are: |
880 | --with-arch is ignored if -march is specified or a -mips is specified | |
1ab8a8c2 JM |
881 | (other than -mips16); likewise --with-arch-32 and --with-arch-64. |
882 | --with-tune is ignored if -mtune is specified; likewise | |
883 | --with-tune-32 and --with-tune-64. | |
7816bea0 DJ |
884 | --with-abi is ignored if -mabi is specified. |
885 | --with-float is ignored if -mhard-float or -msoft-float are | |
9f0df97a | 886 | specified. |
050af144 MF |
887 | --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are |
888 | specified. | |
ff3f3951 | 889 | --with-nan is ignored if -mnan is specified. |
6cf538da RS |
890 | --with-fp-32 is ignored if -msoft-float, -msingle-float, -mmsa or -mfp are |
891 | specified. | |
050af144 MF |
892 | --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg |
893 | or -mno-odd-spreg are specified. | |
9f0df97a DD |
894 | --with-divide is ignored if -mdivide-traps or -mdivide-breaks are |
895 | specified. */ | |
7816bea0 | 896 | #define OPTION_DEFAULT_SPECS \ |
e2c14f5d | 897 | {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \ |
1ab8a8c2 JM |
898 | {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ |
899 | {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \ | |
7816bea0 | 900 | {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ |
1ab8a8c2 JM |
901 | {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ |
902 | {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \ | |
7816bea0 | 903 | {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \ |
9f0df97a | 904 | {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ |
050af144 | 905 | {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \ |
ff3f3951 | 906 | {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \ |
050af144 | 907 | {"fp_32", "%{" OPT_ARCH32 \ |
6cf538da | 908 | ":%{!msoft-float:%{!msingle-float:%{!mfp*:%{!mmsa:-mfp%(VALUE)}}}}}" }, \ |
050af144 MF |
909 | {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \ |
910 | "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \ | |
66471b47 | 911 | {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \ |
e21d5757 | 912 | {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \ |
b96c5923 | 913 | {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \ |
ab6b44cb | 914 | {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \ |
d821744c MF |
915 | {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \ |
916 | {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \ | |
9f0df97a | 917 | |
fcd7669c MF |
918 | /* A spec that infers the: |
919 | -mnan=2008 setting from a -mips argument, | |
8ae8bad7 CX |
920 | -mdsp setting from a -march argument. |
921 | -mloongson-mmi setting from a -march argument. */ | |
922 | #define BASE_DRIVER_SELF_SPECS \ | |
923 | MIPS_ISA_NAN2008_SPEC, \ | |
924 | MIPS_ASE_DSP_SPEC, \ | |
375899d9 | 925 | MIPS_ASE_LOONGSON_MMI_SPEC, \ |
8fa1acc7 CX |
926 | MIPS_ASE_LOONGSON_EXT_SPEC, \ |
927 | MIPS_ASE_MSA_SPEC | |
928 | ||
8ae8bad7 CX |
929 | |
930 | #define MIPS_ASE_DSP_SPEC \ | |
037f9973 | 931 | "%{!mno-dsp: \ |
8ced5d2d RS |
932 | %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \ |
933 | |march=interaptiv: -mdsp} \ | |
8e932114 | 934 | %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}" |
7f75ae86 | 935 | |
8ae8bad7 CX |
936 | #define MIPS_ASE_LOONGSON_MMI_SPEC \ |
937 | "%{!mno-loongson-mmi: \ | |
938 | %{march=loongson2e|march=loongson2f|march=loongson3a: -mloongson-mmi}}" | |
939 | ||
375899d9 CX |
940 | #define MIPS_ASE_LOONGSON_EXT_SPEC \ |
941 | "%{!mno-loongson-ext: \ | |
659ce7cb | 942 | %{march=loongson3a|march=gs464: -mloongson-ext} \ |
8fa1acc7 CX |
943 | %{march=gs464e|march=gs264e: %{!mno-loongson-ext2: \ |
944 | -mloongson-ext2 -mloongson-ext}}}" | |
945 | ||
946 | #define MIPS_ASE_MSA_SPEC \ | |
947 | "%{!mno-msa: \ | |
948 | %{march=gs264e: -mmsa}}" | |
375899d9 | 949 | |
82f84ecb MF |
950 | #define DRIVER_SELF_SPECS \ |
951 | MIPS_ISA_LEVEL_SPEC, \ | |
952 | BASE_DRIVER_SELF_SPECS | |
7f75ae86 | 953 | |
9f0df97a DD |
954 | #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \ |
955 | && ISA_HAS_COND_TRAP) | |
7816bea0 | 956 | |
0da4c1ea | 957 | #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16) |
e4f5c5d6 | 958 | |
a27fb29b RS |
959 | /* True if the ABI can only work with 64-bit integer registers. We |
960 | generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but | |
961 | otherwise floating-point registers must also be 64-bit. */ | |
7f9be256 | 962 | #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64) |
a27fb29b RS |
963 | |
964 | /* Likewise for 32-bit regs. */ | |
965 | #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32) | |
966 | ||
2e8a796f RS |
967 | /* True if the file format uses 64-bit symbols. At present, this is |
968 | only true for n64, which uses 64-bit ELF. */ | |
969 | #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64) | |
970 | ||
971 | /* True if symbols are 64 bits wide. This is usually determined by | |
972 | the ABI's file format, but it can be overridden by -msym32. Note that | |
973 | overriding the size with -msym32 changes the ABI of relocatable objects, | |
974 | although it doesn't change the ABI of a fully-linked object. */ | |
81a478c8 RS |
975 | #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \ |
976 | && Pmode == DImode \ | |
977 | && !TARGET_SYM32) | |
cafe096b | 978 | |
85f65093 | 979 | /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */ |
8f2e3902 EC |
980 | #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \ |
981 | || ISA_MIPS4 \ | |
f2d6ca50 | 982 | || ISA_MIPS64 \ |
2b3bd040 AB |
983 | || ISA_MIPS64R2 \ |
984 | || ISA_MIPS64R3 \ | |
82f84ecb MF |
985 | || ISA_MIPS64R5 \ |
986 | || ISA_MIPS64R6) | |
987 | ||
988 | #define ISA_HAS_JR (mips_isa_rev <= 5) | |
1d5d552e | 989 | |
22219d9b MF |
990 | #define ISA_HAS_DELAY_SLOTS 1 |
991 | ||
992 | #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6) | |
993 | ||
112cdef5 | 994 | /* ISA has branch likely instructions (e.g. mips2). */ |
7dac2f89 EC |
995 | /* Disable branchlikely for tx39 until compare rewrite. They haven't |
996 | been generated up to this point. */ | |
82f84ecb | 997 | #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5) |
1d5d552e | 998 | |
050af144 MF |
999 | /* ISA has 32 single-precision registers. */ |
1000 | #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \ | |
2b94a36d | 1001 | && !TARGET_GS464) \ |
050af144 MF |
1002 | || TARGET_FLOAT64 \ |
1003 | || TARGET_MIPS5900) | |
1004 | ||
2f8e468b | 1005 | /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */ |
3f07249e RS |
1006 | #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \ |
1007 | || TARGET_MIPS5400 \ | |
1008 | || TARGET_MIPS5500 \ | |
0de86a92 | 1009 | || TARGET_MIPS5900 \ |
3f07249e RS |
1010 | || TARGET_MIPS7000 \ |
1011 | || TARGET_MIPS9000 \ | |
1012 | || TARGET_MAD \ | |
82f84ecb MF |
1013 | || (mips_isa_rev >= 1 \ |
1014 | && mips_isa_rev <= 5)) \ | |
3f07249e RS |
1015 | && !TARGET_MIPS16) |
1016 | ||
d6d3e623 | 1017 | /* ISA has a three-operand multiplication instruction. */ |
aa5409e7 AN |
1018 | #define ISA_HAS_DMUL3 (TARGET_64BIT \ |
1019 | && TARGET_OCTEON \ | |
1020 | && !TARGET_MIPS16) | |
d6d3e623 | 1021 | |
82f84ecb MF |
1022 | /* ISA has HI and LO registers. */ |
1023 | #define ISA_HAS_HILO (mips_isa_rev <= 5) | |
1024 | ||
0de86a92 | 1025 | /* ISA supports instructions DMULT and DMULTU. */ |
82f84ecb MF |
1026 | #define ISA_HAS_DMULT (TARGET_64BIT \ |
1027 | && !TARGET_MIPS5900 \ | |
1028 | && mips_isa_rev <= 5) | |
0de86a92 | 1029 | |
82f84ecb MF |
1030 | /* ISA supports instructions MULT and MULTU. */ |
1031 | #define ISA_HAS_MULT (mips_isa_rev <= 5) | |
1032 | ||
1033 | /* ISA supports instructions MUL, MULU, MUH, MUHU. */ | |
1034 | #define ISA_HAS_R6MUL (mips_isa_rev >= 6) | |
1035 | ||
1036 | /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */ | |
1037 | #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6) | |
0de86a92 | 1038 | |
d5432112 TT |
1039 | /* For Loongson, it is preferable to use the Loongson-specific division and |
1040 | modulo instructions instead of the regular (D)DIV(U) instruction, | |
1041 | because the former are faster and can also have the effect of reducing | |
1042 | code size. */ | |
1043 | #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \ | |
2b94a36d | 1044 | || TARGET_GS464) \ |
d5432112 TT |
1045 | && !TARGET_MIPS16) |
1046 | ||
0de86a92 | 1047 | /* ISA supports instructions DDIV and DDIVU. */ |
82f84ecb MF |
1048 | #define ISA_HAS_DDIV (TARGET_64BIT \ |
1049 | && !TARGET_MIPS5900 \ | |
d5432112 | 1050 | && !ISA_AVOID_DIV_HILO \ |
82f84ecb | 1051 | && mips_isa_rev <= 5) |
0de86a92 JU |
1052 | |
1053 | /* ISA supports instructions DIV and DIVU. | |
1054 | This is always true, but the macro is needed for ISA_HAS_<D>DIV | |
1055 | in mips.md. */ | |
d5432112 TT |
1056 | #define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \ |
1057 | && mips_isa_rev <= 5) | |
44e88db2 | 1058 | |
82f84ecb MF |
1059 | /* ISA supports instructions DIV, DIVU, MOD and MODU. */ |
1060 | #define ISA_HAS_R6DIV (mips_isa_rev >= 6) | |
1061 | ||
1062 | /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */ | |
1063 | #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6) | |
1064 | ||
b51469a5 MK |
1065 | /* ISA has the floating-point conditional move instructions introduced |
1066 | in mips4. */ | |
1067 | #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \ | |
82f84ecb MF |
1068 | || (mips_isa_rev >= 1 \ |
1069 | && mips_isa_rev <= 5)) \ | |
3f07249e | 1070 | && !TARGET_MIPS5500 \ |
ce3649d2 | 1071 | && !TARGET_MIPS16) |
76ee8042 | 1072 | |
b51469a5 MK |
1073 | /* ISA has the integer conditional move instructions introduced in mips4 and |
1074 | ST Loongson 2E/2F. */ | |
107eea2c JU |
1075 | #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \ |
1076 | || TARGET_MIPS5900 \ | |
1077 | || TARGET_LOONGSON_2EF) | |
b51469a5 | 1078 | |
f457938f | 1079 | /* ISA has LDC1 and SDC1. */ |
04dfc6df JU |
1080 | #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \ |
1081 | && !TARGET_MIPS5900 \ | |
1082 | && !TARGET_MIPS16) | |
f457938f | 1083 | |
76ee8042 | 1084 | /* ISA has the mips4 FP condition code instructions: FP-compare to CC, |
987ba558 | 1085 | branch on CC, and move (both FP and non-FP) on CC. */ |
82f84ecb MF |
1086 | #define ISA_HAS_8CC (ISA_MIPS4 \ |
1087 | || (mips_isa_rev >= 1 \ | |
1088 | && mips_isa_rev <= 5)) | |
1089 | ||
1090 | /* ISA has the FP condition code instructions that store the flag in an | |
1091 | FP register. */ | |
1092 | #define ISA_HAS_CCF (mips_isa_rev >= 6) | |
1093 | ||
1094 | #define ISA_HAS_SEL (mips_isa_rev >= 6) | |
76ee8042 | 1095 | |
4dbe1556 CD |
1096 | /* This is a catch all for other mips4 instructions: indexed load, the |
1097 | FP madd and msub instructions, and the FP recip and recip sqrt | |
7cfe3cc1 MR |
1098 | instructions. Note that this macro should only be used by other |
1099 | ISA_HAS_* macros. */ | |
3f07249e | 1100 | #define ISA_HAS_FP4 ((ISA_MIPS4 \ |
f2d6ca50 | 1101 | || ISA_MIPS64 \ |
82f84ecb MF |
1102 | || (mips_isa_rev >= 2 \ |
1103 | && mips_isa_rev <= 5)) \ | |
3f07249e | 1104 | && !TARGET_MIPS16) |
76ee8042 | 1105 | |
7cfe3cc1 MR |
1106 | /* ISA has floating-point indexed load and store instructions |
1107 | (LWXC1, LDXC1, SWXC1 and SDXC1). */ | |
ab6b44cb MF |
1108 | #define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \ |
1109 | && mips_lxc1_sxc1) | |
7cfe3cc1 | 1110 | |
e5a2b69d | 1111 | /* ISA has paired-single instructions. */ |
96902805 JM |
1112 | #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \ |
1113 | || (mips_isa_rev >= 2 \ | |
1114 | && mips_isa_rev <= 5)) \ | |
1115 | && !TARGET_OCTEON) | |
e5a2b69d | 1116 | |
a0b6cdee | 1117 | /* ISA has conditional trap instructions. */ |
ce3649d2 EC |
1118 | #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \ |
1119 | && !TARGET_MIPS16) | |
1d5d552e | 1120 | |
82f84ecb MF |
1121 | /* ISA has conditional trap with immediate instructions. */ |
1122 | #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \ | |
1123 | && mips_isa_rev <= 5 \ | |
1124 | && !TARGET_MIPS16) | |
1125 | ||
12bf26b6 | 1126 | /* ISA has integer multiply-accumulate instructions, madd and msub. */ |
82f84ecb MF |
1127 | #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \ |
1128 | && mips_isa_rev <= 5) | |
0e5a4ad8 | 1129 | |
8dd58f01 | 1130 | /* Integer multiply-accumulate instructions should be generated. */ |
855e0d0b | 1131 | #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16) |
8dd58f01 | 1132 | |
e5aac417 SE |
1133 | /* ISA has 4 operand fused madd instructions of the form |
1134 | 'd = [+-] (a * b [+-] c)'. */ | |
d821744c MF |
1135 | #define ISA_HAS_FUSED_MADD4 (mips_madd4 \ |
1136 | && (TARGET_MIPS8000 \ | |
659ce7cb | 1137 | || TARGET_GS464 \ |
8fa1acc7 CX |
1138 | || TARGET_GS464E \ |
1139 | || TARGET_GS264E)) | |
b51469a5 | 1140 | |
e5aac417 SE |
1141 | /* ISA has 4 operand unfused madd instructions of the form |
1142 | 'd = [+-] (a * b [+-] c)'. */ | |
d821744c MF |
1143 | #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \ |
1144 | && ISA_HAS_FP4 \ | |
cedb7e2c | 1145 | && !TARGET_MIPS8000 \ |
659ce7cb | 1146 | && !TARGET_GS464 \ |
8fa1acc7 CX |
1147 | && !TARGET_GS464E \ |
1148 | && !TARGET_GS264E) | |
82f84ecb | 1149 | |
e5aac417 SE |
1150 | /* ISA has 3 operand r6 fused madd instructions of the form |
1151 | 'c = c [+-] (a * b)'. */ | |
1152 | #define ISA_HAS_FUSED_MADDF (mips_isa_rev >= 6) | |
b51469a5 | 1153 | |
e5aac417 SE |
1154 | /* ISA has 3 operand loongson fused madd instructions of the form |
1155 | 'c = [+-] (a * b [+-] c)'. */ | |
1156 | #define ISA_HAS_FUSED_MADD3 TARGET_LOONGSON_2EF | |
b51469a5 | 1157 | |
287c5d38 MR |
1158 | /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The |
1159 | MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when | |
1160 | doubles are stored in pairs of FPRs, so for safety's sake, we apply | |
1161 | this restriction to the MIPS IV ISA too. */ | |
1162 | #define ISA_HAS_FP_RECIP_RSQRT(MODE) \ | |
7cfe3cc1 | 1163 | (((ISA_HAS_FP4 \ |
287c5d38 MR |
1164 | && ((MODE) == SFmode \ |
1165 | || ((TARGET_FLOAT64 \ | |
ad782bc9 | 1166 | || mips_isa_rev >= 2) \ |
287c5d38 | 1167 | && (MODE) == DFmode))) \ |
82f84ecb MF |
1168 | || (((MODE) == SFmode \ |
1169 | || (MODE) == DFmode) \ | |
1170 | && (mips_isa_rev >= 6)) \ | |
287c5d38 MR |
1171 | || (TARGET_SB1 \ |
1172 | && (MODE) == V2SFmode)) \ | |
1173 | && !TARGET_MIPS16) | |
1174 | ||
82f84ecb MF |
1175 | #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16) |
1176 | ||
1177 | #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5) | |
1178 | ||
1179 | #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2) | |
1180 | ||
0e5a4ad8 | 1181 | /* ISA has count leading zeroes/ones instruction (not implemented). */ |
ad782bc9 | 1182 | #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16) |
0e5a4ad8 | 1183 | |
f70b5dbf | 1184 | /* ISA has count trailing zeroes/ones instruction. */ |
d6319811 CX |
1185 | #define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2) |
1186 | ||
5ce6f47b EC |
1187 | /* ISA has three operand multiply instructions that put |
1188 | the high part in an accumulator: mulhi or mulhiu. */ | |
3f07249e RS |
1189 | #define ISA_HAS_MULHI ((TARGET_MIPS5400 \ |
1190 | || TARGET_MIPS5500 \ | |
1191 | || TARGET_SR71K) \ | |
1192 | && !TARGET_MIPS16) | |
5ce6f47b | 1193 | |
d2ab0929 MR |
1194 | /* ISA has three operand multiply instructions that negate the |
1195 | result and put the result in an accumulator. */ | |
3f07249e RS |
1196 | #define ISA_HAS_MULS ((TARGET_MIPS5400 \ |
1197 | || TARGET_MIPS5500 \ | |
1198 | || TARGET_SR71K) \ | |
1199 | && !TARGET_MIPS16) | |
5ce6f47b | 1200 | |
d2ab0929 MR |
1201 | /* ISA has three operand multiply instructions that subtract the |
1202 | result from a 4th operand and put the result in an accumulator. */ | |
3f07249e RS |
1203 | #define ISA_HAS_MSAC ((TARGET_MIPS5400 \ |
1204 | || TARGET_MIPS5500 \ | |
1205 | || TARGET_SR71K) \ | |
1206 | && !TARGET_MIPS16) | |
1207 | ||
d2ab0929 MR |
1208 | /* ISA has three operand multiply instructions that add the result |
1209 | to a 4th operand and put the result in an accumulator. */ | |
3f07249e RS |
1210 | #define ISA_HAS_MACC ((TARGET_MIPS4120 \ |
1211 | || TARGET_MIPS4130 \ | |
1212 | || TARGET_MIPS5400 \ | |
1213 | || TARGET_MIPS5500 \ | |
1214 | || TARGET_SR71K) \ | |
1215 | && !TARGET_MIPS16) | |
5ce6f47b | 1216 | |
0ac40e7a | 1217 | /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */ |
3f07249e RS |
1218 | #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \ |
1219 | || TARGET_MIPS4130) \ | |
1220 | && !TARGET_MIPS16) | |
1221 | ||
1222 | /* ISA has the "ror" (rotate right) instructions. */ | |
ad782bc9 | 1223 | #define ISA_HAS_ROR ((mips_isa_rev >= 2 \ |
3f07249e RS |
1224 | || TARGET_MIPS5400 \ |
1225 | || TARGET_MIPS5500 \ | |
0aa222d1 SL |
1226 | || TARGET_SR71K \ |
1227 | || TARGET_SMARTMIPS) \ | |
3f07249e | 1228 | && !TARGET_MIPS16) |
5ce6f47b | 1229 | |
0f37323c RS |
1230 | /* ISA has the WSBH (word swap bytes within halfwords) instruction. |
1231 | 64-bit targets also provide DSBH and DSHD. */ | |
ad782bc9 | 1232 | #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16) |
0f37323c | 1233 | |
4dbe1556 | 1234 | /* ISA has data prefetch instructions. This controls use of 'pref'. */ |
8f2e3902 | 1235 | #define ISA_HAS_PREFETCH ((ISA_MIPS4 \ |
1a0f175d | 1236 | || TARGET_LOONGSON_2EF \ |
107eea2c | 1237 | || TARGET_MIPS5900 \ |
ad782bc9 | 1238 | || mips_isa_rev >= 1) \ |
8f2e3902 EC |
1239 | && !TARGET_MIPS16) |
1240 | ||
047b52f6 MF |
1241 | /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */ |
1242 | #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6) | |
82f84ecb | 1243 | |
4dbe1556 CD |
1244 | /* ISA has data indexed prefetch instructions. This controls use of |
1245 | 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. | |
1246 | (prefx is a cop1x instruction, so can only be used if FP is | |
1247 | enabled.) */ | |
d6319811 CX |
1248 | #define ISA_HAS_PREFETCHX (ISA_HAS_FP4 \ |
1249 | || TARGET_LOONGSON_EXT \ | |
1250 | || TARGET_LOONGSON_EXT2) | |
4dbe1556 | 1251 | |
8214bf98 RS |
1252 | /* True if trunc.w.s and trunc.w.d are real (not synthetic) |
1253 | instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d | |
1254 | also requires TARGET_DOUBLE_FLOAT. */ | |
1255 | #define ISA_HAS_TRUNC_W (!ISA_MIPS1) | |
1256 | ||
2d2a50c3 | 1257 | /* ISA includes the MIPS32r2 seb and seh instructions. */ |
ad782bc9 | 1258 | #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16) |
2d2a50c3 | 1259 | |
e689b870 | 1260 | /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */ |
ad782bc9 | 1261 | #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16) |
e689b870 | 1262 | |
85f65093 | 1263 | /* ISA has instructions for accessing top part of 64-bit fp regs. */ |
050af144 MF |
1264 | #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \ |
1265 | && mips_isa_rev >= 2) | |
6f428062 | 1266 | |
0aa222d1 | 1267 | /* ISA has lwxs instruction (load w/scaled index address. */ |
22c4c869 CM |
1268 | #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \ |
1269 | && !TARGET_MIPS16) | |
0aa222d1 | 1270 | |
770da00a AP |
1271 | /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */ |
1272 | #define ISA_HAS_LBX (TARGET_OCTEON2) | |
1273 | #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2) | |
1274 | #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2) | |
1275 | #define ISA_HAS_LHUX (TARGET_OCTEON2) | |
1276 | #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2) | |
1277 | #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT) | |
1278 | #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \ | |
1279 | && TARGET_64BIT) | |
1280 | ||
254d1646 RS |
1281 | /* The DSP ASE is available. */ |
1282 | #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16) | |
1283 | ||
1284 | /* Revision 2 of the DSP ASE is available. */ | |
1285 | #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16) | |
1286 | ||
6cf538da RS |
1287 | /* The MSA ASE is available. */ |
1288 | #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16) | |
1289 | ||
21c9500d RS |
1290 | /* True if the result of a load is not available to the next instruction. |
1291 | A nop will then be needed between instructions like "lw $4,..." | |
1292 | and "addiu $4,$4,1". */ | |
3f07249e | 1293 | #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \ |
21c9500d | 1294 | && !TARGET_MIPS3900 \ |
107eea2c | 1295 | && !TARGET_MIPS5900 \ |
22c4c869 CM |
1296 | && !TARGET_MIPS16 \ |
1297 | && !TARGET_MICROMIPS) | |
21c9500d RS |
1298 | |
1299 | /* Likewise mtc1 and mfc1. */ | |
4ecfc7e3 | 1300 | #define ISA_HAS_XFER_DELAY (mips_isa <= MIPS_ISA_MIPS3 \ |
107eea2c | 1301 | && !TARGET_MIPS5900 \ |
58684fa0 | 1302 | && !TARGET_LOONGSON_2EF) |
21c9500d RS |
1303 | |
1304 | /* Likewise floating-point comparisons. */ | |
4ecfc7e3 | 1305 | #define ISA_HAS_FCMP_DELAY (mips_isa <= MIPS_ISA_MIPS3 \ |
107eea2c | 1306 | && !TARGET_MIPS5900 \ |
58684fa0 | 1307 | && !TARGET_LOONGSON_2EF) |
21c9500d RS |
1308 | |
1309 | /* True if mflo and mfhi can be immediately followed by instructions | |
fdcf1e1e CD |
1310 | which write to the HI and LO registers. |
1311 | ||
1312 | According to MIPS specifications, MIPS ISAs I, II, and III need | |
1313 | (at least) two instructions between the reads of HI/LO and | |
1314 | instructions which write them, and later ISAs do not. Contradicting | |
1315 | the MIPS specifications, some MIPS IV processor user manuals (e.g. | |
1316 | the UM for the NEC Vr5000) document needing the instructions between | |
1317 | HI/LO reads and writes, as well. Therefore, we declare only MIPS32, | |
1318 | MIPS64 and later ISAs to have the interlocks, plus any specific | |
1319 | earlier-ISA CPUs for which CPU documentation declares that the | |
1320 | instructions are really interlocked. */ | |
ad782bc9 | 1321 | #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \ |
58684fa0 | 1322 | || TARGET_MIPS5500 \ |
107eea2c | 1323 | || TARGET_MIPS5900 \ |
58684fa0 | 1324 | || TARGET_LOONGSON_2EF) |
df770e04 DD |
1325 | |
1326 | /* ISA includes synci, jr.hb and jalr.hb. */ | |
ad782bc9 | 1327 | #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16) |
df770e04 | 1328 | |
8d2fc1c4 | 1329 | /* ISA includes sync. */ |
4ecfc7e3 | 1330 | #define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) && !TARGET_MIPS16) |
e9276c30 RS |
1331 | #define GENERATE_SYNC \ |
1332 | (target_flags_explicit & MASK_LLSC \ | |
1333 | ? TARGET_LLSC && !TARGET_MIPS16 \ | |
1334 | : ISA_HAS_SYNC) | |
8d2fc1c4 DD |
1335 | |
1336 | /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC | |
1337 | because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC | |
1338 | instructions. */ | |
4ecfc7e3 | 1339 | #define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 && !TARGET_MIPS16) |
e9276c30 RS |
1340 | #define GENERATE_LL_SC \ |
1341 | (target_flags_explicit & MASK_LLSC \ | |
1342 | ? TARGET_LLSC && !TARGET_MIPS16 \ | |
1343 | : ISA_HAS_LL_SC) | |
d97e6aca | 1344 | |
6399761a TV |
1345 | #define ISA_HAS_SWAP (TARGET_XLP) |
1346 | #define ISA_HAS_LDADD (TARGET_XLP) | |
1347 | ||
7846e5f9 | 1348 | /* ISA includes the baddu instruction. */ |
aa5409e7 | 1349 | #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16) |
7846e5f9 | 1350 | |
95f6fc60 | 1351 | /* ISA includes the bbit* instructions. */ |
aa5409e7 | 1352 | #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16) |
95f6fc60 | 1353 | |
49912bcd | 1354 | /* ISA includes the cins instruction. */ |
aa5409e7 | 1355 | #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16) |
49912bcd | 1356 | |
c8424132 | 1357 | /* ISA includes the exts instruction. */ |
aa5409e7 | 1358 | #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16) |
c8424132 | 1359 | |
5299815b | 1360 | /* ISA includes the seq and sne instructions. */ |
aa5409e7 | 1361 | #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16) |
5299815b | 1362 | |
d97e6aca | 1363 | /* ISA includes the pop instruction. */ |
aa5409e7 | 1364 | #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) |
4d210b07 RS |
1365 | |
1366 | /* The CACHE instruction is available in non-MIPS16 code. */ | |
4ecfc7e3 | 1367 | #define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3) |
4d210b07 RS |
1368 | |
1369 | /* The CACHE instruction is available. */ | |
1370 | #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16) | |
e75b25e7 | 1371 | \f |
59c94430 MM |
1372 | /* Tell collect what flags to pass to nm. */ |
1373 | #ifndef NM_FLAGS | |
2ce3c6c6 | 1374 | #define NM_FLAGS "-Bn" |
59c94430 MM |
1375 | #endif |
1376 | ||
e75b25e7 | 1377 | \f |
4e88bbcd | 1378 | /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to |
5811cb27 RS |
1379 | the assembler. It may be overridden by subtargets. |
1380 | ||
1381 | Beginning with gas 2.13, -mdebug must be passed to correctly handle | |
1382 | COFF debugging info. */ | |
1383 | ||
4e88bbcd ILT |
1384 | #ifndef SUBTARGET_ASM_DEBUGGING_SPEC |
1385 | #define SUBTARGET_ASM_DEBUGGING_SPEC "\ | |
bb98bc58 JW |
1386 | %{g} %{g0} %{g1} %{g2} %{g3} \ |
1387 | %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \ | |
1388 | %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \ | |
180295ed | 1389 | %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3}" |
4e88bbcd | 1390 | #endif |
bb98bc58 | 1391 | |
aa0c464a MF |
1392 | /* FP_ASM_SPEC represents the floating-point options that must be passed |
1393 | to the assembler when FPXX support exists. Prior to that point the | |
1394 | assembler could accept the options but were not required for | |
1395 | correctness. We only add the options when absolutely necessary | |
1396 | because passing -msoft-float to the assembler will cause it to reject | |
1397 | all hard-float instructions which may require some user code to be | |
1398 | updated. */ | |
1399 | ||
1400 | #ifdef HAVE_AS_DOT_MODULE | |
1401 | #define FP_ASM_SPEC "\ | |
1402 | %{mhard-float} %{msoft-float} \ | |
1403 | %{msingle-float} %{mdouble-float}" | |
1404 | #else | |
1405 | #define FP_ASM_SPEC | |
1406 | #endif | |
1407 | ||
4e88bbcd ILT |
1408 | /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be |
1409 | overridden by subtargets. */ | |
1410 | ||
1411 | #ifndef SUBTARGET_ASM_SPEC | |
1412 | #define SUBTARGET_ASM_SPEC "" | |
bb98bc58 | 1413 | #endif |
4e88bbcd | 1414 | |
b2bcb32d | 1415 | #undef ASM_SPEC |
4e88bbcd | 1416 | #define ASM_SPEC "\ |
2d2a50c3 | 1417 | %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \ |
f2d6ca50 | 1418 | %{mips32*} %{mips64*} \ |
500fc425 | 1419 | %{mips16} %{mno-mips16:-no-mips16} \ |
22c4c869 | 1420 | %{mmicromips} %{mno-micromips} \ |
500fc425 TS |
1421 | %{mips3d} %{mno-mips3d:-no-mips3d} \ |
1422 | %{mdmx} %{mno-mdmx:-no-mdmx} \ | |
1423 | %{mdsp} %{mno-dsp} \ | |
1424 | %{mdspr2} %{mno-dspr2} \ | |
5cb5a23f | 1425 | %{mmcu} %{mno-mcu} \ |
44b20bb8 | 1426 | %{meva} %{mno-eva} \ |
0a39d07b | 1427 | %{mvirt} %{mno-virt} \ |
35773f53 | 1428 | %{mxpa} %{mno-xpa} \ |
9e9e6264 MF |
1429 | %{mcrc} %{mno-crc} \ |
1430 | %{mginv} %{mno-ginv} \ | |
6cf538da | 1431 | %{mmsa} %{mno-msa} \ |
8ae8bad7 | 1432 | %{mloongson-mmi} %{mno-loongson-mmi} \ |
375899d9 | 1433 | %{mloongson-ext} %{mno-loongson-ext} \ |
d6319811 | 1434 | %{mloongson-ext2} %{mno-loongson-ext2} \ |
0aa222d1 | 1435 | %{msmartmips} %{mno-smartmips} \ |
500fc425 | 1436 | %{mmt} %{mno-mt} \ |
fb51a3a8 | 1437 | %{mfix-r5900} %{mno-fix-r5900} \ |
faaa3afb | 1438 | %{mfix-rm7000} %{mno-fix-rm7000} \ |
0ac40e7a | 1439 | %{mfix-vr4120} %{mfix-vr4130} \ |
0eda4033 | 1440 | %{mfix-24k} \ |
29cedf8e | 1441 | %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \ |
4e88bbcd | 1442 | %(subtarget_asm_debugging_spec) \ |
e21d5757 | 1443 | %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \ |
ee692410 | 1444 | %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \ |
050af144 MF |
1445 | %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \ |
1446 | %{modd-spreg} %{mno-odd-spreg} \ | |
d9870b7e | 1447 | %{mshared} %{mno-shared} \ |
acda0e26 | 1448 | %{msym32} %{mno-sym32} \ |
aa0c464a MF |
1449 | %{mtune=*}" \ |
1450 | FP_ASM_SPEC "\ | |
4e88bbcd | 1451 | %(subtarget_asm_spec)" |
e75b25e7 | 1452 | |
31c714e3 | 1453 | /* Extra switches sometimes passed to the linker. */ |
e75b25e7 MM |
1454 | |
1455 | #ifndef LINK_SPEC | |
31c714e3 | 1456 | #define LINK_SPEC "\ |
120dc6cd | 1457 | %(endian_spec) \ |
f2d6ca50 | 1458 | %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \ |
368e0b39 | 1459 | %{shared}" |
0e5a4ad8 EC |
1460 | #endif /* LINK_SPEC defined */ |
1461 | ||
e75b25e7 MM |
1462 | |
1463 | /* Specs for the compiler proper */ | |
1464 | ||
c9db96ce JR |
1465 | /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be |
1466 | overridden by subtargets. */ | |
1467 | #ifndef SUBTARGET_CC1_SPEC | |
1468 | #define SUBTARGET_CC1_SPEC "" | |
1469 | #endif | |
1470 | ||
1471 | /* CC1_SPEC is the set of arguments to pass to the compiler proper. */ | |
1472 | ||
120311ec | 1473 | #undef CC1_SPEC |
31c714e3 | 1474 | #define CC1_SPEC "\ |
96abdcb1 | 1475 | %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \ |
4e314d1f | 1476 | %(subtarget_cc1_spec)" |
e75b25e7 | 1477 | |
4e88bbcd ILT |
1478 | /* Preprocessor specs. */ |
1479 | ||
4e88bbcd ILT |
1480 | /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be |
1481 | overridden by subtargets. */ | |
1482 | #ifndef SUBTARGET_CPP_SPEC | |
1483 | #define SUBTARGET_CPP_SPEC "" | |
1484 | #endif | |
1485 | ||
ce3649d2 | 1486 | #define CPP_SPEC "%(subtarget_cpp_spec)" |
4e88bbcd ILT |
1487 | |
1488 | /* This macro defines names of additional specifications to put in the specs | |
1489 | that can be used in various specifications like CC1_SPEC. Its definition | |
1490 | is an initializer with a subgrouping for each command option. | |
1491 | ||
1492 | Each subgrouping contains a string constant, that defines the | |
7ec022b2 | 1493 | specification name, and a string constant that used by the GCC driver |
4e88bbcd ILT |
1494 | program. |
1495 | ||
1496 | Do not define this macro if it does not need to do anything. */ | |
1497 | ||
1498 | #define EXTRA_SPECS \ | |
829245be KG |
1499 | { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \ |
1500 | { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ | |
829245be KG |
1501 | { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \ |
1502 | { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ | |
5811cb27 | 1503 | { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \ |
120dc6cd | 1504 | { "endian_spec", ENDIAN_SPEC }, \ |
4e88bbcd ILT |
1505 | SUBTARGET_EXTRA_SPECS |
1506 | ||
1507 | #ifndef SUBTARGET_EXTRA_SPECS | |
1508 | #define SUBTARGET_EXTRA_SPECS | |
e75b25e7 | 1509 | #endif |
e75b25e7 | 1510 | \f |
23532de9 | 1511 | #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */ |
deae8de6 EC |
1512 | #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */ |
1513 | ||
1514 | #ifndef PREFERRED_DEBUGGING_TYPE | |
1515 | #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG | |
1516 | #endif | |
e75b25e7 | 1517 | |
2e8a796f RS |
1518 | /* The size of DWARF addresses should be the same as the size of symbols |
1519 | in the target file format. They shouldn't depend on things like -msym32, | |
1520 | because many DWARF consumers do not allow the mixture of address sizes | |
1521 | that one would then get from linking -msym32 code with -msym64 code. | |
1522 | ||
1523 | Note that the default POINTER_SIZE test is not appropriate for MIPS. | |
1524 | EABI64 has 64-bit pointers but uses 32-bit ELF. */ | |
1525 | #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4) | |
d2beeae7 | 1526 | |
59c94430 MM |
1527 | /* By default, turn on GDB extensions. */ |
1528 | #define DEFAULT_GDB_EXTENSIONS 1 | |
1529 | ||
fb01ed38 MF |
1530 | /* Registers may have a prefix which can be ignored when matching |
1531 | user asm and register definitions. */ | |
1532 | #ifndef REGISTER_PREFIX | |
1533 | #define REGISTER_PREFIX "$" | |
1534 | #endif | |
1535 | ||
6ae1498b JW |
1536 | /* Local compiler-generated symbols must have a prefix that the assembler |
1537 | understands. By default, this is $, although some targets (e.g., | |
987ba558 | 1538 | NetBSD-ELF) need to override this. */ |
6ae1498b JW |
1539 | |
1540 | #ifndef LOCAL_LABEL_PREFIX | |
1541 | #define LOCAL_LABEL_PREFIX "$" | |
1542 | #endif | |
1543 | ||
1544 | /* By default on the mips, external symbols do not have an underscore | |
987ba558 | 1545 | prepended, but some targets (e.g., NetBSD) require this. */ |
6ae1498b JW |
1546 | |
1547 | #ifndef USER_LABEL_PREFIX | |
1548 | #define USER_LABEL_PREFIX "" | |
1549 | #endif | |
1550 | ||
e75b25e7 MM |
1551 | /* On Sun 4, this limit is 2048. We use 1500 to be safe, |
1552 | since the length can run past this up to a continuation point. */ | |
44404b8b | 1553 | #undef DBX_CONTIN_LENGTH |
e75b25e7 MM |
1554 | #define DBX_CONTIN_LENGTH 1500 |
1555 | ||
987ba558 | 1556 | /* How to renumber registers for dbx and gdb. */ |
48156a39 | 1557 | #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO] |
e75b25e7 | 1558 | |
dfad12b5 | 1559 | /* The mapping from gcc register number to DWARF 2 CFA column number. */ |
48156a39 | 1560 | #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO] |
c8cc5c4a JM |
1561 | |
1562 | /* The DWARF 2 CFA column which tracks the return address. */ | |
293593b1 | 1563 | #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM |
1f3d0661 | 1564 | |
469ac993 | 1565 | /* Before the prologue, RA lives in r31. */ |
240930c4 | 1566 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) |
469ac993 | 1567 | |
9e800206 | 1568 | /* Describe how we implement __builtin_eh_return. */ |
f1d5187e RS |
1569 | #define EH_RETURN_DATA_REGNO(N) \ |
1570 | ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM) | |
1571 | ||
9e800206 RH |
1572 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3) |
1573 | ||
0c433c31 RS |
1574 | #define EH_USES(N) mips_eh_uses (N) |
1575 | ||
7dac2f89 | 1576 | /* Offsets recorded in opcodes are a multiple of this alignment factor. |
b3276c7a GK |
1577 | The default for this in 64-bit mode is 8, which causes problems with |
1578 | SFmode register saves. */ | |
85bfab36 | 1579 | #define DWARF_CIE_DATA_ALIGNMENT -4 |
b3276c7a | 1580 | |
ab78d4a8 MM |
1581 | /* Correct the offset of automatic variables and arguments. Note that |
1582 | the MIPS debug format wants all automatic variables and arguments | |
1583 | to be in terms of the virtual frame pointer (stack pointer before | |
1584 | any adjustment in the function), while the MIPS 3.0 linker wants | |
1585 | the frame pointer to be the stack pointer after the initial | |
1586 | adjustment. */ | |
e75b25e7 | 1587 | |
8f2e3902 | 1588 | #define DEBUGGER_AUTO_OFFSET(X) \ |
f5963e61 | 1589 | mips_debugger_offset (X, (HOST_WIDE_INT) 0) |
8f2e3902 | 1590 | #define DEBUGGER_ARG_OFFSET(OFFSET, X) \ |
f5963e61 | 1591 | mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET) |
e75b25e7 MM |
1592 | \f |
1593 | /* Target machine storage layout */ | |
1594 | ||
4851a75c | 1595 | #define BITS_BIG_ENDIAN 0 |
96abdcb1 | 1596 | #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
96abdcb1 | 1597 | #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) |
e75b25e7 | 1598 | |
876c09d3 | 1599 | #define MAX_BITS_PER_WORD 64 |
e75b25e7 MM |
1600 | |
1601 | /* Width of a word, in units (bytes). */ | |
456f6501 | 1602 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
3b831805 | 1603 | #ifndef IN_LIBGCC2 |
ef0e53ce | 1604 | #define MIN_UNITS_PER_WORD 4 |
3b831805 | 1605 | #endif |
876c09d3 | 1606 | |
6cf538da RS |
1607 | /* Width of a MSA vector register in bytes. */ |
1608 | #define UNITS_PER_MSA_REG 16 | |
1609 | /* Width of a MSA vector register in bits. */ | |
1610 | #define BITS_PER_MSA_REG (UNITS_PER_MSA_REG * BITS_PER_UNIT) | |
1611 | ||
876c09d3 | 1612 | /* For MIPS, width of a floating point register. */ |
456f6501 | 1613 | #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4) |
e75b25e7 | 1614 | |
e8ab09c1 SL |
1615 | /* The number of consecutive floating-point registers needed to store the |
1616 | largest format supported by the FPU. */ | |
1617 | #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2) | |
1618 | ||
1619 | /* The number of consecutive floating-point registers needed to store the | |
1620 | smallest format supported by the FPU. */ | |
1621 | #define MIN_FPRS_PER_FMT \ | |
050af144 | 1622 | (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT) |
3f26edaa | 1623 | |
8a381273 AO |
1624 | /* The largest size of value that can be held in floating-point |
1625 | registers and moved with a single instruction. */ | |
e8ab09c1 | 1626 | #define UNITS_PER_HWFPVALUE \ |
a38e0142 | 1627 | (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG) |
8a381273 AO |
1628 | |
1629 | /* The largest size of value that can be held in floating-point | |
1630 | registers. */ | |
0e808055 | 1631 | #define UNITS_PER_FPVALUE \ |
a38e0142 | 1632 | (TARGET_SOFT_FLOAT_ABI ? 0 \ |
0e808055 RS |
1633 | : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \ |
1634 | : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT) | |
4d72536e RS |
1635 | |
1636 | /* The number of bytes in a double. */ | |
1637 | #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT) | |
3f26edaa | 1638 | |
dfad12b5 | 1639 | /* Set the sizes of the core types. */ |
e75b25e7 | 1640 | #define SHORT_TYPE_SIZE 16 |
fb8136b2 | 1641 | #define INT_TYPE_SIZE 32 |
456f6501 | 1642 | #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32) |
923d630e | 1643 | #define LONG_LONG_TYPE_SIZE 64 |
e75b25e7 | 1644 | |
dfad12b5 | 1645 | #define FLOAT_TYPE_SIZE 32 |
e75b25e7 | 1646 | #define DOUBLE_TYPE_SIZE 64 |
7f9be256 | 1647 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64) |
8a381273 | 1648 | |
9fc777ad CF |
1649 | /* Define the sizes of fixed-point types. */ |
1650 | #define SHORT_FRACT_TYPE_SIZE 8 | |
1651 | #define FRACT_TYPE_SIZE 16 | |
1652 | #define LONG_FRACT_TYPE_SIZE 32 | |
1653 | #define LONG_LONG_FRACT_TYPE_SIZE 64 | |
1654 | ||
1655 | #define SHORT_ACCUM_TYPE_SIZE 16 | |
1656 | #define ACCUM_TYPE_SIZE 32 | |
1657 | #define LONG_ACCUM_TYPE_SIZE 64 | |
1658 | /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC | |
1659 | doesn't support 128-bit integers for MIPS32 currently. */ | |
1660 | #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64) | |
1661 | ||
8a381273 AO |
1662 | /* long double is not a fixed mode, but the idea is that, if we |
1663 | support long double, we also want a 128-bit integer type. */ | |
1664 | #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE | |
1665 | ||
cafe096b | 1666 | /* Width in bits of a pointer. */ |
1eeed24e | 1667 | #ifndef POINTER_SIZE |
cafe096b | 1668 | #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32) |
1eeed24e | 1669 | #endif |
e75b25e7 | 1670 | |
e75b25e7 | 1671 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
e64ca6c4 | 1672 | #define PARM_BOUNDARY BITS_PER_WORD |
cafe096b | 1673 | |
e75b25e7 MM |
1674 | /* Allocation boundary (in *bits*) for the code of a function. */ |
1675 | #define FUNCTION_BOUNDARY 32 | |
1676 | ||
1677 | /* Alignment of field after `int : 0' in a structure. */ | |
9e95597a | 1678 | #define EMPTY_FIELD_BOUNDARY 32 |
e75b25e7 MM |
1679 | |
1680 | /* Every structure's size must be a multiple of this. */ | |
1681 | /* 8 is observed right on a DECstation and on riscos 4.02. */ | |
1682 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
1683 | ||
6cf538da RS |
1684 | /* There is no point aligning anything to a rounder boundary than |
1685 | LONG_DOUBLE_TYPE_SIZE, unless under MSA the bigggest alignment is | |
1686 | BITS_PER_MSA_REG. */ | |
1687 | #define BIGGEST_ALIGNMENT \ | |
1688 | (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE) | |
e75b25e7 | 1689 | |
dfad12b5 | 1690 | /* All accesses must be aligned. */ |
30a08286 | 1691 | #define STRICT_ALIGNMENT (!ISA_HAS_UNALIGNED_ACCESS) |
e75b25e7 MM |
1692 | |
1693 | /* Define this if you wish to imitate the way many other C compilers | |
1694 | handle alignment of bitfields and the structures that contain | |
1695 | them. | |
1696 | ||
43a88a8c | 1697 | The behavior is that the type written for a bit-field (`int', |
e75b25e7 MM |
1698 | `short', or other integer type) imposes an alignment for the |
1699 | entire structure, as if the structure really did contain an | |
43a88a8c | 1700 | ordinary field of that type. In addition, the bit-field is placed |
e75b25e7 MM |
1701 | within the structure so that it would fit within such a field, |
1702 | not crossing a boundary for it. | |
1703 | ||
43a88a8c | 1704 | Thus, on most machines, a bit-field whose type is written as `int' |
e75b25e7 MM |
1705 | would not cross a four-byte boundary, and would force four-byte |
1706 | alignment for the whole structure. (The alignment used may not | |
1707 | be four bytes; it is controlled by the other alignment | |
1708 | parameters.) | |
1709 | ||
1710 | If the macro is defined, its definition should be a C expression; | |
1711 | a nonzero value for the expression enables this behavior. */ | |
1712 | ||
1713 | #define PCC_BITFIELD_TYPE_MATTERS 1 | |
1714 | ||
e75b25e7 MM |
1715 | /* If defined, a C expression to compute the alignment for a static |
1716 | variable. TYPE is the data type, and ALIGN is the alignment that | |
1717 | the object would ordinarily have. The value of this macro is used | |
1718 | instead of that alignment to align the object. | |
1719 | ||
1720 | If this macro is not defined, then ALIGN is used. | |
1721 | ||
1722 | One use of this macro is to increase alignment of medium-size | |
1723 | data to make it all fit in fewer cache lines. Another is to | |
1724 | cause character arrays to be word-aligned so that `strcpy' calls | |
1725 | that copy constants to character arrays can be done inline. */ | |
1726 | ||
1727 | #undef DATA_ALIGNMENT | |
1728 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
1729 | ((((ALIGN) < BITS_PER_WORD) \ | |
1730 | && (TREE_CODE (TYPE) == ARRAY_TYPE \ | |
1731 | || TREE_CODE (TYPE) == UNION_TYPE \ | |
1732 | || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) | |
1733 | ||
adb417d7 NS |
1734 | /* We need this for the same reason as DATA_ALIGNMENT, namely to cause |
1735 | character arrays to be word-aligned so that `strcpy' calls that copy | |
1736 | constants to character arrays can be done inline, and 'strcmp' can be | |
1737 | optimised to use word loads. */ | |
1738 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
1739 | DATA_ALIGNMENT (TYPE, ALIGN) | |
1740 | ||
648bb159 | 1741 | #define PAD_VARARGS_DOWN \ |
76b0cbf8 | 1742 | (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) |
f5c8ac96 | 1743 | |
9a63901f RK |
1744 | /* Define if operations between registers always perform the operation |
1745 | on the full register even if a narrower mode is specified. */ | |
9e11bfef | 1746 | #define WORD_REGISTER_OPERATIONS 1 |
9a63901f | 1747 | |
85f65093 | 1748 | /* When in 64-bit mode, move insns will sign extend SImode and CCmode |
dab66575 | 1749 | moves. All other references are zero extended. */ |
a872728c JL |
1750 | #define LOAD_EXTEND_OP(MODE) \ |
1751 | (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \ | |
1752 | ? SIGN_EXTEND : ZERO_EXTEND) | |
2bcb2ab3 GK |
1753 | |
1754 | /* Define this macro if it is advisable to hold scalars in registers | |
7dac2f89 | 1755 | in a wider mode than that declared by the program. In such cases, |
2bcb2ab3 GK |
1756 | the value is constrained to be within the bounds of the declared |
1757 | type, but kept valid in the wider mode. The signedness of the | |
cafe096b | 1758 | extension may differ from that of the type. */ |
2bcb2ab3 GK |
1759 | |
1760 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
1761 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
cafe096b EC |
1762 | && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ |
1763 | { \ | |
1764 | if ((MODE) == SImode) \ | |
1765 | (UNSIGNEDP) = 0; \ | |
1766 | (MODE) = Pmode; \ | |
1767 | } | |
1768 | ||
0dc31782 RS |
1769 | /* Pmode is always the same as ptr_mode, but not always the same as word_mode. |
1770 | Extensions of pointers to word_mode must be signed. */ | |
1771 | #define POINTERS_EXTEND_UNSIGNED false | |
1772 | ||
cafe096b | 1773 | /* Define if loading short immediate values into registers sign extends. */ |
58f2ae18 | 1774 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
09d8cc0e ILT |
1775 | |
1776 | /* The [d]clz instructions have the natural values at 0. */ | |
1777 | ||
1778 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ | |
6cf538da | 1779 | ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) |
e75b25e7 MM |
1780 | \f |
1781 | /* Standard register usage. */ | |
1782 | ||
dfad12b5 | 1783 | /* Number of hardware registers. We have: |
e75b25e7 | 1784 | |
dfad12b5 RS |
1785 | - 32 integer registers |
1786 | - 32 floating point registers | |
1787 | - 8 condition code registers | |
1788 | - 2 accumulator registers (hi and lo) | |
1789 | - 32 registers each for coprocessors 0, 2 and 3 | |
0c433c31 | 1790 | - 4 fake registers: |
bcbc6b7f RS |
1791 | - ARG_POINTER_REGNUM |
1792 | - FRAME_POINTER_REGNUM | |
dbc90b65 | 1793 | - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details) |
0c433c31 RS |
1794 | - CPRESTORE_SLOT_REGNUM |
1795 | - 2 dummy entries that were used at various times in the past. | |
118ea793 CF |
1796 | - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE |
1797 | - 6 DSP control registers */ | |
e75b25e7 | 1798 | |
118ea793 | 1799 | #define FIRST_PSEUDO_REGISTER 188 |
e75b25e7 | 1800 | |
dfad12b5 RS |
1801 | /* By default, fix the kernel registers ($26 and $27), the global |
1802 | pointer ($28) and the stack pointer ($29). This can change | |
1803 | depending on the command-line options. | |
e75b25e7 | 1804 | |
dfad12b5 | 1805 | Regarding coprocessor registers: without evidence to the contrary, |
d604bca3 | 1806 | it's best to assume that each coprocessor register has a unique |
525c561d | 1807 | use. This can be overridden, in, e.g., mips_option_override or |
5efd84c5 NF |
1808 | TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be |
1809 | inappropriate for a particular target. */ | |
d604bca3 | 1810 | |
e75b25e7 MM |
1811 | #define FIXED_REGISTERS \ |
1812 | { \ | |
1813 | 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
cafe096b | 1814 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ |
e75b25e7 MM |
1815 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1816 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
d334c3c1 | 1817 | 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \ |
d604bca3 MH |
1818 | /* COP0 registers */ \ |
1819 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1820 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1821 | /* COP2 registers */ \ | |
1822 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1823 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1824 | /* COP3 registers */ \ | |
1825 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
118ea793 CF |
1826 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ |
1827 | /* 6 DSP accumulator registers & 6 control registers */ \ | |
1828 | 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \ | |
e75b25e7 MM |
1829 | } |
1830 | ||
1831 | ||
dfad12b5 RS |
1832 | /* Set up this array for o32 by default. |
1833 | ||
1834 | Note that we don't mark $31 as a call-clobbered register. The idea is | |
1835 | that it's really the call instructions themselves which clobber $31. | |
cafe096b EC |
1836 | We don't care what the called function does with it afterwards. |
1837 | ||
1838 | This approach makes it easier to implement sibcalls. Unlike normal | |
1839 | calls, sibcalls don't clobber $31, so the register reaches the | |
1840 | called function in tact. EPILOGUE_USES says that $31 is useful | |
1841 | to the called function. */ | |
e75b25e7 | 1842 | |
2ca2d9ee EC |
1843 | #define CALL_REALLY_USED_REGISTERS \ |
1844 | { /* General registers. */ \ | |
1845 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
cafe096b | 1846 | 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \ |
2ca2d9ee EC |
1847 | /* Floating-point registers. */ \ |
1848 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ | |
1849 | 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1850 | /* Others. */ \ | |
dbc90b65 | 1851 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \ |
d604bca3 MH |
1852 | /* COP0 registers */ \ |
1853 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1854 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1855 | /* COP2 registers */ \ | |
1856 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1857 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
1858 | /* COP3 registers */ \ | |
1859 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
118ea793 CF |
1860 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
1861 | /* 6 DSP accumulator registers & 6 control registers */ \ | |
1862 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \ | |
2ca2d9ee | 1863 | } |
e75b25e7 MM |
1864 | |
1865 | /* Internal macros to classify a register number as to whether it's a | |
1866 | general purpose register, a floating point register, a | |
516a2dfd | 1867 | multiply/divide register, or a status register. */ |
e75b25e7 MM |
1868 | |
1869 | #define GP_REG_FIRST 0 | |
1870 | #define GP_REG_LAST 31 | |
1871 | #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) | |
1872 | #define GP_DBX_FIRST 0 | |
e19da24c CF |
1873 | #define K0_REG_NUM (GP_REG_FIRST + 26) |
1874 | #define K1_REG_NUM (GP_REG_FIRST + 27) | |
1875 | #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM)) | |
e75b25e7 MM |
1876 | |
1877 | #define FP_REG_FIRST 32 | |
1878 | #define FP_REG_LAST 63 | |
1879 | #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) | |
1880 | #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32) | |
1881 | ||
1882 | #define MD_REG_FIRST 64 | |
d334c3c1 | 1883 | #define MD_REG_LAST 65 |
e75b25e7 | 1884 | #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1) |
77d4f3a4 | 1885 | #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM) |
e75b25e7 | 1886 | |
6cf538da RS |
1887 | #define MSA_REG_FIRST FP_REG_FIRST |
1888 | #define MSA_REG_LAST FP_REG_LAST | |
1889 | #define MSA_REG_NUM FP_REG_NUM | |
1890 | ||
aa3e18a0 DD |
1891 | /* The DWARF 2 CFA column which tracks the return address from a |
1892 | signal handler context. This means that to maintain backwards | |
1893 | compatibility, no hard register can be assigned this column if it | |
1894 | would need to be handled by the DWARF unwinder. */ | |
1895 | #define DWARF_ALT_FRAME_RETURN_COLUMN 66 | |
1896 | ||
225b8835 | 1897 | #define ST_REG_FIRST 67 |
b8eb88d0 | 1898 | #define ST_REG_LAST 74 |
e75b25e7 MM |
1899 | #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1) |
1900 | ||
39dffea3 | 1901 | |
cafe096b | 1902 | /* FIXME: renumber. */ |
d604bca3 MH |
1903 | #define COP0_REG_FIRST 80 |
1904 | #define COP0_REG_LAST 111 | |
1905 | #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1) | |
1906 | ||
e19da24c CF |
1907 | #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12) |
1908 | #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13) | |
1909 | #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14) | |
1910 | ||
d604bca3 MH |
1911 | #define COP2_REG_FIRST 112 |
1912 | #define COP2_REG_LAST 143 | |
1913 | #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1) | |
1914 | ||
1915 | #define COP3_REG_FIRST 144 | |
1916 | #define COP3_REG_LAST 175 | |
1917 | #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1) | |
2cd45f0e SE |
1918 | |
1919 | /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */ | |
1920 | #define ALL_COP_REG_FIRST COP0_REG_FIRST | |
1921 | #define ALL_COP_REG_LAST COP3_REG_LAST | |
1922 | #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1) | |
d604bca3 | 1923 | |
118ea793 CF |
1924 | #define DSP_ACC_REG_FIRST 176 |
1925 | #define DSP_ACC_REG_LAST 181 | |
1926 | #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1) | |
1927 | ||
e75b25e7 | 1928 | #define AT_REGNUM (GP_REG_FIRST + 1) |
48156a39 NS |
1929 | #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1) |
1930 | #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST) | |
b8eb88d0 | 1931 | |
e19da24c CF |
1932 | /* A few bitfield locations for the coprocessor registers. */ |
1933 | /* Request Interrupt Priority Level is from bit 10 to bit 15 of | |
1934 | the cause register for the EIC interrupt mode. */ | |
1935 | #define CAUSE_IPL 10 | |
6a2b848b RS |
1936 | /* COP1 Enable is at bit 29 of the status register. */ |
1937 | #define SR_COP1 29 | |
e19da24c CF |
1938 | /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */ |
1939 | #define SR_IPL 10 | |
0256a844 MF |
1940 | /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status |
1941 | register. */ | |
1942 | #define SR_IM0 8 | |
e19da24c CF |
1943 | /* Exception Level is at bit 1 of the status register. */ |
1944 | #define SR_EXL 1 | |
1945 | /* Interrupt Enable is at bit 0 of the status register. */ | |
1946 | #define SR_IE 0 | |
1947 | ||
dfad12b5 RS |
1948 | /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC. |
1949 | If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG | |
b8eb88d0 | 1950 | should be used instead. */ |
e75b25e7 MM |
1951 | #define FPSW_REGNUM ST_REG_FIRST |
1952 | ||
75131237 RK |
1953 | #define GP_REG_P(REGNO) \ |
1954 | ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM) | |
2bcb2ab3 GK |
1955 | #define M16_REG_P(REGNO) \ |
1956 | (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17) | |
22c4c869 CM |
1957 | #define M16STORE_REG_P(REGNO) \ |
1958 | (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17) | |
75131237 RK |
1959 | #define FP_REG_P(REGNO) \ |
1960 | ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM) | |
1961 | #define MD_REG_P(REGNO) \ | |
1962 | ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM) | |
1963 | #define ST_REG_P(REGNO) \ | |
1964 | ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM) | |
d604bca3 MH |
1965 | #define COP0_REG_P(REGNO) \ |
1966 | ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM) | |
1967 | #define COP2_REG_P(REGNO) \ | |
1968 | ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM) | |
1969 | #define COP3_REG_P(REGNO) \ | |
1970 | ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM) | |
1971 | #define ALL_COP_REG_P(REGNO) \ | |
1972 | ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM) | |
118ea793 CF |
1973 | /* Test if REGNO is one of the 6 new DSP accumulators. */ |
1974 | #define DSP_ACC_REG_P(REGNO) \ | |
1975 | ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM) | |
1976 | /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */ | |
1977 | #define ACC_REG_P(REGNO) \ | |
1978 | (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO)) | |
6cf538da RS |
1979 | #define MSA_REG_P(REGNO) \ |
1980 | ((unsigned int) ((int) (REGNO) - MSA_REG_FIRST) < MSA_REG_NUM) | |
d604bca3 | 1981 | |
66083422 | 1982 | #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X))) |
6cf538da | 1983 | #define MSA_REG_RTX_P(X) (REG_P (X) && MSA_REG_P (REGNO (X))) |
5b0f0db6 | 1984 | |
96a30b18 RS |
1985 | /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used |
1986 | to initialize the mips16 gp pseudo register. */ | |
1987 | #define CONST_GP_P(X) \ | |
1988 | (GET_CODE (X) == CONST \ | |
1989 | && GET_CODE (XEXP (X, 0)) == UNSPEC \ | |
1990 | && XINT (XEXP (X, 0), 1) == UNSPEC_GP) | |
1991 | ||
d604bca3 MH |
1992 | /* Return coprocessor number from register number. */ |
1993 | ||
1994 | #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \ | |
1995 | (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \ | |
1996 | : COP3_REG_P (REGNO) ? '3' : '?') | |
e75b25e7 | 1997 | |
e75b25e7 | 1998 | |
ec8a2131 RS |
1999 | #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ |
2000 | mips_hard_regno_rename_ok (OLD_REG, NEW_REG) | |
2001 | ||
050af144 MF |
2002 | /* Select a register mode required for caller save of hard regno REGNO. */ |
2003 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ | |
2004 | mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE) | |
2005 | ||
e75b25e7 | 2006 | /* Register to use for pushing function arguments. */ |
0fb5ac6f | 2007 | #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29) |
e75b25e7 | 2008 | |
bcbc6b7f RS |
2009 | /* These two registers don't really exist: they get eliminated to either |
2010 | the stack or hard frame pointer. */ | |
2011 | #define ARG_POINTER_REGNUM 77 | |
2012 | #define FRAME_POINTER_REGNUM 78 | |
2bcb2ab3 GK |
2013 | |
2014 | /* $30 is not available on the mips16, so we use $17 as the frame | |
2015 | pointer. */ | |
2016 | #define HARD_FRAME_POINTER_REGNUM \ | |
2017 | (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30) | |
e75b25e7 | 2018 | |
e3339d0f JM |
2019 | #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 |
2020 | #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 | |
2021 | ||
e75b25e7 | 2022 | /* Register in which static-chain is passed to a function. */ |
e538e028 | 2023 | #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15) |
e75b25e7 | 2024 | |
08d0963a | 2025 | /* Registers used as temporaries in prologue/epilogue code: |
be763023 | 2026 | |
08d0963a RS |
2027 | - If a MIPS16 PIC function needs access to _gp, it first loads |
2028 | the value into MIPS16_PIC_TEMP and then copies it to $gp. | |
2029 | ||
2030 | - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary | |
2031 | register. The register must not conflict with MIPS16_PIC_TEMP. | |
2032 | ||
3b601ca3 EB |
2033 | - If we aren't generating MIPS16 code, the prologue can also use |
2034 | MIPS_PROLOGUE_TEMP2 as a general temporary register. | |
2035 | ||
08d0963a RS |
2036 | - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary |
2037 | register. | |
2038 | ||
2039 | If we're generating MIPS16 code, these registers must come from the | |
2040 | core set of 8. The prologue registers mustn't conflict with any | |
2041 | incoming arguments, the static chain pointer, or the frame pointer. | |
2042 | The epilogue temporary mustn't conflict with the return registers, | |
2043 | the PIC call register ($25), the frame pointer, the EH stack adjustment, | |
e19da24c CF |
2044 | or the EH data registers. |
2045 | ||
2046 | If we're generating interrupt handlers, we use K0 as a temporary register | |
2047 | in prologue/epilogue code. */ | |
08d0963a RS |
2048 | |
2049 | #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2) | |
e19da24c CF |
2050 | #define MIPS_PROLOGUE_TEMP_REGNUM \ |
2051 | (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3) | |
3b601ca3 EB |
2052 | #define MIPS_PROLOGUE_TEMP2_REGNUM \ |
2053 | (TARGET_MIPS16 \ | |
2054 | ? (gcc_unreachable (), INVALID_REGNUM) \ | |
2055 | : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12) | |
e19da24c CF |
2056 | #define MIPS_EPILOGUE_TEMP_REGNUM \ |
2057 | (cfun->machine->interrupt_handler_p \ | |
2058 | ? K0_REG_NUM \ | |
2059 | : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8)) | |
be763023 | 2060 | |
08d0963a | 2061 | #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM) |
be763023 | 2062 | #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM) |
3b601ca3 EB |
2063 | #define MIPS_PROLOGUE_TEMP2(MODE) \ |
2064 | gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM) | |
be763023 | 2065 | #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM) |
e75b25e7 MM |
2066 | |
2067 | /* Define this macro if it is as good or better to call a constant | |
2068 | function address than to call an address kept in a register. */ | |
2069 | #define NO_FUNCTION_CSE 1 | |
2070 | ||
f833ffd4 RS |
2071 | /* The ABI-defined global pointer. Sometimes we use a different |
2072 | register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */ | |
2073 | #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28) | |
2074 | ||
2075 | /* We normally use $28 as the global pointer. However, when generating | |
2076 | n32/64 PIC, it is better for leaf functions to use a call-clobbered | |
2077 | register instead. They can then avoid saving and restoring $28 | |
2078 | and perhaps avoid using a frame at all. | |
2079 | ||
2080 | When a leaf function uses something other than $28, mips_expand_prologue | |
2081 | will modify pic_offset_table_rtx in place. Take the register number | |
2082 | from there after reload. */ | |
2083 | #define PIC_OFFSET_TABLE_REGNUM \ | |
2084 | (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM) | |
e75b25e7 MM |
2085 | \f |
2086 | /* Define the classes of registers for register constraints in the | |
2087 | machine description. Also define ranges of constants. | |
2088 | ||
2089 | One of the classes must always be named ALL_REGS and include all hard regs. | |
2090 | If there is more than one class, another class must be named NO_REGS | |
2091 | and contain no registers. | |
2092 | ||
2093 | The name GENERAL_REGS must be the name of a class (or an alias for | |
2094 | another name such as ALL_REGS). This is the class of registers | |
2095 | that is allowed by "g" or "r" in a register constraint. | |
2096 | Also, registers outside this class are allocated only when | |
2097 | instructions express preferences for them. | |
2098 | ||
2099 | The classes must be numbered in nondecreasing order; that is, | |
2100 | a larger-numbered class must never be contained completely | |
2101 | in a smaller-numbered class. | |
2102 | ||
2103 | For any two classes, it is very desirable that there be another | |
2104 | class that represents their union. */ | |
2105 | ||
2106 | enum reg_class | |
2107 | { | |
2108 | NO_REGS, /* no registers in set */ | |
5e7d8b4c | 2109 | M16_STORE_REGS, /* microMIPS store registers */ |
2bcb2ab3 | 2110 | M16_REGS, /* mips16 directly accessible registers */ |
a78cc314 | 2111 | M16_SP_REGS, /* mips16 + $sp */ |
2bcb2ab3 GK |
2112 | T_REG, /* mips16 T register ($24) */ |
2113 | M16_T_REGS, /* mips16 registers plus T register */ | |
cafe096b | 2114 | PIC_FN_ADDR_REG, /* SVR4 PIC function address register */ |
2feaae20 | 2115 | V1_REG, /* Register $v1 ($3) used for TLS access. */ |
a78cc314 | 2116 | SPILL_REGS, /* All but $sp and call preserved regs are in here */ |
cafe096b | 2117 | LEA_REGS, /* Every GPR except $25 */ |
e75b25e7 MM |
2118 | GR_REGS, /* integer registers */ |
2119 | FP_REGS, /* floating point registers */ | |
48156a39 NS |
2120 | MD0_REG, /* first multiply/divide register */ |
2121 | MD1_REG, /* second multiply/divide register */ | |
e75b25e7 | 2122 | MD_REGS, /* multiply/divide registers (hi/lo) */ |
d604bca3 MH |
2123 | COP0_REGS, /* generic coprocessor classes */ |
2124 | COP2_REGS, | |
2125 | COP3_REGS, | |
e75b25e7 | 2126 | ST_REGS, /* status registers (fp status) */ |
118ea793 CF |
2127 | DSP_ACC_REGS, /* DSP accumulator registers */ |
2128 | ACC_REGS, /* Hi/Lo and DSP accumulator registers */ | |
7314c7dd | 2129 | FRAME_REGS, /* $arg and $frame */ |
5c0a2e3a RS |
2130 | GR_AND_MD0_REGS, /* union classes */ |
2131 | GR_AND_MD1_REGS, | |
2132 | GR_AND_MD_REGS, | |
2133 | GR_AND_ACC_REGS, | |
e75b25e7 MM |
2134 | ALL_REGS, /* all registers */ |
2135 | LIM_REG_CLASSES /* max value + 1 */ | |
2136 | }; | |
2137 | ||
2138 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
2139 | ||
2140 | #define GENERAL_REGS GR_REGS | |
2141 | ||
2142 | /* An initializer containing the names of the register classes as C | |
2143 | string constants. These names are used in writing some of the | |
2144 | debugging dumps. */ | |
2145 | ||
2146 | #define REG_CLASS_NAMES \ | |
2147 | { \ | |
2148 | "NO_REGS", \ | |
5e7d8b4c | 2149 | "M16_STORE_REGS", \ |
2bcb2ab3 | 2150 | "M16_REGS", \ |
a78cc314 | 2151 | "M16_SP_REGS", \ |
2bcb2ab3 GK |
2152 | "T_REG", \ |
2153 | "M16_T_REGS", \ | |
cafe096b | 2154 | "PIC_FN_ADDR_REG", \ |
2feaae20 | 2155 | "V1_REG", \ |
a78cc314 | 2156 | "SPILL_REGS", \ |
cafe096b | 2157 | "LEA_REGS", \ |
e75b25e7 MM |
2158 | "GR_REGS", \ |
2159 | "FP_REGS", \ | |
48156a39 NS |
2160 | "MD0_REG", \ |
2161 | "MD1_REG", \ | |
e75b25e7 | 2162 | "MD_REGS", \ |
d604bca3 MH |
2163 | /* coprocessor registers */ \ |
2164 | "COP0_REGS", \ | |
2165 | "COP2_REGS", \ | |
2166 | "COP3_REGS", \ | |
e75b25e7 | 2167 | "ST_REGS", \ |
118ea793 CF |
2168 | "DSP_ACC_REGS", \ |
2169 | "ACC_REGS", \ | |
7314c7dd | 2170 | "FRAME_REGS", \ |
5c0a2e3a RS |
2171 | "GR_AND_MD0_REGS", \ |
2172 | "GR_AND_MD1_REGS", \ | |
2173 | "GR_AND_MD_REGS", \ | |
2174 | "GR_AND_ACC_REGS", \ | |
e75b25e7 MM |
2175 | "ALL_REGS" \ |
2176 | } | |
2177 | ||
2178 | /* An initializer containing the contents of the register classes, | |
2179 | as integers which are bit masks. The Nth integer specifies the | |
2180 | contents of class N. The way the integer MASK is interpreted is | |
2181 | that register R is in the class if `MASK & (1 << R)' is 1. | |
2182 | ||
2183 | When the machine has more than 32 registers, an integer does not | |
2184 | suffice. Then the integers are replaced by sub-initializers, | |
2185 | braced groupings containing several integers. Each | |
2186 | sub-initializer must be suitable as an initializer for the type | |
2187 | `HARD_REG_SET' which is defined in `hard-reg-set.h'. */ | |
2188 | ||
ec24a740 EC |
2189 | #define REG_CLASS_CONTENTS \ |
2190 | { \ | |
5c0a2e3a | 2191 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ |
5e7d8b4c | 2192 | { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \ |
5c0a2e3a | 2193 | { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \ |
a78cc314 | 2194 | { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \ |
5c0a2e3a RS |
2195 | { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \ |
2196 | { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \ | |
2197 | { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \ | |
2198 | { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \ | |
a78cc314 | 2199 | { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \ |
5c0a2e3a RS |
2200 | { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \ |
2201 | { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \ | |
2202 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \ | |
2203 | { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \ | |
2204 | { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \ | |
2205 | { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \ | |
2206 | { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \ | |
2207 | { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \ | |
2208 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \ | |
2209 | { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \ | |
2210 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \ | |
2211 | { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \ | |
2212 | { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \ | |
2213 | { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \ | |
2214 | { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \ | |
2215 | { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \ | |
2216 | { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \ | |
2217 | { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \ | |
e75b25e7 MM |
2218 | } |
2219 | ||
2220 | ||
2221 | /* A C expression whose value is a register class containing hard | |
2222 | register REGNO. In general there is more that one such class; | |
2223 | choose a class which is "minimal", meaning that no smaller class | |
2224 | also contains the register. */ | |
2225 | ||
e75b25e7 MM |
2226 | #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ] |
2227 | ||
2228 | /* A macro whose definition is the name of the class to which a | |
2229 | valid base register must belong. A base register is one used in | |
2230 | an address which is the register value plus a displacement. */ | |
2231 | ||
a78cc314 | 2232 | #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS) |
e75b25e7 MM |
2233 | |
2234 | /* A macro whose definition is the name of the class to which a | |
2235 | valid index register must belong. An index register is one used | |
2236 | in an address where its value is either multiplied by a scale | |
2237 | factor or added to another register (as well as added to a | |
2238 | displacement). */ | |
2239 | ||
876c09d3 | 2240 | #define INDEX_REG_CLASS NO_REGS |
e75b25e7 | 2241 | |
59dbe1d9 RS |
2242 | /* We generally want to put call-clobbered registers ahead of |
2243 | call-saved ones. (IRA expects this.) */ | |
2bcb2ab3 GK |
2244 | |
2245 | #define REG_ALLOC_ORDER \ | |
e08be11c RS |
2246 | { /* Accumulator registers. When GPRs and accumulators have equal \ |
2247 | cost, we generally prefer to use accumulators. For example, \ | |
2248 | a division of multiplication result is better allocated to LO, \ | |
2249 | so that we put the MFLO at the point of use instead of at the \ | |
2250 | point of definition. It's also needed if we're to take advantage \ | |
2251 | of the extra accumulators available with -mdspr2. In some cases, \ | |
2252 | it can also help to reduce register pressure. */ \ | |
2253 | 64, 65,176,177,178,179,180,181, \ | |
2254 | /* Call-clobbered GPRs. */ \ | |
2255 | 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ | |
59dbe1d9 RS |
2256 | 24, 25, 31, \ |
2257 | /* The global pointer. This is call-clobbered for o32 and o64 \ | |
2258 | abicalls, call-saved for n32 and n64 abicalls, and a program \ | |
2259 | invariant otherwise. Putting it between the call-clobbered \ | |
2260 | and call-saved registers should cope with all eventualities. */ \ | |
2261 | 28, \ | |
2262 | /* Call-saved GPRs. */ \ | |
2263 | 16, 17, 18, 19, 20, 21, 22, 23, 30, \ | |
2264 | /* GPRs that can never be exposed to the register allocator. */ \ | |
e08be11c | 2265 | 0, 26, 27, 29, \ |
59dbe1d9 | 2266 | /* Call-clobbered FPRs. */ \ |
2bcb2ab3 | 2267 | 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ |
59dbe1d9 RS |
2268 | 48, 49, 50, 51, \ |
2269 | /* FPRs that are usually call-saved. The odd ones are actually \ | |
2270 | call-clobbered for n32, but listing them ahead of the even \ | |
2271 | registers might encourage the register allocator to fragment \ | |
2272 | the available FPR pairs. We need paired FPRs to store long \ | |
2273 | doubles, so it isn't clear that using a different order \ | |
2274 | for n32 would be a win. */ \ | |
2275 | 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \ | |
2276 | /* None of the remaining classes have defined call-saved \ | |
2277 | registers. */ \ | |
e08be11c | 2278 | 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ |
d604bca3 MH |
2279 | 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \ |
2280 | 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \ | |
2281 | 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \ | |
2282 | 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \ | |
2283 | 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \ | |
118ea793 | 2284 | 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \ |
e08be11c | 2285 | 182,183,184,185,186,187 \ |
2bcb2ab3 GK |
2286 | } |
2287 | ||
569b7f6a | 2288 | /* True if VALUE is an unsigned 6-bit number. */ |
118ea793 CF |
2289 | |
2290 | #define UIMM6_OPERAND(VALUE) \ | |
2291 | (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0) | |
2292 | ||
2293 | /* True if VALUE is a signed 10-bit number. */ | |
2294 | ||
2295 | #define IMM10_OPERAND(VALUE) \ | |
2296 | ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400) | |
2297 | ||
cafe096b EC |
2298 | /* True if VALUE is a signed 16-bit number. */ |
2299 | ||
2300 | #define SMALL_OPERAND(VALUE) \ | |
2301 | ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000) | |
2302 | ||
2303 | /* True if VALUE is an unsigned 16-bit number. */ | |
2304 | ||
2305 | #define SMALL_OPERAND_UNSIGNED(VALUE) \ | |
2306 | (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) | |
2307 | ||
2308 | /* True if VALUE can be loaded into a register using LUI. */ | |
2309 | ||
2310 | #define LUI_OPERAND(VALUE) \ | |
2311 | (((VALUE) | 0x7fff0000) == 0x7fff0000 \ | |
2312 | || ((VALUE) | 0x7fff0000) + 0x10000 == 0) | |
2313 | ||
2314 | /* Return a value X with the low 16 bits clear, and such that | |
2315 | VALUE - X is a signed 16-bit value. */ | |
2316 | ||
2317 | #define CONST_HIGH_PART(VALUE) \ | |
2318 | (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff) | |
2319 | ||
2320 | #define CONST_LOW_PART(VALUE) \ | |
2321 | ((VALUE) - CONST_HIGH_PART (VALUE)) | |
2322 | ||
2323 | #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X)) | |
2324 | #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X)) | |
2325 | #define LUI_INT(X) LUI_OPERAND (INTVAL (X)) | |
22c4c869 | 2326 | #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047)) |
82f84ecb | 2327 | #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255)) |
cafe096b | 2328 | |
46299de9 | 2329 | /* The HI and LO registers can only be reloaded via the general |
b8eb88d0 ILT |
2330 | registers. Condition code registers can only be loaded to the |
2331 | general registers, and from the floating point registers. */ | |
46299de9 | 2332 | |
225b8835 | 2333 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
65239d20 | 2334 | mips_secondary_reload_class (CLASS, MODE, X, true) |
225b8835 | 2335 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ |
65239d20 | 2336 | mips_secondary_reload_class (CLASS, MODE, X, false) |
46299de9 | 2337 | |
e75b25e7 MM |
2338 | /* Return the maximum number of consecutive registers |
2339 | needed to represent mode MODE in a register of class CLASS. */ | |
2340 | ||
d604bca3 | 2341 | #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE) |
e75b25e7 MM |
2342 | \f |
2343 | /* Stack layout; function entry, exit and calling. */ | |
2344 | ||
62f9f30b | 2345 | #define STACK_GROWS_DOWNWARD 1 |
e75b25e7 | 2346 | |
e9230659 HPN |
2347 | #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ |
2348 | || (flag_sanitize & SANITIZE_ADDRESS) != 0) | |
b5411fea | 2349 | |
ba6adec4 AN |
2350 | /* Size of the area allocated in the frame to save the GP. */ |
2351 | ||
2352 | #define MIPS_GP_SAVE_AREA_SIZE \ | |
2353 | (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0) | |
2354 | ||
cafe096b | 2355 | #define RETURN_ADDR_RTX mips_return_addr |
39dffea3 | 2356 | |
57972505 RS |
2357 | /* Mask off the MIPS16 ISA bit in unwind addresses. |
2358 | ||
2359 | The reason for this is a little subtle. When unwinding a call, | |
2360 | we are given the call's return address, which on most targets | |
2361 | is the address of the following instruction. However, what we | |
2362 | actually want to find is the EH region for the call itself. | |
2363 | The target-independent unwind code therefore searches for "RA - 1". | |
2364 | ||
2365 | In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address. | |
2366 | RA - 1 is therefore the real (even-valued) start of the return | |
2367 | instruction. EH region labels are usually odd-valued MIPS16 symbols | |
2368 | too, so a search for an even address within a MIPS16 region would | |
2369 | usually work. | |
2370 | ||
2371 | However, there is an exception. If the end of an EH region is also | |
2372 | the end of a function, the end label is allowed to be even. This is | |
2373 | necessary because a following non-MIPS16 function may also need EH | |
2374 | information for its first instruction. | |
2375 | ||
2376 | Thus a MIPS16 region may be terminated by an ISA-encoded or a | |
2377 | non-ISA-encoded address. This probably isn't ideal, but it is | |
2378 | the traditional (legacy) behavior. It is therefore only safe | |
2379 | to search MIPS EH regions for an _odd-valued_ address. | |
2380 | ||
2381 | Masking off the ISA bit means that the target-independent code | |
2382 | will search for "(RA & -2) - 1", which is guaranteed to be odd. */ | |
7f48c9e1 AO |
2383 | #define MASK_RETURN_ADDR GEN_INT (-2) |
2384 | ||
cafe096b | 2385 | |
7f48c9e1 AO |
2386 | /* Similarly, don't use the least-significant bit to tell pointers to |
2387 | code from vtable index. */ | |
2388 | ||
2389 | #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta | |
2390 | ||
dfad12b5 | 2391 | /* The eliminations to $17 are only used for mips16 code. See the |
2bcb2ab3 | 2392 | definition of HARD_FRAME_POINTER_REGNUM. */ |
ab78d4a8 MM |
2393 | |
2394 | #define ELIMINABLE_REGS \ | |
2395 | {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
2bcb2ab3 GK |
2396 | { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \ |
2397 | { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \ | |
2bcb2ab3 GK |
2398 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
2399 | { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \ | |
2400 | { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}} | |
ab78d4a8 | 2401 | |
b2471838 | 2402 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
dfad12b5 | 2403 | (OFFSET) = mips_initial_elimination_offset ((FROM), (TO)) |
e75b25e7 | 2404 | |
dfad12b5 | 2405 | /* Allocate stack space for arguments at the beginning of each function. */ |
f73ad30e | 2406 | #define ACCUMULATE_OUTGOING_ARGS 1 |
e75b25e7 | 2407 | |
dfad12b5 | 2408 | /* The argument pointer always points to the first argument. */ |
305aa9e2 | 2409 | #define FIRST_PARM_OFFSET(FNDECL) 0 |
e75b25e7 | 2410 | |
dfad12b5 RS |
2411 | /* o32 and o64 reserve stack space for all argument registers. */ |
2412 | #define REG_PARM_STACK_SPACE(FNDECL) \ | |
7f9be256 | 2413 | (TARGET_OLDABI \ |
dfad12b5 | 2414 | ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \ |
ac8ab9fe | 2415 | : 0) |
e75b25e7 MM |
2416 | |
2417 | /* Define this if it is the responsibility of the caller to | |
7dac2f89 | 2418 | allocate the area reserved for arguments passed in registers. |
e75b25e7 | 2419 | If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect |
7dac2f89 | 2420 | of this macro is to determine whether the space is included in |
38173d38 | 2421 | `crtl->outgoing_args_size'. */ |
81464b2c | 2422 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
e75b25e7 | 2423 | |
e64ca6c4 | 2424 | #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64) |
e75b25e7 | 2425 | \f |
e75b25e7 MM |
2426 | /* Symbolic macros for the registers used to return integer and floating |
2427 | point values. */ | |
2428 | ||
2429 | #define GP_RETURN (GP_REG_FIRST + 2) | |
2430 | #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0)) | |
2431 | ||
7f9be256 | 2432 | #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8) |
ac8ab9fe | 2433 | |
e75b25e7 MM |
2434 | /* Symbolic macros for the first/last argument registers. */ |
2435 | ||
2436 | #define GP_ARG_FIRST (GP_REG_FIRST + 4) | |
ac8ab9fe | 2437 | #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) |
e75b25e7 | 2438 | #define FP_ARG_FIRST (FP_REG_FIRST + 12) |
ac8ab9fe | 2439 | #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1) |
e75b25e7 | 2440 | |
6cf538da RS |
2441 | /* True if MODE is vector and supported in a MSA vector register. */ |
2442 | #define MSA_SUPPORTED_MODE_P(MODE) \ | |
2443 | (ISA_HAS_MSA \ | |
2444 | && GET_MODE_SIZE (MODE) == UNITS_PER_MSA_REG \ | |
2445 | && (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \ | |
2446 | || GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT)) | |
2447 | ||
c2db3f3d RO |
2448 | /* Temporary register that is used when restoring $gp after a call. $4 and $5 |
2449 | are used for returning complex double values in soft-float code, so $6 is the | |
2450 | first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use | |
2451 | $gp itself as the temporary. */ | |
2452 | #define POST_CALL_TMP_REG \ | |
2453 | (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM) | |
2454 | ||
46af8e31 | 2455 | /* 1 if N is a possible register number for function argument passing. |
050af144 MF |
2456 | We have no FP argument registers when soft-float. Special handling |
2457 | is required for O32 where only even numbered registers are used for | |
2458 | O32-FPXX and O32-FP64. */ | |
46af8e31 JW |
2459 | |
2460 | #define FUNCTION_ARG_REGNO_P(N) \ | |
8bf3ccbb | 2461 | ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \ |
050af144 MF |
2462 | || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \ |
2463 | && (mips_abi != ABI_32 \ | |
2464 | || TARGET_FLOAT32 \ | |
2465 | || ((N) % 2 == 0)))) \ | |
8bf3ccbb | 2466 | && !fixed_regs[N]) |
e75b25e7 | 2467 | \f |
dfad12b5 | 2468 | /* This structure has to cope with two different argument allocation |
b11a9d5f RS |
2469 | schemes. Most MIPS ABIs view the arguments as a structure, of which |
2470 | the first N words go in registers and the rest go on the stack. If I | |
2471 | < N, the Ith word might go in Ith integer argument register or in a | |
2472 | floating-point register. For these ABIs, we only need to remember | |
2473 | the offset of the current argument into the structure. | |
4d72536e RS |
2474 | |
2475 | The EABI instead allocates the integer and floating-point arguments | |
2476 | separately. The first N words of FP arguments go in FP registers, | |
2477 | the rest go on the stack. Likewise, the first N words of the other | |
2478 | arguments go in integer registers, and the rest go on the stack. We | |
2479 | need to maintain three counts: the number of integer registers used, | |
2480 | the number of floating-point registers used, and the number of words | |
2481 | passed on the stack. | |
2482 | ||
2483 | We could keep separate information for the two ABIs (a word count for | |
2484 | the standard ABIs, and three separate counts for the EABI). But it | |
2485 | seems simpler to view the standard ABIs as forms of EABI that do not | |
2486 | allocate floating-point registers. | |
2487 | ||
2488 | So for the standard ABIs, the first N words are allocated to integer | |
65239d20 RS |
2489 | registers, and mips_function_arg decides on an argument-by-argument |
2490 | basis whether that argument should really go in an integer register, | |
2491 | or in a floating-point one. */ | |
e75b25e7 MM |
2492 | |
2493 | typedef struct mips_args { | |
4d72536e RS |
2494 | /* Always true for varargs functions. Otherwise true if at least |
2495 | one argument has been passed in an integer register. */ | |
2496 | int gp_reg_found; | |
2497 | ||
2498 | /* The number of arguments seen so far. */ | |
2499 | unsigned int arg_number; | |
2500 | ||
b11a9d5f RS |
2501 | /* The number of integer registers used so far. For all ABIs except |
2502 | EABI, this is the number of words that have been added to the | |
2503 | argument structure, limited to MAX_ARGS_IN_REGISTERS. */ | |
bb63e5a0 | 2504 | unsigned int num_gprs; |
4d72536e RS |
2505 | |
2506 | /* For EABI, the number of floating-point registers used so far. */ | |
bb63e5a0 | 2507 | unsigned int num_fprs; |
4d72536e RS |
2508 | |
2509 | /* The number of words passed on the stack. */ | |
2510 | unsigned int stack_words; | |
2511 | ||
2512 | /* On the mips16, we need to keep track of which floating point | |
2513 | arguments were passed in general registers, but would have been | |
85f65093 KH |
2514 | passed in the FP regs if this were a 32-bit function, so that we |
2515 | can move them to the FP regs if we wind up calling a 32-bit | |
4d72536e RS |
2516 | function. We record this information in fp_code, encoded in base |
2517 | four. A zero digit means no floating point argument, a one digit | |
2518 | means an SFmode argument, and a two digit means a DFmode argument, | |
2519 | and a three digit is not used. The low order digit is the first | |
2520 | argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by | |
2521 | an SFmode argument. ??? A more sophisticated approach will be | |
2522 | needed if MIPS_ABI != ABI_32. */ | |
2523 | int fp_code; | |
2524 | ||
2525 | /* True if the function has a prototype. */ | |
2526 | int prototype; | |
e75b25e7 MM |
2527 | } CUMULATIVE_ARGS; |
2528 | ||
2529 | /* Initialize a variable CUM of type CUMULATIVE_ARGS | |
2530 | for a call to a function whose data type is FNTYPE. | |
ce6e2d90 | 2531 | For a library call, FNTYPE is 0. */ |
e75b25e7 | 2532 | |
0f6937fe | 2533 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ |
65239d20 | 2534 | mips_init_cumulative_args (&CUM, FNTYPE) |
e75b25e7 | 2535 | |
65239d20 | 2536 | #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ |
76b0cbf8 | 2537 | (mips_pad_reg_upward (MODE, TYPE) ? PAD_UPWARD : PAD_DOWNWARD) |
ac8ab9fe | 2538 | |
4d72536e RS |
2539 | /* True if using EABI and varargs can be passed in floating-point |
2540 | registers. Under these conditions, we need a more complex form | |
2541 | of va_list, which tracks GPR, FPR and stack arguments separately. */ | |
2542 | #define EABI_FLOAT_VARARGS_P \ | |
2543 | (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE) | |
2544 | ||
e75b25e7 | 2545 | \f |
e19da24c | 2546 | #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO) |
cafe096b | 2547 | |
ac8ab9fe RS |
2548 | /* Treat LOC as a byte offset from the stack pointer and round it up |
2549 | to the next fully-aligned offset. */ | |
e64ca6c4 | 2550 | #define MIPS_STACK_ALIGN(LOC) \ |
3a1d601a | 2551 | (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8)) |
e75b25e7 MM |
2552 | |
2553 | \f | |
2554 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
2555 | for profiling a function entry. */ | |
2556 | ||
c376dbfb | 2557 | #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE)) |
e75b25e7 | 2558 | |
d9dced13 RS |
2559 | /* The profiler preserves all interesting registers, including $31. */ |
2560 | #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false | |
2561 | ||
f50c57ba JW |
2562 | /* No mips port has ever used the profiler counter word, so don't emit it |
2563 | or the label for it. */ | |
2564 | ||
2565 | #define NO_PROFILE_COUNTERS 1 | |
2566 | ||
d8d5b1e1 MM |
2567 | /* Define this macro if the code for function profiling should come |
2568 | before the function prologue. Normally, the profiling code comes | |
2569 | after. */ | |
2570 | ||
2571 | /* #define PROFILE_BEFORE_PROLOGUE */ | |
2572 | ||
e75b25e7 MM |
2573 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, |
2574 | the stack pointer does not matter. The value is tested only in | |
2575 | functions that have frame pointers. | |
2576 | No definition is equivalent to always zero. */ | |
2577 | ||
2578 | #define EXIT_IGNORE_STACK 1 | |
2579 | ||
2580 | \f | |
c640a3bd | 2581 | /* Trampolines are a block of code followed by two pointers. */ |
e75b25e7 | 2582 | |
c640a3bd RS |
2583 | #define TRAMPOLINE_SIZE \ |
2584 | (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2) | |
e75b25e7 | 2585 | |
c640a3bd RS |
2586 | /* Forcing a 64-bit alignment for 32-bit targets allows us to load two |
2587 | pointers from a single LUI base. */ | |
e75b25e7 | 2588 | |
c640a3bd | 2589 | #define TRAMPOLINE_ALIGNMENT 64 |
e75b25e7 | 2590 | |
a1d29c8c | 2591 | /* mips_trampoline_init calls this library function to flush |
c85f7c16 JL |
2592 | program and data caches. */ |
2593 | ||
2594 | #ifndef CACHE_FLUSH_FUNC | |
2595 | #define CACHE_FLUSH_FUNC "_flush_cache" | |
2596 | #endif | |
2597 | ||
d9dced13 RS |
2598 | #define MIPS_ICACHE_SYNC(ADDR, SIZE) \ |
2599 | /* Flush both caches. We need to flush the data cache in case \ | |
2600 | the system has a write-back cache. */ \ | |
2601 | emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \ | |
db69559b | 2602 | LCT_NORMAL, VOIDmode, ADDR, Pmode, SIZE, Pmode, \ |
d9dced13 RS |
2603 | GEN_INT (3), TYPE_MODE (integer_type_node)) |
2604 | ||
e75b25e7 MM |
2605 | \f |
2606 | /* Addressing modes, and classification of registers for them. */ | |
2607 | ||
bcbc6b7f RS |
2608 | #define REGNO_OK_FOR_INDEX_P(REGNO) 0 |
2609 | #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ | |
2610 | mips_regno_mode_ok_for_base_p (REGNO, MODE, 1) | |
e75b25e7 MM |
2611 | \f |
2612 | /* Maximum number of registers that can appear in a valid memory address. */ | |
2613 | ||
2614 | #define MAX_REGS_PER_ADDRESS 1 | |
2615 | ||
cafe096b EC |
2616 | /* Check for constness inline but use mips_legitimate_address_p |
2617 | to check whether a constant really is an address. */ | |
2618 | ||
2619 | #define CONSTANT_ADDRESS_P(X) \ | |
c6c3dba9 | 2620 | (CONSTANT_P (X) && memory_address_p (SImode, X)) |
cafe096b | 2621 | |
9c9e7632 GK |
2622 | /* This handles the magic '..CURRENT_FUNCTION' symbol, which means |
2623 | 'the start of the function that this code is output in'. */ | |
2624 | ||
66d4b733 TV |
2625 | #define ASM_OUTPUT_LABELREF(FILE,NAME) \ |
2626 | do { \ | |
2627 | if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \ | |
2628 | asm_fprintf ((FILE), "%U%s", \ | |
2629 | XSTR (XEXP (DECL_RTL (current_function_decl), \ | |
2630 | 0), 0)); \ | |
2631 | else \ | |
2632 | asm_fprintf ((FILE), "%U%s", (NAME)); \ | |
2633 | } while (0) | |
e75b25e7 | 2634 | \f |
4dbdb061 JW |
2635 | /* Flag to mark a function decl symbol that requires a long call. */ |
2636 | #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0) | |
2637 | #define SYMBOL_REF_LONG_CALL_P(X) \ | |
2638 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0) | |
2639 | ||
08d0963a RS |
2640 | /* This flag marks functions that cannot be lazily bound. */ |
2641 | #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1) | |
2642 | #define SYMBOL_REF_BIND_NOW_P(RTX) \ | |
2643 | ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0) | |
2644 | ||
c93c5160 RS |
2645 | /* True if we're generating a form of MIPS16 code in which jump tables |
2646 | are stored in the text section and encoded as 16-bit PC-relative | |
2647 | offsets. This is only possible when general text loads are allowed, | |
545ca0f2 JB |
2648 | since the table access itself will be an "lh" instruction. If the |
2649 | PC-relative offsets grow too large, 32-bit offsets are used instead. */ | |
c93c5160 | 2650 | #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS |
2bcb2ab3 | 2651 | |
c93c5160 RS |
2652 | #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES |
2653 | ||
ca97b221 | 2654 | #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode) |
545ca0f2 JB |
2655 | |
2656 | /* Only use short offsets if their range will not overflow. */ | |
2657 | #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \ | |
ca97b221 RS |
2658 | (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \ |
2659 | : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \ | |
2660 | : SImode) | |
c93c5160 RS |
2661 | |
2662 | #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES | |
e75b25e7 | 2663 | |
e75b25e7 | 2664 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
6639753e | 2665 | #ifndef DEFAULT_SIGNED_CHAR |
e75b25e7 | 2666 | #define DEFAULT_SIGNED_CHAR 1 |
6639753e | 2667 | #endif |
e75b25e7 | 2668 | |
a1c6b246 RS |
2669 | /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets, |
2670 | we generally don't want to use them for copying arbitrary data. | |
2671 | A single N-word move is usually the same cost as N single-word moves. */ | |
2672 | #define MOVE_MAX UNITS_PER_WORD | |
6cf538da | 2673 | /* We don't modify it for MSA as it is only used by the classic reload. */ |
876c09d3 | 2674 | #define MAX_MOVE_MAX 8 |
e75b25e7 MM |
2675 | |
2676 | /* Define this macro as a C expression which is nonzero if | |
2677 | accessing less than a word of memory (i.e. a `char' or a | |
2678 | `short') is no faster than accessing a word of memory, i.e., if | |
2679 | such access require more than one instruction or if there is no | |
2680 | difference in cost between byte and (aligned) word loads. | |
2681 | ||
2682 | On RISC machines, it tends to generate better code to define | |
64e7e238 SL |
2683 | this as 1, since it avoids making a QI or HI mode register. |
2684 | ||
2685 | But, generating word accesses for -mips16 is generally bad as shifts | |
2686 | (often extended) would be needed for byte accesses. */ | |
2687 | #define SLOW_BYTE_ACCESS (!TARGET_MIPS16) | |
e75b25e7 | 2688 | |
49042313 | 2689 | /* Standard MIPS integer shifts truncate the shift amount to the |
8ae8bad7 | 2690 | width of the shifted operand. However, Loongson MMI shifts |
49042313 | 2691 | do not truncate the shift amount at all. */ |
8ae8bad7 | 2692 | #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_MMI) |
e75b25e7 | 2693 | |
cafe096b | 2694 | |
e75b25e7 MM |
2695 | /* Specify the machine mode that pointers have. |
2696 | After generation of rtl, the compiler makes no further distinction | |
cafe096b | 2697 | between pointers and any other objects of this machine mode. */ |
876c09d3 | 2698 | |
1eeed24e | 2699 | #ifndef Pmode |
cafe096b | 2700 | #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode) |
1eeed24e | 2701 | #endif |
e75b25e7 | 2702 | |
cafe096b EC |
2703 | /* Give call MEMs SImode since it is the "most permissive" mode |
2704 | for both 32-bit and 64-bit targets. */ | |
e75b25e7 | 2705 | |
cafe096b | 2706 | #define FUNCTION_MODE SImode |
e75b25e7 | 2707 | |
e75b25e7 | 2708 | \f |
4b11e406 RS |
2709 | /* We allocate $fcc registers by hand and can't cope with moves of |
2710 | CCmode registers to and from pseudos (or memory). */ | |
7506f491 DE |
2711 | #define AVOID_CCMODE_COPIES |
2712 | ||
e75b25e7 MM |
2713 | /* A C expression for the cost of a branch instruction. A value of |
2714 | 1 is the default; other values are interpreted relative to that. */ | |
2715 | ||
3a4fd356 | 2716 | #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost |
c1bd2d66 | 2717 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 |
e75b25e7 | 2718 | |
da734fa1 RS |
2719 | /* The MIPS port has several functions that return an instruction count. |
2720 | Multiplying the count by this value gives the number of bytes that | |
2721 | the instructions occupy. */ | |
2722 | #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4) | |
2723 | ||
2724 | /* The length of a NOP in bytes. */ | |
2725 | #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4) | |
2726 | ||
0ff83799 MM |
2727 | /* If defined, modifies the length assigned to instruction INSN as a |
2728 | function of the context in which it is used. LENGTH is an lvalue | |
2729 | that contains the initially computed length of the insn and should | |
2730 | be updated with the correct length of the insn. */ | |
2731 | #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ | |
2732 | ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH))) | |
a8c1d5f8 RS |
2733 | |
2734 | /* Return the asm template for a non-MIPS16 conditional branch instruction. | |
2735 | OPCODE is the opcode's mnemonic and OPERANDS is the asm template for | |
2736 | its operands. */ | |
2737 | #define MIPS_BRANCH(OPCODE, OPERANDS) \ | |
2738 | "%*" OPCODE "%?\t" OPERANDS "%/" | |
d9870b7e | 2739 | |
22219d9b MF |
2740 | #define MIPS_BRANCH_C(OPCODE, OPERANDS) \ |
2741 | "%*" OPCODE "%:\t" OPERANDS | |
2742 | ||
0c433c31 RS |
2743 | /* Return an asm string that forces INSN to be treated as an absolute |
2744 | J or JAL instruction instead of an assembler macro. */ | |
2745 | #define MIPS_ABSOLUTE_JUMP(INSN) \ | |
2746 | (TARGET_ABICALLS_PIC2 \ | |
2747 | ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \ | |
2748 | : INSN) | |
2749 | ||
e75b25e7 MM |
2750 | \f |
2751 | /* Control the assembler format that we output. */ | |
2752 | ||
e75b25e7 MM |
2753 | /* Output to assembler file text saying following lines |
2754 | may contain character constants, extra white space, comments, etc. */ | |
2755 | ||
b2bcb32d | 2756 | #ifndef ASM_APP_ON |
e75b25e7 | 2757 | #define ASM_APP_ON " #APP\n" |
b2bcb32d | 2758 | #endif |
e75b25e7 MM |
2759 | |
2760 | /* Output to assembler file text saying following lines | |
2761 | no longer contain unusual constructs. */ | |
2762 | ||
b2bcb32d | 2763 | #ifndef ASM_APP_OFF |
e75b25e7 | 2764 | #define ASM_APP_OFF " #NO_APP\n" |
b2bcb32d | 2765 | #endif |
e75b25e7 | 2766 | |
5b9cc93e RS |
2767 | #define REGISTER_NAMES \ |
2768 | { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \ | |
2769 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ | |
2770 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \ | |
2771 | "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \ | |
2772 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \ | |
2773 | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \ | |
2774 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \ | |
2775 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \ | |
2776 | "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \ | |
0c433c31 | 2777 | "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \ |
5b9cc93e RS |
2778 | "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \ |
2779 | "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \ | |
2780 | "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \ | |
2781 | "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \ | |
2782 | "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \ | |
2783 | "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \ | |
2784 | "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \ | |
2785 | "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \ | |
2786 | "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \ | |
2787 | "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \ | |
2788 | "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \ | |
118ea793 CF |
2789 | "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \ |
2790 | "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \ | |
2791 | "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" } | |
5b9cc93e RS |
2792 | |
2793 | /* List the "software" names for each register. Also list the numerical | |
2794 | names for $fp and $sp. */ | |
e75b25e7 MM |
2795 | |
2796 | #define ADDITIONAL_REGISTER_NAMES \ | |
2797 | { \ | |
e75b25e7 MM |
2798 | { "$29", 29 + GP_REG_FIRST }, \ |
2799 | { "$30", 30 + GP_REG_FIRST }, \ | |
e75b25e7 MM |
2800 | { "at", 1 + GP_REG_FIRST }, \ |
2801 | { "v0", 2 + GP_REG_FIRST }, \ | |
2802 | { "v1", 3 + GP_REG_FIRST }, \ | |
2803 | { "a0", 4 + GP_REG_FIRST }, \ | |
2804 | { "a1", 5 + GP_REG_FIRST }, \ | |
2805 | { "a2", 6 + GP_REG_FIRST }, \ | |
2806 | { "a3", 7 + GP_REG_FIRST }, \ | |
2807 | { "t0", 8 + GP_REG_FIRST }, \ | |
2808 | { "t1", 9 + GP_REG_FIRST }, \ | |
2809 | { "t2", 10 + GP_REG_FIRST }, \ | |
2810 | { "t3", 11 + GP_REG_FIRST }, \ | |
2811 | { "t4", 12 + GP_REG_FIRST }, \ | |
2812 | { "t5", 13 + GP_REG_FIRST }, \ | |
2813 | { "t6", 14 + GP_REG_FIRST }, \ | |
2814 | { "t7", 15 + GP_REG_FIRST }, \ | |
2815 | { "s0", 16 + GP_REG_FIRST }, \ | |
2816 | { "s1", 17 + GP_REG_FIRST }, \ | |
2817 | { "s2", 18 + GP_REG_FIRST }, \ | |
2818 | { "s3", 19 + GP_REG_FIRST }, \ | |
2819 | { "s4", 20 + GP_REG_FIRST }, \ | |
2820 | { "s5", 21 + GP_REG_FIRST }, \ | |
2821 | { "s6", 22 + GP_REG_FIRST }, \ | |
2822 | { "s7", 23 + GP_REG_FIRST }, \ | |
2823 | { "t8", 24 + GP_REG_FIRST }, \ | |
2824 | { "t9", 25 + GP_REG_FIRST }, \ | |
2825 | { "k0", 26 + GP_REG_FIRST }, \ | |
2826 | { "k1", 27 + GP_REG_FIRST }, \ | |
2827 | { "gp", 28 + GP_REG_FIRST }, \ | |
2828 | { "sp", 29 + GP_REG_FIRST }, \ | |
2829 | { "fp", 30 + GP_REG_FIRST }, \ | |
6cf538da RS |
2830 | { "ra", 31 + GP_REG_FIRST }, \ |
2831 | { "$w0", 0 + FP_REG_FIRST }, \ | |
2832 | { "$w1", 1 + FP_REG_FIRST }, \ | |
2833 | { "$w2", 2 + FP_REG_FIRST }, \ | |
2834 | { "$w3", 3 + FP_REG_FIRST }, \ | |
2835 | { "$w4", 4 + FP_REG_FIRST }, \ | |
2836 | { "$w5", 5 + FP_REG_FIRST }, \ | |
2837 | { "$w6", 6 + FP_REG_FIRST }, \ | |
2838 | { "$w7", 7 + FP_REG_FIRST }, \ | |
2839 | { "$w8", 8 + FP_REG_FIRST }, \ | |
2840 | { "$w9", 9 + FP_REG_FIRST }, \ | |
2841 | { "$w10", 10 + FP_REG_FIRST }, \ | |
2842 | { "$w11", 11 + FP_REG_FIRST }, \ | |
2843 | { "$w12", 12 + FP_REG_FIRST }, \ | |
2844 | { "$w13", 13 + FP_REG_FIRST }, \ | |
2845 | { "$w14", 14 + FP_REG_FIRST }, \ | |
2846 | { "$w15", 15 + FP_REG_FIRST }, \ | |
2847 | { "$w16", 16 + FP_REG_FIRST }, \ | |
2848 | { "$w17", 17 + FP_REG_FIRST }, \ | |
2849 | { "$w18", 18 + FP_REG_FIRST }, \ | |
2850 | { "$w19", 19 + FP_REG_FIRST }, \ | |
2851 | { "$w20", 20 + FP_REG_FIRST }, \ | |
2852 | { "$w21", 21 + FP_REG_FIRST }, \ | |
2853 | { "$w22", 22 + FP_REG_FIRST }, \ | |
2854 | { "$w23", 23 + FP_REG_FIRST }, \ | |
2855 | { "$w24", 24 + FP_REG_FIRST }, \ | |
2856 | { "$w25", 25 + FP_REG_FIRST }, \ | |
2857 | { "$w26", 26 + FP_REG_FIRST }, \ | |
2858 | { "$w27", 27 + FP_REG_FIRST }, \ | |
2859 | { "$w28", 28 + FP_REG_FIRST }, \ | |
2860 | { "$w29", 29 + FP_REG_FIRST }, \ | |
2861 | { "$w30", 30 + FP_REG_FIRST }, \ | |
2862 | { "$w31", 31 + FP_REG_FIRST } \ | |
e75b25e7 MM |
2863 | } |
2864 | ||
e75b25e7 MM |
2865 | #define DBR_OUTPUT_SEQEND(STREAM) \ |
2866 | do \ | |
2867 | { \ | |
cf5fb4b0 RS |
2868 | /* Undo the effect of '%*'. */ \ |
2869 | mips_pop_asm_switch (&mips_nomacro); \ | |
2870 | mips_pop_asm_switch (&mips_noreorder); \ | |
2871 | /* Emit a blank line after the delay slot for emphasis. */ \ | |
e75b25e7 MM |
2872 | fputs ("\n", STREAM); \ |
2873 | } \ | |
2874 | while (0) | |
2875 | ||
9ec36da5 | 2876 | /* The MIPS implementation uses some labels for its own purpose. The |
e75b25e7 MM |
2877 | following lists what labels are created, and are all formed by the |
2878 | pattern $L[a-z].*. The machine independent portion of GCC creates | |
2879 | labels matching: $L[A-Z][0-9]+ and $L[0-9]+. | |
2880 | ||
c5b7917e | 2881 | LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt. |
e75b25e7 MM |
2882 | $Lb[0-9]+ Begin blocks for MIPS debug support |
2883 | $Lc[0-9]+ Label for use in s<xx> operation. | |
33005162 | 2884 | $Le[0-9]+ End blocks for MIPS debug support */ |
e75b25e7 | 2885 | |
44404b8b | 2886 | #undef ASM_DECLARE_OBJECT_NAME |
c1115ccd | 2887 | #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ |
586de218 | 2888 | mips_declare_object (STREAM, NAME, "", ":\n") |
31c714e3 | 2889 | |
506a61b1 KG |
2890 | /* Globalizing directive for a label. */ |
2891 | #define GLOBAL_ASM_OP "\t.globl\t" | |
e75b25e7 | 2892 | |
31c714e3 | 2893 | /* This says how to define a global common symbol. */ |
e75b25e7 | 2894 | |
35f5add9 | 2895 | #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common |
e75b25e7 | 2896 | |
112cdef5 | 2897 | /* This says how to define a local common symbol (i.e., not visible to |
31c714e3 | 2898 | linker). */ |
e75b25e7 | 2899 | |
48b2e0a7 RS |
2900 | #ifndef ASM_OUTPUT_ALIGNED_LOCAL |
2901 | #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \ | |
2902 | mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false) | |
2903 | #endif | |
e75b25e7 MM |
2904 | |
2905 | /* This says how to output an external. It would be possible not to | |
2906 | output anything and let undefined symbol become external. However | |
2907 | the assembler uses length information on externals to allocate in | |
2908 | data/sdata bss/sbss, thereby saving exec time. */ | |
2909 | ||
4d9f4c46 | 2910 | #undef ASM_OUTPUT_EXTERNAL |
e75b25e7 MM |
2911 | #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \ |
2912 | mips_output_external(STREAM,DECL,NAME) | |
2913 | ||
e75b25e7 MM |
2914 | /* This is how to declare a function name. The actual work of |
2915 | emitting the label is moved to function_prologue, so that we can | |
2916 | get the line number correctly emitted before the .ent directive, | |
789b7de5 | 2917 | and after any .file directives. Define as empty so that the function |
4e314d1f EC |
2918 | is not declared before the .ent directive elsewhere. */ |
2919 | ||
44404b8b | 2920 | #undef ASM_DECLARE_FUNCTION_NAME |
33005162 | 2921 | #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) |
4e314d1f | 2922 | |
e75b25e7 MM |
2923 | /* This is how to store into the string LABEL |
2924 | the symbol_ref name of an internal numbered label where | |
2925 | PREFIX is the class of label and NUM is the number within the class. | |
2926 | This is suitable for output with `assemble_name'. */ | |
2927 | ||
44404b8b | 2928 | #undef ASM_GENERATE_INTERNAL_LABEL |
e75b25e7 | 2929 | #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ |
4f70758f | 2930 | sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM)) |
e75b25e7 | 2931 | |
370d36c6 RS |
2932 | /* Print debug labels as "foo = ." rather than "foo:" because they should |
2933 | represent a byte pointer rather than an ISA-encoded address. This is | |
2934 | particularly important for code like: | |
2935 | ||
2936 | $LFBxxx = . | |
2937 | .cfi_startproc | |
2938 | ... | |
2939 | .section .gcc_except_table,... | |
2940 | ... | |
2941 | .uleb128 foo-$LFBxxx | |
2942 | ||
2943 | The .uleb128 requies $LFBxxx to match the FDE start address, which is | |
2944 | likewise a byte pointer rather than an ISA-encoded address. | |
2945 | ||
2946 | At the time of writing, this hook is not used for the function end | |
2947 | label: | |
2948 | ||
2949 | $LFExxx: | |
2950 | .end foo | |
2951 | ||
2952 | But this doesn't matter, because GAS doesn't treat a pre-.end label | |
2953 | as a MIPS16 one anyway. */ | |
2954 | ||
2955 | #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ | |
2956 | fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM) | |
2957 | ||
e75b25e7 MM |
2958 | /* This is how to output an element of a case-vector that is absolute. */ |
2959 | ||
2960 | #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ | |
6ae1498b | 2961 | fprintf (STREAM, "\t%s\t%sL%d\n", \ |
cafe096b | 2962 | ptr_mode == DImode ? ".dword" : ".word", \ |
6ae1498b | 2963 | LOCAL_LABEL_PREFIX, \ |
876c09d3 | 2964 | VALUE) |
e75b25e7 | 2965 | |
827555ea RS |
2966 | /* This is how to output an element of a case-vector. We can make the |
2967 | entries PC-relative in MIPS16 code and GP-relative when .gp(d)word | |
2968 | is supported. */ | |
e75b25e7 | 2969 | |
33f7f353 | 2970 | #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ |
e0bfcea5 | 2971 | do { \ |
c93c5160 | 2972 | if (TARGET_MIPS16_SHORT_JUMP_TABLES) \ |
545ca0f2 JB |
2973 | { \ |
2974 | if (GET_MODE (BODY) == HImode) \ | |
2975 | fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \ | |
2976 | LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ | |
2977 | else \ | |
2978 | fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \ | |
2979 | LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \ | |
2980 | } \ | |
cafe096b | 2981 | else if (TARGET_GPWORD) \ |
6ae1498b | 2982 | fprintf (STREAM, "\t%s\t%sL%d\n", \ |
cafe096b | 2983 | ptr_mode == DImode ? ".gpdword" : ".gpword", \ |
6ae1498b | 2984 | LOCAL_LABEL_PREFIX, VALUE); \ |
8cb6400c RS |
2985 | else if (TARGET_RTP_PIC) \ |
2986 | { \ | |
2987 | /* Make the entry relative to the start of the function. */ \ | |
2988 | rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \ | |
2989 | fprintf (STREAM, "\t%s\t%sL%d-", \ | |
2990 | Pmode == DImode ? ".dword" : ".word", \ | |
2991 | LOCAL_LABEL_PREFIX, VALUE); \ | |
2992 | assemble_name (STREAM, XSTR (fnsym, 0)); \ | |
2993 | fprintf (STREAM, "\n"); \ | |
2994 | } \ | |
516a2dfd | 2995 | else \ |
b2d8cf33 | 2996 | fprintf (STREAM, "\t%s\t%sL%d\n", \ |
cafe096b | 2997 | ptr_mode == DImode ? ".dword" : ".word", \ |
b2d8cf33 | 2998 | LOCAL_LABEL_PREFIX, VALUE); \ |
e0bfcea5 ILT |
2999 | } while (0) |
3000 | ||
2fe2aba3 MR |
3001 | /* Mark inline jump tables as data for the purpose of disassembly. For |
3002 | simplicity embed the jump table's label number in the local symbol | |
3003 | produced so that multiple jump tables within a single function end | |
3004 | up marked with unique symbols. Retain the alignment setting from | |
3005 | `elfos.h' as we are replacing the definition from there. */ | |
3006 | ||
3007 | #undef ASM_OUTPUT_BEFORE_CASE_LABEL | |
3008 | #define ASM_OUTPUT_BEFORE_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \ | |
3009 | do \ | |
3010 | { \ | |
3011 | ASM_OUTPUT_ALIGN ((STREAM), 2); \ | |
3012 | if (JUMP_TABLES_IN_TEXT_SECTION) \ | |
3013 | mips_set_text_contents_type (STREAM, "__jump_", NUM, FALSE); \ | |
3014 | } \ | |
9739c3d3 | 3015 | while (0) |
2fe2aba3 MR |
3016 | |
3017 | /* Reset text marking to code after an inline jump table. Like with | |
3018 | the beginning of a jump table use the label number to keep symbols | |
3019 | unique. */ | |
3020 | ||
3021 | #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) \ | |
3022 | do \ | |
3023 | if (JUMP_TABLES_IN_TEXT_SECTION) \ | |
3024 | mips_set_text_contents_type (STREAM, "__jend_", NUM, TRUE); \ | |
65f371e4 | 3025 | while (0) |
2fe2aba3 | 3026 | |
e75b25e7 MM |
3027 | /* This is how to output an assembler line |
3028 | that says to advance the location counter | |
3029 | to a multiple of 2**LOG bytes. */ | |
3030 | ||
3031 | #define ASM_OUTPUT_ALIGN(STREAM,LOG) \ | |
a688e0b7 | 3032 | fprintf (STREAM, "\t.align\t%d\n", (LOG)) |
e75b25e7 | 3033 | |
38e01259 | 3034 | /* This is how to output an assembler line to advance the location |
e75b25e7 MM |
3035 | counter by SIZE bytes. */ |
3036 | ||
44404b8b | 3037 | #undef ASM_OUTPUT_SKIP |
e75b25e7 | 3038 | #define ASM_OUTPUT_SKIP(STREAM,SIZE) \ |
16998094 | 3039 | fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
e75b25e7 | 3040 | |
e75b25e7 | 3041 | /* This is how to output a string. */ |
44404b8b | 3042 | #undef ASM_OUTPUT_ASCII |
65239d20 | 3043 | #define ASM_OUTPUT_ASCII mips_output_ascii |
e75b25e7 | 3044 | |
e75b25e7 | 3045 | \f |
b82b0773 MM |
3046 | /* Default to -G 8 */ |
3047 | #ifndef MIPS_DEFAULT_GVALUE | |
3048 | #define MIPS_DEFAULT_GVALUE 8 | |
3049 | #endif | |
e75b25e7 | 3050 | |
f3b39eba MM |
3051 | /* Define the strings to put out for each section in the object file. */ |
3052 | #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */ | |
3053 | #define DATA_SECTION_ASM_OP "\t.data" /* large data */ | |
2017ed61 EC |
3054 | |
3055 | #undef READONLY_DATA_SECTION_ASM_OP | |
d48bc59a | 3056 | #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */ |
e75b25e7 | 3057 | \f |
e75b25e7 MM |
3058 | #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \ |
3059 | do \ | |
3060 | { \ | |
f29adf5b SL |
3061 | fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \ |
3062 | TARGET_64BIT ? "daddiu" : "addiu", \ | |
e75b25e7 MM |
3063 | reg_names[STACK_POINTER_REGNUM], \ |
3064 | reg_names[STACK_POINTER_REGNUM], \ | |
876c09d3 | 3065 | TARGET_64BIT ? "sd" : "sw", \ |
e75b25e7 MM |
3066 | reg_names[REGNO], \ |
3067 | reg_names[STACK_POINTER_REGNUM]); \ | |
3068 | } \ | |
3069 | while (0) | |
3070 | ||
3071 | #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \ | |
3072 | do \ | |
3073 | { \ | |
cf5fb4b0 | 3074 | mips_push_asm_switch (&mips_noreorder); \ |
876c09d3 JW |
3075 | fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \ |
3076 | TARGET_64BIT ? "ld" : "lw", \ | |
e75b25e7 MM |
3077 | reg_names[REGNO], \ |
3078 | reg_names[STACK_POINTER_REGNUM], \ | |
876c09d3 | 3079 | TARGET_64BIT ? "daddu" : "addu", \ |
e75b25e7 MM |
3080 | reg_names[STACK_POINTER_REGNUM], \ |
3081 | reg_names[STACK_POINTER_REGNUM]); \ | |
cf5fb4b0 | 3082 | mips_pop_asm_switch (&mips_noreorder); \ |
e75b25e7 MM |
3083 | } \ |
3084 | while (0) | |
3085 | ||
4baed42f DE |
3086 | /* How to start an assembler comment. |
3087 | The leading space is important (the mips native assembler requires it). */ | |
e75b25e7 | 3088 | #ifndef ASM_COMMENT_START |
4baed42f | 3089 | #define ASM_COMMENT_START " #" |
e75b25e7 | 3090 | #endif |
3f1f8d8c | 3091 | \f |
498887c8 | 3092 | #undef SIZE_TYPE |
cafe096b | 3093 | #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int") |
3f1f8d8c | 3094 | |
498887c8 | 3095 | #undef PTRDIFF_TYPE |
cafe096b | 3096 | #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int") |
cfa31150 | 3097 | |
58df0b91 SD |
3098 | /* The minimum alignment of any expanded block move. */ |
3099 | #define MIPS_MIN_MOVE_MEM_ALIGN 16 | |
3100 | ||
a1c6b246 | 3101 | /* The maximum number of bytes that can be copied by one iteration of |
76715c32 | 3102 | a cpymemsi loop; see mips_block_move_loop. */ |
a1c6b246 RS |
3103 | #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \ |
3104 | (UNITS_PER_WORD * 4) | |
3105 | ||
3106 | /* The maximum number of bytes that can be copied by a straight-line | |
76715c32 | 3107 | implementation of cpymemsi; see mips_block_move_straight. We want |
a1c6b246 RS |
3108 | to make sure that any loop-based implementation will iterate at |
3109 | least twice. */ | |
3110 | #define MIPS_MAX_MOVE_BYTES_STRAIGHT \ | |
3111 | (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2) | |
3112 | ||
cfa31150 SL |
3113 | /* The base cost of a memcpy call, for MOVE_RATIO and friends. These |
3114 | values were determined experimentally by benchmarking with CSiBE. | |
3115 | In theory, the call overhead is higher for TARGET_ABICALLS (especially | |
3116 | for o32 where we have to restore $gp afterwards as well as make an | |
3117 | indirect call), but in practice, bumping this up higher for | |
3118 | TARGET_ABICALLS doesn't make much difference to code size. */ | |
3119 | ||
3120 | #define MIPS_CALL_RATIO 8 | |
3121 | ||
76715c32 | 3122 | /* Any loop-based implementation of cpymemsi will have at least |
a1c6b246 RS |
3123 | MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory |
3124 | moves, so allow individual copies of fewer elements. | |
3125 | ||
76715c32 | 3126 | When cpymemsi is not available, use a value approximating |
a1c6b246 RS |
3127 | the length of a memcpy call sequence, so that move_by_pieces |
3128 | will generate inline code if it is shorter than a function call. | |
3129 | Since move_by_pieces_ninsns counts memory-to-memory moves, but | |
3130 | we'll have to generate a load/store pair for each, halve the | |
3131 | value of MIPS_CALL_RATIO to take that into account. */ | |
3132 | ||
e04ad03d | 3133 | #define MOVE_RATIO(speed) \ |
76715c32 | 3134 | (HAVE_cpymemsi \ |
a1c6b246 RS |
3135 | ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \ |
3136 | : MIPS_CALL_RATIO / 2) | |
3137 | ||
cfa31150 SL |
3138 | /* For CLEAR_RATIO, when optimizing for size, give a better estimate |
3139 | of the length of a memset call, but use the default otherwise. */ | |
3140 | ||
e04ad03d JH |
3141 | #define CLEAR_RATIO(speed)\ |
3142 | ((speed) ? 15 : MIPS_CALL_RATIO) | |
cfa31150 SL |
3143 | |
3144 | /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when | |
3145 | optimizing for size adjust the ratio to account for the overhead of | |
3146 | loading the constant and replicating it across the word. */ | |
3147 | ||
e04ad03d JH |
3148 | #define SET_RATIO(speed) \ |
3149 | ((speed) ? 15 : MIPS_CALL_RATIO - 2) | |
2bcb2ab3 | 3150 | \f |
3c0121e4 AO |
3151 | /* Since the bits of the _init and _fini function is spread across |
3152 | many object files, each potentially with its own GP, we must assume | |
3153 | we need to load our GP. We don't preserve $gp or $ra, since each | |
3154 | init/fini chunk is supposed to initialize $gp, and crti/crtn | |
3155 | already take care of preserving $ra and, when appropriate, $gp. */ | |
27d54b2a | 3156 | #if (defined _ABIO32 && _MIPS_SIM == _ABIO32) |
3c0121e4 AO |
3157 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
3158 | asm (SECTION_OP "\n\ | |
1274718f CLT |
3159 | .set push\n\ |
3160 | .set nomips16\n\ | |
3c0121e4 AO |
3161 | .set noreorder\n\ |
3162 | bal 1f\n\ | |
3163 | nop\n\ | |
3164 | 1: .cpload $31\n\ | |
3165 | .set reorder\n\ | |
8d92d274 PJ |
3166 | la $25, " USER_LABEL_PREFIX #FUNC "\n\ |
3167 | jalr $25\n\ | |
1274718f | 3168 | .set pop\n\ |
3c0121e4 | 3169 | " TEXT_SECTION_ASM_OP); |
8d92d274 | 3170 | #elif (defined _ABIN32 && _MIPS_SIM == _ABIN32) |
3c0121e4 AO |
3171 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
3172 | asm (SECTION_OP "\n\ | |
1274718f CLT |
3173 | .set push\n\ |
3174 | .set nomips16\n\ | |
3c0121e4 AO |
3175 | .set noreorder\n\ |
3176 | bal 1f\n\ | |
3177 | nop\n\ | |
3178 | 1: .set reorder\n\ | |
3179 | .cpsetup $31, $2, 1b\n\ | |
8d92d274 PJ |
3180 | la $25, " USER_LABEL_PREFIX #FUNC "\n\ |
3181 | jalr $25\n\ | |
3182 | .set pop\n\ | |
3183 | " TEXT_SECTION_ASM_OP); | |
3184 | #elif (defined _ABI64 && _MIPS_SIM == _ABI64) | |
3185 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
3186 | asm (SECTION_OP "\n\ | |
3187 | .set push\n\ | |
3188 | .set nomips16\n\ | |
3189 | .set noreorder\n\ | |
3190 | bal 1f\n\ | |
3191 | nop\n\ | |
3192 | 1: .set reorder\n\ | |
3193 | .cpsetup $31, $2, 1b\n\ | |
3194 | dla $25, " USER_LABEL_PREFIX #FUNC "\n\ | |
3195 | jalr $25\n\ | |
1274718f | 3196 | .set pop\n\ |
3c0121e4 AO |
3197 | " TEXT_SECTION_ASM_OP); |
3198 | #endif | |
69229b81 DJ |
3199 | |
3200 | #ifndef HAVE_AS_TLS | |
3201 | #define HAVE_AS_TLS 0 | |
3202 | #endif | |
8d2fc1c4 | 3203 | |
ff3f3951 MR |
3204 | #ifndef HAVE_AS_NAN |
3205 | #define HAVE_AS_NAN 0 | |
3206 | #endif | |
3207 | ||
ab77a036 | 3208 | #ifndef USED_FOR_TARGET |
cf5fb4b0 RS |
3209 | /* Information about ".set noFOO; ...; .set FOO" blocks. */ |
3210 | struct mips_asm_switch { | |
3211 | /* The FOO in the description above. */ | |
3212 | const char *name; | |
3213 | ||
3214 | /* The current block nesting level, or 0 if we aren't in a block. */ | |
3215 | int nesting_level; | |
3216 | }; | |
3217 | ||
ab77a036 | 3218 | extern const enum reg_class mips_regno_to_class[]; |
ab77a036 RS |
3219 | extern const char *current_function_file; /* filename current function is in */ |
3220 | extern int num_source_filenames; /* current .file # */ | |
cf5fb4b0 RS |
3221 | extern struct mips_asm_switch mips_noreorder; |
3222 | extern struct mips_asm_switch mips_nomacro; | |
3223 | extern struct mips_asm_switch mips_noat; | |
ab77a036 RS |
3224 | extern int mips_dbx_regno[]; |
3225 | extern int mips_dwarf_regno[]; | |
3226 | extern bool mips_split_p[]; | |
08d0963a | 3227 | extern bool mips_split_hi_p[]; |
ddaf8125 RS |
3228 | extern bool mips_use_pcrel_pool_p[]; |
3229 | extern const char *mips_lo_relocs[]; | |
3230 | extern const char *mips_hi_relocs[]; | |
24609606 RS |
3231 | extern enum processor mips_arch; /* which cpu to codegen for */ |
3232 | extern enum processor mips_tune; /* which cpu to schedule for */ | |
ab77a036 | 3233 | extern int mips_isa; /* architectural level */ |
ad782bc9 | 3234 | extern int mips_isa_rev; |
ab77a036 RS |
3235 | extern const struct mips_cpu_info *mips_arch_info; |
3236 | extern const struct mips_cpu_info *mips_tune_info; | |
22c4c869 | 3237 | extern unsigned int mips_base_compression_flags; |
5aa62249 | 3238 | extern GTY(()) struct target_globals *mips16_globals; |
ba57dd12 | 3239 | extern GTY(()) struct target_globals *micromips_globals; |
d41c8b4c SE |
3240 | |
3241 | /* Information about a function's frame layout. */ | |
3242 | struct GTY(()) mips_frame_info { | |
3243 | /* The size of the frame in bytes. */ | |
3244 | HOST_WIDE_INT total_size; | |
3245 | ||
3246 | /* The number of bytes allocated to variables. */ | |
3247 | HOST_WIDE_INT var_size; | |
3248 | ||
3249 | /* The number of bytes allocated to outgoing function arguments. */ | |
3250 | HOST_WIDE_INT args_size; | |
3251 | ||
3252 | /* The number of bytes allocated to the .cprestore slot, or 0 if there | |
3253 | is no such slot. */ | |
3254 | HOST_WIDE_INT cprestore_size; | |
3255 | ||
3256 | /* Bit X is set if the function saves or restores GPR X. */ | |
3257 | unsigned int mask; | |
3258 | ||
3259 | /* Likewise FPR X. */ | |
3260 | unsigned int fmask; | |
3261 | ||
3262 | /* Likewise doubleword accumulator X ($acX). */ | |
3263 | unsigned int acc_mask; | |
3264 | ||
3265 | /* The number of GPRs, FPRs, doubleword accumulators and COP0 | |
3266 | registers saved. */ | |
3267 | unsigned int num_gp; | |
3268 | unsigned int num_fp; | |
3269 | unsigned int num_acc; | |
3270 | unsigned int num_cop0_regs; | |
3271 | ||
3272 | /* The offset of the topmost GPR, FPR, accumulator and COP0-register | |
3273 | save slots from the top of the frame, or zero if no such slots are | |
3274 | needed. */ | |
3275 | HOST_WIDE_INT gp_save_offset; | |
3276 | HOST_WIDE_INT fp_save_offset; | |
3277 | HOST_WIDE_INT acc_save_offset; | |
3278 | HOST_WIDE_INT cop0_save_offset; | |
3279 | ||
3280 | /* Likewise, but giving offsets from the bottom of the frame. */ | |
3281 | HOST_WIDE_INT gp_sp_offset; | |
3282 | HOST_WIDE_INT fp_sp_offset; | |
3283 | HOST_WIDE_INT acc_sp_offset; | |
3284 | HOST_WIDE_INT cop0_sp_offset; | |
3285 | ||
3286 | /* Similar, but the value passed to _mcount. */ | |
3287 | HOST_WIDE_INT ra_fp_offset; | |
3288 | ||
3289 | /* The offset of arg_pointer_rtx from the bottom of the frame. */ | |
3290 | HOST_WIDE_INT arg_pointer_offset; | |
3291 | ||
3292 | /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */ | |
3293 | HOST_WIDE_INT hard_frame_pointer_offset; | |
3294 | }; | |
3295 | ||
3296 | /* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts. */ | |
3297 | enum mips_int_mask | |
3298 | { | |
3299 | INT_MASK_EIC = -1, | |
3300 | INT_MASK_SW0 = 0, | |
3301 | INT_MASK_SW1 = 1, | |
3302 | INT_MASK_HW0 = 2, | |
3303 | INT_MASK_HW1 = 3, | |
3304 | INT_MASK_HW2 = 4, | |
3305 | INT_MASK_HW3 = 5, | |
3306 | INT_MASK_HW4 = 6, | |
3307 | INT_MASK_HW5 = 7 | |
3308 | }; | |
3309 | ||
3310 | /* Enumeration to mark the existence of the shadow register set. | |
3311 | SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack | |
3312 | pointer. */ | |
3313 | enum mips_shadow_set | |
3314 | { | |
3315 | SHADOW_SET_NO, | |
3316 | SHADOW_SET_YES, | |
3317 | SHADOW_SET_INTSTACK | |
3318 | }; | |
3319 | ||
3320 | struct GTY(()) machine_function { | |
3321 | /* The next floating-point condition-code register to allocate | |
3322 | for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */ | |
3323 | unsigned int next_fcc; | |
3324 | ||
3325 | /* The register returned by mips16_gp_pseudo_reg; see there for details. */ | |
3326 | rtx mips16_gp_pseudo_rtx; | |
3327 | ||
3328 | /* The number of extra stack bytes taken up by register varargs. | |
3329 | This area is allocated by the callee at the very top of the frame. */ | |
3330 | int varargs_size; | |
3331 | ||
3332 | /* The current frame information, calculated by mips_compute_frame_info. */ | |
3333 | struct mips_frame_info frame; | |
3334 | ||
3335 | /* The register to use as the function's global pointer, or INVALID_REGNUM | |
3336 | if the function doesn't need one. */ | |
3337 | unsigned int global_pointer; | |
3338 | ||
3339 | /* How many instructions it takes to load a label into $AT, or 0 if | |
3340 | this property hasn't yet been calculated. */ | |
3341 | unsigned int load_label_num_insns; | |
3342 | ||
3343 | /* True if mips_adjust_insn_length should ignore an instruction's | |
3344 | hazard attribute. */ | |
3345 | bool ignore_hazard_length_p; | |
3346 | ||
3347 | /* True if the whole function is suitable for .set noreorder and | |
3348 | .set nomacro. */ | |
3349 | bool all_noreorder_p; | |
3350 | ||
3351 | /* True if the function has "inflexible" and "flexible" references | |
3352 | to the global pointer. See mips_cfun_has_inflexible_gp_ref_p | |
3353 | and mips_cfun_has_flexible_gp_ref_p for details. */ | |
3354 | bool has_inflexible_gp_insn_p; | |
3355 | bool has_flexible_gp_insn_p; | |
3356 | ||
3357 | /* True if the function's prologue must load the global pointer | |
3358 | value into pic_offset_table_rtx and store the same value in | |
3359 | the function's cprestore slot (if any). Even if this value | |
3360 | is currently false, we may decide to set it to true later; | |
3361 | see mips_must_initialize_gp_p () for details. */ | |
3362 | bool must_initialize_gp_p; | |
3363 | ||
3364 | /* True if the current function must restore $gp after any potential | |
3365 | clobber. This value is only meaningful during the first post-epilogue | |
3366 | split_insns pass; see mips_must_initialize_gp_p () for details. */ | |
3367 | bool must_restore_gp_when_clobbered_p; | |
3368 | ||
3369 | /* True if this is an interrupt handler. */ | |
3370 | bool interrupt_handler_p; | |
3371 | ||
3372 | /* Records the way in which interrupts should be masked. Only used if | |
3373 | interrupts are not kept masked. */ | |
3374 | enum mips_int_mask int_mask; | |
3375 | ||
3376 | /* Records if this is an interrupt handler that uses shadow registers. */ | |
3377 | enum mips_shadow_set use_shadow_register_set; | |
3378 | ||
3379 | /* True if this is an interrupt handler that should keep interrupts | |
3380 | masked. */ | |
3381 | bool keep_interrupts_masked_p; | |
3382 | ||
3383 | /* True if this is an interrupt handler that should use DERET | |
3384 | instead of ERET. */ | |
3385 | bool use_debug_exception_return_p; | |
3386 | ||
3387 | /* True if at least one of the formal parameters to a function must be | |
3388 | written to the frame header (probably so its address can be taken). */ | |
3389 | bool does_not_use_frame_header; | |
3390 | ||
3391 | /* True if none of the functions that are called by this function need | |
3392 | stack space allocated for their arguments. */ | |
3393 | bool optimize_call_stack; | |
0bfbc166 SE |
3394 | |
3395 | /* True if one of the functions calling this function may not allocate | |
3396 | a frame header. */ | |
3397 | bool callers_may_not_allocate_frame; | |
3398 | ||
3399 | /* True if GCC stored callee saved registers in the frame header. */ | |
3400 | bool use_frame_header_for_callee_saved_regs; | |
d41c8b4c | 3401 | }; |
ab77a036 | 3402 | #endif |
58684fa0 MK |
3403 | |
3404 | /* Enable querying of DFA units. */ | |
3405 | #define CPU_UNITS_QUERY 1 | |
1afc5373 CF |
3406 | |
3407 | #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ | |
3408 | mips_final_prescan_insn (INSN, OPVEC, NOPERANDS) | |
28143fdd | 3409 | |
49576e25 RS |
3410 | /* As on most targets, we want the .eh_frame section to be read-only where |
3411 | possible. And as on most targets, this means two things: | |
3412 | ||
3413 | (a) Non-locally-binding pointers must have an indirect encoding, | |
3414 | so that the addresses in the .eh_frame section itself become | |
3415 | locally-binding. | |
3416 | ||
3417 | (b) A shared library's .eh_frame section must encode locally-binding | |
3418 | pointers in a relative (relocation-free) form. | |
3419 | ||
3420 | However, MIPS has traditionally not allowed directives like: | |
3421 | ||
3422 | .long x-. | |
3423 | ||
3424 | in cases where "x" is in a different section, or is not defined in the | |
3425 | same assembly file. We are therefore unable to emit the PC-relative | |
3426 | form required by (b) at assembly time. | |
3427 | ||
3428 | Fortunately, the linker is able to convert absolute addresses into | |
3429 | PC-relative addresses on our behalf. Unfortunately, only certain | |
3430 | versions of the linker know how to do this for indirect pointers, | |
3431 | and for personality data. We must fall back on using writable | |
3432 | .eh_frame sections for shared libraries if the linker does not | |
3433 | support this feature. */ | |
3434 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ | |
3435 | (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr) | |
5aa62249 RS |
3436 | |
3437 | /* For switching between MIPS16 and non-MIPS16 modes. */ | |
3438 | #define SWITCHABLE_TARGET 1 | |
81a478c8 RS |
3439 | |
3440 | /* Several named MIPS patterns depend on Pmode. These patterns have the | |
3441 | form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode. | |
3442 | Add the appropriate suffix to generator function NAME and invoke it | |
3443 | with arguments ARGS. */ | |
3444 | #define PMODE_INSN(NAME, ARGS) \ | |
3445 | (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS) | |
8cfebf86 SE |
3446 | |
3447 | /* If we are *not* using multilibs and the default ABI is not ABI_32 we | |
3448 | need to change these from /lib and /usr/lib. */ | |
3449 | #if MIPS_ABI_DEFAULT == ABI_N32 | |
3450 | #define STANDARD_STARTFILE_PREFIX_1 "/lib32/" | |
3451 | #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/" | |
3452 | #elif MIPS_ABI_DEFAULT == ABI_64 | |
3453 | #define STANDARD_STARTFILE_PREFIX_1 "/lib64/" | |
3454 | #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/" | |
3455 | #endif | |
abf96035 PG |
3456 | |
3457 | /* Load store bonding is not supported by micromips and fix_24k. The | |
3458 | performance can be degraded for those targets. Hence, do not bond for | |
3459 | micromips or fix_24k. */ | |
3460 | #define ENABLE_LD_ST_PAIRS \ | |
30c0ee9c MF |
3461 | (TARGET_LOAD_STORE_PAIRS \ |
3462 | && (TUNE_P5600 || TUNE_I6400 || TUNE_P6600) \ | |
abf96035 | 3463 | && !TARGET_MICROMIPS && !TARGET_FIX_24K) |
a3c1e1f2 DM |
3464 | |
3465 | #define NEED_INDICATE_EXEC_STACK 0 |