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2f2ebf95 | 1 | ;; Pipeline descriptions of Andes NDS32 cpu for GNU compiler |
99dee823 | 2 | ;; Copyright (C) 2012-2021 Free Software Foundation, Inc. |
2f2ebf95 KC |
3 | ;; Contributed by Andes Technology Corporation. |
4 | ;; | |
5 | ;; This file is part of GCC. | |
6 | ;; | |
7 | ;; GCC is free software; you can redistribute it and/or modify it | |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 3, or (at your | |
10 | ;; option) any later version. | |
11 | ;; | |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
16 | ;; | |
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GCC; see the file COPYING3. If not see | |
19 | ;; <http://www.gnu.org/licenses/>. | |
20 | ||
21 | ||
22 | ;; ------------------------------------------------------------------------ | |
23 | ;; Define N10 pipeline settings. | |
24 | ;; ------------------------------------------------------------------------ | |
25 | ||
26 | (define_automaton "nds32_n10_machine") | |
27 | ||
28 | ;; ------------------------------------------------------------------------ | |
29 | ;; Pipeline Stages | |
30 | ;; ------------------------------------------------------------------------ | |
31 | ;; IF - Instruction Fetch | |
32 | ;; II - Instruction Issue / Instruction Decode | |
33 | ;; EX - Instruction Execution | |
34 | ;; MM - Memory Execution | |
35 | ;; WB - Instruction Retire / Result Write-Back | |
36 | ||
37 | (define_cpu_unit "n10_ii" "nds32_n10_machine") | |
38 | (define_cpu_unit "n10_ex" "nds32_n10_machine") | |
39 | (define_cpu_unit "n10_mm" "nds32_n10_machine") | |
40 | (define_cpu_unit "n10_wb" "nds32_n10_machine") | |
41 | (define_cpu_unit "n10f_iq" "nds32_n10_machine") | |
42 | (define_cpu_unit "n10f_rf" "nds32_n10_machine") | |
43 | (define_cpu_unit "n10f_e1" "nds32_n10_machine") | |
44 | (define_cpu_unit "n10f_e2" "nds32_n10_machine") | |
45 | (define_cpu_unit "n10f_e3" "nds32_n10_machine") | |
46 | (define_cpu_unit "n10f_e4" "nds32_n10_machine") | |
47 | ||
48 | (define_insn_reservation "nds_n10_unknown" 1 | |
49 | (and (eq_attr "type" "unknown") | |
50 | (eq_attr "pipeline_model" "n10")) | |
51 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
52 | ||
53 | (define_insn_reservation "nds_n10_misc" 1 | |
54 | (and (eq_attr "type" "misc") | |
55 | (eq_attr "pipeline_model" "n10")) | |
56 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
57 | ||
58 | (define_insn_reservation "nds_n10_mmu" 1 | |
59 | (and (eq_attr "type" "mmu") | |
60 | (eq_attr "pipeline_model" "n10")) | |
61 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
62 | ||
63 | (define_insn_reservation "nds_n10_alu" 1 | |
64 | (and (eq_attr "type" "alu") | |
65 | (eq_attr "pipeline_model" "n10")) | |
66 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
67 | ||
68 | (define_insn_reservation "nds_n10_alu_shift" 1 | |
69 | (and (eq_attr "type" "alu_shift") | |
70 | (eq_attr "pipeline_model" "n10")) | |
71 | "n10_ii, n10_ii+n10_ex, n10_ex+n10_mm, n10_mm+n10_wb, n10_wb") | |
72 | ||
73 | (define_insn_reservation "nds_n10_pbsad" 1 | |
74 | (and (eq_attr "type" "pbsad") | |
75 | (eq_attr "pipeline_model" "n10")) | |
76 | "n10_ii, n10_ex*3, n10_mm, n10_wb") | |
77 | ||
78 | (define_insn_reservation "nds_n10_pbsada" 1 | |
79 | (and (eq_attr "type" "pbsada") | |
80 | (eq_attr "pipeline_model" "n10")) | |
81 | "n10_ii, n10_ex*3, n10_mm, n10_wb") | |
82 | ||
83 | (define_insn_reservation "nds_n10_load" 1 | |
84 | (and (match_test "nds32::load_single_p (insn)") | |
85 | (eq_attr "pipeline_model" "n10")) | |
86 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
87 | ||
88 | (define_insn_reservation "nds_n10_store" 1 | |
89 | (and (match_test "nds32::store_single_p (insn)") | |
90 | (eq_attr "pipeline_model" "n10")) | |
91 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
92 | ||
93 | (define_insn_reservation "nds_n10_load_multiple_1" 1 | |
94 | (and (eq_attr "pipeline_model" "n10") | |
95 | (and (eq_attr "type" "load_multiple") | |
96 | (eq_attr "combo" "1"))) | |
97 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
98 | ||
99 | (define_insn_reservation "nds_n10_load_multiple_2" 1 | |
100 | (and (eq_attr "pipeline_model" "n10") | |
101 | (ior (and (eq_attr "type" "load_multiple") | |
102 | (eq_attr "combo" "2")) | |
103 | (match_test "nds32::load_double_p (insn)"))) | |
104 | "n10_ii, n10_ii+n10_ex, n10_ex+n10_mm, n10_mm+n10_wb, n10_wb") | |
105 | ||
106 | (define_insn_reservation "nds_n10_load_multiple_3" 1 | |
107 | (and (eq_attr "pipeline_model" "n10") | |
108 | (and (eq_attr "type" "load_multiple") | |
109 | (eq_attr "combo" "3"))) | |
110 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
111 | ||
112 | (define_insn_reservation "nds_n10_load_multiple_4" 1 | |
113 | (and (eq_attr "pipeline_model" "n10") | |
114 | (and (eq_attr "type" "load_multiple") | |
115 | (eq_attr "combo" "4"))) | |
116 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ii+n10_ex+n10_mm+n10_wb, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
117 | ||
118 | (define_insn_reservation "nds_n10_load_multiple_5" 1 | |
119 | (and (eq_attr "pipeline_model" "n10") | |
120 | (and (eq_attr "type" "load_multiple") | |
121 | (eq_attr "combo" "5"))) | |
122 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*2, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
123 | ||
124 | (define_insn_reservation "nds_n10_load_multiple_6" 1 | |
125 | (and (eq_attr "pipeline_model" "n10") | |
126 | (and (eq_attr "type" "load_multiple") | |
127 | (eq_attr "combo" "6"))) | |
128 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*3, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
129 | ||
130 | (define_insn_reservation "nds_n10_load_multiple_7" 1 | |
131 | (and (eq_attr "pipeline_model" "n10") | |
132 | (and (eq_attr "type" "load_multiple") | |
133 | (eq_attr "combo" "7"))) | |
134 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*4, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
135 | ||
136 | (define_insn_reservation "nds_n10_load_multiple_N" 1 | |
137 | (and (eq_attr "pipeline_model" "n10") | |
138 | (and (eq_attr "type" "load_multiple") | |
139 | (match_test "get_attr_combo (insn) >= 8"))) | |
140 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*5, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
141 | ||
142 | (define_insn_reservation "nds_n10_store_multiple_1" 1 | |
143 | (and (eq_attr "pipeline_model" "n10") | |
144 | (and (eq_attr "type" "store_multiple") | |
145 | (eq_attr "combo" "1"))) | |
146 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
147 | ||
148 | (define_insn_reservation "nds_n10_store_multiple_2" 1 | |
149 | (and (eq_attr "pipeline_model" "n10") | |
150 | (ior (and (eq_attr "type" "store_multiple") | |
151 | (eq_attr "combo" "2")) | |
152 | (match_test "nds32::store_double_p (insn)"))) | |
153 | "n10_ii, n10_ii+n10_ex, n10_ex+n10_mm, n10_mm+n10_wb, n10_wb") | |
154 | ||
155 | (define_insn_reservation "nds_n10_store_multiple_3" 1 | |
156 | (and (eq_attr "pipeline_model" "n10") | |
157 | (and (eq_attr "type" "store_multiple") | |
158 | (eq_attr "combo" "3"))) | |
159 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
160 | ||
161 | (define_insn_reservation "nds_n10_store_multiple_4" 1 | |
162 | (and (eq_attr "pipeline_model" "n10") | |
163 | (and (eq_attr "type" "store_multiple") | |
164 | (eq_attr "combo" "4"))) | |
165 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, n10_ii+n10_ex+n10_mm+n10_wb, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
166 | ||
167 | (define_insn_reservation "nds_n10_store_multiple_5" 1 | |
168 | (and (eq_attr "pipeline_model" "n10") | |
169 | (and (eq_attr "type" "store_multiple") | |
170 | (eq_attr "combo" "5"))) | |
171 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*2, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
172 | ||
173 | (define_insn_reservation "nds_n10_store_multiple_6" 1 | |
174 | (and (eq_attr "pipeline_model" "n10") | |
175 | (and (eq_attr "type" "store_multiple") | |
176 | (eq_attr "combo" "6"))) | |
177 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*3, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
178 | ||
179 | (define_insn_reservation "nds_n10_store_multiple_7" 1 | |
180 | (and (eq_attr "pipeline_model" "n10") | |
181 | (and (eq_attr "type" "store_multiple") | |
182 | (eq_attr "combo" "7"))) | |
183 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*4, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
184 | ||
185 | (define_insn_reservation "nds_n10_store_multiple_N" 1 | |
186 | (and (eq_attr "pipeline_model" "n10") | |
187 | (and (eq_attr "type" "store_multiple") | |
188 | (match_test "get_attr_combo (insn) >= 8"))) | |
189 | "n10_ii, n10_ii+n10_ex, n10_ii+n10_ex+n10_mm, (n10_ii+n10_ex+n10_mm+n10_wb)*5, n10_ex+n10_mm+n10_wb, n10_mm+n10_wb, n10_wb") | |
190 | ||
191 | (define_insn_reservation "nds_n10_mul" 1 | |
192 | (and (eq_attr "type" "mul") | |
193 | (eq_attr "pipeline_model" "n10")) | |
194 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
195 | ||
196 | (define_insn_reservation "nds_n10_mac" 1 | |
197 | (and (eq_attr "type" "mac") | |
198 | (eq_attr "pipeline_model" "n10")) | |
199 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
200 | ||
201 | (define_insn_reservation "nds_n10_div" 1 | |
202 | (and (eq_attr "type" "div") | |
203 | (eq_attr "pipeline_model" "n10")) | |
204 | "n10_ii, n10_ex*34, n10_mm, n10_wb") | |
205 | ||
206 | (define_insn_reservation "nds_n10_branch" 1 | |
207 | (and (eq_attr "type" "branch") | |
208 | (eq_attr "pipeline_model" "n10")) | |
209 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
210 | ||
211 | (define_insn_reservation "nds_n10_dsp_alu" 1 | |
212 | (and (eq_attr "type" "dalu") | |
213 | (eq_attr "pipeline_model" "n10")) | |
214 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
215 | ||
216 | (define_insn_reservation "nds_n10_dsp_alu64" 1 | |
217 | (and (eq_attr "type" "dalu64") | |
218 | (eq_attr "pipeline_model" "n10")) | |
219 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
220 | ||
221 | (define_insn_reservation "nds_n10_dsp_alu_round" 1 | |
222 | (and (eq_attr "type" "daluround") | |
223 | (eq_attr "pipeline_model" "n10")) | |
224 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
225 | ||
226 | (define_insn_reservation "nds_n10_dsp_cmp" 1 | |
227 | (and (eq_attr "type" "dcmp") | |
228 | (eq_attr "pipeline_model" "n10")) | |
229 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
230 | ||
231 | (define_insn_reservation "nds_n10_dsp_clip" 1 | |
232 | (and (eq_attr "type" "dclip") | |
233 | (eq_attr "pipeline_model" "n10")) | |
234 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
235 | ||
236 | (define_insn_reservation "nds_n10_dsp_mul" 1 | |
237 | (and (eq_attr "type" "dmul") | |
238 | (eq_attr "pipeline_model" "n10")) | |
239 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
240 | ||
241 | (define_insn_reservation "nds_n10_dsp_mac" 1 | |
242 | (and (eq_attr "type" "dmac") | |
243 | (eq_attr "pipeline_model" "n10")) | |
244 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
245 | ||
246 | (define_insn_reservation "nds_n10_dsp_insb" 1 | |
247 | (and (eq_attr "type" "dinsb") | |
248 | (eq_attr "pipeline_model" "n10")) | |
249 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
250 | ||
251 | (define_insn_reservation "nds_n10_dsp_pack" 1 | |
252 | (and (eq_attr "type" "dpack") | |
253 | (eq_attr "pipeline_model" "n10")) | |
254 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
255 | ||
256 | (define_insn_reservation "nds_n10_dsp_bpick" 1 | |
257 | (and (eq_attr "type" "dbpick") | |
258 | (eq_attr "pipeline_model" "n10")) | |
259 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
260 | ||
261 | (define_insn_reservation "nds_n10_dsp_wext" 1 | |
262 | (and (eq_attr "type" "dwext") | |
263 | (eq_attr "pipeline_model" "n10")) | |
264 | "n10_ii, n10_ex, n10_mm, n10_wb") | |
265 | ||
266 | (define_insn_reservation "nds_n10_fpu_alu" 4 | |
267 | (and (eq_attr "type" "falu") | |
268 | (eq_attr "pipeline_model" "n10")) | |
269 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") | |
270 | ||
271 | (define_insn_reservation "nds_n10_fpu_muls" 4 | |
272 | (and (eq_attr "type" "fmuls") | |
273 | (eq_attr "pipeline_model" "n10")) | |
274 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") | |
275 | ||
276 | (define_insn_reservation "nds_n10_fpu_muld" 4 | |
277 | (and (eq_attr "type" "fmuld") | |
278 | (eq_attr "pipeline_model" "n10")) | |
279 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*2, n10f_e3, n10f_e4") | |
280 | ||
281 | (define_insn_reservation "nds_n10_fpu_macs" 4 | |
282 | (and (eq_attr "type" "fmacs") | |
283 | (eq_attr "pipeline_model" "n10")) | |
284 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*3, n10f_e3, n10f_e4") | |
285 | ||
286 | (define_insn_reservation "nds_n10_fpu_macd" 4 | |
287 | (and (eq_attr "type" "fmacd") | |
288 | (eq_attr "pipeline_model" "n10")) | |
289 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*4, n10f_e3, n10f_e4") | |
290 | ||
291 | (define_insn_reservation "nds_n10_fpu_divs" 4 | |
292 | (and (ior (eq_attr "type" "fdivs") | |
293 | (eq_attr "type" "fsqrts")) | |
294 | (eq_attr "pipeline_model" "n10")) | |
295 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*14, n10f_e3, n10f_e4") | |
296 | ||
297 | (define_insn_reservation "nds_n10_fpu_divd" 4 | |
298 | (and (ior (eq_attr "type" "fdivd") | |
299 | (eq_attr "type" "fsqrtd")) | |
300 | (eq_attr "pipeline_model" "n10")) | |
301 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2*28, n10f_e3, n10f_e4") | |
302 | ||
303 | (define_insn_reservation "nds_n10_fpu_fast_alu" 2 | |
304 | (and (ior (eq_attr "type" "fcmp") | |
305 | (ior (eq_attr "type" "fabs") | |
306 | (ior (eq_attr "type" "fcpy") | |
307 | (eq_attr "type" "fcmov")))) | |
308 | (eq_attr "pipeline_model" "n10")) | |
309 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") | |
310 | ||
311 | (define_insn_reservation "nds_n10_fpu_fmtsr" 4 | |
312 | (and (eq_attr "type" "fmtsr") | |
313 | (eq_attr "pipeline_model" "n10")) | |
314 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") | |
315 | ||
316 | (define_insn_reservation "nds_n10_fpu_fmtdr" 4 | |
317 | (and (eq_attr "type" "fmtdr") | |
318 | (eq_attr "pipeline_model" "n10")) | |
319 | "n10_ii, n10_ii+n10f_iq, n10f_iq+n10f_rf, n10f_rf+n10f_e1, n10f_e1+n10f_e2, n10f_e2+n10f_e3, n10f_e3+n10f_e4, n10f_e4") | |
320 | ||
321 | (define_insn_reservation "nds_n10_fpu_fmfsr" 2 | |
322 | (and (eq_attr "type" "fmfsr") | |
323 | (eq_attr "pipeline_model" "n10")) | |
324 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") | |
325 | ||
326 | (define_insn_reservation "nds_n10_fpu_fmfdr" 2 | |
327 | (and (eq_attr "type" "fmfdr") | |
328 | (eq_attr "pipeline_model" "n10")) | |
329 | "n10_ii, n10_ii+n10f_iq, n10f_iq+n10f_rf, n10f_rf+n10f_e1, n10f_e1+n10f_e2, n10f_e2+n10f_e3, n10f_e3+n10f_e4, n10f_e4") | |
330 | ||
331 | (define_insn_reservation "nds_n10_fpu_load" 3 | |
332 | (and (eq_attr "type" "fload") | |
333 | (eq_attr "pipeline_model" "n10")) | |
334 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") | |
335 | ||
336 | (define_insn_reservation "nds_n10_fpu_store" 1 | |
337 | (and (eq_attr "type" "fstore") | |
338 | (eq_attr "pipeline_model" "n10")) | |
339 | "n10_ii, n10f_iq, n10f_rf, n10f_e1, n10f_e2, n10f_e3, n10f_e4") | |
340 | ||
341 | ;; ------------------------------------------------------------------------ | |
342 | ;; Comment Notations and Bypass Rules | |
343 | ;; ------------------------------------------------------------------------ | |
344 | ;; Producers (LHS) | |
345 | ;; LD | |
346 | ;; Load data from the memory and produce the loaded data. The result is | |
347 | ;; ready at MM. | |
348 | ;; LMW(N, M) | |
349 | ;; There are N micro-operations within an instruction that loads multiple | |
350 | ;; words. The result produced by the M-th micro-operation is sent to | |
351 | ;; consumers. The result is ready at MM. | |
352 | ;; MUL, MAC | |
353 | ;; Compute data in the multiply-adder and produce the data. The result | |
354 | ;; is ready at MM. | |
355 | ;; DIV | |
356 | ;; Compute data in the divider and produce the data. The result is ready | |
357 | ;; at MM. | |
358 | ;; | |
359 | ;; Consumers (RHS) | |
360 | ;; ALU, MOVD44, PBSAD, PBSADA_RaRb, MUL, MAC, DIV, MMU | |
361 | ;; Require operands at EX. | |
362 | ;; ALU_SHIFT_Rb | |
363 | ;; An ALU-SHIFT instruction consists of a shift micro-operation followed | |
364 | ;; by an arithmetic micro-operation. The operand Rb is used by the first | |
365 | ;; micro-operation, and there are some latencies if data dependency occurs. | |
366 | ;; MAC_RaRb | |
367 | ;; A MAC instruction does multiplication at EX and does accumulation at MM, | |
368 | ;; so the operand Rt is required at MM, and operands Ra and Rb are required | |
369 | ;; at EX. | |
370 | ;; ADDR_IN | |
371 | ;; If an instruction requires an address as its input operand, the address | |
372 | ;; is required at EX. | |
373 | ;; ST | |
374 | ;; A store instruction requires its data at MM. | |
375 | ;; SMW(N, M) | |
376 | ;; There are N micro-operations within an instruction that stores multiple | |
377 | ;; words. Each M-th micro-operation requires its data at MM. | |
378 | ;; BR | |
379 | ;; If a branch instruction is conditional, its input data is required at EX. | |
380 | ||
381 | ;; FPU_ADDR_OUT -> FPU_ADDR_IN | |
382 | ;; Main pipeline rules don't need this because those default latency is 1. | |
383 | (define_bypass 1 | |
384 | "nds_n10_fpu_load, nds_n10_fpu_store" | |
385 | "nds_n10_fpu_load, nds_n10_fpu_store" | |
386 | "nds32_n10_ex_to_ex_p" | |
387 | ) | |
388 | ||
389 | ;; LD, MUL, MAC, DIV, DALU64, DMUL, DMAC, DALUROUND, DBPICK, DWEXT | |
390 | ;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU, | |
391 | ;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb | |
392 | (define_bypass 2 | |
393 | "nds_n10_load, nds_n10_mul, nds_n10_mac, nds_n10_div,\ | |
394 | nds_n10_dsp_alu64, nds_n10_dsp_mul, nds_n10_dsp_mac,\ | |
395 | nds_n10_dsp_alu_round, nds_n10_dsp_bpick, nds_n10_dsp_wext" | |
396 | "nds_n10_alu, nds_n10_alu_shift,\ | |
397 | nds_n10_pbsad, nds_n10_pbsada,\ | |
398 | nds_n10_mul, nds_n10_mac, nds_n10_div,\ | |
399 | nds_n10_branch,\ | |
400 | nds_n10_load, nds_n10_store,\ | |
401 | nds_n10_load_multiple_1, nds_n10_load_multiple_2, nds_n10_load_multiple_3,\ | |
402 | nds_n10_load_multiple_4, nds_n10_load_multiple_5, nds_n10_load_multiple_6,\ | |
403 | nds_n10_load_multiple_7, nds_n10_load_multiple_N,\ | |
404 | nds_n10_store_multiple_1, nds_n10_store_multiple_2, nds_n10_store_multiple_3,\ | |
405 | nds_n10_store_multiple_4, nds_n10_store_multiple_5, nds_n10_store_multiple_6,\ | |
406 | nds_n10_store_multiple_7, nds_n10_store_multiple_N,\ | |
407 | nds_n10_mmu,\ | |
408 | nds_n10_dsp_alu, nds_n10_dsp_alu_round,\ | |
409 | nds_n10_dsp_mul, nds_n10_dsp_mac, nds_n10_dsp_pack,\ | |
410 | nds_n10_dsp_insb, nds_n10_dsp_cmp, nds_n10_dsp_clip,\ | |
411 | nds_n10_dsp_wext, nds_n10_dsp_bpick" | |
412 | "nds32_n10_mm_to_ex_p" | |
413 | ) | |
414 | ||
415 | ;; LMW(N, N) | |
416 | ;; -> ALU, ALU_SHIFT_Rb, PBSAD, PBSADA_RaRb, MOVD44, MUL, MAC_RaRb, DIV, ADDR_IN, BR, MMU | |
417 | ;; DALU, DALUROUND, DMUL, DMAC_RaRb, DPACK, DINSB, DCMP, DCLIP, WEXT_O, BPICK_RaRb | |
418 | (define_bypass 2 | |
419 | "nds_n10_load_multiple_1, nds_n10_load_multiple_2, nds_n10_load_multiple_3,\ | |
420 | nds_n10_load_multiple_4, nds_n10_load_multiple_5, nds_n10_load_multiple_6,\ | |
421 | nds_n10_load_multiple_7, nds_n10_load_multiple_N" | |
422 | "nds_n10_alu, nds_n10_alu_shift,\ | |
423 | nds_n10_pbsad, nds_n10_pbsada,\ | |
424 | nds_n10_mul, nds_n10_mac, nds_n10_div,\ | |
425 | nds_n10_branch,\ | |
426 | nds_n10_load, nds_n10_store,\ | |
427 | nds_n10_load_multiple_1, nds_n10_load_multiple_2, nds_n10_load_multiple_3,\ | |
428 | nds_n10_load_multiple_4, nds_n10_load_multiple_5, nds_n10_load_multiple_6,\ | |
429 | nds_n10_load_multiple_7, nds_n10_load_multiple_N,\ | |
430 | nds_n10_store_multiple_1, nds_n10_store_multiple_2, nds_n10_store_multiple_3,\ | |
431 | nds_n10_store_multiple_4, nds_n10_store_multiple_5, nds_n10_store_multiple_6,\ | |
432 | nds_n10_store_multiple_7, nds_n10_store_multiple_N,\ | |
433 | nds_n10_mmu,\ | |
434 | nds_n10_dsp_alu, nds_n10_dsp_alu_round,\ | |
435 | nds_n10_dsp_mul, nds_n10_dsp_mac, nds_n10_dsp_pack,\ | |
436 | nds_n10_dsp_insb, nds_n10_dsp_cmp, nds_n10_dsp_clip,\ | |
437 | nds_n10_dsp_wext, nds_n10_dsp_bpick" | |
438 | "nds32_n10_last_load_to_ex_p" | |
439 | ) |