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9304f876 1/* Definitions of target machine of Andes NDS32 cpu for GNU compiler
a945c346 2 Copyright (C) 2012-2024 Free Software Foundation, Inc.
9304f876
CJW		 3 Contributed by Andes Technology Corporation.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21
22/* ------------------------------------------------------------------------ */
23
24/* The following are auxiliary macros or structure declarations
e53b6e56 25 that are used all over the nds32.cc and nds32.h. */
9304f876 26
a5876228
CJW		 27#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
28 (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
29
511a41d7
CJW		 30/* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
31 It is used in nds32_encode_section_info() to store flag in symbol_ref
32 in case the symbol should be placed in .rodata section.
33 So that we can check it in nds32_legitimate_address_p(). */
34#define NDS32_SYMBOL_FLAG_RODATA \
35 (SYMBOL_FLAG_MACH_DEP << 0)
36#define NDS32_SYMBOL_REF_RODATA_P(x) \
37 ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
9304f876 38
b26fa4f9
KLC		 39enum nds32_relax_insn_type
40{
41 RELAX_ORI,
42 RELAX_PLT_ADD,
43 RELAX_TLS_ADD_or_LW,
44 RELAX_TLS_ADD_LW,
45 RELAX_TLS_LW_JRAL,
46 RELAX_DONE
47};
48
6e9ca932
CJW		 49/* Classifies expand result for expand helper function. */
50enum nds32_expand_result_type
51{
52 EXPAND_DONE,
53 EXPAND_FAIL,
54 EXPAND_CREATE_TEMPLATE
55};
56
9304f876
CJW		 57/* Classifies address type to distinguish 16-bit/32-bit format. */
58enum nds32_16bit_address_type
59{
60 /* [reg]: 45 format address. */
61 ADDRESS_REG,
62 /* [lo_reg + imm3u]: 333 format address. */
63 ADDRESS_LO_REG_IMM3U,
64 /* post_inc [lo_reg + imm3u]: 333 format address. */
65 ADDRESS_POST_INC_LO_REG_IMM3U,
67e1eb3d
SC		 66 /* post_modify [lo_reg + imm3u]: 333 format address. */
67 ADDRESS_POST_MODIFY_LO_REG_IMM3U,
8656bbcf
SC		 68 /* [$r8 + imm7u]: r8 imply address. */
69 ADDRESS_R8_IMM7U,
9304f876
CJW		 70 /* [$fp + imm7u]: fp imply address. */
71 ADDRESS_FP_IMM7U,
72 /* [$sp + imm7u]: sp imply address. */
73 ADDRESS_SP_IMM7U,
74 /* Other address format. */
75 ADDRESS_NOT_16BIT_FORMAT
76};
77
78
79/* ------------------------------------------------------------------------ */
80
81/* Define maximum numbers of registers for passing arguments. */
9d93cc24 82#define NDS32_MAX_GPR_REGS_FOR_ARGS 6
e2286268 83#define NDS32_MAX_FPR_REGS_FOR_ARGS 6
9304f876
CJW		 84
85/* Define the register number for first argument. */
86#define NDS32_GPR_ARG_FIRST_REGNUM 0
e2286268 87#define NDS32_FPR_ARG_FIRST_REGNUM 34
9304f876
CJW		 88
89/* Define the register number for return value. */
90#define NDS32_GPR_RET_FIRST_REGNUM 0
e2286268 91#define NDS32_FPR_RET_FIRST_REGNUM 34
9304f876 92
9d93cc24
CJW		 93/* Define the first integer register number. */
94#define NDS32_FIRST_GPR_REGNUM 0
95/* Define the last integer register number. */
96#define NDS32_LAST_GPR_REGNUM 31
9304f876 97
a6c7e777
MC		 98#define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6
99#define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \
100 (TARGET_REDUCED_REGS ? 10 : 14)
101
e2286268
MC		 102/* Define the floating-point number of registers. */
103#define NDS32_FLOAT_REGISTER_NUMBER \
104 (((nds32_fp_regnum == NDS32_CONFIG_FPU_0) \
105 || (nds32_fp_regnum == NDS32_CONFIG_FPU_4)) ? 8 \
106 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_1) \
107 || (nds32_fp_regnum == NDS32_CONFIG_FPU_5)) ? 16 \
108 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_2) \
109 || (nds32_fp_regnum == NDS32_CONFIG_FPU_6)) ? 32 \
110 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_3) \
111 || (nds32_fp_regnum == NDS32_CONFIG_FPU_7)) ? 64 \
112 : 32)
113
114#define NDS32_EXT_FPU_DOT_E (nds32_fp_regnum >= 4)
115
116/* Define the first floating-point register number. */
117#define NDS32_FIRST_FPR_REGNUM 34
118/* Define the last floating-point register number. */
119#define NDS32_LAST_FPR_REGNUM \
120 (NDS32_FIRST_FPR_REGNUM + NDS32_FLOAT_REGISTER_NUMBER - 1)
121
122
123#define NDS32_IS_EXT_FPR_REGNUM(regno) \
124 (((regno) >= NDS32_FIRST_FPR_REGNUM + 32) \
125 && ((regno) < NDS32_FIRST_FPR_REGNUM + 64))
126
127#define NDS32_IS_FPR_REGNUM(regno) \
128 (((regno) >= NDS32_FIRST_FPR_REGNUM) \
129 && ((regno) <= NDS32_LAST_FPR_REGNUM))
130
131#define NDS32_FPR_REGNO_OK_FOR_SINGLE(regno) \
132 ((regno) <= NDS32_LAST_FPR_REGNUM)
133
134#define NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) \
135 ((((regno) - NDS32_FIRST_FPR_REGNUM) & 1) == 0)
136
137#define NDS32_IS_GPR_REGNUM(regno) \
138 (((regno) <= NDS32_LAST_GPR_REGNUM))
139
9304f876
CJW		 140/* Define double word alignment bits. */
141#define NDS32_DOUBLE_WORD_ALIGNMENT 64
142
143/* Define alignment checking macros for convenience. */
144#define NDS32_HALF_WORD_ALIGN_P(value) (((value) & 0x01) == 0)
145#define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
146#define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
147
43fa41c1
CJW		 148/* Determine whether we would like to have code generation strictly aligned.
149 We set it strictly aligned when -malways-align is enabled.
e53b6e56 150 Check gcc/common/config/nds32/nds32-common.cc for the optimizations that
43fa41c1
CJW		 151 apply -malways-align. */
152#define NDS32_ALIGN_P() (TARGET_ALWAYS_ALIGN)
7c32ef41
MC		 153
154#define NDS32_EXT_DSP_P() (TARGET_EXT_DSP && !TARGET_FORCE_NO_EXT_DSP)
155
634bdae9
CJW		 156/* Get alignment according to mode or type information.
157 When 'type' is nonnull, there is no need to look at 'mode'. */
158#define NDS32_MODE_TYPE_ALIGN(mode, type) \
159 (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
160
9304f876
CJW		 161/* Round X up to the nearest double word. */
162#define NDS32_ROUND_UP_DOUBLE_WORD(value) (((value) + 7) & ~7)
163
164
165/* This macro is used to calculate the numbers of registers for
166 containing 'size' bytes of the argument.
167 The size of a register is a word in nds32 target.
168 So we use UNITS_PER_WORD to do the calculation. */
169#define NDS32_NEED_N_REGS_FOR_ARG(mode, type) \
170 ((mode == BLKmode) \
171 ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
172 : ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
173
174/* This macro is used to return the register number for passing argument.
175 We need to obey the following rules:
176 1. If it is required MORE THAN one register,
8a498f99
CJW		 177 we need to further check if it really needs to be
178 aligned on double words.
179 a) If double word alignment is necessary,
180 the register number must be even value.
181 b) Otherwise, the register number can be odd or even value.
9304f876 182 2. If it is required ONLY one register,
8a498f99
CJW		 183 the register number can be odd or even value. */
184#define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \
185 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
186 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
187 ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \
188 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \
9304f876
CJW		 189 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
190
e2286268
MC		 191#define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \
192 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \
193 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \
194 ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1) \
195 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM)) \
196 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM))
197
198/* These two macros are to check if there are still available registers
7f6cd86b
CJW		 199 for passing argument, which must be entirely in registers. */
200#define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \
201 ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
202 + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \
203 <= (NDS32_GPR_ARG_FIRST_REGNUM \
204 + NDS32_MAX_GPR_REGS_FOR_ARGS))
205
e2286268
MC		 206#define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type) \
207 ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
208 + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \
209 <= (NDS32_FPR_ARG_FIRST_REGNUM \
210 + NDS32_MAX_FPR_REGS_FOR_ARGS))
211
212/* These two macros are to check if there are still available registers
7f6cd86b
CJW		 213 for passing argument, either entirely in registers or partially
214 in registers. */
215#define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
216 (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
217 < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
9304f876 218
e2286268
MC		 219#define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \
220 (NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \
221 < NDS32_FPR_ARG_FIRST_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS)
222
9304f876
CJW		 223/* This macro is to check if the register is required to be saved on stack.
224 If call_used_regs[regno] == 0, regno is the callee-saved register.
225 If df_regs_ever_live_p(regno) == true, it is used in the current function.
226 As long as the register satisfies both criteria above,
227 it is required to be saved. */
228#define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \
a365fa06 229 (!call_used_or_fixed_reg_p (regno) && df_regs_ever_live_p (regno))
9304f876 230
a6c7e777
MC		 231/* This macro is to check if the push25/pop25 are available to be used
232 for code generation. Because pop25 also performs return behavior,
233 the instructions may not be available for some cases.
234 If we want to use push25/pop25, all the following conditions must
235 be satisfied:
236 1. TARGET_V3PUSH is set.
237 2. Current function is not an ISR function.
238 3. Current function is not a variadic function.*/
239#define NDS32_V3PUSH_AVAILABLE_P \
240 (TARGET_V3PUSH \
241 && !nds32_isr_function_p (current_function_decl) \
242 && (cfun->machine->va_args_size == 0))
243
9304f876
CJW		 244/* ------------------------------------------------------------------------ */
245
246/* A C structure for machine-specific, per-function data.
247 This is added to the cfun structure. */
248struct GTY(()) machine_function
249{
250 /* Number of bytes allocated on the stack for variadic args
251 if we want to push them into stack as pretend arguments by ourself. */
252 int va_args_size;
253 /* Number of bytes reserved on the stack for
254 local and temporary variables. */
255 int local_size;
256 /* Number of bytes allocated on the stack for outgoing arguments. */
257 int out_args_size;
258
259 /* Number of bytes on the stack for saving $fp. */
260 int fp_size;
261 /* Number of bytes on the stack for saving $gp. */
262 int gp_size;
263 /* Number of bytes on the stack for saving $lp. */
264 int lp_size;
265
c457f751
CJW		 266 /* Number of bytes on the stack for saving general purpose
267 callee-saved registers. */
268 int callee_saved_gpr_regs_size;
269
e2286268
MC		 270 /* Number of bytes on the stack for saving floating-point
271 callee-saved registers. */
272 int callee_saved_fpr_regs_size;
273
9304f876 274 /* The padding bytes in callee-saved area may be required. */
c457f751 275 int callee_saved_area_gpr_padding_bytes;
9304f876 276
c457f751
CJW		 277 /* The first required general purpose callee-saved register. */
278 int callee_saved_first_gpr_regno;
279 /* The last required general purpose callee-saved register. */
280 int callee_saved_last_gpr_regno;
9304f876 281
e2286268
MC		 282 /* The first required floating-point callee-saved register. */
283 int callee_saved_first_fpr_regno;
284 /* The last required floating-point callee-saved register. */
285 int callee_saved_last_fpr_regno;
286
dd1536a7
CJW		 287 /* The padding bytes in varargs area may be required. */
288 int va_args_area_padding_bytes;
289
290 /* The first required register that should be saved on stack for va_args. */
291 int va_args_first_regno;
292 /* The last required register that should be saved on stack for va_args. */
293 int va_args_last_regno;
294
ca3a4a55
CJW		 295 /* Number of bytes on the stack for saving exception handling registers. */
296 int eh_return_data_regs_size;
297 /* The first register of passing exception handling information. */
298 int eh_return_data_first_regno;
299 /* The last register of passing exception handling information. */
300 int eh_return_data_last_regno;
301
302 /* Indicate that whether this function
303 calls __builtin_eh_return. */
304 int use_eh_return_p;
305
9304f876
CJW		 306 /* Indicate that whether this function needs
307 prologue/epilogue code generation. */
308 int naked_p;
309 /* Indicate that whether this function
310 uses fp_as_gp optimization. */
311 int fp_as_gp_p;
5f2a98c3
CJW		 312 /* Indicate that whether this function is under strictly aligned
313 situation for legitimate address checking. This flag informs
314 nds32_legitimate_address_p() how to treat offset alignment:
315 1. The IVOPT phase needs to detect available range for memory access,
316 such as checking [base + 32767] ~ [base + (-32768)].
317 For this case we do not want address to be strictly aligned.
318 2. The rtl lowering and optimization are close to target code.
319 For this case we need address to be strictly aligned. */
320 int strict_aligned_p;
54c537e6
CJW		 321
322 /* Record two similar attributes status. */
323 int attr_naked_p;
324 int attr_no_prologue_p;
9304f876
CJW		 325};
326
327/* A C structure that contains the arguments information. */
328typedef struct
329{
9d93cc24 330 unsigned int gpr_offset;
e2286268 331 unsigned int fpr_offset;
9304f876
CJW		 332} nds32_cumulative_args;
333
334/* ------------------------------------------------------------------------ */
335
336/* The following we define C-ISR related stuff.
337 In nds32 architecture, we have 73 vectors for interrupt/exception.
338 For each vector (except for vector 0, which is used for reset behavior),
339 we allow users to set its register saving scheme and interrupt level. */
340
341/* There are 73 vectors in nds32 architecture.
342 0 for reset handler,
343 1-8 for exception handler,
344 and 9-72 for interrupt handler.
e53b6e56 345 We use an array, which is defined in nds32.cc, to record
9304f876
CJW		 346 essential information for each vector. */
347#define NDS32_N_ISR_VECTORS 73
348
349/* Define possible isr category. */
350enum nds32_isr_category
351{
352 NDS32_ISR_NONE,
353 NDS32_ISR_INTERRUPT,
354 NDS32_ISR_EXCEPTION,
355 NDS32_ISR_RESET
356};
357
358/* Define isr register saving scheme. */
359enum nds32_isr_save_reg
360{
361 NDS32_SAVE_ALL,
362 NDS32_PARTIAL_SAVE
363};
364
365/* Define isr nested type. */
366enum nds32_isr_nested_type
367{
368 NDS32_NESTED,
369 NDS32_NOT_NESTED,
a4931745
CJW		 370 NDS32_NESTED_READY,
371 NDS32_CRITICAL
9304f876
CJW		 372};
373
374/* Define structure to record isr information.
375 The isr vector array 'isr_vectors[]' with this structure
e53b6e56 376 is defined in nds32.cc. */
9304f876
CJW		 377struct nds32_isr_info
378{
379 /* The field to identify isr category.
380 It should be set to NDS32_ISR_NONE by default.
381 If user specifies a function as isr by using attribute,
382 this field will be set accordingly. */
383 enum nds32_isr_category category;
384
385 /* A string for the applied function name.
386 It should be set to empty string by default. */
387 char func_name[100];
388
389 /* The register saving scheme.
390 It should be set to NDS32_PARTIAL_SAVE by default
391 unless user specifies attribute to change it. */
392 enum nds32_isr_save_reg save_reg;
393
394 /* The nested type.
395 It should be set to NDS32_NOT_NESTED by default
396 unless user specifies attribute to change it. */
397 enum nds32_isr_nested_type nested_type;
398
a4931745
CJW		 399 /* Secure isr level.
400 Currently we have 0-3 security level.
401 It should be set to 0 by default.
402 For security processors, this is determined by secure
403 attribute or compiler options. */
404 unsigned int security_level;
405
9304f876
CJW		 406 /* Total vectors.
407 The total vectors = interrupt + exception numbers + reset.
408 It should be set to 0 by default.
409 This field is ONLY used in NDS32_ISR_RESET category. */
410 unsigned int total_n_vectors;
411
412 /* A string for nmi handler name.
413 It should be set to empty string by default.
414 This field is ONLY used in NDS32_ISR_RESET category. */
415 char nmi_name[100];
416
417 /* A string for warm handler name.
418 It should be set to empty string by default.
419 This field is ONLY used in NDS32_ISR_RESET category. */
420 char warm_name[100];
421};
422
423/* ------------------------------------------------------------------------ */
424
425/* Define code for all nds32 builtins. */
426enum nds32_builtins
427{
428 NDS32_BUILTIN_ISYNC,
429 NDS32_BUILTIN_ISB,
154e3ea6
MC		 430 NDS32_BUILTIN_DSB,
431 NDS32_BUILTIN_MSYNC_ALL,
432 NDS32_BUILTIN_MSYNC_STORE,
9304f876
CJW		 433 NDS32_BUILTIN_MFSR,
434 NDS32_BUILTIN_MFUSR,
435 NDS32_BUILTIN_MTSR,
154e3ea6
MC		 436 NDS32_BUILTIN_MTSR_ISB,
437 NDS32_BUILTIN_MTSR_DSB,
9304f876
CJW		 438 NDS32_BUILTIN_MTUSR,
439 NDS32_BUILTIN_SETGIE_EN,
7a12ea32 440 NDS32_BUILTIN_SETGIE_DIS,
0bb4423d
MC		 441 NDS32_BUILTIN_FMFCFG,
442 NDS32_BUILTIN_FMFCSR,
443 NDS32_BUILTIN_FMTCSR,
444 NDS32_BUILTIN_FCPYNSS,
445 NDS32_BUILTIN_FCPYSS,
446 NDS32_BUILTIN_FCPYNSD,
447 NDS32_BUILTIN_FCPYSD,
2feae6cd
MC		 448 NDS32_BUILTIN_ABS,
449 NDS32_BUILTIN_AVE,
450 NDS32_BUILTIN_BCLR,
451 NDS32_BUILTIN_BSET,
452 NDS32_BUILTIN_BTGL,
453 NDS32_BUILTIN_BTST,
454 NDS32_BUILTIN_CLIP,
455 NDS32_BUILTIN_CLIPS,
456 NDS32_BUILTIN_CLZ,
457 NDS32_BUILTIN_CLO,
458 NDS32_BUILTIN_MAX,
459 NDS32_BUILTIN_MIN,
460 NDS32_BUILTIN_PBSAD,
461 NDS32_BUILTIN_PBSADA,
462 NDS32_BUILTIN_BSE,
463 NDS32_BUILTIN_BSP,
3999578c
MC		 464 NDS32_BUILTIN_FFB,
465 NDS32_BUILTIN_FFMISM,
466 NDS32_BUILTIN_FLMISM,
7c32ef41
MC		 467 NDS32_BUILTIN_KADDW,
468 NDS32_BUILTIN_KSUBW,
469 NDS32_BUILTIN_KADDH,
470 NDS32_BUILTIN_KSUBH,
471 NDS32_BUILTIN_KDMBB,
472 NDS32_BUILTIN_V_KDMBB,
473 NDS32_BUILTIN_KDMBT,
474 NDS32_BUILTIN_V_KDMBT,
475 NDS32_BUILTIN_KDMTB,
476 NDS32_BUILTIN_V_KDMTB,
477 NDS32_BUILTIN_KDMTT,
478 NDS32_BUILTIN_V_KDMTT,
479 NDS32_BUILTIN_KHMBB,
480 NDS32_BUILTIN_V_KHMBB,
481 NDS32_BUILTIN_KHMBT,
482 NDS32_BUILTIN_V_KHMBT,
483 NDS32_BUILTIN_KHMTB,
484 NDS32_BUILTIN_V_KHMTB,
485 NDS32_BUILTIN_KHMTT,
486 NDS32_BUILTIN_V_KHMTT,
487 NDS32_BUILTIN_KSLRAW,
488 NDS32_BUILTIN_KSLRAW_U,
489 NDS32_BUILTIN_RDOV,
490 NDS32_BUILTIN_CLROV,
2feae6cd
MC		 491 NDS32_BUILTIN_ROTR,
492 NDS32_BUILTIN_SVA,
493 NDS32_BUILTIN_SVS,
494 NDS32_BUILTIN_WSBH,
495 NDS32_BUILTIN_JR_ITOFF,
496 NDS32_BUILTIN_JR_TOFF,
497 NDS32_BUILTIN_JRAL_ITON,
498 NDS32_BUILTIN_JRAL_TON,
499 NDS32_BUILTIN_RET_ITOFF,
500 NDS32_BUILTIN_RET_TOFF,
501 NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT,
502 NDS32_BUILTIN_STANDBY_WAKE_GRANT,
503 NDS32_BUILTIN_STANDBY_WAKE_DONE,
504 NDS32_BUILTIN_TEQZ,
505 NDS32_BUILTIN_TNEZ,
506 NDS32_BUILTIN_TRAP,
507 NDS32_BUILTIN_SETEND_BIG,
508 NDS32_BUILTIN_SETEND_LITTLE,
509 NDS32_BUILTIN_SYSCALL,
510 NDS32_BUILTIN_BREAK,
511 NDS32_BUILTIN_NOP,
512 NDS32_BUILTIN_SCHE_BARRIER,
513 NDS32_BUILTIN_GET_CURRENT_SP,
514 NDS32_BUILTIN_SET_CURRENT_SP,
515 NDS32_BUILTIN_RETURN_ADDRESS,
154e3ea6
MC		 516 NDS32_BUILTIN_LLW,
517 NDS32_BUILTIN_LWUP,
518 NDS32_BUILTIN_LBUP,
519 NDS32_BUILTIN_SCW,
520 NDS32_BUILTIN_SWUP,
521 NDS32_BUILTIN_SBUP,
f1a0afe2
MC		 522 NDS32_BUILTIN_CCTL_VA_LCK,
523 NDS32_BUILTIN_CCTL_IDX_WBINVAL,
524 NDS32_BUILTIN_CCTL_VA_WBINVAL_L1,
525 NDS32_BUILTIN_CCTL_VA_WBINVAL_LA,
526 NDS32_BUILTIN_CCTL_IDX_READ,
527 NDS32_BUILTIN_CCTL_IDX_WRITE,
528 NDS32_BUILTIN_CCTL_L1D_INVALALL,
529 NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL,
530 NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL,
57aaf0cc
MC		 531 NDS32_BUILTIN_DPREF_QW,
532 NDS32_BUILTIN_DPREF_HW,
533 NDS32_BUILTIN_DPREF_W,
534 NDS32_BUILTIN_DPREF_DW,
535 NDS32_BUILTIN_TLBOP_TRD,
536 NDS32_BUILTIN_TLBOP_TWR,
537 NDS32_BUILTIN_TLBOP_RWR,
538 NDS32_BUILTIN_TLBOP_RWLK,
539 NDS32_BUILTIN_TLBOP_UNLK,
540 NDS32_BUILTIN_TLBOP_PB,
541 NDS32_BUILTIN_TLBOP_INV,
542 NDS32_BUILTIN_TLBOP_FLUA,
e576ddb5
KC		 543 NDS32_BUILTIN_UALOAD_HW,
544 NDS32_BUILTIN_UALOAD_W,
545 NDS32_BUILTIN_UALOAD_DW,
546 NDS32_BUILTIN_UASTORE_HW,
547 NDS32_BUILTIN_UASTORE_W,
548 NDS32_BUILTIN_UASTORE_DW,
8b9322f0
MC		 549 NDS32_BUILTIN_GIE_DIS,
550 NDS32_BUILTIN_GIE_EN,
551 NDS32_BUILTIN_ENABLE_INT,
552 NDS32_BUILTIN_DISABLE_INT,
553 NDS32_BUILTIN_SET_PENDING_SWINT,
554 NDS32_BUILTIN_CLR_PENDING_SWINT,
555 NDS32_BUILTIN_CLR_PENDING_HWINT,
556 NDS32_BUILTIN_GET_ALL_PENDING_INT,
557 NDS32_BUILTIN_GET_PENDING_INT,
558 NDS32_BUILTIN_SET_INT_PRIORITY,
559 NDS32_BUILTIN_GET_INT_PRIORITY,
560 NDS32_BUILTIN_SET_TRIG_LEVEL,
561 NDS32_BUILTIN_SET_TRIG_EDGE,
562 NDS32_BUILTIN_GET_TRIG_TYPE,
7c32ef41
MC		 563 NDS32_BUILTIN_DSP_BEGIN,
564 NDS32_BUILTIN_ADD16,
565 NDS32_BUILTIN_V_UADD16,
566 NDS32_BUILTIN_V_SADD16,
567 NDS32_BUILTIN_RADD16,
568 NDS32_BUILTIN_V_RADD16,
569 NDS32_BUILTIN_URADD16,
570 NDS32_BUILTIN_V_URADD16,
571 NDS32_BUILTIN_KADD16,
572 NDS32_BUILTIN_V_KADD16,
573 NDS32_BUILTIN_UKADD16,
574 NDS32_BUILTIN_V_UKADD16,
575 NDS32_BUILTIN_SUB16,
576 NDS32_BUILTIN_V_USUB16,
577 NDS32_BUILTIN_V_SSUB16,
578 NDS32_BUILTIN_RSUB16,
579 NDS32_BUILTIN_V_RSUB16,
580 NDS32_BUILTIN_URSUB16,
581 NDS32_BUILTIN_V_URSUB16,
582 NDS32_BUILTIN_KSUB16,
583 NDS32_BUILTIN_V_KSUB16,
584 NDS32_BUILTIN_UKSUB16,
585 NDS32_BUILTIN_V_UKSUB16,
586 NDS32_BUILTIN_CRAS16,
587 NDS32_BUILTIN_V_UCRAS16,
588 NDS32_BUILTIN_V_SCRAS16,
589 NDS32_BUILTIN_RCRAS16,
590 NDS32_BUILTIN_V_RCRAS16,
591 NDS32_BUILTIN_URCRAS16,
592 NDS32_BUILTIN_V_URCRAS16,
593 NDS32_BUILTIN_KCRAS16,
594 NDS32_BUILTIN_V_KCRAS16,
595 NDS32_BUILTIN_UKCRAS16,
596 NDS32_BUILTIN_V_UKCRAS16,
597 NDS32_BUILTIN_CRSA16,
598 NDS32_BUILTIN_V_UCRSA16,
599 NDS32_BUILTIN_V_SCRSA16,
600 NDS32_BUILTIN_RCRSA16,
601 NDS32_BUILTIN_V_RCRSA16,
602 NDS32_BUILTIN_URCRSA16,
603 NDS32_BUILTIN_V_URCRSA16,
604 NDS32_BUILTIN_KCRSA16,
605 NDS32_BUILTIN_V_KCRSA16,
606 NDS32_BUILTIN_UKCRSA16,
607 NDS32_BUILTIN_V_UKCRSA16,
608 NDS32_BUILTIN_ADD8,
609 NDS32_BUILTIN_V_UADD8,
610 NDS32_BUILTIN_V_SADD8,
611 NDS32_BUILTIN_RADD8,
612 NDS32_BUILTIN_V_RADD8,
613 NDS32_BUILTIN_URADD8,
614 NDS32_BUILTIN_V_URADD8,
615 NDS32_BUILTIN_KADD8,
616 NDS32_BUILTIN_V_KADD8,
617 NDS32_BUILTIN_UKADD8,
618 NDS32_BUILTIN_V_UKADD8,
619 NDS32_BUILTIN_SUB8,
620 NDS32_BUILTIN_V_USUB8,
621 NDS32_BUILTIN_V_SSUB8,
622 NDS32_BUILTIN_RSUB8,
623 NDS32_BUILTIN_V_RSUB8,
624 NDS32_BUILTIN_URSUB8,
625 NDS32_BUILTIN_V_URSUB8,
626 NDS32_BUILTIN_KSUB8,
627 NDS32_BUILTIN_V_KSUB8,
628 NDS32_BUILTIN_UKSUB8,
629 NDS32_BUILTIN_V_UKSUB8,
630 NDS32_BUILTIN_SRA16,
631 NDS32_BUILTIN_V_SRA16,
632 NDS32_BUILTIN_SRA16_U,
633 NDS32_BUILTIN_V_SRA16_U,
634 NDS32_BUILTIN_SRL16,
635 NDS32_BUILTIN_V_SRL16,
636 NDS32_BUILTIN_SRL16_U,
637 NDS32_BUILTIN_V_SRL16_U,
638 NDS32_BUILTIN_SLL16,
639 NDS32_BUILTIN_V_SLL16,
640 NDS32_BUILTIN_KSLL16,
641 NDS32_BUILTIN_V_KSLL16,
642 NDS32_BUILTIN_KSLRA16,
643 NDS32_BUILTIN_V_KSLRA16,
644 NDS32_BUILTIN_KSLRA16_U,
645 NDS32_BUILTIN_V_KSLRA16_U,
646 NDS32_BUILTIN_CMPEQ16,
647 NDS32_BUILTIN_V_SCMPEQ16,
648 NDS32_BUILTIN_V_UCMPEQ16,
649 NDS32_BUILTIN_SCMPLT16,
650 NDS32_BUILTIN_V_SCMPLT16,
651 NDS32_BUILTIN_SCMPLE16,
652 NDS32_BUILTIN_V_SCMPLE16,
653 NDS32_BUILTIN_UCMPLT16,
654 NDS32_BUILTIN_V_UCMPLT16,
655 NDS32_BUILTIN_UCMPLE16,
656 NDS32_BUILTIN_V_UCMPLE16,
657 NDS32_BUILTIN_CMPEQ8,
658 NDS32_BUILTIN_V_SCMPEQ8,
659 NDS32_BUILTIN_V_UCMPEQ8,
660 NDS32_BUILTIN_SCMPLT8,
661 NDS32_BUILTIN_V_SCMPLT8,
662 NDS32_BUILTIN_SCMPLE8,
663 NDS32_BUILTIN_V_SCMPLE8,
664 NDS32_BUILTIN_UCMPLT8,
665 NDS32_BUILTIN_V_UCMPLT8,
666 NDS32_BUILTIN_UCMPLE8,
667 NDS32_BUILTIN_V_UCMPLE8,
668 NDS32_BUILTIN_SMIN16,
669 NDS32_BUILTIN_V_SMIN16,
670 NDS32_BUILTIN_UMIN16,
671 NDS32_BUILTIN_V_UMIN16,
672 NDS32_BUILTIN_SMAX16,
673 NDS32_BUILTIN_V_SMAX16,
674 NDS32_BUILTIN_UMAX16,
675 NDS32_BUILTIN_V_UMAX16,
676 NDS32_BUILTIN_SCLIP16,
677 NDS32_BUILTIN_V_SCLIP16,
678 NDS32_BUILTIN_UCLIP16,
679 NDS32_BUILTIN_V_UCLIP16,
680 NDS32_BUILTIN_KHM16,
681 NDS32_BUILTIN_V_KHM16,
682 NDS32_BUILTIN_KHMX16,
683 NDS32_BUILTIN_V_KHMX16,
684 NDS32_BUILTIN_KABS16,
685 NDS32_BUILTIN_V_KABS16,
686 NDS32_BUILTIN_SMIN8,
687 NDS32_BUILTIN_V_SMIN8,
688 NDS32_BUILTIN_UMIN8,
689 NDS32_BUILTIN_V_UMIN8,
690 NDS32_BUILTIN_SMAX8,
691 NDS32_BUILTIN_V_SMAX8,
692 NDS32_BUILTIN_UMAX8,
693 NDS32_BUILTIN_V_UMAX8,
694 NDS32_BUILTIN_KABS8,
695 NDS32_BUILTIN_V_KABS8,
696 NDS32_BUILTIN_SUNPKD810,
697 NDS32_BUILTIN_V_SUNPKD810,
698 NDS32_BUILTIN_SUNPKD820,
699 NDS32_BUILTIN_V_SUNPKD820,
700 NDS32_BUILTIN_SUNPKD830,
701 NDS32_BUILTIN_V_SUNPKD830,
702 NDS32_BUILTIN_SUNPKD831,
703 NDS32_BUILTIN_V_SUNPKD831,
704 NDS32_BUILTIN_ZUNPKD810,
705 NDS32_BUILTIN_V_ZUNPKD810,
706 NDS32_BUILTIN_ZUNPKD820,
707 NDS32_BUILTIN_V_ZUNPKD820,
708 NDS32_BUILTIN_ZUNPKD830,
709 NDS32_BUILTIN_V_ZUNPKD830,
710 NDS32_BUILTIN_ZUNPKD831,
711 NDS32_BUILTIN_V_ZUNPKD831,
712 NDS32_BUILTIN_RADDW,
713 NDS32_BUILTIN_URADDW,
714 NDS32_BUILTIN_RSUBW,
715 NDS32_BUILTIN_URSUBW,
716 NDS32_BUILTIN_SRA_U,
717 NDS32_BUILTIN_KSLL,
718 NDS32_BUILTIN_PKBB16,
719 NDS32_BUILTIN_V_PKBB16,
720 NDS32_BUILTIN_PKBT16,
721 NDS32_BUILTIN_V_PKBT16,
722 NDS32_BUILTIN_PKTB16,
723 NDS32_BUILTIN_V_PKTB16,
724 NDS32_BUILTIN_PKTT16,
725 NDS32_BUILTIN_V_PKTT16,
726 NDS32_BUILTIN_SMMUL,
727 NDS32_BUILTIN_SMMUL_U,
728 NDS32_BUILTIN_KMMAC,
729 NDS32_BUILTIN_KMMAC_U,
730 NDS32_BUILTIN_KMMSB,
731 NDS32_BUILTIN_KMMSB_U,
732 NDS32_BUILTIN_KWMMUL,
733 NDS32_BUILTIN_KWMMUL_U,
734 NDS32_BUILTIN_SMMWB,
735 NDS32_BUILTIN_V_SMMWB,
736 NDS32_BUILTIN_SMMWB_U,
737 NDS32_BUILTIN_V_SMMWB_U,
738 NDS32_BUILTIN_SMMWT,
739 NDS32_BUILTIN_V_SMMWT,
740 NDS32_BUILTIN_SMMWT_U,
741 NDS32_BUILTIN_V_SMMWT_U,
742 NDS32_BUILTIN_KMMAWB,
743 NDS32_BUILTIN_V_KMMAWB,
744 NDS32_BUILTIN_KMMAWB_U,
745 NDS32_BUILTIN_V_KMMAWB_U,
746 NDS32_BUILTIN_KMMAWT,
747 NDS32_BUILTIN_V_KMMAWT,
748 NDS32_BUILTIN_KMMAWT_U,
749 NDS32_BUILTIN_V_KMMAWT_U,
750 NDS32_BUILTIN_SMBB,
751 NDS32_BUILTIN_V_SMBB,
752 NDS32_BUILTIN_SMBT,
753 NDS32_BUILTIN_V_SMBT,
754 NDS32_BUILTIN_SMTT,
755 NDS32_BUILTIN_V_SMTT,
756 NDS32_BUILTIN_KMDA,
757 NDS32_BUILTIN_V_KMDA,
758 NDS32_BUILTIN_KMXDA,
759 NDS32_BUILTIN_V_KMXDA,
760 NDS32_BUILTIN_SMDS,
761 NDS32_BUILTIN_V_SMDS,
762 NDS32_BUILTIN_SMDRS,
763 NDS32_BUILTIN_V_SMDRS,
764 NDS32_BUILTIN_SMXDS,
765 NDS32_BUILTIN_V_SMXDS,
766 NDS32_BUILTIN_KMABB,
767 NDS32_BUILTIN_V_KMABB,
768 NDS32_BUILTIN_KMABT,
769 NDS32_BUILTIN_V_KMABT,
770 NDS32_BUILTIN_KMATT,
771 NDS32_BUILTIN_V_KMATT,
772 NDS32_BUILTIN_KMADA,
773 NDS32_BUILTIN_V_KMADA,
774 NDS32_BUILTIN_KMAXDA,
775 NDS32_BUILTIN_V_KMAXDA,
776 NDS32_BUILTIN_KMADS,
777 NDS32_BUILTIN_V_KMADS,
778 NDS32_BUILTIN_KMADRS,
779 NDS32_BUILTIN_V_KMADRS,
780 NDS32_BUILTIN_KMAXDS,
781 NDS32_BUILTIN_V_KMAXDS,
782 NDS32_BUILTIN_KMSDA,
783 NDS32_BUILTIN_V_KMSDA,
784 NDS32_BUILTIN_KMSXDA,
785 NDS32_BUILTIN_V_KMSXDA,
786 NDS32_BUILTIN_SMAL,
787 NDS32_BUILTIN_V_SMAL,
788 NDS32_BUILTIN_BITREV,
789 NDS32_BUILTIN_WEXT,
790 NDS32_BUILTIN_BPICK,
791 NDS32_BUILTIN_INSB,
792 NDS32_BUILTIN_SADD64,
793 NDS32_BUILTIN_UADD64,
794 NDS32_BUILTIN_RADD64,
795 NDS32_BUILTIN_URADD64,
796 NDS32_BUILTIN_KADD64,
797 NDS32_BUILTIN_UKADD64,
798 NDS32_BUILTIN_SSUB64,
799 NDS32_BUILTIN_USUB64,
800 NDS32_BUILTIN_RSUB64,
801 NDS32_BUILTIN_URSUB64,
802 NDS32_BUILTIN_KSUB64,
803 NDS32_BUILTIN_UKSUB64,
804 NDS32_BUILTIN_SMAR64,
805 NDS32_BUILTIN_SMSR64,
806 NDS32_BUILTIN_UMAR64,
807 NDS32_BUILTIN_UMSR64,
808 NDS32_BUILTIN_KMAR64,
809 NDS32_BUILTIN_KMSR64,
810 NDS32_BUILTIN_UKMAR64,
811 NDS32_BUILTIN_UKMSR64,
812 NDS32_BUILTIN_SMALBB,
813 NDS32_BUILTIN_V_SMALBB,
814 NDS32_BUILTIN_SMALBT,
815 NDS32_BUILTIN_V_SMALBT,
816 NDS32_BUILTIN_SMALTT,
817 NDS32_BUILTIN_V_SMALTT,
818 NDS32_BUILTIN_SMALDA,
819 NDS32_BUILTIN_V_SMALDA,
820 NDS32_BUILTIN_SMALXDA,
821 NDS32_BUILTIN_V_SMALXDA,
822 NDS32_BUILTIN_SMALDS,
823 NDS32_BUILTIN_V_SMALDS,
824 NDS32_BUILTIN_SMALDRS,
825 NDS32_BUILTIN_V_SMALDRS,
826 NDS32_BUILTIN_SMALXDS,
827 NDS32_BUILTIN_V_SMALXDS,
828 NDS32_BUILTIN_SMUL16,
829 NDS32_BUILTIN_V_SMUL16,
830 NDS32_BUILTIN_SMULX16,
831 NDS32_BUILTIN_V_SMULX16,
832 NDS32_BUILTIN_UMUL16,
833 NDS32_BUILTIN_V_UMUL16,
834 NDS32_BUILTIN_UMULX16,
835 NDS32_BUILTIN_V_UMULX16,
836 NDS32_BUILTIN_SMSLDA,
837 NDS32_BUILTIN_V_SMSLDA,
838 NDS32_BUILTIN_SMSLXDA,
839 NDS32_BUILTIN_V_SMSLXDA,
840 NDS32_BUILTIN_UCLIP32,
841 NDS32_BUILTIN_SCLIP32,
842 NDS32_BUILTIN_KABS,
843 NDS32_BUILTIN_UALOAD_U16,
844 NDS32_BUILTIN_UALOAD_S16,
845 NDS32_BUILTIN_UALOAD_U8,
846 NDS32_BUILTIN_UALOAD_S8,
847 NDS32_BUILTIN_UASTORE_U16,
848 NDS32_BUILTIN_UASTORE_S16,
849 NDS32_BUILTIN_UASTORE_U8,
850 NDS32_BUILTIN_UASTORE_S8,
851 NDS32_BUILTIN_DSP_END,
bc8a8810
MC		 852 NDS32_BUILTIN_UNALIGNED_FEATURE,
853 NDS32_BUILTIN_ENABLE_UNALIGNED,
854 NDS32_BUILTIN_DISABLE_UNALIGNED,
7a12ea32 855 NDS32_BUILTIN_COUNT
9304f876
CJW		 856};
857
858/* ------------------------------------------------------------------------ */
859
a4931745
CJW		 860#define TARGET_ISR_VECTOR_SIZE_4_BYTE \
861 (nds32_isr_vector_size == 4)
e2286268 862
a4931745 863#define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2)
e2286268
MC		 864#define TARGET_ISA_V3 \
865 (nds32_arch_option == ARCH_V3 \
37d8f611 866 || nds32_arch_option == ARCH_V3J \
e2286268
MC		 867 || nds32_arch_option == ARCH_V3F \
868 || nds32_arch_option == ARCH_V3S)
9304f876
CJW		 869#define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M)
870
dd000841
CJW		 871#define TARGET_PIPELINE_N7 \
872 (nds32_cpu_option == CPU_N7)
873#define TARGET_PIPELINE_N8 \
874 (nds32_cpu_option == CPU_N6 \
875 || nds32_cpu_option == CPU_N8)
b99353a2
KC		 876#define TARGET_PIPELINE_N9 \
877 (nds32_cpu_option == CPU_N9)
dd000841
CJW		 878#define TARGET_PIPELINE_N10 \
879 (nds32_cpu_option == CPU_N10)
880#define TARGET_PIPELINE_N13 \
881 (nds32_cpu_option == CPU_N12 || nds32_cpu_option == CPU_N13)
882#define TARGET_PIPELINE_GRAYWOLF \
883 (nds32_cpu_option == CPU_GRAYWOLF)
b99353a2
KC		 884#define TARGET_PIPELINE_SIMPLE \
885 (nds32_cpu_option == CPU_SIMPLE)
886
77b7a1ca
CJW		 887#define TARGET_CMODEL_SMALL \
888 (nds32_cmodel_option == CMODEL_SMALL)
889#define TARGET_CMODEL_MEDIUM \
890 (nds32_cmodel_option == CMODEL_MEDIUM)
891#define TARGET_CMODEL_LARGE \
892 (nds32_cmodel_option == CMODEL_LARGE)
893
85a98076
KLC		 894#define TARGET_ICT_MODEL_SMALL \
895 (nds32_ict_model == ICT_MODEL_SMALL)
896
897#define TARGET_ICT_MODEL_LARGE \
898 (nds32_ict_model == ICT_MODEL_LARGE)
899
77b7a1ca
CJW		 900/* When -mcmodel=small or -mcmodel=medium,
901 compiler may generate gp-base instruction directly. */
902#define TARGET_GP_DIRECT \
903 (nds32_cmodel_option == CMODEL_SMALL\
904 || nds32_cmodel_option == CMODEL_MEDIUM)
905
b99353a2
KC		 906#define TARGET_MUL_SLOW \
907 (nds32_mul_config == MUL_TYPE_SLOW)
d4a6a4d9 908
e2286268
MC		 909/* Run-time Target Specification. */
910#define TARGET_SOFT_FLOAT (nds32_abi == NDS32_ABI_V2)
911/* Use hardware floating point calling convention. */
912#define TARGET_HARD_FLOAT (nds32_abi == NDS32_ABI_V2_FP_PLUS)
913
914/* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI,
915 1 means hard ABI and using full floating-point instruction,
916 2 means hard ABI and only using single-precision floating-point
917 instruction */
918#if TARGET_ARCH_DEFAULT == 1
919# define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
920# define TARGET_DEFAULT_FPU_ISA MASK_FPU_DOUBLE | MASK_FPU_SINGLE
921# define TARGET_DEFAULT_FPU_FMA 0
922#else
923# if TARGET_ARCH_DEFAULT == 2
924# define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS
925# define TARGET_DEFAULT_FPU_ISA MASK_FPU_SINGLE
926# define TARGET_DEFAULT_FPU_FMA 0
927# else
928# define TARGET_DEFAULT_ABI NDS32_ABI_V2
929# define TARGET_DEFAULT_FPU_ISA 0
930# define TARGET_DEFAULT_FPU_FMA 0
931# endif
932#endif
933
934#define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2
7c32ef41 935
cf3cd43d
CJW		 936/* ------------------------------------------------------------------------ */
937
938#ifdef TARGET_DEFAULT_RELAX
939# define NDS32_RELAX_SPEC " %{!mno-relax:--relax}"
940#else
941# define NDS32_RELAX_SPEC " %{mrelax:--relax}"
942#endif
943
7c32ef41
MC		 944#ifdef TARGET_DEFAULT_EXT_DSP
945# define NDS32_EXT_DSP_SPEC " %{!mno-ext-dsp:-mext-dsp}"
946#else
947# define NDS32_EXT_DSP_SPEC ""
948#endif
949
9304f876
CJW		 950/* ------------------------------------------------------------------------ */
951\f
952/* Controlling the Compilation Driver. */
953
954#define OPTION_DEFAULT_SPECS \
e2286268
MC		 955 {"arch", " %{!march=*:-march=%(VALUE)}" \
956 " %{march=v3f:%{!mfloat-abi=*:-mfloat-abi=hard}" \
957 " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}" \
958 " %{!mno-ext-fpu-dp:%{!mext-fpu-dp:-mext-fpu-dp}}}" \
959 " %{march=v3s:%{!mfloat-abi=*:-mfloat-abi=hard}" \
960 " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}}" }, \
b99353a2 961 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
e2286268 962 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }
9304f876
CJW		 963
964#define CC1_SPEC \
7c32ef41 965 NDS32_EXT_DSP_SPEC
9304f876
CJW		 966
967#define ASM_SPEC \
e2286268
MC		 968 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
969 " %{march=*:-march=%*}" \
8aa27a4c
CJW		 970 " %{mno-16-bit|mno-16bit:-mno-16bit-ext}" \
971 " %{march=v3m:%{!mfull-regs:%{!mreduced-regs:-mreduced-regs}}}" \
972 " %{mfull-regs:-mno-reduced-regs}" \
973 " %{mreduced-regs:-mreduced-regs}" \
e2286268
MC		 974 " %{mabi=*:-mabi=v%*}" \
975 " %{mconfig-fpu=*:-mfpu-freg=%*}" \
976 " %{mext-fpu-mac:-mmac}" \
977 " %{mno-ext-fpu-mac:-mno-mac}" \
978 " %{mext-fpu-sp:-mfpu-sp-ext}" \
979 " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \
980 " %{mext-fpu-dp:-mfpu-dp-ext}" \
7c32ef41 981 " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}" \
8aa27a4c
CJW		 982 " %{mext-dsp:-mdsp-ext}" \
983 " %{O|O1|O2|O3|Ofast:-O1;:-Os}"
9304f876 984
c9eb51a7
CJW		 985/* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
986 configure gcc with --target=nds32be-* setting.
987 Check gcc/config.gcc for more information. */
9304f876 988#ifdef TARGET_BIG_ENDIAN_DEFAULT
c9eb51a7 989# define NDS32_ENDIAN_DEFAULT "mbig-endian"
9304f876 990#else
c9eb51a7 991# define NDS32_ENDIAN_DEFAULT "mlittle-endian"
9304f876
CJW		 992#endif
993
cf3cd43d
CJW		 994#if TARGET_ELF
995# define NDS32_CMODEL_DEFAULT "mcmodel=medium"
996#else
997# define NDS32_CMODEL_DEFAULT "mcmodel=large"
998#endif
c9eb51a7
CJW		 999
1000#define MULTILIB_DEFAULTS \
1001 { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
1002
9304f876
CJW		 1003\f
1004/* Run-time Target Specification. */
1005
72b7e5e1
KC		 1006#define TARGET_CPU_CPP_BUILTINS() \
1007 nds32_cpu_cpp_builtins (pfile)
9304f876
CJW		 1008
1009\f
1010/* Defining Data Structures for Per-function Information. */
1011
1012/* This macro is called once per function,
1013 before generation of any RTL has begun. */
1014#define INIT_EXPANDERS nds32_init_expanders ()
1015
1016\f
1017/* Storage Layout. */
1018
1019#define BITS_BIG_ENDIAN 0
1020
1021#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
1022
1023#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
1024
1025#define UNITS_PER_WORD 4
1026
1027#define PROMOTE_MODE(m, unsignedp, type) \
1028 if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
1029 { \
1030 (m) = SImode; \
1031 }
1032
1033#define PARM_BOUNDARY 32
1034
1035#define STACK_BOUNDARY 64
1036
43fa41c1
CJW		 1037#define FUNCTION_BOUNDARY \
1038 ((NDS32_ALIGN_P () || TARGET_ALIGN_FUNCTION) ? 32 : 16)
9304f876
CJW		 1039
1040#define BIGGEST_ALIGNMENT 64
1041
79498ad8
CJW		 1042#define DATA_ALIGNMENT(constant, basic_align) \
1043 nds32_data_alignment (constant, basic_align)
1044
1045#define LOCAL_ALIGNMENT(type, basic_align) \
1046 nds32_local_alignment (type, basic_align)
1047
9304f876
CJW		 1048#define EMPTY_FIELD_BOUNDARY 32
1049
1050#define STRUCTURE_SIZE_BOUNDARY 8
1051
1052#define STRICT_ALIGNMENT 1
1053
1054#define PCC_BITFIELD_TYPE_MATTERS 1
1055
1056\f
1057/* Layout of Source Language Data Types. */
1058
1059#define INT_TYPE_SIZE 32
1060#define SHORT_TYPE_SIZE 16
1061#define LONG_TYPE_SIZE 32
1062#define LONG_LONG_TYPE_SIZE 64
1063
1064#define FLOAT_TYPE_SIZE 32
1065#define DOUBLE_TYPE_SIZE 64
1066#define LONG_DOUBLE_TYPE_SIZE 64
1067
1068#define DEFAULT_SIGNED_CHAR 1
1069
1070#define SIZE_TYPE "long unsigned int"
1071#define PTRDIFF_TYPE "long int"
7f983342
CJW		 1072#define WCHAR_TYPE "unsigned int"
1073#define WCHAR_TYPE_SIZE 32
9304f876
CJW		 1074
1075\f
1076/* Register Usage. */
1077
1078/* Number of actual hardware registers.
1079 The hardware registers are assigned numbers for the compiler
1080 from 0 to just below FIRST_PSEUDO_REGISTER.
1081 All registers that the compiler knows about must be given numbers,
1082 even those that are not normally considered general registers. */
71d8eff1 1083#define FIRST_PSEUDO_REGISTER 101
9304f876
CJW		 1084
1085/* An initializer that says which registers are used for fixed
1086 purposes all throughout the compiled code and are therefore
1087 not available for general allocation.
1088
1089 $r28 : $fp
1090 $r29 : $gp
1091 $r30 : $lp
1092 $r31 : $sp
1093
e2286268
MC		 1094 caller-save registers: $r0 ~ $r5, $r16 ~ $r23, $fs0 ~ $fs5, $fs22 ~ $fs47
1095 callee-save registers: $r6 ~ $r10, $r11 ~ $r14, $fs6 ~ $fs21, $fs48 ~ $fs63
9304f876
CJW		 1096
1097 reserved for assembler : $r15
1098 reserved for other use : $r24, $r25, $r26, $r27 */
71d8eff1
CJW		 1099#define FIXED_REGISTERS \
1100{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
1101 0, 0, 0, 0, 0, 0, 0, 0, \
1102 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
1103 0, 0, 0, 0, 0, 0, 0, 1, \
1104 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
1105 0, 0, 0, 0, 0, 0, 0, 0, \
1106 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
1107 1, 1, 1, 1, 0, 1, 0, 1, \
e2286268 1108 /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \
71d8eff1 1109 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1110 /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \
71d8eff1 1111 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1112 /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
71d8eff1 1113 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1114 /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
71d8eff1 1115 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1116 /* fs30 fs31 fd16 fd17 fd18 */ \
71d8eff1 1117 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1118 /* fd19 fd20 fd21 fd22 */ \
71d8eff1 1119 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1120 /* fd23 fd24 fd25 fd26 */ \
71d8eff1 1121 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1122 /* fd27 fd28 fd29 fd30 */ \
71d8eff1 1123 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1124 /* fd31 Reserved..................... */ \
71d8eff1 1125 1, 1, 1, 1, 1 \
9304f876
CJW		 1126}
1127
1128/* Identifies the registers that are not available for
1129 general allocation of values that must live across
1130 function calls -- so they are caller-save registers.
1131
1132 0 : callee-save registers
1133 1 : caller-save registers */
71d8eff1
CJW		 1134#define CALL_USED_REGISTERS \
1135{ /* r0 r1 r2 r3 r4 r5 r6 r7 */ \
1136 1, 1, 1, 1, 1, 1, 0, 0, \
1137 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \
1138 0, 0, 0, 0, 0, 0, 0, 1, \
1139 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
1140 1, 1, 1, 1, 1, 1, 1, 1, \
1141 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
1142 1, 1, 1, 1, 0, 1, 0, 1, \
e2286268 1143 /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \
71d8eff1 1144 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1145 /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \
71d8eff1 1146 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1147 /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \
71d8eff1 1148 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1149 /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \
71d8eff1 1150 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1151 /* fs30 fs31 fd16 fd17 fd18 */ \
71d8eff1 1152 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1153 /* fd19 fd20 fd21 fd22 */ \
71d8eff1 1154 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1155 /* fd23 fd24 fd25 fd26 */ \
71d8eff1 1156 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1157 /* fd27 fd28 fd29 fd30 */ \
71d8eff1 1158 1, 1, 1, 1, 1, 1, 1, 1, \
e2286268 1159 /* fd31 Reserved..................... */ \
71d8eff1 1160 1, 1, 1, 1, 1 \
9304f876
CJW		 1161}
1162
1163/* In nds32 target, we have three levels of registers:
1164 LOW_COST_REGS : $r0 ~ $r7
1165 MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
1166 HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */
71d8eff1
CJW		 1167#define REG_ALLOC_ORDER \
1168{ 0, 1, 2, 3, 4, 5, 6, 7, \
1169 16, 17, 18, 19, 9, 10, 11, 12, \
1170 13, 14, 8, 15, 20, 21, 22, 23, \
1171 24, 25, 26, 27, 28, 29, 30, 31, \
1172 32, 33, 34, 35, 36, 37, 38, 39, \
1173 40, 41, 42, 43, 44, 45, 46, 47, \
1174 48, 49, 50, 51, 52, 53, 54, 55, \
1175 56, 57, 58, 59, 60, 61, 62, 63, \
1176 64, 65, 66, 67, 68, 69, 70, 71, \
1177 72, 73, 74, 75, 76, 77, 78, 79, \
1178 80, 81, 82, 83, 84, 85, 86, 87, \
1179 88, 89, 90, 91, 92, 93, 94, 95, \
1180 96, 97, 98, 99, 100, \
9304f876
CJW		 1181}
1182
5e6ae0cc
CJW		 1183/* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1184 to be rearranged based on optimizing for speed or size. */
1185#define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order ()
1186
9304f876
CJW		 1187/* Tell IRA to use the order we define rather than messing it up with its
1188 own cost calculations. */
96092404 1189#define HONOR_REG_ALLOC_ORDER optimize_size
9304f876 1190
9304f876
CJW		 1191\f
1192/* Register Classes. */
1193
1194/* In nds32 target, we have three levels of registers:
1195 Low cost regsiters : $r0 ~ $r7
1196 Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
1197 High cost registers : $r12 ~ $r14, $r20 ~ $r31
1198
1199 In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
1200 so that it provides more chance to use low cost registers. */
1201enum reg_class
1202{
1203 NO_REGS,
36f28760
CJW		 1204 R5_REG,
1205 R8_REG,
9304f876
CJW		 1206 R15_TA_REG,
1207 STACK_REG,
36f28760 1208 FRAME_POINTER_REG,
9304f876
CJW		 1209 LOW_REGS,
1210 MIDDLE_REGS,
1211 HIGH_REGS,
1212 GENERAL_REGS,
1213 FRAME_REGS,
e2286268 1214 FP_REGS,
9304f876
CJW		 1215 ALL_REGS,
1216 LIM_REG_CLASSES
1217};
1218
1219#define N_REG_CLASSES (int) LIM_REG_CLASSES
1220
1221#define REG_CLASS_NAMES \
1222{ \
1223 "NO_REGS", \
36f28760
CJW		 1224 "R5_REG", \
1225 "R8_REG", \
9304f876
CJW		 1226 "R15_TA_REG", \
1227 "STACK_REG", \
36f28760 1228 "FRAME_POINTER_REG", \
9304f876
CJW		 1229 "LOW_REGS", \
1230 "MIDDLE_REGS", \
1231 "HIGH_REGS", \
1232 "GENERAL_REGS", \
1233 "FRAME_REGS", \
e2286268 1234 "FP_REGS", \
9304f876
CJW		 1235 "ALL_REGS" \
1236}
1237
1238#define REG_CLASS_CONTENTS \
71d8eff1
CJW		 1239{ /* NO_REGS */ \
1240 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \
1241 /* R5_REG : 5 */ \
1242 {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \
1243 /* R8_REG : 8 */ \
1244 {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \
1245 /* R15_TA_REG : 15 */ \
1246 {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \
1247 /* STACK_REG : 31 */ \
1248 {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \
1249 /* FRAME_POINTER_REG : 28 */ \
1250 {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \
1251 /* LOW_REGS : 0-7 */ \
1252 {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \
1253 /* MIDDLE_REGS : 0-11, 16-19 */ \
1254 {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \
1255 /* HIGH_REGS : 12-14, 20-31 */ \
1256 {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \
1257 /* GENERAL_REGS : 0-31 */ \
1258 {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \
1259 /* FRAME_REGS : 32, 33 */ \
1260 {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \
e2286268
MC		 1261 /* FP_REGS : 34-98 */ \
1262 {0x00000000, 0xfffffffc, 0xffffffff, 0x00000003}, \
71d8eff1
CJW		 1263 /* ALL_REGS : 0-100 */ \
1264 {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f} \
9304f876
CJW		 1265}
1266
1267#define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
1268
1269#define BASE_REG_CLASS GENERAL_REGS
1270#define INDEX_REG_CLASS GENERAL_REGS
1271
e2286268
MC		 1272#define TEST_REGNO(R, TEST, VALUE) \
1273 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1274
9304f876
CJW		 1275/* Return nonzero if it is suitable for use as a
1276 base register in operand addresses.
1277 So far, we return nonzero only if "num" is a hard reg
1278 of the suitable class or a pseudo register which is
1279 allocated to a suitable hard reg. */
1280#define REGNO_OK_FOR_BASE_P(num) \
e2286268
MC		 1281 (TEST_REGNO (num, <, 32) \
1282 || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
1283 || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
9304f876
CJW		 1284
1285/* Return nonzero if it is suitable for use as a
1286 index register in operand addresses.
1287 So far, we return nonzero only if "num" is a hard reg
1288 of the suitable class or a pseudo register which is
1289 allocated to a suitable hard reg.
1290 The difference between an index register and a base register is that
1291 the index register may be scaled. */
1292#define REGNO_OK_FOR_INDEX_P(num) \
e2286268
MC		 1293 (TEST_REGNO (num, <, 32) \
1294 || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \
1295 || TEST_REGNO (num, ==, ARG_POINTER_REGNUM))
9304f876
CJW		 1296
1297\f
1298/* Obsolete Macros for Defining Constraints. */
1299
1300\f
1301/* Stack Layout and Calling Conventions. */
1302
62f9f30b 1303#define STACK_GROWS_DOWNWARD 1
9304f876
CJW		 1304
1305#define FRAME_GROWS_DOWNWARD 1
1306
9304f876
CJW		 1307#define STACK_POINTER_OFFSET 0
1308
4f44e960
CJW		 1309#define FIRST_PARM_OFFSET(fundecl) \
1310 (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
9304f876 1311
ca3a4a55
CJW		 1312/* A C expression whose value is RTL representing the address in a stack frame
1313 where the pointer to the caller's frame is stored. */
1314#define DYNAMIC_CHAIN_ADDRESS(frameaddr) \
1315 nds32_dynamic_chain_address (frameaddr)
1316
9304f876
CJW		 1317#define RETURN_ADDR_RTX(count, frameaddr) \
1318 nds32_return_addr_rtx (count, frameaddr)
1319
1320/* A C expression whose value is RTL representing the location
1321 of the incoming return address at the beginning of any function
1322 before the prologue.
1323 If this RTL is REG, you should also define
1324 DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO). */
1325#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM)
1326#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM)
1327
ca3a4a55
CJW		 1328/* Use $r0 $r1 to pass exception handling information. */
1329#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) : INVALID_REGNUM)
1330/* The register $r2 that represents a location in which to store a stack
1331 adjustment to be applied before function return.
1332 This is used to unwind the stack to an exception handler's call frame. */
1333#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2)
1334
ca60bd93 1335#define DEBUGGER_REGNO(REGNO) nds32_debugger_regno (REGNO)
e2286268 1336
9304f876
CJW		 1337#define STACK_POINTER_REGNUM SP_REGNUM
1338
1339#define FRAME_POINTER_REGNUM 33
1340
1341#define HARD_FRAME_POINTER_REGNUM FP_REGNUM
1342
1343#define ARG_POINTER_REGNUM 32
1344
1345#define STATIC_CHAIN_REGNUM 16
1346
1347#define ELIMINABLE_REGS \
1348{ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1349 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \
1350 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
1351 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
1352
1353#define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
1354 (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
1355
1356#define ACCUMULATE_OUTGOING_ARGS 1
1357
1358#define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
1359
1360#define CUMULATIVE_ARGS nds32_cumulative_args
1361
1362#define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
1363 nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
1364
e2286268
MC		 1365#define FUNCTION_ARG_REGNO_P(regno) \
1366 (IN_RANGE ((regno), NDS32_FIRST_GPR_REGNUM, NDS32_MAX_GPR_REGS_FOR_ARGS - 1) \
1367 || ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) \
1368 && IN_RANGE ((regno), NDS32_FPR_ARG_FIRST_REGNUM, \
1369 NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS - 1)))
9304f876
CJW		 1370
1371#define DEFAULT_PCC_STRUCT_RETURN 0
1372
1373/* EXIT_IGNORE_STACK should be nonzero if, when returning
1374 from a function, the stack pointer does not matter.
1375 The value is tested only in functions that have frame pointers.
1376 In nds32 target, the function epilogue recovers the
1377 stack pointer from the frame. */
1378#define EXIT_IGNORE_STACK 1
1379
1380#define FUNCTION_PROFILER(file, labelno) \
9e362bd0
CJW		 1381 fprintf (file, "/* profiler %d */\n", (labelno))
1382
1383#define PROFILE_HOOK(LABEL) \
1384 { \
1385 rtx fun, lp; \
1386 lp = get_hard_reg_initial_val (Pmode, LP_REGNUM); \
1387 fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \
1388 emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode); \
1389 }
9304f876
CJW		 1390
1391\f
1392/* Implementing the Varargs Macros. */
1393
1394\f
1395/* Trampolines for Nested Functions. */
1396
1397/* Giving A-function and B-function,
1398 if B-function wants to call A-function's nested function,
1399 we need to fill trampoline code into A-function's stack
1400 so that B-function can execute the code in stack to indirectly
1401 jump to (like 'trampoline' action) desired nested function.
1402
1403 The trampoline code for nds32 target must contains following parts:
1404
1405 1. instructions (4 * 4 = 16 bytes):
8a498f99
CJW		 1406 get $pc first
1407 load chain_value to static chain register via $pc
1408 load nested function address to $r15 via $pc
1409 jump to desired nested function via $r15
9304f876 1410 2. data (4 * 2 = 8 bytes):
8a498f99
CJW		 1411 chain_value
1412 nested function address
9304f876 1413
e53b6e56 1414 Please check nds32.cc implementation for more information. */
9304f876
CJW		 1415#define TRAMPOLINE_SIZE 24
1416
1417/* Because all instructions/data in trampoline template are 4-byte size,
1418 we set trampoline alignment 8*4=32 bits. */
1419#define TRAMPOLINE_ALIGNMENT 32
1420
1421\f
1422/* Implicit Calls to Library Routines. */
1423
1424\f
1425/* Addressing Modes. */
1426
1427/* We can use "LWI.bi Rt, [Ra], 4" to support post increment. */
1428#define HAVE_POST_INCREMENT 1
1429/* We can use "LWI.bi Rt, [Ra], -4" to support post decrement. */
1430#define HAVE_POST_DECREMENT 1
1431
1432/* We have "LWI.bi Rt, [Ra], imm" instruction form. */
1433#define HAVE_POST_MODIFY_DISP 1
1434/* We have "LW.bi Rt, [Ra], Rb" instruction form. */
1435#define HAVE_POST_MODIFY_REG 1
1436
c411e9aa
SC		 1437#define USE_LOAD_POST_INCREMENT(mode) \
1438 nds32_use_load_post_increment(mode)
1439#define USE_LOAD_POST_DECREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1440#define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
1441#define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
1442
9304f876
CJW		 1443#define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
1444
566f31a4 1445#define MAX_REGS_PER_ADDRESS 3
9304f876
CJW		 1446
1447\f
1448/* Anchored Addresses. */
1449
1450\f
1451/* Condition Code Status. */
1452
1453\f
1454/* Describing Relative Costs of Operations. */
1455
1456/* A C expression for the cost of a branch instruction.
1457 A value of 1 is the default;
1458 other values are interpreted relative to that. */
15c193e2 1459#define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1)
9304f876 1460
08ed6d29
CJW		 1461/* Override BRANCH_COST heuristic which empirically produces worse
1462 performance for removing short circuiting from the logical ops. */
1463#define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1464
9304f876
CJW		 1465#define SLOW_BYTE_ACCESS 1
1466
1e8552c2 1467#define NO_FUNCTION_CSE 1
9304f876
CJW		 1468
1469\f
1470/* Adjusting the Instruction Scheduler. */
1471
1472\f
1473/* Dividing the Output into Sections (Texts, Data, . . . ). */
1474
1475#define TEXT_SECTION_ASM_OP "\t.text"
1476#define DATA_SECTION_ASM_OP "\t.data"
1477
1478/* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
1479 So we use '.section .bss' alternatively. */
1480#define BSS_SECTION_ASM_OP "\t.section\t.bss"
1481
1482/* Define this macro to be an expression with a nonzero value if jump tables
1483 (for tablejump insns) should be output in the text section,
1484 along with the assembler instructions.
1485 Otherwise, the readonly data section is used. */
1486#define JUMP_TABLES_IN_TEXT_SECTION 1
1487
1488\f
1489/* Position Independent Code. */
1490
64a08b7f
CJW		 1491#define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
1492
85a98076
KLC		 1493#define SYMBOLIC_CONST_P(X) \
1494(GET_CODE (X) == SYMBOL_REF \
1495 || GET_CODE (X) == LABEL_REF \
1496 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
1497
9304f876
CJW		 1498\f
1499/* Defining the Output Assembler Language. */
1500
1501#define ASM_COMMENT_START "!"
1502
c77562ca 1503#define ASM_APP_ON "! #APP\n"
9304f876
CJW		 1504
1505#define ASM_APP_OFF "! #NO_APP\n"
1506
1507#define ASM_OUTPUT_LABELREF(stream, name) \
1508 asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
1509
1510#define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
1511 assemble_name (stream, XSTR (sym, 0))
1512
1513#define ASM_OUTPUT_LABEL_REF(stream, buf) \
1514 assemble_name (stream, buf)
1515
1516#define LOCAL_LABEL_PREFIX "."
1517
71d8eff1
CJW		 1518#define REGISTER_NAMES \
1519{ "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \
9304f876
CJW		 1520 "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \
1521 "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
1522 "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \
e2286268
MC		 1523 "$AP", "$SFP", "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", \
1524 "$fs6", "$fs7", "$fs8", "$fs9", "$fs10","$fs11","$fs12","$fs13",\
1525 "$fs14","$fs15","$fs16","$fs17","$fs18","$fs19","$fs20","$fs21",\
1526 "$fs22","$fs23","$fs24","$fs25","$fs26","$fs27","$fs28","$fs29",\
1527 "$fs30","$fs31","$fs32","$fs33","$fs34","$fs35","$fs36","$fs37",\
1528 "$fs38","$fs39","$fs40","$fs41","$fs42","$fs43","$fs44","$fs45",\
1529 "$fs46","$fs47","$fs48","$fs49","$fs50","$fs51","$fs52","$fs53",\
1530 "$fs54","$fs55","$fs56","$fs57","$fs58","$fs59","$fs60","$fs61",\
1531 "$fs62","$fs63", "LB", "LE", "LC" \
1532}
1533
1534#define ADDITIONAL_REGISTER_NAMES \
1535{ \
1536 {"$r15", 15}, \
1537 {"$r28", 28}, {"$r29", 29}, {"$r30", 30}, {"$r31", 31}, \
1538 {"$a0", 0}, {"$a1", 1}, {"$a2", 2}, \
1539 {"$a3", 3}, {"$a4", 4}, {"$a5", 5}, \
1540 {"$s0", 6}, {"$s1", 7}, {"$s2", 8}, {"$s3", 9}, \
1541 {"$s4", 10}, {"$s5", 11}, {"$s6", 12}, {"$s7", 13}, \
1542 {"$s8", 14}, \
1543 {"$t0", 16}, {"$t1", 17}, {"$t2", 18}, {"$t3", 19}, \
1544 {"$t4", 20}, {"$t5", 21}, {"$t6", 22}, {"$t7", 23}, \
1545 {"$t8", 24}, {"$t9", 25}, \
1546 {"$p0", 26}, {"$p1", 27}, \
1547 {"$h0", 0}, {"$h1", 1}, {"$h2", 2}, {"$h3", 3}, \
1548 {"$h4", 4}, {"$h5", 5}, {"$h6", 6}, {"$h7", 7}, \
1549 {"$h8", 8}, {"$h9", 9}, {"$h10", 10}, {"$h11", 11}, \
1550 {"$h12", 16}, {"$h13", 17}, {"$h14", 18}, {"$h15", 19}, \
1551 {"$o0", 0}, {"$o1", 1}, {"$o2", 2}, {"$o3", 3}, \
1552 {"$o4", 4}, {"$o5", 5}, {"$o6", 6}, {"$o7", 7}, \
1553}
1554
1555#define OVERLAPPING_REGISTER_NAMES \
1556{ \
1557 {"$fd0", NDS32_FIRST_FPR_REGNUM + 0, 2}, \
1558 {"$fd1", NDS32_FIRST_FPR_REGNUM + 2, 2}, \
1559 {"$fd2", NDS32_FIRST_FPR_REGNUM + 4, 2}, \
1560 {"$fd3", NDS32_FIRST_FPR_REGNUM + 6, 2}, \
1561 {"$fd4", NDS32_FIRST_FPR_REGNUM + 8, 2}, \
1562 {"$fd5", NDS32_FIRST_FPR_REGNUM + 10, 2}, \
1563 {"$fd6", NDS32_FIRST_FPR_REGNUM + 12, 2}, \
1564 {"$fd7", NDS32_FIRST_FPR_REGNUM + 14, 2}, \
1565 {"$fd8", NDS32_FIRST_FPR_REGNUM + 16, 2}, \
1566 {"$fd9", NDS32_FIRST_FPR_REGNUM + 18, 2}, \
1567 {"$fd10", NDS32_FIRST_FPR_REGNUM + 20, 2}, \
1568 {"$fd11", NDS32_FIRST_FPR_REGNUM + 22, 2}, \
1569 {"$fd12", NDS32_FIRST_FPR_REGNUM + 24, 2}, \
1570 {"$fd13", NDS32_FIRST_FPR_REGNUM + 26, 2}, \
1571 {"$fd14", NDS32_FIRST_FPR_REGNUM + 28, 2}, \
1572 {"$fd15", NDS32_FIRST_FPR_REGNUM + 30, 2}, \
1573 {"$fd16", NDS32_FIRST_FPR_REGNUM + 32, 2}, \
1574 {"$fd17", NDS32_FIRST_FPR_REGNUM + 34, 2}, \
1575 {"$fd18", NDS32_FIRST_FPR_REGNUM + 36, 2}, \
1576 {"$fd19", NDS32_FIRST_FPR_REGNUM + 38, 2}, \
1577 {"$fd20", NDS32_FIRST_FPR_REGNUM + 40, 2}, \
1578 {"$fd21", NDS32_FIRST_FPR_REGNUM + 42, 2}, \
1579 {"$fd22", NDS32_FIRST_FPR_REGNUM + 44, 2}, \
1580 {"$fd23", NDS32_FIRST_FPR_REGNUM + 46, 2}, \
1581 {"$fd24", NDS32_FIRST_FPR_REGNUM + 48, 2}, \
1582 {"$fd25", NDS32_FIRST_FPR_REGNUM + 50, 2}, \
1583 {"$fd26", NDS32_FIRST_FPR_REGNUM + 52, 2}, \
1584 {"$fd27", NDS32_FIRST_FPR_REGNUM + 54, 2}, \
1585 {"$fd28", NDS32_FIRST_FPR_REGNUM + 56, 2}, \
1586 {"$fd29", NDS32_FIRST_FPR_REGNUM + 58, 2}, \
1587 {"$fd30", NDS32_FIRST_FPR_REGNUM + 60, 2}, \
1588 {"$fd31", NDS32_FIRST_FPR_REGNUM + 62, 2}, \
9304f876
CJW		 1589}
1590
1591/* Output normal jump table entry. */
1592#define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
1593 asm_fprintf (stream, "\t.word\t%LL%d\n", value)
1594
1595/* Output pc relative jump table entry. */
1596#define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel) \
1597 do \
1598 { \
1599 switch (GET_MODE (body)) \
1600 { \
4e10a5a7 1601 case E_QImode: \
9304f876
CJW		 1602 asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \
1603 break; \
4e10a5a7 1604 case E_HImode: \
9304f876
CJW		 1605 asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \
1606 break; \
4e10a5a7 1607 case E_SImode: \
9304f876
CJW		 1608 asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \
1609 break; \
1610 default: \
1611 gcc_unreachable(); \
1612 } \
1613 } while (0)
1614
1615/* We have to undef it first because elfos.h formerly define it
1616 check gcc/config.gcc and gcc/config/elfos.h for more information. */
1617#undef ASM_OUTPUT_CASE_LABEL
1618#define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table) \
1619 do \
1620 { \
1621 asm_fprintf (stream, "\t! Jump Table Begin\n"); \
1622 (*targetm.asm_out.internal_label) (stream, prefix, num); \
1623 } while (0)
1624
1625#define ASM_OUTPUT_CASE_END(stream, num, table) \
1626 do \
1627 { \
1628 /* Because our jump table is in text section, \
8a498f99
CJW		 1629 we need to make sure 2-byte alignment after \
1630 the jump table for instructions fetch. */ \
9304f876 1631 if (GET_MODE (PATTERN (table)) == QImode) \
8a498f99 1632 ASM_OUTPUT_ALIGN (stream, 1); \
9304f876
CJW		 1633 asm_fprintf (stream, "\t! Jump Table End\n"); \
1634 } while (0)
1635
1636/* This macro is not documented yet.
1637 But we do need it to make jump table vector aligned. */
1638#define ADDR_VEC_ALIGN(JUMPTABLE) 2
1639
1640#define DWARF2_UNWIND_INFO 1
1641
1642#define JUMP_ALIGN(x) \
e6de5335
ML		 1643 (align_jumps.levels[0].log \
1644 ? align_jumps : align_flags (nds32_target_alignment (x)))
9304f876
CJW		 1645
1646#define LOOP_ALIGN(x) \
e6de5335
ML		 1647 (align_loops.levels[0].log \
1648 ? align_loops : align_flags (nds32_target_alignment (x)))
9304f876
CJW		 1649
1650#define LABEL_ALIGN(x) \
e6de5335
ML		 1651 (align_labels.levels[0].log \
1652 ? align_labels : align_flags (nds32_target_alignment (x)))
9304f876
CJW		 1653
1654#define ASM_OUTPUT_ALIGN(stream, power) \
1655 fprintf (stream, "\t.align\t%d\n", power)
1656
1657\f
1658/* Controlling Debugging Information Format. */
1659
1660#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1661
1662#define DWARF2_DEBUGGING_INFO 1
1663
1664#define DWARF2_ASM_LINE_DEBUG_INFO 1
1665
1666\f
1667/* Cross Compilation and Floating Point. */
1668
1669\f
1670/* Mode Switching Instructions. */
1671
1672\f
1673/* Defining target-specific uses of __attribute__. */
1674
1675\f
1676/* Emulating TLS. */
1677
1678\f
1679/* Defining coprocessor specifics for MIPS targets. */
1680
1681\f
1682/* Parameters for Precompiled Header Validity Checking. */
1683
1684\f
1685/* C++ ABI parameters. */
1686
1687\f
1688/* Adding support for named address spaces. */
1689
1690\f
1691/* Miscellaneous Parameters. */
1692
1693/* This is the machine mode that elements of a jump-table should have. */
1694#define CASE_VECTOR_MODE Pmode
1695
1696/* Return the preferred mode for and addr_diff_vec when the mininum
1697 and maximum offset are known. */
1698#define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \
2f1bb3ca 1699 nds32_case_vector_shorten_mode (min_offset, max_offset, body)
9304f876
CJW		 1700
1701/* Generate pc relative jump table when -fpic or -Os. */
1702#define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
1703
1704/* Define this macro if operations between registers with integral mode
1705 smaller than a word are always performed on the entire register. */
9e11bfef 1706#define WORD_REGISTER_OPERATIONS 1
9304f876
CJW		 1707
1708/* A C expression indicating when insns that read memory in mem_mode,
1709 an integral mode narrower than a word, set the bits outside of mem_mode
1710 to be either the sign-extension or the zero-extension of the data read. */
1711#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1712
1713/* The maximum number of bytes that a single instruction can move quickly
1714 between memory and registers or between two memory locations. */
1715#define MOVE_MAX 4
1716
1717/* A C expression that is nonzero if on this machine the number of bits
1718 actually used for the count of a shift operation is equal to the number
1719 of bits needed to represent the size of the object being shifted. */
1720#define SHIFT_COUNT_TRUNCATED 1
1721
9304f876
CJW		 1722/* A C expression describing the value returned by a comparison operator with
1723 an integral mode and stored by a store-flag instruction ('cstoremode4')
1724 when the condition is true. */
1725#define STORE_FLAG_VALUE 1
1726
24a71166
CJW		 1727/* A C expression that indicates whether the architecture defines a value for
1728 clz or ctz with a zero operand. In nds32 clz for 0 result 32 is defined
1729 in ISA spec */
1730#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
1731
9304f876
CJW		 1732/* An alias for the machine mode for pointers. */
1733#define Pmode SImode
1734
1735/* An alias for the machine mode used for memory references to functions
1736 being called, in call RTL expressions. */
1737#define FUNCTION_MODE SImode
1738
1739/* ------------------------------------------------------------------------ */
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