projects / thirdparty / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| 3965b35f SH |
1 | ;; Predicate definitions for OpenRISC |
| 2 | ;; Copyright (C) 2018 Free Software Foundation, Inc. | |
| 3 | ;; Contributed by Stafford Horne | |
| 4 | ||
| 5 | ;; This file is part of GCC. | |
| 6 | ||
| 7 | ;; GCC is free software; you can redistribute it and/or modify it | |
| 8 | ;; under the terms of the GNU General Public License as published | |
| 9 | ;; by the Free Software Foundation; either version 3, or (at your | |
| 10 | ;; option) any later version. | |
| 11 | ||
| 12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT | |
| 13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
| 14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
| 15 | ;; License for more details. | |
| 16 | ||
| 17 | ;; You should have received a copy of the GNU General Public License | |
| 18 | ;; along with GCC; see the file COPYING3. If not see | |
| 19 | ;; <http://www.gnu.org/licenses/>. | |
| 20 | ||
| 21 | ;; ------------------------------------------------------------------------- | |
| 22 | ;; Predicates | |
| 23 | ;; ------------------------------------------------------------------------- | |
| 24 | ||
| 25 | (define_predicate "input_operand" | |
| 26 | (ior (match_operand 0 "register_operand") | |
| 27 | (match_operand 0 "memory_operand") | |
| 28 | (and (match_code "const_int") | |
| 29 | (match_test "satisfies_constraint_I (op) | |
| 30 | || satisfies_constraint_K (op) | |
| 31 | || satisfies_constraint_M (op)")))) | |
| 32 | ||
| 33 | (define_predicate "const0_operand" | |
| 34 | (and (match_code "const_int,const_wide_int,const_double,const_vector") | |
| 35 | (match_test "op == CONST0_RTX (mode)"))) | |
| 36 | ||
| 37 | (define_predicate "reg_or_0_operand" | |
| 38 | (ior (match_operand 0 "register_operand") | |
| 39 | (match_operand 0 "const0_operand"))) | |
| 40 | ||
| 41 | (define_predicate "reg_or_u6_operand" | |
| 42 | (if_then_else (match_code "const_int") | |
| 43 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 0x3f") | |
| 44 | (match_operand 0 "register_operand"))) | |
| 45 | ||
| 46 | (define_predicate "reg_or_u16_operand" | |
| 47 | (if_then_else (match_code "const_int") | |
| 48 | (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 0xffff") | |
| 49 | (match_operand 0 "register_operand"))) | |
| 50 | ||
| 51 | (define_predicate "reg_or_s16_operand" | |
| 52 | (if_then_else (match_code "const_int") | |
| 53 | (match_test "INTVAL (op) >= -32768 && INTVAL (op) <= 32767") | |
| 54 | (match_operand 0 "register_operand"))) | |
| 55 | ||
| 56 | (define_predicate "call_insn_operand" | |
| 57 | (ior (match_code "symbol_ref") | |
| 58 | (match_operand 0 "register_operand"))) | |
| 59 | ||
| 60 | (define_predicate "high_operand" | |
| 61 | (match_code "symbol_ref,label_ref,const,unspec")) | |
| 62 | ||
| 63 | ;; Return true for relocations that must use MOVHI+ADDI | |
| 64 | (define_predicate "losum_add_operand" | |
| 65 | (match_code "symbol_ref,label_ref,const,unspec")) | |
| 66 | ||
| 67 | ;; Return true for relocations that must use MOVHI+ORI | |
| 68 | (define_predicate "losum_ior_operand" | |
| 69 | (and (match_code "unspec") | |
| 70 | (match_test "XINT(op, 1) == UNSPEC_TLSGD"))) | |
| 71 | ||
| 72 | ;; Return true for a "virtual" or "soft" register that will be | |
| 73 | ;; adjusted to a "soft" or "hard" register during elimination. | |
| 74 | (define_predicate "virtual_frame_reg_operand" | |
| 75 | (match_code "reg") | |
| 76 | { | |
| 77 | unsigned regno = REGNO (op); | |
| 78 | return (regno != STACK_POINTER_REGNUM | |
| 79 | && regno != HARD_FRAME_POINTER_REGNUM | |
| 80 | && REGNO_PTR_FRAME_P (regno)); | |
| 81 | }) | |
| 82 | ||
| 83 | (define_predicate "equality_comparison_operator" | |
| 84 | (match_code "ne,eq")) |