[thirdparty/gcc.git] / gcc / config / pa / pa32-regs.h

/* Copyright (C) 2000-2021 Free Software Foundation, Inc.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.

GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
for more details.

Under Section 7 of GPL version 3, you are granted additional
permissions described in the GCC Runtime Library Exception, version
3.1, as published by the Free Software Foundation.

You should have received a copy of the GNU General Public License and
a copy of the GCC Runtime Library Exception along with this program;
see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
<http://www.gnu.org/licenses/>.  */

/* Standard register usage.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.
   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.

   HP-PA 1.0 has 32 fullword registers and 16 floating point
   registers. The floating point registers hold either word or double
   word values.

   16 additional registers are reserved.

   HP-PA 1.1 has 32 fullword registers and 32 floating point
   registers. However, the floating point registers behave
   differently: the left and right halves of registers are addressable
   as 32-bit registers. So, we will set things up like the 68k which
   has different fp units: define separate register sets for the 1.0
   and 1.1 fp units.  */

#define FIRST_PSEUDO_REGISTER 90  /* 32 general regs + 56 fp regs +
				     + 1 shift reg + frame pointer */

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.

   On the HP-PA, these are:
   Reg 0	= 0 (hardware). However, 0 is used for condition code,
                  so is not fixed.
   Reg 1	= ADDIL target/Temporary (hardware).
   Reg 2	= Return Pointer
   Reg 3	= Frame Pointer
   Reg 4	= Frame Pointer (>8k varying frame with HP compilers only)
   Reg 4-18	= Preserved Registers
   Reg 19	= Linkage Table Register in HPUX 8.0 shared library scheme.
   Reg 20-22	= Temporary Registers
   Reg 23-26	= Temporary/Parameter Registers
   Reg 27	= Global Data Pointer (hp)
   Reg 28	= Temporary/Return Value register
   Reg 29	= Temporary/Static Chain/Return Value register #2
   Reg 30	= stack pointer
   Reg 31	= Temporary/Millicode Return Pointer (hp)

   Freg 0-3	= Status Registers	 -- Not known to the compiler.
   Freg 4-7	= Arguments/Return Value
   Freg 8-11	= Temporary Registers
   Freg 12-15	= Preserved Registers

   Freg 16-31	= Reserved

   On the Snake, fp regs are

   Freg 0-3	= Status Registers	-- Not known to the compiler.
   Freg 4L-7R	= Arguments/Return Value
   Freg 8L-11R	= Temporary Registers
   Freg 12L-21R	= Preserved Registers
   Freg 22L-31R = Temporary Registers

*/

#define FIXED_REGISTERS  \
 {0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 1, 0, 0, 1, 0, \
  /* fp registers */	  \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  /* shift register and soft frame pointer */ \
  0, 1}

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.  */
#define CALL_USED_REGISTERS  \
 {1, 1, 1, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 1, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1, \
  /* fp registers */	  \
  1, 1, 1, 1, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 0, 0, 0, 0, \
  0, 0, 0, 0, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1, \
  1, 1, 1, 1, 1, 1, 1, 1, \
  /* shift register and soft frame pointer */ \
  1, 1}

/* Allocate the call used registers first.  This should minimize
   the number of registers that need to be saved (as call used
   registers will generally not be allocated across a call).

   Experimentation has shown slightly better results by allocating
   FP registers first.  We allocate the caller-saved registers more
   or less in reverse order to their allocation as arguments.

   FP registers are ordered so that all L registers are selected before
   R registers.  This works around a false dependency interlock on the
   PA8000 when accessing the high and low parts of an FP register
   independently.  */

#define REG_ALLOC_ORDER \
 {					\
  /* caller-saved fp regs.  */		\
  68, 70, 72, 74, 76, 78, 80, 82,	\
  84, 86, 40, 42, 44, 46, 38, 36,	\
  34, 32,				\
  69, 71, 73, 75, 77, 79, 81, 83,	\
  85, 87, 41, 43, 45, 47, 39, 37,	\
  35, 33,				\
  /* caller-saved general regs.  */	\
  28, 19, 20, 21, 22, 31, 27, 29,	\
  23, 24, 25, 26,  2,			\
  /* callee-saved fp regs.  */		\
  48, 50, 52, 54, 56, 58, 60, 62,	\
  64, 66,				\
  49, 51, 53, 55, 57, 59, 61, 63,	\
  65, 67,				\
  /* callee-saved general regs.  */	\
   3,  4,  5,  6,  7,  8,  9, 10, 	\
  11, 12, 13, 14, 15, 16, 17, 18,	\
  /* special registers.  */		\
   1, 30,  0, 88, 89}


/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.

   On the HP-PA, general registers are 32 bits wide.  The floating
   point registers are 64 bits wide.  Snake fp regs are treated as
   32 bits wide since the left and right parts are independently
   accessible.  */
#define PA_HARD_REGNO_NREGS(REGNO, MODE)				\
  (FP_REGNO_P (REGNO)							\
   ? (!TARGET_PA_11							\
      ? COMPLEX_MODE_P (MODE) ? 2 : 1					\
      : (GET_MODE_SIZE (MODE) + 4 - 1) / 4) 	                        \
   : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

/* There are no instructions that use DImode in PA 1.0, so we only
   allow it in PA 1.1 and later.  */
#define VALID_FP_MODE_P(MODE)						\
  ((MODE) == SFmode || (MODE) == DFmode					\
   || (MODE) == SCmode || (MODE) == DCmode				\
   || (MODE) == SImode || (TARGET_PA_11 && (MODE) == DImode))

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.

   On the HP-PA, the cpu registers can hold any mode that fits in 32 bits.
   For the 64-bit modes, we choose a set of non-overlapping general registers
   that includes the incoming arguments and the return value.  We specify a
   set with no overlaps so that we don't have to specify that the destination
   register is an early clobber in patterns using this mode.  Except for the
   return value, the starting registers are odd.  For 128 and 256 bit modes,
   we similarly specify non-overlapping sets of cpu registers.  However,
   there aren't any patterns defined for modes larger than 64 bits at the
   moment.

   We limit the modes allowed in the floating point registers to the
   set of modes used in the machine definition.  In addition, we allow
   the complex modes SCmode and DCmode.  The real and imaginary parts
   of complex modes are allocated to separate registers.  This might
   allow patterns to be defined in the future to operate on these values.

   The PA 2.0 architecture specifies that quad-precision floating-point
   values should start on an even floating point register.  Thus, we
   choose non-overlapping sets of registers starting on even register
   boundaries for large modes.  However, there is currently no support
   in the machine definition for modes larger than 64 bits.  TFmode is
   supported under HP-UX using libcalls.  Since TFmode values are passed
   by reference, they never need to be loaded into the floating-point
   registers.  */
#define PA_HARD_REGNO_MODE_OK(REGNO, MODE) \
  ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode		\
   : (REGNO) == 88 ? SCALAR_INT_MODE_P (MODE)				\
   : !TARGET_PA_11 && FP_REGNO_P (REGNO)				\
     ? (VALID_FP_MODE_P (MODE)						\
	&& (GET_MODE_SIZE (MODE) <= 8					\
	    || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0)))	\
   : FP_REGNO_P (REGNO)							\
     ? (VALID_FP_MODE_P (MODE)						\
	&& (GET_MODE_SIZE (MODE) <= 4					\
	    || (GET_MODE_SIZE (MODE) == 8 && ((REGNO) & 1) == 0)	\
	    || (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0)	\
	    || (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 7) == 0)))	\
   : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD				\
      || (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD			\
	  && ((((REGNO) & 1) == 1 && (REGNO) <= 25) || (REGNO) == 28))	\
      || (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD			\
	  && ((REGNO) & 3) == 3 && (REGNO) <= 23)			\
      || (GET_MODE_SIZE (MODE) == 8 * UNITS_PER_WORD			\
	  && ((REGNO) & 7) == 3 && (REGNO) <= 19)))

/* How to renumber registers for dbx and gdb.

   Registers 0  - 31 remain unchanged.

   Registers 32 - 87 are mapped to 72 - 127

   Register 88 is mapped to 32.  */

#define DBX_REGISTER_NUMBER(REGNO) \
  ((REGNO) <= 31 ? (REGNO) :						\
   ((REGNO) <= 87 ? (REGNO) + 40 : 32))

/* We must not use the DBX register numbers for the DWARF 2 CFA column
   numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
   Instead use the identity mapping.  */
#define DWARF_FRAME_REGNUM(REG) REG

/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another
   class that represents their union.  */

  /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
     1.1 fp regs, and the high 1.1 fp regs, to which the operands of
     fmpyadd and fmpysub are restricted.  */

enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
		 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};

#define N_REG_CLASSES (int) LIM_REG_CLASSES

/* Give names of register classes as strings for dump file.  */

#define REG_CLASS_NAMES \
  {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
   "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}

/* Define which registers fit in which classes.
   This is an initializer for a vector of HARD_REG_SET
   of length N_REG_CLASSES. Register 0, the "condition code" register,
   is in no class.  */

#define REG_CLASS_CONTENTS	\
 {{0x00000000, 0x00000000, 0x00000000},	/* NO_REGS */			\
  {0x00000002, 0x00000000, 0x00000000},	/* R1_REGS */			\
  {0xfffffffe, 0x00000000, 0x02000000},	/* GENERAL_REGS */		\
  {0x00000000, 0xff000000, 0x00ffffff},	/* FPUPPER_REGS */		\
  {0x00000000, 0xffffffff, 0x00ffffff},	/* FP_REGS */			\
  {0xfffffffe, 0xffffffff, 0x02ffffff},	/* GENERAL_OR_FP_REGS */	\
  {0x00000000, 0x00000000, 0x01000000},	/* SHIFT_REGS */		\
  {0xfffffffe, 0xffffffff, 0x03ffffff}}	/* ALL_REGS */

/* Return the class number of the smallest class containing
   reg number REGNO.  This could be a conditional expression
   or could index an array.  */

#define REGNO_REG_CLASS(REGNO)						\
  ((REGNO) == 0 ? NO_REGS 						\
   : (REGNO) == 1 ? R1_REGS						\
   : (REGNO) < 32 || (REGNO) == 89 ? GENERAL_REGS			\
   : (REGNO) < 56 ? FP_REGS						\
   : (REGNO) < 88 ? FPUPPER_REGS					\
   : SHIFT_REGS)

/* Return the maximum number of consecutive registers
   needed to represent mode MODE in a register of class CLASS.  */
#define CLASS_MAX_NREGS(CLASS, MODE)					\
  ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS			\
   ? (!TARGET_PA_11							\
      ? COMPLEX_MODE_P (MODE) ? 2 : 1					\
      : (GET_MODE_SIZE (MODE) + 4 - 1) / 4)				\
   : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))

/* 1 if N is a possible register number for function argument passing.  */

#define FUNCTION_ARG_REGNO_P(N) \
  (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39)) 

/* How to refer to registers in assembler output.
   This sequence is indexed by compiler's hard-register-number (see above).  */

#define REGISTER_NAMES \
{"%r0",   "%r1",    "%r2",   "%r3",    "%r4",   "%r5",    "%r6",   "%r7",    \
 "%r8",   "%r9",    "%r10",  "%r11",   "%r12",  "%r13",   "%r14",  "%r15",   \
 "%r16",  "%r17",   "%r18",  "%r19",   "%r20",  "%r21",   "%r22",  "%r23",   \
 "%r24",  "%r25",   "%r26",  "%r27",   "%r28",  "%r29",   "%r30",  "%r31",   \
 "%fr4",  "%fr4R",  "%fr5",  "%fr5R",  "%fr6",  "%fr6R",  "%fr7",  "%fr7R",  \
 "%fr8",  "%fr8R",  "%fr9",  "%fr9R",  "%fr10", "%fr10R", "%fr11", "%fr11R", \
 "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \
 "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \
 "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \
 "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \
 "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \
 "SAR",   "sfp"}

#define ADDITIONAL_REGISTER_NAMES \
{{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38},		\
 {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46},		\
 {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54},		\
 {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62},		\
 {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70},		\
 {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78},		\
 {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86},		\
 {"%cr11",88}}

#define FP_SAVED_REG_LAST 66
#define FP_SAVED_REG_FIRST 48
#define FP_REG_STEP 2
#define FP_REG_FIRST 32
#define FP_REG_LAST 87
Commit	Line	Data
99dee823	1	/* Copyright (C) 2000-2021 Free Software Foundation, Inc.
ad41bd84 JM	2
	3	This file is part of GCC.
	4
	5	GCC is free software; you can redistribute it and/or modify it under
	6	the terms of the GNU General Public License as published by the Free
	7	Software Foundation; either version 3, or (at your option) any later
	8	version.
	9
	10	GCC is distributed in the hope that it will be useful, but WITHOUT ANY
	11	WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	for more details.
	14
	15	Under Section 7 of GPL version 3, you are granted additional
	16	permissions described in the GCC Runtime Library Exception, version
	17	3.1, as published by the Free Software Foundation.
	18
	19	You should have received a copy of the GNU General Public License and
	20	a copy of the GCC Runtime Library Exception along with this program;
	21	see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
	22	<http://www.gnu.org/licenses/>. */
	23
88624c0e JL	24	/* Standard register usage. */
	25
	26	/* Number of actual hardware registers.
	27	The hardware registers are assigned numbers for the compiler
	28	from 0 to just below FIRST_PSEUDO_REGISTER.
	29	All registers that the compiler knows about must be given numbers,
	30	even those that are not normally considered general registers.
	31
	32	HP-PA 1.0 has 32 fullword registers and 16 floating point
	33	registers. The floating point registers hold either word or double
	34	word values.
	35
	36	16 additional registers are reserved.
	37
	38	HP-PA 1.1 has 32 fullword registers and 32 floating point
	39	registers. However, the floating point registers behave
	40	differently: the left and right halves of registers are addressable
a7b376ee	41	as 32-bit registers. So, we will set things up like the 68k which
88624c0e	42	has different fp units: define separate register sets for the 1.0
fe19a83d	43	and 1.1 fp units. */
88624c0e	44
bc707992 JDA	45	#define FIRST_PSEUDO_REGISTER 90 /* 32 general regs + 56 fp regs +
bc707992 JDA	46	+ 1 shift reg + frame pointer */
88624c0e JL	47
	48	/* 1 for registers that have pervasive standard uses
	49	and are not available for the register allocator.
	50
	51	On the HP-PA, these are:
	52	Reg 0 = 0 (hardware). However, 0 is used for condition code,
	53	so is not fixed.
	54	Reg 1 = ADDIL target/Temporary (hardware).
	55	Reg 2 = Return Pointer
	56	Reg 3 = Frame Pointer
	57	Reg 4 = Frame Pointer (>8k varying frame with HP compilers only)
	58	Reg 4-18 = Preserved Registers
	59	Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme.
	60	Reg 20-22 = Temporary Registers
	61	Reg 23-26 = Temporary/Parameter Registers
	62	Reg 27 = Global Data Pointer (hp)
	63	Reg 28 = Temporary/Return Value register
	64	Reg 29 = Temporary/Static Chain/Return Value register #2
	65	Reg 30 = stack pointer
	66	Reg 31 = Temporary/Millicode Return Pointer (hp)
	67
	68	Freg 0-3 = Status Registers -- Not known to the compiler.
	69	Freg 4-7 = Arguments/Return Value
	70	Freg 8-11 = Temporary Registers
	71	Freg 12-15 = Preserved Registers
	72
	73	Freg 16-31 = Reserved
	74
	75	On the Snake, fp regs are
	76
	77	Freg 0-3 = Status Registers -- Not known to the compiler.
	78	Freg 4L-7R = Arguments/Return Value
	79	Freg 8L-11R = Temporary Registers
	80	Freg 12L-21R = Preserved Registers
	81	Freg 22L-31R = Temporary Registers
	82
	83	*/
	84
	85	#define FIXED_REGISTERS \
	86	{0, 0, 0, 0, 0, 0, 0, 0, \
	87	0, 0, 0, 0, 0, 0, 0, 0, \
	88	0, 0, 0, 0, 0, 0, 0, 0, \
	89	0, 0, 0, 1, 0, 0, 1, 0, \
	90	/* fp registers */ \
	91	0, 0, 0, 0, 0, 0, 0, 0, \
	92	0, 0, 0, 0, 0, 0, 0, 0, \
	93	0, 0, 0, 0, 0, 0, 0, 0, \
	94	0, 0, 0, 0, 0, 0, 0, 0, \
	95	0, 0, 0, 0, 0, 0, 0, 0, \
	96	0, 0, 0, 0, 0, 0, 0, 0, \
	97	0, 0, 0, 0, 0, 0, 0, 0, \
bc707992 JDA	98	/* shift register and soft frame pointer */ \
bc707992 JDA	99	0, 1}
88624c0e JL	100
	101	/* 1 for registers not available across function calls.
	102	These must include the FIXED_REGISTERS and also any
	103	registers that can be used without being saved.
	104	The latter must include the registers where values are returned
	105	and the register where structure-value addresses are passed.
	106	Aside from that, you can include as many other registers as you like. */
	107	#define CALL_USED_REGISTERS \
	108	{1, 1, 1, 0, 0, 0, 0, 0, \
	109	0, 0, 0, 0, 0, 0, 0, 0, \
	110	0, 0, 0, 1, 1, 1, 1, 1, \
	111	1, 1, 1, 1, 1, 1, 1, 1, \
	112	/* fp registers */ \
	113	1, 1, 1, 1, 1, 1, 1, 1, \
	114	1, 1, 1, 1, 1, 1, 1, 1, \
	115	0, 0, 0, 0, 0, 0, 0, 0, \
	116	0, 0, 0, 0, 0, 0, 0, 0, \
	117	0, 0, 0, 0, 1, 1, 1, 1, \
	118	1, 1, 1, 1, 1, 1, 1, 1, \
	119	1, 1, 1, 1, 1, 1, 1, 1, \
bc707992 JDA	120	/* shift register and soft frame pointer */ \
bc707992 JDA	121	1, 1}
88624c0e	122
88624c0e JL	123	/* Allocate the call used registers first. This should minimize
	124	the number of registers that need to be saved (as call used
	125	registers will generally not be allocated across a call).
	126
	127	Experimentation has shown slightly better results by allocating
747e2d0e JDA	128	FP registers first. We allocate the caller-saved registers more
747e2d0e JDA	129	or less in reverse order to their allocation as arguments.
88624c0e JL	130
	131	FP registers are ordered so that all L registers are selected before
	132	R registers. This works around a false dependency interlock on the
	133	PA8000 when accessing the high and low parts of an FP register
	134	independently. */
	135
	136	#define REG_ALLOC_ORDER \
	137	{ \
	138	/* caller-saved fp regs. */ \
	139	68, 70, 72, 74, 76, 78, 80, 82, \
747e2d0e JDA	140	84, 86, 40, 42, 44, 46, 38, 36, \
747e2d0e JDA	141	34, 32, \
88624c0e	142	69, 71, 73, 75, 77, 79, 81, 83, \
747e2d0e JDA	143	85, 87, 41, 43, 45, 47, 39, 37, \
747e2d0e JDA	144	35, 33, \
88624c0e	145	/* caller-saved general regs. */ \
747e2d0e JDA	146	28, 19, 20, 21, 22, 31, 27, 29, \
747e2d0e JDA	147	23, 24, 25, 26, 2, \
88624c0e JL	148	/* callee-saved fp regs. */ \
	149	48, 50, 52, 54, 56, 58, 60, 62, \
	150	64, 66, \
	151	49, 51, 53, 55, 57, 59, 61, 63, \
	152	65, 67, \
	153	/* callee-saved general regs. */ \
	154	3, 4, 5, 6, 7, 8, 9, 10, \
	155	11, 12, 13, 14, 15, 16, 17, 18, \
	156	/* special registers. */ \
bc707992	157	1, 30, 0, 88, 89}
88624c0e JL	158
	159
	160	/* Return number of consecutive hard regs needed starting at reg REGNO
	161	to hold something of mode MODE.
	162	This is ordinarily the length in words of a value of mode MODE
	163	but can be less for certain modes in special long registers.
	164
47971fa7 JDA	165	On the HP-PA, general registers are 32 bits wide. The floating
	166	point registers are 64 bits wide. Snake fp regs are treated as
	167	32 bits wide since the left and right parts are independently
	168	accessible. */
c43f4279	169	#define PA_HARD_REGNO_NREGS(REGNO, MODE) \
88624c0e	170	(FP_REGNO_P (REGNO) \
47971fa7 JDA	171	? (!TARGET_PA_11 \
	172	? COMPLEX_MODE_P (MODE) ? 2 : 1 \
	173	: (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
	174	: (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
	175
	176	/* There are no instructions that use DImode in PA 1.0, so we only
	177	allow it in PA 1.1 and later. */
	178	#define VALID_FP_MODE_P(MODE) \
	179	((MODE) == SFmode \|\| (MODE) == DFmode \
	180	\|\| (MODE) == SCmode \|\| (MODE) == DCmode \
6982c5d4	181	\|\| (MODE) == SImode \|\| (TARGET_PA_11 && (MODE) == DImode))
88624c0e JL	182
88624c0e JL	183	/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
47971fa7 JDA	184
	185	On the HP-PA, the cpu registers can hold any mode that fits in 32 bits.
	186	For the 64-bit modes, we choose a set of non-overlapping general registers
	187	that includes the incoming arguments and the return value. We specify a
	188	set with no overlaps so that we don't have to specify that the destination
	189	register is an early clobber in patterns using this mode. Except for the
	190	return value, the starting registers are odd. For 128 and 256 bit modes,
	191	we similarly specify non-overlapping sets of cpu registers. However,
	192	there aren't any patterns defined for modes larger than 64 bits at the
	193	moment.
	194
	195	We limit the modes allowed in the floating point registers to the
	196	set of modes used in the machine definition. In addition, we allow
	197	the complex modes SCmode and DCmode. The real and imaginary parts
	198	of complex modes are allocated to separate registers. This might
	199	allow patterns to be defined in the future to operate on these values.
	200
	201	The PA 2.0 architecture specifies that quad-precision floating-point
	202	values should start on an even floating point register. Thus, we
	203	choose non-overlapping sets of registers starting on even register
	204	boundaries for large modes. However, there is currently no support
	205	in the machine definition for modes larger than 64 bits. TFmode is
	206	supported under HP-UX using libcalls. Since TFmode values are passed
	207	by reference, they never need to be loaded into the floating-point
	208	registers. */
f939c3e6	209	#define PA_HARD_REGNO_MODE_OK(REGNO, MODE) \
88624c0e	210	((REGNO) == 0 ? (MODE) == CCmode \|\| (MODE) == CCFPmode \
483d7ad3	211	: (REGNO) == 88 ? SCALAR_INT_MODE_P (MODE) \
88624c0e	212	: !TARGET_PA_11 && FP_REGNO_P (REGNO) \
47971fa7 JDA	213	? (VALID_FP_MODE_P (MODE) \
	214	&& (GET_MODE_SIZE (MODE) <= 8 \
	215	\|\| (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0))) \
88624c0e	216	: FP_REGNO_P (REGNO) \
47971fa7 JDA	217	? (VALID_FP_MODE_P (MODE) \
	218	&& (GET_MODE_SIZE (MODE) <= 4 \
	219	\|\| (GET_MODE_SIZE (MODE) == 8 && ((REGNO) & 1) == 0) \
	220	\|\| (GET_MODE_SIZE (MODE) == 16 && ((REGNO) & 3) == 0) \
	221	\|\| (GET_MODE_SIZE (MODE) == 32 && ((REGNO) & 7) == 0))) \
88624c0e	222	: (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
12877f09 JDA	223	\|\| (GET_MODE_SIZE (MODE) == 2 * UNITS_PER_WORD \
	224	&& ((((REGNO) & 1) == 1 && (REGNO) <= 25) \|\| (REGNO) == 28)) \
	225	\|\| (GET_MODE_SIZE (MODE) == 4 * UNITS_PER_WORD \
47971fa7 JDA	226	&& ((REGNO) & 3) == 3 && (REGNO) <= 23) \
	227	\|\| (GET_MODE_SIZE (MODE) == 8 * UNITS_PER_WORD \
	228	&& ((REGNO) & 7) == 3 && (REGNO) <= 19)))
88624c0e JL	229
	230	/* How to renumber registers for dbx and gdb.
	231
	232	Registers 0 - 31 remain unchanged.
	233
	234	Registers 32 - 87 are mapped to 72 - 127
	235
	236	Register 88 is mapped to 32. */
	237
	238	#define DBX_REGISTER_NUMBER(REGNO) \
	239	((REGNO) <= 31 ? (REGNO) : \
e25724d8 AM	240	((REGNO) <= 87 ? (REGNO) + 40 : 32))
	241
	242	/* We must not use the DBX register numbers for the DWARF 2 CFA column
	243	numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
	244	Instead use the identity mapping. */
	245	#define DWARF_FRAME_REGNUM(REG) REG
88624c0e JL	246
	247	/* Define the classes of registers for register constraints in the
	248	machine description. Also define ranges of constants.
	249
	250	One of the classes must always be named ALL_REGS and include all hard regs.
	251	If there is more than one class, another class must be named NO_REGS
	252	and contain no registers.
	253
	254	The name GENERAL_REGS must be the name of a class (or an alias for
	255	another name such as ALL_REGS). This is the class of registers
	256	that is allowed by "g" or "r" in a register constraint.
	257	Also, registers outside this class are allocated only when
	258	instructions express preferences for them.
	259
	260	The classes must be numbered in nondecreasing order; that is,
	261	a larger-numbered class must never be contained completely
	262	in a smaller-numbered class.
	263
	264	For any two classes, it is very desirable that there be another
	265	class that represents their union. */
	266
	267	/* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
	268	1.1 fp regs, and the high 1.1 fp regs, to which the operands of
	269	fmpyadd and fmpysub are restricted. */
	270
	271	enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
	272	GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
	273
	274	#define N_REG_CLASSES (int) LIM_REG_CLASSES
	275
71cc389b	276	/* Give names of register classes as strings for dump file. */
88624c0e JL	277
	278	#define REG_CLASS_NAMES \
	279	{"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
	280	"GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
	281
	282	/* Define which registers fit in which classes.
	283	This is an initializer for a vector of HARD_REG_SET
	284	of length N_REG_CLASSES. Register 0, the "condition code" register,
fe19a83d	285	is in no class. */
88624c0e JL	286
	287	#define REG_CLASS_CONTENTS \
	288	{{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \
	289	{0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \
bc707992	290	{0xfffffffe, 0x00000000, 0x02000000}, /* GENERAL_REGS */ \
88624c0e JL	291	{0x00000000, 0xff000000, 0x00ffffff}, /* FPUPPER_REGS */ \
88624c0e JL	292	{0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \
bc707992	293	{0xfffffffe, 0xffffffff, 0x02ffffff}, /* GENERAL_OR_FP_REGS */ \
88624c0e	294	{0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \
bc707992	295	{0xfffffffe, 0xffffffff, 0x03ffffff}} /* ALL_REGS */
88624c0e	296
710ba35f	297	/* Return the class number of the smallest class containing
88624c0e JL	298	reg number REGNO. This could be a conditional expression
	299	or could index an array. */
	300
	301	#define REGNO_REG_CLASS(REGNO) \
	302	((REGNO) == 0 ? NO_REGS \
	303	: (REGNO) == 1 ? R1_REGS \
bc707992	304	: (REGNO) < 32 \|\| (REGNO) == 89 ? GENERAL_REGS \
88624c0e JL	305	: (REGNO) < 56 ? FP_REGS \
88624c0e JL	306	: (REGNO) < 88 ? FPUPPER_REGS \
88624c0e JL	307	: SHIFT_REGS)
88624c0e JL	308
88624c0e JL	309	/* Return the maximum number of consecutive registers
	310	needed to represent mode MODE in a register of class CLASS. */
	311	#define CLASS_MAX_NREGS(CLASS, MODE) \
	312	((CLASS) == FP_REGS \|\| (CLASS) == FPUPPER_REGS \
47971fa7 JDA	313	? (!TARGET_PA_11 \
	314	? COMPLEX_MODE_P (MODE) ? 2 : 1 \
	315	: (GET_MODE_SIZE (MODE) + 4 - 1) / 4) \
88624c0e JL	316	: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
	317
	318	/* 1 if N is a possible register number for function argument passing. */
	319
	320	#define FUNCTION_ARG_REGNO_P(N) \
	321	(((N) >= 23 && (N) <= 26) \|\| (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
	322
	323	/* How to refer to registers in assembler output.
	324	This sequence is indexed by compiler's hard-register-number (see above). */
	325
	326	#define REGISTER_NAMES \
	327	{"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
	328	"%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
	329	"%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \
	330	"%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \
	331	"%fr4", "%fr4R", "%fr5", "%fr5R", "%fr6", "%fr6R", "%fr7", "%fr7R", \
	332	"%fr8", "%fr8R", "%fr9", "%fr9R", "%fr10", "%fr10R", "%fr11", "%fr11R", \
	333	"%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \
	334	"%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \
	335	"%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \
	336	"%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \
	337	"%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \
bc707992	338	"SAR", "sfp"}
88624c0e JL	339
	340	#define ADDITIONAL_REGISTER_NAMES \
	341	{{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \
	342	{"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \
	343	{"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \
	344	{"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62}, \
	345	{"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70}, \
	346	{"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78}, \
	347	{"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86}, \
	348	{"%cr11",88}}
	349
	350	#define FP_SAVED_REG_LAST 66
	351	#define FP_SAVED_REG_FIRST 48
	352	#define FP_REG_STEP 2
	353	#define FP_REG_FIRST 32
	354	#define FP_REG_LAST 87