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09cae750 1;; PIC codegen for RISC-V for GNU compiler.
a945c346 2;; Copyright (C) 2011-2024 Free Software Foundation, Inc.
09cae750
PD
3;; Contributed by Andrew Waterman (andrew@sifive.com).
4
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify
8;; it under the terms of the GNU General Public License as published by
9;; the Free Software Foundation; either version 3, or (at your option)
10;; any later version.
11
12;; GCC is distributed in the hope that it will be useful,
13;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15;; GNU General Public License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3. If not see
19;; <http://www.gnu.org/licenses/>.
20
21
22;; Simplify PIC loads to static variables.
23;; These should go away once we figure out how to emit auipc discretely.
24
efc60124 25(define_insn "*local_pic_load<mode>"
09cae750 26 [(set (match_operand:ANYI 0 "register_operand" "=r")
efc60124
JW
27 (mem:ANYI (match_operand 1 "absolute_symbolic_operand" "")))]
28 "USE_LOAD_ADDRESS_MACRO (operands[1])"
29 "<default_load>\t%0,%1"
c85db606
EL
30 [(set_attr "type" "load")
31 (set (attr "length") (const_int 8))])
efc60124 32
7ef00402 33(define_insn "*local_pic_load_s<SUBX:mode>"
efc60124
JW
34 [(set (match_operand:SUPERQI 0 "register_operand" "=r")
35 (sign_extend:SUPERQI (mem:SUBX (match_operand 1 "absolute_symbolic_operand" ""))))]
09cae750 36 "USE_LOAD_ADDRESS_MACRO (operands[1])"
efc60124 37 "<SUBX:load>\t%0,%1"
c85db606
EL
38 [(set_attr "type" "load")
39 (set (attr "length") (const_int 8))])
09cae750 40
7ef00402 41(define_insn "*local_pic_load_u<SUBX:mode>"
efc60124
JW
42 [(set (match_operand:SUPERQI 0 "register_operand" "=r")
43 (zero_extend:SUPERQI (mem:SUBX (match_operand 1 "absolute_symbolic_operand" ""))))]
0b661358 44 "USE_LOAD_ADDRESS_MACRO (operands[1])"
efc60124 45 "<SUBX:load>u\t%0,%1"
c85db606
EL
46 [(set_attr "type" "load")
47 (set (attr "length") (const_int 8))])
0b661358 48
3709ca09 49;; We can support ANYLSF loads into X register if there is no double support
efc60124
JW
50;; or if the target is 64-bit.
51
3709ca09
LD
52(define_insn "*local_pic_load<ANYLSF:mode>"
53 [(set (match_operand:ANYLSF 0 "register_operand" "=f,*r")
54 (mem:ANYLSF (match_operand 1 "absolute_symbolic_operand" "")))
efc60124
JW
55 (clobber (match_scratch:P 2 "=r,X"))]
56 "TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
57 && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)"
58 "@
3709ca09 59 <ANYLSF:load>\t%0,%1,%2
efc60124 60 <softload>\t%0,%1"
c85db606
EL
61 [(set_attr "type" "fpload")
62 (set (attr "length") (const_int 8))])
09cae750 63
efc60124
JW
64;; ??? For a 32-bit target with double float, a DF load into a X reg isn't
65;; supported. ld is not valid in that case. Punt for now. Maybe add a split
66;; for this later.
67
3709ca09
LD
68(define_insn "*local_pic_load_32d<ANYLSF:mode>"
69 [(set (match_operand:ANYLSF 0 "register_operand" "=f")
70 (mem:ANYLSF (match_operand 1 "absolute_symbolic_operand" "")))
efc60124
JW
71 (clobber (match_scratch:P 2 "=r"))]
72 "TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
73 && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)"
3709ca09 74 "<ANYLSF:load>\t%0,%1,%2"
c85db606
EL
75 [(set_attr "type" "fpload")
76 (set (attr "length") (const_int 8))])
09cae750 77
efc60124
JW
78(define_insn "*local_pic_load_sf<mode>"
79 [(set (match_operand:SOFTF 0 "register_operand" "=r")
80 (mem:SOFTF (match_operand 1 "absolute_symbolic_operand" "")))]
81 "!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])"
82 "<softload>\t%0,%1"
c85db606
EL
83 [(set_attr "type" "fpload")
84 (set (attr "length") (const_int 8))])
09cae750 85
efc60124
JW
86;; Simplify PIC stores to static variables.
87;; These should go away once we figure out how to emit auipc discretely.
09cae750 88
efc60124 89(define_insn "*local_pic_store<ANYI:mode>"
09cae750
PD
90 [(set (mem:ANYI (match_operand 0 "absolute_symbolic_operand" ""))
91 (match_operand:ANYI 1 "reg_or_0_operand" "rJ"))
efc60124
JW
92 (clobber (match_scratch:P 2 "=&r"))]
93 "USE_LOAD_ADDRESS_MACRO (operands[0])"
94 "<ANYI:store>\t%z1,%0,%2"
c85db606
EL
95 [(set_attr "type" "store")
96 (set (attr "length") (const_int 8))])
09cae750 97
3709ca09
LD
98(define_insn "*local_pic_store<ANYLSF:mode>"
99 [(set (mem:ANYLSF (match_operand 0 "absolute_symbolic_operand" ""))
100 (match_operand:ANYLSF 1 "register_operand" "f,*r"))
efc60124
JW
101 (clobber (match_scratch:P 2 "=r,&r"))]
102 "TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])
103 && (!TARGET_DOUBLE_FLOAT || TARGET_64BIT)"
104 "@
3709ca09 105 <ANYLSF:store>\t%1,%0,%2
efc60124 106 <softstore>\t%1,%0,%2"
c85db606
EL
107 [(set_attr "type" "fpstore")
108 (set (attr "length") (const_int 8))])
09cae750 109
efc60124
JW
110;; ??? For a 32-bit target with double float, a DF store from a X reg isn't
111;; supported. sd is not valid in that case. Punt for now. Maybe add a split
112;; for this later.
113
3709ca09
LD
114(define_insn "*local_pic_store_32d<ANYLSF:mode>"
115 [(set (match_operand:ANYLSF 0 "register_operand" "=f")
116 (mem:ANYLSF (match_operand 1 "absolute_symbolic_operand" "")))
efc60124
JW
117 (clobber (match_scratch:P 2 "=r"))]
118 "TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[1])
119 && (TARGET_DOUBLE_FLOAT && !TARGET_64BIT)"
3709ca09 120 "<ANYLSF:store>\t%1,%0,%2"
c85db606
EL
121 [(set_attr "type" "fpstore")
122 (set (attr "length") (const_int 8))])
efc60124
JW
123
124(define_insn "*local_pic_store_sf<SOFTF:mode>"
125 [(set (mem:SOFTF (match_operand 0 "absolute_symbolic_operand" ""))
126 (match_operand:SOFTF 1 "register_operand" "r"))
127 (clobber (match_scratch:P 2 "=&r"))]
128 "!TARGET_HARD_FLOAT && USE_LOAD_ADDRESS_MACRO (operands[0])"
129 "<softstore>\t%1,%0,%2"
c85db606
EL
130 [(set_attr "type" "fpstore")
131 (set (attr "length") (const_int 8))])