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09cae750 | 1 | /* Definition of RISC-V target for GNU compiler. |
8d9254fc | 2 | Copyright (C) 2016-2020 Free Software Foundation, Inc. |
09cae750 PD |
3 | Contributed by Andrew Waterman (andrew@sifive.com). |
4 | ||
5 | This file is part of GCC. | |
6 | ||
7 | GCC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GCC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GCC; see the file COPYING3. If not see | |
19 | <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #ifndef GCC_RISCV_OPTS_H | |
22 | #define GCC_RISCV_OPTS_H | |
23 | ||
24 | enum riscv_abi_type { | |
25 | ABI_ILP32, | |
09baee1a | 26 | ABI_ILP32E, |
09cae750 PD |
27 | ABI_ILP32F, |
28 | ABI_ILP32D, | |
29 | ABI_LP64, | |
30 | ABI_LP64F, | |
31 | ABI_LP64D | |
32 | }; | |
33 | extern enum riscv_abi_type riscv_abi; | |
34 | ||
35 | enum riscv_code_model { | |
36 | CM_MEDLOW, | |
37 | CM_MEDANY, | |
38 | CM_PIC | |
39 | }; | |
40 | extern enum riscv_code_model riscv_cmodel; | |
41 | ||
88108b27 AW |
42 | /* Keep this list in sync with define_attr "tune" in riscv.md. */ |
43 | enum riscv_microarchitecture_type { | |
44 | generic, | |
45 | sifive_7 | |
46 | }; | |
47 | extern enum riscv_microarchitecture_type riscv_microarchitecture; | |
48 | ||
ffbb9818 ID |
49 | enum riscv_align_data { |
50 | riscv_align_data_type_xlen, | |
51 | riscv_align_data_type_natural | |
52 | }; | |
53 | ||
09cae750 | 54 | #endif /* ! GCC_RISCV_OPTS_H */ |