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09cae750 | 1 | /* Definition of RISC-V target for GNU compiler. |
a945c346 | 2 | Copyright (C) 2011-2024 Free Software Foundation, Inc. |
09cae750 PD |
3 | Contributed by Andrew Waterman (andrew@sifive.com). |
4 | Based on MIPS target for GNU compiler. | |
5 | ||
6 | This file is part of GCC. | |
7 | ||
8 | GCC is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GCC is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GCC; see the file COPYING3. If not see | |
20 | <http://www.gnu.org/licenses/>. */ | |
21 | ||
22 | #ifndef GCC_RISCV_PROTOS_H | |
23 | #define GCC_RISCV_PROTOS_H | |
24 | ||
942ab49b PN |
25 | #include "memmodel.h" |
26 | ||
09cae750 PD |
27 | /* Symbol types we understand. The order of this list must match that of |
28 | the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ | |
29 | enum riscv_symbol_type { | |
30 | SYMBOL_ABSOLUTE, | |
d07d0e99 | 31 | SYMBOL_FORCE_TO_MEM, |
09cae750 PD |
32 | SYMBOL_PCREL, |
33 | SYMBOL_GOT_DISP, | |
34 | SYMBOL_TLS, | |
35 | SYMBOL_TLS_LE, | |
36 | SYMBOL_TLS_IE, | |
97069657 TI |
37 | SYMBOL_TLS_GD, |
38 | SYMBOL_TLSDESC, | |
09cae750 | 39 | }; |
97069657 | 40 | #define NUM_SYMBOL_TYPES (SYMBOL_TLSDESC + 1) |
09cae750 | 41 | |
96ad6ab2 CM |
42 | /* Classifies an address. |
43 | ||
44 | ADDRESS_REG | |
45 | A natural register + offset address. The register satisfies | |
46 | riscv_valid_base_register_p and the offset is a const_arith_operand. | |
47 | ||
2d65622f CM |
48 | ADDRESS_REG_REG |
49 | A base register indexed by (optionally scaled) register. | |
50 | ||
51 | ADDRESS_REG_UREG | |
52 | A base register indexed by (optionally scaled) zero-extended register. | |
53 | ||
54 | ADDRESS_REG_WB | |
55 | A base register indexed by immediate offset with writeback. | |
56 | ||
96ad6ab2 CM |
57 | ADDRESS_LO_SUM |
58 | A LO_SUM rtx. The first operand is a valid base register and | |
59 | the second operand is a symbolic address. | |
60 | ||
61 | ADDRESS_CONST_INT | |
62 | A signed 16-bit constant address. | |
63 | ||
64 | ADDRESS_SYMBOLIC: | |
65 | A constant symbolic address. */ | |
66 | enum riscv_address_type { | |
67 | ADDRESS_REG, | |
2d65622f CM |
68 | ADDRESS_REG_REG, |
69 | ADDRESS_REG_UREG, | |
70 | ADDRESS_REG_WB, | |
96ad6ab2 CM |
71 | ADDRESS_LO_SUM, |
72 | ADDRESS_CONST_INT, | |
73 | ADDRESS_SYMBOLIC | |
74 | }; | |
75 | ||
76 | /* Information about an address described by riscv_address_type. | |
77 | ||
78 | ADDRESS_CONST_INT | |
79 | No fields are used. | |
80 | ||
81 | ADDRESS_REG | |
82 | REG is the base register and OFFSET is the constant offset. | |
83 | ||
2d65622f CM |
84 | ADDRESS_REG_REG and ADDRESS_REG_UREG |
85 | REG is the base register and OFFSET is the index register. | |
86 | ||
87 | ADDRESS_REG_WB | |
88 | REG is the base register, OFFSET is the constant offset, and | |
89 | shift is the shift amount for the offset. | |
90 | ||
96ad6ab2 CM |
91 | ADDRESS_LO_SUM |
92 | REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE | |
93 | is the type of symbol it references. | |
94 | ||
95 | ADDRESS_SYMBOLIC | |
96 | SYMBOL_TYPE is the type of symbol that the address references. */ | |
97 | struct riscv_address_info { | |
98 | enum riscv_address_type type; | |
99 | rtx reg; | |
100 | rtx offset; | |
101 | enum riscv_symbol_type symbol_type; | |
2d65622f | 102 | int shift; |
96ad6ab2 CM |
103 | }; |
104 | ||
e53b6e56 | 105 | /* Routines implemented in riscv.cc. */ |
9a55cc62 | 106 | extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p); |
09cae750 PD |
107 | extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); |
108 | extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); | |
30699b99 | 109 | extern int riscv_float_const_rtx_index_for_fli (rtx); |
b8506a8a | 110 | extern int riscv_regno_mode_ok_for_base_p (int, machine_mode, bool); |
2d65622f | 111 | extern bool riscv_valid_base_register_p (rtx, machine_mode, bool); |
42360427 CM |
112 | extern enum reg_class riscv_index_reg_class (); |
113 | extern int riscv_regno_ok_for_index_p (int); | |
b8506a8a | 114 | extern int riscv_address_insns (rtx, machine_mode, bool); |
09cae750 PD |
115 | extern int riscv_const_insns (rtx); |
116 | extern int riscv_split_const_insns (rtx); | |
117 | extern int riscv_load_store_insns (rtx, rtx_insn *); | |
118 | extern rtx riscv_emit_move (rtx, rtx); | |
05302544 | 119 | extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *); |
09cae750 PD |
120 | extern bool riscv_split_symbol_type (enum riscv_symbol_type); |
121 | extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type); | |
05302544 | 122 | extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode); |
b8506a8a | 123 | extern bool riscv_legitimize_move (machine_mode, rtx, rtx); |
09cae750 PD |
124 | extern rtx riscv_subword (rtx, bool); |
125 | extern bool riscv_split_64bit_move_p (rtx, rtx); | |
126 | extern void riscv_split_doubleword_move (rtx, rtx); | |
127 | extern const char *riscv_output_move (rtx, rtx); | |
8cad5b14 | 128 | extern const char *riscv_output_return (); |
4abcc500 | 129 | extern void riscv_declare_function_name (FILE *, const char *, tree); |
5f110561 | 130 | extern void riscv_declare_function_size (FILE *, const char *, tree); |
4abcc500 LD |
131 | extern void riscv_asm_output_alias (FILE *, const tree, const tree); |
132 | extern void riscv_asm_output_external (FILE *, const tree, const char *); | |
3d1d3132 FG |
133 | extern bool |
134 | riscv_zcmp_valid_stack_adj_bytes_p (HOST_WIDE_INT, int); | |
0a5170b5 | 135 | extern void riscv_legitimize_poly_move (machine_mode, rtx, rtx, rtx); |
02fcaf41 | 136 | |
09cae750 | 137 | #ifdef RTX_CODE |
8ae83274 | 138 | extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool *invert_ptr = 0); |
9a1a2e98 MR |
139 | extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx, |
140 | bool *invert_ptr = nullptr); | |
09cae750 | 141 | extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx); |
4daeedcb | 142 | extern rtx riscv_emit_unary (enum rtx_code code, rtx dest, rtx x); |
99bfdb07 | 143 | extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y); |
09cae750 | 144 | #endif |
8e7ffe12 | 145 | extern bool riscv_expand_conditional_move (rtx, rtx, rtx, rtx); |
09cae750 PD |
146 | extern rtx riscv_legitimize_call_address (rtx); |
147 | extern void riscv_set_return_address (rtx, rtx); | |
09cae750 | 148 | extern rtx riscv_return_addr (int, rtx); |
3496ca4e | 149 | extern poly_int64 riscv_initial_elimination_offset (int, int); |
09cae750 | 150 | extern void riscv_expand_prologue (void); |
fd1e52dc | 151 | extern void riscv_expand_epilogue (int); |
d0ebdd9f | 152 | extern bool riscv_epilogue_uses (unsigned int); |
09cae750 | 153 | extern bool riscv_can_use_return_insn (void); |
6ed01e6b | 154 | extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode); |
88108b27 | 155 | extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *); |
d0e0c130 KC |
156 | extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *); |
157 | extern bool riscv_gpr_save_operation_p (rtx); | |
b4feb49c | 158 | extern void riscv_reinit (void); |
f556cd8b | 159 | extern poly_uint64 riscv_regmode_natural_size (machine_mode); |
7e924ba3 | 160 | extern bool riscv_v_ext_vector_mode_p (machine_mode); |
12847288 | 161 | extern bool riscv_v_ext_tuple_mode_p (machine_mode); |
33b153ff | 162 | extern bool riscv_v_ext_vls_mode_p (machine_mode); |
6ae5565e | 163 | extern int riscv_get_v_regno_alignment (machine_mode); |
787ac959 | 164 | extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); |
f797260a PN |
165 | extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); |
166 | extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); | |
942ab49b | 167 | extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); |
4bfc4585 | 168 | extern bool riscv_reg_frame_related (rtx); |
09cae750 | 169 | |
e53b6e56 | 170 | /* Routines implemented in riscv-c.cc. */ |
09cae750 | 171 | void riscv_cpu_cpp_builtins (cpp_reader *); |
7d935cdd | 172 | void riscv_register_pragmas (void); |
09cae750 | 173 | |
e53b6e56 | 174 | /* Routines implemented in riscv-builtins.cc. */ |
09cae750 | 175 | extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *); |
60bd33bc | 176 | extern bool riscv_gimple_fold_builtin (gimple_stmt_iterator *); |
b8506a8a | 177 | extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int); |
09cae750 PD |
178 | extern tree riscv_builtin_decl (unsigned int, bool); |
179 | extern void riscv_init_builtins (void); | |
180 | ||
e53b6e56 | 181 | /* Routines implemented in riscv-common.cc. */ |
f908b69c | 182 | extern std::string riscv_arch_str (bool version_p = true); |
b4feb49c | 183 | extern void riscv_parse_arch_string (const char *, struct gcc_options *, location_t); |
8e966210 | 184 | |
e0a5b313 KC |
185 | extern bool riscv_hard_regno_rename_ok (unsigned, unsigned); |
186 | ||
de6320a8 | 187 | rtl_opt_pass * make_pass_shorten_memrefs (gcc::context *ctxt); |
e37bc2cf | 188 | rtl_opt_pass * make_pass_avlprop (gcc::context *ctxt); |
9243c3d1 | 189 | rtl_opt_pass * make_pass_vsetvl (gcc::context *ctxt); |
de6320a8 | 190 | |
32874560 CM |
191 | /* Routines implemented in riscv-string.c. */ |
192 | extern bool riscv_expand_block_move (rtx, rtx, rtx); | |
54ba8d44 | 193 | extern bool riscv_expand_block_clear (rtx, rtx); |
32874560 | 194 | |
72eb8335 KC |
195 | /* Information about one CPU we know about. */ |
196 | struct riscv_cpu_info { | |
197 | /* This CPU's canonical name. */ | |
198 | const char *name; | |
199 | ||
200 | /* Default arch for this CPU, could be NULL if no default arch. */ | |
201 | const char *arch; | |
202 | ||
203 | /* Which automaton to use for tuning. */ | |
204 | const char *tune; | |
205 | }; | |
206 | ||
207 | extern const riscv_cpu_info *riscv_find_cpu (const char *); | |
208 | ||
5e0f67b8 JZ |
209 | /* Common vector costs in any kind of vectorization (e.g VLA and VLS). */ |
210 | struct common_vector_cost | |
211 | { | |
212 | /* Cost of any integer vector operation, excluding the ones handled | |
213 | specially below. */ | |
214 | const int int_stmt_cost; | |
215 | ||
216 | /* Cost of any fp vector operation, excluding the ones handled | |
217 | specially below. */ | |
218 | const int fp_stmt_cost; | |
219 | ||
220 | /* Gather/scatter vectorization cost. */ | |
221 | const int gather_load_cost; | |
222 | const int scatter_store_cost; | |
223 | ||
224 | /* Cost of a vector-to-scalar operation. */ | |
225 | const int vec_to_scalar_cost; | |
226 | ||
227 | /* Cost of a scalar-to-vector operation. */ | |
228 | const int scalar_to_vec_cost; | |
229 | ||
230 | /* Cost of a permute operation. */ | |
231 | const int permute_cost; | |
232 | ||
233 | /* Cost of an aligned vector load. */ | |
234 | const int align_load_cost; | |
235 | ||
236 | /* Cost of an aligned vector store. */ | |
237 | const int align_store_cost; | |
238 | ||
239 | /* Cost of an unaligned vector load. */ | |
240 | const int unalign_load_cost; | |
241 | ||
242 | /* Cost of an unaligned vector store. */ | |
243 | const int unalign_store_cost; | |
244 | }; | |
245 | ||
246 | /* scalable vectorization (VLA) specific cost. */ | |
247 | struct scalable_vector_cost : common_vector_cost | |
248 | { | |
249 | CONSTEXPR scalable_vector_cost (const common_vector_cost &base) | |
250 | : common_vector_cost (base) | |
251 | {} | |
252 | ||
253 | /* TODO: We will need more other kinds of vector cost for VLA. | |
254 | E.g. fold_left reduction cost, lanes load/store cost, ..., etc. */ | |
255 | }; | |
256 | ||
0acb6367 JZ |
257 | /* Additional costs for register copies. Cost is for one register. */ |
258 | struct regmove_vector_cost | |
259 | { | |
260 | const int GR2VR; | |
261 | const int FR2VR; | |
7be87b7d JZ |
262 | const int VR2GR; |
263 | const int VR2FR; | |
0acb6367 JZ |
264 | }; |
265 | ||
5e0f67b8 JZ |
266 | /* Cost for vector insn classes. */ |
267 | struct cpu_vector_cost | |
268 | { | |
269 | /* Cost of any integer scalar operation, excluding load and store. */ | |
270 | const int scalar_int_stmt_cost; | |
271 | ||
272 | /* Cost of any fp scalar operation, excluding load and store. */ | |
273 | const int scalar_fp_stmt_cost; | |
274 | ||
275 | /* Cost of a scalar load. */ | |
276 | const int scalar_load_cost; | |
277 | ||
278 | /* Cost of a scalar store. */ | |
279 | const int scalar_store_cost; | |
280 | ||
281 | /* Cost of a taken branch. */ | |
282 | const int cond_taken_branch_cost; | |
283 | ||
284 | /* Cost of a not-taken branch. */ | |
285 | const int cond_not_taken_branch_cost; | |
286 | ||
287 | /* Cost of an VLS modes operations. */ | |
288 | const common_vector_cost *vls; | |
289 | ||
290 | /* Cost of an VLA modes operations. */ | |
291 | const scalable_vector_cost *vla; | |
0acb6367 JZ |
292 | |
293 | /* Cost of vector register move operations. */ | |
294 | const regmove_vector_cost *regmove; | |
5e0f67b8 JZ |
295 | }; |
296 | ||
b4feb49c | 297 | /* Routines implemented in riscv-selftests.cc. */ |
298 | #if CHECKING_P | |
299 | namespace selftest { | |
3b6d44f4 | 300 | void riscv_run_selftests (void); |
b4feb49c | 301 | } // namespace selftest |
302 | #endif | |
303 | ||
7d935cdd | 304 | namespace riscv_vector { |
01260a82 | 305 | #define RVV_VLMAX regno_reg_rtx[X0_REGNUM] |
272e119d | 306 | #define RVV_VUNDEF(MODE) \ |
01260a82 | 307 | gen_rtx_UNSPEC (MODE, gen_rtvec (1, RVV_VLMAX), UNSPEC_VUNDEF) |
b3176bdc | 308 | |
79ab19bc LD |
309 | /* These flags describe how to pass the operands to a rvv insn pattern. |
310 | e.g.: | |
311 | If a insn has this flags: | |
312 | HAS_DEST_P | HAS_MASK_P | USE_VUNDEF_MERGE_P | |
313 | | TU_POLICY_P | BINARY_OP_P | FRM_DYN_P | |
314 | that means: | |
315 | operands[0] is the dest operand | |
316 | operands[1] is the mask operand | |
317 | operands[2] is the merge operand | |
318 | operands[3] and operands[4] is the two operand to do the operation. | |
319 | operands[5] is the vl operand | |
320 | operands[6] is the tail policy operand | |
321 | operands[7] is the mask policy operands | |
322 | operands[8] is the rounding mode operands | |
323 | ||
324 | Then you can call `emit_vlmax_insn (flags, icode, ops)` to emit a insn. | |
325 | and ops[0] is the dest operand (operands[0]), ops[1] is the mask | |
326 | operand (operands[1]), ops[2] and ops[3] is the two | |
327 | operands (operands[3], operands[4]) to do the operation. Other operands | |
328 | will be created by emit_vlmax_insn according to the flags information. | |
329 | */ | |
330 | enum insn_flags : unsigned int | |
51fd69ec | 331 | { |
79ab19bc LD |
332 | /* flags for dest, mask, merge operands. */ |
333 | /* Means INSN has dest operand. False for STORE insn. */ | |
334 | HAS_DEST_P = 1 << 0, | |
335 | /* Means INSN has mask operand. */ | |
336 | HAS_MASK_P = 1 << 1, | |
337 | /* Means using ALL_TRUES for mask operand. */ | |
338 | USE_ALL_TRUES_MASK_P = 1 << 2, | |
339 | /* Means using ONE_TRUE for mask operand. */ | |
340 | USE_ONE_TRUE_MASK_P = 1 << 3, | |
341 | /* Means INSN has merge operand. */ | |
342 | HAS_MERGE_P = 1 << 4, | |
343 | /* Means using VUNDEF for merge operand. */ | |
344 | USE_VUNDEF_MERGE_P = 1 << 5, | |
345 | ||
346 | /* flags for tail policy and mask plicy operands. */ | |
347 | /* Means the tail policy is TAIL_UNDISTURBED. */ | |
348 | TU_POLICY_P = 1 << 6, | |
349 | /* Means the tail policy is default (return by get_prefer_tail_policy). */ | |
350 | TDEFAULT_POLICY_P = 1 << 7, | |
351 | /* Means the mask policy is MASK_UNDISTURBED. */ | |
352 | MU_POLICY_P = 1 << 8, | |
353 | /* Means the mask policy is default (return by get_prefer_mask_policy). */ | |
354 | MDEFAULT_POLICY_P = 1 << 9, | |
355 | ||
356 | /* flags for the number operands to do the operation. */ | |
357 | /* Means INSN need zero operand to do the operation. e.g. vid.v */ | |
358 | NULLARY_OP_P = 1 << 10, | |
359 | /* Means INSN need one operand to do the operation. */ | |
360 | UNARY_OP_P = 1 << 11, | |
361 | /* Means INSN need two operands to do the operation. */ | |
362 | BINARY_OP_P = 1 << 12, | |
363 | /* Means INSN need two operands to do the operation. */ | |
364 | TERNARY_OP_P = 1 << 13, | |
365 | ||
dd6e5d29 LD |
366 | /* flags for get vtype mode from the index number. default from dest operand. */ |
367 | VTYPE_MODE_FROM_OP1_P = 1 << 14, | |
79ab19bc LD |
368 | |
369 | /* flags for the floating-point rounding mode. */ | |
370 | /* Means INSN has FRM operand and the value is FRM_DYN. */ | |
371 | FRM_DYN_P = 1 << 15, | |
8bf5636e PL |
372 | |
373 | /* Means INSN has FRM operand and the value is FRM_RUP. */ | |
374 | FRM_RUP_P = 1 << 16, | |
83441e75 PL |
375 | |
376 | /* Means INSN has FRM operand and the value is FRM_RDN. */ | |
377 | FRM_RDN_P = 1 << 17, | |
d324984f PL |
378 | |
379 | /* Means INSN has FRM operand and the value is FRM_RMM. */ | |
380 | FRM_RMM_P = 1 << 18, | |
fcbbf158 PL |
381 | |
382 | /* Means INSN has FRM operand and the value is FRM_RNE. */ | |
383 | FRM_RNE_P = 1 << 19, | |
0141ee79 JZ |
384 | |
385 | /* Means INSN has VXRM operand and the value is VXRM_RNU. */ | |
386 | VXRM_RNU_P = 1 << 20, | |
387 | ||
388 | /* Means INSN has VXRM operand and the value is VXRM_RDN. */ | |
389 | VXRM_RDN_P = 1 << 21, | |
51fd69ec | 390 | }; |
79ab19bc LD |
391 | |
392 | enum insn_type : unsigned int | |
393 | { | |
394 | /* some flags macros. */ | |
395 | /* For non-mask insn with tama. */ | |
396 | __NORMAL_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
397 | | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P, | |
398 | /* For non-mask insn with ta, without mask policy operand. */ | |
399 | __NORMAL_OP_TA = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
400 | | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P, | |
401 | /* For non-mask insn with ta, without mask operand and mask policy operand. */ | |
402 | __NORMAL_OP_TA2 | |
403 | = HAS_DEST_P | HAS_MERGE_P | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P, | |
404 | /* For non-mask insn with ma, without tail policy operand. */ | |
405 | __NORMAL_OP_MA = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
406 | | USE_VUNDEF_MERGE_P | MDEFAULT_POLICY_P, | |
407 | /* For mask insn with tama. */ | |
408 | __MASK_OP_TAMA = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | USE_VUNDEF_MERGE_P | |
409 | | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P, | |
410 | /* For mask insn with tamu. */ | |
411 | __MASK_OP_TAMU | |
412 | = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | TDEFAULT_POLICY_P | MU_POLICY_P, | |
413 | /* For mask insn with tuma. */ | |
414 | __MASK_OP_TUMA = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
415 | | TU_POLICY_P | MDEFAULT_POLICY_P, | |
416 | /* For mask insn with mu. */ | |
417 | __MASK_OP_MU = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | MU_POLICY_P, | |
418 | /* For mask insn with ta, without mask policy operand. */ | |
419 | __MASK_OP_TA = HAS_DEST_P | HAS_MASK_P | HAS_MERGE_P | USE_VUNDEF_MERGE_P | |
420 | | TDEFAULT_POLICY_P, | |
421 | ||
422 | /* Nullary operator. e.g. vid.v */ | |
423 | NULLARY_OP = __NORMAL_OP | NULLARY_OP_P, | |
424 | ||
425 | /* Unary operator. */ | |
426 | UNARY_OP = __NORMAL_OP | UNARY_OP_P, | |
427 | UNARY_OP_TAMA = __MASK_OP_TAMA | UNARY_OP_P, | |
428 | UNARY_OP_TAMU = __MASK_OP_TAMU | UNARY_OP_P, | |
429 | UNARY_OP_FRM_DYN = UNARY_OP | FRM_DYN_P, | |
2cc4f58a | 430 | UNARY_OP_FRM_RMM = UNARY_OP | FRM_RMM_P, |
51f7bfaa | 431 | UNARY_OP_FRM_RUP = UNARY_OP | FRM_RUP_P, |
8f52040e | 432 | UNARY_OP_FRM_RDN = UNARY_OP | FRM_RDN_P, |
85858c71 PL |
433 | UNARY_OP_TAMA_FRM_DYN = UNARY_OP_TAMA | FRM_DYN_P, |
434 | UNARY_OP_TAMA_FRM_RUP = UNARY_OP_TAMA | FRM_RUP_P, | |
435 | UNARY_OP_TAMA_FRM_RDN = UNARY_OP_TAMA | FRM_RDN_P, | |
436 | UNARY_OP_TAMA_FRM_RMM = UNARY_OP_TAMA | FRM_RMM_P, | |
437 | UNARY_OP_TAMA_FRM_RNE = UNARY_OP_TAMA | FRM_RNE_P, | |
e2023d2d | 438 | UNARY_OP_TAMU_FRM_DYN = UNARY_OP_TAMU | FRM_DYN_P, |
8bf5636e | 439 | UNARY_OP_TAMU_FRM_RUP = UNARY_OP_TAMU | FRM_RUP_P, |
83441e75 | 440 | UNARY_OP_TAMU_FRM_RDN = UNARY_OP_TAMU | FRM_RDN_P, |
d324984f | 441 | UNARY_OP_TAMU_FRM_RMM = UNARY_OP_TAMU | FRM_RMM_P, |
fcbbf158 | 442 | UNARY_OP_TAMU_FRM_RNE = UNARY_OP_TAMU | FRM_RNE_P, |
79ab19bc LD |
443 | |
444 | /* Binary operator. */ | |
445 | BINARY_OP = __NORMAL_OP | BINARY_OP_P, | |
446 | BINARY_OP_TAMA = __MASK_OP_TAMA | BINARY_OP_P, | |
447 | BINARY_OP_TAMU = __MASK_OP_TAMU | BINARY_OP_P, | |
448 | BINARY_OP_TUMA = __MASK_OP_TUMA | BINARY_OP_P, | |
449 | BINARY_OP_FRM_DYN = BINARY_OP | FRM_DYN_P, | |
0141ee79 JZ |
450 | BINARY_OP_VXRM_RNU = BINARY_OP | VXRM_RNU_P, |
451 | BINARY_OP_VXRM_RDN = BINARY_OP | VXRM_RDN_P, | |
79ab19bc LD |
452 | |
453 | /* Ternary operator. Always have real merge operand. */ | |
454 | TERNARY_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
455 | | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | TERNARY_OP_P, | |
456 | TERNARY_OP_FRM_DYN = TERNARY_OP | FRM_DYN_P, | |
457 | ||
458 | /* For vwmacc, no merge operand. */ | |
459 | WIDEN_TERNARY_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | |
460 | | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | TERNARY_OP_P, | |
461 | WIDEN_TERNARY_OP_FRM_DYN = WIDEN_TERNARY_OP | FRM_DYN_P, | |
462 | ||
463 | /* For vmerge, no mask operand, no mask policy operand. */ | |
464 | MERGE_OP = __NORMAL_OP_TA2 | TERNARY_OP_P, | |
465 | ||
0c42741a RD |
466 | /* For vmerge with TU policy. */ |
467 | MERGE_OP_TU = HAS_DEST_P | HAS_MERGE_P | TERNARY_OP_P | TU_POLICY_P, | |
468 | ||
79ab19bc LD |
469 | /* For vm<compare>, no tail policy operand. */ |
470 | COMPARE_OP = __NORMAL_OP_MA | TERNARY_OP_P, | |
471 | COMPARE_OP_MU = __MASK_OP_MU | TERNARY_OP_P, | |
472 | ||
473 | /* For scatter insn: no dest operand, no merge operand, no tail and mask | |
474 | policy operands. */ | |
475 | SCATTER_OP_M = HAS_MASK_P | TERNARY_OP_P, | |
476 | ||
477 | /* For vcpop.m, no merge operand, no tail and mask policy operands. */ | |
478 | CPOP_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | UNARY_OP_P | |
dd6e5d29 | 479 | | VTYPE_MODE_FROM_OP1_P, |
79ab19bc LD |
480 | |
481 | /* For mask instrunctions, no tail and mask policy operands. */ | |
482 | UNARY_MASK_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
483 | | USE_VUNDEF_MERGE_P | UNARY_OP_P, | |
484 | BINARY_MASK_OP = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | HAS_MERGE_P | |
485 | | USE_VUNDEF_MERGE_P | BINARY_OP_P, | |
486 | ||
487 | /* For vcompress.vm */ | |
488 | COMPRESS_OP = __NORMAL_OP_TA2 | BINARY_OP_P, | |
489 | /* has merge operand but use ta. */ | |
490 | COMPRESS_OP_MERGE | |
491 | = HAS_DEST_P | HAS_MERGE_P | TDEFAULT_POLICY_P | BINARY_OP_P, | |
492 | ||
6aaf72ff JZ |
493 | /* For vslideup.up has merge operand but use ta. */ |
494 | SLIDEUP_OP_MERGE = HAS_DEST_P | HAS_MASK_P | USE_ALL_TRUES_MASK_P | |
495 | | HAS_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | |
496 | | BINARY_OP_P, | |
497 | ||
79ab19bc | 498 | /* For vreduce, no mask policy operand. */ |
dd6e5d29 | 499 | REDUCE_OP = __NORMAL_OP_TA | BINARY_OP_P | VTYPE_MODE_FROM_OP1_P, |
5bc8c83d | 500 | REDUCE_OP_M = __MASK_OP_TA | BINARY_OP_P | VTYPE_MODE_FROM_OP1_P, |
dd6e5d29 | 501 | REDUCE_OP_FRM_DYN = REDUCE_OP | FRM_DYN_P | VTYPE_MODE_FROM_OP1_P, |
79ab19bc | 502 | REDUCE_OP_M_FRM_DYN |
dd6e5d29 | 503 | = __MASK_OP_TA | BINARY_OP_P | FRM_DYN_P | VTYPE_MODE_FROM_OP1_P, |
79ab19bc LD |
504 | |
505 | /* For vmv.s.x/vfmv.s.f. */ | |
506 | SCALAR_MOVE_OP = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P | HAS_MERGE_P | |
507 | | USE_VUNDEF_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | |
508 | | UNARY_OP_P, | |
28f16f6d PL |
509 | |
510 | SCALAR_MOVE_MERGED_OP = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P | |
511 | | HAS_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P | |
512 | | UNARY_OP_P, | |
79ab19bc LD |
513 | }; |
514 | ||
3b16afeb JZZ |
515 | enum vlmul_type |
516 | { | |
517 | LMUL_1 = 0, | |
518 | LMUL_2 = 1, | |
519 | LMUL_4 = 2, | |
520 | LMUL_8 = 3, | |
521 | LMUL_RESERVED = 4, | |
522 | LMUL_F8 = 5, | |
523 | LMUL_F4 = 6, | |
524 | LMUL_F2 = 7, | |
ec99ffab | 525 | NUM_LMUL = 8 |
3b16afeb | 526 | }; |
9243c3d1 | 527 | |
e99cdab8 LD |
528 | /* The RISC-V vsetvli pass uses "known vlmax" operations for optimization. |
529 | Whether or not an instruction actually is a vlmax operation is not | |
530 | recognizable from the length operand alone but the avl_type operand | |
531 | is used instead. In general, there are two cases: | |
532 | ||
533 | - Emit a vlmax operation by calling emit_vlmax_insn[_lra]. Here we emit | |
534 | a vsetvli with vlmax configuration and set the avl_type to VLMAX for | |
535 | VLA modes or VLS for VLS modes. | |
536 | - Emit an operation that uses the existing (last-set) length and | |
537 | set the avl_type to NONVLMAX. | |
538 | ||
539 | Sometimes we also need to set the VLMAX or VLS avl_type to an operation that | |
540 | already uses a given length register. This can happen during or after | |
541 | register allocation when we are not allowed to create a new register. | |
542 | For that case we also allow to set the avl_type to VLMAX or VLS. | |
543 | */ | |
9243c3d1 JZZ |
544 | enum avl_type |
545 | { | |
e99cdab8 LD |
546 | NONVLMAX = 0, |
547 | VLMAX = 1, | |
548 | VLS = 2, | |
9243c3d1 | 549 | }; |
7d935cdd | 550 | /* Routines implemented in riscv-vector-builtins.cc. */ |
3b6d44f4 | 551 | void init_builtins (void); |
af3a9807 | 552 | void reinit_builtins (void); |
3b6d44f4 | 553 | const char *mangle_builtin_type (const_tree); |
509c10a6 | 554 | tree lookup_vector_type_attribute (const_tree); |
94a4b932 | 555 | bool builtin_type_p (const_tree); |
7d935cdd | 556 | #ifdef GCC_TARGET_H |
3b6d44f4 | 557 | bool verify_type_context (location_t, type_context_kind, const_tree, bool); |
631e86b7 JZ |
558 | bool expand_vec_perm_const (machine_mode, machine_mode, rtx, rtx, rtx, |
559 | const vec_perm_indices &); | |
7d935cdd | 560 | #endif |
3b6d44f4 JZZ |
561 | void handle_pragma_vector (void); |
562 | tree builtin_decl (unsigned, bool); | |
60bd33bc | 563 | gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *); |
3b6d44f4 | 564 | rtx expand_builtin (unsigned int, tree, rtx); |
7caa1ae5 JZZ |
565 | bool check_builtin_call (location_t, vec<location_t>, unsigned int, |
566 | tree, unsigned int, tree *); | |
db5c3f6d | 567 | tree resolve_overloaded_builtin (location_t, unsigned int, tree, vec<tree, va_gc> *); |
3b6d44f4 | 568 | bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT); |
f416a3fd | 569 | bool legitimize_move (rtx, rtx *); |
cd0c433e | 570 | void emit_vlmax_vsetvl (machine_mode, rtx); |
40fc8e3d | 571 | void emit_hard_vlmax_vsetvl (machine_mode, rtx); |
79ab19bc LD |
572 | void emit_vlmax_insn (unsigned, unsigned, rtx *); |
573 | void emit_nonvlmax_insn (unsigned, unsigned, rtx *, rtx); | |
574 | void emit_vlmax_insn_lra (unsigned, unsigned, rtx *, rtx); | |
3b6d44f4 | 575 | enum vlmul_type get_vlmul (machine_mode); |
b3176bdc | 576 | rtx get_vlmax_rtx (machine_mode); |
3b6d44f4 | 577 | unsigned int get_ratio (machine_mode); |
12847288 JZZ |
578 | unsigned int get_nf (machine_mode); |
579 | machine_mode get_subpart_mode (machine_mode); | |
3b6d44f4 JZZ |
580 | int get_ta (rtx); |
581 | int get_ma (rtx); | |
582 | int get_avl_type (rtx); | |
583 | unsigned int calculate_ratio (unsigned int, enum vlmul_type); | |
f556cd8b JZZ |
584 | enum tail_policy |
585 | { | |
586 | TAIL_UNDISTURBED = 0, | |
587 | TAIL_AGNOSTIC = 1, | |
9243c3d1 | 588 | TAIL_ANY = 2, |
f556cd8b JZZ |
589 | }; |
590 | ||
591 | enum mask_policy | |
592 | { | |
593 | MASK_UNDISTURBED = 0, | |
594 | MASK_AGNOSTIC = 1, | |
9243c3d1 | 595 | MASK_ANY = 2, |
f556cd8b | 596 | }; |
8390a2af | 597 | |
e69d050f LD |
598 | /* Return true if VALUE is agnostic or any policy. */ |
599 | #define IS_AGNOSTIC(VALUE) (bool) (VALUE & 0x1 || (VALUE >> 1 & 0x1)) | |
600 | ||
9243c3d1 JZZ |
601 | enum tail_policy get_prefer_tail_policy (); |
602 | enum mask_policy get_prefer_mask_policy (); | |
a143c3f7 | 603 | rtx get_avl_type_rtx (enum avl_type); |
6c9bcb6c | 604 | opt_machine_mode get_vector_mode (scalar_mode, poly_uint64); |
12847288 | 605 | opt_machine_mode get_tuple_mode (machine_mode, unsigned int); |
3b6d44f4 JZZ |
606 | bool simm5_p (rtx); |
607 | bool neg_simm5_p (rtx); | |
a035d133 | 608 | #ifdef RTX_CODE |
3b6d44f4 | 609 | bool has_vi_variant_p (rtx_code, rtx); |
1cd8254e | 610 | void expand_vec_cmp (rtx, rtx_code, rtx, rtx, rtx = nullptr, rtx = nullptr); |
e0600a02 | 611 | bool expand_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); |
4d1c8b04 LD |
612 | void expand_cond_len_unop (unsigned, rtx *); |
613 | void expand_cond_len_binop (unsigned, rtx *); | |
e6413b5d | 614 | void expand_reduction (unsigned, unsigned, rtx *, rtx); |
8bf5636e | 615 | void expand_vec_ceil (rtx, rtx, machine_mode, machine_mode); |
83441e75 | 616 | void expand_vec_floor (rtx, rtx, machine_mode, machine_mode); |
e2023d2d | 617 | void expand_vec_nearbyint (rtx, rtx, machine_mode, machine_mode); |
e4cf5f54 | 618 | void expand_vec_rint (rtx, rtx, machine_mode, machine_mode); |
d324984f | 619 | void expand_vec_round (rtx, rtx, machine_mode, machine_mode); |
1c4ca595 | 620 | void expand_vec_trunc (rtx, rtx, machine_mode, machine_mode); |
fcbbf158 | 621 | void expand_vec_roundeven (rtx, rtx, machine_mode, machine_mode); |
5dfa501d PL |
622 | void expand_vec_lrint (rtx, rtx, machine_mode, machine_mode, machine_mode); |
623 | void expand_vec_lround (rtx, rtx, machine_mode, machine_mode, machine_mode); | |
51f7bfaa | 624 | void expand_vec_lceil (rtx, rtx, machine_mode, machine_mode); |
8f52040e | 625 | void expand_vec_lfloor (rtx, rtx, machine_mode, machine_mode); |
a035d133 | 626 | #endif |
51fd69ec | 627 | bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, |
eb1cdb3e | 628 | bool, void (*)(rtx *, rtx), enum avl_type); |
ec99ffab | 629 | rtx gen_scalar_move_mask (machine_mode); |
9c032218 | 630 | rtx gen_no_side_effects_vsetvl_rtx (machine_mode, rtx, rtx); |
1bff101b JZZ |
631 | |
632 | /* RVV vector register sizes. | |
633 | TODO: Currently, we only add RVV_32/RVV_64/RVV_128, we may need to | |
634 | support other values in the future. */ | |
635 | enum vlen_enum | |
636 | { | |
637 | RVV_32 = 32, | |
638 | RVV_64 = 64, | |
639 | RVV_65536 = 65536 | |
640 | }; | |
641 | bool slide1_sew64_helper (int, machine_mode, machine_mode, | |
642 | machine_mode, rtx *); | |
db4f7a9b | 643 | rtx gen_avl_for_scalar_move (rtx); |
51fd69ec | 644 | void expand_tuple_move (rtx *); |
9464e72b | 645 | bool expand_block_move (rtx, rtx, rtx); |
2d76f2b4 | 646 | machine_mode preferred_simd_mode (scalar_mode); |
1349f530 | 647 | machine_mode get_mask_mode (machine_mode); |
71a5ac67 | 648 | void expand_vec_series (rtx, rtx, rtx, rtx = 0); |
1c1a9d8e | 649 | void expand_vec_init (rtx, rtx); |
2418cdfc | 650 | void expand_vec_perm (rtx, rtx, rtx, rtx); |
55dcf277 | 651 | void expand_select_vl (rtx *); |
d42d199e | 652 | void expand_load_store (rtx *, bool); |
f048af2a | 653 | void expand_gather_scatter (rtx *, bool); |
0d2673e9 | 654 | void expand_cond_len_ternop (unsigned, rtx *); |
95d2ce05 | 655 | void prepare_ternary_operands (rtx *); |
fe578886 | 656 | void expand_lanes_load_store (rtx *, bool); |
e7545cad | 657 | void expand_fold_extract_last (rtx *); |
8a87ba0b JZ |
658 | void expand_cond_unop (unsigned, rtx *); |
659 | void expand_cond_binop (unsigned, rtx *); | |
660 | void expand_cond_ternop (unsigned, rtx *); | |
82bbbb73 | 661 | void expand_popcount (rtx *); |
2664964b | 662 | void expand_rawmemchr (machine_mode, rtx, rtx, rtx, bool = false); |
d468718c | 663 | bool expand_strcmp (rtx, rtx, rtx, rtx, unsigned HOST_WIDE_INT, bool); |
0a5170b5 | 664 | void emit_vec_extract (rtx, rtx, rtx); |
47ffabaf | 665 | |
5ed88078 | 666 | /* Rounding mode bitfield for fixed point VXRM. */ |
47ffabaf | 667 | enum fixed_point_rounding_mode |
5ed88078 JZ |
668 | { |
669 | VXRM_RNU, | |
670 | VXRM_RNE, | |
671 | VXRM_RDN, | |
672 | VXRM_ROD | |
673 | }; | |
47ffabaf | 674 | |
7f4644f8 PL |
675 | /* Rounding mode bitfield for floating point FRM. The value of enum comes |
676 | from the below link. | |
677 | https://github.com/riscv/riscv-isa-manual/blob/main/src/f-st-ext.adoc#floating-point-control-and-status-register | |
678 | */ | |
47ffabaf | 679 | enum floating_point_rounding_mode |
8cd140d3 | 680 | { |
7f4644f8 PL |
681 | FRM_RNE = 0, /* Aka 0b000. */ |
682 | FRM_RTZ = 1, /* Aka 0b001. */ | |
683 | FRM_RDN = 2, /* Aka 0b010. */ | |
684 | FRM_RUP = 3, /* Aka 0b011. */ | |
685 | FRM_RMM = 4, /* Aka 0b100. */ | |
686 | FRM_DYN = 7, /* Aka 0b111. */ | |
4d1e97f5 PL |
687 | FRM_STATIC_MIN = FRM_RNE, |
688 | FRM_STATIC_MAX = FRM_RMM, | |
4cede0de PL |
689 | FRM_DYN_EXIT = 8, |
690 | FRM_DYN_CALL = 9, | |
691 | FRM_NONE = 10, | |
8cd140d3 | 692 | }; |
25907509 | 693 | |
4cede0de | 694 | enum floating_point_rounding_mode get_frm_mode (rtx); |
25907509 RD |
695 | opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode, |
696 | poly_uint64); | |
697 | unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool); | |
d05aac04 JZ |
698 | bool cmp_lmul_le_one (machine_mode); |
699 | bool cmp_lmul_gt_one (machine_mode); | |
66c26e5c | 700 | bool vls_mode_valid_p (machine_mode); |
5e714992 | 701 | bool vlmax_avl_type_p (rtx_insn *); |
8064e7e2 JZ |
702 | bool has_vl_op (rtx_insn *); |
703 | bool tail_agnostic_p (rtx_insn *); | |
704 | void validate_change_or_fail (rtx, rtx *, rtx, bool); | |
705 | bool nonvlmax_avl_type_p (rtx_insn *); | |
706 | bool vlmax_avl_p (rtx); | |
707 | uint8_t get_sew (rtx_insn *); | |
708 | enum vlmul_type get_vlmul (rtx_insn *); | |
709 | int count_regno_occurrences (rtx_insn *, unsigned int); | |
5ea3c039 | 710 | bool imm_avl_p (machine_mode); |
418bd642 | 711 | bool can_be_broadcasted_p (rtx); |
8b93a0f3 | 712 | bool gather_scatter_valid_offset_p (machine_mode); |
fda2e1ab | 713 | HOST_WIDE_INT estimated_poly_value (poly_int64, unsigned int); |
9873f13d | 714 | bool whole_reg_to_reg_move_p (rtx *, machine_mode, int); |
f9df0034 | 715 | bool splat_to_scalar_move_p (rtx *); |
f652a358 | 716 | rtx get_fp_rounding_coefficient (machine_mode); |
7d935cdd JZZ |
717 | } |
718 | ||
cbd50570 JZZ |
719 | /* We classify builtin types into two classes: |
720 | 1. General builtin class which is defined in riscv_builtins. | |
721 | 2. Vector builtin class which is a special builtin architecture | |
722 | that implement intrinsic short into "pragma". */ | |
723 | enum riscv_builtin_class | |
724 | { | |
725 | RISCV_BUILTIN_GENERAL, | |
726 | RISCV_BUILTIN_VECTOR | |
727 | }; | |
728 | ||
729 | const unsigned int RISCV_BUILTIN_SHIFT = 1; | |
730 | ||
731 | /* Mask that selects the riscv_builtin_class part of a function code. */ | |
732 | const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1; | |
733 | ||
df48285b | 734 | /* Routines implemented in riscv-string.cc. */ |
949f1ccf | 735 | extern bool riscv_expand_strcmp (rtx, rtx, rtx, rtx, rtx); |
df48285b CM |
736 | extern bool riscv_expand_strlen (rtx, rtx, rtx, rtx); |
737 | ||
02fcaf41 | 738 | /* Routines implemented in thead.cc. */ |
c177f28d | 739 | extern bool extract_base_offset_in_addr (rtx, rtx *, rtx *); |
02fcaf41 CM |
740 | extern bool th_mempair_operands_p (rtx[4], bool, machine_mode); |
741 | extern void th_mempair_order_operands (rtx[4], bool, machine_mode); | |
742 | extern void th_mempair_prepare_save_restore_operands (rtx[4], bool, | |
743 | machine_mode, | |
744 | int, HOST_WIDE_INT, | |
745 | int, HOST_WIDE_INT); | |
746 | extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode); | |
52e809d5 JM |
747 | extern unsigned int th_int_get_mask (unsigned int); |
748 | extern unsigned int th_int_get_save_adjustment (void); | |
749 | extern rtx th_int_adjust_cfi_prologue (unsigned int); | |
9a55cc62 | 750 | extern const char *th_asm_output_opcode (FILE *asm_out_file, const char *p); |
02fcaf41 CM |
751 | #ifdef RTX_CODE |
752 | extern const char* | |
753 | th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); | |
2d65622f CM |
754 | extern bool th_memidx_legitimate_modify_p (rtx); |
755 | extern bool th_memidx_legitimate_modify_p (rtx, bool); | |
756 | extern bool th_memidx_legitimate_index_p (rtx); | |
757 | extern bool th_memidx_legitimate_index_p (rtx, bool); | |
758 | extern bool th_classify_address (struct riscv_address_info *, | |
759 | rtx, machine_mode, bool); | |
760 | extern const char *th_output_move (rtx, rtx); | |
761 | extern bool th_print_operand_address (FILE *, machine_mode, rtx); | |
02fcaf41 CM |
762 | #endif |
763 | ||
065be0ff | 764 | extern bool riscv_use_divmod_expander (void); |
1d4d302a | 765 | void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int); |
5f110561 KC |
766 | extern bool |
767 | riscv_option_valid_attribute_p (tree, tree, tree, int); | |
768 | extern void | |
769 | riscv_override_options_internal (struct gcc_options *); | |
af3a9807 | 770 | extern void riscv_option_override (void); |
5f110561 KC |
771 | |
772 | struct riscv_tune_param; | |
773 | /* Information about one micro-arch we know about. */ | |
774 | struct riscv_tune_info { | |
775 | /* This micro-arch canonical name. */ | |
776 | const char *name; | |
777 | ||
778 | /* Which automaton to use for tuning. */ | |
779 | enum riscv_microarchitecture_type microarchitecture; | |
780 | ||
781 | /* Tuning parameters for this micro-arch. */ | |
782 | const struct riscv_tune_param *tune_param; | |
783 | }; | |
784 | ||
785 | const struct riscv_tune_info * | |
786 | riscv_parse_tune (const char *, bool); | |
0acb6367 | 787 | const cpu_vector_cost *get_vector_costs (); |
1d4d302a | 788 | |
7af0f1e1 KC |
789 | enum |
790 | { | |
791 | RISCV_MAJOR_VERSION_BASE = 1000000, | |
792 | RISCV_MINOR_VERSION_BASE = 1000, | |
793 | RISCV_REVISION_VERSION_BASE = 1, | |
794 | }; | |
795 | ||
09cae750 | 796 | #endif /* ! GCC_RISCV_PROTOS_H */ |