[thirdparty/gcc.git] / gcc / config / rs6000 / dfp.md

;; Decimal Floating Point (DFP) patterns.
;; Copyright (C) 2007-2024 Free Software Foundation, Inc.
;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
;; (bergner@vnet.ibm.com).

;; This file is part of GCC.

;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published
;; by the Free Software Foundation; either version 3, or (at your
;; option) any later version.

;; GCC is distributed in the hope that it will be useful, but WITHOUT
;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
;; License for more details.

;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

;;
;; UNSPEC usage
;;

(define_c_enum "unspec"
  [UNSPEC_MOVSD_LOAD
   UNSPEC_MOVSD_STORE
  ])

; Either of the two decimal modes.
(define_mode_iterator DDTD [DD TD])

(define_mode_attr q [(DD "") (TD "q")])


(define_insn "movsd_store"
  [(set (match_operand:DD 0 "nonimmediate_operand" "=m")
	(unspec:DD [(match_operand:SD 1 "input_operand" "d")]
		   UNSPEC_MOVSD_STORE))]
  "(gpc_reg_operand (operands[0], DDmode)
   || gpc_reg_operand (operands[1], SDmode))
   && TARGET_HARD_FLOAT"
  "stfd%U0%X0 %1,%0"
  [(set_attr "type" "fpstore")])

(define_insn "movsd_load"
  [(set (match_operand:SD 0 "nonimmediate_operand" "=f")
	(unspec:SD [(match_operand:DD 1 "input_operand" "m")]
		   UNSPEC_MOVSD_LOAD))]
  "(gpc_reg_operand (operands[0], SDmode)
   || gpc_reg_operand (operands[1], DDmode))
   && TARGET_HARD_FLOAT"
  "lfd%U1%X1 %0,%1"
  [(set_attr "type" "fpload")])

;; Hardware support for decimal floating point operations.

(define_insn "extendsddd2"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
  "TARGET_DFP"
  "dctdp %0,%1"
  [(set_attr "type" "dfp")])

(define_expand "extendsdtd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
{
  rtx tmp = gen_reg_rtx (DDmode);
  emit_insn (gen_extendsddd2 (tmp, operands[1]));
  emit_insn (gen_extendddtd2 (operands[0], tmp));
  DONE;
})

(define_insn "truncddsd2"
  [(set (match_operand:SD 0 "gpc_reg_operand" "=f")
	(float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "drsp %0,%1"
  [(set_attr "type" "dfp")])

(define_insn "negdd2"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
  "TARGET_HARD_FLOAT"
  "fneg %0,%1"
  [(set_attr "type" "fpsimple")])

(define_insn "absdd2"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
  "TARGET_HARD_FLOAT"
  "fabs %0,%1"
  [(set_attr "type" "fpsimple")])

(define_insn "*nabsdd2_fpr"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
  "TARGET_HARD_FLOAT"
  "fnabs %0,%1"
  [(set_attr "type" "fpsimple")])

(define_insn "negtd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
	(neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
  "TARGET_HARD_FLOAT"
  "@
   fneg %0,%1
   fneg %0,%1\;fmr %L0,%L1"
  [(set_attr "type" "fpsimple")
   (set_attr "length" "4,8")])

(define_insn "abstd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
	(abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
  "TARGET_HARD_FLOAT"
  "@
   fabs %0,%1
   fabs %0,%1\;fmr %L0,%L1"
  [(set_attr "type" "fpsimple")
   (set_attr "length" "4,8")])

(define_insn "*nabstd2_fpr"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
	(neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]
  "TARGET_HARD_FLOAT"
  "@
   fnabs %0,%1
   fnabs %0,%1\;fmr %L0,%L1"
  [(set_attr "type" "fpsimple")
   (set_attr "length" "4,8")])

;; Hardware support for decimal floating point operations.

(define_insn "extendddtd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dctqpq %0,%1"
  [(set_attr "type" "dfp")
   (set_attr "size" "128")])

;; The result of drdpq is an even/odd register pair with the converted
;; value in the even register and zero in the odd register.
;; FIXME: Avoid the register move by using a reload constraint to ensure
;; that the result is the first of the pair receiving the result of drdpq.

(define_insn "trunctddd2"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d")))
   (clobber (match_scratch:TD 2 "=d"))]
  "TARGET_DFP"
  "drdpq %2,%1\;fmr %0,%2"
  [(set_attr "type" "dfp")
   (set_attr "size" "128")
   (set_attr "length" "8")])

(define_insn "trunctdsd2"
  [(set (match_operand:SD 0 "gpc_reg_operand" "=d,d")
	(float_truncate:SD (match_operand:TD 1 "gpc_reg_operand" "d,d")))
   (clobber (match_scratch:TD 2 "=&d,&d"))
   (clobber (match_scratch:DF 3 "=&d,&d"))]
  "TARGET_DFP"
  "@
   mffscdrni %3,7\;drdpq %2,%1\;mffscdrn %3,%3\;drsp %0,%2
   mffs %3\;mtfsfi 7,7,1\;drdpq %2,%1\;mtfsf 0xff,%3,1,0\;drsp %0,%2"
  [(set_attr "type" "dfp")
   (set_attr "isa" "p9,*")
   (set_attr "length" "16,20")])

(define_insn "add<mode>3"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	(plus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
		   (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dadd<q> %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "sub<mode>3"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	(minus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
		    (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dsub<q> %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "mul<mode>3"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	(mult:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
		   (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dmul<q> %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "div<mode>3"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	(div:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
		  (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "ddiv<q> %0,%1,%2"
  [(set_attr "type" "dfp")])

(define_insn "*cmp<mode>_internal1"
  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
	(compare:CCFP (match_operand:DDTD 1 "gpc_reg_operand" "d")
		      (match_operand:DDTD 2 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dcmpu<q> %0,%1,%2"
  [(set_attr "type" "dfp")
   (set_attr "size" "<bits>")])

(define_insn "floatdidd2"
  [(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP && TARGET_POPCNTD"
  "dcffix %0,%1"
  [(set_attr "type" "dfp")])

(define_insn "floatditd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dcffixq %0,%1"
  [(set_attr "type" "dfp")
   (set_attr "size" "128")])

(define_insn "floattitd2"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(float:TD (match_operand:TI 1 "gpc_reg_operand" "v")))]
  "TARGET_POWER10"
  "dcffixqq %0,%1"
  [(set_attr "type" "dfp")])

;; Convert a decimal64/128 to a decimal64/128 whose value is an integer.
;; This is the first stage of converting it to an integer type.

(define_insn "ftrunc<mode>2"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	(fix:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "drintn<q>. 0,%0,%1,1"
  [(set_attr "type" "dfp")
   (set_attr "size" "<bits>")])

;; Convert a decimal64/128 whose value is an integer to an actual integer.
;; This is the second stage of converting decimal float to integer type.

(define_insn "fix<mode>di2"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
	(fix:DI (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
  "TARGET_DFP"
  "dctfix<q> %0,%1"
  [(set_attr "type" "dfp")
   (set_attr "size" "<bits>")])

(define_insn "fixtdti2"
  [(set (match_operand:TI 0 "gpc_reg_operand" "=v")
	(fix:TI (match_operand:TD 1 "gpc_reg_operand" "d")))]
  "TARGET_POWER10"
  "dctfixqq %0,%1"
  [(set_attr "type" "dfp")])
\f
;; Decimal builtin support

(define_c_enum "unspec"
  [UNSPEC_DDEDPD
   UNSPEC_DENBCD
   UNSPEC_DXEX
   UNSPEC_DIEX
   UNSPEC_DSCLI
   UNSPEC_DTSTSFI
   UNSPEC_DSCRI
   UNSPEC_DQUAN])

(define_code_iterator DFP_TEST [eq lt gt unordered])

(define_insn "dfp_ddedpd_<mode>"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	(unspec:DDTD [(match_operand:QI 1 "const_0_to_3_operand" "i")
		      (match_operand:DDTD 2 "gpc_reg_operand" "d")]
		     UNSPEC_DDEDPD))]
  "TARGET_DFP"
  "ddedpd<q> %1,%0,%2"
  [(set_attr "type" "dfp")
   (set_attr "size" "<bits>")])

(define_insn "dfp_denbcd_<mode>"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	(unspec:DDTD [(match_operand:QI 1 "const_0_to_1_operand" "i")
		      (match_operand:DDTD 2 "gpc_reg_operand" "d")]
		     UNSPEC_DENBCD))]
  "TARGET_DFP"
  "denbcd<q> %1,%0,%2"
  [(set_attr "type" "dfp")
   (set_attr "size" "<bits>")])

(define_insn "dfp_denbcd_v16qi_inst"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(unspec:TD [(match_operand:QI 1 "const_0_to_1_operand" "i")
		    (match_operand:V16QI 2 "register_operand" "d")]
		   UNSPEC_DENBCD))]
  "TARGET_DFP"
  "denbcdq %1,%0,%2"
  [(set_attr "type" "dfp")])

(define_expand "dfp_denbcd_v16qi"
  [(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	(unspec:TD [(match_operand:V16QI 1 "register_operand" "v")]
		   UNSPEC_DENBCD))]
  "TARGET_DFP"
 {
   // Move vs128 upper 64-bits and lower 64-bits to fp register pair
   convert_move (operands[0], operands[1], true);
   emit_insn (gen_dfp_denbcd_v16qi_inst (operands[0], GEN_INT(1),
					 operands[0]));
   DONE;
 })

(define_insn "dfp_dxex_<mode>"
  [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
	(unspec:DI [(match_operand:DDTD 1 "gpc_reg_operand" "d")]
		   UNSPEC_DXEX))]
  "TARGET_DFP"
  "dxex<q> %0,%1"
  [(set_attr "type" "dfp")
   (set_attr "size" "<bits>")])

(define_insn "dfp_diex_<mode>"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	(unspec:DDTD [(match_operand:DI 1 "gpc_reg_operand" "d")
		      (match_operand:DDTD 2 "gpc_reg_operand" "d")]
		     UNSPEC_DXEX))]
  "TARGET_DFP"
  "diex<q> %0,%1,%2"
  [(set_attr "type" "dfp")
   (set_attr "size" "<bits>")])

(define_expand "dfptstsfi_<code>_<mode>"
  [(set (match_dup 3)
	(compare:CCFP (unspec:DDTD [(match_operand:SI 1 "const_int_operand")
				    (match_operand:DDTD 2 "gpc_reg_operand")]
				   UNSPEC_DTSTSFI)
		      (const_int 0)))
   (set (match_operand:SI 0 "register_operand")
	(DFP_TEST:SI (match_dup 3)
		     (const_int 0)))
  ]
  "TARGET_P9_MISC"
{
  if (<CODE> == UNORDERED && !HONOR_NANS (<MODE>mode))
    {
      emit_move_insn (operands[0], const0_rtx);
      DONE;
    }

  operands[3] = gen_reg_rtx (CCFPmode);
})

(define_insn "*dfp_sgnfcnc_<mode>"
  [(set (match_operand:CCFP 0 "" "=y")
	(compare:CCFP
	 (unspec:DDTD [(match_operand:SI 1 "const_int_operand" "n")
		       (match_operand:DDTD 2 "gpc_reg_operand" "d")]
		      UNSPEC_DTSTSFI)
	 (match_operand:SI 3 "zero_constant" "j")))]
  "TARGET_P9_MISC"
{
  /* If immediate operand is greater than 63, it will behave as if
     the value had been 63.  The code generator does not support
     immediate operand values greater than 63.  */
  if (!(IN_RANGE (INTVAL (operands[1]), 0, 63)))
    operands[1] = GEN_INT (63);
  return "dtstsfi<q> %0,%1,%2";
}
  [(set_attr "type" "fp")
   (set_attr "size" "<bits>")])

(define_insn "dfp_dscli_<mode>"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	(unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
		      (match_operand:QI 2 "immediate_operand" "i")]
		     UNSPEC_DSCLI))]
  "TARGET_DFP"
  "dscli<q> %0,%1,%2"
  [(set_attr "type" "dfp")
   (set_attr "size" "<bits>")])

(define_insn "dfp_dscri_<mode>"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	(unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
		      (match_operand:QI 2 "immediate_operand" "i")]
		     UNSPEC_DSCRI))]
  "TARGET_DFP"
  "dscri<q> %0,%1,%2"
  [(set_attr "type" "dfp")
   (set_attr "size" "<bits>")])

(define_insn "dfp_dqua_<mode>"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
        (unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
		      (match_operand:DDTD 2 "gpc_reg_operand" "d")
		      (match_operand:SI 3 "const_0_to_3_operand" "n")]
                     UNSPEC_DQUAN))]
  "TARGET_DFP"
  "dqua<q> %0,%1,%2,%3"
  [(set_attr "type" "dfp")
   (set_attr "size" "<bits>")])

(define_insn "dfp_dquai_<mode>"
  [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
        (unspec:DDTD [(match_operand:SI 1 "s5bit_cint_operand" "n")
		      (match_operand:DDTD 2 "gpc_reg_operand" "d")
		      (match_operand:SI 3 "const_0_to_3_operand" "n")]
                     UNSPEC_DQUAN))]
  "TARGET_DFP"
  "dquai<q> %1,%0,%2,%3"
  [(set_attr "type" "dfp")
   (set_attr "size" "<bits>")])
Commit	Line	Data
7393f7f8	1	;; Decimal Floating Point (DFP) patterns.
a945c346	2	;; Copyright (C) 2007-2024 Free Software Foundation, Inc.
7393f7f8 BE	3	;; Contributed by Ben Elliston (bje@au.ibm.com) and Peter Bergner
	4	;; (bergner@vnet.ibm.com).
	5
	6	;; This file is part of GCC.
	7
	8	;; GCC is free software; you can redistribute it and/or modify it
	9	;; under the terms of the GNU General Public License as published
2f83c7d6	10	;; by the Free Software Foundation; either version 3, or (at your
7393f7f8 BE	11	;; option) any later version.
	12
	13	;; GCC is distributed in the hope that it will be useful, but WITHOUT
	14	;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	15	;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
	16	;; License for more details.
	17
	18	;; You should have received a copy of the GNU General Public License
2f83c7d6 NC	19	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	20	;; <http://www.gnu.org/licenses/>.
7393f7f8	21
e41b2a33 PB	22	;;
	23	;; UNSPEC usage
	24	;;
	25
f3c33d9d MM	26	(define_c_enum "unspec"
	27	[UNSPEC_MOVSD_LOAD
	28	UNSPEC_MOVSD_STORE
e41b2a33 PB	29	])
e41b2a33 PB	30
b1bb8160	31	; Either of the two decimal modes.
e35f75d3	32	(define_mode_iterator DDTD [DD TD])
b1bb8160	33
e35f75d3	34	(define_mode_attr q [(DD "") (TD "q")])
b1bb8160	35
e41b2a33	36
e41b2a33 PB	37	(define_insn "movsd_store"
e41b2a33 PB	38	[(set (match_operand:DD 0 "nonimmediate_operand" "=m")
799dbb0f	39	(unspec:DD [(match_operand:SD 1 "input_operand" "d")]
e41b2a33 PB	40	UNSPEC_MOVSD_STORE))]
	41	"(gpc_reg_operand (operands[0], DDmode)
	42	\|\| gpc_reg_operand (operands[1], SDmode))
11d8d07e	43	&& TARGET_HARD_FLOAT"
e41b2a33	44	"stfd%U0%X0 %1,%0"
b24a46be	45	[(set_attr "type" "fpstore")])
e41b2a33 PB	46
	47	(define_insn "movsd_load"
	48	[(set (match_operand:SD 0 "nonimmediate_operand" "=f")
	49	(unspec:SD [(match_operand:DD 1 "input_operand" "m")]
	50	UNSPEC_MOVSD_LOAD))]
	51	"(gpc_reg_operand (operands[0], SDmode)
	52	\|\| gpc_reg_operand (operands[1], DDmode))
11d8d07e	53	&& TARGET_HARD_FLOAT"
e41b2a33	54	"lfd%U1%X1 %0,%1"
b24a46be	55	[(set_attr "type" "fpload")])
e41b2a33 PB	56
	57	;; Hardware support for decimal floating point operations.
	58
	59	(define_insn "extendsddd2"
799dbb0f	60	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
e41b2a33 PB	61	(float_extend:DD (match_operand:SD 1 "gpc_reg_operand" "f")))]
	62	"TARGET_DFP"
	63	"dctdp %0,%1"
eda328bf	64	[(set_attr "type" "dfp")])
e41b2a33 PB	65
e41b2a33 PB	66	(define_expand "extendsdtd2"
799dbb0f ME	67	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
799dbb0f ME	68	(float_extend:TD (match_operand:SD 1 "gpc_reg_operand" "d")))]
e41b2a33 PB	69	"TARGET_DFP"
	70	{
	71	rtx tmp = gen_reg_rtx (DDmode);
	72	emit_insn (gen_extendsddd2 (tmp, operands[1]));
	73	emit_insn (gen_extendddtd2 (operands[0], tmp));
	74	DONE;
	75	})
	76
	77	(define_insn "truncddsd2"
	78	[(set (match_operand:SD 0 "gpc_reg_operand" "=f")
799dbb0f	79	(float_truncate:SD (match_operand:DD 1 "gpc_reg_operand" "d")))]
e41b2a33 PB	80	"TARGET_DFP"
e41b2a33 PB	81	"drsp %0,%1"
eda328bf	82	[(set_attr "type" "dfp")])
e41b2a33	83
11d8d07e	84	(define_insn "negdd2"
799dbb0f ME	85	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
799dbb0f ME	86	(neg:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
11d8d07e	87	"TARGET_HARD_FLOAT"
c092b045	88	"fneg %0,%1"
7c788ce2	89	[(set_attr "type" "fpsimple")])
c092b045	90
11d8d07e	91	(define_insn "absdd2"
799dbb0f ME	92	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
799dbb0f ME	93	(abs:DD (match_operand:DD 1 "gpc_reg_operand" "d")))]
11d8d07e	94	"TARGET_HARD_FLOAT"
c092b045	95	"fabs %0,%1"
7c788ce2	96	[(set_attr "type" "fpsimple")])
c092b045 PB	97
c092b045 PB	98	(define_insn "*nabsdd2_fpr"
799dbb0f ME	99	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
799dbb0f ME	100	(neg:DD (abs:DD (match_operand:DD 1 "gpc_reg_operand" "d"))))]
11d8d07e	101	"TARGET_HARD_FLOAT"
c092b045	102	"fnabs %0,%1"
7c788ce2	103	[(set_attr "type" "fpsimple")])
c092b045	104
11d8d07e	105	(define_insn "negtd2"
e2323f5b PB	106	[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
e2323f5b PB	107	(neg:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
11d8d07e	108	"TARGET_HARD_FLOAT"
e2323f5b PB	109	"@
	110	fneg %0,%1
	111	fneg %0,%1\;fmr %L0,%L1"
7c788ce2	112	[(set_attr "type" "fpsimple")
e2323f5b	113	(set_attr "length" "4,8")])
c092b045	114
11d8d07e	115	(define_insn "abstd2"
e2323f5b PB	116	[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
e2323f5b PB	117	(abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d")))]
11d8d07e	118	"TARGET_HARD_FLOAT"
e2323f5b PB	119	"@
	120	fabs %0,%1
	121	fabs %0,%1\;fmr %L0,%L1"
7c788ce2	122	[(set_attr "type" "fpsimple")
e2323f5b	123	(set_attr "length" "4,8")])
c092b045 PB	124
c092b045 PB	125	(define_insn "*nabstd2_fpr"
e2323f5b PB	126	[(set (match_operand:TD 0 "gpc_reg_operand" "=d,d")
e2323f5b PB	127	(neg:TD (abs:TD (match_operand:TD 1 "gpc_reg_operand" "0,d"))))]
11d8d07e	128	"TARGET_HARD_FLOAT"
e2323f5b PB	129	"@
	130	fnabs %0,%1
	131	fnabs %0,%1\;fmr %L0,%L1"
7c788ce2	132	[(set_attr "type" "fpsimple")
e2323f5b	133	(set_attr "length" "4,8")])
c092b045	134
6ef9a246 JJ	135	;; Hardware support for decimal floating point operations.
	136
	137	(define_insn "extendddtd2"
799dbb0f ME	138	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
799dbb0f ME	139	(float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))]
6ef9a246 JJ	140	"TARGET_DFP"
6ef9a246 JJ	141	"dctqpq %0,%1"
9a5a1e27 PH	142	[(set_attr "type" "dfp")
9a5a1e27 PH	143	(set_attr "size" "128")])
6ef9a246 JJ	144
	145	;; The result of drdpq is an even/odd register pair with the converted
	146	;; value in the even register and zero in the odd register.
	147	;; FIXME: Avoid the register move by using a reload constraint to ensure
	148	;; that the result is the first of the pair receiving the result of drdpq.
	149
	150	(define_insn "trunctddd2"
799dbb0f ME	151	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	152	(float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "d")))
	153	(clobber (match_scratch:TD 2 "=d"))]
6ef9a246 JJ	154	"TARGET_DFP"
6ef9a246 JJ	155	"drdpq %2,%1\;fmr %0,%2"
eda328bf	156	[(set_attr "type" "dfp")
9a5a1e27	157	(set_attr "size" "128")
521466e5	158	(set_attr "length" "8")])
6ef9a246	159
8a8c2573 PB	160	(define_insn "trunctdsd2"
	161	[(set (match_operand:SD 0 "gpc_reg_operand" "=d,d")
	162	(float_truncate:SD (match_operand:TD 1 "gpc_reg_operand" "d,d")))
	163	(clobber (match_scratch:TD 2 "=&d,&d"))
	164	(clobber (match_scratch:DF 3 "=&d,&d"))]
	165	"TARGET_DFP"
	166	"@
	167	mffscdrni %3,7\;drdpq %2,%1\;mffscdrn %3,%3\;drsp %0,%2
	168	mffs %3\;mtfsfi 7,7,1\;drdpq %2,%1\;mtfsf 0xff,%3,1,0\;drsp %0,%2"
	169	[(set_attr "type" "dfp")
	170	(set_attr "isa" "p9,*")
	171	(set_attr "length" "16,20")])
	172
b1bb8160	173	(define_insn "add<mode>3"
e35f75d3 SB	174	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	175	(plus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
	176	(match_operand:DDTD 2 "gpc_reg_operand" "d")))]
6ef9a246	177	"TARGET_DFP"
e35f75d3	178	"dadd<q> %0,%1,%2"
eda328bf	179	[(set_attr "type" "dfp")])
6ef9a246	180
b1bb8160	181	(define_insn "sub<mode>3"
e35f75d3 SB	182	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	183	(minus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
	184	(match_operand:DDTD 2 "gpc_reg_operand" "d")))]
6ef9a246	185	"TARGET_DFP"
e35f75d3	186	"dsub<q> %0,%1,%2"
eda328bf	187	[(set_attr "type" "dfp")])
6ef9a246	188
b1bb8160	189	(define_insn "mul<mode>3"
e35f75d3 SB	190	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	191	(mult:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
	192	(match_operand:DDTD 2 "gpc_reg_operand" "d")))]
6ef9a246	193	"TARGET_DFP"
e35f75d3	194	"dmul<q> %0,%1,%2"
eda328bf	195	[(set_attr "type" "dfp")])
6ef9a246	196
b1bb8160	197	(define_insn "div<mode>3"
e35f75d3 SB	198	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	199	(div:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")
	200	(match_operand:DDTD 2 "gpc_reg_operand" "d")))]
6ef9a246	201	"TARGET_DFP"
e35f75d3	202	"ddiv<q> %0,%1,%2"
eda328bf	203	[(set_attr "type" "dfp")])
6ef9a246	204
b1bb8160	205	(define_insn "*cmp<mode>_internal1"
6ef9a246	206	[(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
e35f75d3 SB	207	(compare:CCFP (match_operand:DDTD 1 "gpc_reg_operand" "d")
e35f75d3 SB	208	(match_operand:DDTD 2 "gpc_reg_operand" "d")))]
6ef9a246	209	"TARGET_DFP"
e35f75d3	210	"dcmpu<q> %0,%1,%2"
9a5a1e27 PH	211	[(set_attr "type" "dfp")
9a5a1e27 PH	212	(set_attr "size" "<bits>")])
6ef9a246	213
6f975f93 PB	214	(define_insn "floatdidd2"
	215	[(set (match_operand:DD 0 "gpc_reg_operand" "=d")
	216	(float:DD (match_operand:DI 1 "gpc_reg_operand" "d")))]
	217	"TARGET_DFP && TARGET_POPCNTD"
	218	"dcffix %0,%1"
eda328bf	219	[(set_attr "type" "dfp")])
6f975f93	220
6ef9a246	221	(define_insn "floatditd2"
799dbb0f ME	222	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
799dbb0f ME	223	(float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))]
6ef9a246 JJ	224	"TARGET_DFP"
6ef9a246 JJ	225	"dcffixq %0,%1"
9a5a1e27 PH	226	[(set_attr "type" "dfp")
9a5a1e27 PH	227	(set_attr "size" "128")])
6ef9a246	228
976ffcf8 CL	229	(define_insn "floattitd2"
	230	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	231	(float:TD (match_operand:TI 1 "gpc_reg_operand" "v")))]
	232	"TARGET_POWER10"
	233	"dcffixqq %0,%1"
	234	[(set_attr "type" "dfp")])
	235
b1bb8160	236	;; Convert a decimal64/128 to a decimal64/128 whose value is an integer.
6ef9a246 JJ	237	;; This is the first stage of converting it to an integer type.
6ef9a246 JJ	238
b1bb8160	239	(define_insn "ftrunc<mode>2"
e35f75d3 SB	240	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
e35f75d3 SB	241	(fix:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
6ef9a246	242	"TARGET_DFP"
e35f75d3	243	"drintn<q>. 0,%0,%1,1"
9a5a1e27 PH	244	[(set_attr "type" "dfp")
9a5a1e27 PH	245	(set_attr "size" "<bits>")])
6ef9a246	246
b1bb8160	247	;; Convert a decimal64/128 whose value is an integer to an actual integer.
6ef9a246 JJ	248	;; This is the second stage of converting decimal float to integer type.
6ef9a246 JJ	249
b1bb8160	250	(define_insn "fix<mode>di2"
799dbb0f	251	[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
e35f75d3	252	(fix:DI (match_operand:DDTD 1 "gpc_reg_operand" "d")))]
6ef9a246	253	"TARGET_DFP"
e35f75d3	254	"dctfix<q> %0,%1"
9a5a1e27 PH	255	[(set_attr "type" "dfp")
9a5a1e27 PH	256	(set_attr "size" "<bits>")])
976ffcf8 CL	257
	258	(define_insn "fixtdti2"
	259	[(set (match_operand:TI 0 "gpc_reg_operand" "=v")
	260	(fix:TI (match_operand:TD 1 "gpc_reg_operand" "d")))]
	261	"TARGET_POWER10"
	262	"dctfixqq %0,%1"
	263	[(set_attr "type" "dfp")])
06b39289 MM	264	\f
	265	;; Decimal builtin support
	266
	267	(define_c_enum "unspec"
	268	[UNSPEC_DDEDPD
	269	UNSPEC_DENBCD
	270	UNSPEC_DXEX
	271	UNSPEC_DIEX
	272	UNSPEC_DSCLI
5a3a6a5e	273	UNSPEC_DTSTSFI
14a3839c CL	274	UNSPEC_DSCRI
14a3839c CL	275	UNSPEC_DQUAN])
06b39289	276
5a3a6a5e KN	277	(define_code_iterator DFP_TEST [eq lt gt unordered])
5a3a6a5e KN	278
06b39289	279	(define_insn "dfp_ddedpd_<mode>"
e35f75d3 SB	280	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	281	(unspec:DDTD [(match_operand:QI 1 "const_0_to_3_operand" "i")
	282	(match_operand:DDTD 2 "gpc_reg_operand" "d")]
	283	UNSPEC_DDEDPD))]
06b39289	284	"TARGET_DFP"
e35f75d3	285	"ddedpd<q> %1,%0,%2"
9a5a1e27 PH	286	[(set_attr "type" "dfp")
9a5a1e27 PH	287	(set_attr "size" "<bits>")])
06b39289 MM	288
06b39289 MM	289	(define_insn "dfp_denbcd_<mode>"
e35f75d3 SB	290	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	291	(unspec:DDTD [(match_operand:QI 1 "const_0_to_1_operand" "i")
	292	(match_operand:DDTD 2 "gpc_reg_operand" "d")]
	293	UNSPEC_DENBCD))]
06b39289	294	"TARGET_DFP"
e35f75d3	295	"denbcd<q> %1,%0,%2"
9a5a1e27 PH	296	[(set_attr "type" "dfp")
9a5a1e27 PH	297	(set_attr "size" "<bits>")])
06b39289	298
05161256 CL	299	(define_insn "dfp_denbcd_v16qi_inst"
	300	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	301	(unspec:TD [(match_operand:QI 1 "const_0_to_1_operand" "i")
	302	(match_operand:V16QI 2 "register_operand" "d")]
	303	UNSPEC_DENBCD))]
	304	"TARGET_DFP"
	305	"denbcdq %1,%0,%2"
	306	[(set_attr "type" "dfp")])
	307
	308	(define_expand "dfp_denbcd_v16qi"
	309	[(set (match_operand:TD 0 "gpc_reg_operand" "=d")
	310	(unspec:TD [(match_operand:V16QI 1 "register_operand" "v")]
	311	UNSPEC_DENBCD))]
	312	"TARGET_DFP"
	313	{
	314	// Move vs128 upper 64-bits and lower 64-bits to fp register pair
	315	convert_move (operands[0], operands[1], true);
	316	emit_insn (gen_dfp_denbcd_v16qi_inst (operands[0], GEN_INT(1),
	317	operands[0]));
	318	DONE;
	319	})
	320
06b39289	321	(define_insn "dfp_dxex_<mode>"
05dc406d	322	[(set (match_operand:DI 0 "gpc_reg_operand" "=d")
e35f75d3	323	(unspec:DI [(match_operand:DDTD 1 "gpc_reg_operand" "d")]
05dc406d	324	UNSPEC_DXEX))]
06b39289	325	"TARGET_DFP"
e35f75d3	326	"dxex<q> %0,%1"
9a5a1e27 PH	327	[(set_attr "type" "dfp")
9a5a1e27 PH	328	(set_attr "size" "<bits>")])
06b39289 MM	329
06b39289 MM	330	(define_insn "dfp_diex_<mode>"
e35f75d3 SB	331	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	332	(unspec:DDTD [(match_operand:DI 1 "gpc_reg_operand" "d")
	333	(match_operand:DDTD 2 "gpc_reg_operand" "d")]
	334	UNSPEC_DXEX))]
06b39289	335	"TARGET_DFP"
e35f75d3	336	"diex<q> %0,%1,%2"
9a5a1e27 PH	337	[(set_attr "type" "dfp")
9a5a1e27 PH	338	(set_attr "size" "<bits>")])
06b39289	339
5a3a6a5e KN	340	(define_expand "dfptstsfi_<code>_<mode>"
5a3a6a5e KN	341	[(set (match_dup 3)
e35f75d3 SB	342	(compare:CCFP (unspec:DDTD [(match_operand:SI 1 "const_int_operand")
	343	(match_operand:DDTD 2 "gpc_reg_operand")]
	344	UNSPEC_DTSTSFI)
	345	(const_int 0)))
ad18eed2	346	(set (match_operand:SI 0 "register_operand")
e35f75d3	347	(DFP_TEST:SI (match_dup 3)
5a3a6a5e KN	348	(const_int 0)))
	349	]
	350	"TARGET_P9_MISC"
	351	{
bcb4b4b4 SB	352	if (<CODE> == UNORDERED && !HONOR_NANS (<MODE>mode))
	353	{
	354	emit_move_insn (operands[0], const0_rtx);
	355	DONE;
	356	}
	357
5a3a6a5e	358	operands[3] = gen_reg_rtx (CCFPmode);
5a3a6a5e KN	359	})
	360
	361	(define_insn "*dfp_sgnfcnc_<mode>"
	362	[(set (match_operand:CCFP 0 "" "=y")
e35f75d3 SB	363	(compare:CCFP
	364	(unspec:DDTD [(match_operand:SI 1 "const_int_operand" "n")
	365	(match_operand:DDTD 2 "gpc_reg_operand" "d")]
	366	UNSPEC_DTSTSFI)
5a3a6a5e KN	367	(match_operand:SI 3 "zero_constant" "j")))]
	368	"TARGET_P9_MISC"
	369	{
	370	/* If immediate operand is greater than 63, it will behave as if
	371	the value had been 63. The code generator does not support
	372	immediate operand values greater than 63. */
	373	if (!(IN_RANGE (INTVAL (operands[1]), 0, 63)))
	374	operands[1] = GEN_INT (63);
e35f75d3	375	return "dtstsfi<q> %0,%1,%2";
5a3a6a5e	376	}
9a5a1e27 PH	377	[(set_attr "type" "fp")
9a5a1e27 PH	378	(set_attr "size" "<bits>")])
5a3a6a5e	379
06b39289	380	(define_insn "dfp_dscli_<mode>"
e35f75d3 SB	381	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	382	(unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
	383	(match_operand:QI 2 "immediate_operand" "i")]
	384	UNSPEC_DSCLI))]
06b39289	385	"TARGET_DFP"
e35f75d3	386	"dscli<q> %0,%1,%2"
9a5a1e27 PH	387	[(set_attr "type" "dfp")
9a5a1e27 PH	388	(set_attr "size" "<bits>")])
06b39289 MM	389
06b39289 MM	390	(define_insn "dfp_dscri_<mode>"
e35f75d3 SB	391	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	392	(unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
	393	(match_operand:QI 2 "immediate_operand" "i")]
	394	UNSPEC_DSCRI))]
06b39289	395	"TARGET_DFP"
e35f75d3	396	"dscri<q> %0,%1,%2"
9a5a1e27 PH	397	[(set_attr "type" "dfp")
9a5a1e27 PH	398	(set_attr "size" "<bits>")])
14a3839c CL	399
	400	(define_insn "dfp_dqua_<mode>"
	401	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	402	(unspec:DDTD [(match_operand:DDTD 1 "gpc_reg_operand" "d")
	403	(match_operand:DDTD 2 "gpc_reg_operand" "d")
	404	(match_operand:SI 3 "const_0_to_3_operand" "n")]
	405	UNSPEC_DQUAN))]
	406	"TARGET_DFP"
	407	"dqua<q> %0,%1,%2,%3"
	408	[(set_attr "type" "dfp")
	409	(set_attr "size" "<bits>")])
	410
	411	(define_insn "dfp_dquai_<mode>"
	412	[(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
	413	(unspec:DDTD [(match_operand:SI 1 "s5bit_cint_operand" "n")
	414	(match_operand:DDTD 2 "gpc_reg_operand" "d")
	415	(match_operand:SI 3 "const_0_to_3_operand" "n")]
	416	UNSPEC_DQUAN))]
	417	"TARGET_DFP"
	418	"dquai<q> %1,%0,%2,%3"
	419	[(set_attr "type" "dfp")
	420	(set_attr "size" "<bits>")])