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f045b2c9 | 1 | /* Definitions of target machine for GNU compiler, for IBM RS/6000. |
a5544970 | 2 | Copyright (C) 1992-2019 Free Software Foundation, Inc. |
6a7ec0a7 | 3 | Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
f045b2c9 | 4 | |
5de601cf | 5 | This file is part of GCC. |
f045b2c9 | 6 | |
5de601cf NC |
7 | GCC is free software; you can redistribute it and/or modify it |
8 | under the terms of the GNU General Public License as published | |
2f83c7d6 | 9 | by the Free Software Foundation; either version 3, or (at your |
5de601cf | 10 | option) any later version. |
f045b2c9 | 11 | |
5de601cf NC |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
f045b2c9 | 16 | |
748086b7 JJ |
17 | Under Section 7 of GPL version 3, you are granted additional |
18 | permissions described in the GCC Runtime Library Exception, version | |
19 | 3.1, as published by the Free Software Foundation. | |
20 | ||
21 | You should have received a copy of the GNU General Public License and | |
22 | a copy of the GCC Runtime Library Exception along with this program; | |
23 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see | |
2f83c7d6 | 24 | <http://www.gnu.org/licenses/>. */ |
f045b2c9 RS |
25 | |
26 | /* Note that some other tm.h files include this one and then override | |
9ebbca7d | 27 | many of the definitions. */ |
f045b2c9 | 28 | |
fd438373 MM |
29 | #ifndef RS6000_OPTS_H |
30 | #include "config/rs6000/rs6000-opts.h" | |
31 | #endif | |
32 | ||
6a8886e4 MM |
33 | /* 128-bit floating point precision values. */ |
34 | #ifndef RS6000_MODES_H | |
35 | #include "config/rs6000/rs6000-modes.h" | |
36 | #endif | |
37 | ||
9ebbca7d GK |
38 | /* Definitions for the object file format. These are set at |
39 | compile-time. */ | |
f045b2c9 | 40 | |
9ebbca7d GK |
41 | #define OBJECT_XCOFF 1 |
42 | #define OBJECT_ELF 2 | |
ee890fe2 | 43 | #define OBJECT_MACHO 4 |
f045b2c9 | 44 | |
9ebbca7d | 45 | #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) |
2bfcf297 | 46 | #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) |
ee890fe2 | 47 | #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) |
f045b2c9 | 48 | |
2bfcf297 DB |
49 | #ifndef TARGET_AIX |
50 | #define TARGET_AIX 0 | |
51 | #endif | |
52 | ||
78009d9f MM |
53 | #ifndef TARGET_AIX_OS |
54 | #define TARGET_AIX_OS 0 | |
55 | #endif | |
56 | ||
85b776df AM |
57 | /* Control whether function entry points use a "dot" symbol when |
58 | ABI_AIX. */ | |
59 | #define DOT_SYMBOLS 1 | |
60 | ||
8e3f41e7 MM |
61 | /* Default string to use for cpu if not specified. */ |
62 | #ifndef TARGET_CPU_DEFAULT | |
63 | #define TARGET_CPU_DEFAULT ((char *)0) | |
64 | #endif | |
65 | ||
f565b0a1 | 66 | /* If configured for PPC405, support PPC405CR Erratum77. */ |
b0bfee6e | 67 | #ifdef CONFIG_PPC405CR |
f565b0a1 DE |
68 | #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) |
69 | #else | |
70 | #define PPC405_ERRATUM77 0 | |
71 | #endif | |
72 | ||
cacf1ca8 MM |
73 | /* Common ASM definitions used by ASM_SPEC among the various targets for |
74 | handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to | |
75 | provide the default assembler options if the user uses -mcpu=native, so if | |
1b58c736 PB |
76 | you make changes here, make them also there. PR63177: Do not pass -mpower8 |
77 | to the assembler if -mpower9-vector was also used. */ | |
f984d8df | 78 | #define ASM_CPU_SPEC \ |
28a09576 AM |
79 | "%{mcpu=native: %(asm_cpu_native); \ |
80 | mcpu=power9: -mpower9; \ | |
81 | mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \ | |
82 | mcpu=power7: -mpower7; \ | |
83 | mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
84 | mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
85 | mcpu=power5+: -mpower5; \ | |
86 | mcpu=power5: -mpower5; \ | |
87 | mcpu=power4: -mpower4; \ | |
88 | mcpu=power3: -mppc64; \ | |
89 | mcpu=powerpc: -mppc; \ | |
f7bdd292 | 90 | mcpu=powerpc64: -mppc64; \ |
28a09576 AM |
91 | mcpu=a2: -ma2; \ |
92 | mcpu=cell: -mcell; \ | |
f7bdd292 | 93 | mcpu=rs64: -mppc64; \ |
28a09576 AM |
94 | mcpu=401: -mppc; \ |
95 | mcpu=403: -m403; \ | |
96 | mcpu=405: -m405; \ | |
97 | mcpu=405fp: -m405; \ | |
98 | mcpu=440: -m440; \ | |
99 | mcpu=440fp: -m440; \ | |
100 | mcpu=464: -m440; \ | |
101 | mcpu=464fp: -m440; \ | |
102 | mcpu=476: -m476; \ | |
103 | mcpu=476fp: -m476; \ | |
104 | mcpu=505: -mppc; \ | |
105 | mcpu=601: -m601; \ | |
106 | mcpu=602: -mppc; \ | |
107 | mcpu=603: -mppc; \ | |
108 | mcpu=603e: -mppc; \ | |
109 | mcpu=ec603e: -mppc; \ | |
110 | mcpu=604: -mppc; \ | |
111 | mcpu=604e: -mppc; \ | |
112 | mcpu=620: -mppc64; \ | |
113 | mcpu=630: -mppc64; \ | |
114 | mcpu=740: -mppc; \ | |
115 | mcpu=750: -mppc; \ | |
116 | mcpu=G3: -mppc; \ | |
117 | mcpu=7400: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ | |
118 | mcpu=7450: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ | |
119 | mcpu=G4: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ | |
120 | mcpu=801: -mppc; \ | |
121 | mcpu=821: -mppc; \ | |
122 | mcpu=823: -mppc; \ | |
123 | mcpu=860: -mppc; \ | |
124 | mcpu=970: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
125 | mcpu=G5: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ | |
126 | mcpu=8540: -me500; \ | |
127 | mcpu=8548: -me500; \ | |
128 | mcpu=e300c2: -me300; \ | |
129 | mcpu=e300c3: -me300; \ | |
130 | mcpu=e500mc: -me500mc; \ | |
131 | mcpu=e500mc64: -me500mc64; \ | |
132 | mcpu=e5500: -me5500; \ | |
133 | mcpu=e6500: -me6500; \ | |
f7bdd292 | 134 | mcpu=titan: -mtitan; \ |
28a09576 AM |
135 | !mcpu*: %{mpower9-vector: -mpower9; \ |
136 | mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ | |
137 | mvsx: -mpower7; \ | |
138 | mpowerpc64: -mppc64;: %(asm_default)}; \ | |
f7bdd292 | 139 | :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \ |
28a09576 | 140 | %{mvsx: -mvsx -maltivec; maltivec: -maltivec} \ |
93ae5495 | 141 | -many" |
f984d8df DB |
142 | |
143 | #define CPP_DEFAULT_SPEC "" | |
144 | ||
145 | #define ASM_DEFAULT_SPEC "" | |
146 | ||
841faeed MM |
147 | /* This macro defines names of additional specifications to put in the specs |
148 | that can be used in various specifications like CC1_SPEC. Its definition | |
149 | is an initializer with a subgrouping for each command option. | |
150 | ||
151 | Each subgrouping contains a string constant, that defines the | |
5de601cf | 152 | specification name, and a string constant that used by the GCC driver |
841faeed MM |
153 | program. |
154 | ||
155 | Do not define this macro if it does not need to do anything. */ | |
156 | ||
7509c759 | 157 | #define SUBTARGET_EXTRA_SPECS |
7509c759 | 158 | |
c81bebd7 | 159 | #define EXTRA_SPECS \ |
c81bebd7 | 160 | { "cpp_default", CPP_DEFAULT_SPEC }, \ |
c81bebd7 | 161 | { "asm_cpu", ASM_CPU_SPEC }, \ |
cacf1ca8 | 162 | { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ |
c81bebd7 | 163 | { "asm_default", ASM_DEFAULT_SPEC }, \ |
0eab6840 | 164 | { "cc1_cpu", CC1_CPU_SPEC }, \ |
7509c759 MM |
165 | SUBTARGET_EXTRA_SPECS |
166 | ||
0eab6840 DE |
167 | /* -mcpu=native handling only makes sense with compiler running on |
168 | an PowerPC chip. If changing this condition, also change | |
169 | the condition in driver-rs6000.c. */ | |
170 | #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) | |
171 | /* In driver-rs6000.c. */ | |
172 | extern const char *host_detect_local_cpu (int argc, const char **argv); | |
173 | #define EXTRA_SPEC_FUNCTIONS \ | |
174 | { "local_cpu_detect", host_detect_local_cpu }, | |
175 | #define HAVE_LOCAL_CPU_DETECT | |
cacf1ca8 MM |
176 | #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" |
177 | ||
178 | #else | |
179 | #define ASM_CPU_NATIVE_SPEC "%(asm_default)" | |
0eab6840 DE |
180 | #endif |
181 | ||
ee7caeb3 DE |
182 | #ifndef CC1_CPU_SPEC |
183 | #ifdef HAVE_LOCAL_CPU_DETECT | |
0eab6840 DE |
184 | #define CC1_CPU_SPEC \ |
185 | "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ | |
186 | %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
ee7caeb3 DE |
187 | #else |
188 | #define CC1_CPU_SPEC "" | |
189 | #endif | |
0eab6840 DE |
190 | #endif |
191 | ||
fb623df5 | 192 | /* Architecture type. */ |
f045b2c9 | 193 | |
bb22512c | 194 | /* Define TARGET_MFCRF if the target assembler does not support the |
78f5898b | 195 | optional field operand for mfcr. */ |
fb623df5 | 196 | |
78f5898b | 197 | #ifndef HAVE_AS_MFCRF |
432218ba | 198 | #undef TARGET_MFCRF |
ffa22984 DE |
199 | #define TARGET_MFCRF 0 |
200 | #endif | |
201 | ||
9752c4ad AM |
202 | /* Define TARGET_TLS_MARKERS if the target assembler does not support |
203 | arg markers for __tls_get_addr calls. */ | |
204 | #ifndef HAVE_AS_TLS_MARKERS | |
205 | #undef TARGET_TLS_MARKERS | |
206 | #define TARGET_TLS_MARKERS 0 | |
207 | #else | |
208 | #define TARGET_TLS_MARKERS tls_markers | |
209 | #endif | |
210 | ||
7f970b70 AM |
211 | #ifndef TARGET_SECURE_PLT |
212 | #define TARGET_SECURE_PLT 0 | |
213 | #endif | |
214 | ||
070b27da AM |
215 | #ifndef TARGET_CMODEL |
216 | #define TARGET_CMODEL CMODEL_SMALL | |
217 | #endif | |
218 | ||
2f3e5814 | 219 | #define TARGET_32BIT (! TARGET_64BIT) |
d14a6d05 | 220 | |
c4501e62 JJ |
221 | #ifndef HAVE_AS_TLS |
222 | #define HAVE_AS_TLS 0 | |
223 | #endif | |
224 | ||
3f79c0ad AM |
225 | #ifndef HAVE_AS_PLTSEQ |
226 | #define HAVE_AS_PLTSEQ 0 | |
227 | #endif | |
228 | ||
be26142a PB |
229 | #ifndef TARGET_LINK_STACK |
230 | #define TARGET_LINK_STACK 0 | |
231 | #endif | |
232 | ||
233 | #ifndef SET_TARGET_LINK_STACK | |
234 | #define SET_TARGET_LINK_STACK(X) do { } while (0) | |
235 | #endif | |
236 | ||
08213983 MM |
237 | #ifndef TARGET_FLOAT128_ENABLE_TYPE |
238 | #define TARGET_FLOAT128_ENABLE_TYPE 0 | |
239 | #endif | |
240 | ||
48d72335 DE |
241 | /* Return 1 for a symbol ref for a thread-local storage symbol. */ |
242 | #define RS6000_SYMBOL_REF_TLS_P(RTX) \ | |
243 | (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) | |
244 | ||
996ed075 JJ |
245 | #ifdef IN_LIBGCC2 |
246 | /* For libgcc2 we make sure this is a compile time constant */ | |
67796c1f | 247 | #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) |
78f5898b | 248 | #undef TARGET_POWERPC64 |
996ed075 JJ |
249 | #define TARGET_POWERPC64 1 |
250 | #else | |
78f5898b | 251 | #undef TARGET_POWERPC64 |
996ed075 JJ |
252 | #define TARGET_POWERPC64 0 |
253 | #endif | |
b6c9286a | 254 | #else |
78f5898b | 255 | /* The option machinery will define this. */ |
b6c9286a MM |
256 | #endif |
257 | ||
20c89ab7 | 258 | #define TARGET_DEFAULT (MASK_MULTIPLE) |
9ebbca7d | 259 | |
8482e358 | 260 | /* Define generic processor types based upon current deployment. */ |
3cb999d8 | 261 | #define PROCESSOR_COMMON PROCESSOR_PPC601 |
3cb999d8 DE |
262 | #define PROCESSOR_POWERPC PROCESSOR_PPC604 |
263 | #define PROCESSOR_POWERPC64 PROCESSOR_RS64A | |
6e151478 | 264 | |
fb623df5 | 265 | /* Define the default processor. This is overridden by other tm.h files. */ |
f3061fa4 | 266 | #define PROCESSOR_DEFAULT PROCESSOR_PPC603 |
3cb999d8 | 267 | #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A |
fb623df5 | 268 | |
59ac9a55 JJ |
269 | /* Specify the dialect of assembler to use. Only new mnemonics are supported |
270 | starting with GCC 4.8, i.e. just one dialect, but for backwards | |
271 | compatibility with older inline asm ASSEMBLER_DIALECT needs to be | |
272 | defined. */ | |
273 | #define ASSEMBLER_DIALECT 1 | |
274 | ||
38c1f2d7 | 275 | /* Debug support */ |
fd438373 MM |
276 | #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ |
277 | #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ | |
278 | #define MASK_DEBUG_REG 0x04 /* debug register handling */ | |
279 | #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ | |
280 | #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ | |
281 | #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ | |
7fa14a01 | 282 | #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ |
fd438373 MM |
283 | #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ |
284 | | MASK_DEBUG_ARG \ | |
285 | | MASK_DEBUG_REG \ | |
286 | | MASK_DEBUG_ADDR \ | |
287 | | MASK_DEBUG_COST \ | |
7fa14a01 MM |
288 | | MASK_DEBUG_TARGET \ |
289 | | MASK_DEBUG_BUILTIN) | |
fd438373 MM |
290 | |
291 | #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) | |
292 | #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) | |
293 | #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) | |
294 | #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) | |
295 | #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) | |
296 | #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) | |
7fa14a01 | 297 | #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) |
cacf1ca8 | 298 | |
2c83faf8 MM |
299 | /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM |
300 | long double format that uses a pair of doubles, or IEEE 128-bit floating | |
301 | point. KFmode was added as a way to represent IEEE 128-bit floating point, | |
302 | even if the default for long double is the IBM long double format. | |
303 | Similarly IFmode is the IBM long double format even if the default is IEEE | |
0bc36dec | 304 | 128-bit. Don't allow IFmode if -msoft-float. */ |
2c83faf8 | 305 | #define FLOAT128_IEEE_P(MODE) \ |
83cbbe3a MM |
306 | ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ |
307 | && ((MODE) == TFmode || (MODE) == TCmode)) \ | |
4304ccfd | 308 | || ((MODE) == KFmode) || ((MODE) == KCmode)) |
2c83faf8 MM |
309 | |
310 | #define FLOAT128_IBM_P(MODE) \ | |
83cbbe3a MM |
311 | ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ |
312 | && ((MODE) == TFmode || (MODE) == TCmode)) \ | |
11d8d07e | 313 | || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) |
2c83faf8 MM |
314 | |
315 | /* Helper macros to say whether a 128-bit floating point type can go in a | |
316 | single vector register, or whether it needs paired scalar values. */ | |
08213983 | 317 | #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) |
2c83faf8 MM |
318 | |
319 | #define FLOAT128_2REG_P(MODE) \ | |
320 | (FLOAT128_IBM_P (MODE) \ | |
321 | || ((MODE) == TDmode) \ | |
08213983 | 322 | || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) |
2c83faf8 MM |
323 | |
324 | /* Return true for floating point that does not use a vector register. */ | |
325 | #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ | |
326 | (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) | |
327 | ||
f62511da | 328 | /* Describe the vector unit used for arithmetic operations. */ |
cacf1ca8 MM |
329 | extern enum rs6000_vector rs6000_vector_unit[]; |
330 | ||
331 | #define VECTOR_UNIT_NONE_P(MODE) \ | |
332 | (rs6000_vector_unit[(MODE)] == VECTOR_NONE) | |
333 | ||
334 | #define VECTOR_UNIT_VSX_P(MODE) \ | |
335 | (rs6000_vector_unit[(MODE)] == VECTOR_VSX) | |
336 | ||
f62511da MM |
337 | #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ |
338 | (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) | |
339 | ||
cacf1ca8 MM |
340 | #define VECTOR_UNIT_ALTIVEC_P(MODE) \ |
341 | (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) | |
342 | ||
f62511da MM |
343 | #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ |
344 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ | |
345 | (int)VECTOR_VSX, \ | |
346 | (int)VECTOR_P8_VECTOR)) | |
347 | ||
348 | /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either | |
349 | altivec (VMX) or VSX vector instructions. P8 vector support is upwards | |
350 | compatible, so allow it as well, rather than changing all of the uses of the | |
351 | macro. */ | |
cacf1ca8 | 352 | #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ |
f62511da MM |
353 | (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ |
354 | (int)VECTOR_ALTIVEC, \ | |
355 | (int)VECTOR_P8_VECTOR)) | |
cacf1ca8 MM |
356 | |
357 | /* Describe whether to use VSX loads or Altivec loads. For now, just use the | |
358 | same unit as the vector unit we are using, but we may want to migrate to | |
359 | using VSX style loads even for types handled by altivec. */ | |
360 | extern enum rs6000_vector rs6000_vector_mem[]; | |
361 | ||
362 | #define VECTOR_MEM_NONE_P(MODE) \ | |
363 | (rs6000_vector_mem[(MODE)] == VECTOR_NONE) | |
364 | ||
365 | #define VECTOR_MEM_VSX_P(MODE) \ | |
366 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
367 | ||
f62511da MM |
368 | #define VECTOR_MEM_P8_VECTOR_P(MODE) \ |
369 | (rs6000_vector_mem[(MODE)] == VECTOR_VSX) | |
370 | ||
cacf1ca8 MM |
371 | #define VECTOR_MEM_ALTIVEC_P(MODE) \ |
372 | (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) | |
373 | ||
f62511da MM |
374 | #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ |
375 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ | |
376 | (int)VECTOR_VSX, \ | |
377 | (int)VECTOR_P8_VECTOR)) | |
378 | ||
cacf1ca8 | 379 | #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ |
f62511da MM |
380 | (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ |
381 | (int)VECTOR_ALTIVEC, \ | |
382 | (int)VECTOR_P8_VECTOR)) | |
cacf1ca8 MM |
383 | |
384 | /* Return the alignment of a given vector type, which is set based on the | |
385 | vector unit use. VSX for instance can load 32 or 64 bit aligned words | |
386 | without problems, while Altivec requires 128-bit aligned vectors. */ | |
387 | extern int rs6000_vector_align[]; | |
388 | ||
389 | #define VECTOR_ALIGN(MODE) \ | |
390 | ((rs6000_vector_align[(MODE)] != 0) \ | |
391 | ? rs6000_vector_align[(MODE)] \ | |
392 | : (int)GET_MODE_BITSIZE ((MODE))) | |
393 | ||
117f16fb MM |
394 | /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
395 | with scalar instructions. */ | |
396 | #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) | |
397 | ||
dd551aa1 MM |
398 | /* Element number of the 64-bit value in a 128-bit vector that can be accessed |
399 | with the ISA 3.0 MFVSRLD instructions. */ | |
400 | #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) | |
401 | ||
025d9908 KH |
402 | /* Alignment options for fields in structures for sub-targets following |
403 | AIX-like ABI. | |
404 | ALIGN_POWER word-aligns FP doubles (default AIX ABI). | |
405 | ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). | |
406 | ||
407 | Override the macro definitions when compiling libobjc to avoid undefined | |
408 | reference to rs6000_alignment_flags due to library's use of GCC alignment | |
409 | macros which use the macros below. */ | |
f676971a | 410 | |
025d9908 KH |
411 | #ifndef IN_TARGET_LIBS |
412 | #define MASK_ALIGN_POWER 0x00000000 | |
413 | #define MASK_ALIGN_NATURAL 0x00000001 | |
414 | #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) | |
415 | #else | |
416 | #define TARGET_ALIGN_NATURAL 0 | |
417 | #endif | |
6fa3f289 | 418 | |
6a8886e4 MM |
419 | /* We use values 126..128 to pick the appropriate long double type (IFmode, |
420 | KFmode, TFmode). */ | |
421 | #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) | |
602ea4d3 | 422 | #define TARGET_IEEEQUAD rs6000_ieeequad |
6fa3f289 | 423 | #define TARGET_ALTIVEC_ABI rs6000_altivec_abi |
cacf1ca8 | 424 | #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) |
6fa3f289 | 425 | |
7042fe5e | 426 | /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. |
2c2aa74d | 427 | Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ |
c3f8384f MM |
428 | #define TARGET_FCFID (TARGET_POWERPC64 \ |
429 | || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
430 | || TARGET_POPCNTB /* ISA 2.02 */ \ | |
431 | || TARGET_CMPB /* ISA 2.05 */ \ | |
2c2aa74d | 432 | || TARGET_POPCNTD) /* ISA 2.06 */ |
7042fe5e MM |
433 | |
434 | #define TARGET_FCTIDZ TARGET_FCFID | |
435 | #define TARGET_STFIWX TARGET_PPC_GFXOPT | |
436 | #define TARGET_LFIWAX TARGET_CMPB | |
437 | #define TARGET_LFIWZX TARGET_POPCNTD | |
438 | #define TARGET_FCFIDS TARGET_POPCNTD | |
439 | #define TARGET_FCFIDU TARGET_POPCNTD | |
440 | #define TARGET_FCFIDUS TARGET_POPCNTD | |
441 | #define TARGET_FCTIDUZ TARGET_POPCNTD | |
442 | #define TARGET_FCTIWUZ TARGET_POPCNTD | |
0299bc72 MM |
443 | #define TARGET_CTZ TARGET_MODULO |
444 | #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) | |
dd551aa1 | 445 | #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) |
7042fe5e | 446 | |
f62511da MM |
447 | #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) |
448 | #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) | |
a16a872d | 449 | #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) |
dd551aa1 MM |
450 | #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ |
451 | && TARGET_POWERPC64) | |
c5e74d9d | 452 | #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ |
6bd6f4f4 | 453 | && TARGET_POWERPC64) |
fba4b861 | 454 | |
fba4b861 MM |
455 | /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ |
456 | #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT | |
457 | #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) | |
458 | ||
87b44b83 AS |
459 | /* This wants to be set for p8 and newer. On p7, overlapping unaligned |
460 | loads are slow. */ | |
461 | #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX | |
f62511da MM |
462 | |
463 | /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present | |
464 | in power7, so conditionalize them on p8 features. TImode syncs need quad | |
465 | memory support. */ | |
b846c948 MM |
466 | #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ |
467 | || TARGET_QUAD_MEMORY_ATOMIC \ | |
468 | || TARGET_DIRECT_MOVE) | |
469 | ||
470 | #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC | |
f62511da | 471 | |
c6d5ff83 MM |
472 | /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need |
473 | to allocate the SDmode stack slot to get the value into the proper location | |
474 | in the register. */ | |
475 | #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) | |
476 | ||
21316320 MM |
477 | /* ISA 3.0 has new min/max functions that don't need fast math that are being |
478 | phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct | |
479 | answers if the arguments are not in the normal range. */ | |
2c2aa74d SB |
480 | #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ |
481 | && (TARGET_P9_MINMAX || !flag_trapping_math)) | |
21316320 | 482 | |
4d967549 MM |
483 | /* In switching from using target_flags to using rs6000_isa_flags, the options |
484 | machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map | |
485 | OPTION_MASK_<xxx> back into MASK_<xxx>. */ | |
486 | #define MASK_ALTIVEC OPTION_MASK_ALTIVEC | |
487 | #define MASK_CMPB OPTION_MASK_CMPB | |
f62511da | 488 | #define MASK_CRYPTO OPTION_MASK_CRYPTO |
4d967549 | 489 | #define MASK_DFP OPTION_MASK_DFP |
f62511da | 490 | #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE |
4d967549 MM |
491 | #define MASK_DLMZB OPTION_MASK_DLMZB |
492 | #define MASK_EABI OPTION_MASK_EABI | |
bbd35101 | 493 | #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD |
12fca96e | 494 | #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW |
4d967549 | 495 | #define MASK_FPRND OPTION_MASK_FPRND |
f62511da | 496 | #define MASK_P8_FUSION OPTION_MASK_P8_FUSION |
4d967549 | 497 | #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT |
0258b6e4 | 498 | #define MASK_HTM OPTION_MASK_HTM |
4d967549 MM |
499 | #define MASK_ISEL OPTION_MASK_ISEL |
500 | #define MASK_MFCRF OPTION_MASK_MFCRF | |
501 | #define MASK_MFPGPR OPTION_MASK_MFPGPR | |
502 | #define MASK_MULHW OPTION_MASK_MULHW | |
503 | #define MASK_MULTIPLE OPTION_MASK_MULTIPLE | |
504 | #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE | |
f62511da | 505 | #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR |
8fa97501 | 506 | #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR |
5a3a6a5e | 507 | #define MASK_P9_MISC OPTION_MASK_P9_MISC |
4d967549 MM |
508 | #define MASK_POPCNTB OPTION_MASK_POPCNTB |
509 | #define MASK_POPCNTD OPTION_MASK_POPCNTD | |
510 | #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT | |
511 | #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT | |
512 | #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION | |
513 | #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT | |
514 | #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN | |
4d967549 MM |
515 | #define MASK_UPDATE OPTION_MASK_UPDATE |
516 | #define MASK_VSX OPTION_MASK_VSX | |
517 | ||
518 | #ifndef IN_LIBGCC2 | |
519 | #define MASK_POWERPC64 OPTION_MASK_POWERPC64 | |
520 | #endif | |
521 | ||
522 | #ifdef TARGET_64BIT | |
523 | #define MASK_64BIT OPTION_MASK_64BIT | |
524 | #endif | |
525 | ||
4d967549 MM |
526 | #ifdef TARGET_LITTLE_ENDIAN |
527 | #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN | |
528 | #endif | |
529 | ||
4d967549 MM |
530 | #ifdef TARGET_REGNAMES |
531 | #define MASK_REGNAMES OPTION_MASK_REGNAMES | |
532 | #endif | |
533 | ||
534 | #ifdef TARGET_PROTOTYPE | |
535 | #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE | |
536 | #endif | |
537 | ||
4f45da44 KN |
538 | #ifdef TARGET_MODULO |
539 | #define RS6000_BTM_MODULO OPTION_MASK_MODULO | |
540 | #endif | |
541 | ||
542 | ||
7fa14a01 MM |
543 | /* For power systems, we want to enable Altivec and VSX builtins even if the |
544 | user did not use -maltivec or -mvsx to allow the builtins to be used inside | |
545 | of #pragma GCC target or the target attribute to change the code level for a | |
55928937 SB |
546 | given system. */ |
547 | ||
548 | #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ | |
549 | || TARGET_PPC_GPOPT /* 970/power4 */ \ | |
550 | || TARGET_POPCNTB /* ISA 2.02 */ \ | |
551 | || TARGET_CMPB /* ISA 2.05 */ \ | |
552 | || TARGET_POPCNTD /* ISA 2.06 */ \ | |
553 | || TARGET_ALTIVEC \ | |
554 | || TARGET_VSX \ | |
555 | || TARGET_HARD_FLOAT) | |
7fa14a01 | 556 | |
a7c6c6d6 OH |
557 | /* E500 cores only support plain "sync", not lwsync. */ |
558 | #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ | |
559 | || rs6000_cpu == PROCESSOR_PPC8548) | |
7fa14a01 MM |
560 | |
561 | ||
92902797 | 562 | /* Which machine supports the various reciprocal estimate instructions. */ |
2c2aa74d | 563 | #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) |
92902797 | 564 | |
2c2aa74d | 565 | #define TARGET_FRE (TARGET_HARD_FLOAT \ |
92902797 MM |
566 | && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) |
567 | ||
568 | #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ | |
2c2aa74d | 569 | && TARGET_PPC_GFXOPT) |
92902797 | 570 | |
2c2aa74d | 571 | #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ |
92902797 MM |
572 | && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) |
573 | ||
6019c0fc MM |
574 | /* Macro to say whether we can do optimizations where we need to do parts of |
575 | the calculation in 64-bit GPRs and then is transfered to the vector | |
427a7384 | 576 | registers. */ |
e0d32185 MM |
577 | #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ |
578 | && TARGET_P8_VECTOR \ | |
427a7384 | 579 | && TARGET_POWERPC64) |
e0d32185 | 580 | |
92902797 MM |
581 | /* Whether the various reciprocal divide/square root estimate instructions |
582 | exist, and whether we should automatically generate code for the instruction | |
583 | by default. */ | |
584 | #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ | |
585 | #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ | |
586 | #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ | |
587 | #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ | |
588 | ||
589 | extern unsigned char rs6000_recip_bits[]; | |
590 | ||
591 | #define RS6000_RECIP_HAVE_RE_P(MODE) \ | |
592 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) | |
593 | ||
594 | #define RS6000_RECIP_AUTO_RE_P(MODE) \ | |
595 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) | |
596 | ||
597 | #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ | |
598 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) | |
599 | ||
600 | #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ | |
601 | (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) | |
602 | ||
c5387660 JM |
603 | /* The default CPU for TARGET_OPTION_OVERRIDE. */ |
604 | #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT | |
f045b2c9 | 605 | |
a5c76ee6 | 606 | /* Target pragma. */ |
c58b209a NB |
607 | #define REGISTER_TARGET_PRAGMAS() do { \ |
608 | c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ | |
fd438373 | 609 | targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ |
2fab365e | 610 | targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ |
7fa14a01 | 611 | rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ |
a5c76ee6 ZW |
612 | } while (0) |
613 | ||
4c4eb375 GK |
614 | /* Target #defines. */ |
615 | #define TARGET_CPU_CPP_BUILTINS() \ | |
616 | rs6000_cpu_cpp_builtins (pfile) | |
647d340d | 617 | |
b4c522fa IB |
618 | /* Target CPU versions for D. */ |
619 | #define TARGET_D_CPU_VERSIONS rs6000_d_target_versions | |
620 | ||
647d340d JT |
621 | /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order |
622 | we're compiling for. Some configurations may need to override it. */ | |
623 | #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ | |
624 | do \ | |
625 | { \ | |
626 | if (BYTES_BIG_ENDIAN) \ | |
627 | { \ | |
628 | builtin_define ("__BIG_ENDIAN__"); \ | |
629 | builtin_define ("_BIG_ENDIAN"); \ | |
630 | builtin_assert ("machine=bigendian"); \ | |
631 | } \ | |
632 | else \ | |
633 | { \ | |
634 | builtin_define ("__LITTLE_ENDIAN__"); \ | |
635 | builtin_define ("_LITTLE_ENDIAN"); \ | |
636 | builtin_assert ("machine=littleendian"); \ | |
637 | } \ | |
638 | } \ | |
639 | while (0) | |
f045b2c9 | 640 | \f |
4c4eb375 | 641 | /* Target machine storage layout. */ |
f045b2c9 | 642 | |
13d39dbc | 643 | /* Define this macro if it is advisable to hold scalars in registers |
c81bebd7 | 644 | in a wider mode than that declared by the program. In such cases, |
ef457bda RK |
645 | the value is constrained to be within the bounds of the declared |
646 | type, but kept valid in the wider mode. The signedness of the | |
647 | extension may differ from that of the type. */ | |
648 | ||
39403d82 DE |
649 | #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ |
650 | if (GET_MODE_CLASS (MODE) == MODE_INT \ | |
96922e4c | 651 | && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \ |
b78d48dd | 652 | (MODE) = TARGET_32BIT ? SImode : DImode; |
39403d82 | 653 | |
f045b2c9 | 654 | /* Define this if most significant bit is lowest numbered |
82e41834 KH |
655 | in instructions that operate on numbered bit-fields. */ |
656 | /* That is true on RS/6000. */ | |
f045b2c9 RS |
657 | #define BITS_BIG_ENDIAN 1 |
658 | ||
659 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
660 | /* That is true on RS/6000. */ | |
661 | #define BYTES_BIG_ENDIAN 1 | |
662 | ||
663 | /* Define this if most significant word of a multiword number is lowest | |
c81bebd7 | 664 | numbered. |
f045b2c9 RS |
665 | |
666 | For RS/6000 we can decide arbitrarily since there are no machine | |
82e41834 | 667 | instructions for them. Might as well be consistent with bits and bytes. */ |
f045b2c9 RS |
668 | #define WORDS_BIG_ENDIAN 1 |
669 | ||
50751417 AM |
670 | /* This says that for the IBM long double the larger magnitude double |
671 | comes first. It's really a two element double array, and arrays | |
672 | don't index differently between little- and big-endian. */ | |
673 | #define LONG_DOUBLE_LARGE_FIRST 1 | |
674 | ||
2e360ab3 | 675 | #define MAX_BITS_PER_WORD 64 |
f045b2c9 RS |
676 | |
677 | /* Width of a word, in units (bytes). */ | |
c1aa3958 | 678 | #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) |
f34fc46e DE |
679 | #ifdef IN_LIBGCC2 |
680 | #define MIN_UNITS_PER_WORD UNITS_PER_WORD | |
681 | #else | |
ef0e53ce | 682 | #define MIN_UNITS_PER_WORD 4 |
f34fc46e | 683 | #endif |
2e360ab3 | 684 | #define UNITS_PER_FP_WORD 8 |
0ac081f6 | 685 | #define UNITS_PER_ALTIVEC_WORD 16 |
cacf1ca8 | 686 | #define UNITS_PER_VSX_WORD 16 |
f045b2c9 | 687 | |
915f619f JW |
688 | /* Type used for ptrdiff_t, as a string used in a declaration. */ |
689 | #define PTRDIFF_TYPE "int" | |
690 | ||
058ef853 DE |
691 | /* Type used for size_t, as a string used in a declaration. */ |
692 | #define SIZE_TYPE "long unsigned int" | |
693 | ||
f045b2c9 RS |
694 | /* Type used for wchar_t, as a string used in a declaration. */ |
695 | #define WCHAR_TYPE "short unsigned int" | |
696 | ||
697 | /* Width of wchar_t in bits. */ | |
698 | #define WCHAR_TYPE_SIZE 16 | |
699 | ||
9e654916 RK |
700 | /* A C expression for the size in bits of the type `short' on the |
701 | target machine. If you don't define this, the default is half a | |
702 | word. (If this would be less than one storage unit, it is | |
703 | rounded up to one unit.) */ | |
704 | #define SHORT_TYPE_SIZE 16 | |
705 | ||
706 | /* A C expression for the size in bits of the type `int' on the | |
707 | target machine. If you don't define this, the default is one | |
708 | word. */ | |
19d2d16f | 709 | #define INT_TYPE_SIZE 32 |
9e654916 RK |
710 | |
711 | /* A C expression for the size in bits of the type `long' on the | |
712 | target machine. If you don't define this, the default is one | |
713 | word. */ | |
2f3e5814 | 714 | #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) |
9e654916 RK |
715 | |
716 | /* A C expression for the size in bits of the type `long long' on the | |
717 | target machine. If you don't define this, the default is two | |
718 | words. */ | |
719 | #define LONG_LONG_TYPE_SIZE 64 | |
720 | ||
9e654916 RK |
721 | /* A C expression for the size in bits of the type `float' on the |
722 | target machine. If you don't define this, the default is one | |
723 | word. */ | |
724 | #define FLOAT_TYPE_SIZE 32 | |
725 | ||
726 | /* A C expression for the size in bits of the type `double' on the | |
727 | target machine. If you don't define this, the default is two | |
728 | words. */ | |
729 | #define DOUBLE_TYPE_SIZE 64 | |
730 | ||
6a8886e4 MM |
731 | /* A C expression for the size in bits of the type `long double' on the target |
732 | machine. If you don't define this, the default is two words. */ | |
6fa3f289 | 733 | #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size |
06f4e019 | 734 | |
5b8f5865 DE |
735 | /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ |
736 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
737 | ||
f045b2c9 RS |
738 | /* Width in bits of a pointer. |
739 | See also the macro `Pmode' defined below. */ | |
cacf1ca8 MM |
740 | extern unsigned rs6000_pointer_size; |
741 | #define POINTER_SIZE rs6000_pointer_size | |
f045b2c9 RS |
742 | |
743 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
2f3e5814 | 744 | #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) |
f045b2c9 RS |
745 | |
746 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
cacf1ca8 MM |
747 | #define STACK_BOUNDARY \ |
748 | ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ | |
749 | ? 64 : 128) | |
f045b2c9 RS |
750 | |
751 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
752 | #define FUNCTION_BOUNDARY 32 | |
753 | ||
754 | /* No data type wants to be aligned rounder than this. */ | |
0ac081f6 AH |
755 | #define BIGGEST_ALIGNMENT 128 |
756 | ||
f045b2c9 RS |
757 | /* Alignment of field after `int : 0' in a structure. */ |
758 | #define EMPTY_FIELD_BOUNDARY 32 | |
759 | ||
760 | /* Every structure's size must be a multiple of this. */ | |
761 | #define STRUCTURE_SIZE_BOUNDARY 8 | |
762 | ||
43a88a8c | 763 | /* A bit-field declared as `int' forces `int' alignment for the struct. */ |
f045b2c9 RS |
764 | #define PCC_BITFIELD_TYPE_MATTERS 1 |
765 | ||
69eff9da AM |
766 | enum data_align { align_abi, align_opt, align_both }; |
767 | ||
768 | /* A C expression to compute the alignment for a variables in the | |
769 | local store. TYPE is the data type, and ALIGN is the alignment | |
770 | that the object would ordinarily have. */ | |
771 | #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ | |
772 | rs6000_data_alignment (TYPE, ALIGN, align_both) | |
773 | ||
69eff9da AM |
774 | /* Make arrays of chars word-aligned for the same reasons. */ |
775 | #define DATA_ALIGNMENT(TYPE, ALIGN) \ | |
776 | rs6000_data_alignment (TYPE, ALIGN, align_opt) | |
777 | ||
e075a6cc | 778 | /* Align vectors to 128 bits. */ |
69eff9da AM |
779 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ |
780 | rs6000_data_alignment (TYPE, ALIGN, align_abi) | |
f045b2c9 | 781 | |
a0ab749a | 782 | /* Nonzero if move instructions will actually fail to work |
f045b2c9 | 783 | when given unaligned data. */ |
fdaff8ba | 784 | #define STRICT_ALIGNMENT 0 |
f045b2c9 RS |
785 | \f |
786 | /* Standard register usage. */ | |
787 | ||
788 | /* Number of actual hardware registers. | |
789 | The hardware registers are assigned numbers for the compiler | |
790 | from 0 to just below FIRST_PSEUDO_REGISTER. | |
791 | All registers that the compiler knows about must be given numbers, | |
792 | even those that are not normally considered general registers. | |
793 | ||
794 | RS/6000 has 32 fixed-point registers, 32 floating-point registers, | |
462f7901 SB |
795 | a count register, a link register, and 8 condition register fields, |
796 | which we view here as separate registers. AltiVec adds 32 vector | |
797 | registers and a VRsave register. | |
f045b2c9 RS |
798 | |
799 | In addition, the difference between the frame and argument pointers is | |
800 | a function of the number of registers saved, so we need to have a | |
801 | register for AP that will later be eliminated in favor of SP or FP. | |
802a0058 | 802 | This is a normal register, but it is fixed. |
f045b2c9 | 803 | |
802a0058 MM |
804 | We also create a pseudo register for float/int conversions, that will |
805 | really represent the memory location used. It is represented here as | |
806 | a register, in order to work around problems in allocating stack storage | |
7d5175e1 | 807 | in inline functions. |
802a0058 | 808 | |
7d5175e1 | 809 | Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame |
7a5add18 PB |
810 | pointer, which is eventually eliminated in favor of SP or FP. |
811 | ||
812 | The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ | |
7d5175e1 | 813 | |
346081bd | 814 | #define FIRST_PSEUDO_REGISTER 115 |
f045b2c9 | 815 | |
d6a7951f | 816 | /* This must be included for pre gcc 3.0 glibc compatibility. */ |
7d5f33bc | 817 | #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 |
62153b61 | 818 | |
e075a6cc | 819 | /* The sfp register and 3 HTM registers |
23742a9e RAR |
820 | aren't included in DWARF_FRAME_REGISTERS. */ |
821 | #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) | |
c19de7aa | 822 | |
ed1cf8ff | 823 | /* Use standard DWARF numbering for DWARF debugging information. */ |
3d36d470 | 824 | #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) |
ed1cf8ff | 825 | |
93c9d1ba | 826 | /* Use gcc hard register numbering for eh_frame. */ |
3d36d470 | 827 | #define DWARF_FRAME_REGNUM(REGNO) (REGNO) |
41f3a930 | 828 | |
ed1cf8ff GK |
829 | /* Map register numbers held in the call frame info that gcc has |
830 | collected using DWARF_FRAME_REGNUM to those that should be output in | |
3d36d470 UW |
831 | .debug_frame and .eh_frame. */ |
832 | #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ | |
833 | rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1) | |
ed1cf8ff | 834 | |
f045b2c9 RS |
835 | /* 1 for registers that have pervasive standard uses |
836 | and are not available for the register allocator. | |
837 | ||
5dead3e5 DJ |
838 | On RS/6000, r1 is used for the stack. On Darwin, r2 is available |
839 | as a local register; for all other OS's r2 is the TOC pointer. | |
f045b2c9 | 840 | |
a127c4e5 RK |
841 | On System V implementations, r13 is fixed and not available for use. */ |
842 | ||
f045b2c9 | 843 | #define FIXED_REGISTERS \ |
5dead3e5 | 844 | {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
845 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
846 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
847 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
36bd0c3e | 848 | 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ |
0ac081f6 AH |
849 | /* AltiVec registers. */ \ |
850 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
851 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 852 | 1, 1 \ |
346081bd | 853 | , 1, 1, 1, 1 \ |
0ac081f6 | 854 | } |
f045b2c9 RS |
855 | |
856 | /* 1 for registers not available across function calls. | |
857 | These must include the FIXED_REGISTERS and also any | |
858 | registers that can be used without being saved. | |
859 | The latter must include the registers where values are returned | |
860 | and the register where structure-value addresses are passed. | |
861 | Aside from that, you can include as many other registers as you like. */ | |
862 | ||
863 | #define CALL_USED_REGISTERS \ | |
a127c4e5 | 864 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ |
f045b2c9 RS |
865 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ |
866 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
867 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0ac081f6 AH |
868 | 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
869 | /* AltiVec registers. */ \ | |
870 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
871 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 872 | 1, 1 \ |
346081bd | 873 | , 1, 1, 1, 1 \ |
0ac081f6 AH |
874 | } |
875 | ||
289e96b2 AH |
876 | /* Like `CALL_USED_REGISTERS' except this macro doesn't require that |
877 | the entire set of `FIXED_REGISTERS' be included. | |
878 | (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). | |
879 | This macro is optional. If not specified, it defaults to the value | |
880 | of `CALL_USED_REGISTERS'. */ | |
f676971a | 881 | |
289e96b2 AH |
882 | #define CALL_REALLY_USED_REGISTERS \ |
883 | {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ | |
884 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
885 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ | |
886 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
0b390d60 | 887 | 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ |
289e96b2 AH |
888 | /* AltiVec registers. */ \ |
889 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
890 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ | |
5f004351 | 891 | 0, 0 \ |
346081bd | 892 | , 0, 0, 0, 0 \ |
289e96b2 | 893 | } |
f045b2c9 | 894 | |
28bcfd4d | 895 | #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) |
9ebbca7d | 896 | |
d62294f5 | 897 | #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) |
b427dd7a AM |
898 | #define FIRST_SAVED_FP_REGNO (14+32) |
899 | #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) | |
d62294f5 | 900 | |
f045b2c9 RS |
901 | /* List the order in which to allocate registers. Each register must be |
902 | listed once, even those in FIXED_REGISTERS. | |
903 | ||
904 | We allocate in the following order: | |
905 | fp0 (not saved or used for anything) | |
906 | fp13 - fp2 (not saved; incoming fp arg registers) | |
907 | fp1 (not saved; return value) | |
9390387d | 908 | fp31 - fp14 (saved; order given to save least number) |
36bd0c3e SB |
909 | cr7, cr5 (not saved or special) |
910 | cr6 (not saved, but used for vector operations) | |
5accd822 | 911 | cr1 (not saved, but used for FP operations) |
f045b2c9 | 912 | cr0 (not saved, but used for arithmetic operations) |
5accd822 | 913 | cr4, cr3, cr2 (saved) |
f045b2c9 | 914 | r9 (not saved; best for TImode) |
d44b26bd | 915 | r10, r8-r4 (not saved; highest first for less conflict with params) |
9390387d | 916 | r3 (not saved; return value register) |
d44b26bd AM |
917 | r11 (not saved; later alloc to help shrink-wrap) |
918 | r0 (not saved; cannot be base reg) | |
f045b2c9 RS |
919 | r31 - r13 (saved; order given to save least number) |
920 | r12 (not saved; if used for DImode or DFmode would use r13) | |
f045b2c9 RS |
921 | ctr (not saved; when we have the choice ctr is better) |
922 | lr (saved) | |
36bd0c3e | 923 | r1, r2, ap, ca (fixed) |
9390387d AM |
924 | v0 - v1 (not saved or used for anything) |
925 | v13 - v3 (not saved; incoming vector arg registers) | |
926 | v2 (not saved; incoming vector arg reg; return value) | |
927 | v19 - v14 (not saved or used for anything) | |
928 | v31 - v20 (saved; order given to save least number) | |
929 | vrsave, vscr (fixed) | |
7d5175e1 | 930 | sfp (fixed) |
0258b6e4 PB |
931 | tfhar (fixed) |
932 | tfiar (fixed) | |
933 | texasr (fixed) | |
0ac081f6 | 934 | */ |
f676971a | 935 | |
6b13641d DJ |
936 | #if FIXED_R2 == 1 |
937 | #define MAYBE_R2_AVAILABLE | |
938 | #define MAYBE_R2_FIXED 2, | |
939 | #else | |
940 | #define MAYBE_R2_AVAILABLE 2, | |
941 | #define MAYBE_R2_FIXED | |
942 | #endif | |
f045b2c9 | 943 | |
d44b26bd AM |
944 | #if FIXED_R13 == 1 |
945 | #define EARLY_R12 12, | |
946 | #define LATE_R12 | |
947 | #else | |
948 | #define EARLY_R12 | |
949 | #define LATE_R12 12, | |
950 | #endif | |
951 | ||
9390387d AM |
952 | #define REG_ALLOC_ORDER \ |
953 | {32, \ | |
f62511da MM |
954 | /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ |
955 | /* not use fr14 which is a saved register. */ \ | |
956 | 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ | |
9390387d AM |
957 | 33, \ |
958 | 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ | |
959 | 50, 49, 48, 47, 46, \ | |
273f3d4b | 960 | 68, 75, 73, 74, 69, 72, 71, 70, \ |
d44b26bd AM |
961 | MAYBE_R2_AVAILABLE \ |
962 | 9, 10, 8, 7, 6, 5, 4, \ | |
963 | 3, EARLY_R12 11, 0, \ | |
9390387d | 964 | 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ |
d44b26bd | 965 | 18, 17, 16, 15, 14, 13, LATE_R12 \ |
462f7901 | 966 | 66, 65, \ |
36bd0c3e | 967 | 1, MAYBE_R2_FIXED 67, 76, \ |
9390387d AM |
968 | /* AltiVec registers. */ \ |
969 | 77, 78, \ | |
970 | 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ | |
971 | 79, \ | |
972 | 96, 95, 94, 93, 92, 91, \ | |
973 | 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ | |
974 | 109, 110, \ | |
346081bd | 975 | 111, 112, 113, 114 \ |
0ac081f6 | 976 | } |
f045b2c9 RS |
977 | |
978 | /* True if register is floating-point. */ | |
979 | #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) | |
980 | ||
981 | /* True if register is a condition register. */ | |
1de43f85 | 982 | #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) |
f045b2c9 | 983 | |
815cdc52 | 984 | /* True if register is a condition register, but not cr0. */ |
1de43f85 | 985 | #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) |
815cdc52 | 986 | |
f045b2c9 | 987 | /* True if register is an integer register. */ |
7d5175e1 JJ |
988 | #define INT_REGNO_P(N) \ |
989 | ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) | |
f045b2c9 | 990 | |
f6b5d695 SB |
991 | /* True if register is the CA register. */ |
992 | #define CA_REGNO_P(N) ((N) == CA_REGNO) | |
802a0058 | 993 | |
0ac081f6 AH |
994 | /* True if register is an AltiVec register. */ |
995 | #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) | |
996 | ||
cacf1ca8 MM |
997 | /* True if register is a VSX register. */ |
998 | #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) | |
999 | ||
1000 | /* Alternate name for any vector register supporting floating point, no matter | |
1001 | which instruction set(s) are available. */ | |
1002 | #define VFLOAT_REGNO_P(N) \ | |
1003 | (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) | |
1004 | ||
1005 | /* Alternate name for any vector register supporting integer, no matter which | |
1006 | instruction set(s) are available. */ | |
1007 | #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) | |
1008 | ||
1009 | /* Alternate name for any vector register supporting logical operations, no | |
dd7a40e1 MM |
1010 | matter which instruction set(s) are available. Allow GPRs as well as the |
1011 | vector registers. */ | |
f62511da | 1012 | #define VLOGICAL_REGNO_P(N) \ |
dd7a40e1 MM |
1013 | (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ |
1014 | || (TARGET_VSX && FP_REGNO_P (N))) \ | |
cacf1ca8 | 1015 | |
79eefb0d | 1016 | /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate |
5ec6aff2 MM |
1017 | enough space to account for vectors in FP regs. However, TFmode/TDmode |
1018 | should not use VSX instructions to do a caller save. */ | |
dbcc9f08 | 1019 | #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ |
90b725f0 PB |
1020 | ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ |
1021 | ? (MODE) \ | |
1022 | : TARGET_VSX \ | |
1023 | && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ | |
1024 | && FP_REGNO_P (REGNO) \ | |
5ec6aff2 | 1025 | ? V2DFmode \ |
f7c12ec4 | 1026 | : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ |
5ec6aff2 | 1027 | ? DFmode \ |
f7c12ec4 | 1028 | : (MODE) == TDmode && FP_REGNO_P (REGNO) \ |
5ec6aff2 | 1029 | ? DImode \ |
79eefb0d PH |
1030 | : choose_hard_reg_mode ((REGNO), (NREGS), false)) |
1031 | ||
cacf1ca8 MM |
1032 | #define VSX_VECTOR_MODE(MODE) \ |
1033 | ((MODE) == V4SFmode \ | |
1034 | || (MODE) == V2DFmode) \ | |
1035 | ||
bdb60a10 MM |
1036 | /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not |
1037 | really a vector, but we want to treat it as a vector for moves, and | |
1038 | such. */ | |
1039 | ||
1040 | #define ALTIVEC_VECTOR_MODE(MODE) \ | |
1041 | ((MODE) == V16QImode \ | |
1042 | || (MODE) == V8HImode \ | |
1043 | || (MODE) == V4SFmode \ | |
1044 | || (MODE) == V4SImode \ | |
1045 | || FLOAT128_VECTOR_P (MODE)) | |
0ac081f6 | 1046 | |
dbcc9f08 MM |
1047 | #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ |
1048 | (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ | |
a16a872d | 1049 | || (MODE) == V2DImode || (MODE) == V1TImode) |
dbcc9f08 | 1050 | |
c8ae788f SB |
1051 | /* Post-reload, we can't use any new AltiVec registers, as we already |
1052 | emitted the vrsave mask. */ | |
1053 | ||
1054 | #define HARD_REGNO_RENAME_OK(SRC, DST) \ | |
6fb5fa3c | 1055 | (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) |
c8ae788f | 1056 | |
f045b2c9 RS |
1057 | /* Specify the cost of a branch insn; roughly the number of extra insns that |
1058 | should be added to avoid a branch. | |
1059 | ||
ef457bda | 1060 | Set this to 3 on the RS/6000 since that is roughly the average cost of an |
f045b2c9 RS |
1061 | unscheduled conditional branch. */ |
1062 | ||
3a4fd356 | 1063 | #define BRANCH_COST(speed_p, predictable_p) 3 |
f045b2c9 | 1064 | |
85e50b6b | 1065 | /* Override BRANCH_COST heuristic which empirically produces worse |
b8610a53 | 1066 | performance for removing short circuiting from the logical ops. */ |
85e50b6b | 1067 | |
b8610a53 | 1068 | #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 |
a3170dc6 | 1069 | |
f045b2c9 RS |
1070 | /* Specify the registers used for certain standard purposes. |
1071 | The values of these macros are register numbers. */ | |
1072 | ||
1073 | /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ | |
1074 | /* #define PC_REGNUM */ | |
1075 | ||
1076 | /* Register to use for pushing function arguments. */ | |
1077 | #define STACK_POINTER_REGNUM 1 | |
1078 | ||
1079 | /* Base register for access to local variables of the function. */ | |
7d5175e1 JJ |
1080 | #define HARD_FRAME_POINTER_REGNUM 31 |
1081 | ||
1082 | /* Base register for access to local variables of the function. */ | |
346081bd | 1083 | #define FRAME_POINTER_REGNUM 111 |
f045b2c9 | 1084 | |
f045b2c9 RS |
1085 | /* Base register for access to arguments of the function. */ |
1086 | #define ARG_POINTER_REGNUM 67 | |
1087 | ||
1088 | /* Place to put static chain when calling a function that requires it. */ | |
1089 | #define STATIC_CHAIN_REGNUM 11 | |
1090 | ||
26a2e6ae PB |
1091 | /* Base register for access to thread local storage variables. */ |
1092 | #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) | |
1093 | ||
f045b2c9 RS |
1094 | \f |
1095 | /* Define the classes of registers for register constraints in the | |
1096 | machine description. Also define ranges of constants. | |
1097 | ||
1098 | One of the classes must always be named ALL_REGS and include all hard regs. | |
1099 | If there is more than one class, another class must be named NO_REGS | |
1100 | and contain no registers. | |
1101 | ||
1102 | The name GENERAL_REGS must be the name of a class (or an alias for | |
1103 | another name such as ALL_REGS). This is the class of registers | |
1104 | that is allowed by "g" or "r" in a register constraint. | |
1105 | Also, registers outside this class are allocated only when | |
1106 | instructions express preferences for them. | |
1107 | ||
1108 | The classes must be numbered in nondecreasing order; that is, | |
1109 | a larger-numbered class must never be contained completely | |
1110 | in a smaller-numbered class. | |
1111 | ||
1112 | For any two classes, it is very desirable that there be another | |
1113 | class that represents their union. */ | |
c81bebd7 | 1114 | |
cacf1ca8 | 1115 | /* The RS/6000 has three types of registers, fixed-point, floating-point, and |
462f7901 | 1116 | condition registers, plus three special registers, CTR, and the link |
cacf1ca8 MM |
1117 | register. AltiVec adds a vector register class. VSX registers overlap the |
1118 | FPR registers and the Altivec registers. | |
f045b2c9 RS |
1119 | |
1120 | However, r0 is special in that it cannot be used as a base register. | |
1121 | So make a class for registers valid as base registers. | |
1122 | ||
1123 | Also, cr0 is the only condition code register that can be used in | |
0d86f538 | 1124 | arithmetic insns, so make a separate class for it. */ |
f045b2c9 | 1125 | |
ebedb4dd MM |
1126 | enum reg_class |
1127 | { | |
1128 | NO_REGS, | |
ebedb4dd MM |
1129 | BASE_REGS, |
1130 | GENERAL_REGS, | |
1131 | FLOAT_REGS, | |
0ac081f6 | 1132 | ALTIVEC_REGS, |
8beb65e3 | 1133 | VSX_REGS, |
0ac081f6 | 1134 | VRSAVE_REGS, |
5f004351 | 1135 | VSCR_REGS, |
0258b6e4 | 1136 | SPR_REGS, |
ebedb4dd | 1137 | NON_SPECIAL_REGS, |
ebedb4dd MM |
1138 | LINK_REGS, |
1139 | CTR_REGS, | |
1140 | LINK_OR_CTR_REGS, | |
1141 | SPECIAL_REGS, | |
1142 | SPEC_OR_GEN_REGS, | |
1143 | CR0_REGS, | |
ebedb4dd MM |
1144 | CR_REGS, |
1145 | NON_FLOAT_REGS, | |
f6b5d695 | 1146 | CA_REGS, |
ebedb4dd MM |
1147 | ALL_REGS, |
1148 | LIM_REG_CLASSES | |
1149 | }; | |
f045b2c9 RS |
1150 | |
1151 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
1152 | ||
82e41834 | 1153 | /* Give names of register classes as strings for dump file. */ |
f045b2c9 | 1154 | |
ebedb4dd MM |
1155 | #define REG_CLASS_NAMES \ |
1156 | { \ | |
1157 | "NO_REGS", \ | |
ebedb4dd MM |
1158 | "BASE_REGS", \ |
1159 | "GENERAL_REGS", \ | |
1160 | "FLOAT_REGS", \ | |
0ac081f6 | 1161 | "ALTIVEC_REGS", \ |
8beb65e3 | 1162 | "VSX_REGS", \ |
0ac081f6 | 1163 | "VRSAVE_REGS", \ |
5f004351 | 1164 | "VSCR_REGS", \ |
0258b6e4 | 1165 | "SPR_REGS", \ |
ebedb4dd | 1166 | "NON_SPECIAL_REGS", \ |
ebedb4dd MM |
1167 | "LINK_REGS", \ |
1168 | "CTR_REGS", \ | |
1169 | "LINK_OR_CTR_REGS", \ | |
1170 | "SPECIAL_REGS", \ | |
1171 | "SPEC_OR_GEN_REGS", \ | |
1172 | "CR0_REGS", \ | |
ebedb4dd MM |
1173 | "CR_REGS", \ |
1174 | "NON_FLOAT_REGS", \ | |
f6b5d695 | 1175 | "CA_REGS", \ |
ebedb4dd MM |
1176 | "ALL_REGS" \ |
1177 | } | |
f045b2c9 RS |
1178 | |
1179 | /* Define which registers fit in which classes. | |
1180 | This is an initializer for a vector of HARD_REG_SET | |
1181 | of length N_REG_CLASSES. */ | |
1182 | ||
23742a9e RAR |
1183 | #define REG_CLASS_CONTENTS \ |
1184 | { \ | |
1185 | /* NO_REGS. */ \ | |
3e2bca2e | 1186 | { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ |
23742a9e | 1187 | /* BASE_REGS. */ \ |
346081bd | 1188 | { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \ |
23742a9e | 1189 | /* GENERAL_REGS. */ \ |
346081bd | 1190 | { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \ |
23742a9e | 1191 | /* FLOAT_REGS. */ \ |
3e2bca2e | 1192 | { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ |
23742a9e | 1193 | /* ALTIVEC_REGS. */ \ |
3e2bca2e | 1194 | { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \ |
23742a9e | 1195 | /* VSX_REGS. */ \ |
3e2bca2e | 1196 | { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \ |
23742a9e | 1197 | /* VRSAVE_REGS. */ \ |
3e2bca2e | 1198 | { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ |
23742a9e | 1199 | /* VSCR_REGS. */ \ |
3e2bca2e | 1200 | { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \ |
23742a9e | 1201 | /* SPR_REGS. */ \ |
346081bd | 1202 | { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \ |
23742a9e | 1203 | /* NON_SPECIAL_REGS. */ \ |
346081bd | 1204 | { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \ |
23742a9e | 1205 | /* LINK_REGS. */ \ |
3e2bca2e | 1206 | { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \ |
23742a9e | 1207 | /* CTR_REGS. */ \ |
3e2bca2e | 1208 | { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \ |
23742a9e | 1209 | /* LINK_OR_CTR_REGS. */ \ |
3e2bca2e | 1210 | { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \ |
23742a9e | 1211 | /* SPECIAL_REGS. */ \ |
3e2bca2e | 1212 | { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \ |
23742a9e | 1213 | /* SPEC_OR_GEN_REGS. */ \ |
346081bd | 1214 | { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \ |
23742a9e | 1215 | /* CR0_REGS. */ \ |
3e2bca2e | 1216 | { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \ |
23742a9e | 1217 | /* CR_REGS. */ \ |
3e2bca2e | 1218 | { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \ |
23742a9e | 1219 | /* NON_FLOAT_REGS. */ \ |
346081bd | 1220 | { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \ |
23742a9e | 1221 | /* CA_REGS. */ \ |
3e2bca2e | 1222 | { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \ |
23742a9e | 1223 | /* ALL_REGS. */ \ |
346081bd | 1224 | { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \ |
ebedb4dd | 1225 | } |
f045b2c9 RS |
1226 | |
1227 | /* The same information, inverted: | |
1228 | Return the class number of the smallest class containing | |
1229 | reg number REGNO. This could be a conditional expression | |
1230 | or could index an array. */ | |
1231 | ||
cacf1ca8 MM |
1232 | extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; |
1233 | ||
cacf1ca8 | 1234 | #define REGNO_REG_CLASS(REGNO) \ |
e28c2052 | 1235 | (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ |
cacf1ca8 MM |
1236 | rs6000_regno_regclass[(REGNO)]) |
1237 | ||
a72c65c7 MM |
1238 | /* Register classes for various constraints that are based on the target |
1239 | switches. */ | |
1240 | enum r6000_reg_class_enum { | |
1241 | RS6000_CONSTRAINT_d, /* fpr registers for double values */ | |
1242 | RS6000_CONSTRAINT_f, /* fpr registers for single values */ | |
1243 | RS6000_CONSTRAINT_v, /* Altivec registers */ | |
1244 | RS6000_CONSTRAINT_wa, /* Any VSX register */ | |
d5906efc | 1245 | RS6000_CONSTRAINT_wb, /* Altivec register if ISA 3.0 vector. */ |
a72c65c7 | 1246 | RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ |
dd551aa1 | 1247 | RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ |
a72c65c7 | 1248 | RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ |
5e8586d7 | 1249 | RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ |
59f5868d MM |
1250 | RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ |
1251 | RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ | |
1252 | RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ | |
1253 | RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ | |
c6d5ff83 | 1254 | RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ |
f62511da | 1255 | RS6000_CONSTRAINT_wm, /* VSX register for direct move */ |
4e8a3a35 | 1256 | RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */ |
c477a667 MM |
1257 | RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */ |
1258 | RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */ | |
f62511da | 1259 | RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ |
a72c65c7 | 1260 | RS6000_CONSTRAINT_ws, /* VSX register for DF */ |
c6d5ff83 | 1261 | RS6000_CONSTRAINT_wt, /* VSX register for TImode */ |
5e8586d7 MM |
1262 | RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */ |
1263 | RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ | |
1264 | RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ | |
c6d5ff83 | 1265 | RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ |
5e8586d7 | 1266 | RS6000_CONSTRAINT_wy, /* VSX register for SF */ |
c6d5ff83 | 1267 | RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ |
99211352 | 1268 | RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ |
787c7a65 MM |
1269 | RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */ |
1270 | RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */ | |
1271 | RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */ | |
1272 | RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */ | |
a72c65c7 MM |
1273 | RS6000_CONSTRAINT_MAX |
1274 | }; | |
1275 | ||
1276 | extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; | |
f045b2c9 RS |
1277 | |
1278 | /* The class value for index registers, and the one for base regs. */ | |
1279 | #define INDEX_REG_CLASS GENERAL_REGS | |
1280 | #define BASE_REG_CLASS BASE_REGS | |
1281 | ||
cacf1ca8 MM |
1282 | /* Return whether a given register class can hold VSX objects. */ |
1283 | #define VSX_REG_CLASS_P(CLASS) \ | |
1284 | ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) | |
1285 | ||
59f5868d MM |
1286 | /* Return whether a given register class targets general purpose registers. */ |
1287 | #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) | |
1288 | ||
f045b2c9 RS |
1289 | /* Given an rtx X being reloaded into a reg required to be |
1290 | in class CLASS, return the class of reg to actually use. | |
1291 | In general this is just CLASS; but on some machines | |
c81bebd7 | 1292 | in some cases it is preferable to use a more restrictive class. |
f045b2c9 RS |
1293 | |
1294 | On the RS/6000, we have to return NO_REGS when we want to reload a | |
f676971a | 1295 | floating-point CONST_DOUBLE to force it to be copied to memory. |
1e66d555 GK |
1296 | |
1297 | We also don't want to reload integer values into floating-point | |
1298 | registers if we can at all help it. In fact, this can | |
37409796 | 1299 | cause reload to die, if it tries to generate a reload of CTR |
1e66d555 GK |
1300 | into a FP register and discovers it doesn't have the memory location |
1301 | required. | |
1302 | ||
1303 | ??? Would it be a good idea to have reload do the converse, that is | |
1304 | try to reload floating modes into FP registers if possible? | |
1305 | */ | |
f045b2c9 | 1306 | |
802a0058 | 1307 | #define PREFERRED_RELOAD_CLASS(X,CLASS) \ |
8beb65e3 | 1308 | rs6000_preferred_reload_class_ptr (X, CLASS) |
c81bebd7 | 1309 | |
f045b2c9 RS |
1310 | /* Return the register class of a scratch register needed to copy IN into |
1311 | or out of a register in CLASS in MODE. If it can be done directly, | |
1312 | NO_REGS is returned. */ | |
1313 | ||
1314 | #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ | |
8beb65e3 | 1315 | rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) |
f045b2c9 RS |
1316 | |
1317 | /* Return the maximum number of consecutive registers | |
1318 | needed to represent mode MODE in a register of class CLASS. | |
1319 | ||
cacf1ca8 MM |
1320 | On RS/6000, this is the size of MODE in words, except in the FP regs, where |
1321 | a single reg is enough for two words, unless we have VSX, where the FP | |
1322 | registers can hold 128 bits. */ | |
1323 | #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] | |
580d3230 | 1324 | |
f045b2c9 RS |
1325 | /* Stack layout; function entry, exit and calling. */ |
1326 | ||
1327 | /* Define this if pushing a word on the stack | |
1328 | makes the stack pointer a smaller address. */ | |
62f9f30b | 1329 | #define STACK_GROWS_DOWNWARD 1 |
f045b2c9 | 1330 | |
327e5343 FJ |
1331 | /* Offsets recorded in opcodes are a multiple of this alignment factor. */ |
1332 | #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) | |
1333 | ||
a4d05547 | 1334 | /* Define this to nonzero if the nominal address of the stack frame |
f045b2c9 RS |
1335 | is at the high-address end of the local variables; |
1336 | that is, each additional local variable allocated | |
1337 | goes at a more negative offset in the frame. | |
1338 | ||
1339 | On the RS/6000, we grow upwards, from the area after the outgoing | |
1340 | arguments. */ | |
de5a5fa1 MP |
1341 | #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ |
1342 | || (flag_sanitize & SANITIZE_ADDRESS) != 0) | |
f045b2c9 | 1343 | |
4697a36c | 1344 | /* Size of the fixed area on the stack */ |
9ebbca7d | 1345 | #define RS6000_SAVE_AREA \ |
b54214fe UW |
1346 | ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ |
1347 | << (TARGET_64BIT ? 1 : 0)) | |
4697a36c | 1348 | |
b54214fe UW |
1349 | /* Stack offset for toc save slot. */ |
1350 | #define RS6000_TOC_SAVE_SLOT \ | |
1351 | ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) | |
b6c9286a | 1352 | |
4697a36c | 1353 | /* Align an address */ |
4f59f9f2 | 1354 | #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) |
4697a36c | 1355 | |
f045b2c9 RS |
1356 | /* Offset within stack frame to start allocating local variables at. |
1357 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
1358 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
c81bebd7 | 1359 | of the first local allocated. |
f045b2c9 RS |
1360 | |
1361 | On the RS/6000, the frame pointer is the same as the stack pointer, | |
1362 | except for dynamic allocations. So we start after the fixed area and | |
a7790c71 DV |
1363 | outgoing parameter area. |
1364 | ||
1365 | If the function uses dynamic stack space (CALLS_ALLOCA is set), that | |
1366 | space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the | |
1367 | sizes of the fixed area and the parameter area must be a multiple of | |
1368 | STACK_BOUNDARY. */ | |
f045b2c9 | 1369 | |
2a31c321 RS |
1370 | #define RS6000_STARTING_FRAME_OFFSET \ |
1371 | (cfun->calls_alloca \ | |
1372 | ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ | |
1373 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ | |
1374 | : (RS6000_ALIGN (crtl->outgoing_args_size, \ | |
1375 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ | |
1376 | + RS6000_SAVE_AREA)) | |
802a0058 MM |
1377 | |
1378 | /* Offset from the stack pointer register to an item dynamically | |
1379 | allocated on the stack, e.g., by `alloca'. | |
1380 | ||
1381 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
1382 | length of the outgoing arguments. The default is correct for most | |
a7790c71 DV |
1383 | machines. See `function.c' for details. |
1384 | ||
1385 | This value must be a multiple of STACK_BOUNDARY (hard coded in | |
1386 | `emit-rtl.c'). */ | |
802a0058 | 1387 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
a20c5714 RS |
1388 | RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \ |
1389 | + STACK_POINTER_OFFSET, \ | |
a7790c71 | 1390 | (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) |
f045b2c9 RS |
1391 | |
1392 | /* If we generate an insn to push BYTES bytes, | |
1393 | this says how many the stack pointer really advances by. | |
1394 | On RS/6000, don't define this because there are no push insns. */ | |
1395 | /* #define PUSH_ROUNDING(BYTES) */ | |
1396 | ||
1397 | /* Offset of first parameter from the argument pointer register value. | |
1398 | On the RS/6000, we define the argument pointer to the start of the fixed | |
1399 | area. */ | |
4697a36c | 1400 | #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA |
f045b2c9 | 1401 | |
62153b61 JM |
1402 | /* Offset from the argument pointer register value to the top of |
1403 | stack. This is different from FIRST_PARM_OFFSET because of the | |
1404 | register save area. */ | |
1405 | #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 | |
1406 | ||
f045b2c9 RS |
1407 | /* Define this if stack space is still allocated for a parameter passed |
1408 | in a register. The value is the number of bytes allocated to this | |
1409 | area. */ | |
ddbb449f AM |
1410 | #define REG_PARM_STACK_SPACE(FNDECL) \ |
1411 | rs6000_reg_parm_stack_space ((FNDECL), false) | |
1412 | ||
1413 | /* Define this macro if space guaranteed when compiling a function body | |
1414 | is different to space required when making a call, a situation that | |
1415 | can arise with K&R style function definitions. */ | |
1416 | #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ | |
1417 | rs6000_reg_parm_stack_space ((FNDECL), true) | |
f045b2c9 RS |
1418 | |
1419 | /* Define this if the above stack space is to be considered part of the | |
1420 | space allocated by the caller. */ | |
81464b2c | 1421 | #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 |
f045b2c9 RS |
1422 | |
1423 | /* This is the difference between the logical top of stack and the actual sp. | |
1424 | ||
82e41834 | 1425 | For the RS/6000, sp points past the fixed area. */ |
4697a36c | 1426 | #define STACK_POINTER_OFFSET RS6000_SAVE_AREA |
f045b2c9 RS |
1427 | |
1428 | /* Define this if the maximum size of all the outgoing args is to be | |
1429 | accumulated and pushed during the prologue. The amount can be | |
38173d38 | 1430 | found in the variable crtl->outgoing_args_size. */ |
f73ad30e | 1431 | #define ACCUMULATE_OUTGOING_ARGS 1 |
f045b2c9 | 1432 | |
f045b2c9 RS |
1433 | /* Define how to find the value returned by a library function |
1434 | assuming the value has mode MODE. */ | |
1435 | ||
ded9bf77 | 1436 | #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) |
f045b2c9 | 1437 | |
6fa3f289 ZW |
1438 | /* DRAFT_V4_STRUCT_RET defaults off. */ |
1439 | #define DRAFT_V4_STRUCT_RET 0 | |
f607bc57 | 1440 | |
bd5bd7ac | 1441 | /* Let TARGET_RETURN_IN_MEMORY control what happens. */ |
f607bc57 | 1442 | #define DEFAULT_PCC_STRUCT_RETURN 0 |
f045b2c9 | 1443 | |
a260abc9 | 1444 | /* Mode of stack savearea. |
dfdfa60f DE |
1445 | FUNCTION is VOIDmode because calling convention maintains SP. |
1446 | BLOCK needs Pmode for SP. | |
a260abc9 DE |
1447 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ |
1448 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
dfdfa60f | 1449 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ |
c6d5ff83 | 1450 | : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) |
a260abc9 | 1451 | |
4697a36c MM |
1452 | /* Minimum and maximum general purpose registers used to hold arguments. */ |
1453 | #define GP_ARG_MIN_REG 3 | |
1454 | #define GP_ARG_MAX_REG 10 | |
1455 | #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) | |
1456 | ||
1457 | /* Minimum and maximum floating point registers used to hold arguments. */ | |
1458 | #define FP_ARG_MIN_REG 33 | |
7509c759 MM |
1459 | #define FP_ARG_AIX_MAX_REG 45 |
1460 | #define FP_ARG_V4_MAX_REG 40 | |
008e32c0 UW |
1461 | #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ |
1462 | ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) | |
4697a36c MM |
1463 | #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) |
1464 | ||
0ac081f6 AH |
1465 | /* Minimum and maximum AltiVec registers used to hold arguments. */ |
1466 | #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) | |
1467 | #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) | |
1468 | #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) | |
1469 | ||
b54214fe UW |
1470 | /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ |
1471 | #define AGGR_ARG_NUM_REG 8 | |
1472 | ||
4697a36c MM |
1473 | /* Return registers */ |
1474 | #define GP_ARG_RETURN GP_ARG_MIN_REG | |
1475 | #define FP_ARG_RETURN FP_ARG_MIN_REG | |
0ac081f6 | 1476 | #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) |
b54214fe UW |
1477 | #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ |
1478 | : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) | |
4304ccfd MM |
1479 | #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ |
1480 | ? (ALTIVEC_ARG_RETURN \ | |
08213983 | 1481 | + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ |
b54214fe | 1482 | : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) |
4697a36c | 1483 | |
7509c759 | 1484 | /* Flags for the call/call_value rtl operations set up by function_arg */ |
6a4cee5f | 1485 | #define CALL_NORMAL 0x00000000 /* no special processing */ |
9ebbca7d | 1486 | /* Bits in 0x00000001 are unused. */ |
6a4cee5f MM |
1487 | #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ |
1488 | #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ | |
1489 | #define CALL_LONG 0x00000008 /* always call indirect */ | |
b9599e46 | 1490 | #define CALL_LIBCALL 0x00000010 /* libcall */ |
7509c759 | 1491 | |
f57fe068 AM |
1492 | /* We don't have prologue and epilogue functions to save/restore |
1493 | everything for most ABIs. */ | |
1494 | #define WORLD_SAVE_P(INFO) 0 | |
1495 | ||
f045b2c9 RS |
1496 | /* 1 if N is a possible register number for a function value |
1497 | as seen by the caller. | |
1498 | ||
0ac081f6 | 1499 | On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ |
e87a88d3 AM |
1500 | #define FUNCTION_VALUE_REGNO_P(N) \ |
1501 | ((N) == GP_ARG_RETURN \ | |
202687fb | 1502 | || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ |
11d8d07e | 1503 | && TARGET_HARD_FLOAT) \ |
202687fb | 1504 | || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ |
b54214fe | 1505 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) |
f045b2c9 RS |
1506 | |
1507 | /* 1 if N is a possible register number for function argument passing. | |
0ac081f6 AH |
1508 | On RS/6000, these are r3-r10 and fp1-fp13. |
1509 | On AltiVec, v2 - v13 are used for passing vectors. */ | |
4697a36c | 1510 | #define FUNCTION_ARG_REGNO_P(N) \ |
202687fb MM |
1511 | (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ |
1512 | || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ | |
44688022 | 1513 | && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ |
202687fb | 1514 | || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ |
11d8d07e | 1515 | && TARGET_HARD_FLOAT)) |
f045b2c9 RS |
1516 | \f |
1517 | /* Define a data type for recording info about an argument list | |
1518 | during the scan of that argument list. This data type should | |
1519 | hold all necessary information about the function itself | |
1520 | and about the args processed so far, enough to enable macros | |
1521 | such as FUNCTION_ARG to determine where the next arg should go. | |
1522 | ||
1523 | On the RS/6000, this is a structure. The first element is the number of | |
1524 | total argument words, the second is used to store the next | |
1525 | floating-point register number, and the third says how many more args we | |
4697a36c MM |
1526 | have prototype types for. |
1527 | ||
4cc833b7 | 1528 | For ABI_V4, we treat these slightly differently -- `sysv_gregno' is |
07488f32 | 1529 | the next available GP register, `fregno' is the next available FP |
4cc833b7 RH |
1530 | register, and `words' is the number of words used on the stack. |
1531 | ||
bd227acc | 1532 | The varargs/stdarg support requires that this structure's size |
4cc833b7 | 1533 | be a multiple of sizeof(int). */ |
4697a36c MM |
1534 | |
1535 | typedef struct rs6000_args | |
1536 | { | |
4cc833b7 | 1537 | int words; /* # words used for passing GP registers */ |
6a4cee5f | 1538 | int fregno; /* next available FP register */ |
0ac081f6 | 1539 | int vregno; /* next available AltiVec register */ |
6a4cee5f | 1540 | int nargs_prototype; /* # args left in the current prototype */ |
6a4cee5f | 1541 | int prototype; /* Whether a prototype was defined */ |
a6c9bed4 | 1542 | int stdarg; /* Whether function is a stdarg function. */ |
6a4cee5f | 1543 | int call_cookie; /* Do special things for this call */ |
4cc833b7 | 1544 | int sysv_gregno; /* next available GP register */ |
0b5383eb DJ |
1545 | int intoffset; /* running offset in struct (darwin64) */ |
1546 | int use_stack; /* any part of struct on stack (darwin64) */ | |
a9ab25e2 IS |
1547 | int floats_in_gpr; /* count of SFmode floats taking up |
1548 | GPR space (darwin64) */ | |
0b5383eb | 1549 | int named; /* false for varargs params */ |
617718f7 | 1550 | int escapes; /* if function visible outside tu */ |
bdb60a10 | 1551 | int libcall; /* If this is a compiler generated call. */ |
4697a36c | 1552 | } CUMULATIVE_ARGS; |
f045b2c9 | 1553 | |
f045b2c9 RS |
1554 | /* Initialize a variable CUM of type CUMULATIVE_ARGS |
1555 | for a call to a function whose data type is FNTYPE. | |
1556 | For a library call, FNTYPE is 0. */ | |
1557 | ||
617718f7 AM |
1558 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ |
1559 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ | |
1560 | N_NAMED_ARGS, FNDECL, VOIDmode) | |
f045b2c9 RS |
1561 | |
1562 | /* Similar, but when scanning the definition of a procedure. We always | |
1563 | set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ | |
1564 | ||
0f6937fe | 1565 | #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ |
617718f7 AM |
1566 | init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ |
1567 | 1000, current_function_decl, VOIDmode) | |
b9599e46 FS |
1568 | |
1569 | /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ | |
1570 | ||
1571 | #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ | |
617718f7 AM |
1572 | init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ |
1573 | 0, NULL_TREE, MODE) | |
f045b2c9 | 1574 | |
6e985040 | 1575 | #define PAD_VARARGS_DOWN \ |
76b0cbf8 | 1576 | (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) |
2a55fd42 | 1577 | |
f045b2c9 | 1578 | /* Output assembler code to FILE to increment profiler label # LABELNO |
58a39e45 | 1579 | for profiling a function entry. */ |
f045b2c9 RS |
1580 | |
1581 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
58a39e45 | 1582 | output_function_profiler ((FILE), (LABELNO)); |
f045b2c9 RS |
1583 | |
1584 | /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, | |
1585 | the stack pointer does not matter. No definition is equivalent to | |
1586 | always zero. | |
1587 | ||
a0ab749a | 1588 | On the RS/6000, this is nonzero because we can restore the stack from |
f045b2c9 RS |
1589 | its backpointer, which we maintain. */ |
1590 | #define EXIT_IGNORE_STACK 1 | |
1591 | ||
a701949a FS |
1592 | /* Define this macro as a C expression that is nonzero for registers |
1593 | that are used by the epilogue or the return' pattern. The stack | |
1594 | and frame pointer registers are already be assumed to be used as | |
1595 | needed. */ | |
1596 | ||
83720594 | 1597 | #define EPILOGUE_USES(REGNO) \ |
1de43f85 | 1598 | ((reload_completed && (REGNO) == LR_REGNO) \ |
b1765bde | 1599 | || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ |
cacf1ca8 | 1600 | || (crtl->calls_eh_return \ |
3553b09d | 1601 | && TARGET_AIX \ |
ff3867ae | 1602 | && (REGNO) == 2)) |
2bfcf297 | 1603 | |
f045b2c9 | 1604 | \f |
f045b2c9 RS |
1605 | /* Length in units of the trampoline for entering a nested function. */ |
1606 | ||
b6c9286a | 1607 | #define TRAMPOLINE_SIZE rs6000_trampoline_size () |
f045b2c9 | 1608 | \f |
f33985c6 | 1609 | /* Definitions for __builtin_return_address and __builtin_frame_address. |
893fc0a0 | 1610 | __builtin_return_address (0) should give link register (LR_REGNO), enable |
82e41834 | 1611 | this. */ |
f33985c6 MS |
1612 | /* This should be uncommented, so that the link register is used, but |
1613 | currently this would result in unmatched insns and spilling fixed | |
1614 | registers so we'll leave it for another day. When these problems are | |
1615 | taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. | |
1616 | (mrs) */ | |
1617 | /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ | |
f09d4c33 | 1618 | |
b6c9286a MM |
1619 | /* Number of bytes into the frame return addresses can be found. See |
1620 | rs6000_stack_info in rs6000.c for more information on how the different | |
1621 | abi's store the return address. */ | |
008e32c0 UW |
1622 | #define RETURN_ADDRESS_OFFSET \ |
1623 | ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) | |
f09d4c33 | 1624 | |
f33985c6 MS |
1625 | /* The current return address is in link register (65). The return address |
1626 | of anything farther back is accessed normally at an offset of 8 from the | |
1627 | frame pointer. */ | |
71f123ca FS |
1628 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
1629 | (rs6000_return_addr (COUNT, FRAME)) | |
1630 | ||
f33985c6 | 1631 | \f |
f045b2c9 RS |
1632 | /* Definitions for register eliminations. |
1633 | ||
1634 | We have two registers that can be eliminated on the RS/6000. First, the | |
1635 | frame pointer register can often be eliminated in favor of the stack | |
1636 | pointer register. Secondly, the argument pointer register can always be | |
642a35f1 JW |
1637 | eliminated; it is replaced with either the stack or frame pointer. |
1638 | ||
1639 | In addition, we use the elimination mechanism to see if r30 is needed | |
1640 | Initially we assume that it isn't. If it is, we spill it. This is done | |
1641 | by making it an eliminable register. We replace it with itself so that | |
1642 | if it isn't needed, then existing uses won't be modified. */ | |
f045b2c9 RS |
1643 | |
1644 | /* This is an array of structures. Each structure initializes one pair | |
1645 | of eliminable registers. The "from" register number is given first, | |
1646 | followed by "to". Eliminations of the same "from" register are listed | |
1647 | in order of preference. */ | |
7d5175e1 JJ |
1648 | #define ELIMINABLE_REGS \ |
1649 | {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1650 | { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1651 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
1652 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
1653 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
97b23853 | 1654 | { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } |
f045b2c9 | 1655 | |
f045b2c9 RS |
1656 | /* Define the offset between two registers, one to be eliminated, and the other |
1657 | its replacement, at the start of a routine. */ | |
d1d0c603 JJ |
1658 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
1659 | ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) | |
f045b2c9 RS |
1660 | \f |
1661 | /* Addressing modes, and classification of registers for them. */ | |
1662 | ||
940da324 JL |
1663 | #define HAVE_PRE_DECREMENT 1 |
1664 | #define HAVE_PRE_INCREMENT 1 | |
6fb5fa3c DB |
1665 | #define HAVE_PRE_MODIFY_DISP 1 |
1666 | #define HAVE_PRE_MODIFY_REG 1 | |
f045b2c9 RS |
1667 | |
1668 | /* Macros to check register numbers against specific register classes. */ | |
1669 | ||
1670 | /* These assume that REGNO is a hard or pseudo reg number. | |
1671 | They give nonzero only if REGNO is a hard reg of the suitable class | |
1672 | or a pseudo reg currently allocated to a suitable hard reg. | |
1673 | Since they use reg_renumber, they are safe only once reg_renumber | |
aeb9f7cf SB |
1674 | has been allocated, which happens in reginfo.c during register |
1675 | allocation. */ | |
f045b2c9 RS |
1676 | |
1677 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
1678 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1679 | ? (REGNO) <= 31 || (REGNO) == 67 \ | |
7d5175e1 | 1680 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1681 | : (reg_renumber[REGNO] >= 0 \ |
7d5175e1 JJ |
1682 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1683 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
f045b2c9 RS |
1684 | |
1685 | #define REGNO_OK_FOR_BASE_P(REGNO) \ | |
1686 | ((REGNO) < FIRST_PSEUDO_REGISTER \ | |
1687 | ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ | |
7d5175e1 | 1688 | || (REGNO) == FRAME_POINTER_REGNUM \ |
f045b2c9 | 1689 | : (reg_renumber[REGNO] > 0 \ |
7d5175e1 JJ |
1690 | && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ |
1691 | || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) | |
c6c3dba9 PB |
1692 | |
1693 | /* Nonzero if X is a hard reg that can be used as an index | |
1694 | or if it is a pseudo reg in the non-strict case. */ | |
1695 | #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ | |
1696 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
1697 | || REGNO_OK_FOR_INDEX_P (REGNO (X))) | |
1698 | ||
1699 | /* Nonzero if X is a hard reg that can be used as a base reg | |
1700 | or if it is a pseudo reg in the non-strict case. */ | |
1701 | #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ | |
1702 | ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
1703 | || REGNO_OK_FOR_BASE_P (REGNO (X))) | |
1704 | ||
f045b2c9 RS |
1705 | \f |
1706 | /* Maximum number of registers that can appear in a valid memory address. */ | |
1707 | ||
1708 | #define MAX_REGS_PER_ADDRESS 2 | |
1709 | ||
1710 | /* Recognize any constant value that is a valid address. */ | |
1711 | ||
6eff269e BK |
1712 | #define CONSTANT_ADDRESS_P(X) \ |
1713 | (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ | |
1714 | || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ | |
1715 | || GET_CODE (X) == HIGH) | |
f045b2c9 | 1716 | |
48d72335 | 1717 | #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) |
66180ff3 | 1718 | #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ |
76492753 PB |
1719 | && EASY_VECTOR_15((n) >> 1) \ |
1720 | && ((n) & 1) == 0) | |
48d72335 | 1721 | |
29e6733c | 1722 | #define EASY_VECTOR_MSB(n,mode) \ |
683be46f | 1723 | ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ |
29e6733c MM |
1724 | ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) |
1725 | ||
f045b2c9 | 1726 | \f |
a260abc9 DE |
1727 | /* Try a machine-dependent way of reloading an illegitimate address |
1728 | operand. If we find one, push the reload and jump to WIN. This | |
1729 | macro is used in only one place: `find_reloads_address' in reload.c. | |
1730 | ||
f676971a | 1731 | Implemented on rs6000 by rs6000_legitimize_reload_address. |
24ea750e | 1732 | Note that (X) is evaluated twice; this is safe in current usage. */ |
f676971a | 1733 | |
a9098fd0 GK |
1734 | #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ |
1735 | do { \ | |
24ea750e | 1736 | int win; \ |
8beb65e3 | 1737 | (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ |
24ea750e DJ |
1738 | (int)(TYPE), (IND_LEVELS), &win); \ |
1739 | if ( win ) \ | |
1740 | goto WIN; \ | |
a260abc9 DE |
1741 | } while (0) |
1742 | ||
944258eb | 1743 | #define FIND_BASE_TERM rs6000_find_base_term |
766a866c MM |
1744 | \f |
1745 | /* The register number of the register used to address a table of | |
1746 | static data addresses in memory. In some cases this register is | |
1747 | defined by a processor's "application binary interface" (ABI). | |
1748 | When this macro is defined, RTL is generated for this register | |
1749 | once, as with the stack pointer and frame pointer registers. If | |
1750 | this macro is not defined, it is up to the machine-dependent files | |
1751 | to allocate such a register (if necessary). */ | |
1752 | ||
1db02437 | 1753 | #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 |
24f77f59 AM |
1754 | #define PIC_OFFSET_TABLE_REGNUM \ |
1755 | (TARGET_TOC ? TOC_REGISTER \ | |
1756 | : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ | |
1757 | : INVALID_REGNUM) | |
766a866c | 1758 | |
97b23853 | 1759 | #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) |
9ebbca7d | 1760 | |
766a866c MM |
1761 | /* Define this macro if the register defined by |
1762 | `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define | |
089a05b8 | 1763 | this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ |
766a866c MM |
1764 | |
1765 | /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ | |
1766 | ||
766a866c MM |
1767 | /* A C expression that is nonzero if X is a legitimate immediate |
1768 | operand on the target machine when generating position independent | |
1769 | code. You can assume that X satisfies `CONSTANT_P', so you need | |
1770 | not check this. You can also assume FLAG_PIC is true, so you need | |
1771 | not check it either. You need not define this macro if all | |
1772 | constants (including `SYMBOL_REF') can be immediate operands when | |
1773 | generating position independent code. */ | |
1774 | ||
1775 | /* #define LEGITIMATE_PIC_OPERAND_P (X) */ | |
f045b2c9 | 1776 | \f |
f045b2c9 RS |
1777 | /* Specify the machine mode that this machine uses |
1778 | for the index in the tablejump instruction. */ | |
e1565e65 | 1779 | #define CASE_VECTOR_MODE SImode |
f045b2c9 | 1780 | |
18543a22 ILT |
1781 | /* Define as C expression which evaluates to nonzero if the tablejump |
1782 | instruction expects the table to contain offsets from the address of the | |
1783 | table. | |
82e41834 | 1784 | Do not define this if the table should contain absolute addresses. */ |
18543a22 | 1785 | #define CASE_VECTOR_PC_RELATIVE 1 |
f045b2c9 | 1786 | |
f045b2c9 RS |
1787 | /* Define this as 1 if `char' should by default be signed; else as 0. */ |
1788 | #define DEFAULT_SIGNED_CHAR 0 | |
1789 | ||
c1618c0c DE |
1790 | /* An integer expression for the size in bits of the largest integer machine |
1791 | mode that should actually be used. */ | |
1792 | ||
1793 | /* Allow pairs of registers to be used, which is the intent of the default. */ | |
1794 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) | |
1795 | ||
f045b2c9 RS |
1796 | /* Max number of bytes we can move from memory to memory |
1797 | in one reasonably fast instruction. */ | |
2f3e5814 | 1798 | #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) |
7e69e155 | 1799 | #define MAX_MOVE_MAX 8 |
f045b2c9 RS |
1800 | |
1801 | /* Nonzero if access to memory by bytes is no faster than for words. | |
a0ab749a | 1802 | Also nonzero if doing byte operations (specifically shifts) in registers |
f045b2c9 RS |
1803 | is undesirable. */ |
1804 | #define SLOW_BYTE_ACCESS 1 | |
1805 | ||
9a63901f RK |
1806 | /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD |
1807 | will either zero-extend or sign-extend. The value of this macro should | |
1808 | be the code that says which one of the two operations is implicitly | |
f822d252 | 1809 | done, UNKNOWN if none. */ |
9a63901f | 1810 | #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND |
225211e2 RK |
1811 | |
1812 | /* Define if loading short immediate values into registers sign extends. */ | |
58f2ae18 | 1813 | #define SHORT_IMMEDIATES_SIGN_EXTEND 1 |
fdaff8ba | 1814 | \f |
94993909 | 1815 | /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ |
d865b122 | 1816 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
bb0f9c02 | 1817 | ((VALUE) = GET_MODE_BITSIZE (MODE), 2) |
d865b122 | 1818 | |
0299bc72 | 1819 | /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of |
bb0f9c02 SB |
1820 | zero. The hardware instructions added in Power9 and the sequences using |
1821 | popcount return 32 or 64. */ | |
0299bc72 | 1822 | #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ |
bb0f9c02 SB |
1823 | (TARGET_CTZ || TARGET_POPCNTD \ |
1824 | ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ | |
1825 | : ((VALUE) = -1, 2)) | |
94993909 | 1826 | |
f045b2c9 RS |
1827 | /* Specify the machine mode that pointers have. |
1828 | After generation of rtl, the compiler makes no further distinction | |
1829 | between pointers and any other objects of this machine mode. */ | |
501623d4 RS |
1830 | extern scalar_int_mode rs6000_pmode; |
1831 | #define Pmode rs6000_pmode | |
f045b2c9 | 1832 | |
a3c9585f | 1833 | /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ |
4c81e946 FJ |
1834 | #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) |
1835 | ||
f045b2c9 | 1836 | /* Mode of a function address in a call instruction (for indexing purposes). |
f045b2c9 | 1837 | Doesn't matter on RS/6000. */ |
5b71a4e7 | 1838 | #define FUNCTION_MODE SImode |
f045b2c9 RS |
1839 | |
1840 | /* Define this if addresses of constant functions | |
1841 | shouldn't be put through pseudo regs where they can be cse'd. | |
1842 | Desirable on machines where ordinary constants are expensive | |
1843 | but a CALL with constant address is cheap. */ | |
1e8552c2 | 1844 | #define NO_FUNCTION_CSE 1 |
f045b2c9 | 1845 | |
d969caf8 | 1846 | /* Define this to be nonzero if shift instructions ignore all but the low-order |
6febd581 RK |
1847 | few bits. |
1848 | ||
1849 | The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED | |
1850 | have been dropped from the PowerPC architecture. */ | |
c28a7c24 | 1851 | #define SHIFT_COUNT_TRUNCATED 0 |
f045b2c9 | 1852 | |
f045b2c9 RS |
1853 | /* Adjust the length of an INSN. LENGTH is the currently-computed length and |
1854 | should be adjusted to reflect any required changes. This macro is used when | |
1855 | there is some systematic length adjustment required that would be difficult | |
1856 | to express in the length attribute. */ | |
1857 | ||
1858 | /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ | |
1859 | ||
39a10a29 GK |
1860 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a |
1861 | COMPARE, return the mode to be used for the comparison. For | |
1862 | floating-point, CCFPmode should be used. CCUNSmode should be used | |
1863 | for unsigned comparisons. CCEQmode should be used when we are | |
1864 | doing an inequality comparison on the result of a | |
1865 | comparison. CCmode should be used in all other cases. */ | |
c5defebb | 1866 | |
b565a316 | 1867 | #define SELECT_CC_MODE(OP,X,Y) \ |
ebb109ad | 1868 | (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ |
c5defebb | 1869 | : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ |
ec8e098d | 1870 | : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ |
c5defebb | 1871 | ? CCEQmode : CCmode)) |
f045b2c9 | 1872 | |
b39358e1 GK |
1873 | /* Can the condition code MODE be safely reversed? This is safe in |
1874 | all cases on this port, because at present it doesn't use the | |
1875 | trapping FP comparisons (fcmpo). */ | |
1876 | #define REVERSIBLE_CC_MODE(MODE) 1 | |
1877 | ||
1878 | /* Given a condition code and a mode, return the inverse condition. */ | |
1879 | #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) | |
1880 | ||
d9664254 SB |
1881 | \f |
1882 | /* Target cpu costs. */ | |
1883 | ||
1884 | struct processor_costs { | |
1885 | const int mulsi; /* cost of SImode multiplication. */ | |
1886 | const int mulsi_const; /* cost of SImode multiplication by constant. */ | |
1887 | const int mulsi_const9; /* cost of SImode mult by short constant. */ | |
1888 | const int muldi; /* cost of DImode multiplication. */ | |
1889 | const int divsi; /* cost of SImode division. */ | |
1890 | const int divdi; /* cost of DImode division. */ | |
1891 | const int fp; /* cost of simple SFmode and DFmode insns. */ | |
1892 | const int dmul; /* cost of DFmode multiplication (and fmadd). */ | |
1893 | const int sdiv; /* cost of SFmode division (fdivs). */ | |
1894 | const int ddiv; /* cost of DFmode division (fdiv). */ | |
1895 | const int cache_line_size; /* cache line size in bytes. */ | |
1896 | const int l1_cache_size; /* size of l1 cache, in kilobytes. */ | |
1897 | const int l2_cache_size; /* size of l2 cache, in kilobytes. */ | |
1898 | const int simultaneous_prefetches; /* number of parallel prefetch | |
1899 | operations. */ | |
1900 | const int sfdf_convert; /* cost of SF->DF conversion. */ | |
1901 | }; | |
1902 | ||
1903 | extern const struct processor_costs *rs6000_cost; | |
f045b2c9 RS |
1904 | \f |
1905 | /* Control the assembler format that we output. */ | |
1906 | ||
1b279f39 DE |
1907 | /* A C string constant describing how to begin a comment in the target |
1908 | assembler language. The compiler assumes that the comment will end at | |
1909 | the end of the line. */ | |
1910 | #define ASM_COMMENT_START " #" | |
6b67933e | 1911 | |
38c1f2d7 MM |
1912 | /* Flag to say the TOC is initialized */ |
1913 | extern int toc_initialized; | |
1914 | ||
f045b2c9 RS |
1915 | /* Macro to output a special constant pool entry. Go to WIN if we output |
1916 | it. Otherwise, it is written the usual way. | |
1917 | ||
1918 | On the RS/6000, toc entries are handled this way. */ | |
1919 | ||
a9098fd0 GK |
1920 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ |
1921 | { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ | |
1922 | { \ | |
1923 | output_toc (FILE, X, LABELNO, MODE); \ | |
1924 | goto WIN; \ | |
1925 | } \ | |
f045b2c9 RS |
1926 | } |
1927 | ||
ebd97b96 DE |
1928 | #ifdef HAVE_GAS_WEAK |
1929 | #define RS6000_WEAK 1 | |
1930 | #else | |
1931 | #define RS6000_WEAK 0 | |
1932 | #endif | |
290ad355 | 1933 | |
79c4e63f AM |
1934 | #if RS6000_WEAK |
1935 | /* Used in lieu of ASM_WEAKEN_LABEL. */ | |
8d91472f DE |
1936 | #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ |
1937 | rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) | |
79c4e63f AM |
1938 | #endif |
1939 | ||
ff2d10c1 AO |
1940 | #if HAVE_GAS_WEAKREF |
1941 | #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ | |
1942 | do \ | |
1943 | { \ | |
1944 | fputs ("\t.weakref\t", (FILE)); \ | |
1945 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
1946 | fputs (", ", (FILE)); \ | |
1947 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
1948 | if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ | |
1949 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ | |
1950 | { \ | |
1951 | fputs ("\n\t.weakref\t.", (FILE)); \ | |
1952 | RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ | |
1953 | fputs (", .", (FILE)); \ | |
1954 | RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ | |
1955 | } \ | |
1956 | fputc ('\n', (FILE)); \ | |
1957 | } while (0) | |
1958 | #endif | |
1959 | ||
79c4e63f AM |
1960 | /* This implements the `alias' attribute. */ |
1961 | #undef ASM_OUTPUT_DEF_FROM_DECLS | |
1962 | #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ | |
1963 | do \ | |
1964 | { \ | |
1965 | const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ | |
1966 | const char *name = IDENTIFIER_POINTER (TARGET); \ | |
1967 | if (TREE_CODE (DECL) == FUNCTION_DECL \ | |
85b776df | 1968 | && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ |
79c4e63f AM |
1969 | { \ |
1970 | if (TREE_PUBLIC (DECL)) \ | |
1971 | { \ | |
1972 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ | |
1973 | { \ | |
1974 | fputs ("\t.globl\t.", FILE); \ | |
cbaaba19 | 1975 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f AM |
1976 | putc ('\n', FILE); \ |
1977 | } \ | |
1978 | } \ | |
1979 | else if (TARGET_XCOFF) \ | |
1980 | { \ | |
c167bc5b DE |
1981 | if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ |
1982 | { \ | |
1983 | fputs ("\t.lglobl\t.", FILE); \ | |
1984 | RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
1985 | putc ('\n', FILE); \ | |
1986 | fputs ("\t.lglobl\t", FILE); \ | |
1987 | RS6000_OUTPUT_BASENAME (FILE, alias); \ | |
1988 | putc ('\n', FILE); \ | |
1989 | } \ | |
79c4e63f AM |
1990 | } \ |
1991 | fputs ("\t.set\t.", FILE); \ | |
cbaaba19 | 1992 | RS6000_OUTPUT_BASENAME (FILE, alias); \ |
79c4e63f | 1993 | fputs (",.", FILE); \ |
cbaaba19 | 1994 | RS6000_OUTPUT_BASENAME (FILE, name); \ |
79c4e63f AM |
1995 | fputc ('\n', FILE); \ |
1996 | } \ | |
1997 | ASM_OUTPUT_DEF (FILE, alias, name); \ | |
1998 | } \ | |
1999 | while (0) | |
290ad355 | 2000 | |
1bc7c5b6 ZW |
2001 | #define TARGET_ASM_FILE_START rs6000_file_start |
2002 | ||
f045b2c9 RS |
2003 | /* Output to assembler file text saying following lines |
2004 | may contain character constants, extra white space, comments, etc. */ | |
2005 | ||
2006 | #define ASM_APP_ON "" | |
2007 | ||
2008 | /* Output to assembler file text saying following lines | |
2009 | no longer contain unusual constructs. */ | |
2010 | ||
2011 | #define ASM_APP_OFF "" | |
2012 | ||
f045b2c9 RS |
2013 | /* How to refer to registers in assembler output. |
2014 | This sequence is indexed by compiler's hard-register-number (see above). */ | |
2015 | ||
82e41834 | 2016 | extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ |
c81bebd7 MM |
2017 | |
2018 | #define REGISTER_NAMES \ | |
2019 | { \ | |
2020 | &rs6000_reg_names[ 0][0], /* r0 */ \ | |
2021 | &rs6000_reg_names[ 1][0], /* r1 */ \ | |
2022 | &rs6000_reg_names[ 2][0], /* r2 */ \ | |
2023 | &rs6000_reg_names[ 3][0], /* r3 */ \ | |
2024 | &rs6000_reg_names[ 4][0], /* r4 */ \ | |
2025 | &rs6000_reg_names[ 5][0], /* r5 */ \ | |
2026 | &rs6000_reg_names[ 6][0], /* r6 */ \ | |
2027 | &rs6000_reg_names[ 7][0], /* r7 */ \ | |
2028 | &rs6000_reg_names[ 8][0], /* r8 */ \ | |
2029 | &rs6000_reg_names[ 9][0], /* r9 */ \ | |
2030 | &rs6000_reg_names[10][0], /* r10 */ \ | |
2031 | &rs6000_reg_names[11][0], /* r11 */ \ | |
2032 | &rs6000_reg_names[12][0], /* r12 */ \ | |
2033 | &rs6000_reg_names[13][0], /* r13 */ \ | |
2034 | &rs6000_reg_names[14][0], /* r14 */ \ | |
2035 | &rs6000_reg_names[15][0], /* r15 */ \ | |
2036 | &rs6000_reg_names[16][0], /* r16 */ \ | |
2037 | &rs6000_reg_names[17][0], /* r17 */ \ | |
2038 | &rs6000_reg_names[18][0], /* r18 */ \ | |
2039 | &rs6000_reg_names[19][0], /* r19 */ \ | |
2040 | &rs6000_reg_names[20][0], /* r20 */ \ | |
2041 | &rs6000_reg_names[21][0], /* r21 */ \ | |
2042 | &rs6000_reg_names[22][0], /* r22 */ \ | |
2043 | &rs6000_reg_names[23][0], /* r23 */ \ | |
2044 | &rs6000_reg_names[24][0], /* r24 */ \ | |
2045 | &rs6000_reg_names[25][0], /* r25 */ \ | |
2046 | &rs6000_reg_names[26][0], /* r26 */ \ | |
2047 | &rs6000_reg_names[27][0], /* r27 */ \ | |
2048 | &rs6000_reg_names[28][0], /* r28 */ \ | |
2049 | &rs6000_reg_names[29][0], /* r29 */ \ | |
2050 | &rs6000_reg_names[30][0], /* r30 */ \ | |
2051 | &rs6000_reg_names[31][0], /* r31 */ \ | |
2052 | \ | |
2053 | &rs6000_reg_names[32][0], /* fr0 */ \ | |
2054 | &rs6000_reg_names[33][0], /* fr1 */ \ | |
2055 | &rs6000_reg_names[34][0], /* fr2 */ \ | |
2056 | &rs6000_reg_names[35][0], /* fr3 */ \ | |
2057 | &rs6000_reg_names[36][0], /* fr4 */ \ | |
2058 | &rs6000_reg_names[37][0], /* fr5 */ \ | |
2059 | &rs6000_reg_names[38][0], /* fr6 */ \ | |
2060 | &rs6000_reg_names[39][0], /* fr7 */ \ | |
2061 | &rs6000_reg_names[40][0], /* fr8 */ \ | |
2062 | &rs6000_reg_names[41][0], /* fr9 */ \ | |
2063 | &rs6000_reg_names[42][0], /* fr10 */ \ | |
2064 | &rs6000_reg_names[43][0], /* fr11 */ \ | |
2065 | &rs6000_reg_names[44][0], /* fr12 */ \ | |
2066 | &rs6000_reg_names[45][0], /* fr13 */ \ | |
2067 | &rs6000_reg_names[46][0], /* fr14 */ \ | |
2068 | &rs6000_reg_names[47][0], /* fr15 */ \ | |
2069 | &rs6000_reg_names[48][0], /* fr16 */ \ | |
2070 | &rs6000_reg_names[49][0], /* fr17 */ \ | |
2071 | &rs6000_reg_names[50][0], /* fr18 */ \ | |
2072 | &rs6000_reg_names[51][0], /* fr19 */ \ | |
2073 | &rs6000_reg_names[52][0], /* fr20 */ \ | |
2074 | &rs6000_reg_names[53][0], /* fr21 */ \ | |
2075 | &rs6000_reg_names[54][0], /* fr22 */ \ | |
2076 | &rs6000_reg_names[55][0], /* fr23 */ \ | |
2077 | &rs6000_reg_names[56][0], /* fr24 */ \ | |
2078 | &rs6000_reg_names[57][0], /* fr25 */ \ | |
2079 | &rs6000_reg_names[58][0], /* fr26 */ \ | |
2080 | &rs6000_reg_names[59][0], /* fr27 */ \ | |
2081 | &rs6000_reg_names[60][0], /* fr28 */ \ | |
2082 | &rs6000_reg_names[61][0], /* fr29 */ \ | |
2083 | &rs6000_reg_names[62][0], /* fr30 */ \ | |
2084 | &rs6000_reg_names[63][0], /* fr31 */ \ | |
2085 | \ | |
462f7901 | 2086 | &rs6000_reg_names[64][0], /* was mq */ \ |
c81bebd7 MM |
2087 | &rs6000_reg_names[65][0], /* lr */ \ |
2088 | &rs6000_reg_names[66][0], /* ctr */ \ | |
2089 | &rs6000_reg_names[67][0], /* ap */ \ | |
2090 | \ | |
2091 | &rs6000_reg_names[68][0], /* cr0 */ \ | |
2092 | &rs6000_reg_names[69][0], /* cr1 */ \ | |
2093 | &rs6000_reg_names[70][0], /* cr2 */ \ | |
2094 | &rs6000_reg_names[71][0], /* cr3 */ \ | |
2095 | &rs6000_reg_names[72][0], /* cr4 */ \ | |
2096 | &rs6000_reg_names[73][0], /* cr5 */ \ | |
2097 | &rs6000_reg_names[74][0], /* cr6 */ \ | |
2098 | &rs6000_reg_names[75][0], /* cr7 */ \ | |
802a0058 | 2099 | \ |
f6b5d695 | 2100 | &rs6000_reg_names[76][0], /* ca */ \ |
0ac081f6 AH |
2101 | \ |
2102 | &rs6000_reg_names[77][0], /* v0 */ \ | |
2103 | &rs6000_reg_names[78][0], /* v1 */ \ | |
2104 | &rs6000_reg_names[79][0], /* v2 */ \ | |
2105 | &rs6000_reg_names[80][0], /* v3 */ \ | |
2106 | &rs6000_reg_names[81][0], /* v4 */ \ | |
2107 | &rs6000_reg_names[82][0], /* v5 */ \ | |
2108 | &rs6000_reg_names[83][0], /* v6 */ \ | |
2109 | &rs6000_reg_names[84][0], /* v7 */ \ | |
2110 | &rs6000_reg_names[85][0], /* v8 */ \ | |
2111 | &rs6000_reg_names[86][0], /* v9 */ \ | |
2112 | &rs6000_reg_names[87][0], /* v10 */ \ | |
2113 | &rs6000_reg_names[88][0], /* v11 */ \ | |
2114 | &rs6000_reg_names[89][0], /* v12 */ \ | |
2115 | &rs6000_reg_names[90][0], /* v13 */ \ | |
2116 | &rs6000_reg_names[91][0], /* v14 */ \ | |
2117 | &rs6000_reg_names[92][0], /* v15 */ \ | |
2118 | &rs6000_reg_names[93][0], /* v16 */ \ | |
2119 | &rs6000_reg_names[94][0], /* v17 */ \ | |
2120 | &rs6000_reg_names[95][0], /* v18 */ \ | |
2121 | &rs6000_reg_names[96][0], /* v19 */ \ | |
2122 | &rs6000_reg_names[97][0], /* v20 */ \ | |
2123 | &rs6000_reg_names[98][0], /* v21 */ \ | |
2124 | &rs6000_reg_names[99][0], /* v22 */ \ | |
2125 | &rs6000_reg_names[100][0], /* v23 */ \ | |
2126 | &rs6000_reg_names[101][0], /* v24 */ \ | |
2127 | &rs6000_reg_names[102][0], /* v25 */ \ | |
2128 | &rs6000_reg_names[103][0], /* v26 */ \ | |
2129 | &rs6000_reg_names[104][0], /* v27 */ \ | |
2130 | &rs6000_reg_names[105][0], /* v28 */ \ | |
2131 | &rs6000_reg_names[106][0], /* v29 */ \ | |
2132 | &rs6000_reg_names[107][0], /* v30 */ \ | |
2133 | &rs6000_reg_names[108][0], /* v31 */ \ | |
2134 | &rs6000_reg_names[109][0], /* vrsave */ \ | |
5f004351 | 2135 | &rs6000_reg_names[110][0], /* vscr */ \ |
346081bd SB |
2136 | &rs6000_reg_names[111][0], /* sfp */ \ |
2137 | &rs6000_reg_names[112][0], /* tfhar */ \ | |
2138 | &rs6000_reg_names[113][0], /* tfiar */ \ | |
2139 | &rs6000_reg_names[114][0], /* texasr */ \ | |
c81bebd7 MM |
2140 | } |
2141 | ||
f045b2c9 RS |
2142 | /* Table of additional register names to use in user input. */ |
2143 | ||
2144 | #define ADDITIONAL_REGISTER_NAMES \ | |
c4d38ccb MM |
2145 | {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ |
2146 | {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ | |
2147 | {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ | |
2148 | {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ | |
2149 | {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ | |
2150 | {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ | |
2151 | {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ | |
2152 | {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ | |
2153 | {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ | |
2154 | {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ | |
2155 | {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ | |
2156 | {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ | |
2157 | {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ | |
2158 | {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ | |
2159 | {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ | |
2160 | {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ | |
0ac081f6 AH |
2161 | {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ |
2162 | {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ | |
2163 | {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ | |
2164 | {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ | |
2165 | {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ | |
2166 | {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ | |
2167 | {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ | |
2168 | {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ | |
5f004351 | 2169 | {"vrsave", 109}, {"vscr", 110}, \ |
462f7901 | 2170 | /* no additional names for: lr, ctr, ap */ \ |
c4d38ccb MM |
2171 | {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ |
2172 | {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ | |
cacf1ca8 | 2173 | {"cc", 68}, {"sp", 1}, {"toc", 2}, \ |
f6b5d695 SB |
2174 | /* CA is only part of XER, but we do not model the other parts (yet). */ \ |
2175 | {"xer", 76}, \ | |
cacf1ca8 MM |
2176 | /* VSX registers overlaid on top of FR, Altivec registers */ \ |
2177 | {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ | |
2178 | {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ | |
2179 | {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ | |
2180 | {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ | |
2181 | {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ | |
2182 | {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ | |
2183 | {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ | |
2184 | {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ | |
2185 | {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ | |
2186 | {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ | |
2187 | {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ | |
2188 | {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ | |
2189 | {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ | |
2190 | {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ | |
2191 | {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ | |
0258b6e4 PB |
2192 | {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ |
2193 | /* Transactional Memory Facility (HTM) Registers. */ \ | |
346081bd | 2194 | {"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \ |
23742a9e | 2195 | } |
f045b2c9 | 2196 | |
f045b2c9 RS |
2197 | /* This is how to output an element of a case-vector that is relative. */ |
2198 | ||
e1565e65 | 2199 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ |
3daf36a4 | 2200 | do { char buf[100]; \ |
e1565e65 | 2201 | fputs ("\t.long ", FILE); \ |
3daf36a4 ILT |
2202 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ |
2203 | assemble_name (FILE, buf); \ | |
19d2d16f | 2204 | putc ('-', FILE); \ |
3daf36a4 ILT |
2205 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ |
2206 | assemble_name (FILE, buf); \ | |
19d2d16f | 2207 | putc ('\n', FILE); \ |
3daf36a4 | 2208 | } while (0) |
f045b2c9 RS |
2209 | |
2210 | /* This is how to output an assembler line | |
2211 | that says to advance the location counter | |
2212 | to a multiple of 2**LOG bytes. */ | |
2213 | ||
2214 | #define ASM_OUTPUT_ALIGN(FILE,LOG) \ | |
2215 | if ((LOG) != 0) \ | |
2216 | fprintf (FILE, "\t.align %d\n", (LOG)) | |
2217 | ||
58082ff6 PH |
2218 | /* How to align the given loop. */ |
2219 | #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) | |
2220 | ||
d28073d4 BS |
2221 | /* Alignment guaranteed by __builtin_malloc. */ |
2222 | /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. | |
2223 | However, specifying the stronger guarantee currently leads to | |
2224 | a regression in SPEC CPU2006 437.leslie3d. The stronger | |
2225 | guarantee should be implemented here once that's fixed. */ | |
2226 | #define MALLOC_ABI_ALIGNMENT (64) | |
2227 | ||
9ebbca7d GK |
2228 | /* Pick up the return address upon entry to a procedure. Used for |
2229 | dwarf2 unwind information. This also enables the table driven | |
2230 | mechanism. */ | |
2231 | ||
1de43f85 DE |
2232 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) |
2233 | #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) | |
9ebbca7d | 2234 | |
83720594 RH |
2235 | /* Describe how we implement __builtin_eh_return. */ |
2236 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) | |
2237 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
2238 | ||
f045b2c9 RS |
2239 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
2240 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
2241 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
2242 | ||
2243 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
2244 | ||
2245 | /* Define which CODE values are valid. */ | |
2246 | ||
3cf437d4 | 2247 | #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') |
f045b2c9 RS |
2248 | |
2249 | /* Print a memory address as an operand to reference that memory location. */ | |
2250 | ||
2251 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
2252 | ||
c82846bc DE |
2253 | /* For switching between functions with different target attributes. */ |
2254 | #define SWITCHABLE_TARGET 1 | |
2255 | ||
b6c9286a MM |
2256 | /* uncomment for disabling the corresponding default options */ |
2257 | /* #define MACHINE_no_sched_interblock */ | |
2258 | /* #define MACHINE_no_sched_speculative */ | |
2259 | /* #define MACHINE_no_sched_speculative_load */ | |
2260 | ||
766a866c | 2261 | /* General flags. */ |
a7df97e6 | 2262 | extern int frame_pointer_needed; |
0ac081f6 | 2263 | |
7fa14a01 MM |
2264 | /* Classification of the builtin functions as to which switches enable the |
2265 | builtin, and what attributes it should have. We used to use the target | |
2266 | flags macros, but we've run out of bits, so we now map the options into new | |
2267 | settings used here. */ | |
2268 | ||
2269 | /* Builtin attributes. */ | |
2270 | #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ | |
2271 | #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ | |
2272 | #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ | |
2273 | #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ | |
2274 | #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ | |
2275 | #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ | |
7fa14a01 MM |
2276 | #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ |
2277 | #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ | |
2278 | ||
2279 | #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ | |
902cb7b1 KN |
2280 | #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor |
2281 | modifies global state. */ | |
4f45da44 KN |
2282 | #define RS6000_BTC_PURE 0x00000200 /* reads global |
2283 | state/mem and does | |
2284 | not modify global state. */ | |
7fa14a01 MM |
2285 | #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ |
2286 | #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ | |
2287 | ||
2288 | /* Miscellaneous information. */ | |
0258b6e4 PB |
2289 | #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ |
2290 | #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ | |
01f61a78 PB |
2291 | #define RS6000_BTC_CR 0x04000000 /* function references a CR. */ |
2292 | #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ | |
0258b6e4 | 2293 | #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ |
1c9df37c MM |
2294 | |
2295 | /* Convenience macros to document the instruction type. */ | |
7fa14a01 MM |
2296 | #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ |
2297 | #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ | |
2298 | ||
2299 | /* Builtin targets. For now, we reuse the masks for those options that are in | |
55928937 SB |
2300 | target flags, and pick a random bit for ldbl128, which isn't in |
2301 | target_flags. */ | |
4b705221 | 2302 | #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ |
7fa14a01 | 2303 | #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ |
4fd18c78 | 2304 | #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ |
7fa14a01 | 2305 | #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ |
f62511da | 2306 | #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ |
8fa97501 | 2307 | #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ |
5a3a6a5e | 2308 | #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ |
f62511da | 2309 | #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ |
0258b6e4 | 2310 | #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ |
7fa14a01 MM |
2311 | #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ |
2312 | #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ | |
2313 | #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ | |
2314 | #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ | |
2315 | #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ | |
7fa14a01 | 2316 | #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ |
06b39289 | 2317 | #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ |
f93bc5b3 | 2318 | #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ |
8241efd1 | 2319 | #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ |
4f45da44 | 2320 | #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ |
eb581af4 | 2321 | #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ |
bbd35101 | 2322 | #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ |
12fca96e | 2323 | #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ |
7fa14a01 MM |
2324 | |
2325 | #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | |
2326 | | RS6000_BTM_VSX \ | |
f62511da | 2327 | | RS6000_BTM_P8_VECTOR \ |
8fa97501 | 2328 | | RS6000_BTM_P9_VECTOR \ |
5a3a6a5e | 2329 | | RS6000_BTM_P9_MISC \ |
402e60c5 | 2330 | | RS6000_BTM_MODULO \ |
f62511da | 2331 | | RS6000_BTM_CRYPTO \ |
7fa14a01 MM |
2332 | | RS6000_BTM_FRE \ |
2333 | | RS6000_BTM_FRES \ | |
2334 | | RS6000_BTM_FRSQRTE \ | |
2335 | | RS6000_BTM_FRSQRTES \ | |
0258b6e4 | 2336 | | RS6000_BTM_HTM \ |
7fa14a01 | 2337 | | RS6000_BTM_POPCNTD \ |
06b39289 | 2338 | | RS6000_BTM_CELL \ |
f93bc5b3 | 2339 | | RS6000_BTM_DFP \ |
8241efd1 | 2340 | | RS6000_BTM_HARD_FLOAT \ |
53605f35 | 2341 | | RS6000_BTM_LDBL128 \ |
eb581af4 | 2342 | | RS6000_BTM_POWERPC64 \ |
12fca96e MM |
2343 | | RS6000_BTM_FLOAT128 \ |
2344 | | RS6000_BTM_FLOAT128_HW) | |
7fa14a01 MM |
2345 | |
2346 | /* Define builtin enum index. */ | |
2347 | ||
4f45da44 | 2348 | #undef RS6000_BUILTIN_0 |
7fa14a01 MM |
2349 | #undef RS6000_BUILTIN_1 |
2350 | #undef RS6000_BUILTIN_2 | |
2351 | #undef RS6000_BUILTIN_3 | |
2352 | #undef RS6000_BUILTIN_A | |
2353 | #undef RS6000_BUILTIN_D | |
0258b6e4 | 2354 | #undef RS6000_BUILTIN_H |
7fa14a01 | 2355 | #undef RS6000_BUILTIN_P |
7fa14a01 MM |
2356 | #undef RS6000_BUILTIN_X |
2357 | ||
4f45da44 | 2358 | #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
7fa14a01 MM |
2359 | #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
2360 | #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2361 | #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2362 | #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
2363 | #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, | |
0258b6e4 | 2364 | #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
7fa14a01 | 2365 | #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
7fa14a01 | 2366 | #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, |
1c9df37c | 2367 | |
0ac081f6 AH |
2368 | enum rs6000_builtins |
2369 | { | |
1c9df37c | 2370 | #include "rs6000-builtin.def" |
a72c65c7 | 2371 | |
58646b77 PB |
2372 | RS6000_BUILTIN_COUNT |
2373 | }; | |
2374 | ||
4f45da44 | 2375 | #undef RS6000_BUILTIN_0 |
7fa14a01 MM |
2376 | #undef RS6000_BUILTIN_1 |
2377 | #undef RS6000_BUILTIN_2 | |
2378 | #undef RS6000_BUILTIN_3 | |
2379 | #undef RS6000_BUILTIN_A | |
2380 | #undef RS6000_BUILTIN_D | |
0258b6e4 | 2381 | #undef RS6000_BUILTIN_H |
7fa14a01 | 2382 | #undef RS6000_BUILTIN_P |
7fa14a01 | 2383 | #undef RS6000_BUILTIN_X |
1c9df37c | 2384 | |
58646b77 PB |
2385 | enum rs6000_builtin_type_index |
2386 | { | |
2387 | RS6000_BTI_NOT_OPAQUE, | |
58646b77 | 2388 | RS6000_BTI_opaque_V4SI, |
d4f18ec6 | 2389 | RS6000_BTI_V16QI, /* __vector signed char */ |
a16a872d | 2390 | RS6000_BTI_V1TI, |
a72c65c7 MM |
2391 | RS6000_BTI_V2DI, |
2392 | RS6000_BTI_V2DF, | |
58646b77 PB |
2393 | RS6000_BTI_V4HI, |
2394 | RS6000_BTI_V4SI, | |
2395 | RS6000_BTI_V4SF, | |
2396 | RS6000_BTI_V8HI, | |
d4f18ec6 | 2397 | RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */ |
a16a872d | 2398 | RS6000_BTI_unsigned_V1TI, |
58646b77 PB |
2399 | RS6000_BTI_unsigned_V8HI, |
2400 | RS6000_BTI_unsigned_V4SI, | |
a72c65c7 | 2401 | RS6000_BTI_unsigned_V2DI, |
58646b77 PB |
2402 | RS6000_BTI_bool_char, /* __bool char */ |
2403 | RS6000_BTI_bool_short, /* __bool short */ | |
2404 | RS6000_BTI_bool_int, /* __bool int */ | |
d4f18ec6 KN |
2405 | RS6000_BTI_bool_long_long, /* __bool long long */ |
2406 | RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4 | |
2407 | channels of 1, 5, 5, and 5 bits | |
2408 | respectively as packed with the | |
2409 | vpkpx insn. __pixel is only | |
2410 | meaningful as a vector type. | |
2411 | There is no corresponding scalar | |
2412 | __pixel data type.) */ | |
58646b77 PB |
2413 | RS6000_BTI_bool_V16QI, /* __vector __bool char */ |
2414 | RS6000_BTI_bool_V8HI, /* __vector __bool short */ | |
2415 | RS6000_BTI_bool_V4SI, /* __vector __bool int */ | |
a72c65c7 | 2416 | RS6000_BTI_bool_V2DI, /* __vector __bool long */ |
58646b77 PB |
2417 | RS6000_BTI_pixel_V8HI, /* __vector __pixel */ |
2418 | RS6000_BTI_long, /* long_integer_type_node */ | |
2419 | RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ | |
c9485473 MM |
2420 | RS6000_BTI_long_long, /* long_long_integer_type_node */ |
2421 | RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ | |
d4f18ec6 | 2422 | RS6000_BTI_INTQI, /* (signed) intQI_type_node */ |
58646b77 PB |
2423 | RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ |
2424 | RS6000_BTI_INTHI, /* intHI_type_node */ | |
2425 | RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ | |
d4f18ec6 | 2426 | RS6000_BTI_INTSI, /* intSI_type_node (signed) */ |
58646b77 | 2427 | RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ |
a72c65c7 MM |
2428 | RS6000_BTI_INTDI, /* intDI_type_node */ |
2429 | RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ | |
a16a872d MM |
2430 | RS6000_BTI_INTTI, /* intTI_type_node */ |
2431 | RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ | |
58646b77 | 2432 | RS6000_BTI_float, /* float_type_node */ |
a72c65c7 | 2433 | RS6000_BTI_double, /* double_type_node */ |
06b39289 MM |
2434 | RS6000_BTI_long_double, /* long_double_type_node */ |
2435 | RS6000_BTI_dfloat64, /* dfloat64_type_node */ | |
2436 | RS6000_BTI_dfloat128, /* dfloat128_type_node */ | |
58646b77 | 2437 | RS6000_BTI_void, /* void_type_node */ |
6712d6fd MM |
2438 | RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ |
2439 | RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ | |
53605f35 | 2440 | RS6000_BTI_const_str, /* pointer to const char * */ |
58646b77 | 2441 | RS6000_BTI_MAX |
0ac081f6 | 2442 | }; |
58646b77 PB |
2443 | |
2444 | ||
58646b77 PB |
2445 | #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) |
2446 | #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) | |
a16a872d | 2447 | #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) |
a72c65c7 MM |
2448 | #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) |
2449 | #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) | |
58646b77 PB |
2450 | #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) |
2451 | #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) | |
2452 | #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) | |
2453 | #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) | |
2454 | #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) | |
a16a872d | 2455 | #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) |
58646b77 PB |
2456 | #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) |
2457 | #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) | |
a72c65c7 | 2458 | #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) |
58646b77 PB |
2459 | #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) |
2460 | #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) | |
2461 | #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) | |
d4f18ec6 | 2462 | #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long]) |
58646b77 PB |
2463 | #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) |
2464 | #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) | |
2465 | #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) | |
2466 | #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) | |
a72c65c7 | 2467 | #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) |
58646b77 PB |
2468 | #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) |
2469 | ||
c9485473 MM |
2470 | #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) |
2471 | #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) | |
58646b77 PB |
2472 | #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) |
2473 | #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) | |
2474 | #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) | |
2475 | #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) | |
2476 | #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) | |
2477 | #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) | |
2478 | #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) | |
2479 | #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) | |
a72c65c7 MM |
2480 | #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) |
2481 | #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) | |
a16a872d MM |
2482 | #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) |
2483 | #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) | |
58646b77 | 2484 | #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) |
a72c65c7 | 2485 | #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) |
06b39289 MM |
2486 | #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) |
2487 | #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) | |
2488 | #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) | |
58646b77 | 2489 | #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) |
6712d6fd MM |
2490 | #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) |
2491 | #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) | |
53605f35 | 2492 | #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) |
58646b77 PB |
2493 | |
2494 | extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; | |
2495 | extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; | |
2496 | ||
807e902e | 2497 | #define TARGET_SUPPORTS_WIDE_INT 1 |
08213983 MM |
2498 | |
2499 | #if (GCC_VERSION >= 3000) | |
2500 | #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 | |
2501 | #endif |