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077dab3b | 1 | ;; Scheduling description for z900 (cpu 2064). |
a945c346 | 2 | ;; Copyright (C) 2003-2024 Free Software Foundation, Inc. |
077dab3b HP |
3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com). | |
58add37a UW |
5 | |
6 | ;; This file is part of GCC. | |
7 | ||
8 | ;; GCC is free software; you can redistribute it and/or modify it under | |
9 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 10 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
11 | ;; version. |
12 | ||
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | ;; for more details. | |
17 | ||
077dab3b | 18 | ;; You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
19 | ;; along with GCC; see the file COPYING3. If not see |
20 | ;; <http://www.gnu.org/licenses/>. | |
077dab3b HP |
21 | |
22 | ;; | |
23 | ;; References: | |
f4aa3848 | 24 | ;; The microarchitecture of the IBM eServer z900 processor. |
077dab3b HP |
25 | ;; E.M. Schwarz et al. |
26 | ;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002. | |
f4aa3848 | 27 | ;; |
077dab3b | 28 | ;; z900 (cpu 2064) pipeline |
f4aa3848 | 29 | ;; |
077dab3b HP |
30 | ;; dec |
31 | ;; --> | <--- | |
32 | ;; LA bypass | agen | | |
f4aa3848 | 33 | ;; | | | |
077dab3b | 34 | ;; --- c1 | Load bypass |
f4aa3848 | 35 | ;; | | |
077dab3b HP |
36 | ;; c2---- |
37 | ;; | | |
f4aa3848 AK |
38 | ;; e1 |
39 | ;; | | |
077dab3b HP |
40 | ;; wr |
41 | ||
42 | (define_automaton "z_ipu") | |
43 | (define_cpu_unit "z_e1" "z_ipu") | |
44 | (define_cpu_unit "z_wr" "z_ipu") | |
45 | ||
46 | ||
f4aa3848 | 47 | (define_insn_reservation "z_la" 1 |
52d4aa4f | 48 | (and (eq_attr "cpu" "z900") |
077dab3b HP |
49 | (eq_attr "type" "la")) |
50 | "z_e1,z_wr") | |
51 | ||
f4aa3848 | 52 | (define_insn_reservation "z_larl" 1 |
52d4aa4f | 53 | (and (eq_attr "cpu" "z900") |
077dab3b HP |
54 | (eq_attr "type" "larl")) |
55 | "z_e1,z_wr") | |
56 | ||
57 | (define_insn_reservation "z_load" 1 | |
52d4aa4f | 58 | (and (eq_attr "cpu" "z900") |
077dab3b HP |
59 | (eq_attr "type" "load")) |
60 | "z_e1,z_wr") | |
61 | ||
62 | (define_insn_reservation "z_store" 1 | |
52d4aa4f | 63 | (and (eq_attr "cpu" "z900") |
077dab3b HP |
64 | (eq_attr "type" "store")) |
65 | "z_e1,z_wr") | |
66 | ||
e0374221 | 67 | (define_insn_reservation "z_sem" 2 |
52d4aa4f | 68 | (and (eq_attr "cpu" "z900") |
e0374221 AS |
69 | (eq_attr "type" "sem")) |
70 | "z_e1*2,z_wr") | |
71 | ||
077dab3b | 72 | (define_insn_reservation "z_call" 5 |
52d4aa4f | 73 | (and (eq_attr "cpu" "z900") |
077dab3b HP |
74 | (eq_attr "type" "jsr")) |
75 | "z_e1*5,z_wr") | |
76 | ||
ed0e512a | 77 | (define_insn_reservation "z_mul" 5 |
52d4aa4f | 78 | (and (eq_attr "cpu" "z900") |
ed0e512a AK |
79 | (eq_attr "type" "imulsi,imulhi")) |
80 | "z_e1*5,z_wr") | |
81 | ||
82 | (define_insn_reservation "z_inf" 10 | |
52d4aa4f | 83 | (and (eq_attr "cpu" "z900") |
ed0e512a AK |
84 | (eq_attr "type" "idiv,imuldi")) |
85 | "z_e1*10,z_wr") | |
86 | ||
29a74354 | 87 | ;; For everything else we check the atype flag. |
077dab3b HP |
88 | |
89 | (define_insn_reservation "z_int" 1 | |
52d4aa4f | 90 | (and (eq_attr "cpu" "z900") |
29a74354 UW |
91 | (and (not (eq_attr "type" "la,larl,load,store,jsr")) |
92 | (eq_attr "atype" "reg"))) | |
077dab3b HP |
93 | "z_e1,z_wr") |
94 | ||
95 | (define_insn_reservation "z_agen" 1 | |
52d4aa4f | 96 | (and (eq_attr "cpu" "z900") |
29a74354 UW |
97 | (and (not (eq_attr "type" "la,larl,load,store,jsr")) |
98 | (eq_attr "atype" "agen"))) | |
077dab3b HP |
99 | "z_e1,z_wr") |
100 | ||
077dab3b | 101 | ;; |
f4aa3848 | 102 | ;; s390_agen_dep_p returns 1, if a register is set in the |
fae778eb | 103 | ;; first insn and used in the dependent insn to form a address. |
077dab3b HP |
104 | ;; |
105 | ||
106 | ;; | |
fae778eb | 107 | ;; If an instruction uses a register to address memory, it needs |
077dab3b | 108 | ;; to be set 5 cycles in advance. |
f4aa3848 | 109 | ;; |
077dab3b | 110 | |
f4aa3848 | 111 | (define_bypass 5 "z_int,z_agen" |
077dab3b HP |
112 | "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") |
113 | ||
114 | ;; | |
f4aa3848 AK |
115 | ;; A load type instruction uses a bypass to feed the result back |
116 | ;; to the address generation pipeline stage. | |
077dab3b HP |
117 | ;; |
118 | ||
f4aa3848 | 119 | (define_bypass 3 "z_load" |
077dab3b HP |
120 | "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") |
121 | ||
122 | ;; | |
f4aa3848 AK |
123 | ;; A load address type instruction uses a bypass to feed the |
124 | ;; result back to the address generation pipeline stage. | |
077dab3b HP |
125 | ;; |
126 | ||
f4aa3848 | 127 | (define_bypass 2 "z_larl,z_la" |
077dab3b HP |
128 | "z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p") |
129 | ||
130 | ||
131 | ||
132 | ||
133 |