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32a7ab3d | 1 | ;; Constraint definitions for Renesas / SuperH SH. |
7adcbafe | 2 | ;; Copyright (C) 2007-2022 Free Software Foundation, Inc. |
32a7ab3d KK |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
32a7ab3d KK |
9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
32a7ab3d KK |
19 | |
20 | ;; Overview of uppercase letter constraints: | |
2fdc0399 OE |
21 | ;; Axx: atomic memory operand constraints |
22 | ;; Ara: Same as Sra but disallows r15 | |
23 | ;; Add: Same as Sdd but disallows r15 | |
32a7ab3d KK |
24 | ;; Bxx: miscellaneous constraints |
25 | ;; Bsc: SCRATCH - for the scratch register in movsi_ie in the | |
26 | ;; fldi0 / fldi0 cases | |
27 | ;; Cxx: Constants other than only CONST_INT | |
1e44e857 | 28 | ;; Ccl: call site label |
32a7ab3d KK |
29 | ;; Csy: label or symbol |
30 | ;; Cpg: non-explicit constants that can be directly loaded into a general | |
50fe8924 | 31 | ;; purpose register in PIC code. Like 's' except we don't allow |
dc3ba671 | 32 | ;; PIC_ADDR_P |
32a7ab3d KK |
33 | ;; IJKLMNOP: CONT_INT constants |
34 | ;; Ixx: signed xx bit | |
5e204a6e OE |
35 | ;; Jmb: 0x000000FF |
36 | ;; Jmw: 0x0000FFFF | |
78040535 | 37 | ;; Jhb: 0x80000000 |
32a7ab3d KK |
38 | ;; Kxx: unsigned xx bit |
39 | ;; M: 1 | |
40 | ;; N: 0 | |
41 | ;; P27: 1 | 2 | 8 | 16 | |
de6adfa2 N |
42 | ;; Pso: 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 |
43 | ;; Psz: ~1 | ~2 | ~4 | ~8 | ~16 | ~32 | ~64 | ~128 | |
7df2d73c OE |
44 | ;; G: Floating point 0 |
45 | ;; H: Floating point 1 | |
32a7ab3d KK |
46 | ;; Q: pc relative load operand |
47 | ;; Rxx: reserved for exotic register classes. | |
7df2d73c OE |
48 | ;; Sxx: extra memory constraints |
49 | ;; Sua: unaligned memory address | |
50 | ;; Sbv: QImode address without displacement | |
51 | ;; Sbw: QImode address with 12 bit displacement | |
52 | ;; Snd: address without displacement | |
53 | ;; Sdd: address with displacement | |
24c18ad8 | 54 | ;; Sra: simple register address |
32a7ab3d KK |
55 | ;; W: vector |
56 | ;; Z: zero in any mode | |
57 | ;; | |
58 | ;; unused CONST_INT constraint letters: LO | |
b48e9677 | 59 | ;; unused "extra" constraint letters: D T U Y |
32a7ab3d KK |
60 | |
61 | ;; Register constraints | |
62 | (define_register_constraint "a" "ALL_REGS" | |
63 | "@internal") | |
64 | ||
32a7ab3d KK |
65 | (define_register_constraint "c" "FPSCR_REGS" |
66 | "Floating-point status register.") | |
67 | ||
68 | (define_register_constraint "d" "DF_REGS" | |
69 | "Double precision floating-point register.") | |
70 | ||
71 | (define_register_constraint "e" "TARGET_FMOVD ? NO_REGS : FP_REGS" | |
72 | "Floating-point register.") | |
73 | ||
74 | (define_register_constraint "f" "FP_REGS" | |
75 | "Floating-point register.") | |
76 | ||
77 | (define_register_constraint "k" "SIBCALL_REGS" | |
78 | "@internal") | |
79 | ||
80 | (define_register_constraint "l" "PR_REGS" | |
81 | "PR register.") | |
82 | ||
83 | (define_register_constraint "t" "T_REGS" | |
84 | "T register.") | |
85 | ||
a4f71b01 JM |
86 | (define_register_constraint "u" "NON_SP_REGS" |
87 | "Non-stack-pointer register.") | |
88 | ||
32a7ab3d KK |
89 | (define_register_constraint "w" "FP0_REGS" |
90 | "Floating-point register 0.") | |
91 | ||
92 | (define_register_constraint "x" "MAC_REGS" | |
93 | "MACH and MACL registers.") | |
94 | ||
95 | (define_register_constraint "y" "FPUL_REGS" | |
96 | "FPUL register.") | |
97 | ||
98 | (define_register_constraint "z" "R0_REGS" | |
99 | "R0 register.") | |
100 | ||
101 | ;; Integer constraints | |
32a7ab3d KK |
102 | (define_constraint "I08" |
103 | "A signed 8-bit constant, as used in add, sub, etc." | |
104 | (and (match_code "const_int") | |
105 | (match_test "ival >= -128 && ival <= 127"))) | |
106 | ||
32a7ab3d | 107 | (define_constraint "I16" |
e1fab8ba | 108 | "A signed 16-bit constant." |
32a7ab3d KK |
109 | (and (match_code "const_int") |
110 | (match_test "ival >= -32768 && ival <= 32767"))) | |
111 | ||
112 | (define_constraint "I20" | |
113 | "A signed 20-bit constant, as used in SH2A movi20." | |
114 | (and (match_code "const_int") | |
115 | (match_test "ival >= -524288 && ival <= 524287") | |
116 | (match_test "TARGET_SH2A"))) | |
117 | ||
e990551a JS |
118 | (define_constraint "I28" |
119 | "A signed 28-bit constant, as used in SH2A movi20s." | |
120 | (and (match_code "const_int") | |
121 | (match_test "ival >= -134217728 && ival <= 134217727") | |
122 | (match_test "(ival & 255) == 0") | |
123 | (match_test "TARGET_SH2A"))) | |
344332e8 | 124 | |
5e204a6e OE |
125 | (define_constraint "Jmb" |
126 | "Low byte mask constant 0x000000FF" | |
127 | (and (match_code "const_int") | |
128 | (match_test "ival == 0xFF"))) | |
129 | ||
130 | (define_constraint "Jmw" | |
131 | "Low word mask constant 0x0000FFFF" | |
132 | (and (match_code "const_int") | |
133 | (match_test "ival == 0xFFFF"))) | |
134 | ||
78040535 OE |
135 | (define_constraint "Jhb" |
136 | "Highest bit constant" | |
137 | (and (match_code "const_int") | |
138 | (match_test "(ival & 0xFFFFFFFF) == 0x80000000"))) | |
139 | ||
9eb3a0dd N |
140 | (define_constraint "K03" |
141 | "An unsigned 3-bit constant, as used in SH2A bclr, bset, etc." | |
142 | (and (match_code "const_int") | |
143 | (match_test "ival >= 0 && ival <= 7"))) | |
144 | ||
344332e8 OE |
145 | (define_constraint "K04" |
146 | "An unsigned 4-bit constant, as used in mov.b displacement addressing." | |
147 | (and (match_code "const_int") | |
148 | (match_test "ival >= 0 && ival <= 15"))) | |
149 | ||
8c2a3f3b OE |
150 | (define_constraint "K05" |
151 | "An unsigned 5-bit constant, as used in mov.w displacement addressing." | |
152 | (and (match_code "const_int") | |
153 | (match_test "ival >= 0 && ival <= 31"))) | |
154 | ||
32a7ab3d KK |
155 | (define_constraint "K08" |
156 | "An unsigned 8-bit constant, as used in and, or, etc." | |
157 | (and (match_code "const_int") | |
158 | (match_test "ival >= 0 && ival <= 255"))) | |
159 | ||
9eb3a0dd | 160 | (define_constraint "K12" |
8c2a3f3b OE |
161 | "An unsigned 12-bit constant, as used in SH2A 12-bit mov.b displacement |
162 | addressing." | |
9eb3a0dd N |
163 | (and (match_code "const_int") |
164 | (match_test "ival >= 0 && ival <= 4095"))) | |
165 | ||
8c2a3f3b OE |
166 | (define_constraint "K13" |
167 | "An unsigned 13-bit constant, as used in SH2A 12-bit mov.w displacement | |
168 | addressing." | |
169 | (and (match_code "const_int") | |
170 | (match_test "ival >= 0 && ival <= 8191"))) | |
171 | ||
32a7ab3d KK |
172 | (define_constraint "P27" |
173 | "A constant for shift operand 1,2,8 or 16." | |
174 | (and (match_code "const_int") | |
175 | (match_test "ival == 1 || ival == 2 || ival == 8 || ival == 16"))) | |
176 | ||
177 | (define_constraint "M" | |
178 | "Integer constant 1." | |
179 | (and (match_code "const_int") | |
180 | (match_test "ival == 1"))) | |
181 | ||
182 | (define_constraint "N" | |
183 | "Integer constant 0." | |
184 | (and (match_code "const_int") | |
185 | (match_test "ival == 0"))) | |
186 | ||
187 | ;; Floating-point constraints | |
188 | (define_constraint "G" | |
189 | "Double constant 0." | |
190 | (and (match_code "const_double") | |
ddfe2bdb | 191 | (match_test "fp_zero_operand (op)"))) |
32a7ab3d KK |
192 | |
193 | (define_constraint "H" | |
194 | "Double constant 1." | |
195 | (and (match_code "const_double") | |
ddfe2bdb | 196 | (match_test "fp_one_operand (op)"))) |
32a7ab3d KK |
197 | |
198 | ;; Extra constraints | |
199 | (define_constraint "Q" | |
200 | "A pc relative load operand." | |
201 | (and (match_code "mem") | |
91f65b12 | 202 | (match_test "GET_MODE (op) != QImode") |
32a7ab3d KK |
203 | (match_test "IS_PC_RELATIVE_LOAD_ADDR_P (XEXP (op, 0))"))) |
204 | ||
205 | (define_constraint "Bsc" | |
206 | "Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber | |
207 | operand is not SCRATCH (i.e. REG) then R0 is probably being used, | |
208 | hence mova is being used, hence do not select this pattern." | |
209 | (match_code "scratch")) | |
210 | ||
1e44e857 DJ |
211 | (define_constraint "Ccl" |
212 | "A call site label, for bsrf." | |
213 | (and (match_code "unspec") | |
214 | (match_test "XINT (op, 1) == UNSPEC_CALLER"))) | |
215 | ||
32a7ab3d KK |
216 | (define_constraint "Csy" |
217 | "A label or a symbol." | |
218 | (ior (match_test "NON_PIC_REFERENCE_P (op)") | |
dc3ba671 | 219 | (match_test "PIC_ADDR_P (op)"))) |
32a7ab3d KK |
220 | |
221 | (define_constraint "Z" | |
222 | "A zero in any shape or form." | |
223 | (match_test "op == CONST0_RTX (GET_MODE (op))")) | |
224 | ||
225 | (define_constraint "W" | |
226 | "Any vector constant we can handle." | |
227 | (and (match_code "const_vector") | |
228 | (ior (match_test "sh_rep_vec (op, VOIDmode)") | |
229 | (match_test "HOST_BITS_PER_WIDE_INT >= 64 | |
230 | ? sh_const_vec (op, VOIDmode) | |
231 | : sh_1el_vec (op, VOIDmode)")))) | |
232 | ||
233 | (define_constraint "Cpg" | |
234 | "A non-explicit constant that can be loaded directly into a general | |
235 | purpose register. This is like 's' except we don't allow | |
dc3ba671 | 236 | PIC_ADDR_P." |
32a7ab3d KK |
237 | (match_test "IS_NON_EXPLICIT_CONSTANT_P (op)")) |
238 | ||
de6adfa2 N |
239 | (define_constraint "Pso" |
240 | "Integer constant with a single bit set in its lower 8-bit." | |
241 | (and (match_code "const_int") | |
242 | (ior (match_test "ival == 1") | |
243 | (match_test "ival == 2") | |
244 | (match_test "ival == 4") | |
245 | (match_test "ival == 8") | |
246 | (match_test "ival == 16") | |
247 | (match_test "ival == 32") | |
248 | (match_test "ival == 64") | |
249 | (match_test "ival == 128")))) | |
250 | ||
251 | (define_constraint "Psz" | |
252 | "Integer constant with a single zero bit in the lower 8-bit." | |
253 | (and (match_code "const_int") | |
254 | (ior (match_test "~ival == 1") | |
255 | (match_test "~ival == 2") | |
256 | (match_test "~ival == 4") | |
257 | (match_test "~ival == 8") | |
258 | (match_test "~ival == 16") | |
259 | (match_test "~ival == 32") | |
260 | (match_test "~ival == 64") | |
261 | (match_test "~ival == 128")))) | |
262 | ||
32a7ab3d KK |
263 | (define_memory_constraint "Sua" |
264 | "@internal" | |
265 | (and (match_test "memory_operand (op, GET_MODE (op))") | |
266 | (match_test "GET_CODE (XEXP (op, 0)) != PLUS"))) | |
9eb3a0dd | 267 | |
8c2a3f3b OE |
268 | (define_memory_constraint "Sdd" |
269 | "A memory reference that uses displacement addressing." | |
91f65b12 | 270 | (and (match_code "mem") |
21f65dc8 OE |
271 | (match_code "plus" "0") |
272 | (match_code "reg" "00") | |
273 | (match_code "const_int" "01"))) | |
8c2a3f3b OE |
274 | |
275 | (define_memory_constraint "Snd" | |
276 | "A memory reference that excludes displacement addressing." | |
91f65b12 OE |
277 | (and (match_code "mem") |
278 | (match_test "! satisfies_constraint_Sdd (op)"))) | |
8c2a3f3b | 279 | |
852776b3 KK |
280 | (define_memory_constraint "Sid" |
281 | "A memory reference that uses index addressing." | |
282 | (and (match_code "mem") | |
283 | (match_code "plus" "0") | |
284 | (match_code "reg" "00") | |
285 | (match_code "reg" "01"))) | |
286 | ||
287 | (define_memory_constraint "Ssd" | |
288 | "A memory reference that excludes index and displacement addressing." | |
289 | (and (match_code "mem") | |
290 | (match_test "! satisfies_constraint_Sid (op)") | |
291 | (match_test "! satisfies_constraint_Sdd (op)"))) | |
292 | ||
9eb3a0dd N |
293 | (define_memory_constraint "Sbv" |
294 | "A memory reference, as used in SH2A bclr.b, bset.b, etc." | |
295 | (and (match_test "MEM_P (op) && GET_MODE (op) == QImode") | |
296 | (match_test "REG_P (XEXP (op, 0))"))) | |
297 | ||
298 | (define_memory_constraint "Sbw" | |
299 | "A memory reference, as used in SH2A bclr.b, bset.b, etc." | |
8c2a3f3b OE |
300 | (and (match_test "satisfies_constraint_Sdd (op)") |
301 | (match_test "GET_MODE (op) == QImode") | |
9eb3a0dd | 302 | (match_test "satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))"))) |
344332e8 | 303 | |
24c18ad8 | 304 | (define_memory_constraint "Sra" |
50fe8924 | 305 | "A memory reference that uses simple register addressing." |
21f65dc8 OE |
306 | (and (match_code "mem") |
307 | (match_code "reg" "0"))) | |
24c18ad8 | 308 | |
2fdc0399 OE |
309 | (define_memory_constraint "Ara" |
310 | "A memory reference that uses simple register addressing suitable for | |
311 | gusa atomic operations." | |
312 | (and (match_code "mem") | |
313 | (match_code "reg" "0") | |
314 | (match_test "REGNO (XEXP (op, 0)) != SP_REG"))) | |
315 | ||
316 | (define_memory_constraint "Add" | |
317 | "A memory reference that uses displacement addressing suitable for | |
318 | gusa atomic operations." | |
319 | (and (match_code "mem") | |
320 | (match_test "GET_MODE (op) == SImode") | |
321 | (match_code "plus" "0") | |
322 | (match_code "reg" "00") | |
323 | (match_code "const_int" "01") | |
324 | (match_test "REGNO (XEXP (XEXP (op, 0), 0)) != SP_REG"))) |