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312209c6 | 1 | ;; Scheduling description for Renesas SH4a |
78d310c2 | 2 | ;; Copyright (C) 2003, 2004, 2006 Free Software Foundation, Inc. |
312209c6 | 3 | ;; |
713e31f4 | 4 | ;; This file is part of GCC. |
312209c6 AO |
5 | ;; |
6 | ;; GNU CC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
8 | ;; the Free Software Foundation; either version 2, or (at your option) | |
9 | ;; any later version. | |
10 | ;; | |
11 | ;; GNU CC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
17 | ;; along with GNU CC; see the file COPYING. If not, write to | |
39d14dda KC |
18 | ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, |
19 | ;; Boston, MA 02110-1301, USA. | |
312209c6 AO |
20 | |
21 | ;; The following description models the SH4A pipeline | |
22 | ;; using the DFA based scheduler. | |
23 | ||
24 | (define_automaton "sh4a") | |
25 | ||
26 | (define_cpu_unit "sh4a_ex" "sh4a") | |
27 | (define_cpu_unit "sh4a_ls" "sh4a") | |
28 | (define_cpu_unit "sh4a_fex" "sh4a") | |
29 | (define_cpu_unit "sh4a_fls" "sh4a") | |
30 | (define_cpu_unit "sh4a_mult" "sh4a") | |
31 | (define_cpu_unit "sh4a_fdiv" "sh4a") | |
32 | ||
33 | ;; Decoding is done on the integer pipeline like the | |
34 | ;; sh4. Define issue to be the | of the two pipelines | |
35 | ;; to control how often instructions are issued. | |
36 | (define_reservation "ID_or" "sh4a_ex|sh4a_ls") | |
37 | (define_reservation "ID_and" "sh4a_ex+sh4a_ls") | |
38 | ||
39 | ||
40 | ;; ======================================================= | |
41 | ;; Locking Descriptions | |
42 | ||
43 | ;; Sh4a_Memory access on the LS pipeline. | |
44 | (define_cpu_unit "sh4a_memory" "sh4a") | |
45 | ||
46 | ;; Other access on the LS pipeline. | |
47 | (define_cpu_unit "sh4a_load_store" "sh4a") | |
48 | ||
49 | ;; The address calculator used for branch instructions. | |
50 | ;; This will be reserved after "issue" of branch instructions | |
51 | ;; and this is to make sure that no two branch instructions | |
52 | ;; can be issued in parallel. | |
53 | (define_reservation "sh4a_addrcalc" "sh4a_ex") | |
54 | ||
55 | ;; ======================================================= | |
56 | ;; Reservations | |
57 | ||
58 | ;; Branch (BF,BF/S,BT,BT/S,BRA,BSR) | |
59 | ;; Group: BR | |
60 | ;; Latency when taken: 2 | |
61 | (define_insn_reservation "sh4a_branch" 2 | |
62 | (and (eq_attr "cpu" "sh4a") | |
63 | (eq_attr "type" "cbranch,jump")) | |
64 | "ID_or+sh4a_addrcalc") | |
65 | ||
66 | ;; Jump (JSR,JMP,RTS) | |
67 | ;; Group: BR | |
68 | ;; Latency: 3 | |
69 | (define_insn_reservation "sh4a_jump" 3 | |
70 | (and (eq_attr "cpu" "sh4a") | |
71 | (eq_attr "type" "return,jump_ind")) | |
72 | "ID_or+sh4a_addrcalc") | |
73 | ||
74 | ;; RTE | |
75 | ;; Group: CO | |
76 | ;; Latency: 3 | |
77 | (define_insn_reservation "sh4a_rte" 3 | |
78 | (and (eq_attr "cpu" "sh4a") | |
79 | (eq_attr "type" "rte")) | |
80 | "ID_and*4") | |
81 | ||
82 | ;; EX Group Single | |
83 | ;; Group: EX | |
84 | ;; Latency: 0 | |
85 | (define_insn_reservation "sh4a_ex" 0 | |
86 | (and (eq_attr "cpu" "sh4a") | |
87 | (eq_attr "insn_class" "ex_group")) | |
88 | "sh4a_ex") | |
89 | ||
90 | ;; MOVA | |
91 | ;; Group: LS | |
92 | ;; Latency: 1 | |
93 | (define_insn_reservation "sh4a_mova" 1 | |
94 | (and (eq_attr "cpu" "sh4a") | |
95 | (eq_attr "type" "mova")) | |
96 | "sh4a_ls+sh4a_load_store") | |
97 | ||
98 | ;; MOV | |
99 | ;; Group: MT | |
100 | ;; Latency: 0 | |
78d310c2 R |
101 | ;; ??? not sure if movi8 belongs here, but that's where it was |
102 | ;; effectively before. | |
312209c6 AO |
103 | (define_insn_reservation "sh4a_mov" 0 |
104 | (and (eq_attr "cpu" "sh4a") | |
78d310c2 | 105 | (eq_attr "type" "move,movi8,gp_mac")) |
312209c6 AO |
106 | "ID_or") |
107 | ||
108 | ;; Load | |
109 | ;; Group: LS | |
110 | ;; Latency: 3 | |
111 | (define_insn_reservation "sh4a_load" 3 | |
112 | (and (eq_attr "cpu" "sh4a") | |
78d310c2 | 113 | (eq_attr "type" "load,pcload,mem_mac")) |
312209c6 AO |
114 | "sh4a_ls+sh4a_memory") |
115 | ||
116 | (define_insn_reservation "sh4a_load_si" 3 | |
117 | (and (eq_attr "cpu" "sh4a") | |
118 | (eq_attr "type" "load_si,pcload_si")) | |
119 | "sh4a_ls+sh4a_memory") | |
120 | ||
121 | ;; Store | |
122 | ;; Group: LS | |
123 | ;; Latency: 0 | |
124 | (define_insn_reservation "sh4a_store" 0 | |
125 | (and (eq_attr "cpu" "sh4a") | |
78d310c2 | 126 | (eq_attr "type" "store,fstore,mac_mem")) |
312209c6 AO |
127 | "sh4a_ls+sh4a_memory") |
128 | ||
129 | ;; CWB TYPE | |
130 | ||
131 | ;; MOVUA | |
132 | ;; Group: LS | |
133 | ;; Latency: 3 | |
134 | (define_insn_reservation "sh4a_movua" 3 | |
135 | (and (eq_attr "cpu" "sh4a") | |
136 | (eq_attr "type" "movua")) | |
137 | "sh4a_ls+sh4a_memory*2") | |
138 | ||
139 | ;; Fixed point multiplication (single) | |
140 | ;; Group: CO | |
141 | ;; Latency: 2 | |
142 | (define_insn_reservation "sh4a_smult" 2 | |
143 | (and (eq_attr "cpu" "sh4a") | |
144 | (eq_attr "type" "smpy")) | |
145 | "ID_or+sh4a_mult") | |
146 | ||
147 | ;; Fixed point multiplication (double) | |
148 | ;; Group: CO | |
149 | ;; Latency: 3 | |
150 | (define_insn_reservation "sh4a_dmult" 3 | |
151 | (and (eq_attr "cpu" "sh4a") | |
152 | (eq_attr "type" "dmpy")) | |
153 | "ID_or+sh4a_mult") | |
154 | ||
155 | (define_insn_reservation "sh4a_mac_gp" 3 | |
156 | (and (eq_attr "cpu" "sh4a") | |
157 | (eq_attr "type" "mac_gp")) | |
158 | "ID_and") | |
159 | ||
160 | ;; Other MT group instructions(1 step operations) | |
161 | ;; Group: MT | |
162 | ;; Latency: 1 | |
163 | (define_insn_reservation "sh4a_mt" 1 | |
164 | (and (eq_attr "cpu" "sh4a") | |
165 | (eq_attr "type" "mt_group")) | |
166 | "ID_or") | |
167 | ||
168 | ;; Floating point reg move | |
169 | ;; Group: LS | |
170 | ;; Latency: 2 | |
171 | (define_insn_reservation "sh4a_freg_mov" 2 | |
172 | (and (eq_attr "cpu" "sh4a") | |
173 | (eq_attr "type" "fmove")) | |
174 | "sh4a_ls,sh4a_fls") | |
175 | ||
176 | ;; Single precision floating point computation FCMP/EQ, | |
177 | ;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG | |
178 | ;; Group: FE | |
179 | ;; Latency: 3 | |
180 | (define_insn_reservation "sh4a_fp_arith" 3 | |
181 | (and (eq_attr "cpu" "sh4a") | |
78d310c2 | 182 | (eq_attr "type" "fp,fp_cmp,fpscr_toggle")) |
312209c6 AO |
183 | "ID_or,sh4a_fex") |
184 | ||
185 | (define_insn_reservation "sh4a_fp_arith_ftrc" 3 | |
186 | (and (eq_attr "cpu" "sh4a") | |
187 | (eq_attr "type" "ftrc_s")) | |
188 | "ID_or,sh4a_fex") | |
189 | ||
190 | ;; Single-precision FDIV/FSQRT | |
191 | ;; Group: FE | |
192 | ;; Latency: 20 | |
193 | (define_insn_reservation "sh4a_fdiv" 20 | |
194 | (and (eq_attr "cpu" "sh4a") | |
195 | (eq_attr "type" "fdiv")) | |
196 | "ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex") | |
197 | ||
198 | ;; Double Precision floating point computation | |
199 | ;; (FCNVDS, FCNVSD, FLOAT, FTRC) | |
200 | ;; Group: FE | |
201 | ;; Latency: 3 | |
202 | (define_insn_reservation "sh4a_dp_float" 3 | |
203 | (and (eq_attr "cpu" "sh4a") | |
204 | (eq_attr "type" "dfp_conv")) | |
205 | "ID_or,sh4a_fex") | |
206 | ||
207 | ;; Double-precision floating-point (FADD,FMUL,FSUB) | |
208 | ;; Group: FE | |
209 | ;; Latency: 5 | |
210 | (define_insn_reservation "sh4a_fp_double_arith" 5 | |
211 | (and (eq_attr "cpu" "sh4a") | |
78d310c2 | 212 | (eq_attr "type" "dfp_arith,dfp_mul")) |
312209c6 AO |
213 | "ID_or,sh4a_fex*3") |
214 | ||
215 | ;; Double precision FDIV/SQRT | |
216 | ;; Group: FE | |
217 | ;; Latency: 36 | |
218 | (define_insn_reservation "sh4a_dp_div" 36 | |
219 | (and (eq_attr "cpu" "sh4a") | |
220 | (eq_attr "type" "dfdiv")) | |
221 | "ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex*2") | |
222 | ||
223 | ;; FSRRA | |
224 | ;; Group: FE | |
225 | ;; Latency: 5 | |
226 | (define_insn_reservation "sh4a_fsrra" 5 | |
227 | (and (eq_attr "cpu" "sh4a") | |
228 | (eq_attr "type" "fsrra")) | |
229 | "ID_or,sh4a_fex") | |
230 | ||
231 | ;; FSCA | |
232 | ;; Group: FE | |
233 | ;; Latency: 7 | |
234 | (define_insn_reservation "sh4a_fsca" 7 | |
235 | (and (eq_attr "cpu" "sh4a") | |
236 | (eq_attr "type" "fsca")) | |
237 | "ID_or,sh4a_fex*3") |