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312209c6 | 1 | ;; Scheduling description for Renesas SH4a |
d1e082c2 | 2 | ;; Copyright (C) 2003-2013 Free Software Foundation, Inc. |
312209c6 | 3 | ;; |
713e31f4 | 4 | ;; This file is part of GCC. |
312209c6 AO |
5 | ;; |
6 | ;; GNU CC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
312209c6 AO |
9 | ;; any later version. |
10 | ;; | |
11 | ;; GNU CC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
312209c6 AO |
19 | |
20 | ;; The following description models the SH4A pipeline | |
21 | ;; using the DFA based scheduler. | |
22 | ||
23 | (define_automaton "sh4a") | |
24 | ||
25 | (define_cpu_unit "sh4a_ex" "sh4a") | |
26 | (define_cpu_unit "sh4a_ls" "sh4a") | |
27 | (define_cpu_unit "sh4a_fex" "sh4a") | |
28 | (define_cpu_unit "sh4a_fls" "sh4a") | |
29 | (define_cpu_unit "sh4a_mult" "sh4a") | |
30 | (define_cpu_unit "sh4a_fdiv" "sh4a") | |
31 | ||
32 | ;; Decoding is done on the integer pipeline like the | |
33 | ;; sh4. Define issue to be the | of the two pipelines | |
34 | ;; to control how often instructions are issued. | |
35 | (define_reservation "ID_or" "sh4a_ex|sh4a_ls") | |
36 | (define_reservation "ID_and" "sh4a_ex+sh4a_ls") | |
37 | ||
38 | ||
39 | ;; ======================================================= | |
40 | ;; Locking Descriptions | |
41 | ||
42 | ;; Sh4a_Memory access on the LS pipeline. | |
43 | (define_cpu_unit "sh4a_memory" "sh4a") | |
44 | ||
45 | ;; Other access on the LS pipeline. | |
46 | (define_cpu_unit "sh4a_load_store" "sh4a") | |
47 | ||
48 | ;; The address calculator used for branch instructions. | |
49 | ;; This will be reserved after "issue" of branch instructions | |
50 | ;; and this is to make sure that no two branch instructions | |
51 | ;; can be issued in parallel. | |
52 | (define_reservation "sh4a_addrcalc" "sh4a_ex") | |
53 | ||
54 | ;; ======================================================= | |
55 | ;; Reservations | |
56 | ||
57 | ;; Branch (BF,BF/S,BT,BT/S,BRA,BSR) | |
58 | ;; Group: BR | |
59 | ;; Latency when taken: 2 | |
60 | (define_insn_reservation "sh4a_branch" 2 | |
61 | (and (eq_attr "cpu" "sh4a") | |
62 | (eq_attr "type" "cbranch,jump")) | |
63 | "ID_or+sh4a_addrcalc") | |
64 | ||
65 | ;; Jump (JSR,JMP,RTS) | |
66 | ;; Group: BR | |
67 | ;; Latency: 3 | |
68 | (define_insn_reservation "sh4a_jump" 3 | |
69 | (and (eq_attr "cpu" "sh4a") | |
70 | (eq_attr "type" "return,jump_ind")) | |
71 | "ID_or+sh4a_addrcalc") | |
72 | ||
73 | ;; RTE | |
74 | ;; Group: CO | |
75 | ;; Latency: 3 | |
76 | (define_insn_reservation "sh4a_rte" 3 | |
77 | (and (eq_attr "cpu" "sh4a") | |
78 | (eq_attr "type" "rte")) | |
79 | "ID_and*4") | |
80 | ||
81 | ;; EX Group Single | |
82 | ;; Group: EX | |
83 | ;; Latency: 0 | |
84 | (define_insn_reservation "sh4a_ex" 0 | |
85 | (and (eq_attr "cpu" "sh4a") | |
86 | (eq_attr "insn_class" "ex_group")) | |
87 | "sh4a_ex") | |
88 | ||
89 | ;; MOVA | |
90 | ;; Group: LS | |
91 | ;; Latency: 1 | |
92 | (define_insn_reservation "sh4a_mova" 1 | |
93 | (and (eq_attr "cpu" "sh4a") | |
94 | (eq_attr "type" "mova")) | |
95 | "sh4a_ls+sh4a_load_store") | |
96 | ||
97 | ;; MOV | |
98 | ;; Group: MT | |
99 | ;; Latency: 0 | |
78d310c2 R |
100 | ;; ??? not sure if movi8 belongs here, but that's where it was |
101 | ;; effectively before. | |
312209c6 AO |
102 | (define_insn_reservation "sh4a_mov" 0 |
103 | (and (eq_attr "cpu" "sh4a") | |
78d310c2 | 104 | (eq_attr "type" "move,movi8,gp_mac")) |
312209c6 AO |
105 | "ID_or") |
106 | ||
107 | ;; Load | |
108 | ;; Group: LS | |
109 | ;; Latency: 3 | |
110 | (define_insn_reservation "sh4a_load" 3 | |
111 | (and (eq_attr "cpu" "sh4a") | |
78d310c2 | 112 | (eq_attr "type" "load,pcload,mem_mac")) |
312209c6 AO |
113 | "sh4a_ls+sh4a_memory") |
114 | ||
115 | (define_insn_reservation "sh4a_load_si" 3 | |
116 | (and (eq_attr "cpu" "sh4a") | |
117 | (eq_attr "type" "load_si,pcload_si")) | |
118 | "sh4a_ls+sh4a_memory") | |
119 | ||
120 | ;; Store | |
121 | ;; Group: LS | |
122 | ;; Latency: 0 | |
123 | (define_insn_reservation "sh4a_store" 0 | |
124 | (and (eq_attr "cpu" "sh4a") | |
78d310c2 | 125 | (eq_attr "type" "store,fstore,mac_mem")) |
312209c6 AO |
126 | "sh4a_ls+sh4a_memory") |
127 | ||
128 | ;; CWB TYPE | |
129 | ||
130 | ;; MOVUA | |
131 | ;; Group: LS | |
132 | ;; Latency: 3 | |
133 | (define_insn_reservation "sh4a_movua" 3 | |
134 | (and (eq_attr "cpu" "sh4a") | |
135 | (eq_attr "type" "movua")) | |
136 | "sh4a_ls+sh4a_memory*2") | |
137 | ||
138 | ;; Fixed point multiplication (single) | |
139 | ;; Group: CO | |
140 | ;; Latency: 2 | |
141 | (define_insn_reservation "sh4a_smult" 2 | |
142 | (and (eq_attr "cpu" "sh4a") | |
143 | (eq_attr "type" "smpy")) | |
144 | "ID_or+sh4a_mult") | |
145 | ||
146 | ;; Fixed point multiplication (double) | |
147 | ;; Group: CO | |
148 | ;; Latency: 3 | |
149 | (define_insn_reservation "sh4a_dmult" 3 | |
150 | (and (eq_attr "cpu" "sh4a") | |
151 | (eq_attr "type" "dmpy")) | |
152 | "ID_or+sh4a_mult") | |
153 | ||
154 | (define_insn_reservation "sh4a_mac_gp" 3 | |
155 | (and (eq_attr "cpu" "sh4a") | |
156 | (eq_attr "type" "mac_gp")) | |
157 | "ID_and") | |
158 | ||
159 | ;; Other MT group instructions(1 step operations) | |
160 | ;; Group: MT | |
161 | ;; Latency: 1 | |
162 | (define_insn_reservation "sh4a_mt" 1 | |
163 | (and (eq_attr "cpu" "sh4a") | |
164 | (eq_attr "type" "mt_group")) | |
165 | "ID_or") | |
166 | ||
167 | ;; Floating point reg move | |
168 | ;; Group: LS | |
169 | ;; Latency: 2 | |
170 | (define_insn_reservation "sh4a_freg_mov" 2 | |
171 | (and (eq_attr "cpu" "sh4a") | |
172 | (eq_attr "type" "fmove")) | |
173 | "sh4a_ls,sh4a_fls") | |
174 | ||
175 | ;; Single precision floating point computation FCMP/EQ, | |
176 | ;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG | |
177 | ;; Group: FE | |
178 | ;; Latency: 3 | |
179 | (define_insn_reservation "sh4a_fp_arith" 3 | |
180 | (and (eq_attr "cpu" "sh4a") | |
78d310c2 | 181 | (eq_attr "type" "fp,fp_cmp,fpscr_toggle")) |
312209c6 AO |
182 | "ID_or,sh4a_fex") |
183 | ||
184 | (define_insn_reservation "sh4a_fp_arith_ftrc" 3 | |
185 | (and (eq_attr "cpu" "sh4a") | |
186 | (eq_attr "type" "ftrc_s")) | |
187 | "ID_or,sh4a_fex") | |
188 | ||
189 | ;; Single-precision FDIV/FSQRT | |
190 | ;; Group: FE | |
191 | ;; Latency: 20 | |
192 | (define_insn_reservation "sh4a_fdiv" 20 | |
193 | (and (eq_attr "cpu" "sh4a") | |
194 | (eq_attr "type" "fdiv")) | |
195 | "ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex") | |
196 | ||
197 | ;; Double Precision floating point computation | |
198 | ;; (FCNVDS, FCNVSD, FLOAT, FTRC) | |
199 | ;; Group: FE | |
200 | ;; Latency: 3 | |
201 | (define_insn_reservation "sh4a_dp_float" 3 | |
202 | (and (eq_attr "cpu" "sh4a") | |
203 | (eq_attr "type" "dfp_conv")) | |
204 | "ID_or,sh4a_fex") | |
205 | ||
206 | ;; Double-precision floating-point (FADD,FMUL,FSUB) | |
207 | ;; Group: FE | |
208 | ;; Latency: 5 | |
209 | (define_insn_reservation "sh4a_fp_double_arith" 5 | |
210 | (and (eq_attr "cpu" "sh4a") | |
78d310c2 | 211 | (eq_attr "type" "dfp_arith,dfp_mul")) |
312209c6 AO |
212 | "ID_or,sh4a_fex*3") |
213 | ||
214 | ;; Double precision FDIV/SQRT | |
215 | ;; Group: FE | |
216 | ;; Latency: 36 | |
217 | (define_insn_reservation "sh4a_dp_div" 36 | |
218 | (and (eq_attr "cpu" "sh4a") | |
219 | (eq_attr "type" "dfdiv")) | |
220 | "ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex*2") | |
221 | ||
222 | ;; FSRRA | |
223 | ;; Group: FE | |
224 | ;; Latency: 5 | |
225 | (define_insn_reservation "sh4a_fsrra" 5 | |
226 | (and (eq_attr "cpu" "sh4a") | |
227 | (eq_attr "type" "fsrra")) | |
228 | "ID_or,sh4a_fex") | |
229 | ||
230 | ;; FSCA | |
231 | ;; Group: FE | |
232 | ;; Latency: 7 | |
233 | (define_insn_reservation "sh4a_fsca" 7 | |
234 | (and (eq_attr "cpu" "sh4a") | |
235 | (eq_attr "type" "fsca")) | |
236 | "ID_or,sh4a_fex*3") |