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4c837a1e | 1 | ;; Scheduling description for Niagara. |
99dee823 | 2 | ;; Copyright (C) 2006-2021 Free Software Foundation, Inc. |
4c837a1e DM |
3 | ;; |
4 | ;; This file is part of GCC. | |
5 | ;; | |
6 | ;; GCC is free software; you can redistribute it and/or modify | |
7 | ;; it under the terms of the GNU General Public License as published by | |
2f83c7d6 | 8 | ;; the Free Software Foundation; either version 3, or (at your option) |
4c837a1e DM |
9 | ;; any later version. |
10 | ;; | |
11 | ;; GCC is distributed in the hope that it will be useful, | |
12 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ;; GNU General Public License for more details. | |
15 | ;; | |
16 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
17 | ;; along with GCC; see the file COPYING3. If not see |
18 | ;; <http://www.gnu.org/licenses/>. | |
4c837a1e DM |
19 | |
20 | ;; Niagara is a single-issue processor. | |
21 | ||
22 | (define_automaton "niagara_0") | |
23 | ||
24 | (define_cpu_unit "niag_pipe" "niagara_0") | |
25 | ||
26 | (define_insn_reservation "niag_5cycle" 5 | |
27 | (and (eq_attr "cpu" "niagara") | |
28 | (eq_attr "type" "multi,flushw,iflush,trap")) | |
29 | "niag_pipe*5") | |
30 | ||
31 | (define_insn_reservation "niag_4cycle" 4 | |
32 | (and (eq_attr "cpu" "niagara") | |
33 | (eq_attr "type" "savew")) | |
34 | "niag_pipe*4") | |
35 | ||
36 | /* Most basic operations are single-cycle. */ | |
37 | (define_insn_reservation "niag_ialu" 1 | |
38 | (and (eq_attr "cpu" "niagara") | |
39 | (eq_attr "type" "ialu,shift,compare,cmove")) | |
40 | "niag_pipe") | |
41 | ||
42 | (define_insn_reservation "niag_imul" 11 | |
43 | (and (eq_attr "cpu" "niagara") | |
44 | (eq_attr "type" "imul")) | |
45 | "niag_pipe*11") | |
46 | ||
47 | (define_insn_reservation "niag_idiv" 72 | |
48 | (and (eq_attr "cpu" "niagara") | |
49 | (eq_attr "type" "idiv")) | |
50 | "niag_pipe*72") | |
51 | ||
52 | (define_insn_reservation "niag_branch" 3 | |
53 | (and (eq_attr "cpu" "niagara") | |
54 | (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch")) | |
55 | "niag_pipe*3") | |
56 | ||
57 | (define_insn_reservation "niag_3cycle_load" 3 | |
58 | (and (eq_attr "cpu" "niagara") | |
59 | (eq_attr "type" "load")) | |
60 | "niag_pipe*3") | |
61 | ||
62 | (define_insn_reservation "niag_9cycle_load" 9 | |
63 | (and (eq_attr "cpu" "niagara") | |
64 | (eq_attr "type" "fpload")) | |
65 | "niag_pipe*9") | |
66 | ||
67 | (define_insn_reservation "niag_1cycle_store" 1 | |
68 | (and (eq_attr "cpu" "niagara") | |
69 | (eq_attr "type" "store")) | |
70 | "niag_pipe") | |
71 | ||
72 | (define_insn_reservation "niag_8cycle_store" 8 | |
73 | (and (eq_attr "cpu" "niagara") | |
74 | (eq_attr "type" "fpstore")) | |
75 | "niag_pipe*8") | |
76 | ||
77 | /* Things incorrectly modelled here: | |
78 | * FPADD{s,d}: 26 cycles | |
79 | * FPSUB{s,d}: 26 cycles | |
80 | * FABSD: 26 cycles | |
81 | * F{s,d}TO{s,d}: 26 cycles | |
82 | * F{s,d}TO{i,x}: 26 cycles | |
83 | * FSMULD: 29 cycles | |
84 | */ | |
85 | (define_insn_reservation "niag_fmov" 8 | |
86 | (and (eq_attr "cpu" "niagara") | |
87 | (eq_attr "type" "fpmove,fpcmove,fpcrmove")) | |
88 | "niag_pipe*8") | |
89 | ||
90 | (define_insn_reservation "niag_fpcmp" 26 | |
91 | (and (eq_attr "cpu" "niagara") | |
92 | (eq_attr "type" "fpcmp")) | |
93 | "niag_pipe*26") | |
94 | ||
95 | (define_insn_reservation "niag_fmult" 29 | |
96 | (and (eq_attr "cpu" "niagara") | |
97 | (eq_attr "type" "fpmul")) | |
98 | "niag_pipe*29") | |
99 | ||
100 | (define_insn_reservation "niag_fdivs" 54 | |
101 | (and (eq_attr "cpu" "niagara") | |
102 | (eq_attr "type" "fpdivs")) | |
103 | "niag_pipe*54") | |
104 | ||
105 | (define_insn_reservation "niag_fdivd" 83 | |
106 | (and (eq_attr "cpu" "niagara") | |
107 | (eq_attr "type" "fpdivd")) | |
108 | "niag_pipe*83") | |
109 | ||
110 | /* Things incorrectly modelled here: | |
111 | * FPADD{16,32}: 10 cycles | |
112 | * FPSUB{16,32}: 10 cycles | |
113 | * FALIGNDATA: 10 cycles | |
114 | */ | |
115 | (define_insn_reservation "niag_vis" 8 | |
116 | (and (eq_attr "cpu" "niagara") | |
bcc3c3f1 | 117 | (eq_attr "type" "fga,visl,viscmp,vismv,fgm_pack,fgm_mul,pdist,edge,edgen,gsr,array,bmask")) |
4c837a1e | 118 | "niag_pipe*8") |