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6a151f87 | 1 | /* Prototypes of target machine for SPARC. |
99dee823 | 2 | Copyright (C) 1999-2021 Free Software Foundation, Inc. |
b1474bb7 | 3 | Contributed by Michael Tiemann (tiemann@cygnus.com). |
6a151f87 | 4 | 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, |
b1474bb7 KG |
5 | at Cygnus Support. |
6 | ||
de0a398e | 7 | This file is part of GCC. |
b1474bb7 | 8 | |
de0a398e | 9 | GCC is free software; you can redistribute it and/or modify |
b1474bb7 | 10 | it under the terms of the GNU General Public License as published by |
2f83c7d6 | 11 | the Free Software Foundation; either version 3, or (at your option) |
b1474bb7 KG |
12 | any later version. |
13 | ||
de0a398e | 14 | GCC is distributed in the hope that it will be useful, |
b1474bb7 KG |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
b1474bb7 KG |
22 | |
23 | #ifndef __SPARC_PROTOS_H__ | |
24 | #define __SPARC_PROTOS_H__ | |
25 | ||
26 | #ifdef TREE_CODE | |
b1474bb7 | 27 | #ifdef RTX_CODE |
e80d5f80 | 28 | extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree); |
b1474bb7 | 29 | #endif |
e80d5f80 | 30 | extern unsigned long sparc_type_code (tree); |
b1474bb7 KG |
31 | #endif /* TREE_CODE */ |
32 | ||
fed94fc9 EB |
33 | extern void sparc_order_regs_for_local_alloc (void); |
34 | extern int sparc_leaf_reg_remap (int); | |
9e6a4b77 | 35 | extern int sparc_initial_elimination_offset (int); |
9ac617d4 | 36 | extern void sparc_expand_prologue (void); |
b11b0904 EB |
37 | extern void sparc_flat_expand_prologue (void); |
38 | extern void sparc_expand_epilogue (bool); | |
39 | extern void sparc_flat_expand_epilogue (bool); | |
5be9b7a1 | 40 | extern bool sparc_can_use_return_insn_p (void); |
e80d5f80 | 41 | extern int check_pic (int); |
e80d5f80 KG |
42 | extern void sparc_profile_hook (int); |
43 | extern void sparc_override_options (void); | |
e80d5f80 | 44 | extern void sparc_output_scratch_registers (FILE *); |
8d12174d | 45 | extern void sparc_target_macros (void); |
6af11d2b | 46 | extern void sparc_emit_membar_for_model (enum memmodel, int, int); |
227efe87 | 47 | extern int sparc_branch_cost (bool, bool); |
b1474bb7 KG |
48 | |
49 | #ifdef RTX_CODE | |
ef4bddc2 | 50 | extern machine_mode select_cc_mode (enum rtx_code, rtx, rtx); |
b1474bb7 | 51 | /* Define the function that build the compare insn for scc and bcc. */ |
f90b7a5a PB |
52 | extern rtx gen_compare_reg (rtx cmp); |
53 | extern rtx sparc_emit_float_lib_cmp (rtx, rtx, enum rtx_code); | |
ef4bddc2 RS |
54 | extern void sparc_emit_floatunsdi (rtx [2], machine_mode); |
55 | extern void sparc_emit_fixunsdi (rtx [2], machine_mode); | |
e80d5f80 KG |
56 | extern void emit_tfmode_binop (enum rtx_code, rtx *); |
57 | extern void emit_tfmode_unop (enum rtx_code, rtx *); | |
58 | extern void emit_tfmode_cvt (enum rtx_code, rtx *); | |
5751a10b JJ |
59 | extern bool constant_address_p (rtx); |
60 | extern bool legitimate_pic_operand_p (rtx); | |
ef4bddc2 | 61 | extern rtx sparc_legitimize_reload_address (rtx, machine_mode, int, int, |
58e6223e | 62 | int, int *win); |
bc6d3f91 | 63 | extern void load_got_register (void); |
1910440e | 64 | extern void sparc_emit_call_insn (rtx, rtx); |
e80d5f80 | 65 | extern void sparc_defer_case_vector (rtx, rtx, int); |
ef4bddc2 | 66 | extern bool sparc_expand_move (machine_mode, rtx *); |
e80d5f80 | 67 | extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx); |
dc7342d2 EB |
68 | extern int sparc_split_reg_mem_legitimate (rtx, rtx); |
69 | extern void sparc_split_reg_mem (rtx, rtx, machine_mode); | |
70 | extern void sparc_split_mem_reg (rtx, rtx, machine_mode); | |
71 | extern int sparc_split_reg_reg_legitimate (rtx, rtx); | |
72 | extern void sparc_split_reg_reg (rtx, rtx, machine_mode); | |
0a83f1a4 | 73 | extern const char *output_load_pcrel_sym (rtx *); |
e1faf324 DM |
74 | extern const char *output_ubranch (rtx, rtx_insn *); |
75 | extern const char *output_cbranch (rtx, rtx, int, int, int, rtx_insn *); | |
76 | extern const char *output_return (rtx_insn *); | |
77 | extern const char *output_sibcall (rtx_insn *, rtx); | |
78 | extern const char *output_v8plus_shift (rtx_insn *, rtx *, const char *); | |
79 | extern const char *output_v8plus_mult (rtx_insn *, rtx *, const char *); | |
80 | extern const char *output_v9branch (rtx, rtx, int, int, int, int, rtx_insn *); | |
260c8ba3 | 81 | extern const char *output_probe_stack_range (rtx, rtx); |
e1faf324 | 82 | extern const char *output_cbcond (rtx, rtx, rtx_insn *); |
f90b7a5a PB |
83 | extern bool emit_scc_insn (rtx []); |
84 | extern void emit_conditional_branch_insn (rtx []); | |
b5ccb9ed | 85 | extern int registers_ok_for_ldd_peep (rtx, rtx); |
e80d5f80 | 86 | extern int mems_ok_for_ldd_peep (rtx, rtx, rtx); |
ef4bddc2 | 87 | extern rtx widen_mem_for_ldd_peep (rtx, rtx, machine_mode); |
b32d5189 | 88 | extern int empty_delay_slot (rtx_insn *); |
82082f65 | 89 | extern int emit_cbcond_nop (rtx_insn *); |
84034c69 DM |
90 | extern int eligible_for_return_delay (rtx_insn *); |
91 | extern int eligible_for_sibcall_delay (rtx_insn *); | |
ef4bddc2 | 92 | extern int emit_move_sequence (rtx, machine_mode); |
e80d5f80 KG |
93 | extern int fp_sethi_p (rtx); |
94 | extern int fp_mov_p (rtx); | |
95 | extern int fp_high_losum_p (rtx); | |
96 | extern int mem_min_alignment (rtx, int); | |
97 | extern int pic_address_needs_scratch (rtx); | |
e80d5f80 | 98 | extern int register_ok_for_ldd (rtx); |
157891a3 | 99 | extern int memory_ok_for_ldd (rtx); |
e80d5f80 | 100 | extern int v9_regcmp_p (enum rtx_code); |
b1474bb7 KG |
101 | /* Function used for V8+ code generation. Returns 1 if the high |
102 | 32 bits of REG are 0 before INSN. */ | |
b32d5189 | 103 | extern int sparc_check_64 (rtx, rtx_insn *); |
e80d5f80 | 104 | extern rtx gen_df_reg (rtx, int); |
470b6e51 | 105 | extern void sparc_expand_compare_and_swap (rtx op[]); |
e00560c2 | 106 | extern void sparc_expand_vector_init (rtx, rtx); |
ef4bddc2 RS |
107 | extern void sparc_expand_vec_perm_bmask(machine_mode, rtx); |
108 | extern bool sparc_expand_conditional_move (machine_mode, rtx *); | |
109 | extern void sparc_expand_vcond (machine_mode, rtx *, int, int); | |
110 | unsigned int sparc_regmode_natural_size (machine_mode); | |
b1474bb7 KG |
111 | #endif /* RTX_CODE */ |
112 | ||
6af11d2b | 113 | extern rtl_opt_pass *make_pass_work_around_errata (gcc::context *); |
9a738908 | 114 | |
b4c522fa IB |
115 | /* Routines implemented in sparc-d.c */ |
116 | extern void sparc_d_target_versions (void); | |
3785d2b2 | 117 | extern void sparc_d_register_target_info (void); |
b4c522fa | 118 | |
b1474bb7 | 119 | #endif /* __SPARC_PROTOS_H__ */ |