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Support for the SPARC M8 cpu.
[thirdparty/gcc.git] / gcc / config / sparc / sparc.opt
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1; Options for the SPARC port of the compiler
2;
cbe34bb5 3; Copyright (C) 2005-2017 Free Software Foundation, Inc.
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4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it under
8; the terms of the GNU General Public License as published by the Free
2f83c7d6 9; Software Foundation; either version 3, or (at your option) any later
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10; version.
11;
12; GCC is distributed in the hope that it will be useful, but WITHOUT
13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15; License for more details.
16;
17; You should have received a copy of the GNU General Public License
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18; along with GCC; see the file COPYING3. If not see
19; <http://www.gnu.org/licenses/>.
fe609b0f 20
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21HeaderInclude
22config/sparc/sparc-opts.h
23
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24;; Debug flags
25TargetVariable
26unsigned int sparc_debug
27
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28mfpu
29Target Report Mask(FPU)
a7b2e184 30Use hardware FP.
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31
32mhard-float
719e1e80 33Target RejectNegative Mask(FPU)
a7b2e184 34Use hardware FP.
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35
36msoft-float
37Target RejectNegative InverseMask(FPU)
a7b2e184 38Do not use hardware FP.
fe609b0f 39
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40mflat
41Target Report Mask(FLAT)
a7b2e184 42Use flat register window model.
b11b0904 43
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44munaligned-doubles
45Target Report Mask(UNALIGNED_DOUBLES)
a7b2e184 46Assume possible double misalignment.
fe609b0f 47
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48mapp-regs
49Target Report Mask(APP_REGS)
a7b2e184 50Use ABI reserved registers.
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51
52mhard-quad-float
53Target Report RejectNegative Mask(HARD_QUAD)
a7b2e184 54Use hardware quad FP instructions.
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55
56msoft-quad-float
57Target Report RejectNegative InverseMask(HARD_QUAD)
a7b2e184 58Do not use hardware quad fp instructions.
fe609b0f 59
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60mlra
61Target Report Mask(LRA)
62Enable Local Register Allocation.
63
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64mv8plus
65Target Report Mask(V8PLUS)
a7b2e184 66Compile for V8+ ABI.
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67
68mvis
69Target Report Mask(VIS)
a7b2e184 70Use UltraSPARC Visual Instruction Set version 1.0 extensions.
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71
72mvis2
73Target Report Mask(VIS2)
a7b2e184 74Use UltraSPARC Visual Instruction Set version 2.0 extensions.
fe609b0f 75
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76mvis3
77Target Report Mask(VIS3)
a7b2e184 78Use UltraSPARC Visual Instruction Set version 3.0 extensions.
96d7b15f 79
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80mvis4
81Target Report Mask(VIS4)
82Use UltraSPARC Visual Instruction Set version 4.0 extensions.
83
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84mvis4b
85Target Report Mask(VIS4B)
86Use additional VIS instructions introduced in OSA2017.
87
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88mcbcond
89Target Report Mask(CBCOND)
a7b2e184 90Use UltraSPARC Compare-and-Branch extensions.
8b98b5fd 91
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92mfmaf
93Target Report Mask(FMAF)
a7b2e184 94Use UltraSPARC Fused Multiply-Add extensions.
e8b141b5 95
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96mpopc
97Target Report Mask(POPC)
a7b2e184 98Use UltraSPARC Population-Count instruction.
dc78280f 99
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100msubxc
101Target Report Mask(SUBXC)
102Use UltraSPARC Subtract-Extended-with-Carry instruction.
103
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104mptr64
105Target Report RejectNegative Mask(PTR64)
a7b2e184 106Pointers are 64-bit.
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107
108mptr32
109Target Report RejectNegative InverseMask(PTR64)
a7b2e184 110Pointers are 32-bit.
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111
112m64
113Target Report RejectNegative Mask(64BIT)
a7b2e184 114Use 64-bit ABI.
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115
116m32
117Target Report RejectNegative InverseMask(64BIT)
a7b2e184 118Use 32-bit ABI.
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119
120mstack-bias
121Target Report Mask(STACK_BIAS)
a7b2e184 122Use stack bias.
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123
124mfaster-structs
125Target Report Mask(FASTER_STRUCTS)
a7b2e184 126Use structs on stronger alignment for double-word copies.
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127
128mrelax
129Target
a7b2e184 130Optimize tail call instructions in assembler and linker.
fe609b0f 131
ba21a04a 132muser-mode
a01a33a2 133Target Report InverseMask(SV_MODE)
a7b2e184 134Do not generate code that can only run in supervisor mode (default).
ba21a04a 135
fe609b0f 136mcpu=
023592aa 137Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)
a7b2e184 138Use features of and schedule code for given CPU.
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139
140mtune=
023592aa 141Target RejectNegative Joined Var(sparc_cpu) Enum(sparc_processor_type) Init(PROCESSOR_V7)
a7b2e184 142Schedule code for given CPU.
fe609b0f 143
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144Enum
145Name(sparc_processor_type) Type(enum processor_type)
146
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147EnumValue
148Enum(sparc_processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly
149
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150EnumValue
151Enum(sparc_processor_type) String(v7) Value(PROCESSOR_V7)
152
153EnumValue
154Enum(sparc_processor_type) String(cypress) Value(PROCESSOR_CYPRESS)
155
156EnumValue
157Enum(sparc_processor_type) String(v8) Value(PROCESSOR_V8)
158
159EnumValue
160Enum(sparc_processor_type) String(supersparc) Value(PROCESSOR_SUPERSPARC)
161
162EnumValue
163Enum(sparc_processor_type) String(hypersparc) Value(PROCESSOR_HYPERSPARC)
164
165EnumValue
166Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON)
167
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168EnumValue
169Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)
170
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171EnumValue
172Enum(sparc_processor_type) String(leon3v7) Value(PROCESSOR_LEON3V7)
173
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174EnumValue
175Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)
176
177EnumValue
178Enum(sparc_processor_type) String(f930) Value(PROCESSOR_F930)
179
180EnumValue
181Enum(sparc_processor_type) String(f934) Value(PROCESSOR_F934)
182
183EnumValue
184Enum(sparc_processor_type) String(sparclite86x) Value(PROCESSOR_SPARCLITE86X)
185
186EnumValue
187Enum(sparc_processor_type) String(sparclet) Value(PROCESSOR_SPARCLET)
188
189EnumValue
190Enum(sparc_processor_type) String(tsc701) Value(PROCESSOR_TSC701)
191
192EnumValue
193Enum(sparc_processor_type) String(v9) Value(PROCESSOR_V9)
194
195EnumValue
196Enum(sparc_processor_type) String(ultrasparc) Value(PROCESSOR_ULTRASPARC)
197
198EnumValue
199Enum(sparc_processor_type) String(ultrasparc3) Value(PROCESSOR_ULTRASPARC3)
200
201EnumValue
202Enum(sparc_processor_type) String(niagara) Value(PROCESSOR_NIAGARA)
203
204EnumValue
205Enum(sparc_processor_type) String(niagara2) Value(PROCESSOR_NIAGARA2)
206
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207EnumValue
208Enum(sparc_processor_type) String(niagara3) Value(PROCESSOR_NIAGARA3)
209
210EnumValue
211Enum(sparc_processor_type) String(niagara4) Value(PROCESSOR_NIAGARA4)
212
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213EnumValue
214Enum(sparc_processor_type) String(niagara7) Value(PROCESSOR_NIAGARA7)
215
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216EnumValue
217Enum(sparc_processor_type) String(m8) Value(PROCESSOR_M8)
218
fe609b0f 219mcmodel=
55bea00a 220Target RejectNegative Joined Var(sparc_cmodel_string)
a7b2e184 221Use given SPARC-V9 code model.
fe609b0f 222
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223mdebug=
224Target RejectNegative Joined Var(sparc_debug_string)
a7b2e184 225Enable debug output.
a0bd60d1 226
2225b57c 227mstd-struct-return
9250444b 228Target Report Var(sparc_std_struct_return)
2225b57c 229Enable strict 32-bit psABI struct return checking.
fe609b0f 230
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231mfix-at697f
232Target Report RejectNegative Var(sparc_fix_at697f)
233Enable workaround for single erratum of AT697F processor
cad669df 234(corresponding to erratum #13 of AT697E processor).
c49c4c85 235
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236mfix-ut699
237Target Report RejectNegative Var(sparc_fix_ut699)
a7b2e184 238Enable workarounds for the errata of the UT699 processor.
5c3eacbb 239
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240Mask(LONG_DOUBLE_128)
241;; Use 128-bit long double
242
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243Mask(LEON)
244;; Generate code for LEON
245
246Mask(LEON3)
247;; Generate code for LEON3
248
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249Mask(SPARCLITE)
250;; Generate code for SPARClite
251
252Mask(SPARCLET)
253;; Generate code for SPARClet
254
255Mask(V8)
256;; Generate code for SPARC-V8
257
258Mask(V9)
259;; Generate code for SPARC-V9
260
261Mask(DEPRECATED_V8_INSNS)
262;; Generate code that uses the V8 instructions deprecated
263;; in the V9 architecture.
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264
265mmemory-model=
266Target RejectNegative Joined Var(sparc_memory_model) Enum(sparc_memory_model) Init(SMM_DEFAULT)
267Specify the memory model in effect for the program.
268
269Enum
270Name(sparc_memory_model) Type(enum sparc_memory_model_type)
271
272EnumValue
273Enum(sparc_memory_model) String(default) Value(SMM_DEFAULT)
274
275EnumValue
276Enum(sparc_memory_model) String(rmo) Value(SMM_RMO)
277
278EnumValue
279Enum(sparc_memory_model) String(pso) Value(SMM_PSO)
280
281EnumValue
282Enum(sparc_memory_model) String(tso) Value(SMM_TSO)
283
284EnumValue
285Enum(sparc_memory_model) String(sc) Value(SMM_SC)