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sparc.opt (msubxc): New option.
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1; Options for the SPARC port of the compiler
2;
818ab71a 3; Copyright (C) 2005-2016 Free Software Foundation, Inc.
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4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it under
8; the terms of the GNU General Public License as published by the Free
2f83c7d6 9; Software Foundation; either version 3, or (at your option) any later
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10; version.
11;
12; GCC is distributed in the hope that it will be useful, but WITHOUT
13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15; License for more details.
16;
17; You should have received a copy of the GNU General Public License
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18; along with GCC; see the file COPYING3. If not see
19; <http://www.gnu.org/licenses/>.
fe609b0f 20
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21HeaderInclude
22config/sparc/sparc-opts.h
23
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24;; Debug flags
25TargetVariable
26unsigned int sparc_debug
27
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28mfpu
29Target Report Mask(FPU)
a7b2e184 30Use hardware FP.
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31
32mhard-float
719e1e80 33Target RejectNegative Mask(FPU)
a7b2e184 34Use hardware FP.
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35
36msoft-float
37Target RejectNegative InverseMask(FPU)
a7b2e184 38Do not use hardware FP.
fe609b0f 39
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40mflat
41Target Report Mask(FLAT)
a7b2e184 42Use flat register window model.
b11b0904 43
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44munaligned-doubles
45Target Report Mask(UNALIGNED_DOUBLES)
a7b2e184 46Assume possible double misalignment.
fe609b0f 47
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48mapp-regs
49Target Report Mask(APP_REGS)
a7b2e184 50Use ABI reserved registers.
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51
52mhard-quad-float
53Target Report RejectNegative Mask(HARD_QUAD)
a7b2e184 54Use hardware quad FP instructions.
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55
56msoft-quad-float
57Target Report RejectNegative InverseMask(HARD_QUAD)
a7b2e184 58Do not use hardware quad fp instructions.
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59
60mv8plus
61Target Report Mask(V8PLUS)
a7b2e184 62Compile for V8+ ABI.
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63
64mvis
65Target Report Mask(VIS)
a7b2e184 66Use UltraSPARC Visual Instruction Set version 1.0 extensions.
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67
68mvis2
69Target Report Mask(VIS2)
a7b2e184 70Use UltraSPARC Visual Instruction Set version 2.0 extensions.
fe609b0f 71
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72mvis3
73Target Report Mask(VIS3)
a7b2e184 74Use UltraSPARC Visual Instruction Set version 3.0 extensions.
96d7b15f 75
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76mvis4
77Target Report Mask(VIS4)
78Use UltraSPARC Visual Instruction Set version 4.0 extensions.
79
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80mcbcond
81Target Report Mask(CBCOND)
a7b2e184 82Use UltraSPARC Compare-and-Branch extensions.
8b98b5fd 83
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84mfmaf
85Target Report Mask(FMAF)
a7b2e184 86Use UltraSPARC Fused Multiply-Add extensions.
e8b141b5 87
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88mpopc
89Target Report Mask(POPC)
a7b2e184 90Use UltraSPARC Population-Count instruction.
dc78280f 91
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92msubxc
93Target Report Mask(SUBXC)
94Use UltraSPARC Subtract-Extended-with-Carry instruction.
95
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96mptr64
97Target Report RejectNegative Mask(PTR64)
a7b2e184 98Pointers are 64-bit.
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99
100mptr32
101Target Report RejectNegative InverseMask(PTR64)
a7b2e184 102Pointers are 32-bit.
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103
104m64
105Target Report RejectNegative Mask(64BIT)
a7b2e184 106Use 64-bit ABI.
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107
108m32
109Target Report RejectNegative InverseMask(64BIT)
a7b2e184 110Use 32-bit ABI.
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111
112mstack-bias
113Target Report Mask(STACK_BIAS)
a7b2e184 114Use stack bias.
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115
116mfaster-structs
117Target Report Mask(FASTER_STRUCTS)
a7b2e184 118Use structs on stronger alignment for double-word copies.
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119
120mrelax
121Target
a7b2e184 122Optimize tail call instructions in assembler and linker.
fe609b0f 123
ba21a04a 124muser-mode
a01a33a2 125Target Report InverseMask(SV_MODE)
a7b2e184 126Do not generate code that can only run in supervisor mode (default).
ba21a04a 127
fe609b0f 128mcpu=
023592aa 129Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)
a7b2e184 130Use features of and schedule code for given CPU.
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131
132mtune=
023592aa 133Target RejectNegative Joined Var(sparc_cpu) Enum(sparc_processor_type) Init(PROCESSOR_V7)
a7b2e184 134Schedule code for given CPU.
fe609b0f 135
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136Enum
137Name(sparc_processor_type) Type(enum processor_type)
138
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139EnumValue
140Enum(sparc_processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly
141
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142EnumValue
143Enum(sparc_processor_type) String(v7) Value(PROCESSOR_V7)
144
145EnumValue
146Enum(sparc_processor_type) String(cypress) Value(PROCESSOR_CYPRESS)
147
148EnumValue
149Enum(sparc_processor_type) String(v8) Value(PROCESSOR_V8)
150
151EnumValue
152Enum(sparc_processor_type) String(supersparc) Value(PROCESSOR_SUPERSPARC)
153
154EnumValue
155Enum(sparc_processor_type) String(hypersparc) Value(PROCESSOR_HYPERSPARC)
156
157EnumValue
158Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON)
159
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160EnumValue
161Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)
162
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163EnumValue
164Enum(sparc_processor_type) String(leon3v7) Value(PROCESSOR_LEON3V7)
165
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166EnumValue
167Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)
168
169EnumValue
170Enum(sparc_processor_type) String(f930) Value(PROCESSOR_F930)
171
172EnumValue
173Enum(sparc_processor_type) String(f934) Value(PROCESSOR_F934)
174
175EnumValue
176Enum(sparc_processor_type) String(sparclite86x) Value(PROCESSOR_SPARCLITE86X)
177
178EnumValue
179Enum(sparc_processor_type) String(sparclet) Value(PROCESSOR_SPARCLET)
180
181EnumValue
182Enum(sparc_processor_type) String(tsc701) Value(PROCESSOR_TSC701)
183
184EnumValue
185Enum(sparc_processor_type) String(v9) Value(PROCESSOR_V9)
186
187EnumValue
188Enum(sparc_processor_type) String(ultrasparc) Value(PROCESSOR_ULTRASPARC)
189
190EnumValue
191Enum(sparc_processor_type) String(ultrasparc3) Value(PROCESSOR_ULTRASPARC3)
192
193EnumValue
194Enum(sparc_processor_type) String(niagara) Value(PROCESSOR_NIAGARA)
195
196EnumValue
197Enum(sparc_processor_type) String(niagara2) Value(PROCESSOR_NIAGARA2)
198
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199EnumValue
200Enum(sparc_processor_type) String(niagara3) Value(PROCESSOR_NIAGARA3)
201
202EnumValue
203Enum(sparc_processor_type) String(niagara4) Value(PROCESSOR_NIAGARA4)
204
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205EnumValue
206Enum(sparc_processor_type) String(niagara7) Value(PROCESSOR_NIAGARA7)
207
fe609b0f 208mcmodel=
55bea00a 209Target RejectNegative Joined Var(sparc_cmodel_string)
a7b2e184 210Use given SPARC-V9 code model.
fe609b0f 211
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212mdebug=
213Target RejectNegative Joined Var(sparc_debug_string)
a7b2e184 214Enable debug output.
a0bd60d1 215
2225b57c 216mstd-struct-return
9250444b 217Target Report Var(sparc_std_struct_return)
2225b57c 218Enable strict 32-bit psABI struct return checking.
fe609b0f 219
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220mfix-at697f
221Target Report RejectNegative Var(sparc_fix_at697f)
222Enable workaround for single erratum of AT697F processor
cad669df 223(corresponding to erratum #13 of AT697E processor).
c49c4c85 224
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225mfix-ut699
226Target Report RejectNegative Var(sparc_fix_ut699)
a7b2e184 227Enable workarounds for the errata of the UT699 processor.
5c3eacbb 228
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229Mask(LONG_DOUBLE_128)
230;; Use 128-bit long double
231
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232Mask(LEON)
233;; Generate code for LEON
234
235Mask(LEON3)
236;; Generate code for LEON3
237
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238Mask(SPARCLITE)
239;; Generate code for SPARClite
240
241Mask(SPARCLET)
242;; Generate code for SPARClet
243
244Mask(V8)
245;; Generate code for SPARC-V8
246
247Mask(V9)
248;; Generate code for SPARC-V9
249
250Mask(DEPRECATED_V8_INSNS)
251;; Generate code that uses the V8 instructions deprecated
252;; in the V9 architecture.
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253
254mmemory-model=
255Target RejectNegative Joined Var(sparc_memory_model) Enum(sparc_memory_model) Init(SMM_DEFAULT)
256Specify the memory model in effect for the program.
257
258Enum
259Name(sparc_memory_model) Type(enum sparc_memory_model_type)
260
261EnumValue
262Enum(sparc_memory_model) String(default) Value(SMM_DEFAULT)
263
264EnumValue
265Enum(sparc_memory_model) String(rmo) Value(SMM_RMO)
266
267EnumValue
268Enum(sparc_memory_model) String(pso) Value(SMM_PSO)
269
270EnumValue
271Enum(sparc_memory_model) String(tso) Value(SMM_TSO)
272
273EnumValue
274Enum(sparc_memory_model) String(sc) Value(SMM_SC)