[thirdparty/gcc.git] / gcc / config / sparc / sync.md

;; GCC machine description for SPARC synchronization instructions.
;; Copyright (C) 2005-2023 Free Software Foundation, Inc.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3.  If not see
;; <http://www.gnu.org/licenses/>.

(define_mode_iterator I12MODE [QI HI])
(define_mode_iterator I124MODE [QI HI SI])
(define_mode_iterator I24MODE [HI SI])
(define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
(define_mode_attr modesuffix [(SI "") (DI "x")])

(define_expand "mem_thread_fence"
  [(match_operand:SI 0 "const_int_operand")]
  "TARGET_V8 || TARGET_V9"
{
  enum memmodel model = (enum memmodel) INTVAL (operands[0]);
  sparc_emit_membar_for_model (model, 3, 3);
  DONE;
})

(define_expand "membar"
  [(set (match_dup 1)
	(unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")]
		    UNSPEC_MEMBAR))]
  "TARGET_V8 || TARGET_V9"
{
  operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
  MEM_VOLATILE_P (operands[1]) = 1;
})

;; A compiler-only memory barrier.  Generic code, when checking for the
;; existence of various named patterns, uses asm("":::"memory") when we
;; don't need an actual instruction.  Here, it's easiest to pretend that
;; membar 0 is such a barrier.  Further, this gives us a nice hook to 
;; ignore all such barriers on Sparc V7.
(define_insn "*membar_empty"
  [(set (match_operand:BLK 0 "" "")
	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")]
		    UNSPEC_MEMBAR))]
  ""
  ""
  [(set_attr "type" "multi")
   (set_attr "length" "0")])

;; For V8, STBAR is exactly membar #StoreStore, by definition.
(define_insn "*membar_storestore"
  [(set (match_operand:BLK 0 "" "")
	(unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))]
  "TARGET_V8"
  "stbar"
  [(set_attr "type" "multi")])

;; For LEON3, STB has the effect of membar #StoreLoad.
(define_insn "*membar_storeload_leon3"
  [(set (match_operand:BLK 0 "" "")
	(unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
  "TARGET_LEON3"
  "stb\t%%g0, [%%sp-1]"
  [(set_attr "type" "store")])

;; For V8, LDSTUB has the effect of membar #StoreLoad.
(define_insn "*membar_storeload"
  [(set (match_operand:BLK 0 "" "")
	(unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
  "TARGET_V8 && !TARGET_LEON3"
  "ldstub\t[%%sp-1], %%g0"
  [(set_attr "type" "multi")])

;; Put the two together, in combination with the fact that V8 implements PSO
;; as its weakest memory model, means a full barrier.  Match all remaining
;; instances of the membar pattern for Sparc V8.
(define_insn "*membar_v8"
  [(set (match_operand:BLK 0 "" "")
	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
		    UNSPEC_MEMBAR))]
  "TARGET_V8"
  "stbar\n\tldstub\t[%%sp-1], %%g0"
  [(set_attr "type" "multi")
   (set_attr "length" "2")])

;; For V9, we have the full membar instruction.
(define_insn "*membar"
  [(set (match_operand:BLK 0 "" "")
	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
		    UNSPEC_MEMBAR))]
  "TARGET_V9"
  "membar\t%1"
  [(set_attr "type" "multi")])

(define_peephole2
  [(set (match_operand:BLK 0 "" "")
	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
		    UNSPEC_MEMBAR))
   (set (match_operand:BLK 2 "" "")
	(unspec:BLK [(match_dup 2) (match_operand:SI 3 "const_int_operand")]
		    UNSPEC_MEMBAR))]
  ""
  [(set (match_operand:BLK 0 "" "")
	(unspec:BLK [(match_dup 0) (match_dup 1)] UNSPEC_MEMBAR))]
{ operands[1] = GEN_INT (UINTVAL (operands[1]) | UINTVAL (operands[3])); })

(define_expand "atomic_load<mode>"
  [(match_operand:I 0 "register_operand" "")
   (match_operand:I 1 "memory_operand" "")
   (match_operand:SI 2 "const_int_operand" "")]
  ""
{
  enum memmodel model = (enum memmodel) INTVAL (operands[2]);

  sparc_emit_membar_for_model (model, 1, 1);

  if (TARGET_ARCH64 || <MODE>mode != DImode)
    emit_move_insn (operands[0], operands[1]);
  else
    emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));

  sparc_emit_membar_for_model (model, 1, 2);
  DONE;
})

(define_insn "atomic_loaddi_1"
  [(set (match_operand:DI 0 "register_operand" "=r,?*f")
	(unspec:DI [(match_operand:DI 1 "memory_operand" "T,T")]
		   UNSPEC_ATOMIC))]
  "TARGET_ARCH32"
  "ldd\t%1, %0"
  [(set_attr "type" "load,fpload")])

(define_expand "atomic_store<mode>"
  [(match_operand:I 0 "memory_operand" "")
   (match_operand:I 1 "register_operand" "")
   (match_operand:SI 2 "const_int_operand" "")]
  ""
{
  enum memmodel model = (enum memmodel) INTVAL (operands[2]);

  sparc_emit_membar_for_model (model, 2, 1);

  if (TARGET_ARCH64 || <MODE>mode != DImode)
    emit_move_insn (operands[0], operands[1]);
  else
    emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));

  sparc_emit_membar_for_model (model, 2, 2);
  DONE;
})

(define_insn "atomic_storedi_1"
  [(set (match_operand:DI 0 "memory_operand" "=T,T,T")
	(unspec:DI
	  [(match_operand:DI 1 "register_or_v9_zero_operand" "J,r,?*f")]
	  UNSPEC_ATOMIC))]
  "TARGET_ARCH32"
  "@
   stx\t%r1, %0
   std\t%1, %0
   std\t%1, %0"
  [(set_attr "type" "store,store,fpstore")
   (set_attr "cpu_feature" "v9,*,*")])

(define_expand "atomic_compare_and_swap<mode>"
  [(match_operand:SI 0 "register_operand" "")		;; bool output
   (match_operand:I 1 "register_operand" "")		;; val output
   (match_operand:I 2 "mem_noofs_operand" "")		;; memory
   (match_operand:I 3 "register_operand" "")		;; expected
   (match_operand:I 4 "register_operand" "")		;; desired
   (match_operand:SI 5 "const_int_operand" "")		;; is_weak
   (match_operand:SI 6 "const_int_operand" "")		;; mod_s
   (match_operand:SI 7 "const_int_operand" "")]		;; mod_f
  "(TARGET_V9 || TARGET_LEON3)
   && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)"
{
  sparc_expand_compare_and_swap (operands);
  DONE;
})

(define_expand "atomic_compare_and_swap<mode>_1"
  [(parallel
     [(set (match_operand:I48MODE 0 "register_operand" "")
	   (match_operand:I48MODE 1 "mem_noofs_operand" ""))
      (set (match_dup 1)
	   (unspec_volatile:I48MODE
	     [(match_operand:I48MODE 2 "register_operand" "")
	      (match_operand:I48MODE 3 "register_operand" "")]
	     UNSPECV_CAS))])]
  "TARGET_V9 || TARGET_LEON3"
  "")

(define_insn "*atomic_compare_and_swap<mode>_1"
  [(set (match_operand:I48MODE 0 "register_operand" "=r")
	(match_operand:I48MODE 1 "mem_noofs_operand" "+W"))
   (set (match_dup 1)
	(unspec_volatile:I48MODE
	  [(match_operand:I48MODE 2 "register_operand" "r")
	   (match_operand:I48MODE 3 "register_operand" "0")]
	  UNSPECV_CAS))]
  "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64)"
  "cas<modesuffix>\t%1, %2, %0"
  [(set_attr "type" "multi")])

(define_insn "atomic_compare_and_swap_leon3_1"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operand:SI 1 "mem_noofs_operand" "+W"))
   (set (match_dup 1)
	(unspec_volatile:SI
	  [(match_operand:SI 2 "register_operand" "r")
	   (match_operand:SI 3 "register_operand" "0")]
	  UNSPECV_CAS))]
  "TARGET_LEON3"
{
  if (sparc_fix_gr712rc)
    output_asm_insn (".align\t16", operands);
  if (TARGET_SV_MODE)
    return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space.  */
  else
    return "casa\t%1 0xa, %2, %0"; /* ASI for user data space.  */
}
  [(set_attr "type" "multi")
   (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
		      (const_int 4) (const_int 1)))])

(define_insn "*atomic_compare_and_swapdi_v8plus"
  [(set (match_operand:DI 0 "register_operand" "=h")
	(match_operand:DI 1 "mem_noofs_operand" "+W"))
   (set (match_dup 1)
	(unspec_volatile:DI
	  [(match_operand:DI 2 "register_operand" "h")
	   (match_operand:DI 3 "register_operand" "0")]
	  UNSPECV_CAS))]
  "TARGET_V8PLUS"
{
  if (sparc_check_64 (operands[3], insn) <= 0)
    output_asm_insn ("srl\t%L3, 0, %L3", operands);
  output_asm_insn ("sllx\t%H3, 32, %H3", operands);
  output_asm_insn ("or\t%L3, %H3, %L3", operands);
  if (sparc_check_64 (operands[2], insn) <= 0)
    output_asm_insn ("srl\t%L2, 0, %L2", operands);
  output_asm_insn ("sllx\t%H2, 32, %H3", operands);
  output_asm_insn ("or\t%L2, %H3, %H3", operands);
  output_asm_insn ("casx\t%1, %H3, %L3", operands);
  return "srlx\t%L3, 32, %H3";
}
  [(set_attr "type" "multi")
   (set_attr "length" "8")])

(define_expand "atomic_exchangesi"
  [(match_operand:SI 0 "register_operand" "")
   (match_operand:SI 1 "memory_operand" "")
   (match_operand:SI 2 "register_operand" "")
   (match_operand:SI 3 "const_int_operand" "")]
  "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
{
  enum memmodel model = (enum memmodel) INTVAL (operands[3]);

  sparc_emit_membar_for_model (model, 3, 1);
  emit_insn (gen_swapsi (operands[0], operands[1], operands[2]));
  sparc_emit_membar_for_model (model, 3, 2);
  DONE;
})

(define_insn "swapsi"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")]
			    UNSPECV_SWAP))
   (set (match_dup 1)
	(match_operand:SI 2 "register_operand" "0"))]
  "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699"
{
  if (sparc_fix_gr712rc)
    return ".align\t16\n\tswap\t%1, %0";
  else
    return "swap\t%1, %0";
}
  [(set_attr "type" "multi")
   (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
		      (const_int 4) (const_int 1)))])

(define_expand "atomic_test_and_set"
  [(match_operand:QI 0 "register_operand" "")
   (match_operand:QI 1 "memory_operand" "")
   (match_operand:SI 2 "const_int_operand" "")]
  "!sparc_fix_ut699"
{
  enum memmodel model = (enum memmodel) INTVAL (operands[2]);
  rtx ret;

  sparc_emit_membar_for_model (model, 3, 1);
  emit_insn (gen_ldstub (operands[0], operands[1]));
  sparc_emit_membar_for_model (model, 3, 2);

  /* Convert the 0/0xff result we would otherwise have to a boolean.
     I.e. ignore all but bit 0.  */
  ret = expand_simple_binop (QImode, AND, operands[0], const1_rtx,
			     operands[0], true, OPTAB_LIB_WIDEN);
  if (ret != operands[0])
    emit_move_insn (operands[0], ret);

  DONE;
})

(define_insn "ldstub"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
			    UNSPECV_LDSTUB))
   (set (match_dup 1) (const_int -1))]
  "!sparc_fix_ut699"
{
  if (sparc_fix_gr712rc)
    return ".align\t16\n\tldstub\t%1, %0";
  else
    return "ldstub\t%1, %0";
}
  [(set_attr "type" "multi")
   (set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
		      (const_int 4) (const_int 1)))])
Commit	Line	Data
396b535a	1	;; GCC machine description for SPARC synchronization instructions.
83ffe9cd	2	;; Copyright (C) 2005-2023 Free Software Foundation, Inc.
396b535a JJ	3	;;
	4	;; This file is part of GCC.
	5	;;
	6	;; GCC is free software; you can redistribute it and/or modify
	7	;; it under the terms of the GNU General Public License as published by
2f83c7d6	8	;; the Free Software Foundation; either version 3, or (at your option)
396b535a JJ	9	;; any later version.
	10	;;
	11	;; GCC is distributed in the hope that it will be useful,
	12	;; but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	;; GNU General Public License for more details.
	15	;;
	16	;; You should have received a copy of the GNU General Public License
2f83c7d6 NC	17	;; along with GCC; see the file COPYING3. If not see
2f83c7d6 NC	18	;; <http://www.gnu.org/licenses/>.
396b535a	19
3abcb3a7	20	(define_mode_iterator I12MODE [QI HI])
99ee7887	21	(define_mode_iterator I124MODE [QI HI SI])
3abcb3a7 HPN	22	(define_mode_iterator I24MODE [HI SI])
3abcb3a7 HPN	23	(define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 \|\| TARGET_V8PLUS")])
396b535a JJ	24	(define_mode_attr modesuffix [(SI "") (DI "x")])
396b535a JJ	25
9a738908 RH	26	(define_expand "mem_thread_fence"
	27	[(match_operand:SI 0 "const_int_operand")]
	28	"TARGET_V8 \|\| TARGET_V9"
	29	{
	30	enum memmodel model = (enum memmodel) INTVAL (operands[0]);
	31	sparc_emit_membar_for_model (model, 3, 3);
	32	DONE;
	33	})
	34
9a738908 RH	35	(define_expand "membar"
9a738908 RH	36	[(set (match_dup 1)
ba6bdc29	37	(unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")]
9a738908 RH	38	UNSPEC_MEMBAR))]
	39	"TARGET_V8 \|\| TARGET_V9"
	40	{
	41	operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
	42	MEM_VOLATILE_P (operands[1]) = 1;
	43	})
	44
	45	;; A compiler-only memory barrier. Generic code, when checking for the
073a8998	46	;; existence of various named patterns, uses asm("":::"memory") when we
9a738908 RH	47	;; don't need an actual instruction. Here, it's easiest to pretend that
	48	;; membar 0 is such a barrier. Further, this gives us a nice hook to
	49	;; ignore all such barriers on Sparc V7.
	50	(define_insn "*membar_empty"
	51	[(set (match_operand:BLK 0 "" "")
	52	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")]
	53	UNSPEC_MEMBAR))]
	54	""
	55	""
	56	[(set_attr "type" "multi")
	57	(set_attr "length" "0")])
	58
	59	;; For V8, STBAR is exactly membar #StoreStore, by definition.
	60	(define_insn "*membar_storestore"
	61	[(set (match_operand:BLK 0 "" "")
	62	(unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))]
	63	"TARGET_V8"
	64	"stbar"
	65	[(set_attr "type" "multi")])
	66
49cc765d DC	67	;; For LEON3, STB has the effect of membar #StoreLoad.
	68	(define_insn "*membar_storeload_leon3"
	69	[(set (match_operand:BLK 0 "" "")
	70	(unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
	71	"TARGET_LEON3"
	72	"stb\t%%g0, [%%sp-1]"
	73	[(set_attr "type" "store")])
	74
ba6bdc29	75	;; For V8, LDSTUB has the effect of membar #StoreLoad.
9a738908 RH	76	(define_insn "*membar_storeload"
	77	[(set (match_operand:BLK 0 "" "")
	78	(unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
49cc765d	79	"TARGET_V8 && !TARGET_LEON3"
9a738908 RH	80	"ldstub\t[%%sp-1], %%g0"
	81	[(set_attr "type" "multi")])
	82
	83	;; Put the two together, in combination with the fact that V8 implements PSO
	84	;; as its weakest memory model, means a full barrier. Match all remaining
	85	;; instances of the membar pattern for Sparc V8.
97269a23	86	(define_insn "*membar_v8"
396b535a	87	[(set (match_operand:BLK 0 "" "")
9a738908 RH	88	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
9a738908 RH	89	UNSPEC_MEMBAR))]
396b535a	90	"TARGET_V8"
97269a23 EB	91	"stbar\n\tldstub\t[%%sp-1], %%g0"
	92	[(set_attr "type" "multi")
	93	(set_attr "length" "2")])
396b535a	94
9a738908	95	;; For V9, we have the full membar instruction.
396b535a JJ	96	(define_insn "*membar"
396b535a JJ	97	[(set (match_operand:BLK 0 "" "")
9a738908 RH	98	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
9a738908 RH	99	UNSPEC_MEMBAR))]
396b535a	100	"TARGET_V9"
9a738908	101	"membar\t%1"
396b535a JJ	102	[(set_attr "type" "multi")])
396b535a JJ	103
3f67a73d EB	104	(define_peephole2
	105	[(set (match_operand:BLK 0 "" "")
	106	(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
	107	UNSPEC_MEMBAR))
	108	(set (match_operand:BLK 2 "" "")
	109	(unspec:BLK [(match_dup 2) (match_operand:SI 3 "const_int_operand")]
	110	UNSPEC_MEMBAR))]
	111	""
	112	[(set (match_operand:BLK 0 "" "")
	113	(unspec:BLK [(match_dup 0) (match_dup 1)] UNSPEC_MEMBAR))]
	114	{ operands[1] = GEN_INT (UINTVAL (operands[1]) \| UINTVAL (operands[3])); })
	115
cfe8fee7 RH	116	(define_expand "atomic_load<mode>"
	117	[(match_operand:I 0 "register_operand" "")
	118	(match_operand:I 1 "memory_operand" "")
	119	(match_operand:SI 2 "const_int_operand" "")]
	120	""
	121	{
	122	enum memmodel model = (enum memmodel) INTVAL (operands[2]);
	123
	124	sparc_emit_membar_for_model (model, 1, 1);
	125
	126	if (TARGET_ARCH64 \|\| <MODE>mode != DImode)
	127	emit_move_insn (operands[0], operands[1]);
	128	else
	129	emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));
	130
	131	sparc_emit_membar_for_model (model, 1, 2);
	132	DONE;
	133	})
	134
	135	(define_insn "atomic_loaddi_1"
f3877b2f EB	136	[(set (match_operand:DI 0 "register_operand" "=r,?*f")
f3877b2f EB	137	(unspec:DI [(match_operand:DI 1 "memory_operand" "T,T")]
cfe8fee7	138	UNSPEC_ATOMIC))]
f3877b2f	139	"TARGET_ARCH32"
cfe8fee7 RH	140	"ldd\t%1, %0"
	141	[(set_attr "type" "load,fpload")])
	142
	143	(define_expand "atomic_store<mode>"
ba6bdc29 EB	144	[(match_operand:I 0 "memory_operand" "")
ba6bdc29 EB	145	(match_operand:I 1 "register_operand" "")
cfe8fee7 RH	146	(match_operand:SI 2 "const_int_operand" "")]
	147	""
	148	{
	149	enum memmodel model = (enum memmodel) INTVAL (operands[2]);
	150
	151	sparc_emit_membar_for_model (model, 2, 1);
	152
	153	if (TARGET_ARCH64 \|\| <MODE>mode != DImode)
	154	emit_move_insn (operands[0], operands[1]);
	155	else
	156	emit_insn (gen_atomic_storedi_1 (operands[0], operands[1]));
	157
	158	sparc_emit_membar_for_model (model, 2, 2);
	159	DONE;
	160	})
	161
	162	(define_insn "atomic_storedi_1"
f3877b2f	163	[(set (match_operand:DI 0 "memory_operand" "=T,T,T")
cfe8fee7	164	(unspec:DI
f3877b2f	165	[(match_operand:DI 1 "register_or_v9_zero_operand" "J,r,?*f")]
cfe8fee7	166	UNSPEC_ATOMIC))]
f3877b2f	167	"TARGET_ARCH32"
cfe8fee7 RH	168	"@
	169	stx\t%r1, %0
	170	std\t%1, %0
	171	std\t%1, %0"
	172	[(set_attr "type" "store,store,fpstore")
	173	(set_attr "cpu_feature" "v9,,")])
	174
470b6e51 RH	175	(define_expand "atomic_compare_and_swap<mode>"
	176	[(match_operand:SI 0 "register_operand" "") ;; bool output
	177	(match_operand:I 1 "register_operand" "") ;; val output
	178	(match_operand:I 2 "mem_noofs_operand" "") ;; memory
	179	(match_operand:I 3 "register_operand" "") ;; expected
	180	(match_operand:I 4 "register_operand" "") ;; desired
	181	(match_operand:SI 5 "const_int_operand" "") ;; is_weak
	182	(match_operand:SI 6 "const_int_operand" "") ;; mod_s
	183	(match_operand:SI 7 "const_int_operand" "")] ;; mod_f
1f65ae7a EB	184	"(TARGET_V9 \|\| TARGET_LEON3)
1f65ae7a EB	185	&& (<MODE>mode != DImode \|\| TARGET_ARCH64 \|\| TARGET_V8PLUS)"
396b535a	186	{
470b6e51	187	sparc_expand_compare_and_swap (operands);
396b535a JJ	188	DONE;
	189	})
	190
470b6e51	191	(define_expand "atomic_compare_and_swap<mode>_1"
396b535a	192	[(parallel
bfb7cccf	193	[(set (match_operand:I48MODE 0 "register_operand" "")
470b6e51	194	(match_operand:I48MODE 1 "mem_noofs_operand" ""))
396b535a JJ	195	(set (match_dup 1)
	196	(unspec_volatile:I48MODE
	197	[(match_operand:I48MODE 2 "register_operand" "")
	198	(match_operand:I48MODE 3 "register_operand" "")]
	199	UNSPECV_CAS))])]
1f65ae7a	200	"TARGET_V9 \|\| TARGET_LEON3"
470b6e51	201	"")
396b535a	202
470b6e51	203	(define_insn "*atomic_compare_and_swap<mode>_1"
396b535a	204	[(set (match_operand:I48MODE 0 "register_operand" "=r")
d8b84e27	205	(match_operand:I48MODE 1 "mem_noofs_operand" "+W"))
470b6e51	206	(set (match_dup 1)
396b535a JJ	207	(unspec_volatile:I48MODE
	208	[(match_operand:I48MODE 2 "register_operand" "r")
	209	(match_operand:I48MODE 3 "register_operand" "0")]
	210	UNSPECV_CAS))]
ba21a04a	211	"TARGET_V9 && (<MODE>mode != DImode \|\| TARGET_ARCH64)"
470b6e51	212	"cas<modesuffix>\t%1, %2, %0"
396b535a JJ	213	[(set_attr "type" "multi")])
396b535a JJ	214
47c72733	215	(define_insn "atomic_compare_and_swap_leon3_1"
ba21a04a	216	[(set (match_operand:SI 0 "register_operand" "=r")
d8b84e27	217	(match_operand:SI 1 "mem_noofs_operand" "+W"))
ba21a04a EB	218	(set (match_dup 1)
	219	(unspec_volatile:SI
	220	[(match_operand:SI 2 "register_operand" "r")
	221	(match_operand:SI 3 "register_operand" "0")]
	222	UNSPECV_CAS))]
	223	"TARGET_LEON3"
	224	{
aed17373 DC	225	if (sparc_fix_gr712rc)
aed17373 DC	226	output_asm_insn (".align\t16", operands);
a01a33a2	227	if (TARGET_SV_MODE)
ba21a04a	228	return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */
a01a33a2 DC	229	else
a01a33a2 DC	230	return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */
ba21a04a	231	}
aed17373 DC	232	[(set_attr "type" "multi")
	233	(set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
	234	(const_int 4) (const_int 1)))])
ba21a04a	235
470b6e51	236	(define_insn "*atomic_compare_and_swapdi_v8plus"
396b535a	237	[(set (match_operand:DI 0 "register_operand" "=h")
d8b84e27	238	(match_operand:DI 1 "mem_noofs_operand" "+W"))
470b6e51	239	(set (match_dup 1)
396b535a JJ	240	(unspec_volatile:DI
	241	[(match_operand:DI 2 "register_operand" "h")
	242	(match_operand:DI 3 "register_operand" "0")]
	243	UNSPECV_CAS))]
	244	"TARGET_V8PLUS"
	245	{
	246	if (sparc_check_64 (operands[3], insn) <= 0)
	247	output_asm_insn ("srl\t%L3, 0, %L3", operands);
	248	output_asm_insn ("sllx\t%H3, 32, %H3", operands);
	249	output_asm_insn ("or\t%L3, %H3, %L3", operands);
	250	if (sparc_check_64 (operands[2], insn) <= 0)
	251	output_asm_insn ("srl\t%L2, 0, %L2", operands);
	252	output_asm_insn ("sllx\t%H2, 32, %H3", operands);
	253	output_asm_insn ("or\t%L2, %H3, %H3", operands);
470b6e51	254	output_asm_insn ("casx\t%1, %H3, %L3", operands);
396b535a JJ	255	return "srlx\t%L3, 32, %H3";
	256	}
	257	[(set_attr "type" "multi")
	258	(set_attr "length" "8")])
	259
99ee7887 RH	260	(define_expand "atomic_exchangesi"
	261	[(match_operand:SI 0 "register_operand" "")
	262	(match_operand:SI 1 "memory_operand" "")
	263	(match_operand:SI 2 "register_operand" "")
	264	(match_operand:SI 3 "const_int_operand" "")]
38ae58ca	265	"(TARGET_V8 \|\| TARGET_V9) && !sparc_fix_ut699"
396b535a	266	{
99ee7887	267	enum memmodel model = (enum memmodel) INTVAL (operands[3]);
396b535a	268
99ee7887 RH	269	sparc_emit_membar_for_model (model, 3, 1);
	270	emit_insn (gen_swapsi (operands[0], operands[1], operands[2]));
	271	sparc_emit_membar_for_model (model, 3, 2);
	272	DONE;
396b535a JJ	273	})
396b535a JJ	274
99ee7887	275	(define_insn "swapsi"
396b535a JJ	276	[(set (match_operand:SI 0 "register_operand" "=r")
	277	(unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")]
	278	UNSPECV_SWAP))
	279	(set (match_dup 1)
	280	(match_operand:SI 2 "register_operand" "0"))]
38ae58ca	281	"(TARGET_V8 \|\| TARGET_V9) && !sparc_fix_ut699"
aed17373 DC	282	{
	283	if (sparc_fix_gr712rc)
	284	return ".align\t16\n\tswap\t%1, %0";
	285	else
	286	return "swap\t%1, %0";
	287	}
	288	[(set_attr "type" "multi")
	289	(set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
	290	(const_int 4) (const_int 1)))])
396b535a	291
5a843a13 RH	292	(define_expand "atomic_test_and_set"
	293	[(match_operand:QI 0 "register_operand" "")
	294	(match_operand:QI 1 "memory_operand" "")
99ee7887	295	(match_operand:SI 2 "const_int_operand" "")]
38ae58ca	296	"!sparc_fix_ut699"
99ee7887 RH	297	{
99ee7887 RH	298	enum memmodel model = (enum memmodel) INTVAL (operands[2]);
5a843a13	299	rtx ret;
396b535a	300
99ee7887	301	sparc_emit_membar_for_model (model, 3, 1);
5a843a13 RH	302	emit_insn (gen_ldstub (operands[0], operands[1]));
5a843a13 RH	303	sparc_emit_membar_for_model (model, 3, 2);
99ee7887	304
5a843a13 RH	305	/* Convert the 0/0xff result we would otherwise have to a boolean.
	306	I.e. ignore all but bit 0. */
	307	ret = expand_simple_binop (QImode, AND, operands[0], const1_rtx,
	308	operands[0], true, OPTAB_LIB_WIDEN);
	309	if (ret != operands[0])
	310	emit_move_insn (operands[0], ret);
99ee7887	311
99ee7887 RH	312	DONE;
99ee7887 RH	313	})
396b535a	314
5a843a13	315	(define_insn "ldstub"
396b535a JJ	316	[(set (match_operand:QI 0 "register_operand" "=r")
	317	(unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")]
	318	UNSPECV_LDSTUB))
	319	(set (match_dup 1) (const_int -1))]
38ae58ca	320	"!sparc_fix_ut699"
aed17373 DC	321	{
	322	if (sparc_fix_gr712rc)
	323	return ".align\t16\n\tldstub\t%1, %0";
	324	else
	325	return "ldstub\t%1, %0";
	326	}
	327	[(set_attr "type" "multi")
	328	(set (attr "length") (if_then_else (eq_attr "fix_gr712rc" "true")
	329	(const_int 4) (const_int 1)))])