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8aeea6e6 1;; Machine description for GNU compiler, VAX Version
99dee823 2;; Copyright (C) 1987-2021 Free Software Foundation, Inc.
ab835497 3
e7d9d16b 4;; This file is part of GCC.
ab835497 5
e7d9d16b 6;; GCC is free software; you can redistribute it and/or modify
ab835497 7;; it under the terms of the GNU General Public License as published by
2f83c7d6 8;; the Free Software Foundation; either version 3, or (at your option)
ab835497
RK		 9;; any later version.
10
e7d9d16b 11;; GCC is distributed in the hope that it will be useful,
ab835497
RK		 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14;; GNU General Public License for more details.
15
16;; You should have received a copy of the GNU General Public License
2f83c7d6
NC		 17;; along with GCC; see the file COPYING3. If not see
18;; <http://www.gnu.org/licenses/>.
ab835497
RK		 19
20
21;;- Instruction patterns. When multiple patterns apply,
22;;- the first one in the file is chosen.
23;;-
821bde61 24;;- See file "rtl.def" for documentation on define_insn, match_*, et al.
ab835497 25
ec20cffb
JT		 26;; UNSPEC_VOLATILE usage:
27
a3515605
RH		 28(define_c_enum "unspecv" [
29 VUNSPEC_BLOCKAGE ; 'blockage' insn to prevent scheduling across an
0f8def68 30 ; insn in the code.
a3515605
RH		 31 VUNSPEC_SYNC_ISTREAM ; sequence of insns to sync the I-stream
32 VUNSPEC_PEM ; 'procedure_entry_mask' insn.
33])
34
35(define_constants
36 [(VAX_AP_REGNUM 12) ; Register 12 contains the argument pointer
0f8def68
JBG		 37 (VAX_FP_REGNUM 13) ; Register 13 contains the frame pointer
38 (VAX_SP_REGNUM 14) ; Register 14 contains the stack pointer
39 (VAX_PC_REGNUM 15) ; Register 15 contains the program counter
e552abe2
MR		 40 (VAX_PSL_REGNUM 16) ; Register 16 contains the processor status
41 ; and condition codes in particular
ec20cffb
JT		 42 ]
43)
44
aabcd309 45;; Integer modes supported on VAX, with a mapping from machine mode
20acd226 46;; to mnemonic suffix. DImode is always a special case.
3abcb3a7 47(define_mode_iterator VAXint [QI HI SI])
c4e75102
MT		 48(define_mode_iterator VAXintQH [QI HI])
49(define_mode_iterator VAXintQHSD [QI HI SI DI])
50(define_mode_attr isfx [(QI "b") (HI "w") (SI "l") (DI "q")])
ab835497 51
20acd226 52;; Similar for float modes supported on VAX.
3abcb3a7 53(define_mode_iterator VAXfp [SF DF])
20acd226 54(define_mode_attr fsfx [(SF "f") (DF "%#")])
ab835497 55
821bde61 56;; Some output patterns want integer immediates with a prefix...
20acd226 57(define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")])
ab835497 58
e552abe2
MR		 59(define_mode_iterator VAXcc [CC CCN CCNZ CCZ])
60(define_mode_iterator VAXccnz [CCN CCNZ CCZ])
61(define_mode_attr cc [(CC "cc") (CCN "ccn") (CCNZ "ccnz") (CCZ "ccz")])
62
63(define_code_iterator any_extract [sign_extract zero_extract])
64
c4e75102
MT		 65;;
66(include "constraints.md")
67(include "predicates.md")
68
e552abe2
MR		 69;; Make instructions that set the N, N+Z, and Z condition codes respectively.
70(define_subst "subst_<cc>"
71 [(set (match_operand 0 "")
72 (match_operand 1 ""))
73 (clobber (reg:CC VAX_PSL_REGNUM))]
ab835497 74 ""
e552abe2
MR		 75 [(set (reg:VAXccnz VAX_PSL_REGNUM)
76 (compare:VAXccnz (match_dup 1)
77 (const_int 0)))
78 (set (match_dup 0)
79 (match_dup 1))])
80
81(define_subst "subst_f<cc>"
82 [(set (match_operand 0 "")
83 (match_operand 1 ""))
84 (clobber (reg:CC VAX_PSL_REGNUM))]
85 ""
86 [(set (reg:VAXccnz VAX_PSL_REGNUM)
87 (compare:VAXccnz (match_dup 1)
88 (const_double_zero)))
89 (set (match_dup 0)
90 (match_dup 1))])
91
92;; Select all from the attributes below that apply to a given insn that
93;; has a clobber on CC for the comparison elimination pass to use it in
94;; place of a subsequent comparison instruction matching the mode used
95;; by a comparison operator in branch.
96;;
97;; For example a branch doing `eq' in SImode will use `*cmpsi_ccz', so
98;; to eliminate it a `*movsi_ccz', etc. pattern will be required via the
99;; `ccz' substitution. Analogously for the other CC modes.
100;;
101;; The general `cc' mode, which sets all of the C, N, V and Z condition
102;; codes, has to be handled specially as it makes no sense for the usual
103;; comparison against zero, so no substitution has been defined for it.
104(define_subst_attr "ccn" "subst_ccn" "" "_ccn")
105(define_subst_attr "ccnz" "subst_ccnz" "" "_ccnz")
106(define_subst_attr "ccz" "subst_ccz" "" "_ccz")
107(define_subst_attr "fccn" "subst_fccn" "" "_ccn")
108(define_subst_attr "fccnz" "subst_fccnz" "" "_ccnz")
109(define_subst_attr "fccz" "subst_fccz" "" "_ccz")
110
111(define_insn "*cmp<VAXint:mode>_<VAXcc:mode>"
112 [(set (reg:VAXcc VAX_PSL_REGNUM)
113 (compare:VAXcc (match_operand:VAXint 0 "general_operand" "nrmT,nrmT")
114 (match_operand:VAXint 1 "general_operand" "I,nrmT")))]
115 "reload_completed"
f90b7a5a
PB		 116 "@
117 tst<VAXint:isfx> %0
118 cmp<VAXint:isfx> %0,%1")
ab835497 119
e552abe2
MR		 120;; We don't have a CMPQ instruction, but we can set the N and Z condition
121;; codes with MOVQ, and also this comparison can be folded into a preceding
122;; operation by the post-reload comparison elimination pass.
123(define_insn "*cmpdi_<VAXccnz:mode>"
124 [(set (reg:VAXccnz VAX_PSL_REGNUM)
125 (compare:VAXccnz (match_operand:DI 0 "general_operand" "r,nmT")
126 (match_operand:DI 1 "const_zero_operand" "I,I")))
127 (clobber (match_scratch:DI 2 "=X,r"))]
128 "reload_completed"
129 "@
130 movq %0,%0
131 movq %0,%2")
132
133(define_insn "*cmp<VAXfp:mode>_<VAXccnz:mode>"
134 [(set (reg:VAXccnz VAX_PSL_REGNUM)
135 (compare:VAXccnz (match_operand:VAXfp 0 "general_operand" "gF,gF")
136 (match_operand:VAXfp 1 "general_operand" "G,gF")))]
137 "reload_completed"
00a8faa3 138 "@
20acd226
SB		 139 tst<VAXfp:fsfx> %0
140 cmp<VAXfp:fsfx> %0,%1")
ab835497 141
e552abe2
MR		 142(define_insn "*bit<VAXint:mode>_<VAXccnz:mode>"
143 [(set (reg:VAXccnz VAX_PSL_REGNUM)
144 (compare:VAXccnz
145 (and:VAXint (match_operand:VAXint 0 "general_operand" "nrmT")
146 (match_operand:VAXint 1 "general_operand" "nrmT"))
147 (const_int 0)))]
148 "reload_completed"
20acd226 149 "bit<VAXint:isfx> %0,%1")
ab835497 150
8aeea6e6 151;; The VAX has no sCOND insns. It does have add/subtract with carry
76f941a8
DA		 152;; which could be used to implement the sltu and sgeu patterns. However,
153;; to do this properly requires a complete rewrite of the compare insns
154;; to keep them together with the sltu/sgeu insns until after the
155;; reload pass is complete. The previous implementation didn't do this
156;; and has been deleted.
ab835497 157
ab835497 158\f
e552abe2 159(define_insn_and_split "mov<mode>"
20acd226
SB		 160 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
161 (match_operand:VAXfp 1 "general_operand" "G,gF"))]
ab835497 162 ""
e552abe2
MR		 163 "#"
164 "reload_completed"
165 [(parallel
166 [(set (match_dup 0)
167 (match_dup 1))
168 (clobber (reg:CC VAX_PSL_REGNUM))])]
169 "")
170
171(define_insn "*mov<mode><fccn><fccnz><fccz>"
172 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
173 (match_operand:VAXfp 1 "general_operand" "G,gF"))
174 (clobber (reg:CC VAX_PSL_REGNUM))]
175 "reload_completed"
ab835497 176 "@
20acd226
SB		 177 clr<VAXfp:fsfx> %0
178 mov<VAXfp:fsfx> %1,%0")
ab835497 179
8aeea6e6 180;; Some VAXen don't support this instruction.
e552abe2 181;;(define_insn_and_split "movti"
3c085897 182;; [(set (match_operand:TI 0 "nonimmediate_operand" "=g")
ab835497
RK		 183;; (match_operand:TI 1 "general_operand" "g"))]
184;; ""
e552abe2
MR		 185;; "#"
186;; "reload_completed"
187;; [(parallel
188;; [(set (match_dup 0)
189;; (match_dup 1))
190;; (clobber (reg:CC VAX_PSL_REGNUM))])]
191;; "")
192;;
193;;(define_insn "*movti<ccn><ccnz><ccz>"
194;; [(set (match_operand:TI 0 "nonimmediate_operand" "=g")
195;; (match_operand:TI 1 "general_operand" "g"))
196;; (clobber (reg:CC VAX_PSL_REGNUM))]
197;; "reload_completed"
3c085897 198;; "movo %1,%0")
ab835497 199
e552abe2 200(define_insn_and_split "movdi"
c4e75102
MT		 201 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
202 (match_operand:DI 1 "general_operand" "g"))]
ab835497 203 ""
e552abe2
MR		 204 "#"
205 "reload_completed"
206 [(parallel
207 [(set (match_dup 0)
208 (match_dup 1))
209 (clobber (reg:CC VAX_PSL_REGNUM))])]
210 "")
211
212;; In some cases `vax_output_int_move' splits a `DImode' move into a pair
213;; of `SImode' moves, in which case the flags aren't usefully set. Have
214;; separate patterns then, for the cases where the move may and may not be
215;; split each. We use the outer condition only so in some cases we will
216;; fail to notice the move does not actually get split, but this is OK.
217(define_insn "*movdi_maybe_split"
218 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
219 (match_operand:DI 1 "general_operand" "g"))
220 (clobber (reg:CC VAX_PSL_REGNUM))]
221 "reload_completed && vax_maybe_split_dimode_move (operands)"
222 "* return vax_output_int_move (insn, operands, DImode);")
223
224(define_insn "*movdi_unsplit<ccn><ccnz><ccz>"
225 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
226 (match_operand:DI 1 "general_operand" "g"))
227 (clobber (reg:CC VAX_PSL_REGNUM))]
228 "reload_completed && !vax_maybe_split_dimode_move (operands)"
c4e75102 229 "* return vax_output_int_move (insn, operands, DImode);")
ab835497 230
8aeea6e6 231;; The VAX move instructions have space-time tradeoffs. On a MicroVAX
00a8faa3
RK		 232;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl
233;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles
234;; if the constant is smaller than 4 bytes, 3 cycles for a longword
235;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster
236;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt
237;; instructions take 4 cycles. inc takes 3 cycles. The machine description
238;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
239;; instead of movl).
240
241;; Cycle counts for other models may vary (on a VAX 750 they are similar,
242;; but on a VAX 9000 most move and add instructions with one constant
243;; operand take 1 cycle).
244
245;; Loads of constants between 64 and 128 used to be done with
246;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
247
c4e75102
MT		 248(define_expand "movsi"
249 [(set (match_operand:SI 0 "nonimmediate_operand" "")
250 (match_operand:SI 1 "general_operand" ""))]
251 ""
252 "
253{
254#ifdef NO_EXTERNAL_INDIRECT_ADDRESS
255 if (flag_pic
256 && GET_CODE (operands[1]) == CONST
257 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF
258 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0)))
259 {
260 rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0);
261 rtx const_int = XEXP (XEXP (operands[1], 0), 1);
262 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
263 emit_move_insn (temp, symbol_ref);
264 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int));
265 DONE;
266 }
267#endif
268}")
269
e552abe2 270(define_insn_and_split "movsi_2"
c4e75102
MT		 271 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
272 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))]
273 ""
e552abe2
MR		 274 "#"
275 "reload_completed"
276 [(parallel
277 [(set (match_dup 0)
278 (match_dup 1))
279 (clobber (reg:CC VAX_PSL_REGNUM))])]
280 "")
281
282(define_insn "*movsi_2<ccn><ccnz><ccz>"
283 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
284 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))
285 (clobber (reg:CC VAX_PSL_REGNUM))]
286 "reload_completed"
c4e75102
MT		 287 "* return vax_output_int_move (insn, operands, SImode);")
288
e552abe2 289(define_insn_and_split "mov<mode>"
c4e75102
MT		 290 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g")
291 (match_operand:VAXintQH 1 "general_operand" "g"))]
ab835497 292 ""
e552abe2
MR		 293 "#"
294 "reload_completed"
295 [(parallel
296 [(set (match_dup 0)
297 (match_dup 1))
298 (clobber (reg:CC VAX_PSL_REGNUM))])]
299 "")
300
301(define_insn "*mov<mode><ccn><ccnz><ccz>"
302 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g")
303 (match_operand:VAXintQH 1 "general_operand" "g"))
304 (clobber (reg:CC VAX_PSL_REGNUM))]
305 "reload_completed"
20acd226 306 "* return vax_output_int_move (insn, operands, <MODE>mode);")
00a8faa3 307
e552abe2
MR		 308(define_insn_and_split "movstricthi"
309 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
00a8faa3
RK		 310 (match_operand:HI 1 "general_operand" "g"))]
311 ""
e552abe2
MR		 312 "#"
313 "reload_completed"
314 [(parallel
315 [(set (strict_low_part (match_dup 0))
316 (match_dup 1))
317 (clobber (reg:CC VAX_PSL_REGNUM))])]
318 "")
319
320(define_insn "*movstricthi<ccn><ccnz><ccz>"
321 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
322 (match_operand:HI 1 "general_operand" "g"))
323 (clobber (reg:CC VAX_PSL_REGNUM))]
324 "reload_completed"
00a8faa3
RK		 325 "*
326{
d97c1295 327 if (CONST_INT_P (operands[1]))
ab835497
RK		 328 {
329 int i = INTVAL (operands[1]);
00a8faa3
RK		 330 if (i == 0)
331 return \"clrw %0\";
332 else if ((unsigned int)i < 64)
333 return \"movw %1,%0\";
334 else if ((unsigned int)~i < 64)
335 return \"mcomw %H1,%0\";
336 else if ((unsigned int)i < 256)
337 return \"movzbw %1,%0\";
ab835497
RK		 338 }
339 return \"movw %1,%0\";
340}")
341
e552abe2
MR		 342(define_insn_and_split "movstrictqi"
343 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
00a8faa3
RK		 344 (match_operand:QI 1 "general_operand" "g"))]
345 ""
e552abe2
MR		 346 "#"
347 "reload_completed"
348 [(parallel
349 [(set (strict_low_part (match_dup 0))
350 (match_dup 1))
351 (clobber (reg:CC VAX_PSL_REGNUM))])]
352 "")
353
354(define_insn "*movstrictqi<ccn><ccnz><ccz>"
355 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
356 (match_operand:QI 1 "general_operand" "g"))
357 (clobber (reg:CC VAX_PSL_REGNUM))]
358 "reload_completed"
00a8faa3
RK		 359 "*
360{
d97c1295 361 if (CONST_INT_P (operands[1]))
ab835497
RK		 362 {
363 int i = INTVAL (operands[1]);
00a8faa3
RK		 364 if (i == 0)
365 return \"clrb %0\";
366 else if ((unsigned int)~i < 64)
367 return \"mcomb %B1,%0\";
ab835497
RK		 368 }
369 return \"movb %1,%0\";
370}")
371
7133bb7f 372;; This is here to accept 4 arguments and pass the first 3 along
e93fbce8 373;; to the movmemhi1 pattern that really does the work.
76715c32 374(define_expand "cpymemhi"
e93fbce8
MR		 375 [(set (match_operand:BLK 0 "memory_operand" "")
376 (match_operand:BLK 1 "memory_operand" ""))
377 (use (match_operand:HI 2 "general_operand" ""))
7133bb7f
RS		 378 (match_operand 3 "" "")]
379 ""
380 "
c4e75102 381{
e93fbce8
MR		 382 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
383 DONE;
384}")
385
386(define_expand "movmemhi"
387 [(set (match_operand:BLK 0 "memory_operand" "")
388 (match_operand:BLK 1 "memory_operand" ""))
389 (use (match_operand:HI 2 "general_operand" ""))
390 (match_operand 3 "" "")]
391 ""
392 "
393{
394 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
7133bb7f 395 DONE;
c4e75102 396}")
7133bb7f 397
ab835497
RK		 398;; The definition of this insn does not really explain what it does,
399;; but it should suffice
400;; that anything generated as this insn will be recognized as one
401;; and that it won't successfully combine with anything.
c4e75102 402
e552abe2 403(define_insn_and_split "movmemhi1"
c4e75102
MT		 404 [(set (match_operand:BLK 0 "memory_operand" "=o")
405 (match_operand:BLK 1 "memory_operand" "o"))
ab835497
RK		 406 (use (match_operand:HI 2 "general_operand" "g"))
407 (clobber (reg:SI 0))
408 (clobber (reg:SI 1))
409 (clobber (reg:SI 2))
410 (clobber (reg:SI 3))
411 (clobber (reg:SI 4))
412 (clobber (reg:SI 5))]
413 ""
e552abe2
MR		 414 "#"
415 "reload_completed"
416 [(parallel
417 [(set (match_dup 0)
418 (match_dup 1))
419 (use (match_dup 2))
420 (clobber (reg:SI 0))
421 (clobber (reg:SI 1))
422 (clobber (reg:SI 2))
423 (clobber (reg:SI 3))
424 (clobber (reg:SI 4))
425 (clobber (reg:SI 5))
426 (clobber (reg:CC VAX_PSL_REGNUM))])]
427 "")
428
429(define_insn "*movmemhi1"
430 [(set (match_operand:BLK 0 "memory_operand" "=o")
431 (match_operand:BLK 1 "memory_operand" "o"))
432 (use (match_operand:HI 2 "general_operand" "g"))
433 (clobber (reg:SI 0))
434 (clobber (reg:SI 1))
435 (clobber (reg:SI 2))
436 (clobber (reg:SI 3))
437 (clobber (reg:SI 4))
438 (clobber (reg:SI 5))
439 (clobber (reg:CC VAX_PSL_REGNUM))]
440 "reload_completed"
ab835497
RK		 441 "movc3 %2,%1,%0")
442\f
443;; Extension and truncation insns.
444
e552abe2 445(define_insn_and_split "truncsiqi2"
17ad4377 446 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
c4e75102 447 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
ab835497 448 ""
e552abe2
MR		 449 "#"
450 "reload_completed"
451 [(parallel
452 [(set (match_dup 0)
453 (truncate:QI (match_dup 1)))
454 (clobber (reg:CC VAX_PSL_REGNUM))])]
455 "")
456
457(define_insn "*truncsiqi2<ccn><ccnz><ccz>"
458 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
459 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))
460 (clobber (reg:CC VAX_PSL_REGNUM))]
461 "reload_completed"
ab835497
RK		 462 "cvtlb %1,%0")
463
e552abe2 464(define_insn_and_split "truncsihi2"
17ad4377 465 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
c4e75102 466 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
ab835497 467 ""
e552abe2
MR		 468 "#"
469 "reload_completed"
470 [(parallel
471 [(set (match_dup 0)
472 (truncate:HI (match_dup 1)))
473 (clobber (reg:CC VAX_PSL_REGNUM))])]
474 "")
475
476(define_insn "*truncsihi2<ccn><ccnz><ccz>"
477 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
478 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))
479 (clobber (reg:CC VAX_PSL_REGNUM))]
480 "reload_completed"
ab835497
RK		 481 "cvtlw %1,%0")
482
e552abe2 483(define_insn_and_split "trunchiqi2"
17ad4377 484 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
ab835497
RK		 485 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
486 ""
e552abe2
MR		 487 "#"
488 "reload_completed"
489 [(parallel
490 [(set (match_dup 0)
491 (truncate:QI (match_dup 1)))
492 (clobber (reg:CC VAX_PSL_REGNUM))])]
493 "")
494
495(define_insn "*trunchiqi2<ccn><ccnz><ccz>"
496 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
497 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))
498 (clobber (reg:CC VAX_PSL_REGNUM))]
499 "reload_completed"
ab835497
RK		 500 "cvtwb %1,%0")
501
e552abe2 502(define_insn_and_split "extendhisi2"
17ad4377 503 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
ab835497
RK		 504 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
505 ""
e552abe2
MR		 506 "#"
507 "reload_completed"
508 [(parallel
509 [(set (match_dup 0)
510 (sign_extend:SI (match_dup 1)))
511 (clobber (reg:CC VAX_PSL_REGNUM))])]
512 "")
513
514(define_insn "*extendhisi2<ccn><ccnz><ccz>"
515 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
516 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))
517 (clobber (reg:CC VAX_PSL_REGNUM))]
518 "reload_completed"
ab835497
RK		 519 "cvtwl %1,%0")
520
e552abe2 521(define_insn_and_split "extendqihi2"
17ad4377 522 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
ab835497
RK		 523 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
524 ""
e552abe2
MR		 525 "#"
526 "reload_completed"
527 [(parallel
528 [(set (match_dup 0)
529 (sign_extend:HI (match_dup 1)))
530 (clobber (reg:CC VAX_PSL_REGNUM))])]
531 "")
532
533(define_insn "*extendqihi2<ccn><ccnz><ccz>"
534 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
535 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))
536 (clobber (reg:CC VAX_PSL_REGNUM))]
537 "reload_completed"
ab835497
RK		 538 "cvtbw %1,%0")
539
e552abe2 540(define_insn_and_split "extendqisi2"
17ad4377 541 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
ab835497
RK		 542 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
543 ""
e552abe2
MR		 544 "#"
545 "reload_completed"
546 [(parallel
547 [(set (match_dup 0)
548 (sign_extend:SI (match_dup 1)))
549 (clobber (reg:CC VAX_PSL_REGNUM))])]
550 "")
551
552(define_insn "*extendqisi2<ccn><ccnz><ccz>"
553 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
554 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
555 (clobber (reg:CC VAX_PSL_REGNUM))]
556 "reload_completed"
ab835497
RK		 557 "cvtbl %1,%0")
558
e552abe2 559(define_insn_and_split "extendsfdf2"
17ad4377 560 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
ab835497
RK		 561 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
562 ""
e552abe2
MR		 563 "#"
564 "reload_completed"
565 [(parallel
566 [(set (match_dup 0)
567 (float_extend:DF (match_dup 1)))
568 (clobber (reg:CC VAX_PSL_REGNUM))])]
569 "")
570
571(define_insn "*extendsfdf2<fccn><fccnz><fccz>"
572 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
573 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))
574 (clobber (reg:CC VAX_PSL_REGNUM))]
575 "reload_completed"
ab835497
RK		 576 "cvtf%# %1,%0")
577
e552abe2 578(define_insn_and_split "truncdfsf2"
17ad4377 579 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
ab835497
RK		 580 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
581 ""
e552abe2
MR		 582 "#"
583 "reload_completed"
584 [(parallel
585 [(set (match_dup 0)
586 (float_truncate:SF (match_dup 1)))
587 (clobber (reg:CC VAX_PSL_REGNUM))])]
588 "")
589
590(define_insn "*truncdfsf2<fccn><fccnz><fccz>"
591 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
592 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))
593 (clobber (reg:CC VAX_PSL_REGNUM))]
594 "reload_completed"
ab835497
RK		 595 "cvt%#f %1,%0")
596
e552abe2 597(define_insn_and_split "zero_extendhisi2"
17ad4377 598 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
ab835497
RK		 599 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
600 ""
e552abe2
MR		 601 "#"
602 "reload_completed"
603 [(parallel
604 [(set (match_dup 0)
605 (zero_extend:SI (match_dup 1)))
606 (clobber (reg:CC VAX_PSL_REGNUM))])]
607 "")
608
609(define_insn "*zero_extendhisi2<ccn><ccnz><ccz>"
610 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
611 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))
612 (clobber (reg:CC VAX_PSL_REGNUM))]
613 "reload_completed"
ab835497
RK		 614 "movzwl %1,%0")
615
e552abe2 616(define_insn_and_split "zero_extendqihi2"
17ad4377 617 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
ab835497
RK		 618 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
619 ""
e552abe2
MR		 620 "#"
621 "reload_completed"
622 [(parallel
623 [(set (match_dup 0)
624 (zero_extend:HI (match_dup 1)))
625 (clobber (reg:CC VAX_PSL_REGNUM))])]
626 "")
627
628(define_insn "*zero_extendqihi2<ccn><ccnz><ccz>"
629 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
630 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))
631 (clobber (reg:CC VAX_PSL_REGNUM))]
632 "reload_completed"
ab835497
RK		 633 "movzbw %1,%0")
634
e552abe2 635(define_insn_and_split "zero_extendqisi2"
17ad4377 636 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
ab835497
RK		 637 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
638 ""
e552abe2
MR		 639 "#"
640 "reload_completed"
641 [(parallel
642 [(set (match_dup 0)
643 (zero_extend:SI (match_dup 1)))
644 (clobber (reg:CC VAX_PSL_REGNUM))])]
645 "")
646
647(define_insn "*zero_extendqisi2<ccn><ccnz><ccz>"
648 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
649 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
650 (clobber (reg:CC VAX_PSL_REGNUM))]
651 "reload_completed"
ab835497
RK		 652 "movzbl %1,%0")
653\f
654;; Fix-to-float conversion insns.
655
e552abe2 656(define_insn_and_split "float<VAXint:mode><VAXfp:mode>2"
20acd226
SB		 657 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
658 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))]
ab835497 659 ""
e552abe2
MR		 660 "#"
661 "reload_completed"
662 [(parallel
663 [(set (match_dup 0)
664 (float:VAXfp (match_dup 1)))
665 (clobber (reg:CC VAX_PSL_REGNUM))])]
666 "")
667
668(define_insn "*float<VAXint:mode><VAXfp:mode>2<fccn><fccnz><fccz>"
669 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
670 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))
671 (clobber (reg:CC VAX_PSL_REGNUM))]
672 "reload_completed"
20acd226 673 "cvt<VAXint:isfx><VAXfp:fsfx> %1,%0")
ab835497 674
ab835497
RK		 675;; Float-to-fix conversion insns.
676
e552abe2 677(define_insn_and_split "fix_trunc<VAXfp:mode><VAXint:mode>2"
20acd226 678 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
5e4aec98 679 (fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF")))]
ab835497 680 ""
e552abe2
MR		 681 "#"
682 "reload_completed"
683 [(parallel
684 [(set (match_dup 0)
685 (fix:VAXint (match_dup 1)))
686 (clobber (reg:CC VAX_PSL_REGNUM))])]
687 "")
688
689(define_insn "*fix_trunc<VAXfp:mode><VAXint:mode>2<ccn><ccnz><ccz>"
690 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
691 (fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF")))
692 (clobber (reg:CC VAX_PSL_REGNUM))]
693 "reload_completed"
20acd226 694 "cvt<VAXfp:fsfx><VAXint:isfx> %1,%0")
5e4aec98
RH		 695
696(define_expand "fixuns_trunc<VAXfp:mode><VAXint:mode>2"
697 [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
698 (fix:VAXint (match_operand:VAXfp 1 "general_operand")))]
699 "")
ab835497
RK		 700\f
701;;- All kinds of add instructions.
702
e552abe2 703(define_insn_and_split "add<mode>3"
20acd226
SB		 704 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
705 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
706 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
ab835497 707 ""
e552abe2
MR		 708 "#"
709 "reload_completed"
710 [(parallel
711 [(set (match_dup 0)
712 (plus:VAXfp (match_dup 1)
713 (match_dup 2)))
714 (clobber (reg:CC VAX_PSL_REGNUM))])]
715 "")
716
717(define_insn "*add<mode>3<fccn><fccnz><fccz>"
718 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
719 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
720 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))
721 (clobber (reg:CC VAX_PSL_REGNUM))]
722 "reload_completed"
ab835497 723 "@
20acd226
SB		 724 add<VAXfp:fsfx>2 %2,%0
725 add<VAXfp:fsfx>2 %1,%0
726 add<VAXfp:fsfx>3 %1,%2,%0")
ab835497 727
e552abe2 728(define_insn_and_split "add<mode>3"
20acd226 729 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
c4e75102 730 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")
f78ac4f2 731 (match_operand:VAXint 2 "general_operand" "nrmT")))]
ab835497 732 ""
e552abe2
MR		 733 "#"
734 "reload_completed"
735 [(parallel
736 [(set (match_dup 0)
737 (plus:VAXint (match_dup 1)
738 (match_dup 2)))
739 (clobber (reg:CC VAX_PSL_REGNUM))])]
740 "")
741
742(define_insn "*add<mode>3<ccn><ccnz><ccz>"
743 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
744 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")
745 (match_operand:VAXint 2 "general_operand" "nrmT")))
746 (clobber (reg:CC VAX_PSL_REGNUM))]
747 "reload_completed"
20acd226 748 "* return vax_output_int_add (insn, operands, <MODE>mode);")
ab835497 749
c4e75102
MT		 750(define_expand "adddi3"
751 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
752 (plus:DI (match_operand:DI 1 "general_operand" "g")
753 (match_operand:DI 2 "general_operand" "g")))]
754 "!reload_in_progress"
755 "vax_expand_addsub_di_operands (operands, PLUS); DONE;")
756
e552abe2 757(define_insn_and_split "adcdi3"
c4e75102
MT		 758 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr")
759 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0")
760 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))]
761 "TARGET_QMATH"
e552abe2
MR		 762 "#"
763 "&& reload_completed"
764 [(parallel
765 [(set (match_dup 0)
766 (plus:DI (match_dup 1)
767 (match_dup 2)))
768 (clobber (reg:CC VAX_PSL_REGNUM))])]
769 "")
770
771(define_insn "*adcdi3<ccn>"
772 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr")
773 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0")
774 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))
775 (clobber (reg:CC VAX_PSL_REGNUM))]
776 "TARGET_QMATH && reload_completed"
c4e75102
MT		 777 "* return vax_output_int_add (insn, operands, DImode);")
778
ab835497 779;; The add-with-carry (adwc) instruction only accepts two operands.
e552abe2 780(define_insn_and_split "adddi3_old"
17ad4377 781 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
ab835497 782 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
c4e75102
MT		 783 (match_operand:DI 2 "general_operand" "Fsro,Fs")))]
784 "!TARGET_QMATH"
e552abe2
MR		 785 "#"
786 "&& reload_completed"
787 [(parallel
788 [(set (match_dup 0)
789 (plus:DI (match_dup 1)
790 (match_dup 2)))
791 (clobber (reg:CC VAX_PSL_REGNUM))])]
792 "")
793
794(define_insn "*adddi3_old<ccn>"
795 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
796 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
797 (match_operand:DI 2 "general_operand" "Fsro,Fs")))
798 (clobber (reg:CC VAX_PSL_REGNUM))]
799 "!TARGET_QMATH && reload_completed"
c4e75102 800 "* return vax_output_int_add (insn, operands, DImode);")
ab835497
RK		 801\f
802;;- All kinds of subtract instructions.
803
e552abe2 804(define_insn_and_split "sub<mode>3"
20acd226
SB		 805 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
806 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
807 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
ab835497 808 ""
e552abe2
MR		 809 "#"
810 "reload_completed"
811 [(parallel
812 [(set (match_dup 0)
813 (minus:VAXfp (match_dup 1)
814 (match_dup 2)))
815 (clobber (reg:CC VAX_PSL_REGNUM))])]
816 "")
817
818(define_insn "*sub<mode>3<fccn><fccnz><fccz>"
819 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
820 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
821 (match_operand:VAXfp 2 "general_operand" "gF,gF")))
822 (clobber (reg:CC VAX_PSL_REGNUM))]
823 "reload_completed"
ab835497 824 "@
20acd226
SB		 825 sub<VAXfp:fsfx>2 %2,%0
826 sub<VAXfp:fsfx>3 %2,%1,%0")
ab835497 827
e552abe2 828(define_insn_and_split "sub<mode>3"
20acd226 829 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
c4e75102 830 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
f78ac4f2 831 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
ab835497 832 ""
e552abe2
MR		 833 "#"
834 "reload_completed"
835 [(parallel
836 [(set (match_dup 0)
837 (minus:VAXint (match_dup 1)
838 (match_dup 2)))
839 (clobber (reg:CC VAX_PSL_REGNUM))])]
840 "")
841
842(define_insn "*sub<mode>3<ccn><ccnz><ccz>"
843 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
844 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
845 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))
846 (clobber (reg:CC VAX_PSL_REGNUM))]
847 "reload_completed"
848 "@
849 sub<VAXint:isfx>2 %2,%0
850 sub<VAXint:isfx>3 %2,%1,%0")
851
852(define_insn "*sub<mode>3_cc"
853 [(set (reg:CC VAX_PSL_REGNUM)
854 (compare:CC (match_operand:VAXint 1 "general_operand" "0,nrmT")
855 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))
856 (set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
857 (minus:VAXint (match_dup 1)
858 (match_dup 2)))]
859 "reload_completed"
ab835497 860 "@
20acd226
SB		 861 sub<VAXint:isfx>2 %2,%0
862 sub<VAXint:isfx>3 %2,%1,%0")
ab835497 863
c4e75102
MT		 864(define_expand "subdi3"
865 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
866 (minus:DI (match_operand:DI 1 "general_operand" "g")
867 (match_operand:DI 2 "general_operand" "g")))]
868 "!reload_in_progress"
869 "vax_expand_addsub_di_operands (operands, MINUS); DONE;")
870
e552abe2 871(define_insn_and_split "sbcdi3"
73f793e3 872 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,Rr")
c4e75102
MT		 873 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
874 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))]
875 "TARGET_QMATH"
e552abe2
MR		 876 "#"
877 "&& reload_completed"
878 [(parallel
879 [(set (match_dup 0)
880 (minus:DI (match_dup 1)
881 (match_dup 2)))
882 (clobber (reg:CC VAX_PSL_REGNUM))])]
883 "")
884
885(define_insn "*sbcdi3<ccn>"
886 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,Rr")
887 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
888 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))
889 (clobber (reg:CC VAX_PSL_REGNUM))]
890 "TARGET_QMATH && reload_completed"
c4e75102
MT		 891 "* return vax_output_int_subtract (insn, operands, DImode);")
892
ab835497 893;; The subtract-with-carry (sbwc) instruction only takes two operands.
e552abe2 894(define_insn_and_split "subdi3_old"
17ad4377 895 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
ab835497 896 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
c4e75102
MT		 897 (match_operand:DI 2 "general_operand" "Fsor,Fs")))]
898 "!TARGET_QMATH"
e552abe2
MR		 899 "#"
900 "&& reload_completed"
901 [(parallel
902 [(set (match_dup 0)
903 (minus:DI (match_dup 1)
904 (match_dup 2)))
905 (clobber (reg:CC VAX_PSL_REGNUM))])]
906 "")
907
908(define_insn "*subdi3_old<ccn>"
909 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
910 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
911 (match_operand:DI 2 "general_operand" "Fsor,Fs")))
912 (clobber (reg:CC VAX_PSL_REGNUM))]
913 "!TARGET_QMATH && reload_completed"
c4e75102 914 "* return vax_output_int_subtract (insn, operands, DImode);")
ab835497
RK		 915\f
916;;- Multiply instructions.
917
e552abe2 918(define_insn_and_split "mul<mode>3"
20acd226
SB		 919 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
920 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
921 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
ab835497 922 ""
e552abe2
MR		 923 "#"
924 "reload_completed"
925 [(parallel
926 [(set (match_dup 0)
927 (mult:VAXfp (match_dup 1)
928 (match_dup 2)))
929 (clobber (reg:CC VAX_PSL_REGNUM))])]
930 "")
931
932(define_insn "*mul<mode>3<fccn><fccnz><fccz>"
933 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
934 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
935 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))
936 (clobber (reg:CC VAX_PSL_REGNUM))]
937 "reload_completed"
ab835497 938 "@
20acd226
SB		 939 mul<VAXfp:fsfx>2 %2,%0
940 mul<VAXfp:fsfx>2 %1,%0
941 mul<VAXfp:fsfx>3 %1,%2,%0")
ab835497 942
e552abe2 943(define_insn_and_split "mul<mode>3"
20acd226 944 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
c4e75102 945 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
f78ac4f2 946 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
ab835497 947 ""
e552abe2
MR		 948 "#"
949 "reload_completed"
950 [(parallel
951 [(set (match_dup 0)
952 (mult:VAXint (match_dup 1)
953 (match_dup 2)))
954 (clobber (reg:CC VAX_PSL_REGNUM))])]
955 "")
956
957(define_insn "*mul<mode>3<ccn><ccnz><ccz>"
958 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
959 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
960 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))
961 (clobber (reg:CC VAX_PSL_REGNUM))]
962 "reload_completed"
ab835497 963 "@
20acd226
SB		 964 mul<VAXint:isfx>2 %2,%0
965 mul<VAXint:isfx>2 %1,%0
966 mul<VAXint:isfx>3 %1,%2,%0")
ab835497 967
e552abe2 968(define_insn_and_split "mulsidi3"
17ad4377 969 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
2b39f513
MR		 970 (mult:DI
971 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
972 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))))]
ab835497 973 ""
e552abe2
MR		 974 "#"
975 "reload_completed"
976 [(parallel
977 [(set (match_dup 0)
978 (mult:DI
979 (sign_extend:DI (match_dup 1))
980 (sign_extend:DI (match_dup 2))))
981 (clobber (reg:CC VAX_PSL_REGNUM))])]
982 "")
983
984(define_insn "*mulsidi3<ccn><ccnz><ccz>"
985 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
986 (mult:DI
987 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
988 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))))
989 (clobber (reg:CC VAX_PSL_REGNUM))]
990 "reload_completed"
ab835497
RK		 991 "emul %1,%2,$0,%0")
992
e552abe2 993(define_insn_and_split "*maddsidi4"
17ad4377 994 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
ab835497 995 (plus:DI
2b39f513
MR		 996 (mult:DI
997 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
998 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
999 (sign_extend:DI (match_operand:SI 3 "general_operand" "g"))))]
ab835497 1000 ""
e552abe2
MR		 1001 "#"
1002 "reload_completed"
1003 [(parallel
1004 [(set (match_dup 0)
1005 (plus:DI
1006 (mult:DI
1007 (sign_extend:DI (match_dup 1))
1008 (sign_extend:DI (match_dup 2)))
1009 (sign_extend:DI (match_dup 3))))
1010 (clobber (reg:CC VAX_PSL_REGNUM))])]
1011 "")
1012
1013(define_insn "*maddsidi4_2<ccn><ccnz><ccz>"
1014 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1015 (plus:DI
1016 (mult:DI
1017 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1018 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
1019 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))
1020 (clobber (reg:CC VAX_PSL_REGNUM))]
1021 "reload_completed"
ab835497
RK		 1022 "emul %1,%2,%3,%0")
1023
1024;; 'F' constraint means type CONST_DOUBLE
e552abe2 1025(define_insn_and_split "*maddsidi4_const"
17ad4377 1026 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
ab835497 1027 (plus:DI
2b39f513
MR		 1028 (mult:DI
1029 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1030 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
1031 (match_operand:DI 3 "immediate_operand" "F")))]
821bde61 1032 "GET_CODE (operands[3]) == CONST_DOUBLE
2b39f513 1033 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
e552abe2
MR		 1034 "#"
1035 "&& reload_completed"
1036 [(parallel
1037 [(set (match_dup 0)
1038 (plus:DI
1039 (mult:DI
1040 (sign_extend:DI (match_dup 1))
1041 (sign_extend:DI (match_dup 2)))
1042 (match_dup 3)))
1043 (clobber (reg:CC VAX_PSL_REGNUM))])]
1044 "")
1045
1046(define_insn "*maddsidi4_const_2<ccn><ccnz><ccz>"
1047 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1048 (plus:DI
1049 (mult:DI
1050 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1051 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
1052 (match_operand:DI 3 "immediate_operand" "F")))
1053 (clobber (reg:CC VAX_PSL_REGNUM))]
1054 "GET_CODE (operands[3]) == CONST_DOUBLE
1055 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)
1056 && reload_completed"
ab835497
RK		 1057 "*
1058{
1059 if (CONST_DOUBLE_HIGH (operands[3]))
3a598fbe 1060 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
ab835497
RK		 1061 return \"emul %1,%2,%3,%0\";
1062}")
1063\f
1064;;- Divide instructions.
1065
e552abe2 1066(define_insn_and_split "div<mode>3"
20acd226
SB		 1067 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
1068 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
1069 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
ab835497 1070 ""
e552abe2
MR		 1071 "#"
1072 "reload_completed"
1073 [(parallel
1074 [(set (match_dup 0)
1075 (div:VAXfp (match_dup 1)
1076 (match_dup 2)))
1077 (clobber (reg:CC VAX_PSL_REGNUM))])]
1078 "")
1079
1080(define_insn "*div<mode>3<fccn><fccnz><fccz>"
1081 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
1082 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
1083 (match_operand:VAXfp 2 "general_operand" "gF,gF")))
1084 (clobber (reg:CC VAX_PSL_REGNUM))]
1085 "reload_completed"
ab835497 1086 "@
20acd226
SB		 1087 div<VAXfp:fsfx>2 %2,%0
1088 div<VAXfp:fsfx>3 %2,%1,%0")
ab835497 1089
e552abe2 1090(define_insn_and_split "div<mode>3"
20acd226 1091 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
c4e75102 1092 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
f78ac4f2 1093 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
ab835497 1094 ""
e552abe2
MR		 1095 "#"
1096 "reload_completed"
1097 [(parallel
1098 [(set (match_dup 0)
1099 (div:VAXint (match_dup 1)
1100 (match_dup 2)))
1101 (clobber (reg:CC VAX_PSL_REGNUM))])]
1102 "")
1103
1104(define_insn "*div<mode>3<ccn><ccnz><ccz>"
1105 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1106 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
1107 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))
1108 (clobber (reg:CC VAX_PSL_REGNUM))]
1109 "reload_completed"
ab835497 1110 "@
20acd226
SB		 1111 div<VAXint:isfx>2 %2,%0
1112 div<VAXint:isfx>3 %2,%1,%0")
ab835497 1113
1be9edfa
MR		 1114;; This is left out because it is very slow;
1115;; we are better off programming around the "lack" of this insn.
e552abe2 1116;;(define_insn_and_split "divmoddisi4"
1be9edfa
MR		 1117;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1118;; (div:SI (match_operand:DI 1 "general_operand" "g")
1119;; (match_operand:SI 2 "general_operand" "g")))
1120;; (set (match_operand:SI 3 "nonimmediate_operand" "=g")
1121;; (mod:SI (match_dup 1)
1122;; (match_dup 2)))]
1123;; ""
e552abe2
MR		 1124;; "#"
1125;; "reload_completed"
1126;; [(parallel
1127;; [(set (match_dup 0)
1128;; (div:SI (match_dup 1)
1129;; (match_dup 2)))
1130;; (set (match_dup 3)
1131;; (mod:SI (match_dup 1)
1132;; (match_dup 2)))
1133;; (clobber (reg:CC VAX_PSL_REGNUM))])]
1134;; "")
1135;;
1136;;(define_insn "*divmoddisi4<ccn><ccnz><ccz>"
1137;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1138;; (div:SI (match_operand:DI 1 "general_operand" "g")
1139;; (match_operand:SI 2 "general_operand" "g")))
1140;; (set (match_operand:SI 3 "nonimmediate_operand" "=g")
1141;; (mod:SI (match_dup 1)
1142;; (match_dup 2)))
1143;; (clobber (reg:CC VAX_PSL_REGNUM))]
1144;; "reload_completed"
1be9edfa 1145;; "ediv %2,%1,%0,%3")
ab835497 1146\f
8aeea6e6 1147;; Bit-and on the VAX is done with a clear-bits insn.
20acd226
SB		 1148(define_expand "and<mode>3"
1149 [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
1150 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" ""))
f78ac4f2 1151 (match_operand:VAXint 2 "general_operand" "")))]
ab835497
RK		 1152 ""
1153 "
1154{
59482679
RS		 1155 rtx op1 = operands[1];
1156
1157 /* If there is a constant argument, complement that one. */
c4e75102 1158 if (CONST_INT_P (operands[2]) && ! CONST_INT_P (op1))
59482679
RS		 1159 {
1160 operands[1] = operands[2];
1161 operands[2] = op1;
1162 op1 = operands[1];
1163 }
1164
d97c1295 1165 if (CONST_INT_P (op1))
3a598fbe 1166 operands[1] = GEN_INT (~INTVAL (op1));
ab835497 1167 else
20acd226 1168 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1);
ab835497
RK		 1169}")
1170
e552abe2 1171(define_insn_and_split "*and<mode>3"
20acd226 1172 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
e552abe2
MR		 1173 (and:VAXint (not:VAXint
1174 (match_operand:VAXint 1 "general_operand" "nrmT,nrmT"))
c4e75102 1175 (match_operand:VAXint 2 "general_operand" "0,nrmT")))]
ab835497 1176 ""
e552abe2
MR		 1177 "#"
1178 "reload_completed"
1179 [(parallel
1180 [(set (match_dup 0)
1181 (and:VAXint (not:VAXint
1182 (match_dup 1))
1183 (match_dup 2)))
1184 (clobber (reg:CC VAX_PSL_REGNUM))])]
1185 "")
1186
1187(define_insn "*and<mode>3_2<ccn><ccnz><ccz>"
1188 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1189 (and:VAXint (not:VAXint
1190 (match_operand:VAXint 1 "general_operand" "nrmT,nrmT"))
1191 (match_operand:VAXint 2 "general_operand" "0,nrmT")))
1192 (clobber (reg:CC VAX_PSL_REGNUM))]
1193 "reload_completed"
ab835497 1194 "@
20acd226
SB		 1195 bic<VAXint:isfx>2 %1,%0
1196 bic<VAXint:isfx>3 %1,%2,%0")
ab835497
RK		 1197
1198;; The following used to be needed because constant propagation can
1199;; create them starting from the bic insn patterns above. This is no
1200;; longer a problem. However, having these patterns allows optimization
1201;; opportunities in combine.c.
1202
e552abe2 1203(define_insn_and_split "*and<mode>3_const_int"
20acd226 1204 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
c4e75102 1205 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
f78ac4f2 1206 (match_operand:VAXint 2 "const_int_operand" "n,n")))]
ab835497 1207 ""
e552abe2
MR		 1208 "#"
1209 "reload_completed"
1210 [(parallel
1211 [(set (match_dup 0)
1212 (and:VAXint (match_dup 1)
1213 (match_dup 2)))
1214 (clobber (reg:CC VAX_PSL_REGNUM))])]
1215 "")
1216
1217(define_insn "*and<mode>3_2_const_int<ccn><ccnz><ccz>"
1218 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1219 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
1220 (match_operand:VAXint 2 "const_int_operand" "n,n")))
1221 (clobber (reg:CC VAX_PSL_REGNUM))]
1222 "reload_completed"
ab835497 1223 "@
20acd226
SB		 1224 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0
1225 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0")
ab835497 1226
e552abe2
MR		 1227;; We have no direct AND operation and consequently the RTL sequence
1228;; the "and<mode>3" pattern produces does not match the instruction
1229;; the "*bit<mode>" pattern does for the purpose of the compare
1230;; elimination pass. Try to get rid of the extra operation by hand
1231;; and where the sequence is used to set the condition codes only
1232;; convert MNEG/BIC => BIT.
1233(define_peephole2
1234 [(parallel
1235 [(set (match_operand:VAXint 0 "register_operand")
1236 (not:VAXint (match_operand:VAXint 1 "general_operand")))
1237 (clobber (reg:CC VAX_PSL_REGNUM))])
1238 (parallel
1239 [(set (reg:VAXccnz VAX_PSL_REGNUM)
1240 (compare:VAXccnz
1241 (and:VAXint (not:VAXint (match_dup 0))
1242 (match_operand:VAXint 3 "general_operand"))
1243 (const_int 0)))
1244 (set (match_operand:VAXint 2 "register_operand")
1245 (and:VAXint (not:VAXint (match_dup 0))
1246 (match_dup 3)))])]
1247 "peep2_reg_dead_p (2, operands[0]) && peep2_reg_dead_p (2, operands[2])"
1248 [(set (reg:VAXccnz VAX_PSL_REGNUM)
1249 (compare:VAXccnz
1250 (and:VAXint (match_dup 1)
1251 (match_dup 3))
1252 (const_int 0)))]
1253 "")
ab835497
RK		 1254\f
1255;;- Bit set instructions.
1256
e552abe2 1257(define_insn_and_split "ior<mode>3"
20acd226 1258 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
c4e75102 1259 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
f78ac4f2 1260 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
ab835497 1261 ""
e552abe2
MR		 1262 "#"
1263 "reload_completed"
1264 [(parallel
1265 [(set (match_dup 0)
1266 (ior:VAXint (match_dup 1)
1267 (match_dup 2)))
1268 (clobber (reg:CC VAX_PSL_REGNUM))])]
1269 "")
1270
1271(define_insn "*ior<mode>3<ccn><ccnz><ccz>"
1272 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1273 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1274 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))
1275 (clobber (reg:CC VAX_PSL_REGNUM))]
1276 "reload_completed"
ab835497 1277 "@
20acd226
SB		 1278 bis<VAXint:isfx>2 %2,%0
1279 bis<VAXint:isfx>2 %1,%0
1280 bis<VAXint:isfx>3 %2,%1,%0")
ab835497
RK		 1281
1282;;- xor instructions.
1283
e552abe2 1284(define_insn_and_split "xor<mode>3"
20acd226 1285 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
c4e75102 1286 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
f78ac4f2 1287 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
ab835497 1288 ""
e552abe2
MR		 1289 "#"
1290 "reload_completed"
1291 [(parallel
1292 [(set (match_dup 0)
1293 (xor:VAXint (match_dup 1)
1294 (match_dup 2)))
1295 (clobber (reg:CC VAX_PSL_REGNUM))])]
1296 "")
1297
1298(define_insn "*xor<mode>3<ccn><ccnz><ccz>"
1299 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1300 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1301 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))
1302 (clobber (reg:CC VAX_PSL_REGNUM))]
1303 "reload_completed"
ab835497 1304 "@
20acd226
SB		 1305 xor<VAXint:isfx>2 %2,%0
1306 xor<VAXint:isfx>2 %1,%0
1307 xor<VAXint:isfx>3 %2,%1,%0")
ab835497 1308\f
e552abe2 1309(define_insn_and_split "neg<mode>2"
20acd226
SB		 1310 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
1311 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))]
ab835497 1312 ""
e552abe2
MR		 1313 "#"
1314 "reload_completed"
1315 [(parallel
1316 [(set (match_dup 0)
1317 (neg:VAXfp (match_dup 1)))
1318 (clobber (reg:CC VAX_PSL_REGNUM))])]
1319 "")
1320
1321(define_insn "*neg<mode>2<fccn><fccnz><fccz>"
1322 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
1323 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))
1324 (clobber (reg:CC VAX_PSL_REGNUM))]
1325 "reload_completed"
20acd226 1326 "mneg<VAXfp:fsfx> %1,%0")
ab835497 1327
e552abe2 1328(define_insn_and_split "neg<mode>2"
20acd226 1329 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
c4e75102 1330 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
ab835497 1331 ""
e552abe2
MR		 1332 "#"
1333 "reload_completed"
1334 [(parallel
1335 [(set (match_dup 0)
1336 (neg:VAXint (match_dup 1)))
1337 (clobber (reg:CC VAX_PSL_REGNUM))])]
1338 "")
1339
1340(define_insn "*neg<mode>2<ccn><ccnz><ccz>"
1341 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
1342 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))
1343 (clobber (reg:CC VAX_PSL_REGNUM))]
1344 "reload_completed"
1345 "mneg<VAXint:isfx> %1,%0")
1346
1347(define_insn "*neg<mode>2_cc"
1348 [(set (reg:CC VAX_PSL_REGNUM)
1349 (compare:CC (const_int 0)
1350 (neg:VAXint
1351 (match_operand:VAXint 1 "general_operand" "0,nrmT"))))
1352 (set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1353 (neg:VAXint (match_dup 1)))]
1354 "reload_completed"
20acd226 1355 "mneg<VAXint:isfx> %1,%0")
ab835497 1356
e552abe2 1357(define_insn_and_split "one_cmpl<mode>2"
20acd226 1358 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
c4e75102 1359 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
ab835497 1360 ""
e552abe2
MR		 1361 "#"
1362 "reload_completed"
1363 [(parallel
1364 [(set (match_dup 0)
1365 (not:VAXint (match_dup 1)))
1366 (clobber (reg:CC VAX_PSL_REGNUM))])]
1367 "")
ab835497 1368
e552abe2
MR		 1369(define_insn "*one_cmpl<mode>2<ccn><ccnz><ccz>"
1370 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
1371 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))
1372 (clobber (reg:CC VAX_PSL_REGNUM))]
1373 "reload_completed"
1374 "mcom<VAXint:isfx> %1,%0")
ab835497 1375\f
8aeea6e6 1376;; Arithmetic right shift on the VAX works by negating the shift count,
ab835497 1377;; then emitting a right shift with the shift count negated. This means
821bde61 1378;; that all actual shift counts in the RTL will be positive. This
ab835497
RK		 1379;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
1380;; which isn't valid.
1381(define_expand "ashrsi3"
1382 [(set (match_operand:SI 0 "general_operand" "=g")
1383 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
f78ac4f2 1384 (match_operand:QI 2 "general_operand" "g")))]
ab835497
RK		 1385 ""
1386 "
1387{
c4e75102 1388 if (! CONST_INT_P(operands[2]))
c5c76735 1389 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
ab835497
RK		 1390}")
1391
e552abe2 1392(define_insn_and_split "*ashlnegsi3_const_int"
17ad4377 1393 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
c4e75102 1394 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
ab835497
RK		 1395 (match_operand:QI 2 "const_int_operand" "n")))]
1396 ""
e552abe2
MR		 1397 "#"
1398 "reload_completed"
1399 [(parallel
1400 [(set (match_dup 0)
1401 (ashiftrt:SI (match_dup 1)
1402 (match_dup 2)))
1403 (clobber (reg:CC VAX_PSL_REGNUM))])]
1404 "")
1405
1406(define_insn "*ashlnegsi3_const_int_2<ccn><ccnz><ccz>"
1407 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1408 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1409 (match_operand:QI 2 "const_int_operand" "n")))
1410 (clobber (reg:CC VAX_PSL_REGNUM))]
1411 "reload_completed"
ab835497
RK		 1412 "ashl $%n2,%1,%0")
1413
e552abe2 1414(define_insn_and_split "*ashlnegsi3"
17ad4377 1415 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
c4e75102 1416 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
ab835497
RK		 1417 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1418 ""
e552abe2
MR		 1419 "#"
1420 "reload_completed"
1421 [(parallel
1422 [(set (match_dup 0)
1423 (ashiftrt:SI (match_dup 1)
1424 (neg:QI (match_dup 2))))
1425 (clobber (reg:CC VAX_PSL_REGNUM))])]
1426 "")
1427
1428(define_insn "*ashlnegsi3_2<ccn><ccnz><ccz>"
1429 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1430 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1431 (neg:QI (match_operand:QI 2 "general_operand" "g"))))
1432 (clobber (reg:CC VAX_PSL_REGNUM))]
1433 "reload_completed"
ab835497
RK		 1434 "ashl %2,%1,%0")
1435
e552abe2 1436(define_insn_and_split "ashlsi3"
17ad4377 1437 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
c4e75102 1438 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
ab835497
RK		 1439 (match_operand:QI 2 "general_operand" "g")))]
1440 ""
e552abe2
MR		 1441 "#"
1442 "reload_completed"
1443 [(parallel
1444 [(set (match_dup 0)
1445 (ashift:SI (match_dup 1)
1446 (match_dup 2)))
1447 (clobber (reg:CC VAX_PSL_REGNUM))])]
1448 "")
1449
1450(define_insn "*ashlsi3<ccn><ccnz><ccz>"
1451 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1452 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
1453 (match_operand:QI 2 "general_operand" "g")))
1454 (clobber (reg:CC VAX_PSL_REGNUM))]
1455 "reload_completed"
ab835497
RK		 1456 "*
1457{
1458 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1459 return \"addl2 %0,%0\";
c4e75102 1460 if (REG_P (operands[1]) && CONST_INT_P (operands[2]))
ab835497
RK		 1461 {
1462 int i = INTVAL (operands[2]);
1463 if (i == 1)
1464 return \"addl3 %1,%1,%0\";
c4e75102
MT		 1465 if (i == 2 && !optimize_size)
1466 {
1467 if (push_operand (operands[0], SImode))
1468 return \"pushal 0[%1]\";
1469 return \"moval 0[%1],%0\";
1470 }
1471 if (i == 3 && !optimize_size)
1472 {
1473 if (push_operand (operands[0], SImode))
1474 return \"pushaq 0[%1]\";
1475 return \"movaq 0[%1],%0\";
1476 }
ab835497
RK		 1477 }
1478 return \"ashl %2,%1,%0\";
1479}")
1480
8aeea6e6 1481;; Arithmetic right shift on the VAX works by negating the shift count.
ab835497
RK		 1482(define_expand "ashrdi3"
1483 [(set (match_operand:DI 0 "general_operand" "=g")
1484 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1485 (match_operand:QI 2 "general_operand" "g")))]
1486 ""
1487 "
1488{
c5c76735 1489 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
ab835497
RK		 1490}")
1491
e552abe2 1492(define_insn_and_split "ashldi3"
17ad4377 1493 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
ab835497
RK		 1494 (ashift:DI (match_operand:DI 1 "general_operand" "g")
1495 (match_operand:QI 2 "general_operand" "g")))]
1496 ""
e552abe2
MR		 1497 "#"
1498 "reload_completed"
1499 [(parallel
1500 [(set (match_dup 0)
1501 (ashift:DI (match_dup 1)
1502 (match_dup 2)))
1503 (clobber (reg:CC VAX_PSL_REGNUM))])]
1504 "")
1505
1506(define_insn "*ashldi3<ccn><ccnz><ccz>"
1507 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1508 (ashift:DI (match_operand:DI 1 "general_operand" "g")
1509 (match_operand:QI 2 "general_operand" "g")))
1510 (clobber (reg:CC VAX_PSL_REGNUM))]
1511 "reload_completed"
7691132c 1512 "ashq %2,%D1,%0")
ab835497 1513
e552abe2 1514(define_insn_and_split "*ashlnegdi3"
17ad4377 1515 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
ab835497
RK		 1516 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1517 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1518 ""
e552abe2
MR		 1519 "#"
1520 "reload_completed"
1521 [(parallel
1522 [(set (match_dup 0)
1523 (ashiftrt:DI (match_dup 1)
1524 (neg:QI (match_dup 2))))
1525 (clobber (reg:CC VAX_PSL_REGNUM))])]
1526 "")
1527
1528(define_insn "*ashlnegdi3_2<ccn><ccnz><ccz>"
1529 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1530 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1531 (neg:QI (match_operand:QI 2 "general_operand" "g"))))
1532 (clobber (reg:CC VAX_PSL_REGNUM))]
1533 "reload_completed"
7691132c 1534 "ashq %2,%D1,%0")
ab835497 1535
572e10f4
RK		 1536;; We used to have expand_shift handle logical right shifts by using extzv,
1537;; but this make it very difficult to do lshrdi3. Since the VAX is the
1538;; only machine with this kludge, it's better to just do this with a
1539;; define_expand and remove that case from expand_shift.
1540
1541(define_expand "lshrsi3"
1542 [(set (match_dup 3)
1543 (minus:QI (const_int 32)
1544 (match_dup 4)))
c4e75102 1545 (set (match_operand:SI 0 "nonimmediate_operand" "=g")
8fac469f 1546 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
572e10f4
RK		 1547 (match_dup 3)
1548 (match_operand:SI 2 "register_operand" "g")))]
1549 ""
1550 "
1551{
1552 operands[3] = gen_reg_rtx (QImode);
1553 operands[4] = gen_lowpart (QImode, operands[2]);
1554}")
1555
8aeea6e6 1556;; Rotate right on the VAX works by negating the shift count.
ab835497
RK		 1557(define_expand "rotrsi3"
1558 [(set (match_operand:SI 0 "general_operand" "=g")
1559 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1560 (match_operand:QI 2 "general_operand" "g")))]
1561 ""
1562 "
1563{
c4e75102 1564 if (! CONST_INT_P (operands[2]))
c5c76735 1565 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
ab835497
RK		 1566}")
1567
e552abe2 1568(define_insn_and_split "rotlsi3"
17ad4377 1569 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
c4e75102 1570 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT")
ab835497
RK		 1571 (match_operand:QI 2 "general_operand" "g")))]
1572 ""
e552abe2
MR		 1573 "#"
1574 "reload_completed"
1575 [(parallel
1576 [(set (match_dup 0)
1577 (rotate:SI (match_dup 1)
1578 (match_dup 2)))
1579 (clobber (reg:CC VAX_PSL_REGNUM))])]
1580 "")
1581
1582(define_insn "*rotlsi3<ccn><ccnz><ccz>"
1583 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1584 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT")
1585 (match_operand:QI 2 "general_operand" "g")))
1586 (clobber (reg:CC VAX_PSL_REGNUM))]
1587 "reload_completed"
ab835497
RK		 1588 "rotl %2,%1,%0")
1589
e552abe2 1590(define_insn_and_split "*rotrsi3_const_int"
17ad4377 1591 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
c4e75102 1592 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
ab835497
RK		 1593 (match_operand:QI 2 "const_int_operand" "n")))]
1594 ""
e552abe2
MR		 1595 "#"
1596 "reload_completed"
1597 [(parallel
1598 [(set (match_dup 0)
1599 (rotatert:SI (match_dup 1)
1600 (match_dup 2)))
1601 (clobber (reg:CC VAX_PSL_REGNUM))])]
1602 "")
1603
1604(define_insn "*rotrsi3_const_int_2<ccn><ccnz><ccz>"
1605 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1606 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
1607 (match_operand:QI 2 "const_int_operand" "n")))
1608 (clobber (reg:CC VAX_PSL_REGNUM))]
1609 "reload_completed"
49c8f4a4 1610 "rotl %R2,%1,%0")
ab835497 1611
e552abe2 1612(define_insn_and_split "*rotrnegsi3"
17ad4377 1613 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
c4e75102 1614 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
ab835497
RK		 1615 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1616 ""
e552abe2
MR		 1617 "#"
1618 "reload_completed"
1619 [(parallel
1620 [(set (match_dup 0)
1621 (rotatert:SI (match_dup 1)
1622 (neg:QI (match_dup 2))))
1623 (clobber (reg:CC VAX_PSL_REGNUM))])]
1624 "")
1625
1626(define_insn "*rotrnegsi3_2<ccn><ccnz><ccz>"
1627 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1628 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
1629 (neg:QI (match_operand:QI 2 "general_operand" "g"))))
1630 (clobber (reg:CC VAX_PSL_REGNUM))]
1631 "reload_completed"
ab835497
RK		 1632 "rotl %2,%1,%0")
1633
1be9edfa 1634;; This insn is probably slower than a multiply and an add.
e552abe2 1635;;(define_insn_and_split "*amulsi4"
1be9edfa
MR		 1636;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1637;; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1638;; (match_operand:SI 2 "general_operand" "g"))
1639;; (match_operand:SI 3 "general_operand" "g")))]
1640;; ""
e552abe2
MR		 1641;; "#"
1642;; "reload_completed"
1643;; [(parallel
1644;; [(set (match_dup 0)
1645;; (mult:SI (plus:SI (match_dup 1)
1646;; (match_dup 2))
1647;; (match_dup 3)))
1648;; (clobber (reg:CC VAX_PSL_REGNUM))])]
1649;; "")
1650;;
1651;;(define_insn "*amulsi4_2<ccn><ccnz><ccz>"
1652;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1653;; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1654;; (match_operand:SI 2 "general_operand" "g"))
1655;; (match_operand:SI 3 "general_operand" "g")))
1656;; (clobber (reg:CC VAX_PSL_REGNUM))]
1657;; "reload_completed"
1be9edfa 1658;; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
ab835497
RK		 1659\f
1660;; Special cases of bit-field insns which we should
1661;; recognize in preference to the general case.
8a8de750
MR		 1662;; These handle aligned 8-bit and 16-bit fields
1663;; that can be done with move or convert instructions.
ab835497 1664
e552abe2 1665(define_insn_and_split "*insv_aligned"
4c293413 1666 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
ab835497
RK		 1667 (match_operand:QI 1 "const_int_operand" "n")
1668 (match_operand:SI 2 "const_int_operand" "n"))
1669 (match_operand:SI 3 "general_operand" "g"))]
b3f3bba3 1670 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
ab835497 1671 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
590f5d51 1672 && (!MEM_P (operands[0])
b3f3bba3
MR		 1673 || ((!flag_pic
1674 || vax_acceptable_pic_operand_p (XEXP (operands[0], 0),
1675 true, true))
1676 && !mode_dependent_address_p (XEXP (operands[0], 0),
1677 MEM_ADDR_SPACE (operands[0]))))
8a8de750
MR		 1678 && (!(REG_P (operands[0])
1679 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))))
1680 || INTVAL (operands[2]) == 0)"
e552abe2
MR		 1681 "#"
1682 "&& reload_completed"
1683 [(parallel
1684 [(set (zero_extract:SI (match_dup 0)
1685 (match_dup 1)
1686 (match_dup 2))
1687 (match_dup 3))
1688 (clobber (reg:CC VAX_PSL_REGNUM))])]
1689 "")
1690
1691(define_insn "*insv_aligned_2<ccn><ccnz><ccz>"
1692 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
1693 (match_operand:QI 1 "const_int_operand" "n")
1694 (match_operand:SI 2 "const_int_operand" "n"))
1695 (match_operand:SI 3 "general_operand" "g"))
1696 (clobber (reg:CC VAX_PSL_REGNUM))]
1697 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1698 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1699 && (!MEM_P (operands[0])
1700 || ((!flag_pic
1701 || vax_acceptable_pic_operand_p (XEXP (operands[0], 0),
1702 true, true))
1703 && !mode_dependent_address_p (XEXP (operands[0], 0),
1704 MEM_ADDR_SPACE (operands[0]))))
1705 && (!(REG_P (operands[0])
1706 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))))
1707 || INTVAL (operands[2]) == 0)
1708 && reload_completed"
ab835497
RK		 1709 "*
1710{
8a8de750 1711 if (!REG_P (operands[0]))
ab835497 1712 operands[0]
b72f00af
RK		 1713 = adjust_address (operands[0],
1714 INTVAL (operands[1]) == 8 ? QImode : HImode,
1715 INTVAL (operands[2]) / 8);
8a8de750
MR		 1716 else
1717 gcc_assert (INTVAL (operands[2]) == 0);
ab835497
RK		 1718
1719 if (INTVAL (operands[1]) == 8)
1720 return \"movb %3,%0\";
1721 return \"movw %3,%0\";
1722}")
1723
e552abe2 1724(define_insn_and_split "*extzv_aligned"
17ad4377 1725 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
4c293413 1726 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
ab835497
RK		 1727 (match_operand:QI 2 "const_int_operand" "n")
1728 (match_operand:SI 3 "const_int_operand" "n")))]
1729 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1730 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
590f5d51 1731 && (!MEM_P (operands[1])
b3f3bba3
MR		 1732 || ((!flag_pic
1733 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1734 true, true))
1735 && !mode_dependent_address_p (XEXP (operands[1], 0),
1736 MEM_ADDR_SPACE (operands[1]))))
8a8de750
MR		 1737 && (!(REG_P (operands[1])
1738 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1739 || INTVAL (operands[3]) == 0)"
e552abe2
MR		 1740 "#"
1741 "&& reload_completed"
1742 [(parallel
1743 [(set (match_dup 0)
1744 (zero_extract:SI (match_dup 1)
1745 (match_dup 2)
1746 (match_dup 3)))
1747 (clobber (reg:CC VAX_PSL_REGNUM))])]
1748 "")
1749
1750(define_insn "*extzv_aligned_2<ccn><ccnz><ccz>"
1751 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
1752 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1753 (match_operand:QI 2 "const_int_operand" "n")
1754 (match_operand:SI 3 "const_int_operand" "n")))
1755 (clobber (reg:CC VAX_PSL_REGNUM))]
1756 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1757 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1758 && (!MEM_P (operands[1])
1759 || ((!flag_pic
1760 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1761 true, true))
1762 && !mode_dependent_address_p (XEXP (operands[1], 0),
1763 MEM_ADDR_SPACE (operands[1]))))
1764 && (!(REG_P (operands[1])
1765 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1766 || INTVAL (operands[3]) == 0)
1767 && reload_completed"
ab835497
RK		 1768 "*
1769{
8a8de750 1770 if (!REG_P (operands[1]))
ab835497 1771 operands[1]
b72f00af
RK		 1772 = adjust_address (operands[1],
1773 INTVAL (operands[2]) == 8 ? QImode : HImode,
1774 INTVAL (operands[3]) / 8);
8a8de750
MR		 1775 else
1776 gcc_assert (INTVAL (operands[3]) == 0);
ab835497
RK		 1777
1778 if (INTVAL (operands[2]) == 8)
1779 return \"movzbl %1,%0\";
1780 return \"movzwl %1,%0\";
1781}")
1782
e552abe2 1783(define_insn_and_split "*extv_aligned"
17ad4377 1784 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
4c293413 1785 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
ab835497
RK		 1786 (match_operand:QI 2 "const_int_operand" "n")
1787 (match_operand:SI 3 "const_int_operand" "n")))]
1788 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1789 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
590f5d51 1790 && (!MEM_P (operands[1])
b3f3bba3
MR		 1791 || ((!flag_pic
1792 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1793 true, true))
1794 && !mode_dependent_address_p (XEXP (operands[1], 0),
1795 MEM_ADDR_SPACE (operands[1]))))
8a8de750
MR		 1796 && (!(REG_P (operands[1])
1797 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1798 || INTVAL (operands[3]) == 0)"
e552abe2
MR		 1799 "#"
1800 "&& reload_completed"
1801 [(parallel
1802 [(set (match_dup 0)
1803 (sign_extract:SI (match_dup 1)
1804 (match_dup 2)
1805 (match_dup 3)))
1806 (clobber (reg:CC VAX_PSL_REGNUM))])]
1807 "")
1808
1809(define_insn "*extv_aligned_2<ccn><ccnz><ccz>"
1810 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1811 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1812 (match_operand:QI 2 "const_int_operand" "n")
1813 (match_operand:SI 3 "const_int_operand" "n")))
1814 (clobber (reg:CC VAX_PSL_REGNUM))]
1815 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1816 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1817 && (!MEM_P (operands[1])
1818 || ((!flag_pic
1819 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1820 true, true))
1821 && !mode_dependent_address_p (XEXP (operands[1], 0),
1822 MEM_ADDR_SPACE (operands[1]))))
1823 && (!(REG_P (operands[1])
1824 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1825 || INTVAL (operands[3]) == 0)
1826 && reload_completed"
ab835497
RK		 1827 "*
1828{
8a8de750 1829 if (!REG_P (operands[1]))
ab835497 1830 operands[1]
b72f00af
RK		 1831 = adjust_address (operands[1],
1832 INTVAL (operands[2]) == 8 ? QImode : HImode,
1833 INTVAL (operands[3]) / 8);
8a8de750
MR		 1834 else
1835 gcc_assert (INTVAL (operands[3]) == 0);
ab835497
RK		 1836
1837 if (INTVAL (operands[2]) == 8)
1838 return \"cvtbl %1,%0\";
1839 return \"cvtwl %1,%0\";
1840}")
1841\f
4c293413 1842;; Register and non-offsettable-memory SImode cases of bit-field insns.
ab835497 1843
e552abe2
MR		 1844(define_insn "*cmpv_<mode>"
1845 [(set (reg:VAXcc VAX_PSL_REGNUM)
1846 (compare:VAXcc
d38f8441 1847 (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro")
ab835497 1848 (match_operand:QI 1 "general_operand" "g")
c4e75102
MT		 1849 (match_operand:SI 2 "general_operand" "nrmT"))
1850 (match_operand:SI 3 "general_operand" "nrmT")))]
e552abe2 1851 "reload_completed"
ab835497
RK		 1852 "cmpv %2,%1,%0,%3")
1853
e552abe2
MR		 1854(define_insn "*cmpzv_<mode>"
1855 [(set (reg:VAXcc VAX_PSL_REGNUM)
1856 (compare:VAXcc
d38f8441 1857 (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro")
ab835497 1858 (match_operand:QI 1 "general_operand" "g")
c4e75102
MT		 1859 (match_operand:SI 2 "general_operand" "nrmT"))
1860 (match_operand:SI 3 "general_operand" "nrmT")))]
e552abe2 1861 "reload_completed"
ab835497
RK		 1862 "cmpzv %2,%1,%0,%3")
1863
00a8faa3
RK		 1864;; When the field position and size are constant and the destination
1865;; is a register, extv and extzv are much slower than a rotate followed
ddd5a7c1 1866;; by a bicl or sign extension. Because we might end up choosing ext[z]v
d0d99d5f 1867;; anyway, we can't allow immediate values for the primary source operand.
00a8faa3 1868
e552abe2 1869(define_insn_and_split "*extv_non_const"
17ad4377 1870 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
4c293413 1871 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
ab835497 1872 (match_operand:QI 2 "general_operand" "g")
c4e75102 1873 (match_operand:SI 3 "general_operand" "nrmT")))]
ab835497 1874 ""
e552abe2
MR		 1875 "#"
1876 "reload_completed"
1877 [(parallel
1878 [(set (match_dup 0)
1879 (sign_extract:SI (match_dup 1)
1880 (match_dup 2)
1881 (match_dup 3)))
1882 (clobber (reg:CC VAX_PSL_REGNUM))])]
1883 "")
1884
1885(define_insn "*extv_non_const_2<ccn><ccnz><ccz>"
1886 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1887 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1888 (match_operand:QI 2 "general_operand" "g")
1889 (match_operand:SI 3 "general_operand" "nrmT")))
1890 (clobber (reg:CC VAX_PSL_REGNUM))]
1891 "reload_completed"
00a8faa3
RK		 1892 "*
1893{
c4e75102
MT		 1894 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
1895 || ! REG_P (operands[0])
00a8faa3
RK		 1896 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
1897 return \"extv %3,%2,%1,%0\";
1898 if (INTVAL (operands[2]) == 8)
1899 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1900 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1901}")
ab835497 1902
e552abe2 1903(define_insn_and_split "*extzv_non_const"
17ad4377 1904 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
4c293413 1905 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
ab835497 1906 (match_operand:QI 2 "general_operand" "g")
c4e75102 1907 (match_operand:SI 3 "general_operand" "nrmT")))]
ab835497 1908 ""
e552abe2
MR		 1909 "#"
1910 "reload_completed"
1911 [(parallel
1912 [(set (match_dup 0)
1913 (zero_extract:SI (match_dup 1)
1914 (match_dup 2)
1915 (match_dup 3)))
1916 (clobber (reg:CC VAX_PSL_REGNUM))])]
1917 "")
1918
1919(define_insn "*extzv_non_const_2<ccn><ccnz><ccz>"
1920 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1921 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1922 (match_operand:QI 2 "general_operand" "g")
1923 (match_operand:SI 3 "general_operand" "nrmT")))
1924 (clobber (reg:CC VAX_PSL_REGNUM))]
1925 "reload_completed"
00a8faa3
RK		 1926 "*
1927{
c4e75102
MT		 1928 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
1929 || ! REG_P (operands[0]))
00a8faa3
RK		 1930 return \"extzv %3,%2,%1,%0\";
1931 if (INTVAL (operands[2]) == 8)
1932 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1933 if (INTVAL (operands[2]) == 16)
1934 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1935 if (INTVAL (operands[3]) & 31)
1936 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1937 if (rtx_equal_p (operands[0], operands[1]))
1938 return \"bicl2 %M2,%0\";
1939 return \"bicl3 %M2,%1,%0\";
1940}")
ab835497
RK		 1941
1942;; Non-register cases.
1943;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1944;; don't match these (and therefore match the cases above instead).
1945
e552abe2
MR		 1946(define_insn "*cmpv_2_<mode>"
1947 [(set (reg:VAXcc VAX_PSL_REGNUM)
1948 (compare:VAXcc
83199882 1949 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
ab835497 1950 (match_operand:QI 1 "general_operand" "g")
c4e75102
MT		 1951 (match_operand:SI 2 "general_operand" "nrmT"))
1952 (match_operand:SI 3 "general_operand" "nrmT")))]
e552abe2 1953 "reload_completed"
ab835497
RK		 1954 "cmpv %2,%1,%0,%3")
1955
e552abe2
MR		 1956(define_insn "*cmpzv_2_<mode>"
1957 [(set (reg:VAXcc VAX_PSL_REGNUM)
1958 (compare:VAXcc
d38f8441 1959 (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
ab835497 1960 (match_operand:QI 1 "general_operand" "g")
c4e75102
MT		 1961 (match_operand:SI 2 "general_operand" "nrmT"))
1962 (match_operand:SI 3 "general_operand" "nrmT")))]
e552abe2 1963 "reload_completed"
ab835497
RK		 1964 "cmpzv %2,%1,%0,%3")
1965
0a9ea215
MR		 1966(define_expand "extv"
1967 [(set (match_operand:SI 0 "general_operand" "")
1968 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
1969 (match_operand:QI 2 "general_operand" "")
1970 (match_operand:SI 3 "general_operand" "")))]
1971 ""
1972 "")
1973
e552abe2 1974(define_insn_and_split "*extv"
17ad4377 1975 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
83199882 1976 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
ab835497 1977 (match_operand:QI 2 "general_operand" "g")
c4e75102 1978 (match_operand:SI 3 "general_operand" "nrmT")))]
ab835497 1979 ""
e552abe2
MR		 1980 "#"
1981 "reload_completed"
1982 [(parallel
1983 [(set (match_dup 0)
1984 (sign_extract:SI (match_dup 1)
1985 (match_dup 2)
1986 (match_dup 3)))
1987 (clobber (reg:CC VAX_PSL_REGNUM))])]
1988 "")
1989
1990(define_insn "*extv_2<ccn><ccnz><ccz>"
1991 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1992 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
1993 (match_operand:QI 2 "general_operand" "g")
1994 (match_operand:SI 3 "general_operand" "nrmT")))
1995 (clobber (reg:CC VAX_PSL_REGNUM))]
1996 "reload_completed"
00a8faa3
RK		 1997 "*
1998{
c4e75102 1999 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
d97c1295 2000 || !CONST_INT_P (operands[3])
00a8faa3 2001 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
d251be98 2002 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
00a8faa3 2003 || side_effects_p (operands[1])
ff9d4590 2004 || (MEM_P (operands[1])
5bfed9a9
GJL		 2005 && mode_dependent_address_p (XEXP (operands[1], 0),
2006 MEM_ADDR_SPACE (operands[1]))))
00a8faa3
RK		 2007 return \"extv %3,%2,%1,%0\";
2008 if (INTVAL (operands[2]) == 8)
2009 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
2010 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
2011}")
ab835497 2012
83199882
RK		 2013(define_expand "extzv"
2014 [(set (match_operand:SI 0 "general_operand" "")
2015 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
2016 (match_operand:QI 2 "general_operand" "")
2017 (match_operand:SI 3 "general_operand" "")))]
2018 ""
2019 "")
2020
e552abe2 2021(define_insn_and_split "*extzv"
17ad4377 2022 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
83199882 2023 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
ab835497 2024 (match_operand:QI 2 "general_operand" "g")
c4e75102 2025 (match_operand:SI 3 "general_operand" "nrmT")))]
ab835497 2026 ""
e552abe2
MR		 2027 "#"
2028 "reload_completed"
2029 [(parallel
2030 [(set (match_dup 0)
2031 (zero_extract:SI (match_dup 1)
2032 (match_dup 2)
2033 (match_dup 3)))
2034 (clobber (reg:CC VAX_PSL_REGNUM))])]
2035 "")
2036
2037(define_insn "*extzv_2<ccn><ccnz><ccz>"
2038 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2039 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
2040 (match_operand:QI 2 "general_operand" "g")
2041 (match_operand:SI 3 "general_operand" "nrmT")))
2042 (clobber (reg:CC VAX_PSL_REGNUM))]
2043 "reload_completed"
00a8faa3
RK		 2044 "*
2045{
c4e75102 2046 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
d97c1295 2047 || !CONST_INT_P (operands[3])
d251be98 2048 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
00a8faa3 2049 || side_effects_p (operands[1])
ff9d4590 2050 || (MEM_P (operands[1])
5bfed9a9
GJL		 2051 && mode_dependent_address_p (XEXP (operands[1], 0),
2052 MEM_ADDR_SPACE (operands[1]))))
00a8faa3
RK		 2053 return \"extzv %3,%2,%1,%0\";
2054 if (INTVAL (operands[2]) == 8)
2055 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
2056 if (INTVAL (operands[2]) == 16)
2057 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
c4e75102
MT		 2058 if (MEM_P (operands[1])
2059 && GET_CODE (XEXP (operands[1], 0)) == PLUS
2060 && REG_P (XEXP (XEXP (operands[1], 0), 0))
2061 && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1))
2062 && CONST_INT_P (operands[2])
2063 && CONST_INT_P (operands[3]))
2064 {
2065 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2066 HOST_WIDE_INT l = INTVAL (operands[2]);
2067 HOST_WIDE_INT v = INTVAL (operands[3]);
2068 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
2069 {
2070 rtx tmp;
2071 tmp = XEXP (XEXP (operands[1], 0), 0);
2072 if (o & ~3)
2073 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
2074 operands[1] = gen_rtx_MEM (QImode, tmp);
2075 operands[3] = GEN_INT (v + (o & 3) * 8);
2076 }
2077 if (optimize_size)
2078 return \"extzv %3,%2,%1,%0\";
2079 }
00a8faa3
RK		 2080 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
2081}")
ab835497 2082
e552abe2
MR		 2083;; Combine EXTV/CMPL and EXTZV/CMPL sequences where the output of
2084;; extraction is used for the comparison only into CMPV and CMPZV
2085;; respectively.
2086(define_peephole2
2087 [(parallel
2088 [(set (match_operand:SI 0 "register_operand")
2089 (any_extract:SI (match_operand 1 "general_operand")
2090 (match_operand:QI 2 "general_operand")
2091 (match_operand:SI 3 "general_operand")))
2092 (clobber (reg:CC VAX_PSL_REGNUM))])
2093 (set (reg:VAXcc VAX_PSL_REGNUM)
2094 (compare:VAXcc (match_dup 0)
2095 (match_operand:SI 4 "general_operand")))]
2096 "peep2_reg_dead_p (2, operands[0])"
2097 [(set (reg:VAXcc VAX_PSL_REGNUM)
2098 (compare:VAXcc
2099 (any_extract:SI (match_dup 1)
2100 (match_dup 2)
2101 (match_dup 3))
2102 (match_dup 4)))]
2103 "")
2104
83199882
RK		 2105(define_expand "insv"
2106 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
2107 (match_operand:QI 1 "general_operand" "")
2108 (match_operand:SI 2 "general_operand" ""))
2109 (match_operand:SI 3 "general_operand" ""))]
2110 ""
2111 "")
2112
e552abe2 2113;; This one actually doesn't change CC.
4c293413
MR		 2114(define_insn "*insv"
2115 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
ab835497 2116 (match_operand:QI 1 "general_operand" "g")
c4e75102
MT		 2117 (match_operand:SI 2 "general_operand" "nrmT"))
2118 (match_operand:SI 3 "general_operand" "nrmT"))]
ab835497 2119 ""
c4e75102
MT		 2120 "*
2121{
2122 if (MEM_P (operands[0])
2123 && GET_CODE (XEXP (operands[0], 0)) == PLUS
2124 && REG_P (XEXP (XEXP (operands[0], 0), 0))
2125 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
2126 && CONST_INT_P (operands[1])
2127 && CONST_INT_P (operands[2]))
2128 {
2129 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2130 HOST_WIDE_INT v = INTVAL (operands[2]);
2131 HOST_WIDE_INT l = INTVAL (operands[1]);
2132 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
2133 {
2134 rtx tmp;
2135 tmp = XEXP (XEXP (operands[0], 0), 0);
2136 if (o & ~3)
2137 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
2138 operands[0] = gen_rtx_MEM (QImode, tmp);
2139 operands[2] = GEN_INT (v + (o & 3) * 8);
2140 }
2141 }
2142 return \"insv %3,%2,%1,%0\";
2143}")
ab835497 2144
e552abe2 2145;; This one actually doesn't change CC.
4c293413
MR		 2146(define_insn "*insv_2"
2147 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
ab835497 2148 (match_operand:QI 1 "general_operand" "g")
c4e75102
MT		 2149 (match_operand:SI 2 "general_operand" "nrmT"))
2150 (match_operand:SI 3 "general_operand" "nrmT"))]
ab835497
RK		 2151 ""
2152 "insv %3,%2,%1,%0")
2153\f
20acd226 2154;; Unconditional jump
ab835497
RK		 2155(define_insn "jump"
2156 [(set (pc)
2157 (label_ref (match_operand 0 "" "")))]
2158 ""
2159 "jbr %l0")
2160
20acd226 2161;; Conditional jumps
ab835497 2162
f90b7a5a 2163(define_expand "cbranch<mode>4"
e552abe2
MR		 2164 [(set (pc)
2165 (if_then_else
2166 (match_operator 0 "ordered_comparison_operator"
2167 [(match_operand:VAXint 1 "general_operand" "")
2168 (match_operand:VAXint 2 "general_operand" "")])
2169 (label_ref (match_operand 3 "" ""))
2170 (pc)))]
2171 ""
2172 "")
2173
2174(define_insn_and_split "*cbranch<VAXint:mode>4_<VAXcc:mode>"
2175 [(set (pc)
2176 (if_then_else
2177 (match_operator 0 "vax_<cc>_comparison_operator"
2178 [(match_operand:VAXint 1 "general_operand" "nrmT")
2179 (match_operand:VAXint 2 "general_operand" "nrmT")])
2180 (label_ref (match_operand 3 "" ""))
2181 (pc)))]
2182 ""
2183 "#"
2184 "reload_completed"
2185 [(set (reg:VAXcc VAX_PSL_REGNUM)
2186 (compare:VAXcc (match_dup 1) (match_dup 2)))
f90b7a5a 2187 (set (pc)
e552abe2
MR		 2188 (if_then_else
2189 (match_op_dup 0 [(reg:VAXcc VAX_PSL_REGNUM)
2190 (const_int 0)])
2191 (label_ref (match_operand 3 "" ""))
2192 (pc)))]
2193 "")
f90b7a5a
PB		 2194
2195(define_expand "cbranch<mode>4"
e552abe2
MR		 2196 [(set (pc)
2197 (if_then_else
2198 (match_operator 0 "ordered_comparison_operator"
2199 [(match_operand:VAXfp 1 "general_operand" "")
2200 (match_operand:VAXfp 2 "general_operand" "")])
2201 (label_ref (match_operand 3 "" ""))
2202 (pc)))]
2203 ""
2204 "")
2205
2206(define_insn_and_split "*cbranch<VAXfp:mode>4_<VAXccnz:mode>"
2207 [(set (pc)
2208 (if_then_else
2209 (match_operator 0 "vax_<cc>_comparison_operator"
2210 [(match_operand:VAXfp 1 "general_operand" "gF")
2211 (match_operand:VAXfp 2 "general_operand" "gF")])
2212 (label_ref (match_operand 3 "" ""))
2213 (pc)))]
2214 ""
2215 "#"
2216 "reload_completed"
2217 [(set (reg:VAXccnz VAX_PSL_REGNUM)
2218 (compare:VAXccnz (match_dup 1) (match_dup 2)))
f90b7a5a 2219 (set (pc)
e552abe2
MR		 2220 (if_then_else
2221 (match_op_dup 0 [(reg:VAXccnz VAX_PSL_REGNUM)
2222 (const_int 0)])
2223 (label_ref (match_operand 3 "" ""))
2224 (pc)))]
2225 "")
2226
2227(define_insn "*branch_<mode>"
ab835497 2228 [(set (pc)
e552abe2
MR		 2229 (if_then_else (match_operator 0 "vax_<cc>_comparison_operator"
2230 [(reg:VAXcc VAX_PSL_REGNUM)
f90b7a5a
PB		 2231 (const_int 0)])
2232 (label_ref (match_operand 1 "" ""))
ab835497 2233 (pc)))]
e552abe2 2234 "reload_completed"
91ae8fbc 2235 "j%k0 %l1")
ab835497
RK		 2236
2237;; Recognize reversed jumps.
e552abe2 2238(define_insn "*branch_<mode>_reversed"
ab835497 2239 [(set (pc)
e552abe2
MR		 2240 (if_then_else (match_operator 0 "vax_<cc>_comparison_operator"
2241 [(reg:VAXcc VAX_PSL_REGNUM)
ab835497
RK		 2242 (const_int 0)])
2243 (pc)
2244 (label_ref (match_operand 1 "" ""))))]
e552abe2 2245 "reload_completed"
91ae8fbc 2246 "j%K0 %l1") ; %K0 negates condition
ab835497 2247\f
2daed095 2248;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
d38cfc1e
RK		 2249;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
2250;; memory, we use QImode in the insn. So we can't use those instructions
2251;; for mode-dependent addresses.
ab835497
RK		 2252
2253(define_insn ""
2254 [(set (pc)
2255 (if_then_else
83199882 2256 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
ab835497 2257 (const_int 1)
c4e75102 2258 (match_operand:SI 1 "general_operand" "I,nrmT"))
ab835497
RK		 2259 (const_int 0))
2260 (label_ref (match_operand 2 "" ""))
2261 (pc)))]
2262 ""
2263 "@
2264 jlbs %0,%l2
2265 jbs %1,%0,%l2")
2266
2267(define_insn ""
2268 [(set (pc)
2269 (if_then_else
83199882 2270 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
ab835497 2271 (const_int 1)
c4e75102 2272 (match_operand:SI 1 "general_operand" "I,nrmT"))
ab835497
RK		 2273 (const_int 0))
2274 (label_ref (match_operand 2 "" ""))
2275 (pc)))]
2276 ""
2277 "@
2278 jlbc %0,%l2
2279 jbc %1,%0,%l2")
2280
2281(define_insn ""
2282 [(set (pc)
2283 (if_then_else
2284 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
2285 (const_int 1)
c4e75102 2286 (match_operand:SI 1 "general_operand" "I,nrmT"))
ab835497
RK		 2287 (const_int 0))
2288 (label_ref (match_operand 2 "" ""))
2289 (pc)))]
2290 ""
2291 "@
2292 jlbs %0,%l2
2293 jbs %1,%0,%l2")
2294
2295(define_insn ""
2296 [(set (pc)
2297 (if_then_else
2298 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
2299 (const_int 1)
c4e75102 2300 (match_operand:SI 1 "general_operand" "I,nrmT"))
ab835497
RK		 2301 (const_int 0))
2302 (label_ref (match_operand 2 "" ""))
2303 (pc)))]
2304 ""
2305 "@
2306 jlbc %0,%l2
2307 jbc %1,%0,%l2")
2308\f
2309;; Subtract-and-jump and Add-and-jump insns.
2310;; These are not used when output is for the Unix assembler
2311;; because it does not know how to modify them to reach far.
2312
2313;; Normal sob insns.
2314
e552abe2 2315(define_insn_and_split "*jsobgtr"
ab835497
RK		 2316 [(set (pc)
2317 (if_then_else
17ad4377 2318 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
412dc348
RK		 2319 (const_int -1))
2320 (const_int 0))
ab835497
RK		 2321 (label_ref (match_operand 1 "" ""))
2322 (pc)))
2323 (set (match_dup 0)
2324 (plus:SI (match_dup 0)
2325 (const_int -1)))]
2326 "!TARGET_UNIX_ASM"
e552abe2
MR		 2327 "#"
2328 "&& reload_completed"
2329 [(parallel
2330 [(set (pc)
2331 (if_then_else
2332 (gt (plus:SI (match_dup 0)
2333 (const_int -1))
2334 (const_int 0))
2335 (label_ref (match_dup 1))
2336 (pc)))
2337 (set (match_dup 0)
2338 (plus:SI (match_dup 0)
2339 (const_int -1)))
2340 (clobber (reg:CC VAX_PSL_REGNUM))])]
2341 "")
2342
2343(define_insn "*jsobgtr_2"
2344 [(set (pc)
2345 (if_then_else
2346 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2347 (const_int -1))
2348 (const_int 0))
2349 (label_ref (match_operand 1 "" ""))
2350 (pc)))
2351 (set (match_dup 0)
2352 (plus:SI (match_dup 0)
2353 (const_int -1)))
2354 (clobber (reg:CC VAX_PSL_REGNUM))]
2355 "!TARGET_UNIX_ASM && reload_completed"
ab835497
RK		 2356 "jsobgtr %0,%l1")
2357
e552abe2 2358(define_insn_and_split "*jsobgeq"
ab835497
RK		 2359 [(set (pc)
2360 (if_then_else
17ad4377 2361 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
412dc348
RK		 2362 (const_int -1))
2363 (const_int 0))
ab835497
RK		 2364 (label_ref (match_operand 1 "" ""))
2365 (pc)))
2366 (set (match_dup 0)
2367 (plus:SI (match_dup 0)
2368 (const_int -1)))]
2369 "!TARGET_UNIX_ASM"
e552abe2
MR		 2370 "#"
2371 "&& reload_completed"
2372 [(parallel
2373 [(set (pc)
2374 (if_then_else
2375 (ge (plus:SI (match_dup 0)
2376 (const_int -1))
2377 (const_int 0))
2378 (label_ref (match_dup 1))
2379 (pc)))
2380 (set (match_dup 0)
2381 (plus:SI (match_dup 0)
2382 (const_int -1)))
2383 (clobber (reg:CC VAX_PSL_REGNUM))])]
2384 "")
2385
2386(define_insn "*jsobgeq_2"
2387 [(set (pc)
2388 (if_then_else
2389 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2390 (const_int -1))
2391 (const_int 0))
2392 (label_ref (match_operand 1 "" ""))
2393 (pc)))
2394 (set (match_dup 0)
2395 (plus:SI (match_dup 0)
2396 (const_int -1)))
2397 (clobber (reg:CC VAX_PSL_REGNUM))]
2398 "!TARGET_UNIX_ASM && reload_completed"
ab835497
RK		 2399 "jsobgeq %0,%l1")
2400
2401;; Normal aob insns. Define a version for when operands[1] is a constant.
e552abe2 2402(define_insn_and_split "*jaoblss"
ab835497
RK		 2403 [(set (pc)
2404 (if_then_else
17ad4377 2405 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
ab835497 2406 (const_int 1))
c4e75102 2407 (match_operand:SI 1 "general_operand" "nrmT"))
ab835497
RK		 2408 (label_ref (match_operand 2 "" ""))
2409 (pc)))
2410 (set (match_dup 0)
2411 (plus:SI (match_dup 0)
2412 (const_int 1)))]
2413 "!TARGET_UNIX_ASM"
e552abe2
MR		 2414 "#"
2415 "&& reload_completed"
2416 [(parallel
2417 [(set (pc)
2418 (if_then_else
2419 (lt (plus:SI (match_dup 0)
2420 (const_int 1))
2421 (match_dup 1))
2422 (label_ref (match_dup 2))
2423 (pc)))
2424 (set (match_dup 0)
2425 (plus:SI (match_dup 0)
2426 (const_int 1)))
2427 (clobber (reg:CC VAX_PSL_REGNUM))])]
2428 "")
2429
2430(define_insn "*jaoblss_2"
2431 [(set (pc)
2432 (if_then_else
2433 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2434 (const_int 1))
2435 (match_operand:SI 1 "general_operand" "nrmT"))
2436 (label_ref (match_operand 2 "" ""))
2437 (pc)))
2438 (set (match_dup 0)
2439 (plus:SI (match_dup 0)
2440 (const_int 1)))
2441 (clobber (reg:CC VAX_PSL_REGNUM))]
2442 "!TARGET_UNIX_ASM && reload_completed"
ab835497
RK		 2443 "jaoblss %1,%0,%l2")
2444
e552abe2 2445(define_insn_and_split "*jaoblss_const"
ab835497
RK		 2446 [(set (pc)
2447 (if_then_else
17ad4377 2448 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
c4e75102 2449 (match_operand:SI 1 "general_operand" "nrmT"))
ab835497
RK		 2450 (label_ref (match_operand 2 "" ""))
2451 (pc)))
2452 (set (match_dup 0)
2453 (plus:SI (match_dup 0)
2454 (const_int 1)))]
d97c1295 2455 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
e552abe2
MR		 2456 "#"
2457 "&& reload_completed"
2458 [(parallel
2459 [(set (pc)
2460 (if_then_else
2461 (lt (match_dup 0)
2462 (match_dup 1))
2463 (label_ref (match_dup 2))
2464 (pc)))
2465 (set (match_dup 0)
2466 (plus:SI (match_dup 0)
2467 (const_int 1)))
2468 (clobber (reg:CC VAX_PSL_REGNUM))])]
2469 "")
2470
2471(define_insn "*jaoblss_const_2"
2472 [(set (pc)
2473 (if_then_else
2474 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
2475 (match_operand:SI 1 "general_operand" "nrmT"))
2476 (label_ref (match_operand 2 "" ""))
2477 (pc)))
2478 (set (match_dup 0)
2479 (plus:SI (match_dup 0)
2480 (const_int 1)))
2481 (clobber (reg:CC VAX_PSL_REGNUM))]
2482 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1]) && reload_completed"
ab835497
RK		 2483 "jaoblss %P1,%0,%l2")
2484
e552abe2 2485(define_insn_and_split "*jaobleq"
ab835497
RK		 2486 [(set (pc)
2487 (if_then_else
17ad4377 2488 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
ab835497 2489 (const_int 1))
c4e75102 2490 (match_operand:SI 1 "general_operand" "nrmT"))
ab835497
RK		 2491 (label_ref (match_operand 2 "" ""))
2492 (pc)))
2493 (set (match_dup 0)
2494 (plus:SI (match_dup 0)
2495 (const_int 1)))]
2496 "!TARGET_UNIX_ASM"
e552abe2
MR		 2497 "#"
2498 "&& reload_completed"
2499 [(parallel
2500 [(set (pc)
2501 (if_then_else
2502 (le (plus:SI (match_dup 0)
2503 (const_int 1))
2504 (match_dup 1))
2505 (label_ref (match_dup 2))
2506 (pc)))
2507 (set (match_dup 0)
2508 (plus:SI (match_dup 0)
2509 (const_int 1)))
2510 (clobber (reg:CC VAX_PSL_REGNUM))])]
2511 "")
2512
2513(define_insn "*jaobleq_2"
2514 [(set (pc)
2515 (if_then_else
2516 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2517 (const_int 1))
2518 (match_operand:SI 1 "general_operand" "nrmT"))
2519 (label_ref (match_operand 2 "" ""))
2520 (pc)))
2521 (set (match_dup 0)
2522 (plus:SI (match_dup 0)
2523 (const_int 1)))
2524 (clobber (reg:CC VAX_PSL_REGNUM))]
2525 "!TARGET_UNIX_ASM && reload_completed"
ab835497
RK		 2526 "jaobleq %1,%0,%l2")
2527
e552abe2 2528(define_insn_and_split "*jaobleq_const"
ab835497
RK		 2529 [(set (pc)
2530 (if_then_else
17ad4377 2531 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
c4e75102 2532 (match_operand:SI 1 "general_operand" "nrmT"))
ab835497
RK		 2533 (label_ref (match_operand 2 "" ""))
2534 (pc)))
2535 (set (match_dup 0)
2536 (plus:SI (match_dup 0)
2537 (const_int 1)))]
d97c1295 2538 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
e552abe2
MR		 2539 "#"
2540 "&& reload_completed"
2541 [(parallel
2542 [(set (pc)
2543 (if_then_else
2544 (le (match_dup 0)
2545 (match_dup 1))
2546 (label_ref (match_dup 2))
2547 (pc)))
2548 (set (match_dup 0)
2549 (plus:SI (match_dup 0)
2550 (const_int 1)))
2551 (clobber (reg:CC VAX_PSL_REGNUM))])]
2552 "")
2553
2554(define_insn "*jaobleq_const_2"
2555 [(set (pc)
2556 (if_then_else
2557 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
2558 (match_operand:SI 1 "general_operand" "nrmT"))
2559 (label_ref (match_operand 2 "" ""))
2560 (pc)))
2561 (set (match_dup 0)
2562 (plus:SI (match_dup 0)
2563 (const_int 1)))
2564 (clobber (reg:CC VAX_PSL_REGNUM))]
2565 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1]) && reload_completed"
ab835497
RK		 2566 "jaobleq %P1,%0,%l2")
2567
2568;; Something like a sob insn, but compares against -1.
2569;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
2570
e552abe2 2571(define_insn_and_split "*jsobneq_minus_one"
ab835497
RK		 2572 [(set (pc)
2573 (if_then_else
17ad4377 2574 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
ab835497
RK		 2575 (const_int 0))
2576 (label_ref (match_operand 1 "" ""))
2577 (pc)))
2578 (set (match_dup 0)
2579 (plus:SI (match_dup 0)
2580 (const_int -1)))]
2581 ""
e552abe2
MR		 2582 "#"
2583 "reload_completed"
2584 [(parallel
2585 [(set (pc)
2586 (if_then_else
2587 (ne (match_dup 0)
2588 (const_int 0))
2589 (label_ref (match_dup 1))
2590 (pc)))
2591 (set (match_dup 0)
2592 (plus:SI (match_dup 0)
2593 (const_int -1)))
2594 (clobber (reg:CC VAX_PSL_REGNUM))])]
2595 "")
2596
2597(define_insn "*jsobneq_minus_one_2"
2598 [(set (pc)
2599 (if_then_else
2600 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
2601 (const_int 0))
2602 (label_ref (match_operand 1 "" ""))
2603 (pc)))
2604 (set (match_dup 0)
2605 (plus:SI (match_dup 0)
2606 (const_int -1)))
2607 (clobber (reg:CC VAX_PSL_REGNUM))]
2608 "reload_completed"
ab835497
RK		 2609 "decl %0\;jgequ %l1")
2610\f
264ddbaa
RH		 2611(define_expand "call_pop"
2612 [(parallel [(call (match_operand:QI 0 "memory_operand" "")
2613 (match_operand:SI 1 "const_int_operand" ""))
0f8def68
JBG		 2614 (set (reg:SI VAX_SP_REGNUM)
2615 (plus:SI (reg:SI VAX_SP_REGNUM)
264ddbaa
RH		 2616 (match_operand:SI 3 "immediate_operand" "")))])]
2617 ""
264ddbaa 2618{
90285d8d 2619 gcc_assert (INTVAL (operands[3]) <= 255 * 4 && INTVAL (operands[3]) % 4 == 0);
ec20cffb
JT		 2620
2621 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
2622 during EH unwinding. We must include the argument count pushed by
2623 the calls instruction. */
2624 operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
2625})
264ddbaa
RH		 2626
2627(define_insn "*call_pop"
ab835497 2628 [(call (match_operand:QI 0 "memory_operand" "m")
f5963e61 2629 (match_operand:SI 1 "const_int_operand" "n"))
0f8def68
JBG		 2630 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
2631 (match_operand:SI 2 "immediate_operand" "i")))]
ab835497 2632 ""
ec20cffb
JT		 2633{
2634 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
2635 return "calls %1,%0";
2636})
264ddbaa
RH		 2637
2638(define_expand "call_value_pop"
2639 [(parallel [(set (match_operand 0 "" "")
2640 (call (match_operand:QI 1 "memory_operand" "")
2641 (match_operand:SI 2 "const_int_operand" "")))
0f8def68
JBG		 2642 (set (reg:SI VAX_SP_REGNUM)
2643 (plus:SI (reg:SI VAX_SP_REGNUM)
264ddbaa
RH		 2644 (match_operand:SI 4 "immediate_operand" "")))])]
2645 ""
264ddbaa 2646{
90285d8d 2647 gcc_assert (INTVAL (operands[4]) <= 255 * 4 && INTVAL (operands[4]) % 4 == 0);
ec20cffb
JT		 2648
2649 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
2650 during EH unwinding. We must include the argument count pushed by
2651 the calls instruction. */
2652 operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
2653})
ab835497 2654
264ddbaa
RH		 2655(define_insn "*call_value_pop"
2656 [(set (match_operand 0 "" "")
ab835497 2657 (call (match_operand:QI 1 "memory_operand" "m")
f5963e61 2658 (match_operand:SI 2 "const_int_operand" "n")))
0f8def68
JBG		 2659 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
2660 (match_operand:SI 3 "immediate_operand" "i")))]
ab835497 2661 ""
ec20cffb
JT		 2662 "*
2663{
2664 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
2665 return \"calls %2,%1\";
2666}")
2667
2668(define_expand "call"
2669 [(call (match_operand:QI 0 "memory_operand" "")
2670 (match_operand:SI 1 "const_int_operand" ""))]
2671 ""
2672 "
2673{
2674 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
2675 during EH unwinding. We must include the argument count pushed by
2676 the calls instruction. */
2677 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
2678}")
ab835497 2679
ec20cffb
JT		 2680(define_insn "*call"
2681 [(call (match_operand:QI 0 "memory_operand" "m")
f78ac4f2 2682 (match_operand:SI 1 "const_int_operand" ""))]
ab835497 2683 ""
264ddbaa 2684 "calls $0,%0")
ab835497 2685
ec20cffb
JT		 2686(define_expand "call_value"
2687 [(set (match_operand 0 "" "")
2688 (call (match_operand:QI 1 "memory_operand" "")
c4e75102 2689 (match_operand:SI 2 "const_int_operand" "")))]
ec20cffb
JT		 2690 ""
2691 "
2692{
2693 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
2694 during EH unwinding. We must include the argument count pushed by
2695 the calls instruction. */
2696 operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
2697}")
2698
2699(define_insn "*call_value"
264ddbaa 2700 [(set (match_operand 0 "" "")
ab835497 2701 (call (match_operand:QI 1 "memory_operand" "m")
ec20cffb 2702 (match_operand:SI 2 "const_int_operand" "")))]
ab835497 2703 ""
264ddbaa 2704 "calls $0,%1")
ab835497 2705
d0d02377
RS		 2706;; Call subroutine returning any type.
2707
2708(define_expand "untyped_call"
2709 [(parallel [(call (match_operand 0 "" "")
c4e75102
MT		 2710 (const_int 0))
2711 (match_operand 1 "" "")
2712 (match_operand 2 "" "")])]
d0d02377
RS		 2713 ""
2714 "
2715{
2716 int i;
2717
2718 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
2719
2720 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2721 {
2722 rtx set = XVECEXP (operands[2], 0, i);
2723 emit_move_insn (SET_DEST (set), SET_SRC (set));
2724 }
2725
2726 /* The optimizer does not know that the call sets the function value
2727 registers we stored in the result block. We avoid problems by
2728 claiming that all hard registers are used and clobbered at this
2729 point. */
2730 emit_insn (gen_blockage ());
2731
2732 DONE;
2733}")
2734
2735;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2736;; all of memory. This blocks insns from being moved across this point.
2737
2738(define_insn "blockage"
ec20cffb 2739 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
d0d02377
RS		 2740 ""
2741 "")
2742
a3515605
RH		 2743(define_insn "procedure_entry_mask"
2744 [(unspec_volatile [(match_operand 0 "const_int_operand")] VUNSPEC_PEM)]
2745 ""
2746 ".word %x0")
2747
ab835497
RK		 2748(define_insn "return"
2749 [(return)]
2750 ""
2751 "ret")
2752
a3515605
RH		 2753(define_expand "prologue"
2754 [(const_int 0)]
2755 ""
2756{
2757 vax_expand_prologue ();
2758 DONE;
2759})
2760
396ad517
JDA		 2761(define_expand "epilogue"
2762 [(return)]
2763 ""
2764 "
2765{
2766 emit_jump_insn (gen_return ());
2767 DONE;
2768}")
2769
ab835497
RK		 2770(define_insn "nop"
2771 [(const_int 0)]
2772 ""
2773 "nop")
2774
d0b97e0a
RS		 2775;; This had a wider constraint once, and it had trouble.
2776;; If you are tempted to try `g', please don't--it's not worth
2777;; the risk we will reopen the same bug.
ab835497 2778(define_insn "indirect_jump"
5b9b177a 2779 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
d0b97e0a 2780 ""
ab835497
RK		 2781 "jmp (%0)")
2782
7133bb7f 2783;; This is here to accept 5 arguments (as passed by expand_end_case)
05dde071
SB		 2784;; and pass the first 4 along to the casesi1 pattern that really does
2785;; the actual casesi work. We emit a jump here to the default label
2786;; _before_ the casesi so that we can be sure that the casesi never
2787;; drops through.
2788;; This is suboptimal perhaps, but so is much of the rest of this
2789;; machine description. For what it's worth, HPPA uses the same trick.
2790;;
2791;; operand 0 is index
2792;; operand 1 is the minimum bound (a const_int)
2793;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int)
2794;; operand 3 is CODE_LABEL for the table;
2795;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default).
2796;;
2797;; We emit:
2798;; i = index - minimum_bound
2799;; if (i > (maximum_bound - minimum_bound + 1) goto default;
2800;; casesi (i, 0, table);
2801;;
7133bb7f 2802(define_expand "casesi"
05dde071
SB		 2803 [(match_operand:SI 0 "general_operand" "")
2804 (match_operand:SI 1 "general_operand" "")
2805 (match_operand:SI 2 "general_operand" "")
2806 (match_operand 3 "" "")
2807 (match_operand 4 "" "")]
7133bb7f 2808 ""
7ee02381 2809{
f90b7a5a
PB		 2810 rtx test;
2811
05dde071
SB		 2812 /* i = index - minimum_bound;
2813 But only if the lower bound is not already zero. */
2814 if (operands[1] != const0_rtx)
2815 {
2816 rtx index = gen_reg_rtx (SImode);
2817 emit_insn (gen_addsi3 (index,
2818 operands[0],
20d68fa0 2819 gen_int_mode (-INTVAL (operands[1]), SImode)));
05dde071
SB		 2820 operands[0] = index;
2821 }
2822
f90b7a5a
PB		 2823 /* if (i > (maximum_bound - minimum_bound + 1)) goto default; */
2824 test = gen_rtx_fmt_ee (GTU, VOIDmode, operands[0], operands[2]);
2825 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
05dde071
SB		 2826
2827 /* casesi (i, 0, table); */
2828 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
7133bb7f 2829 DONE;
7ee02381 2830})
7133bb7f 2831
05dde071 2832;; This insn is a bit of a lier. It actually falls through if no case
35fd3193 2833;; matches. But, we prevent that from ever happening by emitting a jump
05dde071 2834;; before this, see the define_expand above.
e552abe2 2835(define_insn_and_split "casesi1"
05dde071
SB		 2836 [(match_operand:SI 1 "const_int_operand" "n")
2837 (set (pc)
2838 (plus:SI (sign_extend:SI
e552abe2
MR		 2839 (mem:HI (plus:SI
2840 (mult:SI
2841 (match_operand:SI 0 "general_operand" "nrmT")
2842 (const_int 2))
2843 (pc))))
05dde071 2844 (label_ref:SI (match_operand 2 "" ""))))]
ab835497 2845 ""
e552abe2
MR		 2846 "#"
2847 "reload_completed"
2848 [(parallel
2849 [(match_dup 1)
2850 (set (pc)
2851 (plus:SI (sign_extend:SI
2852 (mem:HI (plus:SI
2853 (mult:SI
2854 (match_dup 0)
2855 (const_int 2))
2856 (pc))))
2857 (label_ref:SI (match_dup 2))))
2858 (clobber (reg:CC VAX_PSL_REGNUM))])]
2859 "")
2860
2861(define_insn "*casesi1"
2862 [(match_operand:SI 1 "const_int_operand" "n")
2863 (set (pc)
2864 (plus:SI (sign_extend:SI
2865 (mem:HI (plus:SI
2866 (mult:SI
2867 (match_operand:SI 0 "general_operand" "nrmT")
2868 (const_int 2))
2869 (pc))))
2870 (label_ref:SI (match_operand 2 "" ""))))
2871 (clobber (reg:CC VAX_PSL_REGNUM))]
2872 "reload_completed"
ab835497
RK		 2873 "casel %0,$0,%1")
2874\f
e552abe2 2875(define_insn_and_split "*pushsym"
c4e75102 2876 [(set (match_operand:SI 0 "push_operand" "=g")
85f5a7d6 2877 (match_operand:SI 1 "pic_symbolic_operand" "A"))]
c4e75102 2878 ""
e552abe2
MR		 2879 "#"
2880 "reload_completed"
2881 [(parallel
2882 [(set (match_dup 0)
2883 (match_dup 1))
2884 (clobber (reg:CC VAX_PSL_REGNUM))])]
2885 "")
2886
2887(define_insn "*pushsym_2<ccn><ccnz><ccz>"
2888 [(set (match_operand:SI 0 "push_operand" "=g")
2889 (match_operand:SI 1 "pic_symbolic_operand" "A"))
2890 (clobber (reg:CC VAX_PSL_REGNUM))]
2891 "reload_completed"
c4e75102
MT		 2892 "pushab %a1")
2893
e552abe2 2894(define_insn_and_split "*movsym"
c4e75102 2895 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
85f5a7d6 2896 (match_operand:SI 1 "pic_symbolic_operand" "A"))]
c4e75102 2897 ""
e552abe2
MR		 2898 "#"
2899 "reload_completed"
2900 [(parallel
2901 [(set (match_dup 0)
2902 (match_dup 1))
2903 (clobber (reg:CC VAX_PSL_REGNUM))])]
2904 "")
2905
2906(define_insn "*movsym_2<ccn><ccnz><ccz>"
2907 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2908 (match_operand:SI 1 "pic_symbolic_operand" "A"))
2909 (clobber (reg:CC VAX_PSL_REGNUM))]
2910 "reload_completed"
c4e75102
MT		 2911 "movab %a1,%0")
2912
e552abe2 2913(define_insn_and_split "*pushsymreg"
c4e75102 2914 [(set (match_operand:SI 0 "push_operand" "=g")
85f5a7d6
MR		 2915 (plus:SI (match_operand:SI 1 "register_operand" "%r")
2916 (match_operand:SI 2 "pic_symbolic_operand" "A")))]
2917 "flag_pic"
e552abe2
MR		 2918 "#"
2919 "&& reload_completed"
2920 [(parallel
2921 [(set (match_dup 0)
2922 (plus:SI (match_dup 1)
2923 (match_dup 2)))
2924 (clobber (reg:CC VAX_PSL_REGNUM))])]
2925 "")
2926
2927(define_insn "*pushsymreg_2<ccn><ccnz><ccz>"
2928 [(set (match_operand:SI 0 "push_operand" "=g")
2929 (plus:SI (match_operand:SI 1 "register_operand" "%r")
2930 (match_operand:SI 2 "pic_symbolic_operand" "A")))
2931 (clobber (reg:CC VAX_PSL_REGNUM))]
2932 "flag_pic && reload_completed"
85f5a7d6 2933 "pushab %a2[%1]")
c4e75102 2934
e552abe2 2935(define_insn_and_split "*movsymreg"
c4e75102 2936 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
85f5a7d6
MR		 2937 (plus:SI (match_operand:SI 1 "register_operand" "%r")
2938 (match_operand:SI 2 "pic_symbolic_operand" "A")))]
2939 "flag_pic"
e552abe2
MR		 2940 "#"
2941 "&& reload_completed"
2942 [(parallel
2943 [(set (match_dup 0)
2944 (plus:SI (match_dup 1)
2945 (match_dup 2)))
2946 (clobber (reg:CC VAX_PSL_REGNUM))])]
2947 "")
2948
2949(define_insn "*movsymreg_2<ccn><ccnz><ccz>"
2950 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2951 (plus:SI (match_operand:SI 1 "register_operand" "%r")
2952 (match_operand:SI 2 "pic_symbolic_operand" "A")))
2953 (clobber (reg:CC VAX_PSL_REGNUM))]
2954 "flag_pic && reload_completed"
85f5a7d6 2955 "movab %a2[%1],%0")
c4e75102 2956\f
821bde61 2957;;- load or push effective address
ab835497
RK		 2958;; These come after the move and add/sub patterns
2959;; because we don't want pushl $1 turned into pushad 1.
2960;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
2961
6da0ede8
RS		 2962;; It does not work to use constraints to distinguish pushes from moves,
2963;; because < matches any autodecrement, not just a push.
2964
e552abe2 2965(define_insn_and_split "pushaddr<mode>"
c4e75102
MT		 2966 [(set (match_operand:SI 0 "push_operand" "=g")
2967 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
ab835497 2968 ""
e552abe2
MR		 2969 "#"
2970 "reload_completed"
2971 [(parallel
2972 [(set (match_dup 0)
2973 (match_dup 1))
2974 (clobber (reg:CC VAX_PSL_REGNUM))])]
2975 "")
2976
2977(define_insn "*pushaddr<mode><ccn><ccnz><ccz>"
2978 [(set (match_operand:SI 0 "push_operand" "=g")
2979 (match_operand:VAXintQHSD 1 "address_operand" "p"))
2980 (clobber (reg:CC VAX_PSL_REGNUM))]
2981 "reload_completed"
c4e75102 2982 "pusha<VAXintQHSD:isfx> %a1")
ab835497 2983
e552abe2 2984(define_insn_and_split "movaddr<mode>"
17ad4377 2985 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
c4e75102 2986 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
ab835497 2987 ""
e552abe2
MR		 2988 "#"
2989 "reload_completed"
2990 [(parallel
2991 [(set (match_dup 0)
2992 (match_dup 1))
2993 (clobber (reg:CC VAX_PSL_REGNUM))])]
2994 "")
2995
2996(define_insn "*movaddr<mode><ccn><ccnz><ccz>"
2997 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2998 (match_operand:VAXintQHSD 1 "address_operand" "p"))
2999 (clobber (reg:CC VAX_PSL_REGNUM))]
3000 "reload_completed"
c4e75102 3001 "mova<VAXintQHSD:isfx> %a1,%0")
ab835497 3002
e552abe2 3003(define_insn_and_split "pushaddr<mode>"
c4e75102
MT		 3004 [(set (match_operand:SI 0 "push_operand" "=g")
3005 (match_operand:VAXfp 1 "address_operand" "p"))]
ab835497 3006 ""
e552abe2
MR		 3007 "#"
3008 "reload_completed"
3009 [(parallel
3010 [(set (match_dup 0)
3011 (match_dup 1))
3012 (clobber (reg:CC VAX_PSL_REGNUM))])]
3013 "")
3014
3015(define_insn "*pushaddr<mode><ccn><ccnz><ccz>"
3016 [(set (match_operand:SI 0 "push_operand" "=g")
3017 (match_operand:VAXfp 1 "address_operand" "p"))
3018 (clobber (reg:CC VAX_PSL_REGNUM))]
3019 "reload_completed"
c4e75102 3020 "pusha<VAXfp:fsfx> %a1")
ab835497 3021
e552abe2 3022(define_insn_and_split "movaddr<mode>"
17ad4377 3023 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
c4e75102 3024 (match_operand:VAXfp 1 "address_operand" "p"))]
ab835497 3025 ""
e552abe2
MR		 3026 "#"
3027 "reload_completed"
3028 [(parallel
3029 [(set (match_dup 0)
3030 (match_dup 1))
3031 (clobber (reg:CC VAX_PSL_REGNUM))])]
3032 "")
3033
3034(define_insn "*movaddr<mode>"
3035 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
3036 (match_operand:VAXfp 1 "address_operand" "p"))
3037 (clobber (reg:CC VAX_PSL_REGNUM))]
3038 "reload_completed"
c4e75102 3039 "mova<VAXfp:fsfx> %a1,%0")
ab835497
RK		 3040\f
3041;; These used to be peepholes, but it is more straightforward to do them
3042;; as single insns. However, we must force the output to be a register
3043;; if it is not an offsettable address so that we know that we can assign
821bde61 3044;; to it twice.
ab835497
RK		 3045
3046;; If we had a good way of evaluating the relative costs, these could be
3047;; machine-independent.
3048
3049;; Optimize extzv ...,z; andl2 ...,z
3050;; or ashl ...,z; andl2 ...,z
3051;; with other operands constant. This is what the combiner converts the
3052;; above sequences to before attempting to recognize the new insn.
3053
e552abe2 3054(define_insn_and_split "*andashlnegsi4"
17ad4377 3055 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
c4e75102 3056 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
ab835497
RK		 3057 (match_operand:QI 2 "const_int_operand" "n"))
3058 (match_operand:SI 3 "const_int_operand" "n")))]
3059 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
e552abe2
MR		 3060 "#"
3061 "&& reload_completed"
3062 [(parallel
3063 [(set (match_dup 0)
3064 (and:SI (ashiftrt:SI (match_dup 1)
3065 (match_dup 2))
3066 (match_dup 3)))
3067 (clobber (reg:CC VAX_PSL_REGNUM))])]
3068 "")
3069
3070(define_insn "*andashlnegsi4_2<ccn><ccnz><ccz>"
3071 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
3072 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
3073 (match_operand:QI 2 "const_int_operand" "n"))
3074 (match_operand:SI 3 "const_int_operand" "n")))
3075 (clobber (reg:CC VAX_PSL_REGNUM))]
3076 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0
3077 && reload_completed"
ab835497
RK		 3078 "*
3079{
3080 unsigned long mask1 = INTVAL (operands[3]);
3081 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
3082
3083 if ((mask1 & mask2) != mask1)
3a598fbe 3084 operands[3] = GEN_INT (mask1 & mask2);
ab835497
RK		 3085
3086 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
3087}")
3088
3089;; left-shift and mask
3090;; The only case where `ashl' is better is if the mask only turns off
3091;; bits that the ashl would anyways, in which case it should have been
3092;; optimized away.
3093
e552abe2 3094(define_insn_and_split "*andashlsi4"
17ad4377 3095 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
c4e75102 3096 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
ab835497
RK		 3097 (match_operand:QI 2 "const_int_operand" "n"))
3098 (match_operand:SI 3 "const_int_operand" "n")))]
3099 ""
e552abe2
MR		 3100 "#"
3101 "reload_completed"
3102 [(parallel
3103 [(set (match_dup 0)
3104 (and:SI (ashift:SI (match_dup 1)
3105 (match_dup 2))
3106 (match_dup 3)))
3107 (clobber (reg:CC VAX_PSL_REGNUM))])]
3108 "")
3109
3110(define_insn "*andashlsi4_2<ccn><ccnz><ccz>"
3111 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
3112 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
3113 (match_operand:QI 2 "const_int_operand" "n"))
3114 (match_operand:SI 3 "const_int_operand" "n")))
3115 (clobber (reg:CC VAX_PSL_REGNUM))]
3116 "reload_completed"
ab835497
RK		 3117 "*
3118{
c5c76735
JL		 3119 operands[3]
3120 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
ab835497
RK		 3121 return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
3122}")
ec20cffb
JT		 3123
3124;; Instruction sequence to sync the VAX instruction stream.
3125(define_insn "sync_istream"
3126 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
3127 ""
3128 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")
c4e75102
MT		 3129
3130(define_expand "nonlocal_goto"
3131 [(use (match_operand 0 "general_operand" ""))
3132 (use (match_operand 1 "general_operand" ""))
3133 (use (match_operand 2 "general_operand" ""))
3134 (use (match_operand 3 "general_operand" ""))]
3135 ""
3136{
3137 rtx lab = operands[1];
3138 rtx stack = operands[2];
3139 rtx fp = operands[3];
3140
3141 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
3142 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
3143
3144 emit_move_insn (hard_frame_pointer_rtx, fp);
9eac0f2a 3145 emit_stack_restore (SAVE_NONLOCAL, stack);
c4e75102
MT		 3146
3147 emit_use (hard_frame_pointer_rtx);
3148 emit_use (stack_pointer_rtx);
3149
3150 /* We'll convert this to direct jump via a peephole optimization. */
3151 emit_indirect_jump (copy_to_reg (lab));
3152 emit_barrier ();
3153 DONE;
3154})
ea84baeb
MR		 3155
3156(include "builtins.md")
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