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7afe21cc | 1 | /* Common subexpression elimination for GNU compiler. |
8d9254fc | 2 | Copyright (C) 1987-2020 Free Software Foundation, Inc. |
7afe21cc | 3 | |
1322177d | 4 | This file is part of GCC. |
7afe21cc | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 9 | version. |
7afe21cc | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
7afe21cc RK |
15 | |
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
7afe21cc | 19 | |
7afe21cc | 20 | #include "config.h" |
670ee920 | 21 | #include "system.h" |
4977bab6 | 22 | #include "coretypes.h" |
c7131fb2 | 23 | #include "backend.h" |
957060b5 | 24 | #include "target.h" |
7afe21cc | 25 | #include "rtl.h" |
957060b5 AM |
26 | #include "tree.h" |
27 | #include "cfghooks.h" | |
c7131fb2 | 28 | #include "df.h" |
4d0cdd0c | 29 | #include "memmodel.h" |
6baf1cc8 | 30 | #include "tm_p.h" |
957060b5 | 31 | #include "insn-config.h" |
7932a3db | 32 | #include "regs.h" |
957060b5 AM |
33 | #include "emit-rtl.h" |
34 | #include "recog.h" | |
60393bbc AM |
35 | #include "cfgrtl.h" |
36 | #include "cfganal.h" | |
37 | #include "cfgcleanup.h" | |
36566b39 | 38 | #include "alias.h" |
50b2596f | 39 | #include "toplev.h" |
2f93eea8 | 40 | #include "rtlhooks-def.h" |
ef330312 | 41 | #include "tree-pass.h" |
6fb5fa3c | 42 | #include "dbgcnt.h" |
e89b312e | 43 | #include "rtl-iter.h" |
311b62ce RS |
44 | #include "regs.h" |
45 | #include "function-abi.h" | |
7afe21cc RK |
46 | |
47 | /* The basic idea of common subexpression elimination is to go | |
48 | through the code, keeping a record of expressions that would | |
49 | have the same value at the current scan point, and replacing | |
50 | expressions encountered with the cheapest equivalent expression. | |
51 | ||
52 | It is too complicated to keep track of the different possibilities | |
e48a7fbe JL |
53 | when control paths merge in this code; so, at each label, we forget all |
54 | that is known and start fresh. This can be described as processing each | |
55 | extended basic block separately. We have a separate pass to perform | |
56 | global CSE. | |
57 | ||
58 | Note CSE can turn a conditional or computed jump into a nop or | |
59 | an unconditional jump. When this occurs we arrange to run the jump | |
60 | optimizer after CSE to delete the unreachable code. | |
7afe21cc RK |
61 | |
62 | We use two data structures to record the equivalent expressions: | |
1bb98cec DM |
63 | a hash table for most expressions, and a vector of "quantity |
64 | numbers" to record equivalent (pseudo) registers. | |
7afe21cc RK |
65 | |
66 | The use of the special data structure for registers is desirable | |
67 | because it is faster. It is possible because registers references | |
68 | contain a fairly small number, the register number, taken from | |
69 | a contiguously allocated series, and two register references are | |
70 | identical if they have the same number. General expressions | |
71 | do not have any such thing, so the only way to retrieve the | |
72 | information recorded on an expression other than a register | |
73 | is to keep it in a hash table. | |
74 | ||
75 | Registers and "quantity numbers": | |
278a83b2 | 76 | |
7afe21cc RK |
77 | At the start of each basic block, all of the (hardware and pseudo) |
78 | registers used in the function are given distinct quantity | |
79 | numbers to indicate their contents. During scan, when the code | |
80 | copies one register into another, we copy the quantity number. | |
81 | When a register is loaded in any other way, we allocate a new | |
82 | quantity number to describe the value generated by this operation. | |
459281be | 83 | `REG_QTY (N)' records what quantity register N is currently thought |
7afe21cc RK |
84 | of as containing. |
85 | ||
08a69267 | 86 | All real quantity numbers are greater than or equal to zero. |
459281be | 87 | If register N has not been assigned a quantity, `REG_QTY (N)' will |
08a69267 | 88 | equal -N - 1, which is always negative. |
7afe21cc | 89 | |
08a69267 RS |
90 | Quantity numbers below zero do not exist and none of the `qty_table' |
91 | entries should be referenced with a negative index. | |
7afe21cc RK |
92 | |
93 | We also maintain a bidirectional chain of registers for each | |
1bb98cec DM |
94 | quantity number. The `qty_table` members `first_reg' and `last_reg', |
95 | and `reg_eqv_table' members `next' and `prev' hold these chains. | |
7afe21cc RK |
96 | |
97 | The first register in a chain is the one whose lifespan is least local. | |
98 | Among equals, it is the one that was seen first. | |
99 | We replace any equivalent register with that one. | |
100 | ||
101 | If two registers have the same quantity number, it must be true that | |
1bb98cec | 102 | REG expressions with qty_table `mode' must be in the hash table for both |
7afe21cc RK |
103 | registers and must be in the same class. |
104 | ||
105 | The converse is not true. Since hard registers may be referenced in | |
106 | any mode, two REG expressions might be equivalent in the hash table | |
107 | but not have the same quantity number if the quantity number of one | |
108 | of the registers is not the same mode as those expressions. | |
278a83b2 | 109 | |
7afe21cc RK |
110 | Constants and quantity numbers |
111 | ||
112 | When a quantity has a known constant value, that value is stored | |
1bb98cec | 113 | in the appropriate qty_table `const_rtx'. This is in addition to |
7afe21cc RK |
114 | putting the constant in the hash table as is usual for non-regs. |
115 | ||
d45cf215 | 116 | Whether a reg or a constant is preferred is determined by the configuration |
7afe21cc RK |
117 | macro CONST_COSTS and will often depend on the constant value. In any |
118 | event, expressions containing constants can be simplified, by fold_rtx. | |
119 | ||
120 | When a quantity has a known nearly constant value (such as an address | |
1bb98cec DM |
121 | of a stack slot), that value is stored in the appropriate qty_table |
122 | `const_rtx'. | |
7afe21cc RK |
123 | |
124 | Integer constants don't have a machine mode. However, cse | |
125 | determines the intended machine mode from the destination | |
126 | of the instruction that moves the constant. The machine mode | |
127 | is recorded in the hash table along with the actual RTL | |
128 | constant expression so that different modes are kept separate. | |
129 | ||
130 | Other expressions: | |
131 | ||
132 | To record known equivalences among expressions in general | |
133 | we use a hash table called `table'. It has a fixed number of buckets | |
134 | that contain chains of `struct table_elt' elements for expressions. | |
135 | These chains connect the elements whose expressions have the same | |
136 | hash codes. | |
137 | ||
138 | Other chains through the same elements connect the elements which | |
139 | currently have equivalent values. | |
140 | ||
141 | Register references in an expression are canonicalized before hashing | |
1bb98cec | 142 | the expression. This is done using `reg_qty' and qty_table `first_reg'. |
7afe21cc RK |
143 | The hash code of a register reference is computed using the quantity |
144 | number, not the register number. | |
145 | ||
146 | When the value of an expression changes, it is necessary to remove from the | |
147 | hash table not just that expression but all expressions whose values | |
148 | could be different as a result. | |
149 | ||
150 | 1. If the value changing is in memory, except in special cases | |
151 | ANYTHING referring to memory could be changed. That is because | |
152 | nobody knows where a pointer does not point. | |
153 | The function `invalidate_memory' removes what is necessary. | |
154 | ||
155 | The special cases are when the address is constant or is | |
156 | a constant plus a fixed register such as the frame pointer | |
157 | or a static chain pointer. When such addresses are stored in, | |
158 | we can tell exactly which other such addresses must be invalidated | |
159 | due to overlap. `invalidate' does this. | |
160 | All expressions that refer to non-constant | |
161 | memory addresses are also invalidated. `invalidate_memory' does this. | |
162 | ||
163 | 2. If the value changing is a register, all expressions | |
164 | containing references to that register, and only those, | |
165 | must be removed. | |
166 | ||
167 | Because searching the entire hash table for expressions that contain | |
168 | a register is very slow, we try to figure out when it isn't necessary. | |
169 | Precisely, this is necessary only when expressions have been | |
170 | entered in the hash table using this register, and then the value has | |
171 | changed, and then another expression wants to be added to refer to | |
172 | the register's new value. This sequence of circumstances is rare | |
173 | within any one basic block. | |
174 | ||
459281be KH |
175 | `REG_TICK' and `REG_IN_TABLE', accessors for members of |
176 | cse_reg_info, are used to detect this case. REG_TICK (i) is | |
177 | incremented whenever a value is stored in register i. | |
178 | REG_IN_TABLE (i) holds -1 if no references to register i have been | |
179 | entered in the table; otherwise, it contains the value REG_TICK (i) | |
180 | had when the references were entered. If we want to enter a | |
181 | reference and REG_IN_TABLE (i) != REG_TICK (i), we must scan and | |
182 | remove old references. Until we want to enter a new entry, the | |
183 | mere fact that the two vectors don't match makes the entries be | |
184 | ignored if anyone tries to match them. | |
7afe21cc RK |
185 | |
186 | Registers themselves are entered in the hash table as well as in | |
459281be KH |
187 | the equivalent-register chains. However, `REG_TICK' and |
188 | `REG_IN_TABLE' do not apply to expressions which are simple | |
7afe21cc RK |
189 | register references. These expressions are removed from the table |
190 | immediately when they become invalid, and this can be done even if | |
191 | we do not immediately search for all the expressions that refer to | |
192 | the register. | |
193 | ||
194 | A CLOBBER rtx in an instruction invalidates its operand for further | |
195 | reuse. A CLOBBER or SET rtx whose operand is a MEM:BLK | |
196 | invalidates everything that resides in memory. | |
197 | ||
198 | Related expressions: | |
199 | ||
200 | Constant expressions that differ only by an additive integer | |
201 | are called related. When a constant expression is put in | |
202 | the table, the related expression with no constant term | |
203 | is also entered. These are made to point at each other | |
204 | so that it is possible to find out if there exists any | |
205 | register equivalent to an expression related to a given expression. */ | |
278a83b2 | 206 | |
1bb98cec DM |
207 | /* Length of qty_table vector. We know in advance we will not need |
208 | a quantity number this big. */ | |
7afe21cc RK |
209 | |
210 | static int max_qty; | |
211 | ||
212 | /* Next quantity number to be allocated. | |
213 | This is 1 + the largest number needed so far. */ | |
214 | ||
215 | static int next_qty; | |
216 | ||
1bb98cec | 217 | /* Per-qty information tracking. |
7afe21cc | 218 | |
1bb98cec DM |
219 | `first_reg' and `last_reg' track the head and tail of the |
220 | chain of registers which currently contain this quantity. | |
7afe21cc | 221 | |
1bb98cec | 222 | `mode' contains the machine mode of this quantity. |
7afe21cc | 223 | |
1bb98cec DM |
224 | `const_rtx' holds the rtx of the constant value of this |
225 | quantity, if known. A summations of the frame/arg pointer | |
226 | and a constant can also be entered here. When this holds | |
227 | a known value, `const_insn' is the insn which stored the | |
228 | constant value. | |
7afe21cc | 229 | |
1bb98cec DM |
230 | `comparison_{code,const,qty}' are used to track when a |
231 | comparison between a quantity and some constant or register has | |
232 | been passed. In such a case, we know the results of the comparison | |
233 | in case we see it again. These members record a comparison that | |
234 | is known to be true. `comparison_code' holds the rtx code of such | |
235 | a comparison, else it is set to UNKNOWN and the other two | |
236 | comparison members are undefined. `comparison_const' holds | |
237 | the constant being compared against, or zero if the comparison | |
238 | is not against a constant. `comparison_qty' holds the quantity | |
239 | being compared against when the result is known. If the comparison | |
240 | is not with a register, `comparison_qty' is -1. */ | |
7afe21cc | 241 | |
1bb98cec DM |
242 | struct qty_table_elem |
243 | { | |
244 | rtx const_rtx; | |
20468884 | 245 | rtx_insn *const_insn; |
1bb98cec DM |
246 | rtx comparison_const; |
247 | int comparison_qty; | |
770ae6cc | 248 | unsigned int first_reg, last_reg; |
496324d0 DN |
249 | /* The sizes of these fields should match the sizes of the |
250 | code and mode fields of struct rtx_def (see rtl.h). */ | |
251 | ENUM_BITFIELD(rtx_code) comparison_code : 16; | |
252 | ENUM_BITFIELD(machine_mode) mode : 8; | |
1bb98cec | 253 | }; |
7afe21cc | 254 | |
1bb98cec DM |
255 | /* The table of all qtys, indexed by qty number. */ |
256 | static struct qty_table_elem *qty_table; | |
7afe21cc | 257 | |
7afe21cc RK |
258 | /* For machines that have a CC0, we do not record its value in the hash |
259 | table since its use is guaranteed to be the insn immediately following | |
260 | its definition and any other insn is presumed to invalidate it. | |
261 | ||
96fb470d SB |
262 | Instead, we store below the current and last value assigned to CC0. |
263 | If it should happen to be a constant, it is stored in preference | |
264 | to the actual assigned value. In case it is a constant, we store | |
265 | the mode in which the constant should be interpreted. */ | |
7afe21cc | 266 | |
96fb470d | 267 | static rtx this_insn_cc0, prev_insn_cc0; |
ef4bddc2 | 268 | static machine_mode this_insn_cc0_mode, prev_insn_cc0_mode; |
7afe21cc RK |
269 | |
270 | /* Insn being scanned. */ | |
271 | ||
20468884 | 272 | static rtx_insn *this_insn; |
f40751dd | 273 | static bool optimize_this_for_speed_p; |
7afe21cc | 274 | |
71d306d1 DE |
275 | /* Index by register number, gives the number of the next (or |
276 | previous) register in the chain of registers sharing the same | |
7afe21cc RK |
277 | value. |
278 | ||
279 | Or -1 if this register is at the end of the chain. | |
280 | ||
459281be | 281 | If REG_QTY (N) == -N - 1, reg_eqv_table[N].next is undefined. */ |
1bb98cec DM |
282 | |
283 | /* Per-register equivalence chain. */ | |
284 | struct reg_eqv_elem | |
285 | { | |
286 | int next, prev; | |
287 | }; | |
7afe21cc | 288 | |
1bb98cec DM |
289 | /* The table of all register equivalence chains. */ |
290 | static struct reg_eqv_elem *reg_eqv_table; | |
7afe21cc | 291 | |
14a774a9 RK |
292 | struct cse_reg_info |
293 | { | |
bc5e3b54 KH |
294 | /* The timestamp at which this register is initialized. */ |
295 | unsigned int timestamp; | |
9b1549b8 DM |
296 | |
297 | /* The quantity number of the register's current contents. */ | |
298 | int reg_qty; | |
299 | ||
300 | /* The number of times the register has been altered in the current | |
301 | basic block. */ | |
302 | int reg_tick; | |
303 | ||
30f72379 MM |
304 | /* The REG_TICK value at which rtx's containing this register are |
305 | valid in the hash table. If this does not equal the current | |
306 | reg_tick value, such expressions existing in the hash table are | |
307 | invalid. */ | |
308 | int reg_in_table; | |
46081bb3 SH |
309 | |
310 | /* The SUBREG that was set when REG_TICK was last incremented. Set | |
311 | to -1 if the last store was to the whole register, not a subreg. */ | |
5dd78e9a | 312 | unsigned int subreg_ticked; |
30f72379 | 313 | }; |
7afe21cc | 314 | |
bc5e3b54 | 315 | /* A table of cse_reg_info indexed by register numbers. */ |
f00822b2 | 316 | static struct cse_reg_info *cse_reg_info_table; |
c1edba58 | 317 | |
bc5e3b54 KH |
318 | /* The size of the above table. */ |
319 | static unsigned int cse_reg_info_table_size; | |
9b1549b8 | 320 | |
bc5e3b54 KH |
321 | /* The index of the first entry that has not been initialized. */ |
322 | static unsigned int cse_reg_info_table_first_uninitialized; | |
7afe21cc | 323 | |
bc5e3b54 | 324 | /* The timestamp at the beginning of the current run of |
932ad4d9 SB |
325 | cse_extended_basic_block. We increment this variable at the beginning of |
326 | the current run of cse_extended_basic_block. The timestamp field of a | |
bc5e3b54 KH |
327 | cse_reg_info entry matches the value of this variable if and only |
328 | if the entry has been initialized during the current run of | |
932ad4d9 | 329 | cse_extended_basic_block. */ |
bc5e3b54 | 330 | static unsigned int cse_reg_info_timestamp; |
7afe21cc | 331 | |
278a83b2 | 332 | /* A HARD_REG_SET containing all the hard registers for which there is |
7afe21cc RK |
333 | currently a REG expression in the hash table. Note the difference |
334 | from the above variables, which indicate if the REG is mentioned in some | |
335 | expression in the table. */ | |
336 | ||
337 | static HARD_REG_SET hard_regs_in_table; | |
338 | ||
2aac3a01 EB |
339 | /* True if CSE has altered the CFG. */ |
340 | static bool cse_cfg_altered; | |
7afe21cc | 341 | |
2aac3a01 EB |
342 | /* True if CSE has altered conditional jump insns in such a way |
343 | that jump optimization should be redone. */ | |
344 | static bool cse_jumps_altered; | |
7afe21cc | 345 | |
2aac3a01 EB |
346 | /* True if we put a LABEL_REF into the hash table for an INSN |
347 | without a REG_LABEL_OPERAND, we have to rerun jump after CSE | |
348 | to put in the note. */ | |
349 | static bool recorded_label_ref; | |
a5dfb4ee | 350 | |
7afe21cc RK |
351 | /* canon_hash stores 1 in do_not_record |
352 | if it notices a reference to CC0, PC, or some other volatile | |
353 | subexpression. */ | |
354 | ||
355 | static int do_not_record; | |
356 | ||
357 | /* canon_hash stores 1 in hash_arg_in_memory | |
358 | if it notices a reference to memory within the expression being hashed. */ | |
359 | ||
360 | static int hash_arg_in_memory; | |
361 | ||
7afe21cc RK |
362 | /* The hash table contains buckets which are chains of `struct table_elt's, |
363 | each recording one expression's information. | |
364 | That expression is in the `exp' field. | |
365 | ||
db048faf MM |
366 | The canon_exp field contains a canonical (from the point of view of |
367 | alias analysis) version of the `exp' field. | |
368 | ||
7afe21cc RK |
369 | Those elements with the same hash code are chained in both directions |
370 | through the `next_same_hash' and `prev_same_hash' fields. | |
371 | ||
372 | Each set of expressions with equivalent values | |
373 | are on a two-way chain through the `next_same_value' | |
374 | and `prev_same_value' fields, and all point with | |
375 | the `first_same_value' field at the first element in | |
376 | that chain. The chain is in order of increasing cost. | |
377 | Each element's cost value is in its `cost' field. | |
378 | ||
379 | The `in_memory' field is nonzero for elements that | |
380 | involve any reference to memory. These elements are removed | |
381 | whenever a write is done to an unidentified location in memory. | |
382 | To be safe, we assume that a memory address is unidentified unless | |
383 | the address is either a symbol constant or a constant plus | |
384 | the frame pointer or argument pointer. | |
385 | ||
7afe21cc RK |
386 | The `related_value' field is used to connect related expressions |
387 | (that differ by adding an integer). | |
388 | The related expressions are chained in a circular fashion. | |
389 | `related_value' is zero for expressions for which this | |
390 | chain is not useful. | |
391 | ||
392 | The `cost' field stores the cost of this element's expression. | |
630c79be BS |
393 | The `regcost' field stores the value returned by approx_reg_cost for |
394 | this element's expression. | |
7afe21cc RK |
395 | |
396 | The `is_const' flag is set if the element is a constant (including | |
397 | a fixed address). | |
398 | ||
399 | The `flag' field is used as a temporary during some search routines. | |
400 | ||
401 | The `mode' field is usually the same as GET_MODE (`exp'), but | |
402 | if `exp' is a CONST_INT and has no machine mode then the `mode' | |
403 | field is the mode it was being used as. Each constant is | |
404 | recorded separately for each mode it is used with. */ | |
405 | ||
7afe21cc RK |
406 | struct table_elt |
407 | { | |
408 | rtx exp; | |
db048faf | 409 | rtx canon_exp; |
7afe21cc RK |
410 | struct table_elt *next_same_hash; |
411 | struct table_elt *prev_same_hash; | |
412 | struct table_elt *next_same_value; | |
413 | struct table_elt *prev_same_value; | |
414 | struct table_elt *first_same_value; | |
415 | struct table_elt *related_value; | |
416 | int cost; | |
630c79be | 417 | int regcost; |
496324d0 DN |
418 | /* The size of this field should match the size |
419 | of the mode field of struct rtx_def (see rtl.h). */ | |
420 | ENUM_BITFIELD(machine_mode) mode : 8; | |
7afe21cc | 421 | char in_memory; |
7afe21cc RK |
422 | char is_const; |
423 | char flag; | |
424 | }; | |
425 | ||
7afe21cc RK |
426 | /* We don't want a lot of buckets, because we rarely have very many |
427 | things stored in the hash table, and a lot of buckets slows | |
428 | down a lot of loops that happen frequently. */ | |
9b1549b8 DM |
429 | #define HASH_SHIFT 5 |
430 | #define HASH_SIZE (1 << HASH_SHIFT) | |
431 | #define HASH_MASK (HASH_SIZE - 1) | |
7afe21cc RK |
432 | |
433 | /* Compute hash code of X in mode M. Special-case case where X is a pseudo | |
434 | register (hard registers may require `do_not_record' to be set). */ | |
435 | ||
436 | #define HASH(X, M) \ | |
f8cfc6aa | 437 | ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER \ |
9b1549b8 DM |
438 | ? (((unsigned) REG << 7) + (unsigned) REG_QTY (REGNO (X))) \ |
439 | : canon_hash (X, M)) & HASH_MASK) | |
7afe21cc | 440 | |
0516f6fe SB |
441 | /* Like HASH, but without side-effects. */ |
442 | #define SAFE_HASH(X, M) \ | |
443 | ((REG_P (X) && REGNO (X) >= FIRST_PSEUDO_REGISTER \ | |
444 | ? (((unsigned) REG << 7) + (unsigned) REG_QTY (REGNO (X))) \ | |
445 | : safe_hash (X, M)) & HASH_MASK) | |
446 | ||
630c79be BS |
447 | /* Determine whether register number N is considered a fixed register for the |
448 | purpose of approximating register costs. | |
7afe21cc RK |
449 | It is desirable to replace other regs with fixed regs, to reduce need for |
450 | non-fixed hard regs. | |
553687c9 | 451 | A reg wins if it is either the frame pointer or designated as fixed. */ |
7afe21cc | 452 | #define FIXED_REGNO_P(N) \ |
8bc169f2 | 453 | ((N) == FRAME_POINTER_REGNUM || (N) == HARD_FRAME_POINTER_REGNUM \ |
6ab832bc | 454 | || fixed_regs[N] || global_regs[N]) |
7afe21cc RK |
455 | |
456 | /* Compute cost of X, as stored in the `cost' field of a table_elt. Fixed | |
ac07e066 RK |
457 | hard registers and pointers into the frame are the cheapest with a cost |
458 | of 0. Next come pseudos with a cost of one and other hard registers with | |
459 | a cost of 2. Aside from these special cases, call `rtx_cost'. */ | |
460 | ||
d67fb775 | 461 | #define CHEAP_REGNO(N) \ |
c3284718 | 462 | (REGNO_PTR_FRAME_P (N) \ |
d67fb775 | 463 | || (HARD_REGISTER_NUM_P (N) \ |
e7bb59fa | 464 | && FIXED_REGNO_P (N) && REGNO_REG_CLASS (N) != NO_REGS)) |
7afe21cc | 465 | |
e548c9df AM |
466 | #define COST(X, MODE) \ |
467 | (REG_P (X) ? 0 : notreg_cost (X, MODE, SET, 1)) | |
468 | #define COST_IN(X, MODE, OUTER, OPNO) \ | |
469 | (REG_P (X) ? 0 : notreg_cost (X, MODE, OUTER, OPNO)) | |
7afe21cc | 470 | |
30f72379 MM |
471 | /* Get the number of times this register has been updated in this |
472 | basic block. */ | |
473 | ||
bc5e3b54 | 474 | #define REG_TICK(N) (get_cse_reg_info (N)->reg_tick) |
30f72379 MM |
475 | |
476 | /* Get the point at which REG was recorded in the table. */ | |
477 | ||
bc5e3b54 | 478 | #define REG_IN_TABLE(N) (get_cse_reg_info (N)->reg_in_table) |
30f72379 | 479 | |
46081bb3 SH |
480 | /* Get the SUBREG set at the last increment to REG_TICK (-1 if not a |
481 | SUBREG). */ | |
482 | ||
bc5e3b54 | 483 | #define SUBREG_TICKED(N) (get_cse_reg_info (N)->subreg_ticked) |
46081bb3 | 484 | |
30f72379 MM |
485 | /* Get the quantity number for REG. */ |
486 | ||
bc5e3b54 | 487 | #define REG_QTY(N) (get_cse_reg_info (N)->reg_qty) |
30f72379 | 488 | |
7afe21cc | 489 | /* Determine if the quantity number for register X represents a valid index |
1bb98cec | 490 | into the qty_table. */ |
7afe21cc | 491 | |
08a69267 | 492 | #define REGNO_QTY_VALID_P(N) (REG_QTY (N) >= 0) |
7afe21cc | 493 | |
2c5bfdf7 AN |
494 | /* Compare table_elt X and Y and return true iff X is cheaper than Y. */ |
495 | ||
496 | #define CHEAPER(X, Y) \ | |
497 | (preferable ((X)->cost, (X)->regcost, (Y)->cost, (Y)->regcost) < 0) | |
498 | ||
9b1549b8 | 499 | static struct table_elt *table[HASH_SIZE]; |
7afe21cc RK |
500 | |
501 | /* Chain of `struct table_elt's made so far for this function | |
502 | but currently removed from the table. */ | |
503 | ||
504 | static struct table_elt *free_element_chain; | |
505 | ||
7afe21cc RK |
506 | /* Set to the cost of a constant pool reference if one was found for a |
507 | symbolic constant. If this was found, it means we should try to | |
508 | convert constants into constant pool entries if they don't fit in | |
509 | the insn. */ | |
510 | ||
511 | static int constant_pool_entries_cost; | |
dd0ba281 | 512 | static int constant_pool_entries_regcost; |
7afe21cc | 513 | |
24b97832 ILT |
514 | /* Trace a patch through the CFG. */ |
515 | ||
516 | struct branch_path | |
517 | { | |
518 | /* The basic block for this path entry. */ | |
519 | basic_block bb; | |
520 | }; | |
521 | ||
932ad4d9 SB |
522 | /* This data describes a block that will be processed by |
523 | cse_extended_basic_block. */ | |
6cd4575e | 524 | |
14a774a9 RK |
525 | struct cse_basic_block_data |
526 | { | |
6cd4575e RK |
527 | /* Total number of SETs in block. */ |
528 | int nsets; | |
6cd4575e RK |
529 | /* Size of current branch path, if any. */ |
530 | int path_size; | |
932ad4d9 | 531 | /* Current path, indicating which basic_blocks will be processed. */ |
24b97832 | 532 | struct branch_path *path; |
6cd4575e RK |
533 | }; |
534 | ||
6fb5fa3c DB |
535 | |
536 | /* Pointers to the live in/live out bitmaps for the boundaries of the | |
537 | current EBB. */ | |
538 | static bitmap cse_ebb_live_in, cse_ebb_live_out; | |
539 | ||
932ad4d9 SB |
540 | /* A simple bitmap to track which basic blocks have been visited |
541 | already as part of an already processed extended basic block. */ | |
542 | static sbitmap cse_visited_basic_blocks; | |
543 | ||
7080f735 | 544 | static bool fixed_base_plus_p (rtx x); |
e548c9df | 545 | static int notreg_cost (rtx, machine_mode, enum rtx_code, int); |
56ae04af | 546 | static int preferable (int, int, int, int); |
7080f735 | 547 | static void new_basic_block (void); |
ef4bddc2 | 548 | static void make_new_qty (unsigned int, machine_mode); |
7080f735 AJ |
549 | static void make_regs_eqv (unsigned int, unsigned int); |
550 | static void delete_reg_equiv (unsigned int); | |
551 | static int mention_regs (rtx); | |
552 | static int insert_regs (rtx, struct table_elt *, int); | |
553 | static void remove_from_table (struct table_elt *, unsigned); | |
d556d181 | 554 | static void remove_pseudo_from_table (rtx, unsigned); |
ef4bddc2 RS |
555 | static struct table_elt *lookup (rtx, unsigned, machine_mode); |
556 | static struct table_elt *lookup_for_remove (rtx, unsigned, machine_mode); | |
7080f735 | 557 | static rtx lookup_as_function (rtx, enum rtx_code); |
2c5bfdf7 | 558 | static struct table_elt *insert_with_costs (rtx, struct table_elt *, unsigned, |
ef4bddc2 | 559 | machine_mode, int, int); |
7080f735 | 560 | static struct table_elt *insert (rtx, struct table_elt *, unsigned, |
ef4bddc2 | 561 | machine_mode); |
7080f735 | 562 | static void merge_equiv_classes (struct table_elt *, struct table_elt *); |
ef4bddc2 | 563 | static void invalidate (rtx, machine_mode); |
7080f735 | 564 | static void remove_invalid_refs (unsigned int); |
91914e56 | 565 | static void remove_invalid_subreg_refs (unsigned int, poly_uint64, |
ef4bddc2 | 566 | machine_mode); |
7080f735 AJ |
567 | static void rehash_using_reg (rtx); |
568 | static void invalidate_memory (void); | |
7080f735 | 569 | static rtx use_related_value (rtx, struct table_elt *); |
0516f6fe | 570 | |
ef4bddc2 RS |
571 | static inline unsigned canon_hash (rtx, machine_mode); |
572 | static inline unsigned safe_hash (rtx, machine_mode); | |
e855c69d | 573 | static inline unsigned hash_rtx_string (const char *); |
0516f6fe | 574 | |
20468884 | 575 | static rtx canon_reg (rtx, rtx_insn *); |
7080f735 | 576 | static enum rtx_code find_comparison_args (enum rtx_code, rtx *, rtx *, |
ef4bddc2 RS |
577 | machine_mode *, |
578 | machine_mode *); | |
20468884 | 579 | static rtx fold_rtx (rtx, rtx_insn *); |
7080f735 | 580 | static rtx equiv_constant (rtx); |
20468884 | 581 | static void record_jump_equiv (rtx_insn *, bool); |
ef4bddc2 | 582 | static void record_jump_cond (enum rtx_code, machine_mode, rtx, rtx, |
7080f735 | 583 | int); |
20468884 | 584 | static void cse_insn (rtx_insn *); |
932ad4d9 | 585 | static void cse_prescan_path (struct cse_basic_block_data *); |
20468884 DM |
586 | static void invalidate_from_clobbers (rtx_insn *); |
587 | static void invalidate_from_sets_and_clobbers (rtx_insn *); | |
6fb5fa3c | 588 | static rtx cse_process_notes (rtx, rtx, bool *); |
932ad4d9 | 589 | static void cse_extended_basic_block (struct cse_basic_block_data *); |
7080f735 | 590 | extern void dump_class (struct table_elt*); |
bc5e3b54 KH |
591 | static void get_cse_reg_info_1 (unsigned int regno); |
592 | static struct cse_reg_info * get_cse_reg_info (unsigned int regno); | |
7080f735 AJ |
593 | |
594 | static void flush_hash_table (void); | |
20468884 DM |
595 | static bool insn_live_p (rtx_insn *, int *); |
596 | static bool set_live_p (rtx, rtx_insn *, int *); | |
20468884 DM |
597 | static void cse_change_cc_mode_insn (rtx_insn *, rtx); |
598 | static void cse_change_cc_mode_insns (rtx_insn *, rtx_insn *, rtx); | |
ef4bddc2 | 599 | static machine_mode cse_cc_succs (basic_block, basic_block, rtx, rtx, |
31e9ebaf | 600 | bool); |
7afe21cc | 601 | \f |
2f93eea8 PB |
602 | |
603 | #undef RTL_HOOKS_GEN_LOWPART | |
604 | #define RTL_HOOKS_GEN_LOWPART gen_lowpart_if_possible | |
605 | ||
606 | static const struct rtl_hooks cse_rtl_hooks = RTL_HOOKS_INITIALIZER; | |
607 | \f | |
6399c0ab | 608 | /* Nonzero if X has the form (PLUS frame-pointer integer). */ |
4977bab6 ZW |
609 | |
610 | static bool | |
7080f735 | 611 | fixed_base_plus_p (rtx x) |
4977bab6 ZW |
612 | { |
613 | switch (GET_CODE (x)) | |
614 | { | |
615 | case REG: | |
616 | if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx) | |
617 | return true; | |
618 | if (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]) | |
619 | return true; | |
4977bab6 ZW |
620 | return false; |
621 | ||
622 | case PLUS: | |
481683e1 | 623 | if (!CONST_INT_P (XEXP (x, 1))) |
4977bab6 ZW |
624 | return false; |
625 | return fixed_base_plus_p (XEXP (x, 0)); | |
626 | ||
4977bab6 ZW |
627 | default: |
628 | return false; | |
629 | } | |
630 | } | |
631 | ||
a4c6502a MM |
632 | /* Dump the expressions in the equivalence class indicated by CLASSP. |
633 | This function is used only for debugging. */ | |
711417cd | 634 | DEBUG_FUNCTION void |
7080f735 | 635 | dump_class (struct table_elt *classp) |
a4c6502a MM |
636 | { |
637 | struct table_elt *elt; | |
638 | ||
639 | fprintf (stderr, "Equivalence chain for "); | |
640 | print_rtl (stderr, classp->exp); | |
641 | fprintf (stderr, ": \n"); | |
278a83b2 | 642 | |
a4c6502a MM |
643 | for (elt = classp->first_same_value; elt; elt = elt->next_same_value) |
644 | { | |
645 | print_rtl (stderr, elt->exp); | |
646 | fprintf (stderr, "\n"); | |
647 | } | |
648 | } | |
649 | ||
e89b312e RS |
650 | /* Return an estimate of the cost of the registers used in an rtx. |
651 | This is mostly the number of different REG expressions in the rtx; | |
652 | however for some exceptions like fixed registers we use a cost of | |
653 | 0. If any other hard register reference occurs, return MAX_COST. */ | |
be8ac49a | 654 | |
630c79be | 655 | static int |
e89b312e | 656 | approx_reg_cost (const_rtx x) |
630c79be | 657 | { |
e89b312e RS |
658 | int cost = 0; |
659 | subrtx_iterator::array_type array; | |
660 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
c863f8c2 | 661 | { |
e89b312e RS |
662 | const_rtx x = *iter; |
663 | if (REG_P (x)) | |
c863f8c2 | 664 | { |
e89b312e RS |
665 | unsigned int regno = REGNO (x); |
666 | if (!CHEAP_REGNO (regno)) | |
c863f8c2 | 667 | { |
e89b312e RS |
668 | if (regno < FIRST_PSEUDO_REGISTER) |
669 | { | |
670 | if (targetm.small_register_classes_for_mode_p (GET_MODE (x))) | |
671 | return MAX_COST; | |
672 | cost += 2; | |
673 | } | |
674 | else | |
675 | cost += 1; | |
c863f8c2 | 676 | } |
c863f8c2 DM |
677 | } |
678 | } | |
c863f8c2 | 679 | return cost; |
630c79be BS |
680 | } |
681 | ||
682 | /* Return a negative value if an rtx A, whose costs are given by COST_A | |
683 | and REGCOST_A, is more desirable than an rtx B. | |
684 | Return a positive value if A is less desirable, or 0 if the two are | |
685 | equally good. */ | |
686 | static int | |
56ae04af | 687 | preferable (int cost_a, int regcost_a, int cost_b, int regcost_b) |
630c79be | 688 | { |
423adbb9 | 689 | /* First, get rid of cases involving expressions that are entirely |
f1c1dfc3 BS |
690 | unwanted. */ |
691 | if (cost_a != cost_b) | |
692 | { | |
693 | if (cost_a == MAX_COST) | |
694 | return 1; | |
695 | if (cost_b == MAX_COST) | |
696 | return -1; | |
697 | } | |
698 | ||
699 | /* Avoid extending lifetimes of hardregs. */ | |
700 | if (regcost_a != regcost_b) | |
701 | { | |
702 | if (regcost_a == MAX_COST) | |
703 | return 1; | |
704 | if (regcost_b == MAX_COST) | |
705 | return -1; | |
706 | } | |
707 | ||
708 | /* Normal operation costs take precedence. */ | |
630c79be BS |
709 | if (cost_a != cost_b) |
710 | return cost_a - cost_b; | |
f1c1dfc3 | 711 | /* Only if these are identical consider effects on register pressure. */ |
630c79be BS |
712 | if (regcost_a != regcost_b) |
713 | return regcost_a - regcost_b; | |
714 | return 0; | |
715 | } | |
716 | ||
954a5693 RK |
717 | /* Internal function, to compute cost when X is not a register; called |
718 | from COST macro to keep it simple. */ | |
719 | ||
720 | static int | |
e548c9df | 721 | notreg_cost (rtx x, machine_mode mode, enum rtx_code outer, int opno) |
954a5693 | 722 | { |
b4206259 | 723 | scalar_int_mode int_mode, inner_mode; |
954a5693 | 724 | return ((GET_CODE (x) == SUBREG |
f8cfc6aa | 725 | && REG_P (SUBREG_REG (x)) |
b4206259 RS |
726 | && is_int_mode (mode, &int_mode) |
727 | && is_int_mode (GET_MODE (SUBREG_REG (x)), &inner_mode) | |
728 | && GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (inner_mode) | |
954a5693 | 729 | && subreg_lowpart_p (x) |
b4206259 | 730 | && TRULY_NOOP_TRUNCATION_MODES_P (int_mode, inner_mode)) |
630c79be | 731 | ? 0 |
e548c9df | 732 | : rtx_cost (x, mode, outer, opno, optimize_this_for_speed_p) * 2); |
954a5693 RK |
733 | } |
734 | ||
01329426 | 735 | \f |
bc5e3b54 | 736 | /* Initialize CSE_REG_INFO_TABLE. */ |
9b1549b8 | 737 | |
bc5e3b54 KH |
738 | static void |
739 | init_cse_reg_info (unsigned int nregs) | |
740 | { | |
741 | /* Do we need to grow the table? */ | |
742 | if (nregs > cse_reg_info_table_size) | |
30f72379 | 743 | { |
bc5e3b54 KH |
744 | unsigned int new_size; |
745 | ||
746 | if (cse_reg_info_table_size < 2048) | |
30f72379 | 747 | { |
bc5e3b54 KH |
748 | /* Compute a new size that is a power of 2 and no smaller |
749 | than the large of NREGS and 64. */ | |
750 | new_size = (cse_reg_info_table_size | |
751 | ? cse_reg_info_table_size : 64); | |
752 | ||
753 | while (new_size < nregs) | |
754 | new_size *= 2; | |
30f72379 MM |
755 | } |
756 | else | |
1590d0d4 | 757 | { |
bc5e3b54 KH |
758 | /* If we need a big table, allocate just enough to hold |
759 | NREGS registers. */ | |
760 | new_size = nregs; | |
1590d0d4 | 761 | } |
9b1549b8 | 762 | |
bc5e3b54 | 763 | /* Reallocate the table with NEW_SIZE entries. */ |
04695783 | 764 | free (cse_reg_info_table); |
5ed6ace5 | 765 | cse_reg_info_table = XNEWVEC (struct cse_reg_info, new_size); |
bc5e3b54 | 766 | cse_reg_info_table_size = new_size; |
a811c672 | 767 | cse_reg_info_table_first_uninitialized = 0; |
bc5e3b54 KH |
768 | } |
769 | ||
770 | /* Do we have all of the first NREGS entries initialized? */ | |
771 | if (cse_reg_info_table_first_uninitialized < nregs) | |
772 | { | |
773 | unsigned int old_timestamp = cse_reg_info_timestamp - 1; | |
774 | unsigned int i; | |
775 | ||
776 | /* Put the old timestamp on newly allocated entries so that they | |
777 | will all be considered out of date. We do not touch those | |
778 | entries beyond the first NREGS entries to be nice to the | |
779 | virtual memory. */ | |
780 | for (i = cse_reg_info_table_first_uninitialized; i < nregs; i++) | |
781 | cse_reg_info_table[i].timestamp = old_timestamp; | |
30f72379 | 782 | |
bc5e3b54 | 783 | cse_reg_info_table_first_uninitialized = nregs; |
30f72379 | 784 | } |
bc5e3b54 KH |
785 | } |
786 | ||
a52aff23 | 787 | /* Given REGNO, initialize the cse_reg_info entry for REGNO. */ |
bc5e3b54 KH |
788 | |
789 | static void | |
790 | get_cse_reg_info_1 (unsigned int regno) | |
791 | { | |
792 | /* Set TIMESTAMP field to CSE_REG_INFO_TIMESTAMP so that this | |
793 | entry will be considered to have been initialized. */ | |
794 | cse_reg_info_table[regno].timestamp = cse_reg_info_timestamp; | |
795 | ||
796 | /* Initialize the rest of the entry. */ | |
797 | cse_reg_info_table[regno].reg_tick = 1; | |
798 | cse_reg_info_table[regno].reg_in_table = -1; | |
799 | cse_reg_info_table[regno].subreg_ticked = -1; | |
800 | cse_reg_info_table[regno].reg_qty = -regno - 1; | |
801 | } | |
802 | ||
803 | /* Find a cse_reg_info entry for REGNO. */ | |
30f72379 | 804 | |
bc5e3b54 KH |
805 | static inline struct cse_reg_info * |
806 | get_cse_reg_info (unsigned int regno) | |
807 | { | |
808 | struct cse_reg_info *p = &cse_reg_info_table[regno]; | |
809 | ||
782c0a3e KH |
810 | /* If this entry has not been initialized, go ahead and initialize |
811 | it. */ | |
bc5e3b54 KH |
812 | if (p->timestamp != cse_reg_info_timestamp) |
813 | get_cse_reg_info_1 (regno); | |
30f72379 | 814 | |
9b1549b8 | 815 | return p; |
30f72379 MM |
816 | } |
817 | ||
7afe21cc RK |
818 | /* Clear the hash table and initialize each register with its own quantity, |
819 | for a new basic block. */ | |
820 | ||
821 | static void | |
7080f735 | 822 | new_basic_block (void) |
7afe21cc | 823 | { |
b3694847 | 824 | int i; |
7afe21cc | 825 | |
08a69267 | 826 | next_qty = 0; |
7afe21cc | 827 | |
a52aff23 | 828 | /* Invalidate cse_reg_info_table. */ |
bc5e3b54 | 829 | cse_reg_info_timestamp++; |
7afe21cc | 830 | |
bc5e3b54 | 831 | /* Clear out hash table state for this pass. */ |
7afe21cc RK |
832 | CLEAR_HARD_REG_SET (hard_regs_in_table); |
833 | ||
834 | /* The per-quantity values used to be initialized here, but it is | |
835 | much faster to initialize each as it is made in `make_new_qty'. */ | |
836 | ||
9b1549b8 | 837 | for (i = 0; i < HASH_SIZE; i++) |
7afe21cc | 838 | { |
9b1549b8 DM |
839 | struct table_elt *first; |
840 | ||
841 | first = table[i]; | |
842 | if (first != NULL) | |
7afe21cc | 843 | { |
9b1549b8 DM |
844 | struct table_elt *last = first; |
845 | ||
846 | table[i] = NULL; | |
847 | ||
848 | while (last->next_same_hash != NULL) | |
849 | last = last->next_same_hash; | |
850 | ||
851 | /* Now relink this hash entire chain into | |
852 | the free element list. */ | |
853 | ||
854 | last->next_same_hash = free_element_chain; | |
855 | free_element_chain = first; | |
7afe21cc RK |
856 | } |
857 | } | |
858 | ||
7afe21cc | 859 | prev_insn_cc0 = 0; |
7afe21cc RK |
860 | } |
861 | ||
1bb98cec DM |
862 | /* Say that register REG contains a quantity in mode MODE not in any |
863 | register before and initialize that quantity. */ | |
7afe21cc RK |
864 | |
865 | static void | |
ef4bddc2 | 866 | make_new_qty (unsigned int reg, machine_mode mode) |
7afe21cc | 867 | { |
b3694847 SS |
868 | int q; |
869 | struct qty_table_elem *ent; | |
870 | struct reg_eqv_elem *eqv; | |
7afe21cc | 871 | |
341c100f | 872 | gcc_assert (next_qty < max_qty); |
7afe21cc | 873 | |
30f72379 | 874 | q = REG_QTY (reg) = next_qty++; |
1bb98cec DM |
875 | ent = &qty_table[q]; |
876 | ent->first_reg = reg; | |
877 | ent->last_reg = reg; | |
878 | ent->mode = mode; | |
20468884 | 879 | ent->const_rtx = ent->const_insn = NULL; |
1bb98cec DM |
880 | ent->comparison_code = UNKNOWN; |
881 | ||
882 | eqv = ®_eqv_table[reg]; | |
883 | eqv->next = eqv->prev = -1; | |
7afe21cc RK |
884 | } |
885 | ||
886 | /* Make reg NEW equivalent to reg OLD. | |
887 | OLD is not changing; NEW is. */ | |
888 | ||
889 | static void | |
32e9fa48 | 890 | make_regs_eqv (unsigned int new_reg, unsigned int old_reg) |
7afe21cc | 891 | { |
770ae6cc | 892 | unsigned int lastr, firstr; |
32e9fa48 | 893 | int q = REG_QTY (old_reg); |
770ae6cc | 894 | struct qty_table_elem *ent; |
1bb98cec DM |
895 | |
896 | ent = &qty_table[q]; | |
7afe21cc RK |
897 | |
898 | /* Nothing should become eqv until it has a "non-invalid" qty number. */ | |
32e9fa48 | 899 | gcc_assert (REGNO_QTY_VALID_P (old_reg)); |
7afe21cc | 900 | |
32e9fa48 | 901 | REG_QTY (new_reg) = q; |
1bb98cec DM |
902 | firstr = ent->first_reg; |
903 | lastr = ent->last_reg; | |
7afe21cc RK |
904 | |
905 | /* Prefer fixed hard registers to anything. Prefer pseudo regs to other | |
906 | hard regs. Among pseudos, if NEW will live longer than any other reg | |
907 | of the same qty, and that is beyond the current basic block, | |
908 | make it the new canonical replacement for this qty. */ | |
909 | if (! (firstr < FIRST_PSEUDO_REGISTER && FIXED_REGNO_P (firstr)) | |
910 | /* Certain fixed registers might be of the class NO_REGS. This means | |
911 | that not only can they not be allocated by the compiler, but | |
830a38ee | 912 | they cannot be used in substitutions or canonicalizations |
7afe21cc | 913 | either. */ |
32e9fa48 KG |
914 | && (new_reg >= FIRST_PSEUDO_REGISTER || REGNO_REG_CLASS (new_reg) != NO_REGS) |
915 | && ((new_reg < FIRST_PSEUDO_REGISTER && FIXED_REGNO_P (new_reg)) | |
916 | || (new_reg >= FIRST_PSEUDO_REGISTER | |
7afe21cc | 917 | && (firstr < FIRST_PSEUDO_REGISTER |
32e9fa48 | 918 | || (bitmap_bit_p (cse_ebb_live_out, new_reg) |
6fb5fa3c | 919 | && !bitmap_bit_p (cse_ebb_live_out, firstr)) |
32e9fa48 | 920 | || (bitmap_bit_p (cse_ebb_live_in, new_reg) |
6fb5fa3c | 921 | && !bitmap_bit_p (cse_ebb_live_in, firstr)))))) |
7afe21cc | 922 | { |
32e9fa48 KG |
923 | reg_eqv_table[firstr].prev = new_reg; |
924 | reg_eqv_table[new_reg].next = firstr; | |
925 | reg_eqv_table[new_reg].prev = -1; | |
926 | ent->first_reg = new_reg; | |
7afe21cc RK |
927 | } |
928 | else | |
929 | { | |
930 | /* If NEW is a hard reg (known to be non-fixed), insert at end. | |
931 | Otherwise, insert before any non-fixed hard regs that are at the | |
932 | end. Registers of class NO_REGS cannot be used as an | |
933 | equivalent for anything. */ | |
1bb98cec | 934 | while (lastr < FIRST_PSEUDO_REGISTER && reg_eqv_table[lastr].prev >= 0 |
7afe21cc | 935 | && (REGNO_REG_CLASS (lastr) == NO_REGS || ! FIXED_REGNO_P (lastr)) |
32e9fa48 | 936 | && new_reg >= FIRST_PSEUDO_REGISTER) |
1bb98cec | 937 | lastr = reg_eqv_table[lastr].prev; |
32e9fa48 | 938 | reg_eqv_table[new_reg].next = reg_eqv_table[lastr].next; |
1bb98cec | 939 | if (reg_eqv_table[lastr].next >= 0) |
32e9fa48 | 940 | reg_eqv_table[reg_eqv_table[lastr].next].prev = new_reg; |
7afe21cc | 941 | else |
32e9fa48 KG |
942 | qty_table[q].last_reg = new_reg; |
943 | reg_eqv_table[lastr].next = new_reg; | |
944 | reg_eqv_table[new_reg].prev = lastr; | |
7afe21cc RK |
945 | } |
946 | } | |
947 | ||
948 | /* Remove REG from its equivalence class. */ | |
949 | ||
950 | static void | |
7080f735 | 951 | delete_reg_equiv (unsigned int reg) |
7afe21cc | 952 | { |
b3694847 SS |
953 | struct qty_table_elem *ent; |
954 | int q = REG_QTY (reg); | |
955 | int p, n; | |
7afe21cc | 956 | |
a4e262bc | 957 | /* If invalid, do nothing. */ |
08a69267 | 958 | if (! REGNO_QTY_VALID_P (reg)) |
7afe21cc RK |
959 | return; |
960 | ||
1bb98cec DM |
961 | ent = &qty_table[q]; |
962 | ||
963 | p = reg_eqv_table[reg].prev; | |
964 | n = reg_eqv_table[reg].next; | |
a4e262bc | 965 | |
7afe21cc | 966 | if (n != -1) |
1bb98cec | 967 | reg_eqv_table[n].prev = p; |
7afe21cc | 968 | else |
1bb98cec | 969 | ent->last_reg = p; |
7afe21cc | 970 | if (p != -1) |
1bb98cec | 971 | reg_eqv_table[p].next = n; |
7afe21cc | 972 | else |
1bb98cec | 973 | ent->first_reg = n; |
7afe21cc | 974 | |
08a69267 | 975 | REG_QTY (reg) = -reg - 1; |
7afe21cc RK |
976 | } |
977 | ||
978 | /* Remove any invalid expressions from the hash table | |
979 | that refer to any of the registers contained in expression X. | |
980 | ||
981 | Make sure that newly inserted references to those registers | |
982 | as subexpressions will be considered valid. | |
983 | ||
984 | mention_regs is not called when a register itself | |
985 | is being stored in the table. | |
986 | ||
987 | Return 1 if we have done something that may have changed the hash code | |
988 | of X. */ | |
989 | ||
990 | static int | |
7080f735 | 991 | mention_regs (rtx x) |
7afe21cc | 992 | { |
b3694847 SS |
993 | enum rtx_code code; |
994 | int i, j; | |
995 | const char *fmt; | |
996 | int changed = 0; | |
7afe21cc RK |
997 | |
998 | if (x == 0) | |
e5f6a288 | 999 | return 0; |
7afe21cc RK |
1000 | |
1001 | code = GET_CODE (x); | |
1002 | if (code == REG) | |
1003 | { | |
770ae6cc | 1004 | unsigned int regno = REGNO (x); |
09e18274 | 1005 | unsigned int endregno = END_REGNO (x); |
770ae6cc | 1006 | unsigned int i; |
7afe21cc RK |
1007 | |
1008 | for (i = regno; i < endregno; i++) | |
1009 | { | |
30f72379 | 1010 | if (REG_IN_TABLE (i) >= 0 && REG_IN_TABLE (i) != REG_TICK (i)) |
7afe21cc RK |
1011 | remove_invalid_refs (i); |
1012 | ||
30f72379 | 1013 | REG_IN_TABLE (i) = REG_TICK (i); |
46081bb3 | 1014 | SUBREG_TICKED (i) = -1; |
7afe21cc RK |
1015 | } |
1016 | ||
1017 | return 0; | |
1018 | } | |
1019 | ||
34c73909 R |
1020 | /* If this is a SUBREG, we don't want to discard other SUBREGs of the same |
1021 | pseudo if they don't use overlapping words. We handle only pseudos | |
1022 | here for simplicity. */ | |
f8cfc6aa | 1023 | if (code == SUBREG && REG_P (SUBREG_REG (x)) |
34c73909 R |
1024 | && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER) |
1025 | { | |
770ae6cc | 1026 | unsigned int i = REGNO (SUBREG_REG (x)); |
34c73909 | 1027 | |
30f72379 | 1028 | if (REG_IN_TABLE (i) >= 0 && REG_IN_TABLE (i) != REG_TICK (i)) |
34c73909 | 1029 | { |
46081bb3 SH |
1030 | /* If REG_IN_TABLE (i) differs from REG_TICK (i) by one, and |
1031 | the last store to this register really stored into this | |
1032 | subreg, then remove the memory of this subreg. | |
1033 | Otherwise, remove any memory of the entire register and | |
1034 | all its subregs from the table. */ | |
1035 | if (REG_TICK (i) - REG_IN_TABLE (i) > 1 | |
5dd78e9a | 1036 | || SUBREG_TICKED (i) != REGNO (SUBREG_REG (x))) |
34c73909 R |
1037 | remove_invalid_refs (i); |
1038 | else | |
ddef6bc7 | 1039 | remove_invalid_subreg_refs (i, SUBREG_BYTE (x), GET_MODE (x)); |
34c73909 R |
1040 | } |
1041 | ||
30f72379 | 1042 | REG_IN_TABLE (i) = REG_TICK (i); |
5dd78e9a | 1043 | SUBREG_TICKED (i) = REGNO (SUBREG_REG (x)); |
34c73909 R |
1044 | return 0; |
1045 | } | |
1046 | ||
7afe21cc RK |
1047 | /* If X is a comparison or a COMPARE and either operand is a register |
1048 | that does not have a quantity, give it one. This is so that a later | |
1049 | call to record_jump_equiv won't cause X to be assigned a different | |
1050 | hash code and not found in the table after that call. | |
1051 | ||
1052 | It is not necessary to do this here, since rehash_using_reg can | |
1053 | fix up the table later, but doing this here eliminates the need to | |
1054 | call that expensive function in the most common case where the only | |
1055 | use of the register is in the comparison. */ | |
1056 | ||
ec8e098d | 1057 | if (code == COMPARE || COMPARISON_P (x)) |
7afe21cc | 1058 | { |
f8cfc6aa | 1059 | if (REG_P (XEXP (x, 0)) |
7afe21cc | 1060 | && ! REGNO_QTY_VALID_P (REGNO (XEXP (x, 0)))) |
9714cf43 | 1061 | if (insert_regs (XEXP (x, 0), NULL, 0)) |
7afe21cc RK |
1062 | { |
1063 | rehash_using_reg (XEXP (x, 0)); | |
1064 | changed = 1; | |
1065 | } | |
1066 | ||
f8cfc6aa | 1067 | if (REG_P (XEXP (x, 1)) |
7afe21cc | 1068 | && ! REGNO_QTY_VALID_P (REGNO (XEXP (x, 1)))) |
9714cf43 | 1069 | if (insert_regs (XEXP (x, 1), NULL, 0)) |
7afe21cc RK |
1070 | { |
1071 | rehash_using_reg (XEXP (x, 1)); | |
1072 | changed = 1; | |
1073 | } | |
1074 | } | |
1075 | ||
1076 | fmt = GET_RTX_FORMAT (code); | |
1077 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
1078 | if (fmt[i] == 'e') | |
1079 | changed |= mention_regs (XEXP (x, i)); | |
1080 | else if (fmt[i] == 'E') | |
1081 | for (j = 0; j < XVECLEN (x, i); j++) | |
1082 | changed |= mention_regs (XVECEXP (x, i, j)); | |
1083 | ||
1084 | return changed; | |
1085 | } | |
1086 | ||
1087 | /* Update the register quantities for inserting X into the hash table | |
1088 | with a value equivalent to CLASSP. | |
1089 | (If the class does not contain a REG, it is irrelevant.) | |
1090 | If MODIFIED is nonzero, X is a destination; it is being modified. | |
1091 | Note that delete_reg_equiv should be called on a register | |
1092 | before insert_regs is done on that register with MODIFIED != 0. | |
1093 | ||
1094 | Nonzero value means that elements of reg_qty have changed | |
1095 | so X's hash code may be different. */ | |
1096 | ||
1097 | static int | |
7080f735 | 1098 | insert_regs (rtx x, struct table_elt *classp, int modified) |
7afe21cc | 1099 | { |
f8cfc6aa | 1100 | if (REG_P (x)) |
7afe21cc | 1101 | { |
770ae6cc RK |
1102 | unsigned int regno = REGNO (x); |
1103 | int qty_valid; | |
7afe21cc | 1104 | |
1ff0c00d RK |
1105 | /* If REGNO is in the equivalence table already but is of the |
1106 | wrong mode for that equivalence, don't do anything here. */ | |
1107 | ||
1bb98cec DM |
1108 | qty_valid = REGNO_QTY_VALID_P (regno); |
1109 | if (qty_valid) | |
1110 | { | |
1111 | struct qty_table_elem *ent = &qty_table[REG_QTY (regno)]; | |
1ff0c00d | 1112 | |
1bb98cec DM |
1113 | if (ent->mode != GET_MODE (x)) |
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | if (modified || ! qty_valid) | |
7afe21cc RK |
1118 | { |
1119 | if (classp) | |
1120 | for (classp = classp->first_same_value; | |
1121 | classp != 0; | |
1122 | classp = classp->next_same_value) | |
f8cfc6aa | 1123 | if (REG_P (classp->exp) |
7afe21cc RK |
1124 | && GET_MODE (classp->exp) == GET_MODE (x)) |
1125 | { | |
cd928652 ZD |
1126 | unsigned c_regno = REGNO (classp->exp); |
1127 | ||
1128 | gcc_assert (REGNO_QTY_VALID_P (c_regno)); | |
1129 | ||
1130 | /* Suppose that 5 is hard reg and 100 and 101 are | |
1131 | pseudos. Consider | |
1132 | ||
1133 | (set (reg:si 100) (reg:si 5)) | |
1134 | (set (reg:si 5) (reg:si 100)) | |
1135 | (set (reg:di 101) (reg:di 5)) | |
1136 | ||
1137 | We would now set REG_QTY (101) = REG_QTY (5), but the | |
1138 | entry for 5 is in SImode. When we use this later in | |
1139 | copy propagation, we get the register in wrong mode. */ | |
1140 | if (qty_table[REG_QTY (c_regno)].mode != GET_MODE (x)) | |
1141 | continue; | |
1142 | ||
1143 | make_regs_eqv (regno, c_regno); | |
7afe21cc RK |
1144 | return 1; |
1145 | } | |
1146 | ||
d9f20424 R |
1147 | /* Mention_regs for a SUBREG checks if REG_TICK is exactly one larger |
1148 | than REG_IN_TABLE to find out if there was only a single preceding | |
1149 | invalidation - for the SUBREG - or another one, which would be | |
1150 | for the full register. However, if we find here that REG_TICK | |
1151 | indicates that the register is invalid, it means that it has | |
1152 | been invalidated in a separate operation. The SUBREG might be used | |
1153 | now (then this is a recursive call), or we might use the full REG | |
1154 | now and a SUBREG of it later. So bump up REG_TICK so that | |
1155 | mention_regs will do the right thing. */ | |
1156 | if (! modified | |
1157 | && REG_IN_TABLE (regno) >= 0 | |
1158 | && REG_TICK (regno) == REG_IN_TABLE (regno) + 1) | |
1159 | REG_TICK (regno)++; | |
1bb98cec | 1160 | make_new_qty (regno, GET_MODE (x)); |
7afe21cc RK |
1161 | return 1; |
1162 | } | |
cdf4112f TG |
1163 | |
1164 | return 0; | |
7afe21cc | 1165 | } |
c610adec RK |
1166 | |
1167 | /* If X is a SUBREG, we will likely be inserting the inner register in the | |
1168 | table. If that register doesn't have an assigned quantity number at | |
1169 | this point but does later, the insertion that we will be doing now will | |
1170 | not be accessible because its hash code will have changed. So assign | |
1171 | a quantity number now. */ | |
1172 | ||
f8cfc6aa | 1173 | else if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)) |
c610adec RK |
1174 | && ! REGNO_QTY_VALID_P (REGNO (SUBREG_REG (x)))) |
1175 | { | |
9714cf43 | 1176 | insert_regs (SUBREG_REG (x), NULL, 0); |
34c73909 | 1177 | mention_regs (x); |
c610adec RK |
1178 | return 1; |
1179 | } | |
7afe21cc RK |
1180 | else |
1181 | return mention_regs (x); | |
1182 | } | |
1183 | \f | |
2c5bfdf7 AN |
1184 | |
1185 | /* Compute upper and lower anchors for CST. Also compute the offset of CST | |
1186 | from these anchors/bases such that *_BASE + *_OFFS = CST. Return false iff | |
1187 | CST is equal to an anchor. */ | |
1188 | ||
1189 | static bool | |
1190 | compute_const_anchors (rtx cst, | |
1191 | HOST_WIDE_INT *lower_base, HOST_WIDE_INT *lower_offs, | |
1192 | HOST_WIDE_INT *upper_base, HOST_WIDE_INT *upper_offs) | |
1193 | { | |
1194 | HOST_WIDE_INT n = INTVAL (cst); | |
1195 | ||
1196 | *lower_base = n & ~(targetm.const_anchor - 1); | |
1197 | if (*lower_base == n) | |
1198 | return false; | |
1199 | ||
1200 | *upper_base = | |
1201 | (n + (targetm.const_anchor - 1)) & ~(targetm.const_anchor - 1); | |
1202 | *upper_offs = n - *upper_base; | |
1203 | *lower_offs = n - *lower_base; | |
1204 | return true; | |
1205 | } | |
1206 | ||
1207 | /* Insert the equivalence between ANCHOR and (REG + OFF) in mode MODE. */ | |
1208 | ||
1209 | static void | |
1210 | insert_const_anchor (HOST_WIDE_INT anchor, rtx reg, HOST_WIDE_INT offs, | |
ef4bddc2 | 1211 | machine_mode mode) |
2c5bfdf7 AN |
1212 | { |
1213 | struct table_elt *elt; | |
1214 | unsigned hash; | |
1215 | rtx anchor_exp; | |
1216 | rtx exp; | |
1217 | ||
1218 | anchor_exp = GEN_INT (anchor); | |
1219 | hash = HASH (anchor_exp, mode); | |
1220 | elt = lookup (anchor_exp, hash, mode); | |
1221 | if (!elt) | |
1222 | elt = insert (anchor_exp, NULL, hash, mode); | |
1223 | ||
0a81f074 | 1224 | exp = plus_constant (mode, reg, offs); |
2c5bfdf7 AN |
1225 | /* REG has just been inserted and the hash codes recomputed. */ |
1226 | mention_regs (exp); | |
1227 | hash = HASH (exp, mode); | |
1228 | ||
1229 | /* Use the cost of the register rather than the whole expression. When | |
1230 | looking up constant anchors we will further offset the corresponding | |
1231 | expression therefore it does not make sense to prefer REGs over | |
1232 | reg-immediate additions. Prefer instead the oldest expression. Also | |
1233 | don't prefer pseudos over hard regs so that we derive constants in | |
1234 | argument registers from other argument registers rather than from the | |
1235 | original pseudo that was used to synthesize the constant. */ | |
e548c9df | 1236 | insert_with_costs (exp, elt, hash, mode, COST (reg, mode), 1); |
2c5bfdf7 AN |
1237 | } |
1238 | ||
1239 | /* The constant CST is equivalent to the register REG. Create | |
1240 | equivalences between the two anchors of CST and the corresponding | |
1241 | register-offset expressions using REG. */ | |
1242 | ||
1243 | static void | |
ef4bddc2 | 1244 | insert_const_anchors (rtx reg, rtx cst, machine_mode mode) |
2c5bfdf7 AN |
1245 | { |
1246 | HOST_WIDE_INT lower_base, lower_offs, upper_base, upper_offs; | |
1247 | ||
1248 | if (!compute_const_anchors (cst, &lower_base, &lower_offs, | |
1249 | &upper_base, &upper_offs)) | |
1250 | return; | |
1251 | ||
1252 | /* Ignore anchors of value 0. Constants accessible from zero are | |
1253 | simple. */ | |
1254 | if (lower_base != 0) | |
1255 | insert_const_anchor (lower_base, reg, -lower_offs, mode); | |
1256 | ||
1257 | if (upper_base != 0) | |
1258 | insert_const_anchor (upper_base, reg, -upper_offs, mode); | |
1259 | } | |
1260 | ||
1261 | /* We need to express ANCHOR_ELT->exp + OFFS. Walk the equivalence list of | |
1262 | ANCHOR_ELT and see if offsetting any of the entries by OFFS would create a | |
1263 | valid expression. Return the cheapest and oldest of such expressions. In | |
1264 | *OLD, return how old the resulting expression is compared to the other | |
1265 | equivalent expressions. */ | |
1266 | ||
1267 | static rtx | |
1268 | find_reg_offset_for_const (struct table_elt *anchor_elt, HOST_WIDE_INT offs, | |
1269 | unsigned *old) | |
1270 | { | |
1271 | struct table_elt *elt; | |
1272 | unsigned idx; | |
1273 | struct table_elt *match_elt; | |
1274 | rtx match; | |
1275 | ||
1276 | /* Find the cheapest and *oldest* expression to maximize the chance of | |
1277 | reusing the same pseudo. */ | |
1278 | ||
1279 | match_elt = NULL; | |
1280 | match = NULL_RTX; | |
1281 | for (elt = anchor_elt->first_same_value, idx = 0; | |
1282 | elt; | |
1283 | elt = elt->next_same_value, idx++) | |
1284 | { | |
1285 | if (match_elt && CHEAPER (match_elt, elt)) | |
1286 | return match; | |
1287 | ||
1288 | if (REG_P (elt->exp) | |
1289 | || (GET_CODE (elt->exp) == PLUS | |
1290 | && REG_P (XEXP (elt->exp, 0)) | |
1291 | && GET_CODE (XEXP (elt->exp, 1)) == CONST_INT)) | |
1292 | { | |
1293 | rtx x; | |
1294 | ||
1295 | /* Ignore expressions that are no longer valid. */ | |
1296 | if (!REG_P (elt->exp) && !exp_equiv_p (elt->exp, elt->exp, 1, false)) | |
1297 | continue; | |
1298 | ||
0a81f074 | 1299 | x = plus_constant (GET_MODE (elt->exp), elt->exp, offs); |
2c5bfdf7 AN |
1300 | if (REG_P (x) |
1301 | || (GET_CODE (x) == PLUS | |
1302 | && IN_RANGE (INTVAL (XEXP (x, 1)), | |
1303 | -targetm.const_anchor, | |
1304 | targetm.const_anchor - 1))) | |
1305 | { | |
1306 | match = x; | |
1307 | match_elt = elt; | |
1308 | *old = idx; | |
1309 | } | |
1310 | } | |
1311 | } | |
1312 | ||
1313 | return match; | |
1314 | } | |
1315 | ||
1316 | /* Try to express the constant SRC_CONST using a register+offset expression | |
1317 | derived from a constant anchor. Return it if successful or NULL_RTX, | |
1318 | otherwise. */ | |
1319 | ||
1320 | static rtx | |
ef4bddc2 | 1321 | try_const_anchors (rtx src_const, machine_mode mode) |
2c5bfdf7 AN |
1322 | { |
1323 | struct table_elt *lower_elt, *upper_elt; | |
1324 | HOST_WIDE_INT lower_base, lower_offs, upper_base, upper_offs; | |
1325 | rtx lower_anchor_rtx, upper_anchor_rtx; | |
1326 | rtx lower_exp = NULL_RTX, upper_exp = NULL_RTX; | |
1327 | unsigned lower_old, upper_old; | |
1328 | ||
40dbb05c RS |
1329 | /* CONST_INT is used for CC modes, but we should leave those alone. */ |
1330 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
1331 | return NULL_RTX; | |
1332 | ||
1333 | gcc_assert (SCALAR_INT_MODE_P (mode)); | |
2c5bfdf7 AN |
1334 | if (!compute_const_anchors (src_const, &lower_base, &lower_offs, |
1335 | &upper_base, &upper_offs)) | |
1336 | return NULL_RTX; | |
1337 | ||
1338 | lower_anchor_rtx = GEN_INT (lower_base); | |
1339 | upper_anchor_rtx = GEN_INT (upper_base); | |
1340 | lower_elt = lookup (lower_anchor_rtx, HASH (lower_anchor_rtx, mode), mode); | |
1341 | upper_elt = lookup (upper_anchor_rtx, HASH (upper_anchor_rtx, mode), mode); | |
1342 | ||
1343 | if (lower_elt) | |
1344 | lower_exp = find_reg_offset_for_const (lower_elt, lower_offs, &lower_old); | |
1345 | if (upper_elt) | |
1346 | upper_exp = find_reg_offset_for_const (upper_elt, upper_offs, &upper_old); | |
1347 | ||
1348 | if (!lower_exp) | |
1349 | return upper_exp; | |
1350 | if (!upper_exp) | |
1351 | return lower_exp; | |
1352 | ||
1353 | /* Return the older expression. */ | |
1354 | return (upper_old > lower_old ? upper_exp : lower_exp); | |
1355 | } | |
1356 | \f | |
7afe21cc RK |
1357 | /* Look in or update the hash table. */ |
1358 | ||
7afe21cc RK |
1359 | /* Remove table element ELT from use in the table. |
1360 | HASH is its hash code, made using the HASH macro. | |
1361 | It's an argument because often that is known in advance | |
1362 | and we save much time not recomputing it. */ | |
1363 | ||
1364 | static void | |
7080f735 | 1365 | remove_from_table (struct table_elt *elt, unsigned int hash) |
7afe21cc RK |
1366 | { |
1367 | if (elt == 0) | |
1368 | return; | |
1369 | ||
1370 | /* Mark this element as removed. See cse_insn. */ | |
1371 | elt->first_same_value = 0; | |
1372 | ||
1373 | /* Remove the table element from its equivalence class. */ | |
278a83b2 | 1374 | |
7afe21cc | 1375 | { |
b3694847 SS |
1376 | struct table_elt *prev = elt->prev_same_value; |
1377 | struct table_elt *next = elt->next_same_value; | |
7afe21cc | 1378 | |
278a83b2 KH |
1379 | if (next) |
1380 | next->prev_same_value = prev; | |
7afe21cc RK |
1381 | |
1382 | if (prev) | |
1383 | prev->next_same_value = next; | |
1384 | else | |
1385 | { | |
b3694847 | 1386 | struct table_elt *newfirst = next; |
7afe21cc RK |
1387 | while (next) |
1388 | { | |
1389 | next->first_same_value = newfirst; | |
1390 | next = next->next_same_value; | |
1391 | } | |
1392 | } | |
1393 | } | |
1394 | ||
1395 | /* Remove the table element from its hash bucket. */ | |
1396 | ||
1397 | { | |
b3694847 SS |
1398 | struct table_elt *prev = elt->prev_same_hash; |
1399 | struct table_elt *next = elt->next_same_hash; | |
7afe21cc | 1400 | |
278a83b2 KH |
1401 | if (next) |
1402 | next->prev_same_hash = prev; | |
7afe21cc RK |
1403 | |
1404 | if (prev) | |
1405 | prev->next_same_hash = next; | |
1406 | else if (table[hash] == elt) | |
1407 | table[hash] = next; | |
1408 | else | |
1409 | { | |
1410 | /* This entry is not in the proper hash bucket. This can happen | |
1411 | when two classes were merged by `merge_equiv_classes'. Search | |
1412 | for the hash bucket that it heads. This happens only very | |
1413 | rarely, so the cost is acceptable. */ | |
9b1549b8 | 1414 | for (hash = 0; hash < HASH_SIZE; hash++) |
7afe21cc RK |
1415 | if (table[hash] == elt) |
1416 | table[hash] = next; | |
1417 | } | |
1418 | } | |
1419 | ||
1420 | /* Remove the table element from its related-value circular chain. */ | |
1421 | ||
1422 | if (elt->related_value != 0 && elt->related_value != elt) | |
1423 | { | |
b3694847 | 1424 | struct table_elt *p = elt->related_value; |
770ae6cc | 1425 | |
7afe21cc RK |
1426 | while (p->related_value != elt) |
1427 | p = p->related_value; | |
1428 | p->related_value = elt->related_value; | |
1429 | if (p->related_value == p) | |
1430 | p->related_value = 0; | |
1431 | } | |
1432 | ||
9b1549b8 DM |
1433 | /* Now add it to the free element chain. */ |
1434 | elt->next_same_hash = free_element_chain; | |
1435 | free_element_chain = elt; | |
7afe21cc RK |
1436 | } |
1437 | ||
d556d181 EB |
1438 | /* Same as above, but X is a pseudo-register. */ |
1439 | ||
1440 | static void | |
1441 | remove_pseudo_from_table (rtx x, unsigned int hash) | |
1442 | { | |
1443 | struct table_elt *elt; | |
1444 | ||
1445 | /* Because a pseudo-register can be referenced in more than one | |
1446 | mode, we might have to remove more than one table entry. */ | |
1447 | while ((elt = lookup_for_remove (x, hash, VOIDmode))) | |
1448 | remove_from_table (elt, hash); | |
1449 | } | |
1450 | ||
7afe21cc RK |
1451 | /* Look up X in the hash table and return its table element, |
1452 | or 0 if X is not in the table. | |
1453 | ||
1454 | MODE is the machine-mode of X, or if X is an integer constant | |
1455 | with VOIDmode then MODE is the mode with which X will be used. | |
1456 | ||
1457 | Here we are satisfied to find an expression whose tree structure | |
1458 | looks like X. */ | |
1459 | ||
1460 | static struct table_elt * | |
ef4bddc2 | 1461 | lookup (rtx x, unsigned int hash, machine_mode mode) |
7afe21cc | 1462 | { |
b3694847 | 1463 | struct table_elt *p; |
7afe21cc RK |
1464 | |
1465 | for (p = table[hash]; p; p = p->next_same_hash) | |
f8cfc6aa | 1466 | if (mode == p->mode && ((x == p->exp && REG_P (x)) |
0516f6fe | 1467 | || exp_equiv_p (x, p->exp, !REG_P (x), false))) |
7afe21cc RK |
1468 | return p; |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | /* Like `lookup' but don't care whether the table element uses invalid regs. | |
1474 | Also ignore discrepancies in the machine mode of a register. */ | |
1475 | ||
1476 | static struct table_elt * | |
ef4bddc2 | 1477 | lookup_for_remove (rtx x, unsigned int hash, machine_mode mode) |
7afe21cc | 1478 | { |
b3694847 | 1479 | struct table_elt *p; |
7afe21cc | 1480 | |
f8cfc6aa | 1481 | if (REG_P (x)) |
7afe21cc | 1482 | { |
770ae6cc RK |
1483 | unsigned int regno = REGNO (x); |
1484 | ||
7afe21cc RK |
1485 | /* Don't check the machine mode when comparing registers; |
1486 | invalidating (REG:SI 0) also invalidates (REG:DF 0). */ | |
1487 | for (p = table[hash]; p; p = p->next_same_hash) | |
f8cfc6aa | 1488 | if (REG_P (p->exp) |
7afe21cc RK |
1489 | && REGNO (p->exp) == regno) |
1490 | return p; | |
1491 | } | |
1492 | else | |
1493 | { | |
1494 | for (p = table[hash]; p; p = p->next_same_hash) | |
0516f6fe SB |
1495 | if (mode == p->mode |
1496 | && (x == p->exp || exp_equiv_p (x, p->exp, 0, false))) | |
7afe21cc RK |
1497 | return p; |
1498 | } | |
1499 | ||
1500 | return 0; | |
1501 | } | |
1502 | ||
1503 | /* Look for an expression equivalent to X and with code CODE. | |
1504 | If one is found, return that expression. */ | |
1505 | ||
1506 | static rtx | |
7080f735 | 1507 | lookup_as_function (rtx x, enum rtx_code code) |
7afe21cc | 1508 | { |
b3694847 | 1509 | struct table_elt *p |
0516f6fe | 1510 | = lookup (x, SAFE_HASH (x, VOIDmode), GET_MODE (x)); |
770ae6cc | 1511 | |
7afe21cc RK |
1512 | if (p == 0) |
1513 | return 0; | |
1514 | ||
1515 | for (p = p->first_same_value; p; p = p->next_same_value) | |
770ae6cc RK |
1516 | if (GET_CODE (p->exp) == code |
1517 | /* Make sure this is a valid entry in the table. */ | |
0516f6fe | 1518 | && exp_equiv_p (p->exp, p->exp, 1, false)) |
770ae6cc | 1519 | return p->exp; |
278a83b2 | 1520 | |
7afe21cc RK |
1521 | return 0; |
1522 | } | |
1523 | ||
2c5bfdf7 AN |
1524 | /* Insert X in the hash table, assuming HASH is its hash code and |
1525 | CLASSP is an element of the class it should go in (or 0 if a new | |
1526 | class should be made). COST is the code of X and reg_cost is the | |
1527 | cost of registers in X. It is inserted at the proper position to | |
1528 | keep the class in the order cheapest first. | |
7afe21cc RK |
1529 | |
1530 | MODE is the machine-mode of X, or if X is an integer constant | |
1531 | with VOIDmode then MODE is the mode with which X will be used. | |
1532 | ||
1533 | For elements of equal cheapness, the most recent one | |
1534 | goes in front, except that the first element in the list | |
1535 | remains first unless a cheaper element is added. The order of | |
1536 | pseudo-registers does not matter, as canon_reg will be called to | |
830a38ee | 1537 | find the cheapest when a register is retrieved from the table. |
7afe21cc RK |
1538 | |
1539 | The in_memory field in the hash table element is set to 0. | |
1540 | The caller must set it nonzero if appropriate. | |
1541 | ||
1542 | You should call insert_regs (X, CLASSP, MODIFY) before calling here, | |
1543 | and if insert_regs returns a nonzero value | |
1544 | you must then recompute its hash code before calling here. | |
1545 | ||
1546 | If necessary, update table showing constant values of quantities. */ | |
1547 | ||
7afe21cc | 1548 | static struct table_elt * |
2c5bfdf7 | 1549 | insert_with_costs (rtx x, struct table_elt *classp, unsigned int hash, |
ef4bddc2 | 1550 | machine_mode mode, int cost, int reg_cost) |
7afe21cc | 1551 | { |
b3694847 | 1552 | struct table_elt *elt; |
7afe21cc RK |
1553 | |
1554 | /* If X is a register and we haven't made a quantity for it, | |
1555 | something is wrong. */ | |
341c100f | 1556 | gcc_assert (!REG_P (x) || REGNO_QTY_VALID_P (REGNO (x))); |
7afe21cc RK |
1557 | |
1558 | /* If X is a hard register, show it is being put in the table. */ | |
f8cfc6aa | 1559 | if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) |
09e18274 | 1560 | add_to_hard_reg_set (&hard_regs_in_table, GET_MODE (x), REGNO (x)); |
7afe21cc | 1561 | |
7afe21cc RK |
1562 | /* Put an element for X into the right hash bucket. */ |
1563 | ||
9b1549b8 DM |
1564 | elt = free_element_chain; |
1565 | if (elt) | |
770ae6cc | 1566 | free_element_chain = elt->next_same_hash; |
9b1549b8 | 1567 | else |
5ed6ace5 | 1568 | elt = XNEW (struct table_elt); |
9b1549b8 | 1569 | |
7afe21cc | 1570 | elt->exp = x; |
db048faf | 1571 | elt->canon_exp = NULL_RTX; |
2c5bfdf7 AN |
1572 | elt->cost = cost; |
1573 | elt->regcost = reg_cost; | |
7afe21cc RK |
1574 | elt->next_same_value = 0; |
1575 | elt->prev_same_value = 0; | |
1576 | elt->next_same_hash = table[hash]; | |
1577 | elt->prev_same_hash = 0; | |
1578 | elt->related_value = 0; | |
1579 | elt->in_memory = 0; | |
1580 | elt->mode = mode; | |
389fdba0 | 1581 | elt->is_const = (CONSTANT_P (x) || fixed_base_plus_p (x)); |
7afe21cc RK |
1582 | |
1583 | if (table[hash]) | |
1584 | table[hash]->prev_same_hash = elt; | |
1585 | table[hash] = elt; | |
1586 | ||
1587 | /* Put it into the proper value-class. */ | |
1588 | if (classp) | |
1589 | { | |
1590 | classp = classp->first_same_value; | |
1591 | if (CHEAPER (elt, classp)) | |
f9da5064 | 1592 | /* Insert at the head of the class. */ |
7afe21cc | 1593 | { |
b3694847 | 1594 | struct table_elt *p; |
7afe21cc RK |
1595 | elt->next_same_value = classp; |
1596 | classp->prev_same_value = elt; | |
1597 | elt->first_same_value = elt; | |
1598 | ||
1599 | for (p = classp; p; p = p->next_same_value) | |
1600 | p->first_same_value = elt; | |
1601 | } | |
1602 | else | |
1603 | { | |
1604 | /* Insert not at head of the class. */ | |
1605 | /* Put it after the last element cheaper than X. */ | |
b3694847 | 1606 | struct table_elt *p, *next; |
770ae6cc | 1607 | |
e84a58ff EB |
1608 | for (p = classp; |
1609 | (next = p->next_same_value) && CHEAPER (next, elt); | |
1610 | p = next) | |
1611 | ; | |
770ae6cc | 1612 | |
7afe21cc RK |
1613 | /* Put it after P and before NEXT. */ |
1614 | elt->next_same_value = next; | |
1615 | if (next) | |
1616 | next->prev_same_value = elt; | |
770ae6cc | 1617 | |
7afe21cc RK |
1618 | elt->prev_same_value = p; |
1619 | p->next_same_value = elt; | |
1620 | elt->first_same_value = classp; | |
1621 | } | |
1622 | } | |
1623 | else | |
1624 | elt->first_same_value = elt; | |
1625 | ||
1626 | /* If this is a constant being set equivalent to a register or a register | |
1627 | being set equivalent to a constant, note the constant equivalence. | |
1628 | ||
1629 | If this is a constant, it cannot be equivalent to a different constant, | |
1630 | and a constant is the only thing that can be cheaper than a register. So | |
1631 | we know the register is the head of the class (before the constant was | |
1632 | inserted). | |
1633 | ||
1634 | If this is a register that is not already known equivalent to a | |
1635 | constant, we must check the entire class. | |
1636 | ||
1637 | If this is a register that is already known equivalent to an insn, | |
1bb98cec | 1638 | update the qtys `const_insn' to show that `this_insn' is the latest |
7afe21cc RK |
1639 | insn making that quantity equivalent to the constant. */ |
1640 | ||
f8cfc6aa JQ |
1641 | if (elt->is_const && classp && REG_P (classp->exp) |
1642 | && !REG_P (x)) | |
7afe21cc | 1643 | { |
1bb98cec DM |
1644 | int exp_q = REG_QTY (REGNO (classp->exp)); |
1645 | struct qty_table_elem *exp_ent = &qty_table[exp_q]; | |
1646 | ||
4de249d9 | 1647 | exp_ent->const_rtx = gen_lowpart (exp_ent->mode, x); |
1bb98cec | 1648 | exp_ent->const_insn = this_insn; |
7afe21cc RK |
1649 | } |
1650 | ||
f8cfc6aa | 1651 | else if (REG_P (x) |
1bb98cec DM |
1652 | && classp |
1653 | && ! qty_table[REG_QTY (REGNO (x))].const_rtx | |
f353588a | 1654 | && ! elt->is_const) |
7afe21cc | 1655 | { |
b3694847 | 1656 | struct table_elt *p; |
7afe21cc RK |
1657 | |
1658 | for (p = classp; p != 0; p = p->next_same_value) | |
1659 | { | |
f8cfc6aa | 1660 | if (p->is_const && !REG_P (p->exp)) |
7afe21cc | 1661 | { |
1bb98cec DM |
1662 | int x_q = REG_QTY (REGNO (x)); |
1663 | struct qty_table_elem *x_ent = &qty_table[x_q]; | |
1664 | ||
770ae6cc | 1665 | x_ent->const_rtx |
4de249d9 | 1666 | = gen_lowpart (GET_MODE (x), p->exp); |
1bb98cec | 1667 | x_ent->const_insn = this_insn; |
7afe21cc RK |
1668 | break; |
1669 | } | |
1670 | } | |
1671 | } | |
1672 | ||
f8cfc6aa | 1673 | else if (REG_P (x) |
1bb98cec DM |
1674 | && qty_table[REG_QTY (REGNO (x))].const_rtx |
1675 | && GET_MODE (x) == qty_table[REG_QTY (REGNO (x))].mode) | |
1676 | qty_table[REG_QTY (REGNO (x))].const_insn = this_insn; | |
7afe21cc RK |
1677 | |
1678 | /* If this is a constant with symbolic value, | |
1679 | and it has a term with an explicit integer value, | |
1680 | link it up with related expressions. */ | |
1681 | if (GET_CODE (x) == CONST) | |
1682 | { | |
1683 | rtx subexp = get_related_value (x); | |
2197a88a | 1684 | unsigned subhash; |
7afe21cc RK |
1685 | struct table_elt *subelt, *subelt_prev; |
1686 | ||
1687 | if (subexp != 0) | |
1688 | { | |
1689 | /* Get the integer-free subexpression in the hash table. */ | |
0516f6fe | 1690 | subhash = SAFE_HASH (subexp, mode); |
7afe21cc RK |
1691 | subelt = lookup (subexp, subhash, mode); |
1692 | if (subelt == 0) | |
9714cf43 | 1693 | subelt = insert (subexp, NULL, subhash, mode); |
7afe21cc RK |
1694 | /* Initialize SUBELT's circular chain if it has none. */ |
1695 | if (subelt->related_value == 0) | |
1696 | subelt->related_value = subelt; | |
1697 | /* Find the element in the circular chain that precedes SUBELT. */ | |
1698 | subelt_prev = subelt; | |
1699 | while (subelt_prev->related_value != subelt) | |
1700 | subelt_prev = subelt_prev->related_value; | |
1701 | /* Put new ELT into SUBELT's circular chain just before SUBELT. | |
1702 | This way the element that follows SUBELT is the oldest one. */ | |
1703 | elt->related_value = subelt_prev->related_value; | |
1704 | subelt_prev->related_value = elt; | |
1705 | } | |
1706 | } | |
1707 | ||
1708 | return elt; | |
1709 | } | |
2c5bfdf7 AN |
1710 | |
1711 | /* Wrap insert_with_costs by passing the default costs. */ | |
1712 | ||
1713 | static struct table_elt * | |
1714 | insert (rtx x, struct table_elt *classp, unsigned int hash, | |
ef4bddc2 | 1715 | machine_mode mode) |
2c5bfdf7 | 1716 | { |
e548c9df AM |
1717 | return insert_with_costs (x, classp, hash, mode, |
1718 | COST (x, mode), approx_reg_cost (x)); | |
2c5bfdf7 AN |
1719 | } |
1720 | ||
7afe21cc RK |
1721 | \f |
1722 | /* Given two equivalence classes, CLASS1 and CLASS2, put all the entries from | |
1723 | CLASS2 into CLASS1. This is done when we have reached an insn which makes | |
1724 | the two classes equivalent. | |
1725 | ||
1726 | CLASS1 will be the surviving class; CLASS2 should not be used after this | |
1727 | call. | |
1728 | ||
1729 | Any invalid entries in CLASS2 will not be copied. */ | |
1730 | ||
1731 | static void | |
7080f735 | 1732 | merge_equiv_classes (struct table_elt *class1, struct table_elt *class2) |
7afe21cc | 1733 | { |
32e9fa48 | 1734 | struct table_elt *elt, *next, *new_elt; |
7afe21cc RK |
1735 | |
1736 | /* Ensure we start with the head of the classes. */ | |
1737 | class1 = class1->first_same_value; | |
1738 | class2 = class2->first_same_value; | |
1739 | ||
1740 | /* If they were already equal, forget it. */ | |
1741 | if (class1 == class2) | |
1742 | return; | |
1743 | ||
1744 | for (elt = class2; elt; elt = next) | |
1745 | { | |
770ae6cc | 1746 | unsigned int hash; |
7afe21cc | 1747 | rtx exp = elt->exp; |
ef4bddc2 | 1748 | machine_mode mode = elt->mode; |
7afe21cc RK |
1749 | |
1750 | next = elt->next_same_value; | |
1751 | ||
1752 | /* Remove old entry, make a new one in CLASS1's class. | |
1753 | Don't do this for invalid entries as we cannot find their | |
0f41302f | 1754 | hash code (it also isn't necessary). */ |
0516f6fe | 1755 | if (REG_P (exp) || exp_equiv_p (exp, exp, 1, false)) |
7afe21cc | 1756 | { |
a90fc8e0 RH |
1757 | bool need_rehash = false; |
1758 | ||
7afe21cc | 1759 | hash_arg_in_memory = 0; |
7afe21cc | 1760 | hash = HASH (exp, mode); |
278a83b2 | 1761 | |
f8cfc6aa | 1762 | if (REG_P (exp)) |
a90fc8e0 | 1763 | { |
08a69267 | 1764 | need_rehash = REGNO_QTY_VALID_P (REGNO (exp)); |
a90fc8e0 RH |
1765 | delete_reg_equiv (REGNO (exp)); |
1766 | } | |
278a83b2 | 1767 | |
d556d181 EB |
1768 | if (REG_P (exp) && REGNO (exp) >= FIRST_PSEUDO_REGISTER) |
1769 | remove_pseudo_from_table (exp, hash); | |
1770 | else | |
1771 | remove_from_table (elt, hash); | |
7afe21cc | 1772 | |
a90fc8e0 | 1773 | if (insert_regs (exp, class1, 0) || need_rehash) |
8ae2b8f6 JW |
1774 | { |
1775 | rehash_using_reg (exp); | |
1776 | hash = HASH (exp, mode); | |
1777 | } | |
32e9fa48 KG |
1778 | new_elt = insert (exp, class1, hash, mode); |
1779 | new_elt->in_memory = hash_arg_in_memory; | |
6c4d60f8 JJ |
1780 | if (GET_CODE (exp) == ASM_OPERANDS && elt->cost == MAX_COST) |
1781 | new_elt->cost = MAX_COST; | |
7afe21cc RK |
1782 | } |
1783 | } | |
1784 | } | |
1785 | \f | |
01e752d3 JL |
1786 | /* Flush the entire hash table. */ |
1787 | ||
1788 | static void | |
7080f735 | 1789 | flush_hash_table (void) |
01e752d3 JL |
1790 | { |
1791 | int i; | |
1792 | struct table_elt *p; | |
1793 | ||
9b1549b8 | 1794 | for (i = 0; i < HASH_SIZE; i++) |
01e752d3 JL |
1795 | for (p = table[i]; p; p = table[i]) |
1796 | { | |
1797 | /* Note that invalidate can remove elements | |
1798 | after P in the current hash chain. */ | |
f8cfc6aa | 1799 | if (REG_P (p->exp)) |
524e3576 | 1800 | invalidate (p->exp, VOIDmode); |
01e752d3 JL |
1801 | else |
1802 | remove_from_table (p, i); | |
1803 | } | |
1804 | } | |
14a774a9 | 1805 | \f |
c992c066 RS |
1806 | /* Check whether an anti dependence exists between X and EXP. MODE and |
1807 | ADDR are as for canon_anti_dependence. */ | |
be8ac49a | 1808 | |
c992c066 | 1809 | static bool |
ef4bddc2 | 1810 | check_dependence (const_rtx x, rtx exp, machine_mode mode, rtx addr) |
2ce6dc2f | 1811 | { |
c992c066 RS |
1812 | subrtx_iterator::array_type array; |
1813 | FOR_EACH_SUBRTX (iter, array, x, NONCONST) | |
1814 | { | |
1815 | const_rtx x = *iter; | |
1816 | if (MEM_P (x) && canon_anti_dependence (x, true, exp, mode, addr)) | |
1817 | return true; | |
1818 | } | |
1819 | return false; | |
2ce6dc2f | 1820 | } |
99788e06 AH |
1821 | |
1822 | /* Remove from the hash table, or mark as invalid, all expressions whose | |
17d184e5 | 1823 | values could be altered by storing in register X. */ |
99788e06 AH |
1824 | |
1825 | static void | |
17d184e5 | 1826 | invalidate_reg (rtx x) |
99788e06 AH |
1827 | { |
1828 | gcc_assert (GET_CODE (x) == REG); | |
1829 | ||
1830 | /* If X is a register, dependencies on its contents are recorded | |
1831 | through the qty number mechanism. Just change the qty number of | |
1832 | the register, mark it as invalid for expressions that refer to it, | |
1833 | and remove it itself. */ | |
1834 | unsigned int regno = REGNO (x); | |
1835 | unsigned int hash = HASH (x, GET_MODE (x)); | |
1836 | ||
1837 | /* Remove REGNO from any quantity list it might be on and indicate | |
1838 | that its value might have changed. If it is a pseudo, remove its | |
1839 | entry from the hash table. | |
1840 | ||
1841 | For a hard register, we do the first two actions above for any | |
1842 | additional hard registers corresponding to X. Then, if any of these | |
1843 | registers are in the table, we must remove any REG entries that | |
1844 | overlap these registers. */ | |
1845 | ||
1846 | delete_reg_equiv (regno); | |
1847 | REG_TICK (regno)++; | |
1848 | SUBREG_TICKED (regno) = -1; | |
1849 | ||
1850 | if (regno >= FIRST_PSEUDO_REGISTER) | |
17d184e5 | 1851 | remove_pseudo_from_table (x, hash); |
99788e06 AH |
1852 | else |
1853 | { | |
1854 | HOST_WIDE_INT in_table = TEST_HARD_REG_BIT (hard_regs_in_table, regno); | |
1855 | unsigned int endregno = END_REGNO (x); | |
1856 | unsigned int rn; | |
1857 | struct table_elt *p, *next; | |
1858 | ||
1859 | CLEAR_HARD_REG_BIT (hard_regs_in_table, regno); | |
1860 | ||
1861 | for (rn = regno + 1; rn < endregno; rn++) | |
1862 | { | |
1863 | in_table |= TEST_HARD_REG_BIT (hard_regs_in_table, rn); | |
1864 | CLEAR_HARD_REG_BIT (hard_regs_in_table, rn); | |
1865 | delete_reg_equiv (rn); | |
1866 | REG_TICK (rn)++; | |
1867 | SUBREG_TICKED (rn) = -1; | |
1868 | } | |
1869 | ||
1870 | if (in_table) | |
1871 | for (hash = 0; hash < HASH_SIZE; hash++) | |
1872 | for (p = table[hash]; p; p = next) | |
1873 | { | |
1874 | next = p->next_same_hash; | |
1875 | ||
1876 | if (!REG_P (p->exp) || REGNO (p->exp) >= FIRST_PSEUDO_REGISTER) | |
1877 | continue; | |
1878 | ||
17d184e5 RS |
1879 | unsigned int tregno = REGNO (p->exp); |
1880 | unsigned int tendregno = END_REGNO (p->exp); | |
1881 | if (tendregno > regno && tregno < endregno) | |
1882 | remove_from_table (p, hash); | |
99788e06 AH |
1883 | } |
1884 | } | |
1885 | } | |
1886 | ||
14a774a9 RK |
1887 | /* Remove from the hash table, or mark as invalid, all expressions whose |
1888 | values could be altered by storing in X. X is a register, a subreg, or | |
1889 | a memory reference with nonvarying address (because, when a memory | |
1890 | reference with a varying address is stored in, all memory references are | |
1891 | removed by invalidate_memory so specific invalidation is superfluous). | |
1892 | FULL_MODE, if not VOIDmode, indicates that this much should be | |
1893 | invalidated instead of just the amount indicated by the mode of X. This | |
1894 | is only used for bitfield stores into memory. | |
1895 | ||
1896 | A nonvarying address may be just a register or just a symbol reference, | |
1897 | or it may be either of those plus a numeric offset. */ | |
7afe21cc RK |
1898 | |
1899 | static void | |
ef4bddc2 | 1900 | invalidate (rtx x, machine_mode full_mode) |
7afe21cc | 1901 | { |
b3694847 SS |
1902 | int i; |
1903 | struct table_elt *p; | |
9ddb66ca | 1904 | rtx addr; |
7afe21cc | 1905 | |
14a774a9 | 1906 | switch (GET_CODE (x)) |
7afe21cc | 1907 | { |
14a774a9 | 1908 | case REG: |
17d184e5 | 1909 | invalidate_reg (x); |
7afe21cc | 1910 | return; |
7afe21cc | 1911 | |
14a774a9 | 1912 | case SUBREG: |
bb4034b3 | 1913 | invalidate (SUBREG_REG (x), VOIDmode); |
7afe21cc | 1914 | return; |
aac5cc16 | 1915 | |
14a774a9 | 1916 | case PARALLEL: |
278a83b2 | 1917 | for (i = XVECLEN (x, 0) - 1; i >= 0; --i) |
aac5cc16 RH |
1918 | invalidate (XVECEXP (x, 0, i), VOIDmode); |
1919 | return; | |
aac5cc16 | 1920 | |
14a774a9 RK |
1921 | case EXPR_LIST: |
1922 | /* This is part of a disjoint return value; extract the location in | |
1923 | question ignoring the offset. */ | |
aac5cc16 RH |
1924 | invalidate (XEXP (x, 0), VOIDmode); |
1925 | return; | |
7afe21cc | 1926 | |
14a774a9 | 1927 | case MEM: |
9ddb66ca | 1928 | addr = canon_rtx (get_addr (XEXP (x, 0))); |
db048faf MM |
1929 | /* Calculate the canonical version of X here so that |
1930 | true_dependence doesn't generate new RTL for X on each call. */ | |
1931 | x = canon_rtx (x); | |
1932 | ||
14a774a9 RK |
1933 | /* Remove all hash table elements that refer to overlapping pieces of |
1934 | memory. */ | |
1935 | if (full_mode == VOIDmode) | |
1936 | full_mode = GET_MODE (x); | |
bb4034b3 | 1937 | |
9b1549b8 | 1938 | for (i = 0; i < HASH_SIZE; i++) |
7afe21cc | 1939 | { |
b3694847 | 1940 | struct table_elt *next; |
14a774a9 RK |
1941 | |
1942 | for (p = table[i]; p; p = next) | |
1943 | { | |
1944 | next = p->next_same_hash; | |
db048faf MM |
1945 | if (p->in_memory) |
1946 | { | |
2ce6dc2f JH |
1947 | /* Just canonicalize the expression once; |
1948 | otherwise each time we call invalidate | |
1949 | true_dependence will canonicalize the | |
1950 | expression again. */ | |
1951 | if (!p->canon_exp) | |
1952 | p->canon_exp = canon_rtx (p->exp); | |
c992c066 | 1953 | if (check_dependence (p->canon_exp, x, full_mode, addr)) |
db048faf | 1954 | remove_from_table (p, i); |
db048faf | 1955 | } |
14a774a9 | 1956 | } |
7afe21cc | 1957 | } |
14a774a9 RK |
1958 | return; |
1959 | ||
1960 | default: | |
341c100f | 1961 | gcc_unreachable (); |
7afe21cc RK |
1962 | } |
1963 | } | |
2a1d78d8 JJ |
1964 | |
1965 | /* Invalidate DEST. Used when DEST is not going to be added | |
1966 | into the hash table for some reason, e.g. do_not_record | |
1967 | flagged on it. */ | |
1968 | ||
1969 | static void | |
1970 | invalidate_dest (rtx dest) | |
1971 | { | |
1972 | if (REG_P (dest) | |
1973 | || GET_CODE (dest) == SUBREG | |
1974 | || MEM_P (dest)) | |
1975 | invalidate (dest, VOIDmode); | |
1976 | else if (GET_CODE (dest) == STRICT_LOW_PART | |
1977 | || GET_CODE (dest) == ZERO_EXTRACT) | |
1978 | invalidate (XEXP (dest, 0), GET_MODE (dest)); | |
1979 | } | |
14a774a9 | 1980 | \f |
7afe21cc RK |
1981 | /* Remove all expressions that refer to register REGNO, |
1982 | since they are already invalid, and we are about to | |
1983 | mark that register valid again and don't want the old | |
1984 | expressions to reappear as valid. */ | |
1985 | ||
1986 | static void | |
7080f735 | 1987 | remove_invalid_refs (unsigned int regno) |
7afe21cc | 1988 | { |
770ae6cc RK |
1989 | unsigned int i; |
1990 | struct table_elt *p, *next; | |
7afe21cc | 1991 | |
9b1549b8 | 1992 | for (i = 0; i < HASH_SIZE; i++) |
7afe21cc RK |
1993 | for (p = table[i]; p; p = next) |
1994 | { | |
1995 | next = p->next_same_hash; | |
c9bd6bcd | 1996 | if (!REG_P (p->exp) && refers_to_regno_p (regno, p->exp)) |
7afe21cc RK |
1997 | remove_from_table (p, i); |
1998 | } | |
1999 | } | |
34c73909 | 2000 | |
ddef6bc7 JJ |
2001 | /* Likewise for a subreg with subreg_reg REGNO, subreg_byte OFFSET, |
2002 | and mode MODE. */ | |
34c73909 | 2003 | static void |
91914e56 | 2004 | remove_invalid_subreg_refs (unsigned int regno, poly_uint64 offset, |
ef4bddc2 | 2005 | machine_mode mode) |
34c73909 | 2006 | { |
770ae6cc RK |
2007 | unsigned int i; |
2008 | struct table_elt *p, *next; | |
34c73909 | 2009 | |
9b1549b8 | 2010 | for (i = 0; i < HASH_SIZE; i++) |
34c73909 R |
2011 | for (p = table[i]; p; p = next) |
2012 | { | |
ddef6bc7 | 2013 | rtx exp = p->exp; |
34c73909 | 2014 | next = p->next_same_hash; |
278a83b2 | 2015 | |
f8cfc6aa | 2016 | if (!REG_P (exp) |
34c73909 | 2017 | && (GET_CODE (exp) != SUBREG |
f8cfc6aa | 2018 | || !REG_P (SUBREG_REG (exp)) |
34c73909 | 2019 | || REGNO (SUBREG_REG (exp)) != regno |
91914e56 RS |
2020 | || ranges_maybe_overlap_p (SUBREG_BYTE (exp), |
2021 | GET_MODE_SIZE (GET_MODE (exp)), | |
2022 | offset, GET_MODE_SIZE (mode))) | |
c9bd6bcd | 2023 | && refers_to_regno_p (regno, p->exp)) |
34c73909 R |
2024 | remove_from_table (p, i); |
2025 | } | |
2026 | } | |
7afe21cc RK |
2027 | \f |
2028 | /* Recompute the hash codes of any valid entries in the hash table that | |
2029 | reference X, if X is a register, or SUBREG_REG (X) if X is a SUBREG. | |
2030 | ||
2031 | This is called when we make a jump equivalence. */ | |
2032 | ||
2033 | static void | |
7080f735 | 2034 | rehash_using_reg (rtx x) |
7afe21cc | 2035 | { |
973838fd | 2036 | unsigned int i; |
7afe21cc | 2037 | struct table_elt *p, *next; |
2197a88a | 2038 | unsigned hash; |
7afe21cc RK |
2039 | |
2040 | if (GET_CODE (x) == SUBREG) | |
2041 | x = SUBREG_REG (x); | |
2042 | ||
2043 | /* If X is not a register or if the register is known not to be in any | |
2044 | valid entries in the table, we have no work to do. */ | |
2045 | ||
f8cfc6aa | 2046 | if (!REG_P (x) |
30f72379 MM |
2047 | || REG_IN_TABLE (REGNO (x)) < 0 |
2048 | || REG_IN_TABLE (REGNO (x)) != REG_TICK (REGNO (x))) | |
7afe21cc RK |
2049 | return; |
2050 | ||
2051 | /* Scan all hash chains looking for valid entries that mention X. | |
a90fc8e0 | 2052 | If we find one and it is in the wrong hash chain, move it. */ |
7afe21cc | 2053 | |
9b1549b8 | 2054 | for (i = 0; i < HASH_SIZE; i++) |
7afe21cc RK |
2055 | for (p = table[i]; p; p = next) |
2056 | { | |
2057 | next = p->next_same_hash; | |
a90fc8e0 | 2058 | if (reg_mentioned_p (x, p->exp) |
0516f6fe SB |
2059 | && exp_equiv_p (p->exp, p->exp, 1, false) |
2060 | && i != (hash = SAFE_HASH (p->exp, p->mode))) | |
7afe21cc RK |
2061 | { |
2062 | if (p->next_same_hash) | |
2063 | p->next_same_hash->prev_same_hash = p->prev_same_hash; | |
2064 | ||
2065 | if (p->prev_same_hash) | |
2066 | p->prev_same_hash->next_same_hash = p->next_same_hash; | |
2067 | else | |
2068 | table[i] = p->next_same_hash; | |
2069 | ||
2070 | p->next_same_hash = table[hash]; | |
2071 | p->prev_same_hash = 0; | |
2072 | if (table[hash]) | |
2073 | table[hash]->prev_same_hash = p; | |
2074 | table[hash] = p; | |
2075 | } | |
2076 | } | |
2077 | } | |
2078 | \f | |
7afe21cc | 2079 | /* Remove from the hash table any expression that is a call-clobbered |
311b62ce | 2080 | register in INSN. Also update their TICK values. */ |
7afe21cc RK |
2081 | |
2082 | static void | |
311b62ce | 2083 | invalidate_for_call (rtx_insn *insn) |
7afe21cc | 2084 | { |
311b62ce | 2085 | unsigned int regno; |
2197a88a | 2086 | unsigned hash; |
7afe21cc RK |
2087 | struct table_elt *p, *next; |
2088 | int in_table = 0; | |
c7fb4c7a | 2089 | hard_reg_set_iterator hrsi; |
7afe21cc | 2090 | |
311b62ce RS |
2091 | /* Go through all the hard registers. For each that might be clobbered |
2092 | in call insn INSN, remove the register from quantity chains and update | |
7afe21cc | 2093 | reg_tick if defined. Also see if any of these registers is currently |
311b62ce RS |
2094 | in the table. |
2095 | ||
2096 | ??? We could be more precise for partially-clobbered registers, | |
2097 | and only invalidate values that actually occupy the clobbered part | |
2098 | of the registers. It doesn't seem worth the effort though, since | |
2099 | we shouldn't see this situation much before RA. Whatever choice | |
2100 | we make here has to be consistent with the table walk below, | |
2101 | so any change to this test will require a change there too. */ | |
2102 | HARD_REG_SET callee_clobbers | |
2103 | = insn_callee_abi (insn).full_and_partial_reg_clobbers (); | |
2104 | EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers, 0, regno, hrsi) | |
c7fb4c7a SB |
2105 | { |
2106 | delete_reg_equiv (regno); | |
2107 | if (REG_TICK (regno) >= 0) | |
2108 | { | |
2109 | REG_TICK (regno)++; | |
2110 | SUBREG_TICKED (regno) = -1; | |
2111 | } | |
2112 | in_table |= (TEST_HARD_REG_BIT (hard_regs_in_table, regno) != 0); | |
2113 | } | |
7afe21cc RK |
2114 | |
2115 | /* In the case where we have no call-clobbered hard registers in the | |
2116 | table, we are done. Otherwise, scan the table and remove any | |
2117 | entry that overlaps a call-clobbered register. */ | |
2118 | ||
2119 | if (in_table) | |
9b1549b8 | 2120 | for (hash = 0; hash < HASH_SIZE; hash++) |
7afe21cc RK |
2121 | for (p = table[hash]; p; p = next) |
2122 | { | |
2123 | next = p->next_same_hash; | |
2124 | ||
f8cfc6aa | 2125 | if (!REG_P (p->exp) |
7afe21cc RK |
2126 | || REGNO (p->exp) >= FIRST_PSEUDO_REGISTER) |
2127 | continue; | |
2128 | ||
311b62ce RS |
2129 | /* This must use the same test as above rather than the |
2130 | more accurate clobbers_reg_p. */ | |
2131 | if (overlaps_hard_reg_set_p (callee_clobbers, GET_MODE (p->exp), | |
2132 | REGNO (p->exp))) | |
2133 | remove_from_table (p, hash); | |
7afe21cc RK |
2134 | } |
2135 | } | |
2136 | \f | |
2137 | /* Given an expression X of type CONST, | |
2138 | and ELT which is its table entry (or 0 if it | |
2139 | is not in the hash table), | |
2140 | return an alternate expression for X as a register plus integer. | |
2141 | If none can be found, return 0. */ | |
2142 | ||
2143 | static rtx | |
7080f735 | 2144 | use_related_value (rtx x, struct table_elt *elt) |
7afe21cc | 2145 | { |
b3694847 SS |
2146 | struct table_elt *relt = 0; |
2147 | struct table_elt *p, *q; | |
906c4e36 | 2148 | HOST_WIDE_INT offset; |
7afe21cc RK |
2149 | |
2150 | /* First, is there anything related known? | |
2151 | If we have a table element, we can tell from that. | |
2152 | Otherwise, must look it up. */ | |
2153 | ||
2154 | if (elt != 0 && elt->related_value != 0) | |
2155 | relt = elt; | |
2156 | else if (elt == 0 && GET_CODE (x) == CONST) | |
2157 | { | |
2158 | rtx subexp = get_related_value (x); | |
2159 | if (subexp != 0) | |
2160 | relt = lookup (subexp, | |
0516f6fe | 2161 | SAFE_HASH (subexp, GET_MODE (subexp)), |
7afe21cc RK |
2162 | GET_MODE (subexp)); |
2163 | } | |
2164 | ||
2165 | if (relt == 0) | |
2166 | return 0; | |
2167 | ||
2168 | /* Search all related table entries for one that has an | |
2169 | equivalent register. */ | |
2170 | ||
2171 | p = relt; | |
2172 | while (1) | |
2173 | { | |
2174 | /* This loop is strange in that it is executed in two different cases. | |
2175 | The first is when X is already in the table. Then it is searching | |
2176 | the RELATED_VALUE list of X's class (RELT). The second case is when | |
2177 | X is not in the table. Then RELT points to a class for the related | |
2178 | value. | |
2179 | ||
2180 | Ensure that, whatever case we are in, that we ignore classes that have | |
2181 | the same value as X. */ | |
2182 | ||
2183 | if (rtx_equal_p (x, p->exp)) | |
2184 | q = 0; | |
2185 | else | |
2186 | for (q = p->first_same_value; q; q = q->next_same_value) | |
f8cfc6aa | 2187 | if (REG_P (q->exp)) |
7afe21cc RK |
2188 | break; |
2189 | ||
2190 | if (q) | |
2191 | break; | |
2192 | ||
2193 | p = p->related_value; | |
2194 | ||
2195 | /* We went all the way around, so there is nothing to be found. | |
2196 | Alternatively, perhaps RELT was in the table for some other reason | |
2197 | and it has no related values recorded. */ | |
2198 | if (p == relt || p == 0) | |
2199 | break; | |
2200 | } | |
2201 | ||
2202 | if (q == 0) | |
2203 | return 0; | |
2204 | ||
2205 | offset = (get_integer_term (x) - get_integer_term (p->exp)); | |
2206 | /* Note: OFFSET may be 0 if P->xexp and X are related by commutativity. */ | |
0a81f074 | 2207 | return plus_constant (q->mode, q->exp, offset); |
7afe21cc RK |
2208 | } |
2209 | \f | |
e855c69d | 2210 | |
6462bb43 AO |
2211 | /* Hash a string. Just add its bytes up. */ |
2212 | static inline unsigned | |
0516f6fe | 2213 | hash_rtx_string (const char *ps) |
6462bb43 AO |
2214 | { |
2215 | unsigned hash = 0; | |
68252e27 KH |
2216 | const unsigned char *p = (const unsigned char *) ps; |
2217 | ||
6462bb43 AO |
2218 | if (p) |
2219 | while (*p) | |
2220 | hash += *p++; | |
2221 | ||
2222 | return hash; | |
2223 | } | |
2224 | ||
b8698a0f | 2225 | /* Same as hash_rtx, but call CB on each rtx if it is not NULL. |
e855c69d | 2226 | When the callback returns true, we continue with the new rtx. */ |
7afe21cc | 2227 | |
0516f6fe | 2228 | unsigned |
ef4bddc2 | 2229 | hash_rtx_cb (const_rtx x, machine_mode mode, |
e855c69d AB |
2230 | int *do_not_record_p, int *hash_arg_in_memory_p, |
2231 | bool have_reg_qty, hash_rtx_callback_function cb) | |
7afe21cc | 2232 | { |
b3694847 SS |
2233 | int i, j; |
2234 | unsigned hash = 0; | |
2235 | enum rtx_code code; | |
2236 | const char *fmt; | |
ef4bddc2 | 2237 | machine_mode newmode; |
e855c69d | 2238 | rtx newx; |
7afe21cc | 2239 | |
0516f6fe SB |
2240 | /* Used to turn recursion into iteration. We can't rely on GCC's |
2241 | tail-recursion elimination since we need to keep accumulating values | |
2242 | in HASH. */ | |
7afe21cc RK |
2243 | repeat: |
2244 | if (x == 0) | |
2245 | return hash; | |
2246 | ||
e855c69d | 2247 | /* Invoke the callback first. */ |
b8698a0f | 2248 | if (cb != NULL |
e855c69d AB |
2249 | && ((*cb) (x, mode, &newx, &newmode))) |
2250 | { | |
2251 | hash += hash_rtx_cb (newx, newmode, do_not_record_p, | |
2252 | hash_arg_in_memory_p, have_reg_qty, cb); | |
2253 | return hash; | |
2254 | } | |
2255 | ||
7afe21cc RK |
2256 | code = GET_CODE (x); |
2257 | switch (code) | |
2258 | { | |
2259 | case REG: | |
2260 | { | |
770ae6cc | 2261 | unsigned int regno = REGNO (x); |
7afe21cc | 2262 | |
e855c69d | 2263 | if (do_not_record_p && !reload_completed) |
7afe21cc | 2264 | { |
0516f6fe SB |
2265 | /* On some machines, we can't record any non-fixed hard register, |
2266 | because extending its life will cause reload problems. We | |
2267 | consider ap, fp, sp, gp to be fixed for this purpose. | |
2268 | ||
2269 | We also consider CCmode registers to be fixed for this purpose; | |
2270 | failure to do so leads to failure to simplify 0<100 type of | |
2271 | conditionals. | |
2272 | ||
2273 | On all machines, we can't record any global registers. | |
2274 | Nor should we record any register that is in a small | |
07b8f0a8 | 2275 | class, as defined by TARGET_CLASS_LIKELY_SPILLED_P. */ |
0516f6fe SB |
2276 | bool record; |
2277 | ||
2278 | if (regno >= FIRST_PSEUDO_REGISTER) | |
2279 | record = true; | |
2280 | else if (x == frame_pointer_rtx | |
2281 | || x == hard_frame_pointer_rtx | |
2282 | || x == arg_pointer_rtx | |
2283 | || x == stack_pointer_rtx | |
2284 | || x == pic_offset_table_rtx) | |
2285 | record = true; | |
2286 | else if (global_regs[regno]) | |
2287 | record = false; | |
2288 | else if (fixed_regs[regno]) | |
2289 | record = true; | |
2290 | else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) | |
2291 | record = true; | |
42db504c | 2292 | else if (targetm.small_register_classes_for_mode_p (GET_MODE (x))) |
0516f6fe | 2293 | record = false; |
07b8f0a8 | 2294 | else if (targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno))) |
0516f6fe SB |
2295 | record = false; |
2296 | else | |
2297 | record = true; | |
2298 | ||
2299 | if (!record) | |
2300 | { | |
2301 | *do_not_record_p = 1; | |
2302 | return 0; | |
2303 | } | |
7afe21cc | 2304 | } |
770ae6cc | 2305 | |
0516f6fe SB |
2306 | hash += ((unsigned int) REG << 7); |
2307 | hash += (have_reg_qty ? (unsigned) REG_QTY (regno) : regno); | |
2197a88a | 2308 | return hash; |
7afe21cc RK |
2309 | } |
2310 | ||
34c73909 R |
2311 | /* We handle SUBREG of a REG specially because the underlying |
2312 | reg changes its hash value with every value change; we don't | |
2313 | want to have to forget unrelated subregs when one subreg changes. */ | |
2314 | case SUBREG: | |
2315 | { | |
f8cfc6aa | 2316 | if (REG_P (SUBREG_REG (x))) |
34c73909 | 2317 | { |
0516f6fe | 2318 | hash += (((unsigned int) SUBREG << 7) |
ddef6bc7 | 2319 | + REGNO (SUBREG_REG (x)) |
91914e56 RS |
2320 | + (constant_lower_bound (SUBREG_BYTE (x)) |
2321 | / UNITS_PER_WORD)); | |
34c73909 R |
2322 | return hash; |
2323 | } | |
2324 | break; | |
2325 | } | |
2326 | ||
7afe21cc | 2327 | case CONST_INT: |
0516f6fe SB |
2328 | hash += (((unsigned int) CONST_INT << 7) + (unsigned int) mode |
2329 | + (unsigned int) INTVAL (x)); | |
2330 | return hash; | |
7afe21cc | 2331 | |
807e902e KZ |
2332 | case CONST_WIDE_INT: |
2333 | for (i = 0; i < CONST_WIDE_INT_NUNITS (x); i++) | |
2334 | hash += CONST_WIDE_INT_ELT (x, i); | |
2335 | return hash; | |
2336 | ||
0c12fc9b RS |
2337 | case CONST_POLY_INT: |
2338 | { | |
2339 | inchash::hash h; | |
2340 | h.add_int (hash); | |
2341 | for (unsigned int i = 0; i < NUM_POLY_INT_COEFFS; ++i) | |
2342 | h.add_wide_int (CONST_POLY_INT_COEFFS (x)[i]); | |
2343 | return h.end (); | |
2344 | } | |
2345 | ||
7afe21cc RK |
2346 | case CONST_DOUBLE: |
2347 | /* This is like the general case, except that it only counts | |
2348 | the integers representing the constant. */ | |
0516f6fe | 2349 | hash += (unsigned int) code + (unsigned int) GET_MODE (x); |
807e902e | 2350 | if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (x) == VOIDmode) |
0516f6fe SB |
2351 | hash += ((unsigned int) CONST_DOUBLE_LOW (x) |
2352 | + (unsigned int) CONST_DOUBLE_HIGH (x)); | |
807e902e KZ |
2353 | else |
2354 | hash += real_hash (CONST_DOUBLE_REAL_VALUE (x)); | |
7afe21cc RK |
2355 | return hash; |
2356 | ||
091a3ac7 CF |
2357 | case CONST_FIXED: |
2358 | hash += (unsigned int) code + (unsigned int) GET_MODE (x); | |
2359 | hash += fixed_hash (CONST_FIXED_VALUE (x)); | |
2360 | return hash; | |
2361 | ||
69ef87e2 AH |
2362 | case CONST_VECTOR: |
2363 | { | |
2364 | int units; | |
2365 | rtx elt; | |
2366 | ||
16c78b66 | 2367 | units = const_vector_encoded_nelts (x); |
69ef87e2 AH |
2368 | |
2369 | for (i = 0; i < units; ++i) | |
2370 | { | |
16c78b66 | 2371 | elt = CONST_VECTOR_ENCODED_ELT (x, i); |
e855c69d | 2372 | hash += hash_rtx_cb (elt, GET_MODE (elt), |
b8698a0f | 2373 | do_not_record_p, hash_arg_in_memory_p, |
e855c69d | 2374 | have_reg_qty, cb); |
69ef87e2 AH |
2375 | } |
2376 | ||
2377 | return hash; | |
2378 | } | |
2379 | ||
7afe21cc RK |
2380 | /* Assume there is only one rtx object for any given label. */ |
2381 | case LABEL_REF: | |
0516f6fe SB |
2382 | /* We don't hash on the address of the CODE_LABEL to avoid bootstrap |
2383 | differences and differences between each stage's debugging dumps. */ | |
2384 | hash += (((unsigned int) LABEL_REF << 7) | |
04a121a7 | 2385 | + CODE_LABEL_NUMBER (label_ref_label (x))); |
2197a88a | 2386 | return hash; |
7afe21cc RK |
2387 | |
2388 | case SYMBOL_REF: | |
0516f6fe SB |
2389 | { |
2390 | /* Don't hash on the symbol's address to avoid bootstrap differences. | |
2391 | Different hash values may cause expressions to be recorded in | |
2392 | different orders and thus different registers to be used in the | |
2393 | final assembler. This also avoids differences in the dump files | |
2394 | between various stages. */ | |
2395 | unsigned int h = 0; | |
2396 | const unsigned char *p = (const unsigned char *) XSTR (x, 0); | |
2397 | ||
2398 | while (*p) | |
2399 | h += (h << 7) + *p++; /* ??? revisit */ | |
2400 | ||
2401 | hash += ((unsigned int) SYMBOL_REF << 7) + h; | |
2402 | return hash; | |
2403 | } | |
7afe21cc RK |
2404 | |
2405 | case MEM: | |
14a774a9 RK |
2406 | /* We don't record if marked volatile or if BLKmode since we don't |
2407 | know the size of the move. */ | |
e855c69d | 2408 | if (do_not_record_p && (MEM_VOLATILE_P (x) || GET_MODE (x) == BLKmode)) |
7afe21cc | 2409 | { |
0516f6fe | 2410 | *do_not_record_p = 1; |
7afe21cc RK |
2411 | return 0; |
2412 | } | |
0516f6fe SB |
2413 | if (hash_arg_in_memory_p && !MEM_READONLY_P (x)) |
2414 | *hash_arg_in_memory_p = 1; | |
4977bab6 | 2415 | |
7afe21cc RK |
2416 | /* Now that we have already found this special case, |
2417 | might as well speed it up as much as possible. */ | |
2197a88a | 2418 | hash += (unsigned) MEM; |
7afe21cc RK |
2419 | x = XEXP (x, 0); |
2420 | goto repeat; | |
2421 | ||
bb07060a JW |
2422 | case USE: |
2423 | /* A USE that mentions non-volatile memory needs special | |
2424 | handling since the MEM may be BLKmode which normally | |
2425 | prevents an entry from being made. Pure calls are | |
0516f6fe SB |
2426 | marked by a USE which mentions BLKmode memory. |
2427 | See calls.c:emit_call_1. */ | |
3c0cb5de | 2428 | if (MEM_P (XEXP (x, 0)) |
bb07060a JW |
2429 | && ! MEM_VOLATILE_P (XEXP (x, 0))) |
2430 | { | |
68252e27 | 2431 | hash += (unsigned) USE; |
bb07060a JW |
2432 | x = XEXP (x, 0); |
2433 | ||
0516f6fe SB |
2434 | if (hash_arg_in_memory_p && !MEM_READONLY_P (x)) |
2435 | *hash_arg_in_memory_p = 1; | |
bb07060a JW |
2436 | |
2437 | /* Now that we have already found this special case, | |
2438 | might as well speed it up as much as possible. */ | |
2439 | hash += (unsigned) MEM; | |
2440 | x = XEXP (x, 0); | |
2441 | goto repeat; | |
2442 | } | |
2443 | break; | |
2444 | ||
7afe21cc RK |
2445 | case PRE_DEC: |
2446 | case PRE_INC: | |
2447 | case POST_DEC: | |
2448 | case POST_INC: | |
4b983fdc RH |
2449 | case PRE_MODIFY: |
2450 | case POST_MODIFY: | |
7afe21cc RK |
2451 | case PC: |
2452 | case CC0: | |
2453 | case CALL: | |
2454 | case UNSPEC_VOLATILE: | |
e855c69d AB |
2455 | if (do_not_record_p) { |
2456 | *do_not_record_p = 1; | |
2457 | return 0; | |
2458 | } | |
2459 | else | |
2460 | return hash; | |
2461 | break; | |
7afe21cc RK |
2462 | |
2463 | case ASM_OPERANDS: | |
e855c69d | 2464 | if (do_not_record_p && MEM_VOLATILE_P (x)) |
7afe21cc | 2465 | { |
0516f6fe | 2466 | *do_not_record_p = 1; |
7afe21cc RK |
2467 | return 0; |
2468 | } | |
6462bb43 AO |
2469 | else |
2470 | { | |
2471 | /* We don't want to take the filename and line into account. */ | |
2472 | hash += (unsigned) code + (unsigned) GET_MODE (x) | |
0516f6fe SB |
2473 | + hash_rtx_string (ASM_OPERANDS_TEMPLATE (x)) |
2474 | + hash_rtx_string (ASM_OPERANDS_OUTPUT_CONSTRAINT (x)) | |
6462bb43 AO |
2475 | + (unsigned) ASM_OPERANDS_OUTPUT_IDX (x); |
2476 | ||
2477 | if (ASM_OPERANDS_INPUT_LENGTH (x)) | |
2478 | { | |
2479 | for (i = 1; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) | |
2480 | { | |
e855c69d AB |
2481 | hash += (hash_rtx_cb (ASM_OPERANDS_INPUT (x, i), |
2482 | GET_MODE (ASM_OPERANDS_INPUT (x, i)), | |
2483 | do_not_record_p, hash_arg_in_memory_p, | |
2484 | have_reg_qty, cb) | |
0516f6fe | 2485 | + hash_rtx_string |
e855c69d | 2486 | (ASM_OPERANDS_INPUT_CONSTRAINT (x, i))); |
6462bb43 AO |
2487 | } |
2488 | ||
0516f6fe | 2489 | hash += hash_rtx_string (ASM_OPERANDS_INPUT_CONSTRAINT (x, 0)); |
6462bb43 AO |
2490 | x = ASM_OPERANDS_INPUT (x, 0); |
2491 | mode = GET_MODE (x); | |
2492 | goto repeat; | |
2493 | } | |
2494 | ||
2495 | return hash; | |
2496 | } | |
e9a25f70 | 2497 | break; |
278a83b2 | 2498 | |
e9a25f70 JL |
2499 | default: |
2500 | break; | |
7afe21cc RK |
2501 | } |
2502 | ||
2503 | i = GET_RTX_LENGTH (code) - 1; | |
2197a88a | 2504 | hash += (unsigned) code + (unsigned) GET_MODE (x); |
7afe21cc RK |
2505 | fmt = GET_RTX_FORMAT (code); |
2506 | for (; i >= 0; i--) | |
2507 | { | |
341c100f | 2508 | switch (fmt[i]) |
7afe21cc | 2509 | { |
341c100f | 2510 | case 'e': |
7afe21cc RK |
2511 | /* If we are about to do the last recursive call |
2512 | needed at this level, change it into iteration. | |
2513 | This function is called enough to be worth it. */ | |
2514 | if (i == 0) | |
2515 | { | |
0516f6fe | 2516 | x = XEXP (x, i); |
7afe21cc RK |
2517 | goto repeat; |
2518 | } | |
b8698a0f | 2519 | |
bbbbb16a | 2520 | hash += hash_rtx_cb (XEXP (x, i), VOIDmode, do_not_record_p, |
e855c69d AB |
2521 | hash_arg_in_memory_p, |
2522 | have_reg_qty, cb); | |
341c100f | 2523 | break; |
0516f6fe | 2524 | |
341c100f NS |
2525 | case 'E': |
2526 | for (j = 0; j < XVECLEN (x, i); j++) | |
bbbbb16a | 2527 | hash += hash_rtx_cb (XVECEXP (x, i, j), VOIDmode, do_not_record_p, |
e855c69d AB |
2528 | hash_arg_in_memory_p, |
2529 | have_reg_qty, cb); | |
341c100f | 2530 | break; |
0516f6fe | 2531 | |
341c100f NS |
2532 | case 's': |
2533 | hash += hash_rtx_string (XSTR (x, i)); | |
2534 | break; | |
2535 | ||
2536 | case 'i': | |
2537 | hash += (unsigned int) XINT (x, i); | |
2538 | break; | |
2539 | ||
91914e56 RS |
2540 | case 'p': |
2541 | hash += constant_lower_bound (SUBREG_BYTE (x)); | |
2542 | break; | |
2543 | ||
341c100f NS |
2544 | case '0': case 't': |
2545 | /* Unused. */ | |
2546 | break; | |
2547 | ||
2548 | default: | |
2549 | gcc_unreachable (); | |
2550 | } | |
7afe21cc | 2551 | } |
0516f6fe | 2552 | |
7afe21cc RK |
2553 | return hash; |
2554 | } | |
2555 | ||
e855c69d AB |
2556 | /* Hash an rtx. We are careful to make sure the value is never negative. |
2557 | Equivalent registers hash identically. | |
2558 | MODE is used in hashing for CONST_INTs only; | |
2559 | otherwise the mode of X is used. | |
2560 | ||
2561 | Store 1 in DO_NOT_RECORD_P if any subexpression is volatile. | |
2562 | ||
2563 | If HASH_ARG_IN_MEMORY_P is not NULL, store 1 in it if X contains | |
3e55d79b | 2564 | a MEM rtx which does not have the MEM_READONLY_P flag set. |
e855c69d AB |
2565 | |
2566 | Note that cse_insn knows that the hash code of a MEM expression | |
2567 | is just (int) MEM plus the hash code of the address. */ | |
2568 | ||
2569 | unsigned | |
ef4bddc2 | 2570 | hash_rtx (const_rtx x, machine_mode mode, int *do_not_record_p, |
e855c69d AB |
2571 | int *hash_arg_in_memory_p, bool have_reg_qty) |
2572 | { | |
2573 | return hash_rtx_cb (x, mode, do_not_record_p, | |
2574 | hash_arg_in_memory_p, have_reg_qty, NULL); | |
2575 | } | |
2576 | ||
0516f6fe SB |
2577 | /* Hash an rtx X for cse via hash_rtx. |
2578 | Stores 1 in do_not_record if any subexpression is volatile. | |
2579 | Stores 1 in hash_arg_in_memory if X contains a mem rtx which | |
3e55d79b | 2580 | does not have the MEM_READONLY_P flag set. */ |
0516f6fe SB |
2581 | |
2582 | static inline unsigned | |
ef4bddc2 | 2583 | canon_hash (rtx x, machine_mode mode) |
0516f6fe SB |
2584 | { |
2585 | return hash_rtx (x, mode, &do_not_record, &hash_arg_in_memory, true); | |
2586 | } | |
2587 | ||
2588 | /* Like canon_hash but with no side effects, i.e. do_not_record | |
2589 | and hash_arg_in_memory are not changed. */ | |
7afe21cc | 2590 | |
0516f6fe | 2591 | static inline unsigned |
ef4bddc2 | 2592 | safe_hash (rtx x, machine_mode mode) |
7afe21cc | 2593 | { |
0516f6fe SB |
2594 | int dummy_do_not_record; |
2595 | return hash_rtx (x, mode, &dummy_do_not_record, NULL, true); | |
7afe21cc RK |
2596 | } |
2597 | \f | |
2598 | /* Return 1 iff X and Y would canonicalize into the same thing, | |
2599 | without actually constructing the canonicalization of either one. | |
2600 | If VALIDATE is nonzero, | |
2601 | we assume X is an expression being processed from the rtl | |
2602 | and Y was found in the hash table. We check register refs | |
2603 | in Y for being marked as valid. | |
2604 | ||
0516f6fe | 2605 | If FOR_GCSE is true, we compare X and Y for equivalence for GCSE. */ |
7afe21cc | 2606 | |
0516f6fe | 2607 | int |
4f588890 | 2608 | exp_equiv_p (const_rtx x, const_rtx y, int validate, bool for_gcse) |
7afe21cc | 2609 | { |
b3694847 SS |
2610 | int i, j; |
2611 | enum rtx_code code; | |
2612 | const char *fmt; | |
7afe21cc RK |
2613 | |
2614 | /* Note: it is incorrect to assume an expression is equivalent to itself | |
2615 | if VALIDATE is nonzero. */ | |
2616 | if (x == y && !validate) | |
2617 | return 1; | |
0516f6fe | 2618 | |
7afe21cc RK |
2619 | if (x == 0 || y == 0) |
2620 | return x == y; | |
2621 | ||
2622 | code = GET_CODE (x); | |
2623 | if (code != GET_CODE (y)) | |
0516f6fe | 2624 | return 0; |
7afe21cc RK |
2625 | |
2626 | /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ | |
2627 | if (GET_MODE (x) != GET_MODE (y)) | |
2628 | return 0; | |
2629 | ||
5932a4d4 | 2630 | /* MEMs referring to different address space are not equivalent. */ |
09e881c9 BE |
2631 | if (code == MEM && MEM_ADDR_SPACE (x) != MEM_ADDR_SPACE (y)) |
2632 | return 0; | |
2633 | ||
7afe21cc RK |
2634 | switch (code) |
2635 | { | |
2636 | case PC: | |
2637 | case CC0: | |
d8116890 | 2638 | CASE_CONST_UNIQUE: |
c13e8210 | 2639 | return x == y; |
7afe21cc RK |
2640 | |
2641 | case LABEL_REF: | |
04a121a7 | 2642 | return label_ref_label (x) == label_ref_label (y); |
7afe21cc | 2643 | |
f54d4924 RK |
2644 | case SYMBOL_REF: |
2645 | return XSTR (x, 0) == XSTR (y, 0); | |
2646 | ||
7afe21cc | 2647 | case REG: |
0516f6fe SB |
2648 | if (for_gcse) |
2649 | return REGNO (x) == REGNO (y); | |
2650 | else | |
2651 | { | |
2652 | unsigned int regno = REGNO (y); | |
2653 | unsigned int i; | |
09e18274 | 2654 | unsigned int endregno = END_REGNO (y); |
7afe21cc | 2655 | |
0516f6fe SB |
2656 | /* If the quantities are not the same, the expressions are not |
2657 | equivalent. If there are and we are not to validate, they | |
2658 | are equivalent. Otherwise, ensure all regs are up-to-date. */ | |
7afe21cc | 2659 | |
0516f6fe SB |
2660 | if (REG_QTY (REGNO (x)) != REG_QTY (regno)) |
2661 | return 0; | |
2662 | ||
2663 | if (! validate) | |
2664 | return 1; | |
2665 | ||
2666 | for (i = regno; i < endregno; i++) | |
2667 | if (REG_IN_TABLE (i) != REG_TICK (i)) | |
2668 | return 0; | |
7afe21cc | 2669 | |
7afe21cc | 2670 | return 1; |
0516f6fe | 2671 | } |
7afe21cc | 2672 | |
0516f6fe SB |
2673 | case MEM: |
2674 | if (for_gcse) | |
2675 | { | |
0516f6fe SB |
2676 | /* A volatile mem should not be considered equivalent to any |
2677 | other. */ | |
2678 | if (MEM_VOLATILE_P (x) || MEM_VOLATILE_P (y)) | |
2679 | return 0; | |
8a76c4a0 JJ |
2680 | |
2681 | /* Can't merge two expressions in different alias sets, since we | |
2682 | can decide that the expression is transparent in a block when | |
2683 | it isn't, due to it being set with the different alias set. | |
2684 | ||
2685 | Also, can't merge two expressions with different MEM_ATTRS. | |
2686 | They could e.g. be two different entities allocated into the | |
2687 | same space on the stack (see e.g. PR25130). In that case, the | |
2688 | MEM addresses can be the same, even though the two MEMs are | |
2689 | absolutely not equivalent. | |
2690 | ||
2691 | But because really all MEM attributes should be the same for | |
2692 | equivalent MEMs, we just use the invariant that MEMs that have | |
2693 | the same attributes share the same mem_attrs data structure. */ | |
96b3c03f | 2694 | if (!mem_attrs_eq_p (MEM_ATTRS (x), MEM_ATTRS (y))) |
8a76c4a0 | 2695 | return 0; |
e304caa4 EB |
2696 | |
2697 | /* If we are handling exceptions, we cannot consider two expressions | |
2698 | with different trapping status as equivalent, because simple_mem | |
2699 | might accept one and reject the other. */ | |
2700 | if (cfun->can_throw_non_call_exceptions | |
2701 | && (MEM_NOTRAP_P (x) != MEM_NOTRAP_P (y))) | |
2702 | return 0; | |
0516f6fe SB |
2703 | } |
2704 | break; | |
7afe21cc RK |
2705 | |
2706 | /* For commutative operations, check both orders. */ | |
2707 | case PLUS: | |
2708 | case MULT: | |
2709 | case AND: | |
2710 | case IOR: | |
2711 | case XOR: | |
2712 | case NE: | |
2713 | case EQ: | |
0516f6fe SB |
2714 | return ((exp_equiv_p (XEXP (x, 0), XEXP (y, 0), |
2715 | validate, for_gcse) | |
7afe21cc | 2716 | && exp_equiv_p (XEXP (x, 1), XEXP (y, 1), |
0516f6fe | 2717 | validate, for_gcse)) |
7afe21cc | 2718 | || (exp_equiv_p (XEXP (x, 0), XEXP (y, 1), |
0516f6fe | 2719 | validate, for_gcse) |
7afe21cc | 2720 | && exp_equiv_p (XEXP (x, 1), XEXP (y, 0), |
0516f6fe | 2721 | validate, for_gcse))); |
278a83b2 | 2722 | |
6462bb43 AO |
2723 | case ASM_OPERANDS: |
2724 | /* We don't use the generic code below because we want to | |
2725 | disregard filename and line numbers. */ | |
2726 | ||
2727 | /* A volatile asm isn't equivalent to any other. */ | |
2728 | if (MEM_VOLATILE_P (x) || MEM_VOLATILE_P (y)) | |
2729 | return 0; | |
2730 | ||
2731 | if (GET_MODE (x) != GET_MODE (y) | |
2732 | || strcmp (ASM_OPERANDS_TEMPLATE (x), ASM_OPERANDS_TEMPLATE (y)) | |
2733 | || strcmp (ASM_OPERANDS_OUTPUT_CONSTRAINT (x), | |
2734 | ASM_OPERANDS_OUTPUT_CONSTRAINT (y)) | |
2735 | || ASM_OPERANDS_OUTPUT_IDX (x) != ASM_OPERANDS_OUTPUT_IDX (y) | |
2736 | || ASM_OPERANDS_INPUT_LENGTH (x) != ASM_OPERANDS_INPUT_LENGTH (y)) | |
2737 | return 0; | |
2738 | ||
2739 | if (ASM_OPERANDS_INPUT_LENGTH (x)) | |
2740 | { | |
2741 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) | |
2742 | if (! exp_equiv_p (ASM_OPERANDS_INPUT (x, i), | |
2743 | ASM_OPERANDS_INPUT (y, i), | |
0516f6fe | 2744 | validate, for_gcse) |
6462bb43 AO |
2745 | || strcmp (ASM_OPERANDS_INPUT_CONSTRAINT (x, i), |
2746 | ASM_OPERANDS_INPUT_CONSTRAINT (y, i))) | |
2747 | return 0; | |
2748 | } | |
2749 | ||
2750 | return 1; | |
2751 | ||
e9a25f70 JL |
2752 | default: |
2753 | break; | |
7afe21cc RK |
2754 | } |
2755 | ||
2756 | /* Compare the elements. If any pair of corresponding elements | |
0516f6fe | 2757 | fail to match, return 0 for the whole thing. */ |
7afe21cc RK |
2758 | |
2759 | fmt = GET_RTX_FORMAT (code); | |
2760 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2761 | { | |
906c4e36 | 2762 | switch (fmt[i]) |
7afe21cc | 2763 | { |
906c4e36 | 2764 | case 'e': |
0516f6fe SB |
2765 | if (! exp_equiv_p (XEXP (x, i), XEXP (y, i), |
2766 | validate, for_gcse)) | |
7afe21cc | 2767 | return 0; |
906c4e36 RK |
2768 | break; |
2769 | ||
2770 | case 'E': | |
7afe21cc RK |
2771 | if (XVECLEN (x, i) != XVECLEN (y, i)) |
2772 | return 0; | |
2773 | for (j = 0; j < XVECLEN (x, i); j++) | |
2774 | if (! exp_equiv_p (XVECEXP (x, i, j), XVECEXP (y, i, j), | |
0516f6fe | 2775 | validate, for_gcse)) |
7afe21cc | 2776 | return 0; |
906c4e36 RK |
2777 | break; |
2778 | ||
2779 | case 's': | |
7afe21cc RK |
2780 | if (strcmp (XSTR (x, i), XSTR (y, i))) |
2781 | return 0; | |
906c4e36 RK |
2782 | break; |
2783 | ||
2784 | case 'i': | |
7afe21cc RK |
2785 | if (XINT (x, i) != XINT (y, i)) |
2786 | return 0; | |
906c4e36 RK |
2787 | break; |
2788 | ||
2789 | case 'w': | |
2790 | if (XWINT (x, i) != XWINT (y, i)) | |
2791 | return 0; | |
278a83b2 | 2792 | break; |
906c4e36 | 2793 | |
91914e56 RS |
2794 | case 'p': |
2795 | if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y))) | |
2796 | return 0; | |
2797 | break; | |
2798 | ||
906c4e36 | 2799 | case '0': |
8f985ec4 | 2800 | case 't': |
906c4e36 RK |
2801 | break; |
2802 | ||
2803 | default: | |
341c100f | 2804 | gcc_unreachable (); |
7afe21cc | 2805 | } |
278a83b2 | 2806 | } |
906c4e36 | 2807 | |
7afe21cc RK |
2808 | return 1; |
2809 | } | |
2810 | \f | |
eef3c949 RS |
2811 | /* Subroutine of canon_reg. Pass *XLOC through canon_reg, and validate |
2812 | the result if necessary. INSN is as for canon_reg. */ | |
2813 | ||
2814 | static void | |
20468884 | 2815 | validate_canon_reg (rtx *xloc, rtx_insn *insn) |
eef3c949 | 2816 | { |
6fb5fa3c DB |
2817 | if (*xloc) |
2818 | { | |
32e9fa48 | 2819 | rtx new_rtx = canon_reg (*xloc, insn); |
eef3c949 | 2820 | |
6fb5fa3c DB |
2821 | /* If replacing pseudo with hard reg or vice versa, ensure the |
2822 | insn remains valid. Likewise if the insn has MATCH_DUPs. */ | |
32e9fa48 KG |
2823 | gcc_assert (insn && new_rtx); |
2824 | validate_change (insn, xloc, new_rtx, 1); | |
6fb5fa3c | 2825 | } |
eef3c949 RS |
2826 | } |
2827 | ||
7afe21cc RK |
2828 | /* Canonicalize an expression: |
2829 | replace each register reference inside it | |
2830 | with the "oldest" equivalent register. | |
2831 | ||
67e0a632 | 2832 | If INSN is nonzero validate_change is used to ensure that INSN remains valid |
da7d8304 | 2833 | after we make our substitution. The calls are made with IN_GROUP nonzero |
7722328e RK |
2834 | so apply_change_group must be called upon the outermost return from this |
2835 | function (unless INSN is zero). The result of apply_change_group can | |
2836 | generally be discarded since the changes we are making are optional. */ | |
7afe21cc RK |
2837 | |
2838 | static rtx | |
20468884 | 2839 | canon_reg (rtx x, rtx_insn *insn) |
7afe21cc | 2840 | { |
b3694847 SS |
2841 | int i; |
2842 | enum rtx_code code; | |
2843 | const char *fmt; | |
7afe21cc RK |
2844 | |
2845 | if (x == 0) | |
2846 | return x; | |
2847 | ||
2848 | code = GET_CODE (x); | |
2849 | switch (code) | |
2850 | { | |
2851 | case PC: | |
2852 | case CC0: | |
2853 | case CONST: | |
d8116890 | 2854 | CASE_CONST_ANY: |
7afe21cc RK |
2855 | case SYMBOL_REF: |
2856 | case LABEL_REF: | |
2857 | case ADDR_VEC: | |
2858 | case ADDR_DIFF_VEC: | |
2859 | return x; | |
2860 | ||
2861 | case REG: | |
2862 | { | |
b3694847 SS |
2863 | int first; |
2864 | int q; | |
2865 | struct qty_table_elem *ent; | |
7afe21cc RK |
2866 | |
2867 | /* Never replace a hard reg, because hard regs can appear | |
2868 | in more than one machine mode, and we must preserve the mode | |
2869 | of each occurrence. Also, some hard regs appear in | |
2870 | MEMs that are shared and mustn't be altered. Don't try to | |
2871 | replace any reg that maps to a reg of class NO_REGS. */ | |
2872 | if (REGNO (x) < FIRST_PSEUDO_REGISTER | |
2873 | || ! REGNO_QTY_VALID_P (REGNO (x))) | |
2874 | return x; | |
2875 | ||
278a83b2 | 2876 | q = REG_QTY (REGNO (x)); |
1bb98cec DM |
2877 | ent = &qty_table[q]; |
2878 | first = ent->first_reg; | |
7afe21cc RK |
2879 | return (first >= FIRST_PSEUDO_REGISTER ? regno_reg_rtx[first] |
2880 | : REGNO_REG_CLASS (first) == NO_REGS ? x | |
1bb98cec | 2881 | : gen_rtx_REG (ent->mode, first)); |
7afe21cc | 2882 | } |
278a83b2 | 2883 | |
e9a25f70 JL |
2884 | default: |
2885 | break; | |
7afe21cc RK |
2886 | } |
2887 | ||
2888 | fmt = GET_RTX_FORMAT (code); | |
2889 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
2890 | { | |
b3694847 | 2891 | int j; |
7afe21cc RK |
2892 | |
2893 | if (fmt[i] == 'e') | |
eef3c949 | 2894 | validate_canon_reg (&XEXP (x, i), insn); |
7afe21cc RK |
2895 | else if (fmt[i] == 'E') |
2896 | for (j = 0; j < XVECLEN (x, i); j++) | |
eef3c949 | 2897 | validate_canon_reg (&XVECEXP (x, i, j), insn); |
7afe21cc RK |
2898 | } |
2899 | ||
2900 | return x; | |
2901 | } | |
2902 | \f | |
bca05d20 RK |
2903 | /* Given an operation (CODE, *PARG1, *PARG2), where code is a comparison |
2904 | operation (EQ, NE, GT, etc.), follow it back through the hash table and | |
2905 | what values are being compared. | |
1a87eea2 | 2906 | |
bca05d20 RK |
2907 | *PARG1 and *PARG2 are updated to contain the rtx representing the values |
2908 | actually being compared. For example, if *PARG1 was (cc0) and *PARG2 | |
2909 | was (const_int 0), *PARG1 and *PARG2 will be set to the objects that were | |
2910 | compared to produce cc0. | |
a432f20d | 2911 | |
bca05d20 RK |
2912 | The return value is the comparison operator and is either the code of |
2913 | A or the code corresponding to the inverse of the comparison. */ | |
7afe21cc | 2914 | |
0cedb36c | 2915 | static enum rtx_code |
7080f735 | 2916 | find_comparison_args (enum rtx_code code, rtx *parg1, rtx *parg2, |
ef4bddc2 | 2917 | machine_mode *pmode1, machine_mode *pmode2) |
7afe21cc | 2918 | { |
0cedb36c | 2919 | rtx arg1, arg2; |
6e2830c3 | 2920 | hash_set<rtx> *visited = NULL; |
27ec0502 AJ |
2921 | /* Set nonzero when we find something of interest. */ |
2922 | rtx x = NULL; | |
1a87eea2 | 2923 | |
0cedb36c | 2924 | arg1 = *parg1, arg2 = *parg2; |
7afe21cc | 2925 | |
0cedb36c | 2926 | /* If ARG2 is const0_rtx, see what ARG1 is equivalent to. */ |
7afe21cc | 2927 | |
0cedb36c | 2928 | while (arg2 == CONST0_RTX (GET_MODE (arg1))) |
a432f20d | 2929 | { |
0cedb36c JL |
2930 | int reverse_code = 0; |
2931 | struct table_elt *p = 0; | |
6076248a | 2932 | |
27ec0502 AJ |
2933 | /* Remember state from previous iteration. */ |
2934 | if (x) | |
2935 | { | |
2936 | if (!visited) | |
6e2830c3 TS |
2937 | visited = new hash_set<rtx>; |
2938 | visited->add (x); | |
27ec0502 AJ |
2939 | x = 0; |
2940 | } | |
2941 | ||
0cedb36c JL |
2942 | /* If arg1 is a COMPARE, extract the comparison arguments from it. |
2943 | On machines with CC0, this is the only case that can occur, since | |
2944 | fold_rtx will return the COMPARE or item being compared with zero | |
2945 | when given CC0. */ | |
6076248a | 2946 | |
0cedb36c JL |
2947 | if (GET_CODE (arg1) == COMPARE && arg2 == const0_rtx) |
2948 | x = arg1; | |
6076248a | 2949 | |
0cedb36c JL |
2950 | /* If ARG1 is a comparison operator and CODE is testing for |
2951 | STORE_FLAG_VALUE, get the inner arguments. */ | |
a432f20d | 2952 | |
ec8e098d | 2953 | else if (COMPARISON_P (arg1)) |
7afe21cc | 2954 | { |
efdc7e19 RH |
2955 | #ifdef FLOAT_STORE_FLAG_VALUE |
2956 | REAL_VALUE_TYPE fsfv; | |
2957 | #endif | |
2958 | ||
0cedb36c JL |
2959 | if (code == NE |
2960 | || (GET_MODE_CLASS (GET_MODE (arg1)) == MODE_INT | |
2961 | && code == LT && STORE_FLAG_VALUE == -1) | |
2962 | #ifdef FLOAT_STORE_FLAG_VALUE | |
9b92bf04 | 2963 | || (SCALAR_FLOAT_MODE_P (GET_MODE (arg1)) |
efdc7e19 RH |
2964 | && (fsfv = FLOAT_STORE_FLAG_VALUE (GET_MODE (arg1)), |
2965 | REAL_VALUE_NEGATIVE (fsfv))) | |
7afe21cc | 2966 | #endif |
a432f20d | 2967 | ) |
0cedb36c JL |
2968 | x = arg1; |
2969 | else if (code == EQ | |
2970 | || (GET_MODE_CLASS (GET_MODE (arg1)) == MODE_INT | |
2971 | && code == GE && STORE_FLAG_VALUE == -1) | |
2972 | #ifdef FLOAT_STORE_FLAG_VALUE | |
9b92bf04 | 2973 | || (SCALAR_FLOAT_MODE_P (GET_MODE (arg1)) |
efdc7e19 RH |
2974 | && (fsfv = FLOAT_STORE_FLAG_VALUE (GET_MODE (arg1)), |
2975 | REAL_VALUE_NEGATIVE (fsfv))) | |
0cedb36c JL |
2976 | #endif |
2977 | ) | |
2978 | x = arg1, reverse_code = 1; | |
7afe21cc RK |
2979 | } |
2980 | ||
0cedb36c | 2981 | /* ??? We could also check for |
7afe21cc | 2982 | |
0cedb36c | 2983 | (ne (and (eq (...) (const_int 1))) (const_int 0)) |
7afe21cc | 2984 | |
0cedb36c | 2985 | and related forms, but let's wait until we see them occurring. */ |
7afe21cc | 2986 | |
0cedb36c JL |
2987 | if (x == 0) |
2988 | /* Look up ARG1 in the hash table and see if it has an equivalence | |
2989 | that lets us see what is being compared. */ | |
0516f6fe | 2990 | p = lookup (arg1, SAFE_HASH (arg1, GET_MODE (arg1)), GET_MODE (arg1)); |
278a83b2 | 2991 | if (p) |
8b03b984 R |
2992 | { |
2993 | p = p->first_same_value; | |
2994 | ||
2995 | /* If what we compare is already known to be constant, that is as | |
2996 | good as it gets. | |
2997 | We need to break the loop in this case, because otherwise we | |
2998 | can have an infinite loop when looking at a reg that is known | |
2999 | to be a constant which is the same as a comparison of a reg | |
3000 | against zero which appears later in the insn stream, which in | |
3001 | turn is constant and the same as the comparison of the first reg | |
3002 | against zero... */ | |
3003 | if (p->is_const) | |
3004 | break; | |
3005 | } | |
7afe21cc | 3006 | |
0cedb36c | 3007 | for (; p; p = p->next_same_value) |
7afe21cc | 3008 | { |
ef4bddc2 | 3009 | machine_mode inner_mode = GET_MODE (p->exp); |
efdc7e19 RH |
3010 | #ifdef FLOAT_STORE_FLAG_VALUE |
3011 | REAL_VALUE_TYPE fsfv; | |
3012 | #endif | |
7afe21cc | 3013 | |
0cedb36c | 3014 | /* If the entry isn't valid, skip it. */ |
0516f6fe | 3015 | if (! exp_equiv_p (p->exp, p->exp, 1, false)) |
0cedb36c | 3016 | continue; |
f76b9db2 | 3017 | |
27ec0502 | 3018 | /* If it's a comparison we've used before, skip it. */ |
6e2830c3 | 3019 | if (visited && visited->contains (p->exp)) |
8f1ad6b6 SL |
3020 | continue; |
3021 | ||
bca05d20 RK |
3022 | if (GET_CODE (p->exp) == COMPARE |
3023 | /* Another possibility is that this machine has a compare insn | |
3024 | that includes the comparison code. In that case, ARG1 would | |
3025 | be equivalent to a comparison operation that would set ARG1 to | |
3026 | either STORE_FLAG_VALUE or zero. If this is an NE operation, | |
3027 | ORIG_CODE is the actual comparison being done; if it is an EQ, | |
3028 | we must reverse ORIG_CODE. On machine with a negative value | |
3029 | for STORE_FLAG_VALUE, also look at LT and GE operations. */ | |
3030 | || ((code == NE | |
3031 | || (code == LT | |
2d0c270f BS |
3032 | && val_signbit_known_set_p (inner_mode, |
3033 | STORE_FLAG_VALUE)) | |
0cedb36c | 3034 | #ifdef FLOAT_STORE_FLAG_VALUE |
bca05d20 | 3035 | || (code == LT |
3d8bf70f | 3036 | && SCALAR_FLOAT_MODE_P (inner_mode) |
efdc7e19 RH |
3037 | && (fsfv = FLOAT_STORE_FLAG_VALUE (GET_MODE (arg1)), |
3038 | REAL_VALUE_NEGATIVE (fsfv))) | |
0cedb36c | 3039 | #endif |
bca05d20 | 3040 | ) |
ec8e098d | 3041 | && COMPARISON_P (p->exp))) |
7afe21cc | 3042 | { |
0cedb36c JL |
3043 | x = p->exp; |
3044 | break; | |
3045 | } | |
3046 | else if ((code == EQ | |
3047 | || (code == GE | |
2d0c270f BS |
3048 | && val_signbit_known_set_p (inner_mode, |
3049 | STORE_FLAG_VALUE)) | |
0cedb36c JL |
3050 | #ifdef FLOAT_STORE_FLAG_VALUE |
3051 | || (code == GE | |
3d8bf70f | 3052 | && SCALAR_FLOAT_MODE_P (inner_mode) |
efdc7e19 RH |
3053 | && (fsfv = FLOAT_STORE_FLAG_VALUE (GET_MODE (arg1)), |
3054 | REAL_VALUE_NEGATIVE (fsfv))) | |
0cedb36c JL |
3055 | #endif |
3056 | ) | |
ec8e098d | 3057 | && COMPARISON_P (p->exp)) |
0cedb36c JL |
3058 | { |
3059 | reverse_code = 1; | |
3060 | x = p->exp; | |
3061 | break; | |
7afe21cc RK |
3062 | } |
3063 | ||
4977bab6 ZW |
3064 | /* If this non-trapping address, e.g. fp + constant, the |
3065 | equivalent is a better operand since it may let us predict | |
3066 | the value of the comparison. */ | |
3067 | else if (!rtx_addr_can_trap_p (p->exp)) | |
0cedb36c JL |
3068 | { |
3069 | arg1 = p->exp; | |
3070 | continue; | |
3071 | } | |
7afe21cc | 3072 | } |
7afe21cc | 3073 | |
0cedb36c JL |
3074 | /* If we didn't find a useful equivalence for ARG1, we are done. |
3075 | Otherwise, set up for the next iteration. */ | |
3076 | if (x == 0) | |
3077 | break; | |
7afe21cc | 3078 | |
026c3cfd | 3079 | /* If we need to reverse the comparison, make sure that is |
78192b09 RH |
3080 | possible -- we can't necessarily infer the value of GE from LT |
3081 | with floating-point operands. */ | |
0cedb36c | 3082 | if (reverse_code) |
261efdef | 3083 | { |
c9b0a227 | 3084 | enum rtx_code reversed = reversed_comparison_code (x, NULL); |
261efdef JH |
3085 | if (reversed == UNKNOWN) |
3086 | break; | |
68252e27 KH |
3087 | else |
3088 | code = reversed; | |
261efdef | 3089 | } |
ec8e098d | 3090 | else if (COMPARISON_P (x)) |
261efdef JH |
3091 | code = GET_CODE (x); |
3092 | arg1 = XEXP (x, 0), arg2 = XEXP (x, 1); | |
7afe21cc RK |
3093 | } |
3094 | ||
0cedb36c JL |
3095 | /* Return our results. Return the modes from before fold_rtx |
3096 | because fold_rtx might produce const_int, and then it's too late. */ | |
3097 | *pmode1 = GET_MODE (arg1), *pmode2 = GET_MODE (arg2); | |
3098 | *parg1 = fold_rtx (arg1, 0), *parg2 = fold_rtx (arg2, 0); | |
3099 | ||
27ec0502 | 3100 | if (visited) |
6e2830c3 | 3101 | delete visited; |
0cedb36c | 3102 | return code; |
7afe21cc RK |
3103 | } |
3104 | \f | |
a52b023a PB |
3105 | /* If X is a nontrivial arithmetic operation on an argument for which |
3106 | a constant value can be determined, return the result of operating | |
3107 | on that value, as a constant. Otherwise, return X, possibly with | |
3108 | one or more operands changed to a forward-propagated constant. | |
25910ca4 | 3109 | |
a52b023a PB |
3110 | If X is a register whose contents are known, we do NOT return |
3111 | those contents here; equiv_constant is called to perform that task. | |
3112 | For SUBREGs and MEMs, we do that both here and in equiv_constant. | |
7afe21cc RK |
3113 | |
3114 | INSN is the insn that we may be modifying. If it is 0, make a copy | |
3115 | of X before modifying it. */ | |
3116 | ||
3117 | static rtx | |
20468884 | 3118 | fold_rtx (rtx x, rtx_insn *insn) |
7afe21cc | 3119 | { |
b3694847 | 3120 | enum rtx_code code; |
ef4bddc2 | 3121 | machine_mode mode; |
b3694847 SS |
3122 | const char *fmt; |
3123 | int i; | |
32e9fa48 | 3124 | rtx new_rtx = 0; |
a52b023a | 3125 | int changed = 0; |
5284e559 | 3126 | poly_int64 xval; |
7afe21cc | 3127 | |
a52b023a | 3128 | /* Operands of X. */ |
e54bd4ab JJ |
3129 | /* Workaround -Wmaybe-uninitialized false positive during |
3130 | profiledbootstrap by initializing them. */ | |
3131 | rtx folded_arg0 = NULL_RTX; | |
3132 | rtx folded_arg1 = NULL_RTX; | |
7afe21cc RK |
3133 | |
3134 | /* Constant equivalents of first three operands of X; | |
3135 | 0 when no such equivalent is known. */ | |
3136 | rtx const_arg0; | |
3137 | rtx const_arg1; | |
3138 | rtx const_arg2; | |
3139 | ||
3140 | /* The mode of the first operand of X. We need this for sign and zero | |
3141 | extends. */ | |
ef4bddc2 | 3142 | machine_mode mode_arg0; |
7afe21cc RK |
3143 | |
3144 | if (x == 0) | |
3145 | return x; | |
3146 | ||
a52b023a | 3147 | /* Try to perform some initial simplifications on X. */ |
7afe21cc RK |
3148 | code = GET_CODE (x); |
3149 | switch (code) | |
3150 | { | |
a52b023a PB |
3151 | case MEM: |
3152 | case SUBREG: | |
5141ed42 JL |
3153 | /* The first operand of a SIGN/ZERO_EXTRACT has a different meaning |
3154 | than it would in other contexts. Basically its mode does not | |
3155 | signify the size of the object read. That information is carried | |
3156 | by size operand. If we happen to have a MEM of the appropriate | |
3157 | mode in our tables with a constant value we could simplify the | |
3158 | extraction incorrectly if we allowed substitution of that value | |
3159 | for the MEM. */ | |
3160 | case ZERO_EXTRACT: | |
3161 | case SIGN_EXTRACT: | |
32e9fa48 KG |
3162 | if ((new_rtx = equiv_constant (x)) != NULL_RTX) |
3163 | return new_rtx; | |
a52b023a PB |
3164 | return x; |
3165 | ||
7afe21cc | 3166 | case CONST: |
d8116890 | 3167 | CASE_CONST_ANY: |
7afe21cc RK |
3168 | case SYMBOL_REF: |
3169 | case LABEL_REF: | |
3170 | case REG: | |
01aa1d43 | 3171 | case PC: |
7afe21cc RK |
3172 | /* No use simplifying an EXPR_LIST |
3173 | since they are used only for lists of args | |
3174 | in a function call's REG_EQUAL note. */ | |
3175 | case EXPR_LIST: | |
3176 | return x; | |
3177 | ||
7afe21cc RK |
3178 | case CC0: |
3179 | return prev_insn_cc0; | |
7afe21cc | 3180 | |
9255709c | 3181 | case ASM_OPERANDS: |
6c667859 AB |
3182 | if (insn) |
3183 | { | |
3184 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) | |
3185 | validate_change (insn, &ASM_OPERANDS_INPUT (x, i), | |
3186 | fold_rtx (ASM_OPERANDS_INPUT (x, i), insn), 0); | |
3187 | } | |
a52b023a PB |
3188 | return x; |
3189 | ||
a52b023a | 3190 | case CALL: |
1e8552c2 | 3191 | if (NO_FUNCTION_CSE && CONSTANT_P (XEXP (XEXP (x, 0), 0))) |
a52b023a | 3192 | return x; |
9255709c | 3193 | break; |
278a83b2 | 3194 | |
a52b023a | 3195 | /* Anything else goes through the loop below. */ |
e9a25f70 JL |
3196 | default: |
3197 | break; | |
7afe21cc RK |
3198 | } |
3199 | ||
a52b023a | 3200 | mode = GET_MODE (x); |
7afe21cc RK |
3201 | const_arg0 = 0; |
3202 | const_arg1 = 0; | |
3203 | const_arg2 = 0; | |
3204 | mode_arg0 = VOIDmode; | |
3205 | ||
3206 | /* Try folding our operands. | |
3207 | Then see which ones have constant values known. */ | |
3208 | ||
3209 | fmt = GET_RTX_FORMAT (code); | |
3210 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
3211 | if (fmt[i] == 'e') | |
3212 | { | |
a52b023a | 3213 | rtx folded_arg = XEXP (x, i), const_arg; |
ef4bddc2 | 3214 | machine_mode mode_arg = GET_MODE (folded_arg); |
7e7e28c7 AO |
3215 | |
3216 | switch (GET_CODE (folded_arg)) | |
3217 | { | |
3218 | case MEM: | |
3219 | case REG: | |
3220 | case SUBREG: | |
3221 | const_arg = equiv_constant (folded_arg); | |
3222 | break; | |
3223 | ||
3224 | case CONST: | |
d8116890 | 3225 | CASE_CONST_ANY: |
7e7e28c7 AO |
3226 | case SYMBOL_REF: |
3227 | case LABEL_REF: | |
7e7e28c7 AO |
3228 | const_arg = folded_arg; |
3229 | break; | |
3230 | ||
7e7e28c7 | 3231 | case CC0: |
728acca0 MP |
3232 | /* The cc0-user and cc0-setter may be in different blocks if |
3233 | the cc0-setter potentially traps. In that case PREV_INSN_CC0 | |
3234 | will have been cleared as we exited the block with the | |
3235 | setter. | |
3236 | ||
3237 | While we could potentially track cc0 in this case, it just | |
3238 | doesn't seem to be worth it given that cc0 targets are not | |
3239 | terribly common or important these days and trapping math | |
3240 | is rarely used. The combination of those two conditions | |
3241 | necessary to trip this situation is exceedingly rare in the | |
3242 | real world. */ | |
3243 | if (!prev_insn_cc0) | |
3244 | { | |
3245 | const_arg = NULL_RTX; | |
3246 | } | |
3247 | else | |
3248 | { | |
3249 | folded_arg = prev_insn_cc0; | |
3250 | mode_arg = prev_insn_cc0_mode; | |
3251 | const_arg = equiv_constant (folded_arg); | |
3252 | } | |
7e7e28c7 | 3253 | break; |
7e7e28c7 AO |
3254 | |
3255 | default: | |
3256 | folded_arg = fold_rtx (folded_arg, insn); | |
3257 | const_arg = equiv_constant (folded_arg); | |
3258 | break; | |
3259 | } | |
7afe21cc RK |
3260 | |
3261 | /* For the first three operands, see if the operand | |
3262 | is constant or equivalent to a constant. */ | |
3263 | switch (i) | |
3264 | { | |
3265 | case 0: | |
3266 | folded_arg0 = folded_arg; | |
3267 | const_arg0 = const_arg; | |
3268 | mode_arg0 = mode_arg; | |
3269 | break; | |
3270 | case 1: | |
3271 | folded_arg1 = folded_arg; | |
3272 | const_arg1 = const_arg; | |
3273 | break; | |
3274 | case 2: | |
3275 | const_arg2 = const_arg; | |
3276 | break; | |
3277 | } | |
3278 | ||
a52b023a PB |
3279 | /* Pick the least expensive of the argument and an equivalent constant |
3280 | argument. */ | |
3281 | if (const_arg != 0 | |
3282 | && const_arg != folded_arg | |
e548c9df AM |
3283 | && (COST_IN (const_arg, mode_arg, code, i) |
3284 | <= COST_IN (folded_arg, mode_arg, code, i)) | |
f2fa288f | 3285 | |
8cce3d04 RS |
3286 | /* It's not safe to substitute the operand of a conversion |
3287 | operator with a constant, as the conversion's identity | |
f652d14b | 3288 | depends upon the mode of its operand. This optimization |
8cce3d04 | 3289 | is handled by the call to simplify_unary_operation. */ |
a52b023a PB |
3290 | && (GET_RTX_CLASS (code) != RTX_UNARY |
3291 | || GET_MODE (const_arg) == mode_arg0 | |
3292 | || (code != ZERO_EXTEND | |
3293 | && code != SIGN_EXTEND | |
3294 | && code != TRUNCATE | |
3295 | && code != FLOAT_TRUNCATE | |
3296 | && code != FLOAT_EXTEND | |
3297 | && code != FLOAT | |
3298 | && code != FIX | |
3299 | && code != UNSIGNED_FLOAT | |
3300 | && code != UNSIGNED_FIX))) | |
3301 | folded_arg = const_arg; | |
3302 | ||
3303 | if (folded_arg == XEXP (x, i)) | |
3304 | continue; | |
7afe21cc | 3305 | |
a52b023a PB |
3306 | if (insn == NULL_RTX && !changed) |
3307 | x = copy_rtx (x); | |
3308 | changed = 1; | |
b8b89e7c | 3309 | validate_unshare_change (insn, &XEXP (x, i), folded_arg, 1); |
2d8b0f3a | 3310 | } |
7afe21cc | 3311 | |
a52b023a | 3312 | if (changed) |
7afe21cc | 3313 | { |
a52b023a PB |
3314 | /* Canonicalize X if necessary, and keep const_argN and folded_argN |
3315 | consistent with the order in X. */ | |
3316 | if (canonicalize_change_group (insn, x)) | |
7afe21cc | 3317 | { |
4e1952ab KT |
3318 | std::swap (const_arg0, const_arg1); |
3319 | std::swap (folded_arg0, folded_arg1); | |
7afe21cc | 3320 | } |
a52b023a PB |
3321 | |
3322 | apply_change_group (); | |
7afe21cc RK |
3323 | } |
3324 | ||
3325 | /* If X is an arithmetic operation, see if we can simplify it. */ | |
3326 | ||
3327 | switch (GET_RTX_CLASS (code)) | |
3328 | { | |
ec8e098d | 3329 | case RTX_UNARY: |
67a37737 | 3330 | { |
67a37737 RK |
3331 | /* We can't simplify extension ops unless we know the |
3332 | original mode. */ | |
3333 | if ((code == ZERO_EXTEND || code == SIGN_EXTEND) | |
3334 | && mode_arg0 == VOIDmode) | |
3335 | break; | |
3336 | ||
32e9fa48 | 3337 | new_rtx = simplify_unary_operation (code, mode, |
696d76a5 MS |
3338 | const_arg0 ? const_arg0 : folded_arg0, |
3339 | mode_arg0); | |
67a37737 | 3340 | } |
7afe21cc | 3341 | break; |
278a83b2 | 3342 | |
ec8e098d PB |
3343 | case RTX_COMPARE: |
3344 | case RTX_COMM_COMPARE: | |
7afe21cc RK |
3345 | /* See what items are actually being compared and set FOLDED_ARG[01] |
3346 | to those values and CODE to the actual comparison code. If any are | |
3347 | constant, set CONST_ARG0 and CONST_ARG1 appropriately. We needn't | |
3348 | do anything if both operands are already known to be constant. */ | |
3349 | ||
21e5076a UB |
3350 | /* ??? Vector mode comparisons are not supported yet. */ |
3351 | if (VECTOR_MODE_P (mode)) | |
3352 | break; | |
3353 | ||
7afe21cc RK |
3354 | if (const_arg0 == 0 || const_arg1 == 0) |
3355 | { | |
3356 | struct table_elt *p0, *p1; | |
9e6a14a4 | 3357 | rtx true_rtx, false_rtx; |
ef4bddc2 | 3358 | machine_mode mode_arg1; |
c610adec | 3359 | |
9b92bf04 | 3360 | if (SCALAR_FLOAT_MODE_P (mode)) |
c610adec | 3361 | { |
9e6a14a4 | 3362 | #ifdef FLOAT_STORE_FLAG_VALUE |
555affd7 | 3363 | true_rtx = (const_double_from_real_value |
68252e27 | 3364 | (FLOAT_STORE_FLAG_VALUE (mode), mode)); |
9e6a14a4 L |
3365 | #else |
3366 | true_rtx = NULL_RTX; | |
3367 | #endif | |
d6edb99e | 3368 | false_rtx = CONST0_RTX (mode); |
c610adec | 3369 | } |
9e6a14a4 L |
3370 | else |
3371 | { | |
3372 | true_rtx = const_true_rtx; | |
3373 | false_rtx = const0_rtx; | |
3374 | } | |
7afe21cc | 3375 | |
13c9910f RS |
3376 | code = find_comparison_args (code, &folded_arg0, &folded_arg1, |
3377 | &mode_arg0, &mode_arg1); | |
7afe21cc | 3378 | |
13c9910f RS |
3379 | /* If the mode is VOIDmode or a MODE_CC mode, we don't know |
3380 | what kinds of things are being compared, so we can't do | |
3381 | anything with this comparison. */ | |
7afe21cc RK |
3382 | |
3383 | if (mode_arg0 == VOIDmode || GET_MODE_CLASS (mode_arg0) == MODE_CC) | |
3384 | break; | |
3385 | ||
75335440 KH |
3386 | const_arg0 = equiv_constant (folded_arg0); |
3387 | const_arg1 = equiv_constant (folded_arg1); | |
3388 | ||
0f41302f MS |
3389 | /* If we do not now have two constants being compared, see |
3390 | if we can nevertheless deduce some things about the | |
3391 | comparison. */ | |
7afe21cc RK |
3392 | if (const_arg0 == 0 || const_arg1 == 0) |
3393 | { | |
08678f51 HPN |
3394 | if (const_arg1 != NULL) |
3395 | { | |
3396 | rtx cheapest_simplification; | |
3397 | int cheapest_cost; | |
3398 | rtx simp_result; | |
3399 | struct table_elt *p; | |
3400 | ||
3401 | /* See if we can find an equivalent of folded_arg0 | |
3402 | that gets us a cheaper expression, possibly a | |
3403 | constant through simplifications. */ | |
3404 | p = lookup (folded_arg0, SAFE_HASH (folded_arg0, mode_arg0), | |
3405 | mode_arg0); | |
b8698a0f | 3406 | |
08678f51 HPN |
3407 | if (p != NULL) |
3408 | { | |
3409 | cheapest_simplification = x; | |
e548c9df | 3410 | cheapest_cost = COST (x, mode); |
08678f51 HPN |
3411 | |
3412 | for (p = p->first_same_value; p != NULL; p = p->next_same_value) | |
3413 | { | |
3414 | int cost; | |
3415 | ||
3416 | /* If the entry isn't valid, skip it. */ | |
3417 | if (! exp_equiv_p (p->exp, p->exp, 1, false)) | |
3418 | continue; | |
3419 | ||
3420 | /* Try to simplify using this equivalence. */ | |
3421 | simp_result | |
3422 | = simplify_relational_operation (code, mode, | |
3423 | mode_arg0, | |
3424 | p->exp, | |
3425 | const_arg1); | |
3426 | ||
3427 | if (simp_result == NULL) | |
3428 | continue; | |
3429 | ||
e548c9df | 3430 | cost = COST (simp_result, mode); |
08678f51 HPN |
3431 | if (cost < cheapest_cost) |
3432 | { | |
3433 | cheapest_cost = cost; | |
3434 | cheapest_simplification = simp_result; | |
3435 | } | |
3436 | } | |
3437 | ||
3438 | /* If we have a cheaper expression now, use that | |
3439 | and try folding it further, from the top. */ | |
3440 | if (cheapest_simplification != x) | |
7903b3e5 JH |
3441 | return fold_rtx (copy_rtx (cheapest_simplification), |
3442 | insn); | |
08678f51 HPN |
3443 | } |
3444 | } | |
3445 | ||
fd13313f JH |
3446 | /* See if the two operands are the same. */ |
3447 | ||
39641489 PB |
3448 | if ((REG_P (folded_arg0) |
3449 | && REG_P (folded_arg1) | |
3450 | && (REG_QTY (REGNO (folded_arg0)) | |
3451 | == REG_QTY (REGNO (folded_arg1)))) | |
fd13313f | 3452 | || ((p0 = lookup (folded_arg0, |
0516f6fe SB |
3453 | SAFE_HASH (folded_arg0, mode_arg0), |
3454 | mode_arg0)) | |
fd13313f | 3455 | && (p1 = lookup (folded_arg1, |
0516f6fe SB |
3456 | SAFE_HASH (folded_arg1, mode_arg0), |
3457 | mode_arg0)) | |
fd13313f | 3458 | && p0->first_same_value == p1->first_same_value)) |
39641489 | 3459 | folded_arg1 = folded_arg0; |
7afe21cc RK |
3460 | |
3461 | /* If FOLDED_ARG0 is a register, see if the comparison we are | |
3462 | doing now is either the same as we did before or the reverse | |
3463 | (we only check the reverse if not floating-point). */ | |
f8cfc6aa | 3464 | else if (REG_P (folded_arg0)) |
7afe21cc | 3465 | { |
30f72379 | 3466 | int qty = REG_QTY (REGNO (folded_arg0)); |
7afe21cc | 3467 | |
1bb98cec DM |
3468 | if (REGNO_QTY_VALID_P (REGNO (folded_arg0))) |
3469 | { | |
3470 | struct qty_table_elem *ent = &qty_table[qty]; | |
3471 | ||
3472 | if ((comparison_dominates_p (ent->comparison_code, code) | |
1eb8759b RH |
3473 | || (! FLOAT_MODE_P (mode_arg0) |
3474 | && comparison_dominates_p (ent->comparison_code, | |
3475 | reverse_condition (code)))) | |
1bb98cec DM |
3476 | && (rtx_equal_p (ent->comparison_const, folded_arg1) |
3477 | || (const_arg1 | |
3478 | && rtx_equal_p (ent->comparison_const, | |
3479 | const_arg1)) | |
f8cfc6aa | 3480 | || (REG_P (folded_arg1) |
1bb98cec | 3481 | && (REG_QTY (REGNO (folded_arg1)) == ent->comparison_qty)))) |
9e6a14a4 L |
3482 | { |
3483 | if (comparison_dominates_p (ent->comparison_code, code)) | |
3484 | { | |
3485 | if (true_rtx) | |
3486 | return true_rtx; | |
3487 | else | |
3488 | break; | |
3489 | } | |
3490 | else | |
3491 | return false_rtx; | |
3492 | } | |
1bb98cec | 3493 | } |
7afe21cc RK |
3494 | } |
3495 | } | |
3496 | } | |
3497 | ||
3498 | /* If we are comparing against zero, see if the first operand is | |
3499 | equivalent to an IOR with a constant. If so, we may be able to | |
3500 | determine the result of this comparison. */ | |
39641489 | 3501 | if (const_arg1 == const0_rtx && !const_arg0) |
7afe21cc RK |
3502 | { |
3503 | rtx y = lookup_as_function (folded_arg0, IOR); | |
3504 | rtx inner_const; | |
3505 | ||
3506 | if (y != 0 | |
3507 | && (inner_const = equiv_constant (XEXP (y, 1))) != 0 | |
481683e1 | 3508 | && CONST_INT_P (inner_const) |
7afe21cc | 3509 | && INTVAL (inner_const) != 0) |
39641489 | 3510 | folded_arg0 = gen_rtx_IOR (mode_arg0, XEXP (y, 0), inner_const); |
7afe21cc RK |
3511 | } |
3512 | ||
c6fb08ad | 3513 | { |
bca3cc97 JJ |
3514 | rtx op0 = const_arg0 ? const_arg0 : copy_rtx (folded_arg0); |
3515 | rtx op1 = const_arg1 ? const_arg1 : copy_rtx (folded_arg1); | |
3516 | new_rtx = simplify_relational_operation (code, mode, mode_arg0, | |
3517 | op0, op1); | |
c6fb08ad | 3518 | } |
7afe21cc RK |
3519 | break; |
3520 | ||
ec8e098d PB |
3521 | case RTX_BIN_ARITH: |
3522 | case RTX_COMM_ARITH: | |
7afe21cc RK |
3523 | switch (code) |
3524 | { | |
3525 | case PLUS: | |
3526 | /* If the second operand is a LABEL_REF, see if the first is a MINUS | |
3527 | with that LABEL_REF as its second operand. If so, the result is | |
3528 | the first operand of that MINUS. This handles switches with an | |
3529 | ADDR_DIFF_VEC table. */ | |
3530 | if (const_arg1 && GET_CODE (const_arg1) == LABEL_REF) | |
3531 | { | |
e650cbda RK |
3532 | rtx y |
3533 | = GET_CODE (folded_arg0) == MINUS ? folded_arg0 | |
ddc356e8 | 3534 | : lookup_as_function (folded_arg0, MINUS); |
7afe21cc RK |
3535 | |
3536 | if (y != 0 && GET_CODE (XEXP (y, 1)) == LABEL_REF | |
04a121a7 | 3537 | && label_ref_label (XEXP (y, 1)) == label_ref_label (const_arg1)) |
7afe21cc | 3538 | return XEXP (y, 0); |
67a37737 RK |
3539 | |
3540 | /* Now try for a CONST of a MINUS like the above. */ | |
e650cbda RK |
3541 | if ((y = (GET_CODE (folded_arg0) == CONST ? folded_arg0 |
3542 | : lookup_as_function (folded_arg0, CONST))) != 0 | |
67a37737 RK |
3543 | && GET_CODE (XEXP (y, 0)) == MINUS |
3544 | && GET_CODE (XEXP (XEXP (y, 0), 1)) == LABEL_REF | |
04a121a7 | 3545 | && label_ref_label (XEXP (XEXP (y, 0), 1)) == label_ref_label (const_arg1)) |
67a37737 | 3546 | return XEXP (XEXP (y, 0), 0); |
7afe21cc | 3547 | } |
c2cc0778 | 3548 | |
e650cbda RK |
3549 | /* Likewise if the operands are in the other order. */ |
3550 | if (const_arg0 && GET_CODE (const_arg0) == LABEL_REF) | |
3551 | { | |
3552 | rtx y | |
3553 | = GET_CODE (folded_arg1) == MINUS ? folded_arg1 | |
ddc356e8 | 3554 | : lookup_as_function (folded_arg1, MINUS); |
e650cbda RK |
3555 | |
3556 | if (y != 0 && GET_CODE (XEXP (y, 1)) == LABEL_REF | |
04a121a7 | 3557 | && label_ref_label (XEXP (y, 1)) == label_ref_label (const_arg0)) |
e650cbda RK |
3558 | return XEXP (y, 0); |
3559 | ||
3560 | /* Now try for a CONST of a MINUS like the above. */ | |
3561 | if ((y = (GET_CODE (folded_arg1) == CONST ? folded_arg1 | |
3562 | : lookup_as_function (folded_arg1, CONST))) != 0 | |
3563 | && GET_CODE (XEXP (y, 0)) == MINUS | |
3564 | && GET_CODE (XEXP (XEXP (y, 0), 1)) == LABEL_REF | |
04a121a7 | 3565 | && label_ref_label (XEXP (XEXP (y, 0), 1)) == label_ref_label (const_arg0)) |
e650cbda RK |
3566 | return XEXP (XEXP (y, 0), 0); |
3567 | } | |
3568 | ||
c2cc0778 RK |
3569 | /* If second operand is a register equivalent to a negative |
3570 | CONST_INT, see if we can find a register equivalent to the | |
3571 | positive constant. Make a MINUS if so. Don't do this for | |
5d595063 | 3572 | a non-negative constant since we might then alternate between |
a1f300c0 | 3573 | choosing positive and negative constants. Having the positive |
5d595063 RK |
3574 | constant previously-used is the more common case. Be sure |
3575 | the resulting constant is non-negative; if const_arg1 were | |
3576 | the smallest negative number this would overflow: depending | |
3577 | on the mode, this would either just be the same value (and | |
3578 | hence not save anything) or be incorrect. */ | |
481683e1 | 3579 | if (const_arg1 != 0 && CONST_INT_P (const_arg1) |
5d595063 | 3580 | && INTVAL (const_arg1) < 0 |
4741f6ad JL |
3581 | /* This used to test |
3582 | ||
ddc356e8 | 3583 | -INTVAL (const_arg1) >= 0 |
4741f6ad JL |
3584 | |
3585 | But The Sun V5.0 compilers mis-compiled that test. So | |
3586 | instead we test for the problematic value in a more direct | |
3587 | manner and hope the Sun compilers get it correct. */ | |
5c45a8ac | 3588 | && INTVAL (const_arg1) != |
fecfbfa4 | 3589 | (HOST_WIDE_INT_1 << (HOST_BITS_PER_WIDE_INT - 1)) |
f8cfc6aa | 3590 | && REG_P (folded_arg1)) |
c2cc0778 | 3591 | { |
ddc356e8 | 3592 | rtx new_const = GEN_INT (-INTVAL (const_arg1)); |
c2cc0778 | 3593 | struct table_elt *p |
0516f6fe | 3594 | = lookup (new_const, SAFE_HASH (new_const, mode), mode); |
c2cc0778 RK |
3595 | |
3596 | if (p) | |
3597 | for (p = p->first_same_value; p; p = p->next_same_value) | |
f8cfc6aa | 3598 | if (REG_P (p->exp)) |
0cedb36c | 3599 | return simplify_gen_binary (MINUS, mode, folded_arg0, |
20468884 | 3600 | canon_reg (p->exp, NULL)); |
c2cc0778 | 3601 | } |
13c9910f RS |
3602 | goto from_plus; |
3603 | ||
3604 | case MINUS: | |
3605 | /* If we have (MINUS Y C), see if Y is known to be (PLUS Z C2). | |
3606 | If so, produce (PLUS Z C2-C). */ | |
5284e559 | 3607 | if (const_arg1 != 0 && poly_int_rtx_p (const_arg1, &xval)) |
13c9910f RS |
3608 | { |
3609 | rtx y = lookup_as_function (XEXP (x, 0), PLUS); | |
5284e559 RS |
3610 | if (y && poly_int_rtx_p (XEXP (y, 1))) |
3611 | return fold_rtx (plus_constant (mode, copy_rtx (y), -xval), | |
20468884 | 3612 | NULL); |
13c9910f | 3613 | } |
7afe21cc | 3614 | |
ddc356e8 | 3615 | /* Fall through. */ |
7afe21cc | 3616 | |
13c9910f | 3617 | from_plus: |
7afe21cc RK |
3618 | case SMIN: case SMAX: case UMIN: case UMAX: |
3619 | case IOR: case AND: case XOR: | |
f930bfd0 | 3620 | case MULT: |
7afe21cc RK |
3621 | case ASHIFT: case LSHIFTRT: case ASHIFTRT: |
3622 | /* If we have (<op> <reg> <const_int>) for an associative OP and REG | |
3623 | is known to be of similar form, we may be able to replace the | |
3624 | operation with a combined operation. This may eliminate the | |
3625 | intermediate operation if every use is simplified in this way. | |
3626 | Note that the similar optimization done by combine.c only works | |
3627 | if the intermediate operation's result has only one reference. */ | |
3628 | ||
f8cfc6aa | 3629 | if (REG_P (folded_arg0) |
481683e1 | 3630 | && const_arg1 && CONST_INT_P (const_arg1)) |
7afe21cc RK |
3631 | { |
3632 | int is_shift | |
3633 | = (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT); | |
5bb51e1d | 3634 | rtx y, inner_const, new_const; |
39b2ac74 | 3635 | rtx canon_const_arg1 = const_arg1; |
7afe21cc | 3636 | enum rtx_code associate_code; |
7afe21cc | 3637 | |
824a4527 | 3638 | if (is_shift |
bb06a2d8 | 3639 | && (INTVAL (const_arg1) >= GET_MODE_UNIT_PRECISION (mode) |
824a4527 JDA |
3640 | || INTVAL (const_arg1) < 0)) |
3641 | { | |
3642 | if (SHIFT_COUNT_TRUNCATED) | |
abd3c800 RS |
3643 | canon_const_arg1 = gen_int_shift_amount |
3644 | (mode, (INTVAL (const_arg1) | |
3645 | & (GET_MODE_UNIT_BITSIZE (mode) - 1))); | |
824a4527 JDA |
3646 | else |
3647 | break; | |
3648 | } | |
3649 | ||
5bb51e1d | 3650 | y = lookup_as_function (folded_arg0, code); |
824a4527 JDA |
3651 | if (y == 0) |
3652 | break; | |
824a4527 JDA |
3653 | |
3654 | /* If we have compiled a statement like | |
3655 | "if (x == (x & mask1))", and now are looking at | |
3656 | "x & mask2", we will have a case where the first operand | |
3657 | of Y is the same as our first operand. Unless we detect | |
3658 | this case, an infinite loop will result. */ | |
3659 | if (XEXP (y, 0) == folded_arg0) | |
7afe21cc RK |
3660 | break; |
3661 | ||
5bb51e1d | 3662 | inner_const = equiv_constant (fold_rtx (XEXP (y, 1), 0)); |
481683e1 | 3663 | if (!inner_const || !CONST_INT_P (inner_const)) |
5bb51e1d EB |
3664 | break; |
3665 | ||
7afe21cc RK |
3666 | /* Don't associate these operations if they are a PLUS with the |
3667 | same constant and it is a power of two. These might be doable | |
3668 | with a pre- or post-increment. Similarly for two subtracts of | |
3669 | identical powers of two with post decrement. */ | |
3670 | ||
213d5fbc | 3671 | if (code == PLUS && const_arg1 == inner_const |
940da324 | 3672 | && ((HAVE_PRE_INCREMENT |
146ec50f | 3673 | && pow2p_hwi (INTVAL (const_arg1))) |
940da324 | 3674 | || (HAVE_POST_INCREMENT |
146ec50f | 3675 | && pow2p_hwi (INTVAL (const_arg1))) |
940da324 | 3676 | || (HAVE_PRE_DECREMENT |
146ec50f | 3677 | && pow2p_hwi (- INTVAL (const_arg1))) |
940da324 | 3678 | || (HAVE_POST_DECREMENT |
146ec50f | 3679 | && pow2p_hwi (- INTVAL (const_arg1))))) |
7afe21cc RK |
3680 | break; |
3681 | ||
88057dc8 UB |
3682 | /* ??? Vector mode shifts by scalar |
3683 | shift operand are not supported yet. */ | |
3684 | if (is_shift && VECTOR_MODE_P (mode)) | |
3685 | break; | |
3686 | ||
824a4527 | 3687 | if (is_shift |
bb06a2d8 | 3688 | && (INTVAL (inner_const) >= GET_MODE_UNIT_PRECISION (mode) |
824a4527 JDA |
3689 | || INTVAL (inner_const) < 0)) |
3690 | { | |
3691 | if (SHIFT_COUNT_TRUNCATED) | |
abd3c800 RS |
3692 | inner_const = gen_int_shift_amount |
3693 | (mode, (INTVAL (inner_const) | |
3694 | & (GET_MODE_UNIT_BITSIZE (mode) - 1))); | |
824a4527 JDA |
3695 | else |
3696 | break; | |
3697 | } | |
3698 | ||
7afe21cc | 3699 | /* Compute the code used to compose the constants. For example, |
f930bfd0 | 3700 | A-C1-C2 is A-(C1 + C2), so if CODE == MINUS, we want PLUS. */ |
7afe21cc | 3701 | |
f930bfd0 | 3702 | associate_code = (is_shift || code == MINUS ? PLUS : code); |
7afe21cc RK |
3703 | |
3704 | new_const = simplify_binary_operation (associate_code, mode, | |
39b2ac74 JJ |
3705 | canon_const_arg1, |
3706 | inner_const); | |
7afe21cc RK |
3707 | |
3708 | if (new_const == 0) | |
3709 | break; | |
3710 | ||
3711 | /* If we are associating shift operations, don't let this | |
4908e508 RS |
3712 | produce a shift of the size of the object or larger. |
3713 | This could occur when we follow a sign-extend by a right | |
3714 | shift on a machine that does a sign-extend as a pair | |
3715 | of shifts. */ | |
7afe21cc | 3716 | |
824a4527 | 3717 | if (is_shift |
481683e1 | 3718 | && CONST_INT_P (new_const) |
bb06a2d8 | 3719 | && INTVAL (new_const) >= GET_MODE_UNIT_PRECISION (mode)) |
4908e508 RS |
3720 | { |
3721 | /* As an exception, we can turn an ASHIFTRT of this | |
3722 | form into a shift of the number of bits - 1. */ | |
3723 | if (code == ASHIFTRT) | |
abd3c800 RS |
3724 | new_const = gen_int_shift_amount |
3725 | (mode, GET_MODE_UNIT_BITSIZE (mode) - 1); | |
824a4527 JDA |
3726 | else if (!side_effects_p (XEXP (y, 0))) |
3727 | return CONST0_RTX (mode); | |
4908e508 RS |
3728 | else |
3729 | break; | |
3730 | } | |
7afe21cc RK |
3731 | |
3732 | y = copy_rtx (XEXP (y, 0)); | |
3733 | ||
3734 | /* If Y contains our first operand (the most common way this | |
3735 | can happen is if Y is a MEM), we would do into an infinite | |
3736 | loop if we tried to fold it. So don't in that case. */ | |
3737 | ||
3738 | if (! reg_mentioned_p (folded_arg0, y)) | |
3739 | y = fold_rtx (y, insn); | |
3740 | ||
0cedb36c | 3741 | return simplify_gen_binary (code, mode, y, new_const); |
7afe21cc | 3742 | } |
e9a25f70 JL |
3743 | break; |
3744 | ||
f930bfd0 JW |
3745 | case DIV: case UDIV: |
3746 | /* ??? The associative optimization performed immediately above is | |
3747 | also possible for DIV and UDIV using associate_code of MULT. | |
3748 | However, we would need extra code to verify that the | |
3749 | multiplication does not overflow, that is, there is no overflow | |
3750 | in the calculation of new_const. */ | |
3751 | break; | |
3752 | ||
e9a25f70 JL |
3753 | default: |
3754 | break; | |
7afe21cc RK |
3755 | } |
3756 | ||
32e9fa48 | 3757 | new_rtx = simplify_binary_operation (code, mode, |
7afe21cc RK |
3758 | const_arg0 ? const_arg0 : folded_arg0, |
3759 | const_arg1 ? const_arg1 : folded_arg1); | |
3760 | break; | |
3761 | ||
ec8e098d | 3762 | case RTX_OBJ: |
7afe21cc RK |
3763 | /* (lo_sum (high X) X) is simply X. */ |
3764 | if (code == LO_SUM && const_arg0 != 0 | |
3765 | && GET_CODE (const_arg0) == HIGH | |
3766 | && rtx_equal_p (XEXP (const_arg0, 0), const_arg1)) | |
3767 | return const_arg1; | |
3768 | break; | |
3769 | ||
ec8e098d PB |
3770 | case RTX_TERNARY: |
3771 | case RTX_BITFIELD_OPS: | |
32e9fa48 | 3772 | new_rtx = simplify_ternary_operation (code, mode, mode_arg0, |
7afe21cc RK |
3773 | const_arg0 ? const_arg0 : folded_arg0, |
3774 | const_arg1 ? const_arg1 : folded_arg1, | |
3775 | const_arg2 ? const_arg2 : XEXP (x, 2)); | |
3776 | break; | |
ee5332b8 | 3777 | |
ec8e098d PB |
3778 | default: |
3779 | break; | |
7afe21cc RK |
3780 | } |
3781 | ||
32e9fa48 | 3782 | return new_rtx ? new_rtx : x; |
7afe21cc RK |
3783 | } |
3784 | \f | |
3785 | /* Return a constant value currently equivalent to X. | |
3786 | Return 0 if we don't know one. */ | |
3787 | ||
3788 | static rtx | |
7080f735 | 3789 | equiv_constant (rtx x) |
7afe21cc | 3790 | { |
f8cfc6aa | 3791 | if (REG_P (x) |
1bb98cec DM |
3792 | && REGNO_QTY_VALID_P (REGNO (x))) |
3793 | { | |
3794 | int x_q = REG_QTY (REGNO (x)); | |
3795 | struct qty_table_elem *x_ent = &qty_table[x_q]; | |
3796 | ||
3797 | if (x_ent->const_rtx) | |
4de249d9 | 3798 | x = gen_lowpart (GET_MODE (x), x_ent->const_rtx); |
1bb98cec | 3799 | } |
7afe21cc | 3800 | |
2ce5e1b4 | 3801 | if (x == 0 || CONSTANT_P (x)) |
7afe21cc RK |
3802 | return x; |
3803 | ||
a52b023a PB |
3804 | if (GET_CODE (x) == SUBREG) |
3805 | { | |
ef4bddc2 RS |
3806 | machine_mode mode = GET_MODE (x); |
3807 | machine_mode imode = GET_MODE (SUBREG_REG (x)); | |
32e9fa48 | 3808 | rtx new_rtx; |
a52b023a PB |
3809 | |
3810 | /* See if we previously assigned a constant value to this SUBREG. */ | |
32e9fa48 | 3811 | if ((new_rtx = lookup_as_function (x, CONST_INT)) != 0 |
807e902e | 3812 | || (new_rtx = lookup_as_function (x, CONST_WIDE_INT)) != 0 |
0c12fc9b RS |
3813 | || (NUM_POLY_INT_COEFFS > 1 |
3814 | && (new_rtx = lookup_as_function (x, CONST_POLY_INT)) != 0) | |
32e9fa48 KG |
3815 | || (new_rtx = lookup_as_function (x, CONST_DOUBLE)) != 0 |
3816 | || (new_rtx = lookup_as_function (x, CONST_FIXED)) != 0) | |
3817 | return new_rtx; | |
a52b023a | 3818 | |
f5f8d79d EB |
3819 | /* If we didn't and if doing so makes sense, see if we previously |
3820 | assigned a constant value to the enclosing word mode SUBREG. */ | |
cf098191 RS |
3821 | if (known_lt (GET_MODE_SIZE (mode), UNITS_PER_WORD) |
3822 | && known_lt (UNITS_PER_WORD, GET_MODE_SIZE (imode))) | |
f5f8d79d | 3823 | { |
91914e56 RS |
3824 | poly_int64 byte = (SUBREG_BYTE (x) |
3825 | - subreg_lowpart_offset (mode, word_mode)); | |
3826 | if (known_ge (byte, 0) && multiple_p (byte, UNITS_PER_WORD)) | |
f5f8d79d EB |
3827 | { |
3828 | rtx y = gen_rtx_SUBREG (word_mode, SUBREG_REG (x), byte); | |
3829 | new_rtx = lookup_as_function (y, CONST_INT); | |
3830 | if (new_rtx) | |
3831 | return gen_lowpart (mode, new_rtx); | |
3832 | } | |
3833 | } | |
3834 | ||
7cb6668a MI |
3835 | /* Otherwise see if we already have a constant for the inner REG, |
3836 | and if that is enough to calculate an equivalent constant for | |
3837 | the subreg. Note that the upper bits of paradoxical subregs | |
3838 | are undefined, so they cannot be said to equal anything. */ | |
a52b023a | 3839 | if (REG_P (SUBREG_REG (x)) |
03a95621 | 3840 | && !paradoxical_subreg_p (x) |
32e9fa48 | 3841 | && (new_rtx = equiv_constant (SUBREG_REG (x))) != 0) |
f5f8d79d | 3842 | return simplify_subreg (mode, new_rtx, imode, SUBREG_BYTE (x)); |
a52b023a PB |
3843 | |
3844 | return 0; | |
3845 | } | |
3846 | ||
3847 | /* If X is a MEM, see if it is a constant-pool reference, or look it up in | |
3848 | the hash table in case its value was seen before. */ | |
fc3ffe83 | 3849 | |
3c0cb5de | 3850 | if (MEM_P (x)) |
fc3ffe83 RK |
3851 | { |
3852 | struct table_elt *elt; | |
3853 | ||
a52b023a | 3854 | x = avoid_constant_pool_reference (x); |
fc3ffe83 RK |
3855 | if (CONSTANT_P (x)) |
3856 | return x; | |
3857 | ||
0516f6fe | 3858 | elt = lookup (x, SAFE_HASH (x, GET_MODE (x)), GET_MODE (x)); |
fc3ffe83 RK |
3859 | if (elt == 0) |
3860 | return 0; | |
3861 | ||
3862 | for (elt = elt->first_same_value; elt; elt = elt->next_same_value) | |
3863 | if (elt->is_const && CONSTANT_P (elt->exp)) | |
3864 | return elt->exp; | |
3865 | } | |
3866 | ||
7afe21cc RK |
3867 | return 0; |
3868 | } | |
3869 | \f | |
0129d079 SB |
3870 | /* Given INSN, a jump insn, TAKEN indicates if we are following the |
3871 | "taken" branch. | |
7afe21cc RK |
3872 | |
3873 | In certain cases, this can cause us to add an equivalence. For example, | |
278a83b2 | 3874 | if we are following the taken case of |
7080f735 | 3875 | if (i == 2) |
7afe21cc RK |
3876 | we can add the fact that `i' and '2' are now equivalent. |
3877 | ||
3878 | In any case, we can record that this comparison was passed. If the same | |
3879 | comparison is seen later, we will know its value. */ | |
3880 | ||
3881 | static void | |
20468884 | 3882 | record_jump_equiv (rtx_insn *insn, bool taken) |
7afe21cc RK |
3883 | { |
3884 | int cond_known_true; | |
3885 | rtx op0, op1; | |
7f1c097d | 3886 | rtx set; |
ef4bddc2 | 3887 | machine_mode mode, mode0, mode1; |
7afe21cc RK |
3888 | int reversed_nonequality = 0; |
3889 | enum rtx_code code; | |
3890 | ||
3891 | /* Ensure this is the right kind of insn. */ | |
0129d079 SB |
3892 | gcc_assert (any_condjump_p (insn)); |
3893 | ||
7f1c097d | 3894 | set = pc_set (insn); |
7afe21cc RK |
3895 | |
3896 | /* See if this jump condition is known true or false. */ | |
3897 | if (taken) | |
7f1c097d | 3898 | cond_known_true = (XEXP (SET_SRC (set), 2) == pc_rtx); |
7afe21cc | 3899 | else |
7f1c097d | 3900 | cond_known_true = (XEXP (SET_SRC (set), 1) == pc_rtx); |
7afe21cc RK |
3901 | |
3902 | /* Get the type of comparison being done and the operands being compared. | |
3903 | If we had to reverse a non-equality condition, record that fact so we | |
3904 | know that it isn't valid for floating-point. */ | |
7f1c097d JH |
3905 | code = GET_CODE (XEXP (SET_SRC (set), 0)); |
3906 | op0 = fold_rtx (XEXP (XEXP (SET_SRC (set), 0), 0), insn); | |
3907 | op1 = fold_rtx (XEXP (XEXP (SET_SRC (set), 0), 1), insn); | |
7afe21cc | 3908 | |
3f1d32a5 JL |
3909 | /* On a cc0 target the cc0-setter and cc0-user may end up in different |
3910 | blocks. When that happens the tracking of the cc0-setter via | |
3911 | PREV_INSN_CC0 is spoiled. That means that fold_rtx may return | |
3912 | NULL_RTX. In those cases, there's nothing to record. */ | |
3913 | if (op0 == NULL_RTX || op1 == NULL_RTX) | |
3914 | return; | |
3915 | ||
13c9910f | 3916 | code = find_comparison_args (code, &op0, &op1, &mode0, &mode1); |
7afe21cc RK |
3917 | if (! cond_known_true) |
3918 | { | |
261efdef | 3919 | code = reversed_comparison_code_parts (code, op0, op1, insn); |
1eb8759b RH |
3920 | |
3921 | /* Don't remember if we can't find the inverse. */ | |
3922 | if (code == UNKNOWN) | |
3923 | return; | |
7afe21cc RK |
3924 | } |
3925 | ||
3926 | /* The mode is the mode of the non-constant. */ | |
13c9910f RS |
3927 | mode = mode0; |
3928 | if (mode1 != VOIDmode) | |
3929 | mode = mode1; | |
7afe21cc RK |
3930 | |
3931 | record_jump_cond (code, mode, op0, op1, reversed_nonequality); | |
3932 | } | |
3933 | ||
794693c0 RH |
3934 | /* Yet another form of subreg creation. In this case, we want something in |
3935 | MODE, and we should assume OP has MODE iff it is naturally modeless. */ | |
3936 | ||
3937 | static rtx | |
ef4bddc2 | 3938 | record_jump_cond_subreg (machine_mode mode, rtx op) |
794693c0 | 3939 | { |
ef4bddc2 | 3940 | machine_mode op_mode = GET_MODE (op); |
794693c0 RH |
3941 | if (op_mode == mode || op_mode == VOIDmode) |
3942 | return op; | |
3943 | return lowpart_subreg (mode, op, op_mode); | |
3944 | } | |
3945 | ||
7afe21cc RK |
3946 | /* We know that comparison CODE applied to OP0 and OP1 in MODE is true. |
3947 | REVERSED_NONEQUALITY is nonzero if CODE had to be swapped. | |
3948 | Make any useful entries we can with that information. Called from | |
3949 | above function and called recursively. */ | |
3950 | ||
3951 | static void | |
ef4bddc2 | 3952 | record_jump_cond (enum rtx_code code, machine_mode mode, rtx op0, |
7080f735 | 3953 | rtx op1, int reversed_nonequality) |
7afe21cc | 3954 | { |
2197a88a | 3955 | unsigned op0_hash, op1_hash; |
e428d738 | 3956 | int op0_in_memory, op1_in_memory; |
7afe21cc RK |
3957 | struct table_elt *op0_elt, *op1_elt; |
3958 | ||
3959 | /* If OP0 and OP1 are known equal, and either is a paradoxical SUBREG, | |
3960 | we know that they are also equal in the smaller mode (this is also | |
3961 | true for all smaller modes whether or not there is a SUBREG, but | |
ac7ef8d5 | 3962 | is not worth testing for with no SUBREG). */ |
7afe21cc | 3963 | |
2e794ee8 | 3964 | /* Note that GET_MODE (op0) may not equal MODE. */ |
6a4bdc79 | 3965 | if (code == EQ && paradoxical_subreg_p (op0)) |
7afe21cc | 3966 | { |
ef4bddc2 | 3967 | machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); |
794693c0 RH |
3968 | rtx tem = record_jump_cond_subreg (inner_mode, op1); |
3969 | if (tem) | |
3970 | record_jump_cond (code, mode, SUBREG_REG (op0), tem, | |
3971 | reversed_nonequality); | |
7afe21cc RK |
3972 | } |
3973 | ||
6a4bdc79 | 3974 | if (code == EQ && paradoxical_subreg_p (op1)) |
7afe21cc | 3975 | { |
ef4bddc2 | 3976 | machine_mode inner_mode = GET_MODE (SUBREG_REG (op1)); |
794693c0 RH |
3977 | rtx tem = record_jump_cond_subreg (inner_mode, op0); |
3978 | if (tem) | |
3979 | record_jump_cond (code, mode, SUBREG_REG (op1), tem, | |
3980 | reversed_nonequality); | |
7afe21cc RK |
3981 | } |
3982 | ||
278a83b2 | 3983 | /* Similarly, if this is an NE comparison, and either is a SUBREG |
7afe21cc RK |
3984 | making a smaller mode, we know the whole thing is also NE. */ |
3985 | ||
2e794ee8 RS |
3986 | /* Note that GET_MODE (op0) may not equal MODE; |
3987 | if we test MODE instead, we can get an infinite recursion | |
3988 | alternating between two modes each wider than MODE. */ | |
3989 | ||
bd4288c0 RS |
3990 | if (code == NE |
3991 | && partial_subreg_p (op0) | |
3992 | && subreg_lowpart_p (op0)) | |
7afe21cc | 3993 | { |
ef4bddc2 | 3994 | machine_mode inner_mode = GET_MODE (SUBREG_REG (op0)); |
794693c0 RH |
3995 | rtx tem = record_jump_cond_subreg (inner_mode, op1); |
3996 | if (tem) | |
3997 | record_jump_cond (code, mode, SUBREG_REG (op0), tem, | |
3998 | reversed_nonequality); | |
7afe21cc RK |
3999 | } |
4000 | ||
bd4288c0 RS |
4001 | if (code == NE |
4002 | && partial_subreg_p (op1) | |
4003 | && subreg_lowpart_p (op1)) | |
7afe21cc | 4004 | { |
ef4bddc2 | 4005 | machine_mode inner_mode = GET_MODE (SUBREG_REG (op1)); |
794693c0 RH |
4006 | rtx tem = record_jump_cond_subreg (inner_mode, op0); |
4007 | if (tem) | |
4008 | record_jump_cond (code, mode, SUBREG_REG (op1), tem, | |
4009 | reversed_nonequality); | |
7afe21cc RK |
4010 | } |
4011 | ||
4012 | /* Hash both operands. */ | |
4013 | ||
4014 | do_not_record = 0; | |
4015 | hash_arg_in_memory = 0; | |
2197a88a | 4016 | op0_hash = HASH (op0, mode); |
7afe21cc | 4017 | op0_in_memory = hash_arg_in_memory; |
7afe21cc RK |
4018 | |
4019 | if (do_not_record) | |
4020 | return; | |
4021 | ||
4022 | do_not_record = 0; | |
4023 | hash_arg_in_memory = 0; | |
2197a88a | 4024 | op1_hash = HASH (op1, mode); |
7afe21cc | 4025 | op1_in_memory = hash_arg_in_memory; |
278a83b2 | 4026 | |
7afe21cc RK |
4027 | if (do_not_record) |
4028 | return; | |
4029 | ||
4030 | /* Look up both operands. */ | |
2197a88a RK |
4031 | op0_elt = lookup (op0, op0_hash, mode); |
4032 | op1_elt = lookup (op1, op1_hash, mode); | |
7afe21cc | 4033 | |
af3869c1 RK |
4034 | /* If both operands are already equivalent or if they are not in the |
4035 | table but are identical, do nothing. */ | |
4036 | if ((op0_elt != 0 && op1_elt != 0 | |
4037 | && op0_elt->first_same_value == op1_elt->first_same_value) | |
4038 | || op0 == op1 || rtx_equal_p (op0, op1)) | |
4039 | return; | |
4040 | ||
7afe21cc | 4041 | /* If we aren't setting two things equal all we can do is save this |
b2796a4b RK |
4042 | comparison. Similarly if this is floating-point. In the latter |
4043 | case, OP1 might be zero and both -0.0 and 0.0 are equal to it. | |
4044 | If we record the equality, we might inadvertently delete code | |
4045 | whose intent was to change -0 to +0. */ | |
4046 | ||
cbf6a543 | 4047 | if (code != EQ || FLOAT_MODE_P (GET_MODE (op0))) |
7afe21cc | 4048 | { |
1bb98cec DM |
4049 | struct qty_table_elem *ent; |
4050 | int qty; | |
4051 | ||
7afe21cc RK |
4052 | /* If we reversed a floating-point comparison, if OP0 is not a |
4053 | register, or if OP1 is neither a register or constant, we can't | |
4054 | do anything. */ | |
4055 | ||
f8cfc6aa | 4056 | if (!REG_P (op1)) |
7afe21cc RK |
4057 | op1 = equiv_constant (op1); |
4058 | ||
cbf6a543 | 4059 | if ((reversed_nonequality && FLOAT_MODE_P (mode)) |
f8cfc6aa | 4060 | || !REG_P (op0) || op1 == 0) |
7afe21cc RK |
4061 | return; |
4062 | ||
4063 | /* Put OP0 in the hash table if it isn't already. This gives it a | |
4064 | new quantity number. */ | |
4065 | if (op0_elt == 0) | |
4066 | { | |
9714cf43 | 4067 | if (insert_regs (op0, NULL, 0)) |
7afe21cc RK |
4068 | { |
4069 | rehash_using_reg (op0); | |
2197a88a | 4070 | op0_hash = HASH (op0, mode); |
2bb81c86 RK |
4071 | |
4072 | /* If OP0 is contained in OP1, this changes its hash code | |
4073 | as well. Faster to rehash than to check, except | |
4074 | for the simple case of a constant. */ | |
4075 | if (! CONSTANT_P (op1)) | |
2197a88a | 4076 | op1_hash = HASH (op1,mode); |
7afe21cc RK |
4077 | } |
4078 | ||
9714cf43 | 4079 | op0_elt = insert (op0, NULL, op0_hash, mode); |
7afe21cc | 4080 | op0_elt->in_memory = op0_in_memory; |
7afe21cc RK |
4081 | } |
4082 | ||
1bb98cec DM |
4083 | qty = REG_QTY (REGNO (op0)); |
4084 | ent = &qty_table[qty]; | |
4085 | ||
4086 | ent->comparison_code = code; | |
f8cfc6aa | 4087 | if (REG_P (op1)) |
7afe21cc | 4088 | { |
5d5ea909 | 4089 | /* Look it up again--in case op0 and op1 are the same. */ |
2197a88a | 4090 | op1_elt = lookup (op1, op1_hash, mode); |
5d5ea909 | 4091 | |
7afe21cc RK |
4092 | /* Put OP1 in the hash table so it gets a new quantity number. */ |
4093 | if (op1_elt == 0) | |
4094 | { | |
9714cf43 | 4095 | if (insert_regs (op1, NULL, 0)) |
7afe21cc RK |
4096 | { |
4097 | rehash_using_reg (op1); | |
2197a88a | 4098 | op1_hash = HASH (op1, mode); |
7afe21cc RK |
4099 | } |
4100 | ||
9714cf43 | 4101 | op1_elt = insert (op1, NULL, op1_hash, mode); |
7afe21cc | 4102 | op1_elt->in_memory = op1_in_memory; |
7afe21cc RK |
4103 | } |
4104 | ||
1bb98cec DM |
4105 | ent->comparison_const = NULL_RTX; |
4106 | ent->comparison_qty = REG_QTY (REGNO (op1)); | |
7afe21cc RK |
4107 | } |
4108 | else | |
4109 | { | |
1bb98cec DM |
4110 | ent->comparison_const = op1; |
4111 | ent->comparison_qty = -1; | |
7afe21cc RK |
4112 | } |
4113 | ||
4114 | return; | |
4115 | } | |
4116 | ||
eb5ad42a RS |
4117 | /* If either side is still missing an equivalence, make it now, |
4118 | then merge the equivalences. */ | |
7afe21cc | 4119 | |
7afe21cc RK |
4120 | if (op0_elt == 0) |
4121 | { | |
9714cf43 | 4122 | if (insert_regs (op0, NULL, 0)) |
7afe21cc RK |
4123 | { |
4124 | rehash_using_reg (op0); | |
2197a88a | 4125 | op0_hash = HASH (op0, mode); |
7afe21cc RK |
4126 | } |
4127 | ||
9714cf43 | 4128 | op0_elt = insert (op0, NULL, op0_hash, mode); |
7afe21cc | 4129 | op0_elt->in_memory = op0_in_memory; |
7afe21cc RK |
4130 | } |
4131 | ||
4132 | if (op1_elt == 0) | |
4133 | { | |
9714cf43 | 4134 | if (insert_regs (op1, NULL, 0)) |
7afe21cc RK |
4135 | { |
4136 | rehash_using_reg (op1); | |
2197a88a | 4137 | op1_hash = HASH (op1, mode); |
7afe21cc RK |
4138 | } |
4139 | ||
9714cf43 | 4140 | op1_elt = insert (op1, NULL, op1_hash, mode); |
7afe21cc | 4141 | op1_elt->in_memory = op1_in_memory; |
7afe21cc | 4142 | } |
eb5ad42a RS |
4143 | |
4144 | merge_equiv_classes (op0_elt, op1_elt); | |
7afe21cc RK |
4145 | } |
4146 | \f | |
4147 | /* CSE processing for one instruction. | |
7b02f4e0 SB |
4148 | |
4149 | Most "true" common subexpressions are mostly optimized away in GIMPLE, | |
4150 | but the few that "leak through" are cleaned up by cse_insn, and complex | |
4151 | addressing modes are often formed here. | |
4152 | ||
4153 | The main function is cse_insn, and between here and that function | |
4154 | a couple of helper functions is defined to keep the size of cse_insn | |
4155 | within reasonable proportions. | |
4156 | ||
4157 | Data is shared between the main and helper functions via STRUCT SET, | |
4158 | that contains all data related for every set in the instruction that | |
4159 | is being processed. | |
4160 | ||
4161 | Note that cse_main processes all sets in the instruction. Most | |
4162 | passes in GCC only process simple SET insns or single_set insns, but | |
4163 | CSE processes insns with multiple sets as well. */ | |
7afe21cc RK |
4164 | |
4165 | /* Data on one SET contained in the instruction. */ | |
4166 | ||
4167 | struct set | |
4168 | { | |
4169 | /* The SET rtx itself. */ | |
4170 | rtx rtl; | |
4171 | /* The SET_SRC of the rtx (the original value, if it is changing). */ | |
4172 | rtx src; | |
4173 | /* The hash-table element for the SET_SRC of the SET. */ | |
4174 | struct table_elt *src_elt; | |
2197a88a RK |
4175 | /* Hash value for the SET_SRC. */ |
4176 | unsigned src_hash; | |
4177 | /* Hash value for the SET_DEST. */ | |
4178 | unsigned dest_hash; | |
7afe21cc RK |
4179 | /* The SET_DEST, with SUBREG, etc., stripped. */ |
4180 | rtx inner_dest; | |
278a83b2 | 4181 | /* Nonzero if the SET_SRC is in memory. */ |
7afe21cc | 4182 | char src_in_memory; |
7afe21cc RK |
4183 | /* Nonzero if the SET_SRC contains something |
4184 | whose value cannot be predicted and understood. */ | |
4185 | char src_volatile; | |
496324d0 DN |
4186 | /* Original machine mode, in case it becomes a CONST_INT. |
4187 | The size of this field should match the size of the mode | |
4188 | field of struct rtx_def (see rtl.h). */ | |
4189 | ENUM_BITFIELD(machine_mode) mode : 8; | |
2197a88a RK |
4190 | /* Hash value of constant equivalent for SET_SRC. */ |
4191 | unsigned src_const_hash; | |
34e82342 RB |
4192 | /* A constant equivalent for SET_SRC, if any. */ |
4193 | rtx src_const; | |
7afe21cc RK |
4194 | /* Table entry for constant equivalent for SET_SRC, if any. */ |
4195 | struct table_elt *src_const_elt; | |
05c433f3 PB |
4196 | /* Table entry for the destination address. */ |
4197 | struct table_elt *dest_addr_elt; | |
7afe21cc | 4198 | }; |
7b02f4e0 SB |
4199 | \f |
4200 | /* Special handling for (set REG0 REG1) where REG0 is the | |
4201 | "cheapest", cheaper than REG1. After cse, REG1 will probably not | |
4202 | be used in the sequel, so (if easily done) change this insn to | |
4203 | (set REG1 REG0) and replace REG1 with REG0 in the previous insn | |
4204 | that computed their value. Then REG1 will become a dead store | |
4205 | and won't cloud the situation for later optimizations. | |
4206 | ||
4207 | Do not make this change if REG1 is a hard register, because it will | |
4208 | then be used in the sequel and we may be changing a two-operand insn | |
4209 | into a three-operand insn. | |
4210 | ||
4211 | This is the last transformation that cse_insn will try to do. */ | |
7afe21cc RK |
4212 | |
4213 | static void | |
20468884 | 4214 | try_back_substitute_reg (rtx set, rtx_insn *insn) |
7afe21cc | 4215 | { |
7b02f4e0 SB |
4216 | rtx dest = SET_DEST (set); |
4217 | rtx src = SET_SRC (set); | |
7afe21cc | 4218 | |
7b02f4e0 SB |
4219 | if (REG_P (dest) |
4220 | && REG_P (src) && ! HARD_REGISTER_P (src) | |
4221 | && REGNO_QTY_VALID_P (REGNO (src))) | |
4222 | { | |
4223 | int src_q = REG_QTY (REGNO (src)); | |
4224 | struct qty_table_elem *src_ent = &qty_table[src_q]; | |
7afe21cc | 4225 | |
7b02f4e0 SB |
4226 | if (src_ent->first_reg == REGNO (dest)) |
4227 | { | |
4228 | /* Scan for the previous nonnote insn, but stop at a basic | |
4229 | block boundary. */ | |
20468884 DM |
4230 | rtx_insn *prev = insn; |
4231 | rtx_insn *bb_head = BB_HEAD (BLOCK_FOR_INSN (insn)); | |
7b02f4e0 SB |
4232 | do |
4233 | { | |
4234 | prev = PREV_INSN (prev); | |
4235 | } | |
4236 | while (prev != bb_head && (NOTE_P (prev) || DEBUG_INSN_P (prev))); | |
7afe21cc | 4237 | |
7b02f4e0 SB |
4238 | /* Do not swap the registers around if the previous instruction |
4239 | attaches a REG_EQUIV note to REG1. | |
7afe21cc | 4240 | |
7b02f4e0 SB |
4241 | ??? It's not entirely clear whether we can transfer a REG_EQUIV |
4242 | from the pseudo that originally shadowed an incoming argument | |
4243 | to another register. Some uses of REG_EQUIV might rely on it | |
4244 | being attached to REG1 rather than REG2. | |
7afe21cc | 4245 | |
7b02f4e0 SB |
4246 | This section previously turned the REG_EQUIV into a REG_EQUAL |
4247 | note. We cannot do that because REG_EQUIV may provide an | |
4248 | uninitialized stack slot when REG_PARM_STACK_SPACE is used. */ | |
4249 | if (NONJUMP_INSN_P (prev) | |
4250 | && GET_CODE (PATTERN (prev)) == SET | |
4251 | && SET_DEST (PATTERN (prev)) == src | |
4252 | && ! find_reg_note (prev, REG_EQUIV, NULL_RTX)) | |
4253 | { | |
4254 | rtx note; | |
4255 | ||
4256 | validate_change (prev, &SET_DEST (PATTERN (prev)), dest, 1); | |
4257 | validate_change (insn, &SET_DEST (set), src, 1); | |
4258 | validate_change (insn, &SET_SRC (set), dest, 1); | |
4259 | apply_change_group (); | |
4260 | ||
4261 | /* If INSN has a REG_EQUAL note, and this note mentions | |
4262 | REG0, then we must delete it, because the value in | |
4263 | REG0 has changed. If the note's value is REG1, we must | |
4264 | also delete it because that is now this insn's dest. */ | |
4265 | note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
4266 | if (note != 0 | |
4267 | && (reg_mentioned_p (dest, XEXP (note, 0)) | |
4268 | || rtx_equal_p (src, XEXP (note, 0)))) | |
4269 | remove_note (insn, note); | |
966a140d JL |
4270 | |
4271 | /* If INSN has a REG_ARGS_SIZE note, move it to PREV. */ | |
4272 | note = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX); | |
4273 | if (note != 0) | |
4274 | { | |
4275 | remove_note (insn, note); | |
4276 | gcc_assert (!find_reg_note (prev, REG_ARGS_SIZE, NULL_RTX)); | |
4277 | set_unique_reg_note (prev, REG_ARGS_SIZE, XEXP (note, 0)); | |
4278 | } | |
7b02f4e0 | 4279 | } |
f474c6f8 | 4280 | } |
f1e7c95f | 4281 | } |
7b02f4e0 SB |
4282 | } |
4283 | \f | |
4284 | /* Record all the SETs in this instruction into SETS_PTR, | |
4285 | and return the number of recorded sets. */ | |
4286 | static int | |
20468884 | 4287 | find_sets_in_insn (rtx_insn *insn, struct set **psets) |
7b02f4e0 SB |
4288 | { |
4289 | struct set *sets = *psets; | |
4290 | int n_sets = 0; | |
4291 | rtx x = PATTERN (insn); | |
f1e7c95f | 4292 | |
7afe21cc RK |
4293 | if (GET_CODE (x) == SET) |
4294 | { | |
7afe21cc RK |
4295 | /* Ignore SETs that are unconditional jumps. |
4296 | They never need cse processing, so this does not hurt. | |
4297 | The reason is not efficiency but rather | |
4298 | so that we can test at the end for instructions | |
4299 | that have been simplified to unconditional jumps | |
4300 | and not be misled by unchanged instructions | |
4301 | that were unconditional jumps to begin with. */ | |
4302 | if (SET_DEST (x) == pc_rtx | |
4303 | && GET_CODE (SET_SRC (x)) == LABEL_REF) | |
4304 | ; | |
7afe21cc RK |
4305 | /* Don't count call-insns, (set (reg 0) (call ...)), as a set. |
4306 | The hard function value register is used only once, to copy to | |
7b02f4e0 | 4307 | someplace else, so it isn't worth cse'ing. */ |
7afe21cc | 4308 | else if (GET_CODE (SET_SRC (x)) == CALL) |
7b02f4e0 | 4309 | ; |
7afe21cc | 4310 | else |
7b02f4e0 | 4311 | sets[n_sets++].rtl = x; |
7afe21cc RK |
4312 | } |
4313 | else if (GET_CODE (x) == PARALLEL) | |
4314 | { | |
7b02f4e0 | 4315 | int i, lim = XVECLEN (x, 0); |
278a83b2 | 4316 | |
6c4d60f8 | 4317 | /* Go over the expressions of the PARALLEL in forward order, to |
7b02f4e0 | 4318 | put them in the same order in the SETS array. */ |
7afe21cc RK |
4319 | for (i = 0; i < lim; i++) |
4320 | { | |
b3694847 | 4321 | rtx y = XVECEXP (x, 0, i); |
7afe21cc RK |
4322 | if (GET_CODE (y) == SET) |
4323 | { | |
7722328e RK |
4324 | /* As above, we ignore unconditional jumps and call-insns and |
4325 | ignore the result of apply_change_group. */ | |
7b02f4e0 SB |
4326 | if (SET_DEST (y) == pc_rtx |
4327 | && GET_CODE (SET_SRC (y)) == LABEL_REF) | |
4328 | ; | |
4329 | else if (GET_CODE (SET_SRC (y)) == CALL) | |
7afe21cc RK |
4330 | ; |
4331 | else | |
4332 | sets[n_sets++].rtl = y; | |
4333 | } | |
7afe21cc RK |
4334 | } |
4335 | } | |
7b02f4e0 SB |
4336 | |
4337 | return n_sets; | |
4338 | } | |
4339 | \f | |
6380a82e EB |
4340 | /* Subroutine of canonicalize_insn. X is an ASM_OPERANDS in INSN. */ |
4341 | ||
4342 | static void | |
4343 | canon_asm_operands (rtx x, rtx_insn *insn) | |
4344 | { | |
4345 | for (int i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) | |
4346 | { | |
4347 | rtx input = ASM_OPERANDS_INPUT (x, i); | |
4348 | if (!(REG_P (input) && HARD_REGISTER_P (input))) | |
4349 | { | |
4350 | input = canon_reg (input, insn); | |
4351 | validate_change (insn, &ASM_OPERANDS_INPUT (x, i), input, 1); | |
4352 | } | |
4353 | } | |
4354 | } | |
4355 | ||
7b02f4e0 | 4356 | /* Where possible, substitute every register reference in the N_SETS |
026c3cfd | 4357 | number of SETS in INSN with the canonical register. |
7b02f4e0 SB |
4358 | |
4359 | Register canonicalization propagatest the earliest register (i.e. | |
4360 | one that is set before INSN) with the same value. This is a very | |
4361 | useful, simple form of CSE, to clean up warts from expanding GIMPLE | |
4362 | to RTL. For instance, a CONST for an address is usually expanded | |
4363 | multiple times to loads into different registers, thus creating many | |
4364 | subexpressions of the form: | |
4365 | ||
4366 | (set (reg1) (some_const)) | |
4367 | (set (mem (... reg1 ...) (thing))) | |
4368 | (set (reg2) (some_const)) | |
4369 | (set (mem (... reg2 ...) (thing))) | |
4370 | ||
4371 | After canonicalizing, the code takes the following form: | |
4372 | ||
4373 | (set (reg1) (some_const)) | |
4374 | (set (mem (... reg1 ...) (thing))) | |
4375 | (set (reg2) (some_const)) | |
4376 | (set (mem (... reg1 ...) (thing))) | |
4377 | ||
4378 | The set to reg2 is now trivially dead, and the memory reference (or | |
4379 | address, or whatever) may be a candidate for further CSEing. | |
4380 | ||
4381 | In this function, the result of apply_change_group can be ignored; | |
4382 | see canon_reg. */ | |
4383 | ||
4384 | static void | |
20468884 | 4385 | canonicalize_insn (rtx_insn *insn, struct set **psets, int n_sets) |
7b02f4e0 SB |
4386 | { |
4387 | struct set *sets = *psets; | |
4388 | rtx tem; | |
4389 | rtx x = PATTERN (insn); | |
4390 | int i; | |
4391 | ||
4392 | if (CALL_P (insn)) | |
4393 | { | |
4394 | for (tem = CALL_INSN_FUNCTION_USAGE (insn); tem; tem = XEXP (tem, 1)) | |
e384e6b5 BS |
4395 | if (GET_CODE (XEXP (tem, 0)) != SET) |
4396 | XEXP (tem, 0) = canon_reg (XEXP (tem, 0), insn); | |
7b02f4e0 SB |
4397 | } |
4398 | ||
4399 | if (GET_CODE (x) == SET && GET_CODE (SET_SRC (x)) == CALL) | |
4400 | { | |
4401 | canon_reg (SET_SRC (x), insn); | |
4402 | apply_change_group (); | |
4403 | fold_rtx (SET_SRC (x), insn); | |
4404 | } | |
7afe21cc RK |
4405 | else if (GET_CODE (x) == CLOBBER) |
4406 | { | |
7b02f4e0 SB |
4407 | /* If we clobber memory, canon the address. |
4408 | This does nothing when a register is clobbered | |
4409 | because we have already invalidated the reg. */ | |
3c0cb5de | 4410 | if (MEM_P (XEXP (x, 0))) |
6fb5fa3c | 4411 | canon_reg (XEXP (x, 0), insn); |
7afe21cc | 4412 | } |
7afe21cc | 4413 | else if (GET_CODE (x) == USE |
f8cfc6aa | 4414 | && ! (REG_P (XEXP (x, 0)) |
7afe21cc | 4415 | && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)) |
7b02f4e0 | 4416 | /* Canonicalize a USE of a pseudo register or memory location. */ |
b1ba284c EB |
4417 | canon_reg (x, insn); |
4418 | else if (GET_CODE (x) == ASM_OPERANDS) | |
6380a82e | 4419 | canon_asm_operands (x, insn); |
7afe21cc RK |
4420 | else if (GET_CODE (x) == CALL) |
4421 | { | |
4422 | canon_reg (x, insn); | |
77fa0940 | 4423 | apply_change_group (); |
7afe21cc RK |
4424 | fold_rtx (x, insn); |
4425 | } | |
b5b8b0ac AO |
4426 | else if (DEBUG_INSN_P (insn)) |
4427 | canon_reg (PATTERN (insn), insn); | |
7b02f4e0 SB |
4428 | else if (GET_CODE (x) == PARALLEL) |
4429 | { | |
4430 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
4431 | { | |
4432 | rtx y = XVECEXP (x, 0, i); | |
4433 | if (GET_CODE (y) == SET && GET_CODE (SET_SRC (y)) == CALL) | |
4434 | { | |
4435 | canon_reg (SET_SRC (y), insn); | |
4436 | apply_change_group (); | |
4437 | fold_rtx (SET_SRC (y), insn); | |
4438 | } | |
4439 | else if (GET_CODE (y) == CLOBBER) | |
4440 | { | |
4441 | if (MEM_P (XEXP (y, 0))) | |
4442 | canon_reg (XEXP (y, 0), insn); | |
4443 | } | |
4444 | else if (GET_CODE (y) == USE | |
4445 | && ! (REG_P (XEXP (y, 0)) | |
4446 | && REGNO (XEXP (y, 0)) < FIRST_PSEUDO_REGISTER)) | |
4447 | canon_reg (y, insn); | |
6380a82e EB |
4448 | else if (GET_CODE (y) == ASM_OPERANDS) |
4449 | canon_asm_operands (y, insn); | |
7b02f4e0 SB |
4450 | else if (GET_CODE (y) == CALL) |
4451 | { | |
4452 | canon_reg (y, insn); | |
4453 | apply_change_group (); | |
4454 | fold_rtx (y, insn); | |
4455 | } | |
4456 | } | |
4457 | } | |
7afe21cc | 4458 | |
92f9aa51 | 4459 | if (n_sets == 1 && REG_NOTES (insn) != 0 |
7b02f4e0 | 4460 | && (tem = find_reg_note (insn, REG_EQUAL, NULL_RTX)) != 0) |
7b668f9e | 4461 | { |
7b02f4e0 SB |
4462 | /* We potentially will process this insn many times. Therefore, |
4463 | drop the REG_EQUAL note if it is equal to the SET_SRC of the | |
4464 | unique set in INSN. | |
4465 | ||
4466 | Do not do so if the REG_EQUAL note is for a STRICT_LOW_PART, | |
4467 | because cse_insn handles those specially. */ | |
4468 | if (GET_CODE (SET_DEST (sets[0].rtl)) != STRICT_LOW_PART | |
4469 | && rtx_equal_p (XEXP (tem, 0), SET_SRC (sets[0].rtl))) | |
4470 | remove_note (insn, tem); | |
4471 | else | |
4472 | { | |
4473 | canon_reg (XEXP (tem, 0), insn); | |
4474 | apply_change_group (); | |
4475 | XEXP (tem, 0) = fold_rtx (XEXP (tem, 0), insn); | |
4476 | df_notes_rescan (insn); | |
4477 | } | |
7b668f9e | 4478 | } |
7afe21cc RK |
4479 | |
4480 | /* Canonicalize sources and addresses of destinations. | |
4481 | We do this in a separate pass to avoid problems when a MATCH_DUP is | |
4482 | present in the insn pattern. In that case, we want to ensure that | |
4483 | we don't break the duplicate nature of the pattern. So we will replace | |
4484 | both operands at the same time. Otherwise, we would fail to find an | |
4485 | equivalent substitution in the loop calling validate_change below. | |
7afe21cc RK |
4486 | |
4487 | We used to suppress canonicalization of DEST if it appears in SRC, | |
77fa0940 | 4488 | but we don't do this any more. */ |
7afe21cc RK |
4489 | |
4490 | for (i = 0; i < n_sets; i++) | |
4491 | { | |
4492 | rtx dest = SET_DEST (sets[i].rtl); | |
4493 | rtx src = SET_SRC (sets[i].rtl); | |
32e9fa48 | 4494 | rtx new_rtx = canon_reg (src, insn); |
7afe21cc | 4495 | |
32e9fa48 | 4496 | validate_change (insn, &SET_SRC (sets[i].rtl), new_rtx, 1); |
7afe21cc | 4497 | |
46d096a3 | 4498 | if (GET_CODE (dest) == ZERO_EXTRACT) |
7afe21cc RK |
4499 | { |
4500 | validate_change (insn, &XEXP (dest, 1), | |
77fa0940 | 4501 | canon_reg (XEXP (dest, 1), insn), 1); |
7afe21cc | 4502 | validate_change (insn, &XEXP (dest, 2), |
77fa0940 | 4503 | canon_reg (XEXP (dest, 2), insn), 1); |
7afe21cc RK |
4504 | } |
4505 | ||
46d096a3 | 4506 | while (GET_CODE (dest) == SUBREG |
7afe21cc | 4507 | || GET_CODE (dest) == ZERO_EXTRACT |
46d096a3 | 4508 | || GET_CODE (dest) == STRICT_LOW_PART) |
7afe21cc RK |
4509 | dest = XEXP (dest, 0); |
4510 | ||
3c0cb5de | 4511 | if (MEM_P (dest)) |
7afe21cc RK |
4512 | canon_reg (dest, insn); |
4513 | } | |
4514 | ||
77fa0940 RK |
4515 | /* Now that we have done all the replacements, we can apply the change |
4516 | group and see if they all work. Note that this will cause some | |
4517 | canonicalizations that would have worked individually not to be applied | |
4518 | because some other canonicalization didn't work, but this should not | |
278a83b2 | 4519 | occur often. |
7722328e RK |
4520 | |
4521 | The result of apply_change_group can be ignored; see canon_reg. */ | |
77fa0940 RK |
4522 | |
4523 | apply_change_group (); | |
7b02f4e0 SB |
4524 | } |
4525 | \f | |
4526 | /* Main function of CSE. | |
4527 | First simplify sources and addresses of all assignments | |
4528 | in the instruction, using previously-computed equivalents values. | |
4529 | Then install the new sources and destinations in the table | |
4530 | of available values. */ | |
4531 | ||
4532 | static void | |
20468884 | 4533 | cse_insn (rtx_insn *insn) |
7b02f4e0 SB |
4534 | { |
4535 | rtx x = PATTERN (insn); | |
4536 | int i; | |
4537 | rtx tem; | |
4538 | int n_sets = 0; | |
4539 | ||
4540 | rtx src_eqv = 0; | |
4541 | struct table_elt *src_eqv_elt = 0; | |
4542 | int src_eqv_volatile = 0; | |
4543 | int src_eqv_in_memory = 0; | |
4544 | unsigned src_eqv_hash = 0; | |
4545 | ||
4546 | struct set *sets = (struct set *) 0; | |
4547 | ||
4548 | if (GET_CODE (x) == SET) | |
4549 | sets = XALLOCA (struct set); | |
4550 | else if (GET_CODE (x) == PARALLEL) | |
4551 | sets = XALLOCAVEC (struct set, XVECLEN (x, 0)); | |
4552 | ||
4553 | this_insn = insn; | |
7b02f4e0 SB |
4554 | /* Records what this insn does to set CC0. */ |
4555 | this_insn_cc0 = 0; | |
4556 | this_insn_cc0_mode = VOIDmode; | |
7b02f4e0 SB |
4557 | |
4558 | /* Find all regs explicitly clobbered in this insn, | |
4559 | to ensure they are not replaced with any other regs | |
4560 | elsewhere in this insn. */ | |
4561 | invalidate_from_sets_and_clobbers (insn); | |
4562 | ||
4563 | /* Record all the SETs in this instruction. */ | |
4564 | n_sets = find_sets_in_insn (insn, &sets); | |
4565 | ||
4566 | /* Substitute the canonical register where possible. */ | |
4567 | canonicalize_insn (insn, &sets, n_sets); | |
4568 | ||
4569 | /* If this insn has a REG_EQUAL note, store the equivalent value in SRC_EQV, | |
7f7379f6 KV |
4570 | if different, or if the DEST is a STRICT_LOW_PART/ZERO_EXTRACT. The |
4571 | latter condition is necessary because SRC_EQV is handled specially for | |
4572 | this case, and if it isn't set, then there will be no equivalence | |
4573 | for the destination. */ | |
7b02f4e0 | 4574 | if (n_sets == 1 && REG_NOTES (insn) != 0 |
1e928e07 | 4575 | && (tem = find_reg_note (insn, REG_EQUAL, NULL_RTX)) != 0) |
7f7379f6 | 4576 | { |
7f7379f6 | 4577 | |
1e928e07 KV |
4578 | if (GET_CODE (SET_DEST (sets[0].rtl)) != ZERO_EXTRACT |
4579 | && (! rtx_equal_p (XEXP (tem, 0), SET_SRC (sets[0].rtl)) | |
4580 | || GET_CODE (SET_DEST (sets[0].rtl)) == STRICT_LOW_PART)) | |
4581 | src_eqv = copy_rtx (XEXP (tem, 0)); | |
7f7379f6 KV |
4582 | /* If DEST is of the form ZERO_EXTACT, as in: |
4583 | (set (zero_extract:SI (reg:SI 119) | |
4584 | (const_int 16 [0x10]) | |
4585 | (const_int 16 [0x10])) | |
4586 | (const_int 51154 [0xc7d2])) | |
4587 | REG_EQUAL note will specify the value of register (reg:SI 119) at this | |
4588 | point. Note that this is different from SRC_EQV. We can however | |
4589 | calculate SRC_EQV with the position and width of ZERO_EXTRACT. */ | |
4590 | else if (GET_CODE (SET_DEST (sets[0].rtl)) == ZERO_EXTRACT | |
fa24123b | 4591 | && CONST_INT_P (XEXP (tem, 0)) |
7f7379f6 KV |
4592 | && CONST_INT_P (XEXP (SET_DEST (sets[0].rtl), 1)) |
4593 | && CONST_INT_P (XEXP (SET_DEST (sets[0].rtl), 2))) | |
4594 | { | |
4595 | rtx dest_reg = XEXP (SET_DEST (sets[0].rtl), 0); | |
c7ad039d RS |
4596 | /* This is the mode of XEXP (tem, 0) as well. */ |
4597 | scalar_int_mode dest_mode | |
4598 | = as_a <scalar_int_mode> (GET_MODE (dest_reg)); | |
7f7379f6 KV |
4599 | rtx width = XEXP (SET_DEST (sets[0].rtl), 1); |
4600 | rtx pos = XEXP (SET_DEST (sets[0].rtl), 2); | |
fa24123b | 4601 | HOST_WIDE_INT val = INTVAL (XEXP (tem, 0)); |
7f7379f6 KV |
4602 | HOST_WIDE_INT mask; |
4603 | unsigned int shift; | |
4604 | if (BITS_BIG_ENDIAN) | |
c7ad039d RS |
4605 | shift = (GET_MODE_PRECISION (dest_mode) |
4606 | - INTVAL (pos) - INTVAL (width)); | |
7f7379f6 KV |
4607 | else |
4608 | shift = INTVAL (pos); | |
4609 | if (INTVAL (width) == HOST_BITS_PER_WIDE_INT) | |
dd4786fe | 4610 | mask = HOST_WIDE_INT_M1; |
7f7379f6 | 4611 | else |
fecfbfa4 | 4612 | mask = (HOST_WIDE_INT_1 << INTVAL (width)) - 1; |
7f7379f6 KV |
4613 | val = (val >> shift) & mask; |
4614 | src_eqv = GEN_INT (val); | |
4615 | } | |
4616 | } | |
77fa0940 | 4617 | |
7afe21cc RK |
4618 | /* Set sets[i].src_elt to the class each source belongs to. |
4619 | Detect assignments from or to volatile things | |
4620 | and set set[i] to zero so they will be ignored | |
4621 | in the rest of this function. | |
4622 | ||
4623 | Nothing in this loop changes the hash table or the register chains. */ | |
4624 | ||
4625 | for (i = 0; i < n_sets; i++) | |
4626 | { | |
b4ab701f | 4627 | bool repeat = false; |
aa535578 | 4628 | bool mem_noop_insn = false; |
b3694847 SS |
4629 | rtx src, dest; |
4630 | rtx src_folded; | |
4631 | struct table_elt *elt = 0, *p; | |
ef4bddc2 | 4632 | machine_mode mode; |
7afe21cc RK |
4633 | rtx src_eqv_here; |
4634 | rtx src_const = 0; | |
4635 | rtx src_related = 0; | |
2c5bfdf7 | 4636 | bool src_related_is_const_anchor = false; |
7afe21cc | 4637 | struct table_elt *src_const_elt = 0; |
99a9c946 GS |
4638 | int src_cost = MAX_COST; |
4639 | int src_eqv_cost = MAX_COST; | |
4640 | int src_folded_cost = MAX_COST; | |
4641 | int src_related_cost = MAX_COST; | |
4642 | int src_elt_cost = MAX_COST; | |
4643 | int src_regcost = MAX_COST; | |
4644 | int src_eqv_regcost = MAX_COST; | |
4645 | int src_folded_regcost = MAX_COST; | |
4646 | int src_related_regcost = MAX_COST; | |
4647 | int src_elt_regcost = MAX_COST; | |
da7d8304 | 4648 | /* Set nonzero if we need to call force_const_mem on with the |
7afe21cc RK |
4649 | contents of src_folded before using it. */ |
4650 | int src_folded_force_flag = 0; | |
b4206259 | 4651 | scalar_int_mode int_mode; |
7afe21cc RK |
4652 | |
4653 | dest = SET_DEST (sets[i].rtl); | |
4654 | src = SET_SRC (sets[i].rtl); | |
4655 | ||
4656 | /* If SRC is a constant that has no machine mode, | |
4657 | hash it with the destination's machine mode. | |
4658 | This way we can keep different modes separate. */ | |
4659 | ||
4660 | mode = GET_MODE (src) == VOIDmode ? GET_MODE (dest) : GET_MODE (src); | |
4661 | sets[i].mode = mode; | |
4662 | ||
4663 | if (src_eqv) | |
4664 | { | |
ef4bddc2 | 4665 | machine_mode eqvmode = mode; |
7afe21cc RK |
4666 | if (GET_CODE (dest) == STRICT_LOW_PART) |
4667 | eqvmode = GET_MODE (SUBREG_REG (XEXP (dest, 0))); | |
4668 | do_not_record = 0; | |
4669 | hash_arg_in_memory = 0; | |
2197a88a | 4670 | src_eqv_hash = HASH (src_eqv, eqvmode); |
7afe21cc RK |
4671 | |
4672 | /* Find the equivalence class for the equivalent expression. */ | |
4673 | ||
4674 | if (!do_not_record) | |
2197a88a | 4675 | src_eqv_elt = lookup (src_eqv, src_eqv_hash, eqvmode); |
7afe21cc RK |
4676 | |
4677 | src_eqv_volatile = do_not_record; | |
4678 | src_eqv_in_memory = hash_arg_in_memory; | |
7afe21cc RK |
4679 | } |
4680 | ||
4681 | /* If this is a STRICT_LOW_PART assignment, src_eqv corresponds to the | |
4682 | value of the INNER register, not the destination. So it is not | |
3826a3da | 4683 | a valid substitution for the source. But save it for later. */ |
7afe21cc RK |
4684 | if (GET_CODE (dest) == STRICT_LOW_PART) |
4685 | src_eqv_here = 0; | |
4686 | else | |
4687 | src_eqv_here = src_eqv; | |
4688 | ||
4689 | /* Simplify and foldable subexpressions in SRC. Then get the fully- | |
4690 | simplified result, which may not necessarily be valid. */ | |
625d55af | 4691 | src_folded = fold_rtx (src, NULL); |
7afe21cc | 4692 | |
e6a125a0 RK |
4693 | #if 0 |
4694 | /* ??? This caused bad code to be generated for the m68k port with -O2. | |
4695 | Suppose src is (CONST_INT -1), and that after truncation src_folded | |
4696 | is (CONST_INT 3). Suppose src_folded is then used for src_const. | |
4697 | At the end we will add src and src_const to the same equivalence | |
4698 | class. We now have 3 and -1 on the same equivalence class. This | |
4699 | causes later instructions to be mis-optimized. */ | |
7afe21cc RK |
4700 | /* If storing a constant in a bitfield, pre-truncate the constant |
4701 | so we will be able to record it later. */ | |
46d096a3 | 4702 | if (GET_CODE (SET_DEST (sets[i].rtl)) == ZERO_EXTRACT) |
7afe21cc RK |
4703 | { |
4704 | rtx width = XEXP (SET_DEST (sets[i].rtl), 1); | |
4705 | ||
481683e1 SZ |
4706 | if (CONST_INT_P (src) |
4707 | && CONST_INT_P (width) | |
906c4e36 RK |
4708 | && INTVAL (width) < HOST_BITS_PER_WIDE_INT |
4709 | && (INTVAL (src) & ((HOST_WIDE_INT) (-1) << INTVAL (width)))) | |
4710 | src_folded | |
fecfbfa4 | 4711 | = GEN_INT (INTVAL (src) & ((HOST_WIDE_INT_1 |
906c4e36 | 4712 | << INTVAL (width)) - 1)); |
7afe21cc | 4713 | } |
e6a125a0 | 4714 | #endif |
7afe21cc RK |
4715 | |
4716 | /* Compute SRC's hash code, and also notice if it | |
4717 | should not be recorded at all. In that case, | |
4718 | prevent any further processing of this assignment. */ | |
4719 | do_not_record = 0; | |
4720 | hash_arg_in_memory = 0; | |
7afe21cc RK |
4721 | |
4722 | sets[i].src = src; | |
2197a88a | 4723 | sets[i].src_hash = HASH (src, mode); |
7afe21cc RK |
4724 | sets[i].src_volatile = do_not_record; |
4725 | sets[i].src_in_memory = hash_arg_in_memory; | |
7afe21cc | 4726 | |
50196afa | 4727 | /* If SRC is a MEM, there is a REG_EQUIV note for SRC, and DEST is |
43e72072 JJ |
4728 | a pseudo, do not record SRC. Using SRC as a replacement for |
4729 | anything else will be incorrect in that situation. Note that | |
4730 | this usually occurs only for stack slots, in which case all the | |
4731 | RTL would be referring to SRC, so we don't lose any optimization | |
4732 | opportunities by not having SRC in the hash table. */ | |
50196afa | 4733 | |
3c0cb5de | 4734 | if (MEM_P (src) |
43e72072 | 4735 | && find_reg_note (insn, REG_EQUIV, NULL_RTX) != 0 |
f8cfc6aa | 4736 | && REG_P (dest) |
43e72072 | 4737 | && REGNO (dest) >= FIRST_PSEUDO_REGISTER) |
50196afa RK |
4738 | sets[i].src_volatile = 1; |
4739 | ||
d8d6ea53 JJ |
4740 | else if (GET_CODE (src) == ASM_OPERANDS |
4741 | && GET_CODE (x) == PARALLEL) | |
6c4d60f8 JJ |
4742 | { |
4743 | /* Do not record result of a non-volatile inline asm with | |
4744 | more than one result. */ | |
4745 | if (n_sets > 1) | |
4746 | sets[i].src_volatile = 1; | |
4747 | ||
4748 | int j, lim = XVECLEN (x, 0); | |
4749 | for (j = 0; j < lim; j++) | |
4750 | { | |
4751 | rtx y = XVECEXP (x, 0, j); | |
4752 | /* And do not record result of a non-volatile inline asm | |
4753 | with "memory" clobber. */ | |
4754 | if (GET_CODE (y) == CLOBBER && MEM_P (XEXP (y, 0))) | |
4755 | { | |
4756 | sets[i].src_volatile = 1; | |
4757 | break; | |
4758 | } | |
4759 | } | |
4760 | } | |
d8d6ea53 | 4761 | |
0dadecf6 RK |
4762 | #if 0 |
4763 | /* It is no longer clear why we used to do this, but it doesn't | |
4764 | appear to still be needed. So let's try without it since this | |
4765 | code hurts cse'ing widened ops. */ | |
9a5a17f3 | 4766 | /* If source is a paradoxical subreg (such as QI treated as an SI), |
7afe21cc RK |
4767 | treat it as volatile. It may do the work of an SI in one context |
4768 | where the extra bits are not being used, but cannot replace an SI | |
4769 | in general. */ | |
6a4bdc79 | 4770 | if (paradoxical_subreg_p (src)) |
7afe21cc | 4771 | sets[i].src_volatile = 1; |
0dadecf6 | 4772 | #endif |
7afe21cc RK |
4773 | |
4774 | /* Locate all possible equivalent forms for SRC. Try to replace | |
4775 | SRC in the insn with each cheaper equivalent. | |
4776 | ||
4777 | We have the following types of equivalents: SRC itself, a folded | |
4778 | version, a value given in a REG_EQUAL note, or a value related | |
4779 | to a constant. | |
4780 | ||
4781 | Each of these equivalents may be part of an additional class | |
4782 | of equivalents (if more than one is in the table, they must be in | |
4783 | the same class; we check for this). | |
4784 | ||
4785 | If the source is volatile, we don't do any table lookups. | |
4786 | ||
4787 | We note any constant equivalent for possible later use in a | |
4788 | REG_NOTE. */ | |
4789 | ||
4790 | if (!sets[i].src_volatile) | |
2197a88a | 4791 | elt = lookup (src, sets[i].src_hash, mode); |
7afe21cc RK |
4792 | |
4793 | sets[i].src_elt = elt; | |
4794 | ||
4795 | if (elt && src_eqv_here && src_eqv_elt) | |
278a83b2 KH |
4796 | { |
4797 | if (elt->first_same_value != src_eqv_elt->first_same_value) | |
7afe21cc RK |
4798 | { |
4799 | /* The REG_EQUAL is indicating that two formerly distinct | |
4800 | classes are now equivalent. So merge them. */ | |
4801 | merge_equiv_classes (elt, src_eqv_elt); | |
2197a88a RK |
4802 | src_eqv_hash = HASH (src_eqv, elt->mode); |
4803 | src_eqv_elt = lookup (src_eqv, src_eqv_hash, elt->mode); | |
7afe21cc RK |
4804 | } |
4805 | ||
278a83b2 KH |
4806 | src_eqv_here = 0; |
4807 | } | |
7afe21cc RK |
4808 | |
4809 | else if (src_eqv_elt) | |
278a83b2 | 4810 | elt = src_eqv_elt; |
7afe21cc RK |
4811 | |
4812 | /* Try to find a constant somewhere and record it in `src_const'. | |
4813 | Record its table element, if any, in `src_const_elt'. Look in | |
4814 | any known equivalences first. (If the constant is not in the | |
2197a88a | 4815 | table, also set `sets[i].src_const_hash'). */ |
7afe21cc | 4816 | if (elt) |
278a83b2 | 4817 | for (p = elt->first_same_value; p; p = p->next_same_value) |
7afe21cc RK |
4818 | if (p->is_const) |
4819 | { | |
4820 | src_const = p->exp; | |
4821 | src_const_elt = elt; | |
4822 | break; | |
4823 | } | |
4824 | ||
4825 | if (src_const == 0 | |
4826 | && (CONSTANT_P (src_folded) | |
278a83b2 | 4827 | /* Consider (minus (label_ref L1) (label_ref L2)) as |
7afe21cc RK |
4828 | "constant" here so we will record it. This allows us |
4829 | to fold switch statements when an ADDR_DIFF_VEC is used. */ | |
4830 | || (GET_CODE (src_folded) == MINUS | |
4831 | && GET_CODE (XEXP (src_folded, 0)) == LABEL_REF | |
4832 | && GET_CODE (XEXP (src_folded, 1)) == LABEL_REF))) | |
4833 | src_const = src_folded, src_const_elt = elt; | |
4834 | else if (src_const == 0 && src_eqv_here && CONSTANT_P (src_eqv_here)) | |
4835 | src_const = src_eqv_here, src_const_elt = src_eqv_elt; | |
4836 | ||
4837 | /* If we don't know if the constant is in the table, get its | |
4838 | hash code and look it up. */ | |
4839 | if (src_const && src_const_elt == 0) | |
4840 | { | |
2197a88a RK |
4841 | sets[i].src_const_hash = HASH (src_const, mode); |
4842 | src_const_elt = lookup (src_const, sets[i].src_const_hash, mode); | |
7afe21cc RK |
4843 | } |
4844 | ||
4845 | sets[i].src_const = src_const; | |
4846 | sets[i].src_const_elt = src_const_elt; | |
4847 | ||
4848 | /* If the constant and our source are both in the table, mark them as | |
4849 | equivalent. Otherwise, if a constant is in the table but the source | |
4850 | isn't, set ELT to it. */ | |
4851 | if (src_const_elt && elt | |
4852 | && src_const_elt->first_same_value != elt->first_same_value) | |
4853 | merge_equiv_classes (elt, src_const_elt); | |
4854 | else if (src_const_elt && elt == 0) | |
4855 | elt = src_const_elt; | |
4856 | ||
4857 | /* See if there is a register linearly related to a constant | |
4858 | equivalent of SRC. */ | |
4859 | if (src_const | |
4860 | && (GET_CODE (src_const) == CONST | |
4861 | || (src_const_elt && src_const_elt->related_value != 0))) | |
278a83b2 KH |
4862 | { |
4863 | src_related = use_related_value (src_const, src_const_elt); | |
4864 | if (src_related) | |
4865 | { | |
7afe21cc | 4866 | struct table_elt *src_related_elt |
278a83b2 | 4867 | = lookup (src_related, HASH (src_related, mode), mode); |
7afe21cc | 4868 | if (src_related_elt && elt) |
278a83b2 | 4869 | { |
7afe21cc RK |
4870 | if (elt->first_same_value |
4871 | != src_related_elt->first_same_value) | |
278a83b2 | 4872 | /* This can occur when we previously saw a CONST |
7afe21cc RK |
4873 | involving a SYMBOL_REF and then see the SYMBOL_REF |
4874 | twice. Merge the involved classes. */ | |
4875 | merge_equiv_classes (elt, src_related_elt); | |
4876 | ||
278a83b2 | 4877 | src_related = 0; |
7afe21cc | 4878 | src_related_elt = 0; |
278a83b2 KH |
4879 | } |
4880 | else if (src_related_elt && elt == 0) | |
4881 | elt = src_related_elt; | |
7afe21cc | 4882 | } |
278a83b2 | 4883 | } |
7afe21cc | 4884 | |
e4600702 RK |
4885 | /* See if we have a CONST_INT that is already in a register in a |
4886 | wider mode. */ | |
4887 | ||
481683e1 | 4888 | if (src_const && src_related == 0 && CONST_INT_P (src_const) |
b4206259 RS |
4889 | && is_int_mode (mode, &int_mode) |
4890 | && GET_MODE_PRECISION (int_mode) < BITS_PER_WORD) | |
e4600702 | 4891 | { |
b4206259 RS |
4892 | opt_scalar_int_mode wider_mode_iter; |
4893 | FOR_EACH_WIDER_MODE (wider_mode_iter, int_mode) | |
e4600702 | 4894 | { |
b4206259 | 4895 | scalar_int_mode wider_mode = wider_mode_iter.require (); |
c94843d2 RS |
4896 | if (GET_MODE_PRECISION (wider_mode) > BITS_PER_WORD) |
4897 | break; | |
4898 | ||
e4600702 RK |
4899 | struct table_elt *const_elt |
4900 | = lookup (src_const, HASH (src_const, wider_mode), wider_mode); | |
4901 | ||
4902 | if (const_elt == 0) | |
4903 | continue; | |
4904 | ||
4905 | for (const_elt = const_elt->first_same_value; | |
4906 | const_elt; const_elt = const_elt->next_same_value) | |
f8cfc6aa | 4907 | if (REG_P (const_elt->exp)) |
e4600702 | 4908 | { |
b4206259 | 4909 | src_related = gen_lowpart (int_mode, const_elt->exp); |
e4600702 RK |
4910 | break; |
4911 | } | |
c94843d2 RS |
4912 | |
4913 | if (src_related != 0) | |
4914 | break; | |
e4600702 RK |
4915 | } |
4916 | } | |
4917 | ||
d45cf215 RS |
4918 | /* Another possibility is that we have an AND with a constant in |
4919 | a mode narrower than a word. If so, it might have been generated | |
4920 | as part of an "if" which would narrow the AND. If we already | |
4921 | have done the AND in a wider mode, we can use a SUBREG of that | |
4922 | value. */ | |
4923 | ||
4924 | if (flag_expensive_optimizations && ! src_related | |
54651377 | 4925 | && is_a <scalar_int_mode> (mode, &int_mode) |
481683e1 | 4926 | && GET_CODE (src) == AND && CONST_INT_P (XEXP (src, 1)) |
54651377 | 4927 | && GET_MODE_SIZE (int_mode) < UNITS_PER_WORD) |
d45cf215 | 4928 | { |
59b51186 | 4929 | opt_scalar_int_mode tmode_iter; |
38a448ca | 4930 | rtx new_and = gen_rtx_AND (VOIDmode, NULL_RTX, XEXP (src, 1)); |
d45cf215 | 4931 | |
59b51186 | 4932 | FOR_EACH_WIDER_MODE (tmode_iter, int_mode) |
d45cf215 | 4933 | { |
59b51186 | 4934 | scalar_int_mode tmode = tmode_iter.require (); |
c94843d2 RS |
4935 | if (GET_MODE_SIZE (tmode) > UNITS_PER_WORD) |
4936 | break; | |
4937 | ||
4de249d9 | 4938 | rtx inner = gen_lowpart (tmode, XEXP (src, 0)); |
d45cf215 RS |
4939 | struct table_elt *larger_elt; |
4940 | ||
4941 | if (inner) | |
4942 | { | |
4943 | PUT_MODE (new_and, tmode); | |
4944 | XEXP (new_and, 0) = inner; | |
4945 | larger_elt = lookup (new_and, HASH (new_and, tmode), tmode); | |
4946 | if (larger_elt == 0) | |
4947 | continue; | |
4948 | ||
4949 | for (larger_elt = larger_elt->first_same_value; | |
4950 | larger_elt; larger_elt = larger_elt->next_same_value) | |
f8cfc6aa | 4951 | if (REG_P (larger_elt->exp)) |
d45cf215 RS |
4952 | { |
4953 | src_related | |
54651377 | 4954 | = gen_lowpart (int_mode, larger_elt->exp); |
d45cf215 RS |
4955 | break; |
4956 | } | |
4957 | ||
4958 | if (src_related) | |
4959 | break; | |
4960 | } | |
4961 | } | |
4962 | } | |
7bac1be0 | 4963 | |
7bac1be0 RK |
4964 | /* See if a MEM has already been loaded with a widening operation; |
4965 | if it has, we can use a subreg of that. Many CISC machines | |
4966 | also have such operations, but this is only likely to be | |
71cc389b | 4967 | beneficial on these machines. */ |
278a83b2 | 4968 | |
3712c7a3 | 4969 | rtx_code extend_op; |
ddc356e8 | 4970 | if (flag_expensive_optimizations && src_related == 0 |
3c0cb5de | 4971 | && MEM_P (src) && ! do_not_record |
095a49c8 RS |
4972 | && is_a <scalar_int_mode> (mode, &int_mode) |
4973 | && (extend_op = load_extend_op (int_mode)) != UNKNOWN) | |
7bac1be0 | 4974 | { |
9d80ef7c RH |
4975 | struct rtx_def memory_extend_buf; |
4976 | rtx memory_extend_rtx = &memory_extend_buf; | |
278a83b2 | 4977 | |
7bac1be0 RK |
4978 | /* Set what we are trying to extend and the operation it might |
4979 | have been extended with. */ | |
c3284718 | 4980 | memset (memory_extend_rtx, 0, sizeof (*memory_extend_rtx)); |
3712c7a3 | 4981 | PUT_CODE (memory_extend_rtx, extend_op); |
7bac1be0 | 4982 | XEXP (memory_extend_rtx, 0) = src; |
278a83b2 | 4983 | |
59b51186 RS |
4984 | opt_scalar_int_mode tmode_iter; |
4985 | FOR_EACH_WIDER_MODE (tmode_iter, int_mode) | |
7bac1be0 RK |
4986 | { |
4987 | struct table_elt *larger_elt; | |
278a83b2 | 4988 | |
59b51186 | 4989 | scalar_int_mode tmode = tmode_iter.require (); |
c94843d2 RS |
4990 | if (GET_MODE_SIZE (tmode) > UNITS_PER_WORD) |
4991 | break; | |
4992 | ||
7bac1be0 | 4993 | PUT_MODE (memory_extend_rtx, tmode); |
278a83b2 | 4994 | larger_elt = lookup (memory_extend_rtx, |
7bac1be0 RK |
4995 | HASH (memory_extend_rtx, tmode), tmode); |
4996 | if (larger_elt == 0) | |
4997 | continue; | |
278a83b2 | 4998 | |
7bac1be0 RK |
4999 | for (larger_elt = larger_elt->first_same_value; |
5000 | larger_elt; larger_elt = larger_elt->next_same_value) | |
f8cfc6aa | 5001 | if (REG_P (larger_elt->exp)) |
7bac1be0 | 5002 | { |
095a49c8 | 5003 | src_related = gen_lowpart (int_mode, larger_elt->exp); |
7bac1be0 RK |
5004 | break; |
5005 | } | |
278a83b2 | 5006 | |
7bac1be0 RK |
5007 | if (src_related) |
5008 | break; | |
5009 | } | |
5010 | } | |
278a83b2 | 5011 | |
2c5bfdf7 AN |
5012 | /* Try to express the constant using a register+offset expression |
5013 | derived from a constant anchor. */ | |
5014 | ||
5015 | if (targetm.const_anchor | |
5016 | && !src_related | |
5017 | && src_const | |
5018 | && GET_CODE (src_const) == CONST_INT) | |
5019 | { | |
5020 | src_related = try_const_anchors (src_const, mode); | |
5021 | src_related_is_const_anchor = src_related != NULL_RTX; | |
5022 | } | |
5023 | ||
5024 | ||
7afe21cc | 5025 | if (src == src_folded) |
278a83b2 | 5026 | src_folded = 0; |
7afe21cc | 5027 | |
da7d8304 | 5028 | /* At this point, ELT, if nonzero, points to a class of expressions |
7afe21cc | 5029 | equivalent to the source of this SET and SRC, SRC_EQV, SRC_FOLDED, |
da7d8304 | 5030 | and SRC_RELATED, if nonzero, each contain additional equivalent |
7afe21cc RK |
5031 | expressions. Prune these latter expressions by deleting expressions |
5032 | already in the equivalence class. | |
5033 | ||
5034 | Check for an equivalent identical to the destination. If found, | |
5035 | this is the preferred equivalent since it will likely lead to | |
5036 | elimination of the insn. Indicate this by placing it in | |
5037 | `src_related'. */ | |
5038 | ||
278a83b2 KH |
5039 | if (elt) |
5040 | elt = elt->first_same_value; | |
7afe21cc | 5041 | for (p = elt; p; p = p->next_same_value) |
278a83b2 | 5042 | { |
7afe21cc RK |
5043 | enum rtx_code code = GET_CODE (p->exp); |
5044 | ||
5045 | /* If the expression is not valid, ignore it. Then we do not | |
5046 | have to check for validity below. In most cases, we can use | |
5047 | `rtx_equal_p', since canonicalization has already been done. */ | |
0516f6fe | 5048 | if (code != REG && ! exp_equiv_p (p->exp, p->exp, 1, false)) |
7afe21cc RK |
5049 | continue; |
5050 | ||
5a03c8c4 RK |
5051 | /* Also skip paradoxical subregs, unless that's what we're |
5052 | looking for. */ | |
6a4bdc79 | 5053 | if (paradoxical_subreg_p (p->exp) |
5a03c8c4 RK |
5054 | && ! (src != 0 |
5055 | && GET_CODE (src) == SUBREG | |
5056 | && GET_MODE (src) == GET_MODE (p->exp) | |
bd4288c0 RS |
5057 | && partial_subreg_p (GET_MODE (SUBREG_REG (src)), |
5058 | GET_MODE (SUBREG_REG (p->exp))))) | |
5a03c8c4 RK |
5059 | continue; |
5060 | ||
278a83b2 | 5061 | if (src && GET_CODE (src) == code && rtx_equal_p (src, p->exp)) |
7afe21cc | 5062 | src = 0; |
278a83b2 | 5063 | else if (src_folded && GET_CODE (src_folded) == code |
7afe21cc RK |
5064 | && rtx_equal_p (src_folded, p->exp)) |
5065 | src_folded = 0; | |
278a83b2 | 5066 | else if (src_eqv_here && GET_CODE (src_eqv_here) == code |
7afe21cc RK |
5067 | && rtx_equal_p (src_eqv_here, p->exp)) |
5068 | src_eqv_here = 0; | |
278a83b2 | 5069 | else if (src_related && GET_CODE (src_related) == code |
7afe21cc RK |
5070 | && rtx_equal_p (src_related, p->exp)) |
5071 | src_related = 0; | |
5072 | ||
5073 | /* This is the same as the destination of the insns, we want | |
5074 | to prefer it. Copy it to src_related. The code below will | |
5075 | then give it a negative cost. */ | |
5076 | if (GET_CODE (dest) == code && rtx_equal_p (p->exp, dest)) | |
5077 | src_related = dest; | |
278a83b2 | 5078 | } |
7afe21cc RK |
5079 | |
5080 | /* Find the cheapest valid equivalent, trying all the available | |
5081 | possibilities. Prefer items not in the hash table to ones | |
5082 | that are when they are equal cost. Note that we can never | |
5083 | worsen an insn as the current contents will also succeed. | |
05c33dd8 | 5084 | If we find an equivalent identical to the destination, use it as best, |
0f41302f | 5085 | since this insn will probably be eliminated in that case. */ |
7afe21cc RK |
5086 | if (src) |
5087 | { | |
5088 | if (rtx_equal_p (src, dest)) | |
f1c1dfc3 | 5089 | src_cost = src_regcost = -1; |
7afe21cc | 5090 | else |
630c79be | 5091 | { |
e548c9df | 5092 | src_cost = COST (src, mode); |
630c79be BS |
5093 | src_regcost = approx_reg_cost (src); |
5094 | } | |
7afe21cc RK |
5095 | } |
5096 | ||
5097 | if (src_eqv_here) | |
5098 | { | |
5099 | if (rtx_equal_p (src_eqv_here, dest)) | |
f1c1dfc3 | 5100 | src_eqv_cost = src_eqv_regcost = -1; |
7afe21cc | 5101 | else |
630c79be | 5102 | { |
e548c9df | 5103 | src_eqv_cost = COST (src_eqv_here, mode); |
630c79be BS |
5104 | src_eqv_regcost = approx_reg_cost (src_eqv_here); |
5105 | } | |
7afe21cc RK |
5106 | } |
5107 | ||
5108 | if (src_folded) | |
5109 | { | |
5110 | if (rtx_equal_p (src_folded, dest)) | |
f1c1dfc3 | 5111 | src_folded_cost = src_folded_regcost = -1; |
7afe21cc | 5112 | else |
630c79be | 5113 | { |
e548c9df | 5114 | src_folded_cost = COST (src_folded, mode); |
630c79be BS |
5115 | src_folded_regcost = approx_reg_cost (src_folded); |
5116 | } | |
7afe21cc RK |
5117 | } |
5118 | ||
5119 | if (src_related) | |
5120 | { | |
5121 | if (rtx_equal_p (src_related, dest)) | |
f1c1dfc3 | 5122 | src_related_cost = src_related_regcost = -1; |
7afe21cc | 5123 | else |
630c79be | 5124 | { |
e548c9df | 5125 | src_related_cost = COST (src_related, mode); |
630c79be | 5126 | src_related_regcost = approx_reg_cost (src_related); |
2c5bfdf7 AN |
5127 | |
5128 | /* If a const-anchor is used to synthesize a constant that | |
5129 | normally requires multiple instructions then slightly prefer | |
5130 | it over the original sequence. These instructions are likely | |
5131 | to become redundant now. We can't compare against the cost | |
5132 | of src_eqv_here because, on MIPS for example, multi-insn | |
5133 | constants have zero cost; they are assumed to be hoisted from | |
5134 | loops. */ | |
5135 | if (src_related_is_const_anchor | |
5136 | && src_related_cost == src_cost | |
5137 | && src_eqv_here) | |
5138 | src_related_cost--; | |
630c79be | 5139 | } |
7afe21cc RK |
5140 | } |
5141 | ||
5142 | /* If this was an indirect jump insn, a known label will really be | |
5143 | cheaper even though it looks more expensive. */ | |
5144 | if (dest == pc_rtx && src_const && GET_CODE (src_const) == LABEL_REF) | |
99a9c946 | 5145 | src_folded = src_const, src_folded_cost = src_folded_regcost = -1; |
278a83b2 | 5146 | |
7afe21cc RK |
5147 | /* Terminate loop when replacement made. This must terminate since |
5148 | the current contents will be tested and will always be valid. */ | |
5149 | while (1) | |
278a83b2 KH |
5150 | { |
5151 | rtx trial; | |
7afe21cc | 5152 | |
278a83b2 | 5153 | /* Skip invalid entries. */ |
f8cfc6aa | 5154 | while (elt && !REG_P (elt->exp) |
0516f6fe | 5155 | && ! exp_equiv_p (elt->exp, elt->exp, 1, false)) |
278a83b2 | 5156 | elt = elt->next_same_value; |
5a03c8c4 RK |
5157 | |
5158 | /* A paradoxical subreg would be bad here: it'll be the right | |
5159 | size, but later may be adjusted so that the upper bits aren't | |
5160 | what we want. So reject it. */ | |
5161 | if (elt != 0 | |
6a4bdc79 | 5162 | && paradoxical_subreg_p (elt->exp) |
5a03c8c4 RK |
5163 | /* It is okay, though, if the rtx we're trying to match |
5164 | will ignore any of the bits we can't predict. */ | |
5165 | && ! (src != 0 | |
5166 | && GET_CODE (src) == SUBREG | |
5167 | && GET_MODE (src) == GET_MODE (elt->exp) | |
bd4288c0 RS |
5168 | && partial_subreg_p (GET_MODE (SUBREG_REG (src)), |
5169 | GET_MODE (SUBREG_REG (elt->exp))))) | |
5a03c8c4 RK |
5170 | { |
5171 | elt = elt->next_same_value; | |
5172 | continue; | |
5173 | } | |
278a83b2 | 5174 | |
68252e27 | 5175 | if (elt) |
630c79be BS |
5176 | { |
5177 | src_elt_cost = elt->cost; | |
5178 | src_elt_regcost = elt->regcost; | |
5179 | } | |
7afe21cc | 5180 | |
68252e27 | 5181 | /* Find cheapest and skip it for the next time. For items |
7afe21cc RK |
5182 | of equal cost, use this order: |
5183 | src_folded, src, src_eqv, src_related and hash table entry. */ | |
99a9c946 | 5184 | if (src_folded |
56ae04af KH |
5185 | && preferable (src_folded_cost, src_folded_regcost, |
5186 | src_cost, src_regcost) <= 0 | |
5187 | && preferable (src_folded_cost, src_folded_regcost, | |
5188 | src_eqv_cost, src_eqv_regcost) <= 0 | |
5189 | && preferable (src_folded_cost, src_folded_regcost, | |
5190 | src_related_cost, src_related_regcost) <= 0 | |
5191 | && preferable (src_folded_cost, src_folded_regcost, | |
5192 | src_elt_cost, src_elt_regcost) <= 0) | |
7afe21cc | 5193 | { |
f1c1dfc3 | 5194 | trial = src_folded, src_folded_cost = MAX_COST; |
7afe21cc | 5195 | if (src_folded_force_flag) |
9d8de1de EB |
5196 | { |
5197 | rtx forced = force_const_mem (mode, trial); | |
5198 | if (forced) | |
5199 | trial = forced; | |
5200 | } | |
7afe21cc | 5201 | } |
99a9c946 | 5202 | else if (src |
56ae04af KH |
5203 | && preferable (src_cost, src_regcost, |
5204 | src_eqv_cost, src_eqv_regcost) <= 0 | |
5205 | && preferable (src_cost, src_regcost, | |
5206 | src_related_cost, src_related_regcost) <= 0 | |
5207 | && preferable (src_cost, src_regcost, | |
5208 | src_elt_cost, src_elt_regcost) <= 0) | |
f1c1dfc3 | 5209 | trial = src, src_cost = MAX_COST; |
99a9c946 | 5210 | else if (src_eqv_here |
56ae04af KH |
5211 | && preferable (src_eqv_cost, src_eqv_regcost, |
5212 | src_related_cost, src_related_regcost) <= 0 | |
5213 | && preferable (src_eqv_cost, src_eqv_regcost, | |
5214 | src_elt_cost, src_elt_regcost) <= 0) | |
a36b8a1e | 5215 | trial = src_eqv_here, src_eqv_cost = MAX_COST; |
99a9c946 | 5216 | else if (src_related |
56ae04af KH |
5217 | && preferable (src_related_cost, src_related_regcost, |
5218 | src_elt_cost, src_elt_regcost) <= 0) | |
a36b8a1e | 5219 | trial = src_related, src_related_cost = MAX_COST; |
278a83b2 | 5220 | else |
7afe21cc | 5221 | { |
a36b8a1e | 5222 | trial = elt->exp; |
7afe21cc | 5223 | elt = elt->next_same_value; |
f1c1dfc3 | 5224 | src_elt_cost = MAX_COST; |
7afe21cc RK |
5225 | } |
5226 | ||
b4ab701f JJ |
5227 | /* Try to optimize |
5228 | (set (reg:M N) (const_int A)) | |
5229 | (set (reg:M2 O) (const_int B)) | |
5230 | (set (zero_extract:M2 (reg:M N) (const_int C) (const_int D)) | |
5231 | (reg:M2 O)). */ | |
5232 | if (GET_CODE (SET_DEST (sets[i].rtl)) == ZERO_EXTRACT | |
5233 | && CONST_INT_P (trial) | |
5234 | && CONST_INT_P (XEXP (SET_DEST (sets[i].rtl), 1)) | |
5235 | && CONST_INT_P (XEXP (SET_DEST (sets[i].rtl), 2)) | |
5236 | && REG_P (XEXP (SET_DEST (sets[i].rtl), 0)) | |
bb94ec76 RS |
5237 | && (known_ge |
5238 | (GET_MODE_PRECISION (GET_MODE (SET_DEST (sets[i].rtl))), | |
5239 | INTVAL (XEXP (SET_DEST (sets[i].rtl), 1)))) | |
b4ab701f JJ |
5240 | && ((unsigned) INTVAL (XEXP (SET_DEST (sets[i].rtl), 1)) |
5241 | + (unsigned) INTVAL (XEXP (SET_DEST (sets[i].rtl), 2)) | |
5242 | <= HOST_BITS_PER_WIDE_INT)) | |
5243 | { | |
5244 | rtx dest_reg = XEXP (SET_DEST (sets[i].rtl), 0); | |
5245 | rtx width = XEXP (SET_DEST (sets[i].rtl), 1); | |
5246 | rtx pos = XEXP (SET_DEST (sets[i].rtl), 2); | |
5247 | unsigned int dest_hash = HASH (dest_reg, GET_MODE (dest_reg)); | |
5248 | struct table_elt *dest_elt | |
5249 | = lookup (dest_reg, dest_hash, GET_MODE (dest_reg)); | |
5250 | rtx dest_cst = NULL; | |
5251 | ||
5252 | if (dest_elt) | |
5253 | for (p = dest_elt->first_same_value; p; p = p->next_same_value) | |
5254 | if (p->is_const && CONST_INT_P (p->exp)) | |
5255 | { | |
5256 | dest_cst = p->exp; | |
5257 | break; | |
5258 | } | |
5259 | if (dest_cst) | |
5260 | { | |
5261 | HOST_WIDE_INT val = INTVAL (dest_cst); | |
5262 | HOST_WIDE_INT mask; | |
5263 | unsigned int shift; | |
c7ad039d RS |
5264 | /* This is the mode of DEST_CST as well. */ |
5265 | scalar_int_mode dest_mode | |
5266 | = as_a <scalar_int_mode> (GET_MODE (dest_reg)); | |
b4ab701f | 5267 | if (BITS_BIG_ENDIAN) |
c7ad039d | 5268 | shift = GET_MODE_PRECISION (dest_mode) |
b4ab701f JJ |
5269 | - INTVAL (pos) - INTVAL (width); |
5270 | else | |
5271 | shift = INTVAL (pos); | |
5272 | if (INTVAL (width) == HOST_BITS_PER_WIDE_INT) | |
dd4786fe | 5273 | mask = HOST_WIDE_INT_M1; |
b4ab701f | 5274 | else |
fecfbfa4 | 5275 | mask = (HOST_WIDE_INT_1 << INTVAL (width)) - 1; |
b4ab701f JJ |
5276 | val &= ~(mask << shift); |
5277 | val |= (INTVAL (trial) & mask) << shift; | |
c7ad039d | 5278 | val = trunc_int_for_mode (val, dest_mode); |
b4ab701f JJ |
5279 | validate_unshare_change (insn, &SET_DEST (sets[i].rtl), |
5280 | dest_reg, 1); | |
5281 | validate_unshare_change (insn, &SET_SRC (sets[i].rtl), | |
5282 | GEN_INT (val), 1); | |
5283 | if (apply_change_group ()) | |
5284 | { | |
5285 | rtx note = find_reg_note (insn, REG_EQUAL, NULL_RTX); | |
5286 | if (note) | |
5287 | { | |
5288 | remove_note (insn, note); | |
5289 | df_notes_rescan (insn); | |
5290 | } | |
5291 | src_eqv = NULL_RTX; | |
5292 | src_eqv_elt = NULL; | |
5293 | src_eqv_volatile = 0; | |
5294 | src_eqv_in_memory = 0; | |
5295 | src_eqv_hash = 0; | |
5296 | repeat = true; | |
5297 | break; | |
5298 | } | |
5299 | } | |
5300 | } | |
5301 | ||
7afe21cc RK |
5302 | /* We don't normally have an insn matching (set (pc) (pc)), so |
5303 | check for this separately here. We will delete such an | |
5304 | insn below. | |
5305 | ||
d466c016 JL |
5306 | For other cases such as a table jump or conditional jump |
5307 | where we know the ultimate target, go ahead and replace the | |
5308 | operand. While that may not make a valid insn, we will | |
5309 | reemit the jump below (and also insert any necessary | |
5310 | barriers). */ | |
7afe21cc RK |
5311 | if (n_sets == 1 && dest == pc_rtx |
5312 | && (trial == pc_rtx | |
5313 | || (GET_CODE (trial) == LABEL_REF | |
5314 | && ! condjump_p (insn)))) | |
5315 | { | |
2f39b6ca UW |
5316 | /* Don't substitute non-local labels, this confuses CFG. */ |
5317 | if (GET_CODE (trial) == LABEL_REF | |
5318 | && LABEL_REF_NONLOCAL_P (trial)) | |
5319 | continue; | |
5320 | ||
d466c016 | 5321 | SET_SRC (sets[i].rtl) = trial; |
2aac3a01 | 5322 | cse_jumps_altered = true; |
7afe21cc RK |
5323 | break; |
5324 | } | |
278a83b2 | 5325 | |
dd77684f | 5326 | /* Similarly, lots of targets don't allow no-op |
aa535578 | 5327 | (set (mem x) (mem x)) moves. */ |
dd77684f | 5328 | else if (n_sets == 1 |
aa535578 RS |
5329 | && MEM_P (trial) |
5330 | && MEM_P (dest) | |
dd77684f JJ |
5331 | && rtx_equal_p (trial, dest) |
5332 | && !side_effects_p (dest) | |
5333 | && (cfun->can_delete_dead_exceptions | |
5334 | || insn_nothrow_p (insn))) | |
5335 | { | |
5336 | SET_SRC (sets[i].rtl) = trial; | |
aa535578 | 5337 | mem_noop_insn = true; |
dd77684f JJ |
5338 | break; |
5339 | } | |
5340 | ||
1ef6855c KH |
5341 | /* Reject certain invalid forms of CONST that we create. */ |
5342 | else if (CONSTANT_P (trial) | |
5343 | && GET_CODE (trial) == CONST | |
5344 | /* Reject cases that will cause decode_rtx_const to | |
5345 | die. On the alpha when simplifying a switch, we | |
5346 | get (const (truncate (minus (label_ref) | |
5347 | (label_ref)))). */ | |
5348 | && (GET_CODE (XEXP (trial, 0)) == TRUNCATE | |
5349 | /* Likewise on IA-64, except without the | |
5350 | truncate. */ | |
5351 | || (GET_CODE (XEXP (trial, 0)) == MINUS | |
5352 | && GET_CODE (XEXP (XEXP (trial, 0), 0)) == LABEL_REF | |
5353 | && GET_CODE (XEXP (XEXP (trial, 0), 1)) == LABEL_REF))) | |
5354 | /* Do nothing for this case. */ | |
5355 | ; | |
5356 | ||
23741374 BE |
5357 | /* Do not replace anything with a MEM, except the replacement |
5358 | is a no-op. This allows this loop to terminate. */ | |
5359 | else if (MEM_P (trial) && !rtx_equal_p (trial, SET_SRC(sets[i].rtl))) | |
5360 | /* Do nothing for this case. */ | |
5361 | ; | |
5362 | ||
7afe21cc | 5363 | /* Look for a substitution that makes a valid insn. */ |
6c4d60f8 JJ |
5364 | else if (validate_unshare_change (insn, &SET_SRC (sets[i].rtl), |
5365 | trial, 0)) | |
05c33dd8 | 5366 | { |
32e9fa48 | 5367 | rtx new_rtx = canon_reg (SET_SRC (sets[i].rtl), insn); |
dbaff908 | 5368 | |
7722328e RK |
5369 | /* The result of apply_change_group can be ignored; see |
5370 | canon_reg. */ | |
5371 | ||
32e9fa48 | 5372 | validate_change (insn, &SET_SRC (sets[i].rtl), new_rtx, 1); |
6702af89 | 5373 | apply_change_group (); |
932ad4d9 | 5374 | |
05c33dd8 RK |
5375 | break; |
5376 | } | |
7afe21cc | 5377 | |
278a83b2 | 5378 | /* If we previously found constant pool entries for |
7afe21cc RK |
5379 | constants and this is a constant, try making a |
5380 | pool entry. Put it in src_folded unless we already have done | |
5381 | this since that is where it likely came from. */ | |
5382 | ||
5383 | else if (constant_pool_entries_cost | |
5384 | && CONSTANT_P (trial) | |
1bbd065b | 5385 | && (src_folded == 0 |
3c0cb5de | 5386 | || (!MEM_P (src_folded) |
1bbd065b | 5387 | && ! src_folded_force_flag)) |
9ae8ffe7 JL |
5388 | && GET_MODE_CLASS (mode) != MODE_CC |
5389 | && mode != VOIDmode) | |
7afe21cc RK |
5390 | { |
5391 | src_folded_force_flag = 1; | |
5392 | src_folded = trial; | |
5393 | src_folded_cost = constant_pool_entries_cost; | |
dd0ba281 | 5394 | src_folded_regcost = constant_pool_entries_regcost; |
7afe21cc | 5395 | } |
278a83b2 | 5396 | } |
7afe21cc | 5397 | |
b4ab701f JJ |
5398 | /* If we changed the insn too much, handle this set from scratch. */ |
5399 | if (repeat) | |
5400 | { | |
5401 | i--; | |
5402 | continue; | |
5403 | } | |
5404 | ||
7afe21cc RK |
5405 | src = SET_SRC (sets[i].rtl); |
5406 | ||
5407 | /* In general, it is good to have a SET with SET_SRC == SET_DEST. | |
5408 | However, there is an important exception: If both are registers | |
5409 | that are not the head of their equivalence class, replace SET_SRC | |
5410 | with the head of the class. If we do not do this, we will have | |
5411 | both registers live over a portion of the basic block. This way, | |
5412 | their lifetimes will likely abut instead of overlapping. */ | |
f8cfc6aa | 5413 | if (REG_P (dest) |
1bb98cec | 5414 | && REGNO_QTY_VALID_P (REGNO (dest))) |
7afe21cc | 5415 | { |
1bb98cec DM |
5416 | int dest_q = REG_QTY (REGNO (dest)); |
5417 | struct qty_table_elem *dest_ent = &qty_table[dest_q]; | |
5418 | ||
5419 | if (dest_ent->mode == GET_MODE (dest) | |
5420 | && dest_ent->first_reg != REGNO (dest) | |
f8cfc6aa | 5421 | && REG_P (src) && REGNO (src) == REGNO (dest) |
1bb98cec DM |
5422 | /* Don't do this if the original insn had a hard reg as |
5423 | SET_SRC or SET_DEST. */ | |
f8cfc6aa | 5424 | && (!REG_P (sets[i].src) |
1bb98cec | 5425 | || REGNO (sets[i].src) >= FIRST_PSEUDO_REGISTER) |
f8cfc6aa | 5426 | && (!REG_P (dest) || REGNO (dest) >= FIRST_PSEUDO_REGISTER)) |
1bb98cec DM |
5427 | /* We can't call canon_reg here because it won't do anything if |
5428 | SRC is a hard register. */ | |
759bd8b7 | 5429 | { |
1bb98cec DM |
5430 | int src_q = REG_QTY (REGNO (src)); |
5431 | struct qty_table_elem *src_ent = &qty_table[src_q]; | |
5432 | int first = src_ent->first_reg; | |
5433 | rtx new_src | |
5434 | = (first >= FIRST_PSEUDO_REGISTER | |
5435 | ? regno_reg_rtx[first] : gen_rtx_REG (GET_MODE (src), first)); | |
5436 | ||
5437 | /* We must use validate-change even for this, because this | |
5438 | might be a special no-op instruction, suitable only to | |
5439 | tag notes onto. */ | |
5440 | if (validate_change (insn, &SET_SRC (sets[i].rtl), new_src, 0)) | |
5441 | { | |
5442 | src = new_src; | |
5443 | /* If we had a constant that is cheaper than what we are now | |
5444 | setting SRC to, use that constant. We ignored it when we | |
5445 | thought we could make this into a no-op. */ | |
e548c9df | 5446 | if (src_const && COST (src_const, mode) < COST (src, mode) |
278a83b2 KH |
5447 | && validate_change (insn, &SET_SRC (sets[i].rtl), |
5448 | src_const, 0)) | |
1bb98cec DM |
5449 | src = src_const; |
5450 | } | |
759bd8b7 | 5451 | } |
7afe21cc RK |
5452 | } |
5453 | ||
5454 | /* If we made a change, recompute SRC values. */ | |
5455 | if (src != sets[i].src) | |
278a83b2 | 5456 | { |
278a83b2 KH |
5457 | do_not_record = 0; |
5458 | hash_arg_in_memory = 0; | |
7afe21cc | 5459 | sets[i].src = src; |
278a83b2 KH |
5460 | sets[i].src_hash = HASH (src, mode); |
5461 | sets[i].src_volatile = do_not_record; | |
5462 | sets[i].src_in_memory = hash_arg_in_memory; | |
5463 | sets[i].src_elt = lookup (src, sets[i].src_hash, mode); | |
5464 | } | |
7afe21cc RK |
5465 | |
5466 | /* If this is a single SET, we are setting a register, and we have an | |
73dd3123 EB |
5467 | equivalent constant, we want to add a REG_EQUAL note if the constant |
5468 | is different from the source. We don't want to do it for a constant | |
5469 | pseudo since verifying that this pseudo hasn't been eliminated is a | |
5470 | pain; moreover such a note won't help anything. | |
ac7ef8d5 FS |
5471 | |
5472 | Avoid a REG_EQUAL note for (CONST (MINUS (LABEL_REF) (LABEL_REF))) | |
5473 | which can be created for a reference to a compile time computable | |
5474 | entry in a jump table. */ | |
73dd3123 EB |
5475 | if (n_sets == 1 |
5476 | && REG_P (dest) | |
5477 | && src_const | |
f8cfc6aa | 5478 | && !REG_P (src_const) |
73dd3123 EB |
5479 | && !(GET_CODE (src_const) == SUBREG |
5480 | && REG_P (SUBREG_REG (src_const))) | |
5481 | && !(GET_CODE (src_const) == CONST | |
5482 | && GET_CODE (XEXP (src_const, 0)) == MINUS | |
5483 | && GET_CODE (XEXP (XEXP (src_const, 0), 0)) == LABEL_REF | |
5484 | && GET_CODE (XEXP (XEXP (src_const, 0), 1)) == LABEL_REF) | |
5485 | && !rtx_equal_p (src, src_const)) | |
7afe21cc | 5486 | { |
73dd3123 EB |
5487 | /* Make sure that the rtx is not shared. */ |
5488 | src_const = copy_rtx (src_const); | |
51e2a951 | 5489 | |
73dd3123 EB |
5490 | /* Record the actual constant value in a REG_EQUAL note, |
5491 | making a new one if one does not already exist. */ | |
5492 | set_unique_reg_note (insn, REG_EQUAL, src_const); | |
5493 | df_notes_rescan (insn); | |
7afe21cc RK |
5494 | } |
5495 | ||
5496 | /* Now deal with the destination. */ | |
5497 | do_not_record = 0; | |
7afe21cc | 5498 | |
46d096a3 SB |
5499 | /* Look within any ZERO_EXTRACT to the MEM or REG within it. */ |
5500 | while (GET_CODE (dest) == SUBREG | |
7afe21cc | 5501 | || GET_CODE (dest) == ZERO_EXTRACT |
7afe21cc | 5502 | || GET_CODE (dest) == STRICT_LOW_PART) |
0339ce7e | 5503 | dest = XEXP (dest, 0); |
7afe21cc RK |
5504 | |
5505 | sets[i].inner_dest = dest; | |
5506 | ||
3c0cb5de | 5507 | if (MEM_P (dest)) |
7afe21cc | 5508 | { |
9ae8ffe7 JL |
5509 | #ifdef PUSH_ROUNDING |
5510 | /* Stack pushes invalidate the stack pointer. */ | |
5511 | rtx addr = XEXP (dest, 0); | |
ec8e098d | 5512 | if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC |
9ae8ffe7 | 5513 | && XEXP (addr, 0) == stack_pointer_rtx) |
524e3576 | 5514 | invalidate (stack_pointer_rtx, VOIDmode); |
9ae8ffe7 | 5515 | #endif |
7afe21cc | 5516 | dest = fold_rtx (dest, insn); |
7afe21cc RK |
5517 | } |
5518 | ||
5519 | /* Compute the hash code of the destination now, | |
5520 | before the effects of this instruction are recorded, | |
5521 | since the register values used in the address computation | |
5522 | are those before this instruction. */ | |
2197a88a | 5523 | sets[i].dest_hash = HASH (dest, mode); |
7afe21cc RK |
5524 | |
5525 | /* Don't enter a bit-field in the hash table | |
5526 | because the value in it after the store | |
5527 | may not equal what was stored, due to truncation. */ | |
5528 | ||
46d096a3 | 5529 | if (GET_CODE (SET_DEST (sets[i].rtl)) == ZERO_EXTRACT) |
7afe21cc RK |
5530 | { |
5531 | rtx width = XEXP (SET_DEST (sets[i].rtl), 1); | |
5532 | ||
481683e1 SZ |
5533 | if (src_const != 0 && CONST_INT_P (src_const) |
5534 | && CONST_INT_P (width) | |
906c4e36 RK |
5535 | && INTVAL (width) < HOST_BITS_PER_WIDE_INT |
5536 | && ! (INTVAL (src_const) | |
0cadbfaa | 5537 | & (HOST_WIDE_INT_M1U << INTVAL (width)))) |
7afe21cc RK |
5538 | /* Exception: if the value is constant, |
5539 | and it won't be truncated, record it. */ | |
5540 | ; | |
5541 | else | |
5542 | { | |
5543 | /* This is chosen so that the destination will be invalidated | |
5544 | but no new value will be recorded. | |
5545 | We must invalidate because sometimes constant | |
5546 | values can be recorded for bitfields. */ | |
5547 | sets[i].src_elt = 0; | |
5548 | sets[i].src_volatile = 1; | |
5549 | src_eqv = 0; | |
5550 | src_eqv_elt = 0; | |
5551 | } | |
5552 | } | |
5553 | ||
5554 | /* If only one set in a JUMP_INSN and it is now a no-op, we can delete | |
5555 | the insn. */ | |
5556 | else if (n_sets == 1 && dest == pc_rtx && src == pc_rtx) | |
5557 | { | |
ef178af3 | 5558 | /* One less use of the label this insn used to jump to. */ |
98ccd1d7 | 5559 | cse_cfg_altered |= delete_insn_and_edges (insn); |
2aac3a01 | 5560 | cse_jumps_altered = true; |
7afe21cc RK |
5561 | /* No more processing for this set. */ |
5562 | sets[i].rtl = 0; | |
5563 | } | |
5564 | ||
aa535578 RS |
5565 | /* Similarly for no-op MEM moves. */ |
5566 | else if (mem_noop_insn) | |
dd77684f JJ |
5567 | { |
5568 | if (cfun->can_throw_non_call_exceptions && can_throw_internal (insn)) | |
5569 | cse_cfg_altered = true; | |
98ccd1d7 | 5570 | cse_cfg_altered |= delete_insn_and_edges (insn); |
dd77684f JJ |
5571 | /* No more processing for this set. */ |
5572 | sets[i].rtl = 0; | |
5573 | } | |
5574 | ||
7afe21cc | 5575 | /* If this SET is now setting PC to a label, we know it used to |
d466c016 | 5576 | be a conditional or computed branch. */ |
8f235343 JH |
5577 | else if (dest == pc_rtx && GET_CODE (src) == LABEL_REF |
5578 | && !LABEL_REF_NONLOCAL_P (src)) | |
7afe21cc | 5579 | { |
d466c016 JL |
5580 | /* We reemit the jump in as many cases as possible just in |
5581 | case the form of an unconditional jump is significantly | |
5582 | different than a computed jump or conditional jump. | |
5583 | ||
5584 | If this insn has multiple sets, then reemitting the | |
5585 | jump is nontrivial. So instead we just force rerecognition | |
5586 | and hope for the best. */ | |
5587 | if (n_sets == 1) | |
7afe21cc | 5588 | { |
e67d1102 | 5589 | rtx_jump_insn *new_rtx; |
49506606 | 5590 | rtx note; |
8fb1e50e | 5591 | |
ec4a505f RS |
5592 | rtx_insn *seq = targetm.gen_jump (XEXP (src, 0)); |
5593 | new_rtx = emit_jump_insn_before (seq, insn); | |
32e9fa48 | 5594 | JUMP_LABEL (new_rtx) = XEXP (src, 0); |
7afe21cc | 5595 | LABEL_NUSES (XEXP (src, 0))++; |
9dcb4381 RH |
5596 | |
5597 | /* Make sure to copy over REG_NON_LOCAL_GOTO. */ | |
5598 | note = find_reg_note (insn, REG_NON_LOCAL_GOTO, 0); | |
5599 | if (note) | |
5600 | { | |
5601 | XEXP (note, 1) = NULL_RTX; | |
32e9fa48 | 5602 | REG_NOTES (new_rtx) = note; |
9dcb4381 RH |
5603 | } |
5604 | ||
98ccd1d7 | 5605 | cse_cfg_altered |= delete_insn_and_edges (insn); |
49506606 | 5606 | insn = new_rtx; |
7afe21cc | 5607 | } |
31dcf83f | 5608 | else |
31dcf83f | 5609 | INSN_CODE (insn) = -1; |
7afe21cc | 5610 | |
2aac3a01 EB |
5611 | /* Do not bother deleting any unreachable code, let jump do it. */ |
5612 | cse_jumps_altered = true; | |
7afe21cc RK |
5613 | sets[i].rtl = 0; |
5614 | } | |
5615 | ||
c2a47e48 RK |
5616 | /* If destination is volatile, invalidate it and then do no further |
5617 | processing for this assignment. */ | |
7afe21cc RK |
5618 | |
5619 | else if (do_not_record) | |
c2a47e48 | 5620 | { |
2a1d78d8 | 5621 | invalidate_dest (dest); |
c2a47e48 RK |
5622 | sets[i].rtl = 0; |
5623 | } | |
7afe21cc RK |
5624 | |
5625 | if (sets[i].rtl != 0 && dest != SET_DEST (sets[i].rtl)) | |
2a1d78d8 JJ |
5626 | { |
5627 | do_not_record = 0; | |
5628 | sets[i].dest_hash = HASH (SET_DEST (sets[i].rtl), mode); | |
5629 | if (do_not_record) | |
5630 | { | |
5631 | invalidate_dest (SET_DEST (sets[i].rtl)); | |
5632 | sets[i].rtl = 0; | |
5633 | } | |
5634 | } | |
7afe21cc | 5635 | |
7afe21cc RK |
5636 | /* If setting CC0, record what it was set to, or a constant, if it |
5637 | is equivalent to a constant. If it is being set to a floating-point | |
5638 | value, make a COMPARE with the appropriate constant of 0. If we | |
5639 | don't do this, later code can interpret this as a test against | |
5640 | const0_rtx, which can cause problems if we try to put it into an | |
5641 | insn as a floating-point operand. */ | |
5642 | if (dest == cc0_rtx) | |
5643 | { | |
5644 | this_insn_cc0 = src_const && mode != VOIDmode ? src_const : src; | |
5645 | this_insn_cc0_mode = mode; | |
cbf6a543 | 5646 | if (FLOAT_MODE_P (mode)) |
38a448ca RH |
5647 | this_insn_cc0 = gen_rtx_COMPARE (VOIDmode, this_insn_cc0, |
5648 | CONST0_RTX (mode)); | |
7afe21cc | 5649 | } |
7afe21cc RK |
5650 | } |
5651 | ||
5652 | /* Now enter all non-volatile source expressions in the hash table | |
5653 | if they are not already present. | |
5654 | Record their equivalence classes in src_elt. | |
5655 | This way we can insert the corresponding destinations into | |
5656 | the same classes even if the actual sources are no longer in them | |
5657 | (having been invalidated). */ | |
5658 | ||
5659 | if (src_eqv && src_eqv_elt == 0 && sets[0].rtl != 0 && ! src_eqv_volatile | |
5660 | && ! rtx_equal_p (src_eqv, SET_DEST (sets[0].rtl))) | |
5661 | { | |
b3694847 SS |
5662 | struct table_elt *elt; |
5663 | struct table_elt *classp = sets[0].src_elt; | |
7afe21cc | 5664 | rtx dest = SET_DEST (sets[0].rtl); |
ef4bddc2 | 5665 | machine_mode eqvmode = GET_MODE (dest); |
7afe21cc RK |
5666 | |
5667 | if (GET_CODE (dest) == STRICT_LOW_PART) | |
5668 | { | |
5669 | eqvmode = GET_MODE (SUBREG_REG (XEXP (dest, 0))); | |
5670 | classp = 0; | |
5671 | } | |
5672 | if (insert_regs (src_eqv, classp, 0)) | |
8ae2b8f6 JW |
5673 | { |
5674 | rehash_using_reg (src_eqv); | |
5675 | src_eqv_hash = HASH (src_eqv, eqvmode); | |
5676 | } | |
2197a88a | 5677 | elt = insert (src_eqv, classp, src_eqv_hash, eqvmode); |
7afe21cc | 5678 | elt->in_memory = src_eqv_in_memory; |
7afe21cc | 5679 | src_eqv_elt = elt; |
f7911249 JW |
5680 | |
5681 | /* Check to see if src_eqv_elt is the same as a set source which | |
5682 | does not yet have an elt, and if so set the elt of the set source | |
5683 | to src_eqv_elt. */ | |
5684 | for (i = 0; i < n_sets; i++) | |
26132f71 JW |
5685 | if (sets[i].rtl && sets[i].src_elt == 0 |
5686 | && rtx_equal_p (SET_SRC (sets[i].rtl), src_eqv)) | |
f7911249 | 5687 | sets[i].src_elt = src_eqv_elt; |
7afe21cc RK |
5688 | } |
5689 | ||
5690 | for (i = 0; i < n_sets; i++) | |
5691 | if (sets[i].rtl && ! sets[i].src_volatile | |
5692 | && ! rtx_equal_p (SET_SRC (sets[i].rtl), SET_DEST (sets[i].rtl))) | |
5693 | { | |
5694 | if (GET_CODE (SET_DEST (sets[i].rtl)) == STRICT_LOW_PART) | |
5695 | { | |
5696 | /* REG_EQUAL in setting a STRICT_LOW_PART | |
5697 | gives an equivalent for the entire destination register, | |
5698 | not just for the subreg being stored in now. | |
5699 | This is a more interesting equivalence, so we arrange later | |
5700 | to treat the entire reg as the destination. */ | |
5701 | sets[i].src_elt = src_eqv_elt; | |
2197a88a | 5702 | sets[i].src_hash = src_eqv_hash; |
7afe21cc RK |
5703 | } |
5704 | else | |
5705 | { | |
5706 | /* Insert source and constant equivalent into hash table, if not | |
5707 | already present. */ | |
b3694847 SS |
5708 | struct table_elt *classp = src_eqv_elt; |
5709 | rtx src = sets[i].src; | |
5710 | rtx dest = SET_DEST (sets[i].rtl); | |
ef4bddc2 | 5711 | machine_mode mode |
7afe21cc RK |
5712 | = GET_MODE (src) == VOIDmode ? GET_MODE (dest) : GET_MODE (src); |
5713 | ||
1fcc57f1 AM |
5714 | /* It's possible that we have a source value known to be |
5715 | constant but don't have a REG_EQUAL note on the insn. | |
5716 | Lack of a note will mean src_eqv_elt will be NULL. This | |
5717 | can happen where we've generated a SUBREG to access a | |
5718 | CONST_INT that is already in a register in a wider mode. | |
5719 | Ensure that the source expression is put in the proper | |
5720 | constant class. */ | |
5721 | if (!classp) | |
5722 | classp = sets[i].src_const_elt; | |
5723 | ||
26132f71 | 5724 | if (sets[i].src_elt == 0) |
7afe21cc | 5725 | { |
4a8cae83 | 5726 | struct table_elt *elt; |
26132f71 | 5727 | |
4a8cae83 SB |
5728 | /* Note that these insert_regs calls cannot remove |
5729 | any of the src_elt's, because they would have failed to | |
5730 | match if not still valid. */ | |
5731 | if (insert_regs (src, classp, 0)) | |
5732 | { | |
5733 | rehash_using_reg (src); | |
5734 | sets[i].src_hash = HASH (src, mode); | |
8ae2b8f6 | 5735 | } |
4a8cae83 SB |
5736 | elt = insert (src, classp, sets[i].src_hash, mode); |
5737 | elt->in_memory = sets[i].src_in_memory; | |
6c4d60f8 JJ |
5738 | /* If inline asm has any clobbers, ensure we only reuse |
5739 | existing inline asms and never try to put the ASM_OPERANDS | |
5740 | into an insn that isn't inline asm. */ | |
5741 | if (GET_CODE (src) == ASM_OPERANDS | |
5742 | && GET_CODE (x) == PARALLEL) | |
5743 | elt->cost = MAX_COST; | |
4a8cae83 | 5744 | sets[i].src_elt = classp = elt; |
7afe21cc | 5745 | } |
7afe21cc RK |
5746 | if (sets[i].src_const && sets[i].src_const_elt == 0 |
5747 | && src != sets[i].src_const | |
5748 | && ! rtx_equal_p (sets[i].src_const, src)) | |
5749 | sets[i].src_elt = insert (sets[i].src_const, classp, | |
2197a88a | 5750 | sets[i].src_const_hash, mode); |
7afe21cc RK |
5751 | } |
5752 | } | |
5753 | else if (sets[i].src_elt == 0) | |
5754 | /* If we did not insert the source into the hash table (e.g., it was | |
5755 | volatile), note the equivalence class for the REG_EQUAL value, if any, | |
5756 | so that the destination goes into that class. */ | |
5757 | sets[i].src_elt = src_eqv_elt; | |
5758 | ||
05c433f3 PB |
5759 | /* Record destination addresses in the hash table. This allows us to |
5760 | check if they are invalidated by other sets. */ | |
5761 | for (i = 0; i < n_sets; i++) | |
5762 | { | |
5763 | if (sets[i].rtl) | |
5764 | { | |
5765 | rtx x = sets[i].inner_dest; | |
5766 | struct table_elt *elt; | |
ef4bddc2 | 5767 | machine_mode mode; |
05c433f3 PB |
5768 | unsigned hash; |
5769 | ||
5770 | if (MEM_P (x)) | |
5771 | { | |
5772 | x = XEXP (x, 0); | |
5773 | mode = GET_MODE (x); | |
5774 | hash = HASH (x, mode); | |
5775 | elt = lookup (x, hash, mode); | |
5776 | if (!elt) | |
5777 | { | |
5778 | if (insert_regs (x, NULL, 0)) | |
5779 | { | |
7e7e28c7 AO |
5780 | rtx dest = SET_DEST (sets[i].rtl); |
5781 | ||
05c433f3 PB |
5782 | rehash_using_reg (x); |
5783 | hash = HASH (x, mode); | |
7e7e28c7 | 5784 | sets[i].dest_hash = HASH (dest, GET_MODE (dest)); |
05c433f3 PB |
5785 | } |
5786 | elt = insert (x, NULL, hash, mode); | |
5787 | } | |
5788 | ||
5789 | sets[i].dest_addr_elt = elt; | |
5790 | } | |
5791 | else | |
5792 | sets[i].dest_addr_elt = NULL; | |
5793 | } | |
5794 | } | |
5795 | ||
7b02f4e0 | 5796 | invalidate_from_clobbers (insn); |
77fa0940 | 5797 | |
278a83b2 | 5798 | /* Some registers are invalidated by subroutine calls. Memory is |
77fa0940 RK |
5799 | invalidated by non-constant calls. */ |
5800 | ||
4b4bf941 | 5801 | if (CALL_P (insn)) |
7afe21cc | 5802 | { |
becfd6e5 | 5803 | if (!(RTL_CONST_OR_PURE_CALL_P (insn))) |
9ae8ffe7 | 5804 | invalidate_memory (); |
67c25816 JJ |
5805 | else |
5806 | /* For const/pure calls, invalidate any argument slots, because | |
5807 | those are owned by the callee. */ | |
5808 | for (tem = CALL_INSN_FUNCTION_USAGE (insn); tem; tem = XEXP (tem, 1)) | |
5809 | if (GET_CODE (XEXP (tem, 0)) == USE | |
5810 | && MEM_P (XEXP (XEXP (tem, 0), 0))) | |
5811 | invalidate (XEXP (XEXP (tem, 0), 0), VOIDmode); | |
311b62ce | 5812 | invalidate_for_call (insn); |
7afe21cc RK |
5813 | } |
5814 | ||
5815 | /* Now invalidate everything set by this instruction. | |
5816 | If a SUBREG or other funny destination is being set, | |
5817 | sets[i].rtl is still nonzero, so here we invalidate the reg | |
5818 | a part of which is being set. */ | |
5819 | ||
5820 | for (i = 0; i < n_sets; i++) | |
5821 | if (sets[i].rtl) | |
5822 | { | |
bb4034b3 JW |
5823 | /* We can't use the inner dest, because the mode associated with |
5824 | a ZERO_EXTRACT is significant. */ | |
b3694847 | 5825 | rtx dest = SET_DEST (sets[i].rtl); |
7afe21cc RK |
5826 | |
5827 | /* Needed for registers to remove the register from its | |
5828 | previous quantity's chain. | |
5829 | Needed for memory if this is a nonvarying address, unless | |
5830 | we have just done an invalidate_memory that covers even those. */ | |
f8cfc6aa | 5831 | if (REG_P (dest) || GET_CODE (dest) == SUBREG) |
bb4034b3 | 5832 | invalidate (dest, VOIDmode); |
3c0cb5de | 5833 | else if (MEM_P (dest)) |
32fab725 | 5834 | invalidate (dest, VOIDmode); |
2708da92 RS |
5835 | else if (GET_CODE (dest) == STRICT_LOW_PART |
5836 | || GET_CODE (dest) == ZERO_EXTRACT) | |
bb4034b3 | 5837 | invalidate (XEXP (dest, 0), GET_MODE (dest)); |
7afe21cc RK |
5838 | } |
5839 | ||
932ad4d9 SB |
5840 | /* Don't cse over a call to setjmp; on some machines (eg VAX) |
5841 | the regs restored by the longjmp come from a later time | |
5842 | than the setjmp. */ | |
5843 | if (CALL_P (insn) && find_reg_note (insn, REG_SETJMP, NULL)) | |
5844 | { | |
5845 | flush_hash_table (); | |
5846 | goto done; | |
5847 | } | |
5848 | ||
7afe21cc RK |
5849 | /* Make sure registers mentioned in destinations |
5850 | are safe for use in an expression to be inserted. | |
5851 | This removes from the hash table | |
5852 | any invalid entry that refers to one of these registers. | |
5853 | ||
5854 | We don't care about the return value from mention_regs because | |
5855 | we are going to hash the SET_DEST values unconditionally. */ | |
5856 | ||
5857 | for (i = 0; i < n_sets; i++) | |
34c73909 R |
5858 | { |
5859 | if (sets[i].rtl) | |
5860 | { | |
5861 | rtx x = SET_DEST (sets[i].rtl); | |
5862 | ||
f8cfc6aa | 5863 | if (!REG_P (x)) |
34c73909 R |
5864 | mention_regs (x); |
5865 | else | |
5866 | { | |
5867 | /* We used to rely on all references to a register becoming | |
5868 | inaccessible when a register changes to a new quantity, | |
5869 | since that changes the hash code. However, that is not | |
9b1549b8 | 5870 | safe, since after HASH_SIZE new quantities we get a |
34c73909 R |
5871 | hash 'collision' of a register with its own invalid |
5872 | entries. And since SUBREGs have been changed not to | |
5873 | change their hash code with the hash code of the register, | |
5874 | it wouldn't work any longer at all. So we have to check | |
5875 | for any invalid references lying around now. | |
5876 | This code is similar to the REG case in mention_regs, | |
5877 | but it knows that reg_tick has been incremented, and | |
5878 | it leaves reg_in_table as -1 . */ | |
770ae6cc | 5879 | unsigned int regno = REGNO (x); |
09e18274 | 5880 | unsigned int endregno = END_REGNO (x); |
770ae6cc | 5881 | unsigned int i; |
34c73909 R |
5882 | |
5883 | for (i = regno; i < endregno; i++) | |
5884 | { | |
30f72379 | 5885 | if (REG_IN_TABLE (i) >= 0) |
34c73909 R |
5886 | { |
5887 | remove_invalid_refs (i); | |
30f72379 | 5888 | REG_IN_TABLE (i) = -1; |
34c73909 R |
5889 | } |
5890 | } | |
5891 | } | |
5892 | } | |
5893 | } | |
7afe21cc RK |
5894 | |
5895 | /* We may have just removed some of the src_elt's from the hash table. | |
05c433f3 PB |
5896 | So replace each one with the current head of the same class. |
5897 | Also check if destination addresses have been removed. */ | |
7afe21cc RK |
5898 | |
5899 | for (i = 0; i < n_sets; i++) | |
5900 | if (sets[i].rtl) | |
5901 | { | |
05c433f3 PB |
5902 | if (sets[i].dest_addr_elt |
5903 | && sets[i].dest_addr_elt->first_same_value == 0) | |
5904 | { | |
e67b81d1 | 5905 | /* The elt was removed, which means this destination is not |
05c433f3 PB |
5906 | valid after this instruction. */ |
5907 | sets[i].rtl = NULL_RTX; | |
5908 | } | |
5909 | else if (sets[i].src_elt && sets[i].src_elt->first_same_value == 0) | |
7afe21cc RK |
5910 | /* If elt was removed, find current head of same class, |
5911 | or 0 if nothing remains of that class. */ | |
5912 | { | |
b3694847 | 5913 | struct table_elt *elt = sets[i].src_elt; |
7afe21cc RK |
5914 | |
5915 | while (elt && elt->prev_same_value) | |
5916 | elt = elt->prev_same_value; | |
5917 | ||
5918 | while (elt && elt->first_same_value == 0) | |
5919 | elt = elt->next_same_value; | |
5920 | sets[i].src_elt = elt ? elt->first_same_value : 0; | |
5921 | } | |
5922 | } | |
5923 | ||
5924 | /* Now insert the destinations into their equivalence classes. */ | |
5925 | ||
5926 | for (i = 0; i < n_sets; i++) | |
5927 | if (sets[i].rtl) | |
5928 | { | |
b3694847 | 5929 | rtx dest = SET_DEST (sets[i].rtl); |
b3694847 | 5930 | struct table_elt *elt; |
7afe21cc RK |
5931 | |
5932 | /* Don't record value if we are not supposed to risk allocating | |
5933 | floating-point values in registers that might be wider than | |
5934 | memory. */ | |
5935 | if ((flag_float_store | |
3c0cb5de | 5936 | && MEM_P (dest) |
cbf6a543 | 5937 | && FLOAT_MODE_P (GET_MODE (dest))) |
bc4ddc77 JW |
5938 | /* Don't record BLKmode values, because we don't know the |
5939 | size of it, and can't be sure that other BLKmode values | |
5940 | have the same or smaller size. */ | |
5941 | || GET_MODE (dest) == BLKmode | |
7afe21cc RK |
5942 | /* If we didn't put a REG_EQUAL value or a source into the hash |
5943 | table, there is no point is recording DEST. */ | |
086ad22e | 5944 | || sets[i].src_elt == 0) |
7afe21cc RK |
5945 | continue; |
5946 | ||
5947 | /* STRICT_LOW_PART isn't part of the value BEING set, | |
5948 | and neither is the SUBREG inside it. | |
5949 | Note that in this case SETS[I].SRC_ELT is really SRC_EQV_ELT. */ | |
5950 | if (GET_CODE (dest) == STRICT_LOW_PART) | |
5951 | dest = SUBREG_REG (XEXP (dest, 0)); | |
5952 | ||
f8cfc6aa | 5953 | if (REG_P (dest) || GET_CODE (dest) == SUBREG) |
7afe21cc RK |
5954 | /* Registers must also be inserted into chains for quantities. */ |
5955 | if (insert_regs (dest, sets[i].src_elt, 1)) | |
8ae2b8f6 JW |
5956 | { |
5957 | /* If `insert_regs' changes something, the hash code must be | |
5958 | recalculated. */ | |
5959 | rehash_using_reg (dest); | |
5960 | sets[i].dest_hash = HASH (dest, GET_MODE (dest)); | |
5961 | } | |
7afe21cc | 5962 | |
086ad22e BE |
5963 | /* If DEST is a paradoxical SUBREG, don't record DEST since the bits |
5964 | outside the mode of GET_MODE (SUBREG_REG (dest)) are undefined. */ | |
5965 | if (paradoxical_subreg_p (dest)) | |
5966 | continue; | |
5967 | ||
8fff4fc1 RH |
5968 | elt = insert (dest, sets[i].src_elt, |
5969 | sets[i].dest_hash, GET_MODE (dest)); | |
9de2c71a | 5970 | |
2c5bfdf7 AN |
5971 | /* If this is a constant, insert the constant anchors with the |
5972 | equivalent register-offset expressions using register DEST. */ | |
5973 | if (targetm.const_anchor | |
5974 | && REG_P (dest) | |
5975 | && SCALAR_INT_MODE_P (GET_MODE (dest)) | |
5976 | && GET_CODE (sets[i].src_elt->exp) == CONST_INT) | |
5977 | insert_const_anchors (dest, sets[i].src_elt->exp, GET_MODE (dest)); | |
5978 | ||
3c0cb5de | 5979 | elt->in_memory = (MEM_P (sets[i].inner_dest) |
389fdba0 | 5980 | && !MEM_READONLY_P (sets[i].inner_dest)); |
c256df0b | 5981 | |
fc3ffe83 RK |
5982 | /* If we have (set (subreg:m1 (reg:m2 foo) 0) (bar:m1)), M1 is no |
5983 | narrower than M2, and both M1 and M2 are the same number of words, | |
5984 | we are also doing (set (reg:m2 foo) (subreg:m2 (bar:m1) 0)) so | |
5985 | make that equivalence as well. | |
7afe21cc | 5986 | |
4de249d9 PB |
5987 | However, BAR may have equivalences for which gen_lowpart |
5988 | will produce a simpler value than gen_lowpart applied to | |
7afe21cc | 5989 | BAR (e.g., if BAR was ZERO_EXTENDed from M2), so we will scan all |
278a83b2 | 5990 | BAR's equivalences. If we don't get a simplified form, make |
7afe21cc RK |
5991 | the SUBREG. It will not be used in an equivalence, but will |
5992 | cause two similar assignments to be detected. | |
5993 | ||
5994 | Note the loop below will find SUBREG_REG (DEST) since we have | |
5995 | already entered SRC and DEST of the SET in the table. */ | |
5996 | ||
5997 | if (GET_CODE (dest) == SUBREG | |
cf098191 RS |
5998 | && (known_equal_after_align_down |
5999 | (GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) - 1, | |
6000 | GET_MODE_SIZE (GET_MODE (dest)) - 1, | |
6001 | UNITS_PER_WORD)) | |
bd4288c0 | 6002 | && !partial_subreg_p (dest) |
7afe21cc RK |
6003 | && sets[i].src_elt != 0) |
6004 | { | |
ef4bddc2 | 6005 | machine_mode new_mode = GET_MODE (SUBREG_REG (dest)); |
7afe21cc RK |
6006 | struct table_elt *elt, *classp = 0; |
6007 | ||
6008 | for (elt = sets[i].src_elt->first_same_value; elt; | |
6009 | elt = elt->next_same_value) | |
6010 | { | |
6011 | rtx new_src = 0; | |
2197a88a | 6012 | unsigned src_hash; |
7afe21cc RK |
6013 | struct table_elt *src_elt; |
6014 | ||
6015 | /* Ignore invalid entries. */ | |
f8cfc6aa | 6016 | if (!REG_P (elt->exp) |
0516f6fe | 6017 | && ! exp_equiv_p (elt->exp, elt->exp, 1, false)) |
7afe21cc RK |
6018 | continue; |
6019 | ||
9beb7d20 RH |
6020 | /* We may have already been playing subreg games. If the |
6021 | mode is already correct for the destination, use it. */ | |
6022 | if (GET_MODE (elt->exp) == new_mode) | |
6023 | new_src = elt->exp; | |
6024 | else | |
6025 | { | |
91914e56 | 6026 | poly_uint64 byte |
610c45fc | 6027 | = subreg_lowpart_offset (new_mode, GET_MODE (dest)); |
9beb7d20 RH |
6028 | new_src = simplify_gen_subreg (new_mode, elt->exp, |
6029 | GET_MODE (dest), byte); | |
6030 | } | |
6031 | ||
ff27a429 R |
6032 | /* The call to simplify_gen_subreg fails if the value |
6033 | is VOIDmode, yet we can't do any simplification, e.g. | |
6034 | for EXPR_LISTs denoting function call results. | |
6035 | It is invalid to construct a SUBREG with a VOIDmode | |
6036 | SUBREG_REG, hence a zero new_src means we can't do | |
6037 | this substitution. */ | |
6038 | if (! new_src) | |
6039 | continue; | |
7afe21cc RK |
6040 | |
6041 | src_hash = HASH (new_src, new_mode); | |
6042 | src_elt = lookup (new_src, src_hash, new_mode); | |
6043 | ||
6044 | /* Put the new source in the hash table is if isn't | |
6045 | already. */ | |
6046 | if (src_elt == 0) | |
6047 | { | |
6048 | if (insert_regs (new_src, classp, 0)) | |
8ae2b8f6 JW |
6049 | { |
6050 | rehash_using_reg (new_src); | |
6051 | src_hash = HASH (new_src, new_mode); | |
6052 | } | |
7afe21cc RK |
6053 | src_elt = insert (new_src, classp, src_hash, new_mode); |
6054 | src_elt->in_memory = elt->in_memory; | |
6c4d60f8 JJ |
6055 | if (GET_CODE (new_src) == ASM_OPERANDS |
6056 | && elt->cost == MAX_COST) | |
6057 | src_elt->cost = MAX_COST; | |
7afe21cc RK |
6058 | } |
6059 | else if (classp && classp != src_elt->first_same_value) | |
278a83b2 | 6060 | /* Show that two things that we've seen before are |
7afe21cc RK |
6061 | actually the same. */ |
6062 | merge_equiv_classes (src_elt, classp); | |
6063 | ||
6064 | classp = src_elt->first_same_value; | |
da932f04 JL |
6065 | /* Ignore invalid entries. */ |
6066 | while (classp | |
f8cfc6aa | 6067 | && !REG_P (classp->exp) |
0516f6fe | 6068 | && ! exp_equiv_p (classp->exp, classp->exp, 1, false)) |
da932f04 | 6069 | classp = classp->next_same_value; |
7afe21cc RK |
6070 | } |
6071 | } | |
6072 | } | |
6073 | ||
403e25d0 RK |
6074 | /* Special handling for (set REG0 REG1) where REG0 is the |
6075 | "cheapest", cheaper than REG1. After cse, REG1 will probably not | |
6076 | be used in the sequel, so (if easily done) change this insn to | |
6077 | (set REG1 REG0) and replace REG1 with REG0 in the previous insn | |
6078 | that computed their value. Then REG1 will become a dead store | |
6079 | and won't cloud the situation for later optimizations. | |
7afe21cc RK |
6080 | |
6081 | Do not make this change if REG1 is a hard register, because it will | |
6082 | then be used in the sequel and we may be changing a two-operand insn | |
6083 | into a three-operand insn. | |
6084 | ||
4a8cae83 | 6085 | Also do not do this if we are operating on a copy of INSN. */ |
7afe21cc | 6086 | |
7b02f4e0 SB |
6087 | if (n_sets == 1 && sets[0].rtl) |
6088 | try_back_substitute_reg (sets[0].rtl, insn); | |
7afe21cc | 6089 | |
932ad4d9 | 6090 | done:; |
7afe21cc RK |
6091 | } |
6092 | \f | |
a4c6502a | 6093 | /* Remove from the hash table all expressions that reference memory. */ |
14a774a9 | 6094 | |
7afe21cc | 6095 | static void |
7080f735 | 6096 | invalidate_memory (void) |
7afe21cc | 6097 | { |
b3694847 SS |
6098 | int i; |
6099 | struct table_elt *p, *next; | |
7afe21cc | 6100 | |
9b1549b8 | 6101 | for (i = 0; i < HASH_SIZE; i++) |
9ae8ffe7 JL |
6102 | for (p = table[i]; p; p = next) |
6103 | { | |
6104 | next = p->next_same_hash; | |
6105 | if (p->in_memory) | |
6106 | remove_from_table (p, i); | |
6107 | } | |
6108 | } | |
6109 | ||
7b02f4e0 | 6110 | /* Perform invalidation on the basis of everything about INSN, |
7afe21cc RK |
6111 | except for invalidating the actual places that are SET in it. |
6112 | This includes the places CLOBBERed, and anything that might | |
7b02f4e0 | 6113 | alias with something that is SET or CLOBBERed. */ |
7afe21cc RK |
6114 | |
6115 | static void | |
20468884 | 6116 | invalidate_from_clobbers (rtx_insn *insn) |
7afe21cc | 6117 | { |
7b02f4e0 SB |
6118 | rtx x = PATTERN (insn); |
6119 | ||
7afe21cc RK |
6120 | if (GET_CODE (x) == CLOBBER) |
6121 | { | |
6122 | rtx ref = XEXP (x, 0); | |
9ae8ffe7 JL |
6123 | if (ref) |
6124 | { | |
f8cfc6aa | 6125 | if (REG_P (ref) || GET_CODE (ref) == SUBREG |
3c0cb5de | 6126 | || MEM_P (ref)) |
9ae8ffe7 JL |
6127 | invalidate (ref, VOIDmode); |
6128 | else if (GET_CODE (ref) == STRICT_LOW_PART | |
6129 | || GET_CODE (ref) == ZERO_EXTRACT) | |
6130 | invalidate (XEXP (ref, 0), GET_MODE (ref)); | |
6131 | } | |
7afe21cc RK |
6132 | } |
6133 | else if (GET_CODE (x) == PARALLEL) | |
6134 | { | |
b3694847 | 6135 | int i; |
7afe21cc RK |
6136 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) |
6137 | { | |
b3694847 | 6138 | rtx y = XVECEXP (x, 0, i); |
7afe21cc RK |
6139 | if (GET_CODE (y) == CLOBBER) |
6140 | { | |
6141 | rtx ref = XEXP (y, 0); | |
f8cfc6aa | 6142 | if (REG_P (ref) || GET_CODE (ref) == SUBREG |
3c0cb5de | 6143 | || MEM_P (ref)) |
9ae8ffe7 JL |
6144 | invalidate (ref, VOIDmode); |
6145 | else if (GET_CODE (ref) == STRICT_LOW_PART | |
6146 | || GET_CODE (ref) == ZERO_EXTRACT) | |
6147 | invalidate (XEXP (ref, 0), GET_MODE (ref)); | |
7afe21cc RK |
6148 | } |
6149 | } | |
6150 | } | |
6151 | } | |
6152 | \f | |
7b02f4e0 SB |
6153 | /* Perform invalidation on the basis of everything about INSN. |
6154 | This includes the places CLOBBERed, and anything that might | |
6155 | alias with something that is SET or CLOBBERed. */ | |
6156 | ||
6157 | static void | |
20468884 | 6158 | invalidate_from_sets_and_clobbers (rtx_insn *insn) |
7b02f4e0 SB |
6159 | { |
6160 | rtx tem; | |
6161 | rtx x = PATTERN (insn); | |
6162 | ||
6163 | if (CALL_P (insn)) | |
6164 | { | |
6165 | for (tem = CALL_INSN_FUNCTION_USAGE (insn); tem; tem = XEXP (tem, 1)) | |
99788e06 AH |
6166 | { |
6167 | rtx temx = XEXP (tem, 0); | |
6168 | if (GET_CODE (temx) == CLOBBER) | |
6169 | invalidate (SET_DEST (temx), VOIDmode); | |
99788e06 | 6170 | } |
7b02f4e0 SB |
6171 | } |
6172 | ||
6173 | /* Ensure we invalidate the destination register of a CALL insn. | |
6174 | This is necessary for machines where this register is a fixed_reg, | |
6175 | because no other code would invalidate it. */ | |
6176 | if (GET_CODE (x) == SET && GET_CODE (SET_SRC (x)) == CALL) | |
6177 | invalidate (SET_DEST (x), VOIDmode); | |
6178 | ||
6179 | else if (GET_CODE (x) == PARALLEL) | |
6180 | { | |
6181 | int i; | |
6182 | ||
6183 | for (i = XVECLEN (x, 0) - 1; i >= 0; i--) | |
6184 | { | |
6185 | rtx y = XVECEXP (x, 0, i); | |
6186 | if (GET_CODE (y) == CLOBBER) | |
6187 | { | |
6188 | rtx clobbered = XEXP (y, 0); | |
6189 | ||
6190 | if (REG_P (clobbered) | |
6191 | || GET_CODE (clobbered) == SUBREG) | |
6192 | invalidate (clobbered, VOIDmode); | |
6193 | else if (GET_CODE (clobbered) == STRICT_LOW_PART | |
6194 | || GET_CODE (clobbered) == ZERO_EXTRACT) | |
6195 | invalidate (XEXP (clobbered, 0), GET_MODE (clobbered)); | |
6196 | } | |
6197 | else if (GET_CODE (y) == SET && GET_CODE (SET_SRC (y)) == CALL) | |
6198 | invalidate (SET_DEST (y), VOIDmode); | |
6199 | } | |
6200 | } | |
6201 | } | |
6202 | \f | |
7afe21cc RK |
6203 | /* Process X, part of the REG_NOTES of an insn. Look at any REG_EQUAL notes |
6204 | and replace any registers in them with either an equivalent constant | |
6205 | or the canonical form of the register. If we are inside an address, | |
6206 | only do this if the address remains valid. | |
6207 | ||
6208 | OBJECT is 0 except when within a MEM in which case it is the MEM. | |
6209 | ||
6210 | Return the replacement for X. */ | |
6211 | ||
6212 | static rtx | |
6fb5fa3c | 6213 | cse_process_notes_1 (rtx x, rtx object, bool *changed) |
7afe21cc RK |
6214 | { |
6215 | enum rtx_code code = GET_CODE (x); | |
6f7d635c | 6216 | const char *fmt = GET_RTX_FORMAT (code); |
7afe21cc RK |
6217 | int i; |
6218 | ||
6219 | switch (code) | |
6220 | { | |
7afe21cc RK |
6221 | case CONST: |
6222 | case SYMBOL_REF: | |
6223 | case LABEL_REF: | |
d8116890 | 6224 | CASE_CONST_ANY: |
7afe21cc RK |
6225 | case PC: |
6226 | case CC0: | |
6227 | case LO_SUM: | |
6228 | return x; | |
6229 | ||
6230 | case MEM: | |
c96208fa | 6231 | validate_change (x, &XEXP (x, 0), |
6fb5fa3c | 6232 | cse_process_notes (XEXP (x, 0), x, changed), 0); |
7afe21cc RK |
6233 | return x; |
6234 | ||
6235 | case EXPR_LIST: | |
7afe21cc | 6236 | if (REG_NOTE_KIND (x) == REG_EQUAL) |
6fb5fa3c | 6237 | XEXP (x, 0) = cse_process_notes (XEXP (x, 0), NULL_RTX, changed); |
e5af9ddd RS |
6238 | /* Fall through. */ |
6239 | ||
6240 | case INSN_LIST: | |
6241 | case INT_LIST: | |
7afe21cc | 6242 | if (XEXP (x, 1)) |
6fb5fa3c | 6243 | XEXP (x, 1) = cse_process_notes (XEXP (x, 1), NULL_RTX, changed); |
7afe21cc RK |
6244 | return x; |
6245 | ||
e4890d45 RS |
6246 | case SIGN_EXTEND: |
6247 | case ZERO_EXTEND: | |
0b0ee36c | 6248 | case SUBREG: |
e4890d45 | 6249 | { |
32e9fa48 | 6250 | rtx new_rtx = cse_process_notes (XEXP (x, 0), object, changed); |
e4890d45 RS |
6251 | /* We don't substitute VOIDmode constants into these rtx, |
6252 | since they would impede folding. */ | |
32e9fa48 KG |
6253 | if (GET_MODE (new_rtx) != VOIDmode) |
6254 | validate_change (object, &XEXP (x, 0), new_rtx, 0); | |
e4890d45 RS |
6255 | return x; |
6256 | } | |
6257 | ||
dfebbdc6 JJ |
6258 | case UNSIGNED_FLOAT: |
6259 | { | |
6260 | rtx new_rtx = cse_process_notes (XEXP (x, 0), object, changed); | |
6261 | /* We don't substitute negative VOIDmode constants into these rtx, | |
6262 | since they would impede folding. */ | |
6263 | if (GET_MODE (new_rtx) != VOIDmode | |
6264 | || (CONST_INT_P (new_rtx) && INTVAL (new_rtx) >= 0) | |
6265 | || (CONST_DOUBLE_P (new_rtx) && CONST_DOUBLE_HIGH (new_rtx) >= 0)) | |
6266 | validate_change (object, &XEXP (x, 0), new_rtx, 0); | |
6267 | return x; | |
6268 | } | |
6269 | ||
7afe21cc | 6270 | case REG: |
30f72379 | 6271 | i = REG_QTY (REGNO (x)); |
7afe21cc RK |
6272 | |
6273 | /* Return a constant or a constant register. */ | |
1bb98cec | 6274 | if (REGNO_QTY_VALID_P (REGNO (x))) |
7afe21cc | 6275 | { |
1bb98cec DM |
6276 | struct qty_table_elem *ent = &qty_table[i]; |
6277 | ||
6278 | if (ent->const_rtx != NULL_RTX | |
6279 | && (CONSTANT_P (ent->const_rtx) | |
f8cfc6aa | 6280 | || REG_P (ent->const_rtx))) |
1bb98cec | 6281 | { |
32e9fa48 KG |
6282 | rtx new_rtx = gen_lowpart (GET_MODE (x), ent->const_rtx); |
6283 | if (new_rtx) | |
6284 | return copy_rtx (new_rtx); | |
1bb98cec | 6285 | } |
7afe21cc RK |
6286 | } |
6287 | ||
6288 | /* Otherwise, canonicalize this register. */ | |
20468884 | 6289 | return canon_reg (x, NULL); |
278a83b2 | 6290 | |
e9a25f70 JL |
6291 | default: |
6292 | break; | |
7afe21cc RK |
6293 | } |
6294 | ||
6295 | for (i = 0; i < GET_RTX_LENGTH (code); i++) | |
6296 | if (fmt[i] == 'e') | |
6297 | validate_change (object, &XEXP (x, i), | |
6fb5fa3c | 6298 | cse_process_notes (XEXP (x, i), object, changed), 0); |
7afe21cc RK |
6299 | |
6300 | return x; | |
6301 | } | |
6fb5fa3c DB |
6302 | |
6303 | static rtx | |
6304 | cse_process_notes (rtx x, rtx object, bool *changed) | |
6305 | { | |
32e9fa48 KG |
6306 | rtx new_rtx = cse_process_notes_1 (x, object, changed); |
6307 | if (new_rtx != x) | |
6fb5fa3c | 6308 | *changed = true; |
32e9fa48 | 6309 | return new_rtx; |
6fb5fa3c DB |
6310 | } |
6311 | ||
7afe21cc | 6312 | \f |
932ad4d9 | 6313 | /* Find a path in the CFG, starting with FIRST_BB to perform CSE on. |
7afe21cc | 6314 | |
932ad4d9 SB |
6315 | DATA is a pointer to a struct cse_basic_block_data, that is used to |
6316 | describe the path. | |
6317 | It is filled with a queue of basic blocks, starting with FIRST_BB | |
6318 | and following a trace through the CFG. | |
b8698a0f | 6319 | |
932ad4d9 SB |
6320 | If all paths starting at FIRST_BB have been followed, or no new path |
6321 | starting at FIRST_BB can be constructed, this function returns FALSE. | |
6322 | Otherwise, DATA->path is filled and the function returns TRUE indicating | |
6323 | that a path to follow was found. | |
7afe21cc | 6324 | |
2e226e66 | 6325 | If FOLLOW_JUMPS is false, the maximum path length is 1 and the only |
932ad4d9 | 6326 | block in the path will be FIRST_BB. */ |
7afe21cc | 6327 | |
932ad4d9 SB |
6328 | static bool |
6329 | cse_find_path (basic_block first_bb, struct cse_basic_block_data *data, | |
6330 | int follow_jumps) | |
7afe21cc | 6331 | { |
932ad4d9 SB |
6332 | basic_block bb; |
6333 | edge e; | |
6334 | int path_size; | |
b8698a0f | 6335 | |
d7c028c0 | 6336 | bitmap_set_bit (cse_visited_basic_blocks, first_bb->index); |
7afe21cc | 6337 | |
932ad4d9 SB |
6338 | /* See if there is a previous path. */ |
6339 | path_size = data->path_size; | |
6340 | ||
6341 | /* There is a previous path. Make sure it started with FIRST_BB. */ | |
6342 | if (path_size) | |
6343 | gcc_assert (data->path[0].bb == first_bb); | |
6344 | ||
6345 | /* There was only one basic block in the last path. Clear the path and | |
6346 | return, so that paths starting at another basic block can be tried. */ | |
6347 | if (path_size == 1) | |
6348 | { | |
6349 | path_size = 0; | |
6350 | goto done; | |
6351 | } | |
6352 | ||
6353 | /* If the path was empty from the beginning, construct a new path. */ | |
6354 | if (path_size == 0) | |
6355 | data->path[path_size++].bb = first_bb; | |
6356 | else | |
7afe21cc | 6357 | { |
932ad4d9 SB |
6358 | /* Otherwise, path_size must be equal to or greater than 2, because |
6359 | a previous path exists that is at least two basic blocks long. | |
6360 | ||
6361 | Update the previous branch path, if any. If the last branch was | |
6362 | previously along the branch edge, take the fallthrough edge now. */ | |
6363 | while (path_size >= 2) | |
7afe21cc | 6364 | { |
932ad4d9 SB |
6365 | basic_block last_bb_in_path, previous_bb_in_path; |
6366 | edge e; | |
6367 | ||
6368 | --path_size; | |
6369 | last_bb_in_path = data->path[path_size].bb; | |
6370 | previous_bb_in_path = data->path[path_size - 1].bb; | |
6371 | ||
6372 | /* If we previously followed a path along the branch edge, try | |
6373 | the fallthru edge now. */ | |
6374 | if (EDGE_COUNT (previous_bb_in_path->succs) == 2 | |
6375 | && any_condjump_p (BB_END (previous_bb_in_path)) | |
6376 | && (e = find_edge (previous_bb_in_path, last_bb_in_path)) | |
6377 | && e == BRANCH_EDGE (previous_bb_in_path)) | |
6378 | { | |
6379 | bb = FALLTHRU_EDGE (previous_bb_in_path)->dest; | |
fefa31b5 | 6380 | if (bb != EXIT_BLOCK_PTR_FOR_FN (cfun) |
481e0a49 AO |
6381 | && single_pred_p (bb) |
6382 | /* We used to assert here that we would only see blocks | |
6383 | that we have not visited yet. But we may end up | |
6384 | visiting basic blocks twice if the CFG has changed | |
6385 | in this run of cse_main, because when the CFG changes | |
6386 | the topological sort of the CFG also changes. A basic | |
6387 | blocks that previously had more than two predecessors | |
6388 | may now have a single predecessor, and become part of | |
6389 | a path that starts at another basic block. | |
6390 | ||
6391 | We still want to visit each basic block only once, so | |
6392 | halt the path here if we have already visited BB. */ | |
d7c028c0 | 6393 | && !bitmap_bit_p (cse_visited_basic_blocks, bb->index)) |
932ad4d9 | 6394 | { |
d7c028c0 | 6395 | bitmap_set_bit (cse_visited_basic_blocks, bb->index); |
932ad4d9 SB |
6396 | data->path[path_size++].bb = bb; |
6397 | break; | |
6398 | } | |
6399 | } | |
6400 | ||
6401 | data->path[path_size].bb = NULL; | |
6402 | } | |
6403 | ||
6404 | /* If only one block remains in the path, bail. */ | |
6405 | if (path_size == 1) | |
6406 | { | |
6407 | path_size = 0; | |
6408 | goto done; | |
7afe21cc | 6409 | } |
7afe21cc RK |
6410 | } |
6411 | ||
932ad4d9 SB |
6412 | /* Extend the path if possible. */ |
6413 | if (follow_jumps) | |
7afe21cc | 6414 | { |
932ad4d9 | 6415 | bb = data->path[path_size - 1].bb; |
028d4092 | 6416 | while (bb && path_size < param_max_cse_path_length) |
932ad4d9 SB |
6417 | { |
6418 | if (single_succ_p (bb)) | |
6419 | e = single_succ_edge (bb); | |
6420 | else if (EDGE_COUNT (bb->succs) == 2 | |
6421 | && any_condjump_p (BB_END (bb))) | |
6422 | { | |
6423 | /* First try to follow the branch. If that doesn't lead | |
6424 | to a useful path, follow the fallthru edge. */ | |
6425 | e = BRANCH_EDGE (bb); | |
6426 | if (!single_pred_p (e->dest)) | |
6427 | e = FALLTHRU_EDGE (bb); | |
6428 | } | |
6429 | else | |
6430 | e = NULL; | |
7afe21cc | 6431 | |
bc6d3f91 | 6432 | if (e |
76015c34 | 6433 | && !((e->flags & EDGE_ABNORMAL_CALL) && cfun->has_nonlocal_label) |
fefa31b5 | 6434 | && e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun) |
481e0a49 AO |
6435 | && single_pred_p (e->dest) |
6436 | /* Avoid visiting basic blocks twice. The large comment | |
6437 | above explains why this can happen. */ | |
d7c028c0 | 6438 | && !bitmap_bit_p (cse_visited_basic_blocks, e->dest->index)) |
932ad4d9 SB |
6439 | { |
6440 | basic_block bb2 = e->dest; | |
d7c028c0 | 6441 | bitmap_set_bit (cse_visited_basic_blocks, bb2->index); |
932ad4d9 SB |
6442 | data->path[path_size++].bb = bb2; |
6443 | bb = bb2; | |
6444 | } | |
6445 | else | |
6446 | bb = NULL; | |
6447 | } | |
6448 | } | |
6449 | ||
6450 | done: | |
6451 | data->path_size = path_size; | |
6452 | return path_size != 0; | |
6453 | } | |
6454 | \f | |
6455 | /* Dump the path in DATA to file F. NSETS is the number of sets | |
6456 | in the path. */ | |
6457 | ||
6458 | static void | |
6459 | cse_dump_path (struct cse_basic_block_data *data, int nsets, FILE *f) | |
6460 | { | |
6461 | int path_entry; | |
6462 | ||
6463 | fprintf (f, ";; Following path with %d sets: ", nsets); | |
6464 | for (path_entry = 0; path_entry < data->path_size; path_entry++) | |
6465 | fprintf (f, "%d ", (data->path[path_entry].bb)->index); | |
a29dd8dd | 6466 | fputc ('\n', f); |
932ad4d9 SB |
6467 | fflush (f); |
6468 | } | |
6469 | ||
a7582f7c SB |
6470 | \f |
6471 | /* Return true if BB has exception handling successor edges. */ | |
6472 | ||
6473 | static bool | |
6474 | have_eh_succ_edges (basic_block bb) | |
6475 | { | |
6476 | edge e; | |
6477 | edge_iterator ei; | |
6478 | ||
6479 | FOR_EACH_EDGE (e, ei, bb->succs) | |
6480 | if (e->flags & EDGE_EH) | |
6481 | return true; | |
6482 | ||
6483 | return false; | |
6484 | } | |
6485 | ||
932ad4d9 SB |
6486 | \f |
6487 | /* Scan to the end of the path described by DATA. Return an estimate of | |
6fb5fa3c | 6488 | the total number of SETs of all insns in the path. */ |
932ad4d9 SB |
6489 | |
6490 | static void | |
6491 | cse_prescan_path (struct cse_basic_block_data *data) | |
6492 | { | |
6493 | int nsets = 0; | |
932ad4d9 SB |
6494 | int path_size = data->path_size; |
6495 | int path_entry; | |
6496 | ||
6497 | /* Scan to end of each basic block in the path. */ | |
b8698a0f | 6498 | for (path_entry = 0; path_entry < path_size; path_entry++) |
932ad4d9 SB |
6499 | { |
6500 | basic_block bb; | |
20468884 | 6501 | rtx_insn *insn; |
164c8956 | 6502 | |
932ad4d9 | 6503 | bb = data->path[path_entry].bb; |
7afe21cc | 6504 | |
932ad4d9 | 6505 | FOR_BB_INSNS (bb, insn) |
7afe21cc | 6506 | { |
932ad4d9 SB |
6507 | if (!INSN_P (insn)) |
6508 | continue; | |
278a83b2 | 6509 | |
932ad4d9 SB |
6510 | /* A PARALLEL can have lots of SETs in it, |
6511 | especially if it is really an ASM_OPERANDS. */ | |
6512 | if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
6513 | nsets += XVECLEN (PATTERN (insn), 0); | |
6514 | else | |
6515 | nsets += 1; | |
7afe21cc | 6516 | } |
932ad4d9 SB |
6517 | } |
6518 | ||
932ad4d9 SB |
6519 | data->nsets = nsets; |
6520 | } | |
6521 | \f | |
f0002948 RS |
6522 | /* Return true if the pattern of INSN uses a LABEL_REF for which |
6523 | there isn't a REG_LABEL_OPERAND note. */ | |
6524 | ||
6525 | static bool | |
6526 | check_for_label_ref (rtx_insn *insn) | |
6527 | { | |
6528 | /* If this insn uses a LABEL_REF and there isn't a REG_LABEL_OPERAND | |
6529 | note for it, we must rerun jump since it needs to place the note. If | |
6530 | this is a LABEL_REF for a CODE_LABEL that isn't in the insn chain, | |
6531 | don't do this since no REG_LABEL_OPERAND will be added. */ | |
6532 | subrtx_iterator::array_type array; | |
6533 | FOR_EACH_SUBRTX (iter, array, PATTERN (insn), ALL) | |
6534 | { | |
6535 | const_rtx x = *iter; | |
6536 | if (GET_CODE (x) == LABEL_REF | |
6537 | && !LABEL_REF_NONLOCAL_P (x) | |
6538 | && (!JUMP_P (insn) | |
04a121a7 TS |
6539 | || !label_is_jump_target_p (label_ref_label (x), insn)) |
6540 | && LABEL_P (label_ref_label (x)) | |
6541 | && INSN_UID (label_ref_label (x)) != 0 | |
6542 | && !find_reg_note (insn, REG_LABEL_OPERAND, label_ref_label (x))) | |
f0002948 RS |
6543 | return true; |
6544 | } | |
6545 | return false; | |
6546 | } | |
6547 | ||
932ad4d9 | 6548 | /* Process a single extended basic block described by EBB_DATA. */ |
7afe21cc | 6549 | |
932ad4d9 SB |
6550 | static void |
6551 | cse_extended_basic_block (struct cse_basic_block_data *ebb_data) | |
6552 | { | |
6553 | int path_size = ebb_data->path_size; | |
6554 | int path_entry; | |
6555 | int num_insns = 0; | |
6556 | ||
6557 | /* Allocate the space needed by qty_table. */ | |
6558 | qty_table = XNEWVEC (struct qty_table_elem, max_qty); | |
6559 | ||
6560 | new_basic_block (); | |
89a95777 KZ |
6561 | cse_ebb_live_in = df_get_live_in (ebb_data->path[0].bb); |
6562 | cse_ebb_live_out = df_get_live_out (ebb_data->path[path_size - 1].bb); | |
932ad4d9 SB |
6563 | for (path_entry = 0; path_entry < path_size; path_entry++) |
6564 | { | |
6565 | basic_block bb; | |
20468884 | 6566 | rtx_insn *insn; |
932ad4d9 SB |
6567 | |
6568 | bb = ebb_data->path[path_entry].bb; | |
e186ff69 AK |
6569 | |
6570 | /* Invalidate recorded information for eh regs if there is an EH | |
6571 | edge pointing to that bb. */ | |
6572 | if (bb_has_eh_pred (bb)) | |
6573 | { | |
292321a5 | 6574 | df_ref def; |
e186ff69 | 6575 | |
292321a5 RS |
6576 | FOR_EACH_ARTIFICIAL_DEF (def, bb->index) |
6577 | if (DF_REF_FLAGS (def) & DF_REF_AT_TOP) | |
6578 | invalidate (DF_REF_REG (def), GET_MODE (DF_REF_REG (def))); | |
e186ff69 AK |
6579 | } |
6580 | ||
9fcb01de | 6581 | optimize_this_for_speed_p = optimize_bb_for_speed_p (bb); |
ba4807a0 | 6582 | FOR_BB_INSNS (bb, insn) |
7afe21cc | 6583 | { |
932ad4d9 SB |
6584 | /* If we have processed 1,000 insns, flush the hash table to |
6585 | avoid extreme quadratic behavior. We must not include NOTEs | |
6586 | in the count since there may be more of them when generating | |
6587 | debugging information. If we clear the table at different | |
6588 | times, code generated with -g -O might be different than code | |
6589 | generated with -O but not -g. | |
6590 | ||
6591 | FIXME: This is a real kludge and needs to be done some other | |
6592 | way. */ | |
b5b8b0ac | 6593 | if (NONDEBUG_INSN_P (insn) |
028d4092 | 6594 | && num_insns++ > param_max_cse_insns) |
932ad4d9 SB |
6595 | { |
6596 | flush_hash_table (); | |
6597 | num_insns = 0; | |
6598 | } | |
7afe21cc | 6599 | |
932ad4d9 | 6600 | if (INSN_P (insn)) |
7afe21cc | 6601 | { |
932ad4d9 SB |
6602 | /* Process notes first so we have all notes in canonical forms |
6603 | when looking for duplicate operations. */ | |
6604 | if (REG_NOTES (insn)) | |
6fb5fa3c DB |
6605 | { |
6606 | bool changed = false; | |
6607 | REG_NOTES (insn) = cse_process_notes (REG_NOTES (insn), | |
6608 | NULL_RTX, &changed); | |
6609 | if (changed) | |
6610 | df_notes_rescan (insn); | |
6611 | } | |
932ad4d9 | 6612 | |
4a8cae83 | 6613 | cse_insn (insn); |
932ad4d9 | 6614 | |
932ad4d9 SB |
6615 | /* If we haven't already found an insn where we added a LABEL_REF, |
6616 | check this one. */ | |
2aac3a01 | 6617 | if (INSN_P (insn) && !recorded_label_ref |
f0002948 | 6618 | && check_for_label_ref (insn)) |
2aac3a01 | 6619 | recorded_label_ref = true; |
96fb470d | 6620 | |
058eb3b0 | 6621 | if (HAVE_cc0 && NONDEBUG_INSN_P (insn)) |
96fb470d | 6622 | { |
5f262d13 AO |
6623 | /* If the previous insn sets CC0 and this insn no |
6624 | longer references CC0, delete the previous insn. | |
6625 | Here we use fact that nothing expects CC0 to be | |
6626 | valid over an insn, which is true until the final | |
6627 | pass. */ | |
20468884 DM |
6628 | rtx_insn *prev_insn; |
6629 | rtx tem; | |
5f262d13 AO |
6630 | |
6631 | prev_insn = prev_nonnote_nondebug_insn (insn); | |
6632 | if (prev_insn && NONJUMP_INSN_P (prev_insn) | |
6633 | && (tem = single_set (prev_insn)) != NULL_RTX | |
6634 | && SET_DEST (tem) == cc0_rtx | |
6635 | && ! reg_mentioned_p (cc0_rtx, PATTERN (insn))) | |
6636 | delete_insn (prev_insn); | |
6637 | ||
6638 | /* If this insn is not the last insn in the basic | |
6639 | block, it will be PREV_INSN(insn) in the next | |
6640 | iteration. If we recorded any CC0-related | |
6641 | information for this insn, remember it. */ | |
6642 | if (insn != BB_END (bb)) | |
6643 | { | |
6644 | prev_insn_cc0 = this_insn_cc0; | |
6645 | prev_insn_cc0_mode = this_insn_cc0_mode; | |
6646 | } | |
96fb470d | 6647 | } |
932ad4d9 SB |
6648 | } |
6649 | } | |
7afe21cc | 6650 | |
a7582f7c SB |
6651 | /* With non-call exceptions, we are not always able to update |
6652 | the CFG properly inside cse_insn. So clean up possibly | |
6653 | redundant EH edges here. */ | |
8f4f502f | 6654 | if (cfun->can_throw_non_call_exceptions && have_eh_succ_edges (bb)) |
2aac3a01 | 6655 | cse_cfg_altered |= purge_dead_edges (bb); |
a7582f7c | 6656 | |
932ad4d9 SB |
6657 | /* If we changed a conditional jump, we may have terminated |
6658 | the path we are following. Check that by verifying that | |
6659 | the edge we would take still exists. If the edge does | |
6660 | not exist anymore, purge the remainder of the path. | |
6661 | Note that this will cause us to return to the caller. */ | |
6662 | if (path_entry < path_size - 1) | |
6663 | { | |
6664 | basic_block next_bb = ebb_data->path[path_entry + 1].bb; | |
6665 | if (!find_edge (bb, next_bb)) | |
27511c65 SB |
6666 | { |
6667 | do | |
6668 | { | |
6669 | path_size--; | |
6670 | ||
6671 | /* If we truncate the path, we must also reset the | |
6672 | visited bit on the remaining blocks in the path, | |
6673 | or we will never visit them at all. */ | |
d7c028c0 | 6674 | bitmap_clear_bit (cse_visited_basic_blocks, |
27511c65 SB |
6675 | ebb_data->path[path_size].bb->index); |
6676 | ebb_data->path[path_size].bb = NULL; | |
6677 | } | |
6678 | while (path_size - 1 != path_entry); | |
6679 | ebb_data->path_size = path_size; | |
6680 | } | |
7afe21cc | 6681 | } |
7afe21cc | 6682 | |
932ad4d9 SB |
6683 | /* If this is a conditional jump insn, record any known |
6684 | equivalences due to the condition being tested. */ | |
6685 | insn = BB_END (bb); | |
6686 | if (path_entry < path_size - 1 | |
e2da9ffe | 6687 | && EDGE_COUNT (bb->succs) == 2 |
932ad4d9 SB |
6688 | && JUMP_P (insn) |
6689 | && single_set (insn) | |
6690 | && any_condjump_p (insn)) | |
6691 | { | |
6692 | basic_block next_bb = ebb_data->path[path_entry + 1].bb; | |
6693 | bool taken = (next_bb == BRANCH_EDGE (bb)->dest); | |
6694 | record_jump_equiv (insn, taken); | |
6695 | } | |
96fb470d | 6696 | |
96fb470d SB |
6697 | /* Clear the CC0-tracking related insns, they can't provide |
6698 | useful information across basic block boundaries. */ | |
6699 | prev_insn_cc0 = 0; | |
932ad4d9 | 6700 | } |
7afe21cc | 6701 | |
932ad4d9 | 6702 | gcc_assert (next_qty <= max_qty); |
7afe21cc | 6703 | |
932ad4d9 | 6704 | free (qty_table); |
7afe21cc | 6705 | } |
6fb5fa3c | 6706 | |
7afe21cc | 6707 | \f |
7afe21cc RK |
6708 | /* Perform cse on the instructions of a function. |
6709 | F is the first instruction. | |
6710 | NREGS is one plus the highest pseudo-reg number used in the instruction. | |
6711 | ||
2aac3a01 EB |
6712 | Return 2 if jump optimizations should be redone due to simplifications |
6713 | in conditional jump instructions. | |
6714 | Return 1 if the CFG should be cleaned up because it has been modified. | |
6715 | Return 0 otherwise. */ | |
7afe21cc | 6716 | |
711417cd | 6717 | static int |
20468884 | 6718 | cse_main (rtx_insn *f ATTRIBUTE_UNUSED, int nregs) |
7afe21cc | 6719 | { |
932ad4d9 SB |
6720 | struct cse_basic_block_data ebb_data; |
6721 | basic_block bb; | |
8b1c6fd7 | 6722 | int *rc_order = XNEWVEC (int, last_basic_block_for_fn (cfun)); |
932ad4d9 | 6723 | int i, n_blocks; |
7afe21cc | 6724 | |
afb72432 IE |
6725 | /* CSE doesn't use dominane info but can invalidate it in different ways. |
6726 | For simplicity free dominance info here. */ | |
6727 | free_dominance_info (CDI_DOMINATORS); | |
6728 | ||
6fb5fa3c | 6729 | df_set_flags (DF_LR_RUN_DCE); |
dca3da7a | 6730 | df_note_add_problem (); |
6fb5fa3c DB |
6731 | df_analyze (); |
6732 | df_set_flags (DF_DEFER_INSN_RESCAN); | |
6733 | ||
6734 | reg_scan (get_insns (), max_reg_num ()); | |
bc5e3b54 KH |
6735 | init_cse_reg_info (nregs); |
6736 | ||
932ad4d9 | 6737 | ebb_data.path = XNEWVEC (struct branch_path, |
028d4092 | 6738 | param_max_cse_path_length); |
9bf8cfbf | 6739 | |
2aac3a01 EB |
6740 | cse_cfg_altered = false; |
6741 | cse_jumps_altered = false; | |
6742 | recorded_label_ref = false; | |
7afe21cc | 6743 | constant_pool_entries_cost = 0; |
dd0ba281 | 6744 | constant_pool_entries_regcost = 0; |
932ad4d9 SB |
6745 | ebb_data.path_size = 0; |
6746 | ebb_data.nsets = 0; | |
2f93eea8 | 6747 | rtl_hooks = cse_rtl_hooks; |
7afe21cc RK |
6748 | |
6749 | init_recog (); | |
9ae8ffe7 | 6750 | init_alias_analysis (); |
7afe21cc | 6751 | |
5ed6ace5 | 6752 | reg_eqv_table = XNEWVEC (struct reg_eqv_elem, nregs); |
7afe21cc | 6753 | |
932ad4d9 | 6754 | /* Set up the table of already visited basic blocks. */ |
8b1c6fd7 | 6755 | cse_visited_basic_blocks = sbitmap_alloc (last_basic_block_for_fn (cfun)); |
f61e445a | 6756 | bitmap_clear (cse_visited_basic_blocks); |
7afe21cc | 6757 | |
a7582f7c | 6758 | /* Loop over basic blocks in reverse completion order (RPO), |
932ad4d9 | 6759 | excluding the ENTRY and EXIT blocks. */ |
27511c65 | 6760 | n_blocks = pre_and_rev_post_order_compute (NULL, rc_order, false); |
932ad4d9 SB |
6761 | i = 0; |
6762 | while (i < n_blocks) | |
7afe21cc | 6763 | { |
a7582f7c | 6764 | /* Find the first block in the RPO queue that we have not yet |
932ad4d9 SB |
6765 | processed before. */ |
6766 | do | |
e9a25f70 | 6767 | { |
06e28de2 | 6768 | bb = BASIC_BLOCK_FOR_FN (cfun, rc_order[i++]); |
e9a25f70 | 6769 | } |
d7c028c0 | 6770 | while (bitmap_bit_p (cse_visited_basic_blocks, bb->index) |
932ad4d9 | 6771 | && i < n_blocks); |
7afe21cc | 6772 | |
932ad4d9 SB |
6773 | /* Find all paths starting with BB, and process them. */ |
6774 | while (cse_find_path (bb, &ebb_data, flag_cse_follow_jumps)) | |
7afe21cc | 6775 | { |
932ad4d9 SB |
6776 | /* Pre-scan the path. */ |
6777 | cse_prescan_path (&ebb_data); | |
7afe21cc | 6778 | |
932ad4d9 SB |
6779 | /* If this basic block has no sets, skip it. */ |
6780 | if (ebb_data.nsets == 0) | |
6781 | continue; | |
7afe21cc | 6782 | |
2e226e66 | 6783 | /* Get a reasonable estimate for the maximum number of qty's |
932ad4d9 SB |
6784 | needed for this path. For this, we take the number of sets |
6785 | and multiply that by MAX_RECOG_OPERANDS. */ | |
6786 | max_qty = ebb_data.nsets * MAX_RECOG_OPERANDS; | |
7afe21cc | 6787 | |
932ad4d9 SB |
6788 | /* Dump the path we're about to process. */ |
6789 | if (dump_file) | |
6790 | cse_dump_path (&ebb_data, ebb_data.nsets, dump_file); | |
6a5293dc | 6791 | |
932ad4d9 | 6792 | cse_extended_basic_block (&ebb_data); |
7afe21cc | 6793 | } |
7afe21cc RK |
6794 | } |
6795 | ||
932ad4d9 SB |
6796 | /* Clean up. */ |
6797 | end_alias_analysis (); | |
932ad4d9 SB |
6798 | free (reg_eqv_table); |
6799 | free (ebb_data.path); | |
6800 | sbitmap_free (cse_visited_basic_blocks); | |
27511c65 | 6801 | free (rc_order); |
932ad4d9 | 6802 | rtl_hooks = general_rtl_hooks; |
75c6bd46 | 6803 | |
2aac3a01 EB |
6804 | if (cse_jumps_altered || recorded_label_ref) |
6805 | return 2; | |
6806 | else if (cse_cfg_altered) | |
6807 | return 1; | |
6808 | else | |
6809 | return 0; | |
7afe21cc RK |
6810 | } |
6811 | \f | |
6812 | /* Count the number of times registers are used (not set) in X. | |
6813 | COUNTS is an array in which we accumulate the count, INCR is how much | |
b92ba6ff R |
6814 | we count each register usage. |
6815 | ||
6816 | Don't count a usage of DEST, which is the SET_DEST of a SET which | |
6817 | contains X in its SET_SRC. This is because such a SET does not | |
6818 | modify the liveness of DEST. | |
34161e98 RS |
6819 | DEST is set to pc_rtx for a trapping insn, or for an insn with side effects. |
6820 | We must then count uses of a SET_DEST regardless, because the insn can't be | |
6821 | deleted here. */ | |
7afe21cc RK |
6822 | |
6823 | static void | |
b92ba6ff | 6824 | count_reg_usage (rtx x, int *counts, rtx dest, int incr) |
7afe21cc | 6825 | { |
f1e7c95f | 6826 | enum rtx_code code; |
b17d5d7c | 6827 | rtx note; |
6f7d635c | 6828 | const char *fmt; |
7afe21cc RK |
6829 | int i, j; |
6830 | ||
f1e7c95f RK |
6831 | if (x == 0) |
6832 | return; | |
6833 | ||
6834 | switch (code = GET_CODE (x)) | |
7afe21cc RK |
6835 | { |
6836 | case REG: | |
b92ba6ff R |
6837 | if (x != dest) |
6838 | counts[REGNO (x)] += incr; | |
7afe21cc RK |
6839 | return; |
6840 | ||
6841 | case PC: | |
6842 | case CC0: | |
6843 | case CONST: | |
d8116890 | 6844 | CASE_CONST_ANY: |
7afe21cc RK |
6845 | case SYMBOL_REF: |
6846 | case LABEL_REF: | |
02e39abc JL |
6847 | return; |
6848 | ||
278a83b2 | 6849 | case CLOBBER: |
02e39abc JL |
6850 | /* If we are clobbering a MEM, mark any registers inside the address |
6851 | as being used. */ | |
3c0cb5de | 6852 | if (MEM_P (XEXP (x, 0))) |
b92ba6ff | 6853 | count_reg_usage (XEXP (XEXP (x, 0), 0), counts, NULL_RTX, incr); |
7afe21cc RK |
6854 | return; |
6855 | ||
6856 | case SET: | |
6857 | /* Unless we are setting a REG, count everything in SET_DEST. */ | |
f8cfc6aa | 6858 | if (!REG_P (SET_DEST (x))) |
b92ba6ff R |
6859 | count_reg_usage (SET_DEST (x), counts, NULL_RTX, incr); |
6860 | count_reg_usage (SET_SRC (x), counts, | |
6861 | dest ? dest : SET_DEST (x), | |
6862 | incr); | |
7afe21cc RK |
6863 | return; |
6864 | ||
b5b8b0ac AO |
6865 | case DEBUG_INSN: |
6866 | return; | |
6867 | ||
f1e7c95f | 6868 | case CALL_INSN: |
7afe21cc RK |
6869 | case INSN: |
6870 | case JUMP_INSN: | |
2da02156 | 6871 | /* We expect dest to be NULL_RTX here. If the insn may throw, |
34161e98 RS |
6872 | or if it cannot be deleted due to side-effects, mark this fact |
6873 | by setting DEST to pc_rtx. */ | |
2da02156 EB |
6874 | if ((!cfun->can_delete_dead_exceptions && !insn_nothrow_p (x)) |
6875 | || side_effects_p (PATTERN (x))) | |
b92ba6ff R |
6876 | dest = pc_rtx; |
6877 | if (code == CALL_INSN) | |
6878 | count_reg_usage (CALL_INSN_FUNCTION_USAGE (x), counts, dest, incr); | |
6879 | count_reg_usage (PATTERN (x), counts, dest, incr); | |
7afe21cc RK |
6880 | |
6881 | /* Things used in a REG_EQUAL note aren't dead since loop may try to | |
6882 | use them. */ | |
6883 | ||
b17d5d7c ZD |
6884 | note = find_reg_equal_equiv_note (x); |
6885 | if (note) | |
839844be R |
6886 | { |
6887 | rtx eqv = XEXP (note, 0); | |
6888 | ||
6889 | if (GET_CODE (eqv) == EXPR_LIST) | |
6890 | /* This REG_EQUAL note describes the result of a function call. | |
6891 | Process all the arguments. */ | |
6892 | do | |
6893 | { | |
b92ba6ff | 6894 | count_reg_usage (XEXP (eqv, 0), counts, dest, incr); |
839844be R |
6895 | eqv = XEXP (eqv, 1); |
6896 | } | |
6897 | while (eqv && GET_CODE (eqv) == EXPR_LIST); | |
6898 | else | |
b92ba6ff | 6899 | count_reg_usage (eqv, counts, dest, incr); |
839844be | 6900 | } |
7afe21cc RK |
6901 | return; |
6902 | ||
ee960939 OH |
6903 | case EXPR_LIST: |
6904 | if (REG_NOTE_KIND (x) == REG_EQUAL | |
6905 | || (REG_NOTE_KIND (x) != REG_NONNEG && GET_CODE (XEXP (x,0)) == USE) | |
6906 | /* FUNCTION_USAGE expression lists may include (CLOBBER (mem /u)), | |
6907 | involving registers in the address. */ | |
17d184e5 | 6908 | || GET_CODE (XEXP (x, 0)) == CLOBBER) |
b92ba6ff | 6909 | count_reg_usage (XEXP (x, 0), counts, NULL_RTX, incr); |
ee960939 | 6910 | |
b92ba6ff | 6911 | count_reg_usage (XEXP (x, 1), counts, NULL_RTX, incr); |
ee960939 OH |
6912 | return; |
6913 | ||
a6c14a64 | 6914 | case ASM_OPERANDS: |
a6c14a64 RH |
6915 | /* Iterate over just the inputs, not the constraints as well. */ |
6916 | for (i = ASM_OPERANDS_INPUT_LENGTH (x) - 1; i >= 0; i--) | |
b92ba6ff | 6917 | count_reg_usage (ASM_OPERANDS_INPUT (x, i), counts, dest, incr); |
a6c14a64 RH |
6918 | return; |
6919 | ||
7afe21cc | 6920 | case INSN_LIST: |
f91aec98 | 6921 | case INT_LIST: |
341c100f | 6922 | gcc_unreachable (); |
278a83b2 | 6923 | |
e9a25f70 JL |
6924 | default: |
6925 | break; | |
7afe21cc RK |
6926 | } |
6927 | ||
6928 | fmt = GET_RTX_FORMAT (code); | |
6929 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
6930 | { | |
6931 | if (fmt[i] == 'e') | |
b92ba6ff | 6932 | count_reg_usage (XEXP (x, i), counts, dest, incr); |
7afe21cc RK |
6933 | else if (fmt[i] == 'E') |
6934 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
b92ba6ff | 6935 | count_reg_usage (XVECEXP (x, i, j), counts, dest, incr); |
7afe21cc RK |
6936 | } |
6937 | } | |
6938 | \f | |
6699b754 | 6939 | /* Return true if X is a dead register. */ |
b5b8b0ac | 6940 | |
6699b754 | 6941 | static inline int |
a5b9bc17 | 6942 | is_dead_reg (const_rtx x, int *counts) |
b5b8b0ac | 6943 | { |
b5b8b0ac AO |
6944 | return (REG_P (x) |
6945 | && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
6946 | && counts[REGNO (x)] == 0); | |
6947 | } | |
6948 | ||
4793dca1 JH |
6949 | /* Return true if set is live. */ |
6950 | static bool | |
20468884 | 6951 | set_live_p (rtx set, rtx_insn *insn ATTRIBUTE_UNUSED, /* Only used with HAVE_cc0. */ |
7080f735 | 6952 | int *counts) |
4793dca1 | 6953 | { |
e67d1102 | 6954 | rtx_insn *tem; |
4793dca1 JH |
6955 | |
6956 | if (set_noop_p (set)) | |
6957 | ; | |
6958 | ||
4793dca1 JH |
6959 | else if (GET_CODE (SET_DEST (set)) == CC0 |
6960 | && !side_effects_p (SET_SRC (set)) | |
5f262d13 | 6961 | && ((tem = next_nonnote_nondebug_insn (insn)) == NULL_RTX |
4793dca1 JH |
6962 | || !INSN_P (tem) |
6963 | || !reg_referenced_p (cc0_rtx, PATTERN (tem)))) | |
6964 | return false; | |
6699b754 | 6965 | else if (!is_dead_reg (SET_DEST (set), counts) |
8fff4fc1 | 6966 | || side_effects_p (SET_SRC (set))) |
4793dca1 JH |
6967 | return true; |
6968 | return false; | |
6969 | } | |
6970 | ||
6971 | /* Return true if insn is live. */ | |
6972 | ||
6973 | static bool | |
20468884 | 6974 | insn_live_p (rtx_insn *insn, int *counts) |
4793dca1 JH |
6975 | { |
6976 | int i; | |
2da02156 | 6977 | if (!cfun->can_delete_dead_exceptions && !insn_nothrow_p (insn)) |
a646f6cc AH |
6978 | return true; |
6979 | else if (GET_CODE (PATTERN (insn)) == SET) | |
0021de69 | 6980 | return set_live_p (PATTERN (insn), insn, counts); |
4793dca1 | 6981 | else if (GET_CODE (PATTERN (insn)) == PARALLEL) |
0021de69 DB |
6982 | { |
6983 | for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) | |
6984 | { | |
6985 | rtx elt = XVECEXP (PATTERN (insn), 0, i); | |
4793dca1 | 6986 | |
0021de69 DB |
6987 | if (GET_CODE (elt) == SET) |
6988 | { | |
6989 | if (set_live_p (elt, insn, counts)) | |
6990 | return true; | |
6991 | } | |
17d184e5 | 6992 | else if (GET_CODE (elt) != CLOBBER && GET_CODE (elt) != USE) |
0021de69 DB |
6993 | return true; |
6994 | } | |
6995 | return false; | |
6996 | } | |
b5b8b0ac AO |
6997 | else if (DEBUG_INSN_P (insn)) |
6998 | { | |
20468884 | 6999 | rtx_insn *next; |
b5b8b0ac | 7000 | |
96a95ac1 AO |
7001 | if (DEBUG_MARKER_INSN_P (insn)) |
7002 | return true; | |
7003 | ||
b5b8b0ac AO |
7004 | for (next = NEXT_INSN (insn); next; next = NEXT_INSN (next)) |
7005 | if (NOTE_P (next)) | |
7006 | continue; | |
7007 | else if (!DEBUG_INSN_P (next)) | |
7008 | return true; | |
96a95ac1 AO |
7009 | /* If we find an inspection point, such as a debug begin stmt, |
7010 | we want to keep the earlier debug insn. */ | |
7011 | else if (DEBUG_MARKER_INSN_P (next)) | |
7012 | return true; | |
b5b8b0ac AO |
7013 | else if (INSN_VAR_LOCATION_DECL (insn) == INSN_VAR_LOCATION_DECL (next)) |
7014 | return false; | |
7015 | ||
b5b8b0ac AO |
7016 | return true; |
7017 | } | |
4793dca1 JH |
7018 | else |
7019 | return true; | |
7020 | } | |
7021 | ||
6699b754 JJ |
7022 | /* Count the number of stores into pseudo. Callback for note_stores. */ |
7023 | ||
7024 | static void | |
7025 | count_stores (rtx x, const_rtx set ATTRIBUTE_UNUSED, void *data) | |
7026 | { | |
7027 | int *counts = (int *) data; | |
7028 | if (REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER) | |
7029 | counts[REGNO (x)]++; | |
7030 | } | |
7031 | ||
a5b9bc17 RS |
7032 | /* Return if DEBUG_INSN pattern PAT needs to be reset because some dead |
7033 | pseudo doesn't have a replacement. COUNTS[X] is zero if register X | |
7034 | is dead and REPLACEMENTS[X] is null if it has no replacemenet. | |
7035 | Set *SEEN_REPL to true if we see a dead register that does have | |
7036 | a replacement. */ | |
6699b754 | 7037 | |
a5b9bc17 RS |
7038 | static bool |
7039 | is_dead_debug_insn (const_rtx pat, int *counts, rtx *replacements, | |
7040 | bool *seen_repl) | |
6699b754 | 7041 | { |
a5b9bc17 RS |
7042 | subrtx_iterator::array_type array; |
7043 | FOR_EACH_SUBRTX (iter, array, pat, NONCONST) | |
6699b754 | 7044 | { |
a5b9bc17 RS |
7045 | const_rtx x = *iter; |
7046 | if (is_dead_reg (x, counts)) | |
7047 | { | |
7048 | if (replacements && replacements[REGNO (x)] != NULL_RTX) | |
7049 | *seen_repl = true; | |
7050 | else | |
7051 | return true; | |
7052 | } | |
6699b754 | 7053 | } |
a5b9bc17 | 7054 | return false; |
6699b754 JJ |
7055 | } |
7056 | ||
7057 | /* Replace a dead pseudo in a DEBUG_INSN with replacement DEBUG_EXPR. | |
7058 | Callback for simplify_replace_fn_rtx. */ | |
7059 | ||
7060 | static rtx | |
7061 | replace_dead_reg (rtx x, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data) | |
7062 | { | |
7063 | rtx *replacements = (rtx *) data; | |
7064 | ||
7065 | if (REG_P (x) | |
7066 | && REGNO (x) >= FIRST_PSEUDO_REGISTER | |
7067 | && replacements[REGNO (x)] != NULL_RTX) | |
7068 | { | |
7069 | if (GET_MODE (x) == GET_MODE (replacements[REGNO (x)])) | |
7070 | return replacements[REGNO (x)]; | |
7071 | return lowpart_subreg (GET_MODE (x), replacements[REGNO (x)], | |
7072 | GET_MODE (replacements[REGNO (x)])); | |
7073 | } | |
7074 | return NULL_RTX; | |
7075 | } | |
7076 | ||
7afe21cc RK |
7077 | /* Scan all the insns and delete any that are dead; i.e., they store a register |
7078 | that is never used or they copy a register to itself. | |
7079 | ||
c6a26dc4 JL |
7080 | This is used to remove insns made obviously dead by cse, loop or other |
7081 | optimizations. It improves the heuristics in loop since it won't try to | |
7082 | move dead invariants out of loops or make givs for dead quantities. The | |
7083 | remaining passes of the compilation are also sped up. */ | |
7afe21cc | 7084 | |
3dec4024 | 7085 | int |
169d13f5 | 7086 | delete_trivially_dead_insns (rtx_insn *insns, int nreg) |
7afe21cc | 7087 | { |
4da896b2 | 7088 | int *counts; |
169d13f5 | 7089 | rtx_insn *insn, *prev; |
6699b754 | 7090 | rtx *replacements = NULL; |
65e9fa10 | 7091 | int ndead = 0; |
7afe21cc | 7092 | |
3dec4024 | 7093 | timevar_push (TV_DELETE_TRIVIALLY_DEAD); |
7afe21cc | 7094 | /* First count the number of times each register is used. */ |
36f52e8f | 7095 | if (MAY_HAVE_DEBUG_BIND_INSNS) |
6699b754 JJ |
7096 | { |
7097 | counts = XCNEWVEC (int, nreg * 3); | |
7098 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
36f52e8f | 7099 | if (DEBUG_BIND_INSN_P (insn)) |
6699b754 JJ |
7100 | count_reg_usage (INSN_VAR_LOCATION_LOC (insn), counts + nreg, |
7101 | NULL_RTX, 1); | |
7102 | else if (INSN_P (insn)) | |
7103 | { | |
7104 | count_reg_usage (insn, counts, NULL_RTX, 1); | |
e8448ba5 | 7105 | note_stores (insn, count_stores, counts + nreg * 2); |
6699b754 JJ |
7106 | } |
7107 | /* If there can be debug insns, COUNTS are 3 consecutive arrays. | |
7108 | First one counts how many times each pseudo is used outside | |
7109 | of debug insns, second counts how many times each pseudo is | |
7110 | used in debug insns and third counts how many times a pseudo | |
7111 | is stored. */ | |
7112 | } | |
7113 | else | |
7114 | { | |
7115 | counts = XCNEWVEC (int, nreg); | |
7116 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
7117 | if (INSN_P (insn)) | |
7118 | count_reg_usage (insn, counts, NULL_RTX, 1); | |
7119 | /* If no debug insns can be present, COUNTS is just an array | |
7120 | which counts how many times each pseudo is used. */ | |
7121 | } | |
56873e13 ES |
7122 | /* Pseudo PIC register should be considered as used due to possible |
7123 | new usages generated. */ | |
7124 | if (!reload_completed | |
7125 | && pic_offset_table_rtx | |
7126 | && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) | |
7127 | counts[REGNO (pic_offset_table_rtx)]++; | |
65e9fa10 KH |
7128 | /* Go from the last insn to the first and delete insns that only set unused |
7129 | registers or copy a register to itself. As we delete an insn, remove | |
7130 | usage counts for registers it uses. | |
0cedb36c | 7131 | |
65e9fa10 KH |
7132 | The first jump optimization pass may leave a real insn as the last |
7133 | insn in the function. We must not skip that insn or we may end | |
6699b754 JJ |
7134 | up deleting code that is not really dead. |
7135 | ||
7136 | If some otherwise unused register is only used in DEBUG_INSNs, | |
7137 | try to create a DEBUG_EXPR temporary and emit a DEBUG_INSN before | |
7138 | the setter. Then go through DEBUG_INSNs and if a DEBUG_EXPR | |
7139 | has been created for the unused register, replace it with | |
7140 | the DEBUG_EXPR, otherwise reset the DEBUG_INSN. */ | |
03ce14db | 7141 | for (insn = get_last_insn (); insn; insn = prev) |
65e9fa10 KH |
7142 | { |
7143 | int live_insn = 0; | |
7afe21cc | 7144 | |
03ce14db KH |
7145 | prev = PREV_INSN (insn); |
7146 | if (!INSN_P (insn)) | |
7147 | continue; | |
7afe21cc | 7148 | |
4a8cae83 | 7149 | live_insn = insn_live_p (insn, counts); |
7afe21cc | 7150 | |
65e9fa10 KH |
7151 | /* If this is a dead insn, delete it and show registers in it aren't |
7152 | being used. */ | |
7afe21cc | 7153 | |
6fb5fa3c | 7154 | if (! live_insn && dbg_cnt (delete_trivial_dead)) |
65e9fa10 | 7155 | { |
6699b754 | 7156 | if (DEBUG_INSN_P (insn)) |
36f52e8f AO |
7157 | { |
7158 | if (DEBUG_BIND_INSN_P (insn)) | |
7159 | count_reg_usage (INSN_VAR_LOCATION_LOC (insn), counts + nreg, | |
7160 | NULL_RTX, -1); | |
7161 | } | |
6699b754 JJ |
7162 | else |
7163 | { | |
7164 | rtx set; | |
36f52e8f | 7165 | if (MAY_HAVE_DEBUG_BIND_INSNS |
6699b754 JJ |
7166 | && (set = single_set (insn)) != NULL_RTX |
7167 | && is_dead_reg (SET_DEST (set), counts) | |
7168 | /* Used at least once in some DEBUG_INSN. */ | |
7169 | && counts[REGNO (SET_DEST (set)) + nreg] > 0 | |
7170 | /* And set exactly once. */ | |
7171 | && counts[REGNO (SET_DEST (set)) + nreg * 2] == 1 | |
7172 | && !side_effects_p (SET_SRC (set)) | |
7173 | && asm_noperands (PATTERN (insn)) < 0) | |
7174 | { | |
b2908ba6 DM |
7175 | rtx dval, bind_var_loc; |
7176 | rtx_insn *bind; | |
6699b754 JJ |
7177 | |
7178 | /* Create DEBUG_EXPR (and DEBUG_EXPR_DECL). */ | |
7179 | dval = make_debug_expr_from_rtl (SET_DEST (set)); | |
7180 | ||
7181 | /* Emit a debug bind insn before the insn in which | |
7182 | reg dies. */ | |
b2908ba6 DM |
7183 | bind_var_loc = |
7184 | gen_rtx_VAR_LOCATION (GET_MODE (SET_DEST (set)), | |
7185 | DEBUG_EXPR_TREE_DECL (dval), | |
7186 | SET_SRC (set), | |
7187 | VAR_INIT_STATUS_INITIALIZED); | |
7188 | count_reg_usage (bind_var_loc, counts + nreg, NULL_RTX, 1); | |
7189 | ||
7190 | bind = emit_debug_insn_before (bind_var_loc, insn); | |
6699b754 JJ |
7191 | df_insn_rescan (bind); |
7192 | ||
7193 | if (replacements == NULL) | |
7194 | replacements = XCNEWVEC (rtx, nreg); | |
7195 | replacements[REGNO (SET_DEST (set))] = dval; | |
7196 | } | |
7197 | ||
7198 | count_reg_usage (insn, counts, NULL_RTX, -1); | |
7199 | ndead++; | |
7200 | } | |
98ccd1d7 | 7201 | cse_cfg_altered |= delete_insn_and_edges (insn); |
65e9fa10 | 7202 | } |
68252e27 | 7203 | } |
4da896b2 | 7204 | |
36f52e8f | 7205 | if (MAY_HAVE_DEBUG_BIND_INSNS) |
6699b754 | 7206 | { |
6699b754 | 7207 | for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) |
36f52e8f | 7208 | if (DEBUG_BIND_INSN_P (insn)) |
6699b754 JJ |
7209 | { |
7210 | /* If this debug insn references a dead register that wasn't replaced | |
7211 | with an DEBUG_EXPR, reset the DEBUG_INSN. */ | |
a5b9bc17 RS |
7212 | bool seen_repl = false; |
7213 | if (is_dead_debug_insn (INSN_VAR_LOCATION_LOC (insn), | |
7214 | counts, replacements, &seen_repl)) | |
6699b754 JJ |
7215 | { |
7216 | INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC (); | |
7217 | df_insn_rescan (insn); | |
7218 | } | |
a5b9bc17 | 7219 | else if (seen_repl) |
6699b754 JJ |
7220 | { |
7221 | INSN_VAR_LOCATION_LOC (insn) | |
7222 | = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn), | |
7223 | NULL_RTX, replace_dead_reg, | |
7224 | replacements); | |
7225 | df_insn_rescan (insn); | |
7226 | } | |
7227 | } | |
04695783 | 7228 | free (replacements); |
6699b754 JJ |
7229 | } |
7230 | ||
c263766c | 7231 | if (dump_file && ndead) |
65e9fa10 KH |
7232 | fprintf (dump_file, "Deleted %i trivially dead insns\n", |
7233 | ndead); | |
4da896b2 MM |
7234 | /* Clean up. */ |
7235 | free (counts); | |
3dec4024 JH |
7236 | timevar_pop (TV_DELETE_TRIVIALLY_DEAD); |
7237 | return ndead; | |
7afe21cc | 7238 | } |
e129d93a | 7239 | |
a9052a40 RS |
7240 | /* If LOC contains references to NEWREG in a different mode, change them |
7241 | to use NEWREG instead. */ | |
e129d93a | 7242 | |
a9052a40 RS |
7243 | static void |
7244 | cse_change_cc_mode (subrtx_ptr_iterator::array_type &array, | |
88bdcd3d | 7245 | rtx *loc, rtx_insn *insn, rtx newreg) |
e129d93a | 7246 | { |
a9052a40 | 7247 | FOR_EACH_SUBRTX_PTR (iter, array, loc, NONCONST) |
e129d93a | 7248 | { |
a9052a40 RS |
7249 | rtx *loc = *iter; |
7250 | rtx x = *loc; | |
7251 | if (x | |
7252 | && REG_P (x) | |
7253 | && REGNO (x) == REGNO (newreg) | |
7254 | && GET_MODE (x) != GET_MODE (newreg)) | |
7255 | { | |
7256 | validate_change (insn, loc, newreg, 1); | |
7257 | iter.skip_subrtxes (); | |
7258 | } | |
e129d93a | 7259 | } |
e129d93a ILT |
7260 | } |
7261 | ||
fc188d37 AK |
7262 | /* Change the mode of any reference to the register REGNO (NEWREG) to |
7263 | GET_MODE (NEWREG) in INSN. */ | |
7264 | ||
7265 | static void | |
20468884 | 7266 | cse_change_cc_mode_insn (rtx_insn *insn, rtx newreg) |
fc188d37 | 7267 | { |
fc188d37 AK |
7268 | int success; |
7269 | ||
7270 | if (!INSN_P (insn)) | |
7271 | return; | |
7272 | ||
a9052a40 RS |
7273 | subrtx_ptr_iterator::array_type array; |
7274 | cse_change_cc_mode (array, &PATTERN (insn), insn, newreg); | |
7275 | cse_change_cc_mode (array, ®_NOTES (insn), insn, newreg); | |
b8698a0f | 7276 | |
fc188d37 AK |
7277 | /* If the following assertion was triggered, there is most probably |
7278 | something wrong with the cc_modes_compatible back end function. | |
7279 | CC modes only can be considered compatible if the insn - with the mode | |
7280 | replaced by any of the compatible modes - can still be recognized. */ | |
7281 | success = apply_change_group (); | |
7282 | gcc_assert (success); | |
7283 | } | |
7284 | ||
e129d93a ILT |
7285 | /* Change the mode of any reference to the register REGNO (NEWREG) to |
7286 | GET_MODE (NEWREG), starting at START. Stop before END. Stop at | |
2e802a6f | 7287 | any instruction which modifies NEWREG. */ |
e129d93a ILT |
7288 | |
7289 | static void | |
20468884 | 7290 | cse_change_cc_mode_insns (rtx_insn *start, rtx_insn *end, rtx newreg) |
e129d93a | 7291 | { |
20468884 | 7292 | rtx_insn *insn; |
e129d93a ILT |
7293 | |
7294 | for (insn = start; insn != end; insn = NEXT_INSN (insn)) | |
7295 | { | |
7296 | if (! INSN_P (insn)) | |
7297 | continue; | |
7298 | ||
2e802a6f | 7299 | if (reg_set_p (newreg, insn)) |
e129d93a ILT |
7300 | return; |
7301 | ||
fc188d37 | 7302 | cse_change_cc_mode_insn (insn, newreg); |
e129d93a ILT |
7303 | } |
7304 | } | |
7305 | ||
7306 | /* BB is a basic block which finishes with CC_REG as a condition code | |
7307 | register which is set to CC_SRC. Look through the successors of BB | |
7308 | to find blocks which have a single predecessor (i.e., this one), | |
7309 | and look through those blocks for an assignment to CC_REG which is | |
7310 | equivalent to CC_SRC. CAN_CHANGE_MODE indicates whether we are | |
7311 | permitted to change the mode of CC_SRC to a compatible mode. This | |
7312 | returns VOIDmode if no equivalent assignments were found. | |
7313 | Otherwise it returns the mode which CC_SRC should wind up with. | |
31e9ebaf JJ |
7314 | ORIG_BB should be the same as BB in the outermost cse_cc_succs call, |
7315 | but is passed unmodified down to recursive calls in order to prevent | |
7316 | endless recursion. | |
e129d93a ILT |
7317 | |
7318 | The main complexity in this function is handling the mode issues. | |
7319 | We may have more than one duplicate which we can eliminate, and we | |
7320 | try to find a mode which will work for multiple duplicates. */ | |
7321 | ||
ef4bddc2 | 7322 | static machine_mode |
31e9ebaf JJ |
7323 | cse_cc_succs (basic_block bb, basic_block orig_bb, rtx cc_reg, rtx cc_src, |
7324 | bool can_change_mode) | |
e129d93a ILT |
7325 | { |
7326 | bool found_equiv; | |
ef4bddc2 | 7327 | machine_mode mode; |
e129d93a ILT |
7328 | unsigned int insn_count; |
7329 | edge e; | |
20468884 | 7330 | rtx_insn *insns[2]; |
ef4bddc2 | 7331 | machine_mode modes[2]; |
20468884 | 7332 | rtx_insn *last_insns[2]; |
e129d93a ILT |
7333 | unsigned int i; |
7334 | rtx newreg; | |
628f6a4e | 7335 | edge_iterator ei; |
e129d93a ILT |
7336 | |
7337 | /* We expect to have two successors. Look at both before picking | |
7338 | the final mode for the comparison. If we have more successors | |
7339 | (i.e., some sort of table jump, although that seems unlikely), | |
7340 | then we require all beyond the first two to use the same | |
7341 | mode. */ | |
7342 | ||
7343 | found_equiv = false; | |
7344 | mode = GET_MODE (cc_src); | |
7345 | insn_count = 0; | |
628f6a4e | 7346 | FOR_EACH_EDGE (e, ei, bb->succs) |
e129d93a | 7347 | { |
20468884 DM |
7348 | rtx_insn *insn; |
7349 | rtx_insn *end; | |
e129d93a ILT |
7350 | |
7351 | if (e->flags & EDGE_COMPLEX) | |
7352 | continue; | |
7353 | ||
628f6a4e | 7354 | if (EDGE_COUNT (e->dest->preds) != 1 |
fefa31b5 | 7355 | || e->dest == EXIT_BLOCK_PTR_FOR_FN (cfun) |
31e9ebaf JJ |
7356 | /* Avoid endless recursion on unreachable blocks. */ |
7357 | || e->dest == orig_bb) | |
e129d93a ILT |
7358 | continue; |
7359 | ||
7360 | end = NEXT_INSN (BB_END (e->dest)); | |
7361 | for (insn = BB_HEAD (e->dest); insn != end; insn = NEXT_INSN (insn)) | |
7362 | { | |
7363 | rtx set; | |
7364 | ||
7365 | if (! INSN_P (insn)) | |
7366 | continue; | |
7367 | ||
7368 | /* If CC_SRC is modified, we have to stop looking for | |
7369 | something which uses it. */ | |
7370 | if (modified_in_p (cc_src, insn)) | |
7371 | break; | |
7372 | ||
7373 | /* Check whether INSN sets CC_REG to CC_SRC. */ | |
7374 | set = single_set (insn); | |
7375 | if (set | |
f8cfc6aa | 7376 | && REG_P (SET_DEST (set)) |
e129d93a ILT |
7377 | && REGNO (SET_DEST (set)) == REGNO (cc_reg)) |
7378 | { | |
7379 | bool found; | |
ef4bddc2 RS |
7380 | machine_mode set_mode; |
7381 | machine_mode comp_mode; | |
e129d93a ILT |
7382 | |
7383 | found = false; | |
7384 | set_mode = GET_MODE (SET_SRC (set)); | |
7385 | comp_mode = set_mode; | |
7386 | if (rtx_equal_p (cc_src, SET_SRC (set))) | |
7387 | found = true; | |
7388 | else if (GET_CODE (cc_src) == COMPARE | |
7389 | && GET_CODE (SET_SRC (set)) == COMPARE | |
1f44254c | 7390 | && mode != set_mode |
e129d93a ILT |
7391 | && rtx_equal_p (XEXP (cc_src, 0), |
7392 | XEXP (SET_SRC (set), 0)) | |
7393 | && rtx_equal_p (XEXP (cc_src, 1), | |
7394 | XEXP (SET_SRC (set), 1))) | |
b8698a0f | 7395 | |
e129d93a | 7396 | { |
5fd9b178 | 7397 | comp_mode = targetm.cc_modes_compatible (mode, set_mode); |
e129d93a ILT |
7398 | if (comp_mode != VOIDmode |
7399 | && (can_change_mode || comp_mode == mode)) | |
7400 | found = true; | |
7401 | } | |
7402 | ||
7403 | if (found) | |
7404 | { | |
7405 | found_equiv = true; | |
1f44254c | 7406 | if (insn_count < ARRAY_SIZE (insns)) |
e129d93a ILT |
7407 | { |
7408 | insns[insn_count] = insn; | |
7409 | modes[insn_count] = set_mode; | |
7410 | last_insns[insn_count] = end; | |
7411 | ++insn_count; | |
7412 | ||
1f44254c ILT |
7413 | if (mode != comp_mode) |
7414 | { | |
341c100f | 7415 | gcc_assert (can_change_mode); |
1f44254c | 7416 | mode = comp_mode; |
fc188d37 AK |
7417 | |
7418 | /* The modified insn will be re-recognized later. */ | |
1f44254c ILT |
7419 | PUT_MODE (cc_src, mode); |
7420 | } | |
e129d93a ILT |
7421 | } |
7422 | else | |
7423 | { | |
7424 | if (set_mode != mode) | |
1f44254c ILT |
7425 | { |
7426 | /* We found a matching expression in the | |
7427 | wrong mode, but we don't have room to | |
7428 | store it in the array. Punt. This case | |
7429 | should be rare. */ | |
7430 | break; | |
7431 | } | |
e129d93a ILT |
7432 | /* INSN sets CC_REG to a value equal to CC_SRC |
7433 | with the right mode. We can simply delete | |
7434 | it. */ | |
7435 | delete_insn (insn); | |
7436 | } | |
7437 | ||
7438 | /* We found an instruction to delete. Keep looking, | |
7439 | in the hopes of finding a three-way jump. */ | |
7440 | continue; | |
7441 | } | |
7442 | ||
7443 | /* We found an instruction which sets the condition | |
7444 | code, so don't look any farther. */ | |
7445 | break; | |
7446 | } | |
7447 | ||
7448 | /* If INSN sets CC_REG in some other way, don't look any | |
7449 | farther. */ | |
7450 | if (reg_set_p (cc_reg, insn)) | |
7451 | break; | |
7452 | } | |
7453 | ||
7454 | /* If we fell off the bottom of the block, we can keep looking | |
7455 | through successors. We pass CAN_CHANGE_MODE as false because | |
7456 | we aren't prepared to handle compatibility between the | |
7457 | further blocks and this block. */ | |
7458 | if (insn == end) | |
7459 | { | |
ef4bddc2 | 7460 | machine_mode submode; |
1f44254c | 7461 | |
31e9ebaf | 7462 | submode = cse_cc_succs (e->dest, orig_bb, cc_reg, cc_src, false); |
1f44254c ILT |
7463 | if (submode != VOIDmode) |
7464 | { | |
341c100f | 7465 | gcc_assert (submode == mode); |
1f44254c ILT |
7466 | found_equiv = true; |
7467 | can_change_mode = false; | |
7468 | } | |
e129d93a ILT |
7469 | } |
7470 | } | |
7471 | ||
7472 | if (! found_equiv) | |
7473 | return VOIDmode; | |
7474 | ||
7475 | /* Now INSN_COUNT is the number of instructions we found which set | |
7476 | CC_REG to a value equivalent to CC_SRC. The instructions are in | |
7477 | INSNS. The modes used by those instructions are in MODES. */ | |
7478 | ||
7479 | newreg = NULL_RTX; | |
7480 | for (i = 0; i < insn_count; ++i) | |
7481 | { | |
7482 | if (modes[i] != mode) | |
7483 | { | |
7484 | /* We need to change the mode of CC_REG in INSNS[i] and | |
7485 | subsequent instructions. */ | |
7486 | if (! newreg) | |
7487 | { | |
7488 | if (GET_MODE (cc_reg) == mode) | |
7489 | newreg = cc_reg; | |
7490 | else | |
7491 | newreg = gen_rtx_REG (mode, REGNO (cc_reg)); | |
7492 | } | |
7493 | cse_change_cc_mode_insns (NEXT_INSN (insns[i]), last_insns[i], | |
7494 | newreg); | |
7495 | } | |
7496 | ||
98ccd1d7 | 7497 | cse_cfg_altered |= delete_insn_and_edges (insns[i]); |
e129d93a ILT |
7498 | } |
7499 | ||
7500 | return mode; | |
7501 | } | |
7502 | ||
7503 | /* If we have a fixed condition code register (or two), walk through | |
7504 | the instructions and try to eliminate duplicate assignments. */ | |
7505 | ||
cab2264d | 7506 | static void |
e129d93a ILT |
7507 | cse_condition_code_reg (void) |
7508 | { | |
7509 | unsigned int cc_regno_1; | |
7510 | unsigned int cc_regno_2; | |
7511 | rtx cc_reg_1; | |
7512 | rtx cc_reg_2; | |
7513 | basic_block bb; | |
7514 | ||
5fd9b178 | 7515 | if (! targetm.fixed_condition_code_regs (&cc_regno_1, &cc_regno_2)) |
e129d93a ILT |
7516 | return; |
7517 | ||
7518 | cc_reg_1 = gen_rtx_REG (CCmode, cc_regno_1); | |
7519 | if (cc_regno_2 != INVALID_REGNUM) | |
7520 | cc_reg_2 = gen_rtx_REG (CCmode, cc_regno_2); | |
7521 | else | |
7522 | cc_reg_2 = NULL_RTX; | |
7523 | ||
11cd3bed | 7524 | FOR_EACH_BB_FN (bb, cfun) |
e129d93a | 7525 | { |
20468884 | 7526 | rtx_insn *last_insn; |
e129d93a | 7527 | rtx cc_reg; |
20468884 DM |
7528 | rtx_insn *insn; |
7529 | rtx_insn *cc_src_insn; | |
e129d93a | 7530 | rtx cc_src; |
ef4bddc2 RS |
7531 | machine_mode mode; |
7532 | machine_mode orig_mode; | |
e129d93a ILT |
7533 | |
7534 | /* Look for blocks which end with a conditional jump based on a | |
7535 | condition code register. Then look for the instruction which | |
7536 | sets the condition code register. Then look through the | |
7537 | successor blocks for instructions which set the condition | |
7538 | code register to the same value. There are other possible | |
7539 | uses of the condition code register, but these are by far the | |
7540 | most common and the ones which we are most likely to be able | |
7541 | to optimize. */ | |
7542 | ||
7543 | last_insn = BB_END (bb); | |
4b4bf941 | 7544 | if (!JUMP_P (last_insn)) |
e129d93a ILT |
7545 | continue; |
7546 | ||
7547 | if (reg_referenced_p (cc_reg_1, PATTERN (last_insn))) | |
7548 | cc_reg = cc_reg_1; | |
7549 | else if (cc_reg_2 && reg_referenced_p (cc_reg_2, PATTERN (last_insn))) | |
7550 | cc_reg = cc_reg_2; | |
7551 | else | |
7552 | continue; | |
7553 | ||
20468884 | 7554 | cc_src_insn = NULL; |
e129d93a ILT |
7555 | cc_src = NULL_RTX; |
7556 | for (insn = PREV_INSN (last_insn); | |
7557 | insn && insn != PREV_INSN (BB_HEAD (bb)); | |
7558 | insn = PREV_INSN (insn)) | |
7559 | { | |
7560 | rtx set; | |
7561 | ||
7562 | if (! INSN_P (insn)) | |
7563 | continue; | |
7564 | set = single_set (insn); | |
7565 | if (set | |
f8cfc6aa | 7566 | && REG_P (SET_DEST (set)) |
e129d93a ILT |
7567 | && REGNO (SET_DEST (set)) == REGNO (cc_reg)) |
7568 | { | |
7569 | cc_src_insn = insn; | |
7570 | cc_src = SET_SRC (set); | |
7571 | break; | |
7572 | } | |
7573 | else if (reg_set_p (cc_reg, insn)) | |
7574 | break; | |
7575 | } | |
7576 | ||
7577 | if (! cc_src_insn) | |
7578 | continue; | |
7579 | ||
7580 | if (modified_between_p (cc_src, cc_src_insn, NEXT_INSN (last_insn))) | |
7581 | continue; | |
7582 | ||
7583 | /* Now CC_REG is a condition code register used for a | |
7584 | conditional jump at the end of the block, and CC_SRC, in | |
7585 | CC_SRC_INSN, is the value to which that condition code | |
7586 | register is set, and CC_SRC is still meaningful at the end of | |
7587 | the basic block. */ | |
7588 | ||
1f44254c | 7589 | orig_mode = GET_MODE (cc_src); |
31e9ebaf | 7590 | mode = cse_cc_succs (bb, bb, cc_reg, cc_src, true); |
1f44254c | 7591 | if (mode != VOIDmode) |
e129d93a | 7592 | { |
341c100f | 7593 | gcc_assert (mode == GET_MODE (cc_src)); |
1f44254c | 7594 | if (mode != orig_mode) |
2e802a6f KH |
7595 | { |
7596 | rtx newreg = gen_rtx_REG (mode, REGNO (cc_reg)); | |
7597 | ||
fc188d37 | 7598 | cse_change_cc_mode_insn (cc_src_insn, newreg); |
2e802a6f KH |
7599 | |
7600 | /* Do the same in the following insns that use the | |
7601 | current value of CC_REG within BB. */ | |
7602 | cse_change_cc_mode_insns (NEXT_INSN (cc_src_insn), | |
7603 | NEXT_INSN (last_insn), | |
7604 | newreg); | |
7605 | } | |
e129d93a ILT |
7606 | } |
7607 | } | |
7608 | } | |
ef330312 PB |
7609 | \f |
7610 | ||
7611 | /* Perform common subexpression elimination. Nonzero value from | |
7612 | `cse_main' means that jumps were simplified and some code may now | |
7613 | be unreachable, so do jump optimization again. */ | |
c2924966 | 7614 | static unsigned int |
ef330312 PB |
7615 | rest_of_handle_cse (void) |
7616 | { | |
7617 | int tem; | |
6fb5fa3c | 7618 | |
ef330312 | 7619 | if (dump_file) |
5b4fdb20 | 7620 | dump_flow_info (dump_file, dump_flags); |
ef330312 | 7621 | |
10d22567 | 7622 | tem = cse_main (get_insns (), max_reg_num ()); |
ef330312 PB |
7623 | |
7624 | /* If we are not running more CSE passes, then we are no longer | |
7625 | expecting CSE to be run. But always rerun it in a cheap mode. */ | |
7626 | cse_not_expected = !flag_rerun_cse_after_loop && !flag_gcse; | |
7627 | ||
2aac3a01 EB |
7628 | if (tem == 2) |
7629 | { | |
7630 | timevar_push (TV_JUMP); | |
7631 | rebuild_jump_labels (get_insns ()); | |
da7674f6 | 7632 | cse_cfg_altered |= cleanup_cfg (CLEANUP_CFG_CHANGED); |
2aac3a01 EB |
7633 | timevar_pop (TV_JUMP); |
7634 | } | |
7635 | else if (tem == 1 || optimize > 1) | |
da7674f6 | 7636 | cse_cfg_altered |= cleanup_cfg (0); |
932ad4d9 | 7637 | |
c2924966 | 7638 | return 0; |
ef330312 PB |
7639 | } |
7640 | ||
27a4cd48 DM |
7641 | namespace { |
7642 | ||
7643 | const pass_data pass_data_cse = | |
ef330312 | 7644 | { |
27a4cd48 DM |
7645 | RTL_PASS, /* type */ |
7646 | "cse1", /* name */ | |
7647 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
7648 | TV_CSE, /* tv_id */ |
7649 | 0, /* properties_required */ | |
7650 | 0, /* properties_provided */ | |
7651 | 0, /* properties_destroyed */ | |
7652 | 0, /* todo_flags_start */ | |
3bea341f | 7653 | TODO_df_finish, /* todo_flags_finish */ |
ef330312 PB |
7654 | }; |
7655 | ||
27a4cd48 DM |
7656 | class pass_cse : public rtl_opt_pass |
7657 | { | |
7658 | public: | |
c3284718 RS |
7659 | pass_cse (gcc::context *ctxt) |
7660 | : rtl_opt_pass (pass_data_cse, ctxt) | |
27a4cd48 DM |
7661 | {} |
7662 | ||
7663 | /* opt_pass methods: */ | |
1a3d085c | 7664 | virtual bool gate (function *) { return optimize > 0; } |
be55bfe6 | 7665 | virtual unsigned int execute (function *) { return rest_of_handle_cse (); } |
27a4cd48 DM |
7666 | |
7667 | }; // class pass_cse | |
7668 | ||
7669 | } // anon namespace | |
7670 | ||
7671 | rtl_opt_pass * | |
7672 | make_pass_cse (gcc::context *ctxt) | |
7673 | { | |
7674 | return new pass_cse (ctxt); | |
7675 | } | |
7676 | ||
ef330312 | 7677 | |
ef330312 | 7678 | /* Run second CSE pass after loop optimizations. */ |
c2924966 | 7679 | static unsigned int |
ef330312 PB |
7680 | rest_of_handle_cse2 (void) |
7681 | { | |
7682 | int tem; | |
7683 | ||
7684 | if (dump_file) | |
5b4fdb20 | 7685 | dump_flow_info (dump_file, dump_flags); |
ef330312 | 7686 | |
10d22567 | 7687 | tem = cse_main (get_insns (), max_reg_num ()); |
ef330312 PB |
7688 | |
7689 | /* Run a pass to eliminate duplicated assignments to condition code | |
7690 | registers. We have to run this after bypass_jumps, because it | |
7691 | makes it harder for that pass to determine whether a jump can be | |
7692 | bypassed safely. */ | |
7693 | cse_condition_code_reg (); | |
7694 | ||
ef330312 PB |
7695 | delete_trivially_dead_insns (get_insns (), max_reg_num ()); |
7696 | ||
2aac3a01 | 7697 | if (tem == 2) |
ef330312 PB |
7698 | { |
7699 | timevar_push (TV_JUMP); | |
7700 | rebuild_jump_labels (get_insns ()); | |
da7674f6 | 7701 | cse_cfg_altered |= cleanup_cfg (CLEANUP_CFG_CHANGED); |
ef330312 PB |
7702 | timevar_pop (TV_JUMP); |
7703 | } | |
ba585b91 | 7704 | else if (tem == 1 || cse_cfg_altered) |
da7674f6 | 7705 | cse_cfg_altered |= cleanup_cfg (0); |
2aac3a01 | 7706 | |
ef330312 | 7707 | cse_not_expected = 1; |
c2924966 | 7708 | return 0; |
ef330312 PB |
7709 | } |
7710 | ||
7711 | ||
27a4cd48 DM |
7712 | namespace { |
7713 | ||
7714 | const pass_data pass_data_cse2 = | |
ef330312 | 7715 | { |
27a4cd48 DM |
7716 | RTL_PASS, /* type */ |
7717 | "cse2", /* name */ | |
7718 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
7719 | TV_CSE2, /* tv_id */ |
7720 | 0, /* properties_required */ | |
7721 | 0, /* properties_provided */ | |
7722 | 0, /* properties_destroyed */ | |
7723 | 0, /* todo_flags_start */ | |
3bea341f | 7724 | TODO_df_finish, /* todo_flags_finish */ |
ef330312 | 7725 | }; |
5f39ad47 | 7726 | |
27a4cd48 DM |
7727 | class pass_cse2 : public rtl_opt_pass |
7728 | { | |
7729 | public: | |
c3284718 RS |
7730 | pass_cse2 (gcc::context *ctxt) |
7731 | : rtl_opt_pass (pass_data_cse2, ctxt) | |
27a4cd48 DM |
7732 | {} |
7733 | ||
7734 | /* opt_pass methods: */ | |
1a3d085c TS |
7735 | virtual bool gate (function *) |
7736 | { | |
7737 | return optimize > 0 && flag_rerun_cse_after_loop; | |
7738 | } | |
7739 | ||
be55bfe6 | 7740 | virtual unsigned int execute (function *) { return rest_of_handle_cse2 (); } |
27a4cd48 DM |
7741 | |
7742 | }; // class pass_cse2 | |
7743 | ||
7744 | } // anon namespace | |
7745 | ||
7746 | rtl_opt_pass * | |
7747 | make_pass_cse2 (gcc::context *ctxt) | |
7748 | { | |
7749 | return new pass_cse2 (ctxt); | |
7750 | } | |
7751 | ||
5f39ad47 SB |
7752 | /* Run second CSE pass after loop optimizations. */ |
7753 | static unsigned int | |
7754 | rest_of_handle_cse_after_global_opts (void) | |
7755 | { | |
7756 | int save_cfj; | |
7757 | int tem; | |
7758 | ||
7759 | /* We only want to do local CSE, so don't follow jumps. */ | |
7760 | save_cfj = flag_cse_follow_jumps; | |
7761 | flag_cse_follow_jumps = 0; | |
7762 | ||
7763 | rebuild_jump_labels (get_insns ()); | |
7764 | tem = cse_main (get_insns (), max_reg_num ()); | |
98ccd1d7 | 7765 | cse_cfg_altered |= purge_all_dead_edges (); |
5f39ad47 SB |
7766 | delete_trivially_dead_insns (get_insns (), max_reg_num ()); |
7767 | ||
7768 | cse_not_expected = !flag_rerun_cse_after_loop; | |
7769 | ||
7770 | /* If cse altered any jumps, rerun jump opts to clean things up. */ | |
7771 | if (tem == 2) | |
7772 | { | |
7773 | timevar_push (TV_JUMP); | |
7774 | rebuild_jump_labels (get_insns ()); | |
da7674f6 | 7775 | cse_cfg_altered |= cleanup_cfg (CLEANUP_CFG_CHANGED); |
5f39ad47 SB |
7776 | timevar_pop (TV_JUMP); |
7777 | } | |
ba585b91 | 7778 | else if (tem == 1 || cse_cfg_altered) |
da7674f6 | 7779 | cse_cfg_altered |= cleanup_cfg (0); |
5f39ad47 SB |
7780 | |
7781 | flag_cse_follow_jumps = save_cfj; | |
7782 | return 0; | |
7783 | } | |
7784 | ||
27a4cd48 DM |
7785 | namespace { |
7786 | ||
7787 | const pass_data pass_data_cse_after_global_opts = | |
5f39ad47 | 7788 | { |
27a4cd48 DM |
7789 | RTL_PASS, /* type */ |
7790 | "cse_local", /* name */ | |
7791 | OPTGROUP_NONE, /* optinfo_flags */ | |
27a4cd48 DM |
7792 | TV_CSE, /* tv_id */ |
7793 | 0, /* properties_required */ | |
7794 | 0, /* properties_provided */ | |
7795 | 0, /* properties_destroyed */ | |
7796 | 0, /* todo_flags_start */ | |
3bea341f | 7797 | TODO_df_finish, /* todo_flags_finish */ |
5f39ad47 | 7798 | }; |
27a4cd48 DM |
7799 | |
7800 | class pass_cse_after_global_opts : public rtl_opt_pass | |
7801 | { | |
7802 | public: | |
c3284718 RS |
7803 | pass_cse_after_global_opts (gcc::context *ctxt) |
7804 | : rtl_opt_pass (pass_data_cse_after_global_opts, ctxt) | |
27a4cd48 DM |
7805 | {} |
7806 | ||
7807 | /* opt_pass methods: */ | |
1a3d085c TS |
7808 | virtual bool gate (function *) |
7809 | { | |
7810 | return optimize > 0 && flag_rerun_cse_after_global_opts; | |
7811 | } | |
7812 | ||
be55bfe6 TS |
7813 | virtual unsigned int execute (function *) |
7814 | { | |
7815 | return rest_of_handle_cse_after_global_opts (); | |
7816 | } | |
27a4cd48 DM |
7817 | |
7818 | }; // class pass_cse_after_global_opts | |
7819 | ||
7820 | } // anon namespace | |
7821 | ||
7822 | rtl_opt_pass * | |
7823 | make_pass_cse_after_global_opts (gcc::context *ctxt) | |
7824 | { | |
7825 | return new pass_cse_after_global_opts (ctxt); | |
7826 | } |