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1 | .. |
2 | Copyright 1988-2022 Free Software Foundation, Inc. | |
3 | This is part of the GCC manual. | |
4 | For copying conditions, see the copyright.rst file. | |
5 | ||
6 | .. program:: Visium | |
7 | ||
8 | .. index:: Visium options | |
9 | ||
10 | .. _visium-options: | |
11 | ||
12 | Visium Options | |
13 | ^^^^^^^^^^^^^^ | |
14 | ||
15 | .. option:: -mdebug | |
16 | ||
17 | A program which performs file I/O and is destined to run on an MCM target | |
18 | should be linked with this option. It causes the libraries libc.a and | |
19 | libdebug.a to be linked. The program should be run on the target under | |
20 | the control of the GDB remote debugging stub. | |
21 | ||
22 | .. option:: -msim | |
23 | ||
24 | A program which performs file I/O and is destined to run on the simulator | |
25 | should be linked with option. This causes libraries libc.a and libsim.a to | |
26 | be linked. | |
27 | ||
28 | .. option:: -mfpu, -mhard-float | |
29 | ||
30 | Generate code containing floating-point instructions. This is the | |
31 | default. | |
32 | ||
33 | .. option:: -mno-fpu, -msoft-float | |
34 | ||
35 | Generate code containing library calls for floating-point. | |
36 | ||
37 | :option:`-msoft-float` changes the calling convention in the output file; | |
38 | therefore, it is only useful if you compile *all* of a program with | |
39 | this option. In particular, you need to compile :samp:`libgcc.a`, the | |
40 | library that comes with GCC, with :option:`-msoft-float` in order for | |
41 | this to work. | |
42 | ||
43 | .. option:: -mcpu={cpu_type} | |
44 | ||
45 | Set the instruction set, register set, and instruction scheduling parameters | |
46 | for machine type :samp:`{cpu_type}`. Supported values for :samp:`{cpu_type}` are | |
47 | :samp:`mcm`, :samp:`gr5` and :samp:`gr6`. | |
48 | ||
49 | :samp:`mcm` is a synonym of :samp:`gr5` present for backward compatibility. | |
50 | ||
51 | By default (unless configured otherwise), GCC generates code for the GR5 | |
52 | variant of the Visium architecture. | |
53 | ||
54 | With :option:`-mcpu=gr6`, GCC generates code for the GR6 variant of the Visium | |
55 | architecture. The only difference from GR5 code is that the compiler will | |
56 | generate block move instructions. | |
57 | ||
58 | .. option:: -mtune={cpu_type} | |
59 | ||
60 | Set the instruction scheduling parameters for machine type :samp:`{cpu_type}`, | |
61 | but do not set the instruction set or register set that the option | |
62 | :option:`-mcpu=cpu_type` would. | |
63 | ||
64 | .. option:: -msv-mode | |
65 | ||
66 | Generate code for the supervisor mode, where there are no restrictions on | |
67 | the access to general registers. This is the default. | |
68 | ||
69 | .. option:: -muser-mode | |
70 | ||
71 | Generate code for the user mode, where the access to some general registers | |
72 | is forbidden: on the GR5, registers r24 to r31 cannot be accessed in this | |
3ed1b4ce | 73 | mode; on the GR6, only registers r29 to r31 are affected. |