[thirdparty/gcc.git] / gcc / doc / gccint / target-macros / defining-coprocessor-specifics-for-mips-targets.rst

..
  Copyright 1988-2022 Free Software Foundation, Inc.
  This is part of the GCC manual.
  For copying conditions, see the copyright.rst file.

.. index:: MIPS coprocessor-definition macros

.. _mips-coprocessors:

Defining coprocessor specifics for MIPS targets.
************************************************

The MIPS specification allows MIPS implementations to have as many as 4
coprocessors, each with as many as 32 private registers.  GCC supports
accessing these registers and transferring values between the registers
and memory using asm-ized variables.  For example:

.. code-block:: c++

    register unsigned int cp0count asm ("c0r1");
    unsigned int d;

    d = cp0count + 3;

('c0r1' is the default name of register 1 in coprocessor 0; alternate
names may be added as described below, or the default names may be
overridden entirely in ``SUBTARGET_CONDITIONAL_REGISTER_USAGE``.)

Coprocessor registers are assumed to be epilogue-used; sets to them will
be preserved even if it does not appear that the register is used again
later in the function.

Another note: according to the MIPS spec, coprocessor 1 (if present) is
the FPU.  One accesses COP1 registers through standard mips
floating-point support; they are not included in this mechanism.
Commit	Line	Data
c63539ff ML	1	..
	2	Copyright 1988-2022 Free Software Foundation, Inc.
	3	This is part of the GCC manual.
	4	For copying conditions, see the copyright.rst file.
	5
	6	.. index:: MIPS coprocessor-definition macros
	7
	8	.. _mips-coprocessors:
	9
	10	Defining coprocessor specifics for MIPS targets.
	11	************************************************
	12
	13	The MIPS specification allows MIPS implementations to have as many as 4
	14	coprocessors, each with as many as 32 private registers. GCC supports
	15	accessing these registers and transferring values between the registers
	16	and memory using asm-ized variables. For example:
	17
	18	.. code-block:: c++
	19
	20	register unsigned int cp0count asm ("c0r1");
	21	unsigned int d;
	22
	23	d = cp0count + 3;
	24
	25	('c0r1' is the default name of register 1 in coprocessor 0; alternate
	26	names may be added as described below, or the default names may be
	27	overridden entirely in ``SUBTARGET_CONDITIONAL_REGISTER_USAGE``.)
	28
	29	Coprocessor registers are assumed to be epilogue-used; sets to them will
	30	be preserved even if it does not appear that the register is used again
	31	later in the function.
	32
	33	Another note: according to the MIPS spec, coprocessor 1 (if present) is
	34	the FPU. One accesses COP1 registers through standard mips
3ed1b4ce	35	floating-point support; they are not included in this mechanism.