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1 | .. |
2 | Copyright 1988-2022 Free Software Foundation, Inc. | |
3 | This is part of the GCC manual. | |
4 | For copying conditions, see the copyright.rst file. | |
5 | ||
6 | .. _effective-target-keywords: | |
7 | ||
8 | Keywords describing target attributes | |
9 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ | |
10 | ||
11 | Effective-target keywords identify sets of targets that support | |
12 | particular functionality. They are used to limit tests to be run only | |
13 | for particular targets, or to specify that particular sets of targets | |
14 | are expected to fail some tests. | |
15 | ||
16 | Effective-target keywords are defined in :samp:`lib/target-supports.exp` in | |
17 | the GCC testsuite, with the exception of those that are documented as | |
18 | being local to a particular test directory. | |
19 | ||
20 | The :samp:`effective target` takes into account all of the compiler options | |
21 | with which the test will be compiled, including the multilib options. | |
22 | By convention, keywords ending in ``_nocache`` can also include options | |
23 | specified for the particular test in an earlier ``dg-options`` or | |
24 | ``dg-add-options`` directive. | |
25 | ||
26 | Endianness | |
27 | ~~~~~~~~~~ | |
28 | ||
29 | ``be`` | |
30 | Target uses big-endian memory order for multi-byte and multi-word data. | |
31 | ||
32 | ``le`` | |
33 | Target uses little-endian memory order for multi-byte and multi-word data. | |
34 | ||
35 | Data type sizes | |
36 | ~~~~~~~~~~~~~~~ | |
37 | ||
38 | ``ilp32`` | |
39 | Target has 32-bit ``int``, ``long``, and pointers. | |
40 | ||
41 | ``lp64`` | |
42 | Target has 32-bit ``int``, 64-bit ``long`` and pointers. | |
43 | ||
44 | ``llp64`` | |
45 | Target has 32-bit ``int`` and ``long``, 64-bit ``long long`` | |
46 | and pointers. | |
47 | ||
48 | ``double64`` | |
49 | Target has 64-bit ``double``. | |
50 | ||
51 | ``double64plus`` | |
52 | Target has ``double`` that is 64 bits or longer. | |
53 | ||
54 | ``longdouble128`` | |
55 | Target has 128-bit ``long double``. | |
56 | ||
57 | ``int32plus`` | |
58 | Target has ``int`` that is at 32 bits or longer. | |
59 | ||
60 | ``int16`` | |
61 | Target has ``int`` that is 16 bits or shorter. | |
62 | ||
63 | ``longlong64`` | |
64 | Target has 64-bit ``long long``. | |
65 | ||
66 | ``long_neq_int`` | |
67 | Target has ``int`` and ``long`` with different sizes. | |
68 | ||
69 | ``short_eq_int`` | |
70 | Target has ``short`` and ``int`` with the same size. | |
71 | ||
72 | ``ptr_eq_short`` | |
73 | Target has pointers (``void *``) and ``short`` with the same size. | |
74 | ||
75 | ``int_eq_float`` | |
76 | Target has ``int`` and ``float`` with the same size. | |
77 | ||
78 | ``ptr_eq_long`` | |
79 | Target has pointers (``void *``) and ``long`` with the same size. | |
80 | ||
81 | ``large_double`` | |
82 | Target supports ``double`` that is longer than ``float``. | |
83 | ||
84 | ``large_long_double`` | |
85 | Target supports ``long double`` that is longer than ``double``. | |
86 | ||
87 | ``ptr32plus`` | |
88 | Target has pointers that are 32 bits or longer. | |
89 | ||
90 | ``size20plus`` | |
91 | Target has a 20-bit or larger address space, so supports at least | |
92 | 16-bit array and structure sizes. | |
93 | ||
94 | ``size24plus`` | |
95 | Target has a 24-bit or larger address space, so supports at least | |
96 | 20-bit array and structure sizes. | |
97 | ||
98 | ``size32plus`` | |
99 | Target has a 32-bit or larger address space, so supports at least | |
100 | 24-bit array and structure sizes. | |
101 | ||
102 | ``4byte_wchar_t`` | |
103 | Target has ``wchar_t`` that is at least 4 bytes. | |
104 | ||
105 | :samp:`float{n}` | |
106 | Target has the ``_Floatn`` type. | |
107 | ||
108 | :samp:`float{n}x` | |
109 | Target has the ``_Floatnx`` type. | |
110 | ||
111 | :samp:`float{n}_runtime` | |
112 | Target has the ``_Floatn`` type, including runtime support | |
113 | for any options added with ``dg-add-options``. | |
114 | ||
115 | :samp:`float{n}x_runtime` | |
116 | Target has the ``_Floatnx`` type, including runtime support | |
117 | for any options added with ``dg-add-options``. | |
118 | ||
119 | ``floatn_nx_runtime`` | |
120 | Target has runtime support for any options added with | |
121 | ``dg-add-options`` for any ``_Floatn`` or | |
122 | ``_Floatnx`` type. | |
123 | ||
124 | ``inf`` | |
125 | Target supports floating point infinite (``inf``) for type | |
126 | ``double``. | |
127 | ||
128 | ``inff`` | |
129 | Target supports floating point infinite (``inf``) for type | |
130 | ``float``. | |
131 | ||
132 | Fortran-specific attributes | |
133 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
134 | ||
135 | ``fortran_integer_16`` | |
136 | Target supports Fortran ``integer`` that is 16 bytes or longer. | |
137 | ||
138 | ``fortran_real_10`` | |
139 | Target supports Fortran ``real`` that is 10 bytes or longer. | |
140 | ||
141 | ``fortran_real_16`` | |
142 | Target supports Fortran ``real`` that is 16 bytes or longer. | |
143 | ||
144 | ``fortran_large_int`` | |
145 | Target supports Fortran ``integer`` kinds larger than ``integer(8)``. | |
146 | ||
147 | ``fortran_large_real`` | |
148 | Target supports Fortran ``real`` kinds larger than ``real(8)``. | |
149 | ||
150 | Vector-specific attributes | |
151 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
152 | ||
153 | ``vect_align_stack_vars`` | |
154 | The target's ABI allows stack variables to be aligned to the preferred | |
155 | vector alignment. | |
156 | ||
157 | ``vect_avg_qi`` | |
158 | Target supports both signed and unsigned averaging operations on vectors | |
159 | of bytes. | |
160 | ||
161 | ``vect_mulhrs_hi`` | |
162 | Target supports both signed and unsigned multiply-high-with-round-and-scale | |
163 | operations on vectors of half-words. | |
164 | ||
165 | ``vect_sdiv_pow2_si`` | |
166 | Target supports signed division by constant power-of-2 operations | |
167 | on vectors of 4-byte integers. | |
168 | ||
169 | ``vect_condition`` | |
170 | Target supports vector conditional operations. | |
171 | ||
172 | ``vect_cond_mixed`` | |
173 | Target supports vector conditional operations where comparison operands | |
174 | have different type from the value operands. | |
175 | ||
176 | ``vect_double`` | |
177 | Target supports hardware vectors of ``double``. | |
178 | ||
179 | ``vect_double_cond_arith`` | |
180 | Target supports conditional addition, subtraction, multiplication, | |
181 | division, minimum and maximum on vectors of ``double``, via the | |
182 | ``cond_`` optabs. | |
183 | ||
184 | ``vect_element_align_preferred`` | |
185 | The target's preferred vector alignment is the same as the element | |
186 | alignment. | |
187 | ||
188 | ``vect_float`` | |
189 | Target supports hardware vectors of ``float`` when | |
190 | :option:`-funsafe-math-optimizations` is in effect. | |
191 | ||
192 | ``vect_float_strict`` | |
193 | Target supports hardware vectors of ``float`` when | |
194 | :option:`-funsafe-math-optimizations` is not in effect. | |
195 | This implies ``vect_float``. | |
196 | ||
197 | ``vect_int`` | |
198 | Target supports hardware vectors of ``int``. | |
199 | ||
200 | ``vect_long`` | |
201 | Target supports hardware vectors of ``long``. | |
202 | ||
203 | ``vect_long_long`` | |
204 | Target supports hardware vectors of ``long long``. | |
205 | ||
206 | ``vect_check_ptrs`` | |
207 | Target supports the ``check_raw_ptrs`` and ``check_war_ptrs`` | |
208 | optabs on vectors. | |
209 | ||
210 | ``vect_fully_masked`` | |
211 | Target supports fully-masked (also known as fully-predicated) loops, | |
212 | so that vector loops can handle partial as well as full vectors. | |
213 | ||
214 | ``vect_masked_load`` | |
215 | Target supports vector masked loads. | |
216 | ||
217 | ``vect_masked_store`` | |
218 | Target supports vector masked stores. | |
219 | ||
220 | ``vect_gather_load_ifn`` | |
221 | Target supports vector gather loads using internal functions | |
222 | (rather than via built-in functions or emulation). | |
223 | ||
224 | ``vect_scatter_store`` | |
225 | Target supports vector scatter stores. | |
226 | ||
227 | ``vect_aligned_arrays`` | |
228 | Target aligns arrays to vector alignment boundary. | |
229 | ||
230 | ``vect_hw_misalign`` | |
231 | Target supports a vector misalign access. | |
232 | ||
233 | ``vect_no_align`` | |
234 | Target does not support a vector alignment mechanism. | |
235 | ||
236 | ``vect_peeling_profitable`` | |
237 | Target might require to peel loops for alignment purposes. | |
238 | ||
239 | ``vect_no_int_min_max`` | |
240 | Target does not support a vector min and max instruction on ``int``. | |
241 | ||
242 | ``vect_no_int_add`` | |
243 | Target does not support a vector add instruction on ``int``. | |
244 | ||
245 | ``vect_no_bitwise`` | |
246 | Target does not support vector bitwise instructions. | |
247 | ||
248 | ``vect_bool_cmp`` | |
249 | Target supports comparison of ``bool`` vectors for at least one | |
250 | vector length. | |
251 | ||
252 | ``vect_char_add`` | |
253 | Target supports addition of ``char`` vectors for at least one | |
254 | vector length. | |
255 | ||
256 | ``vect_char_mult`` | |
257 | Target supports ``vector char`` multiplication. | |
258 | ||
259 | ``vect_short_mult`` | |
260 | Target supports ``vector short`` multiplication. | |
261 | ||
262 | ``vect_int_mult`` | |
263 | Target supports ``vector int`` multiplication. | |
264 | ||
265 | ``vect_long_mult`` | |
266 | Target supports 64 bit ``vector long`` multiplication. | |
267 | ||
268 | ``vect_extract_even_odd`` | |
269 | Target supports vector even/odd element extraction. | |
270 | ||
271 | ``vect_extract_even_odd_wide`` | |
272 | Target supports vector even/odd element extraction of vectors with elements | |
273 | ``SImode`` or larger. | |
274 | ||
275 | ``vect_interleave`` | |
276 | Target supports vector interleaving. | |
277 | ||
278 | ``vect_strided`` | |
279 | Target supports vector interleaving and extract even/odd. | |
280 | ||
281 | ``vect_strided_wide`` | |
282 | Target supports vector interleaving and extract even/odd for wide | |
283 | element types. | |
284 | ||
285 | ``vect_perm`` | |
286 | Target supports vector permutation. | |
287 | ||
288 | ``vect_perm_byte`` | |
289 | Target supports permutation of vectors with 8-bit elements. | |
290 | ||
291 | ``vect_perm_short`` | |
292 | Target supports permutation of vectors with 16-bit elements. | |
293 | ||
294 | ``vect_perm3_byte`` | |
295 | Target supports permutation of vectors with 8-bit elements, and for the | |
296 | default vector length it is possible to permute: | |
297 | ||
298 | .. code-block:: c++ | |
299 | ||
300 | { a0, a1, a2, b0, b1, b2, ... } | |
301 | ||
302 | to: | |
303 | ||
304 | .. code-block:: c++ | |
305 | ||
306 | { a0, a0, a0, b0, b0, b0, ... } | |
307 | { a1, a1, a1, b1, b1, b1, ... } | |
308 | { a2, a2, a2, b2, b2, b2, ... } | |
309 | ||
310 | using only two-vector permutes, regardless of how long the sequence is. | |
311 | ||
312 | ``vect_perm3_int`` | |
313 | Like ``vect_perm3_byte``, but for 32-bit elements. | |
314 | ||
315 | ``vect_perm3_short`` | |
316 | Like ``vect_perm3_byte``, but for 16-bit elements. | |
317 | ||
318 | ``vect_shift`` | |
319 | Target supports a hardware vector shift operation. | |
320 | ||
321 | ``vect_unaligned_possible`` | |
322 | Target prefers vectors to have an alignment greater than element | |
323 | alignment, but also allows unaligned vector accesses in some | |
324 | circumstances. | |
325 | ||
326 | ``vect_variable_length`` | |
327 | Target has variable-length vectors. | |
328 | ||
329 | ``vect64`` | |
330 | Target supports vectors of 64 bits. | |
331 | ||
332 | ``vect32`` | |
333 | Target supports vectors of 32 bits. | |
334 | ||
335 | ``vect_widen_sum_hi_to_si`` | |
336 | Target supports a vector widening summation of ``short`` operands | |
337 | into ``int`` results, or can promote (unpack) from ``short`` | |
338 | to ``int``. | |
339 | ||
340 | ``vect_widen_sum_qi_to_hi`` | |
341 | Target supports a vector widening summation of ``char`` operands | |
342 | into ``short`` results, or can promote (unpack) from ``char`` | |
343 | to ``short``. | |
344 | ||
345 | ``vect_widen_sum_qi_to_si`` | |
346 | Target supports a vector widening summation of ``char`` operands | |
347 | into ``int`` results. | |
348 | ||
349 | ``vect_widen_mult_qi_to_hi`` | |
350 | Target supports a vector widening multiplication of ``char`` operands | |
351 | into ``short`` results, or can promote (unpack) from ``char`` to | |
352 | ``short`` and perform non-widening multiplication of ``short``. | |
353 | ||
354 | ``vect_widen_mult_hi_to_si`` | |
355 | Target supports a vector widening multiplication of ``short`` operands | |
356 | into ``int`` results, or can promote (unpack) from ``short`` to | |
357 | ``int`` and perform non-widening multiplication of ``int``. | |
358 | ||
359 | ``vect_widen_mult_si_to_di_pattern`` | |
360 | Target supports a vector widening multiplication of ``int`` operands | |
361 | into ``long`` results. | |
362 | ||
363 | ``vect_sdot_qi`` | |
364 | Target supports a vector dot-product of ``signed char``. | |
365 | ||
366 | ``vect_udot_qi`` | |
367 | Target supports a vector dot-product of ``unsigned char``. | |
368 | ||
369 | ``vect_usdot_qi`` | |
370 | Target supports a vector dot-product where one operand of the multiply is | |
371 | ``signed char`` and the other of ``unsigned char``. | |
372 | ||
373 | ``vect_sdot_hi`` | |
374 | Target supports a vector dot-product of ``signed short``. | |
375 | ||
376 | ``vect_udot_hi`` | |
377 | Target supports a vector dot-product of ``unsigned short``. | |
378 | ||
379 | ``vect_pack_trunc`` | |
380 | Target supports a vector demotion (packing) of ``short`` to ``char`` | |
381 | and from ``int`` to ``short`` using modulo arithmetic. | |
382 | ||
383 | ``vect_unpack`` | |
384 | Target supports a vector promotion (unpacking) of ``char`` to ``short`` | |
385 | and from ``char`` to ``int``. | |
386 | ||
387 | ``vect_intfloat_cvt`` | |
388 | Target supports conversion from ``signed int`` to ``float``. | |
389 | ||
390 | ``vect_uintfloat_cvt`` | |
391 | Target supports conversion from ``unsigned int`` to ``float``. | |
392 | ||
393 | ``vect_floatint_cvt`` | |
394 | Target supports conversion from ``float`` to ``signed int``. | |
395 | ||
396 | ``vect_floatuint_cvt`` | |
397 | Target supports conversion from ``float`` to ``unsigned int``. | |
398 | ||
399 | ``vect_intdouble_cvt`` | |
400 | Target supports conversion from ``signed int`` to ``double``. | |
401 | ||
402 | ``vect_doubleint_cvt`` | |
403 | Target supports conversion from ``double`` to ``signed int``. | |
404 | ||
405 | ``vect_max_reduc`` | |
406 | Target supports max reduction for vectors. | |
407 | ||
408 | ``vect_sizes_16B_8B`` | |
409 | Target supports 16- and 8-bytes vectors. | |
410 | ||
411 | ``vect_sizes_32B_16B`` | |
412 | Target supports 32- and 16-bytes vectors. | |
413 | ||
414 | ``vect_logical_reduc`` | |
415 | Target supports AND, IOR and XOR reduction on vectors. | |
416 | ||
417 | ``vect_fold_extract_last`` | |
418 | Target supports the ``fold_extract_last`` optab. | |
419 | ||
420 | ``vect_len_load_store`` | |
421 | Target supports the ``len_load`` and ``len_store`` optabs. | |
422 | ||
423 | ``vect_partial_vectors_usage_1`` | |
424 | Target supports loop vectorization with partial vectors and | |
425 | ``vect-partial-vector-usage`` is set to 1. | |
426 | ||
427 | ``vect_partial_vectors_usage_2`` | |
428 | Target supports loop vectorization with partial vectors and | |
429 | ``vect-partial-vector-usage`` is set to 2. | |
430 | ||
431 | ``vect_partial_vectors`` | |
432 | Target supports loop vectorization with partial vectors and | |
433 | ``vect-partial-vector-usage`` is nonzero. | |
434 | ||
435 | ``vect_slp_v2qi_store_align`` | |
436 | Target supports vectorization of 2-byte char stores with 2-byte aligned | |
437 | address at plain :option:`-O2`. | |
438 | ||
439 | ``vect_slp_v4qi_store_align`` | |
440 | Target supports vectorization of 4-byte char stores with 4-byte aligned | |
441 | address at plain :option:`-O2`. | |
442 | ||
443 | ``vect_slp_v4qi_store_unalign`` | |
444 | Target supports vectorization of 4-byte char stores with unaligned address | |
445 | at plain :option:`-O2`. | |
446 | ||
447 | ``struct_4char_block_move`` | |
448 | Target supports block move for 8-byte aligned 4-byte size struct initialization. | |
449 | ||
450 | ``vect_slp_v4qi_store_unalign_1`` | |
451 | Target supports vectorization of 4-byte char stores with unaligned address | |
452 | or store them with constant pool at plain :option:`-O2`. | |
453 | ||
454 | ``struct_8char_block_move`` | |
455 | Target supports block move for 8-byte aligned 8-byte size struct initialization. | |
456 | ||
457 | ``vect_slp_v8qi_store_unalign_1`` | |
458 | Target supports vectorization of 8-byte char stores with unaligned address | |
459 | or store them with constant pool at plain :option:`-O2`. | |
460 | ||
461 | ``struct_16char_block_move`` | |
462 | Target supports block move for 8-byte aligned 16-byte size struct | |
463 | initialization. | |
464 | ||
465 | ``vect_slp_v16qi_store_unalign_1`` | |
466 | Target supports vectorization of 16-byte char stores with unaligned address | |
467 | or store them with constant pool at plain :option:`-O2`. | |
468 | ||
469 | ``vect_slp_v2hi_store_align`` | |
470 | Target supports vectorization of 4-byte short stores with 4-byte aligned | |
471 | addressat plain :option:`-O2`. | |
472 | ||
473 | ``vect_slp_v2hi_store_unalign`` | |
474 | Target supports vectorization of 4-byte short stores with unaligned address | |
475 | at plain :option:`-O2`. | |
476 | ||
477 | ``vect_slp_v4hi_store_unalign`` | |
478 | Target supports vectorization of 8-byte short stores with unaligned address | |
479 | at plain :option:`-O2`. | |
480 | ||
481 | ``vect_slp_v2si_store_align`` | |
482 | Target supports vectorization of 8-byte int stores with 8-byte aligned address | |
483 | at plain :option:`-O2`. | |
484 | ||
485 | ``vect_slp_v4si_store_unalign`` | |
486 | Target supports vectorization of 16-byte int stores with unaligned address | |
487 | at plain :option:`-O2`. | |
488 | ||
489 | Thread Local Storage attributes | |
490 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
491 | ||
492 | ``tls`` | |
493 | Target supports thread-local storage. | |
494 | ||
495 | ``tls_native`` | |
496 | Target supports native (rather than emulated) thread-local storage. | |
497 | ||
498 | ``tls_runtime`` | |
499 | Test system supports executing TLS executables. | |
500 | ||
501 | Decimal floating point attributes | |
502 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
503 | ||
504 | ``dfp`` | |
505 | Targets supports compiling decimal floating point extension to C. | |
506 | ||
507 | ``dfp_nocache`` | |
508 | Including the options used to compile this particular test, the | |
509 | target supports compiling decimal floating point extension to C. | |
510 | ||
511 | ``dfprt`` | |
512 | Test system can execute decimal floating point tests. | |
513 | ||
514 | ``dfprt_nocache`` | |
515 | Including the options used to compile this particular test, the | |
516 | test system can execute decimal floating point tests. | |
517 | ||
518 | ``hard_dfp`` | |
519 | Target generates decimal floating point instructions with current options. | |
520 | ||
521 | ``dfp_bid`` | |
522 | Target uses the BID format for decimal floating point. | |
523 | ||
524 | ARM-specific attributes | |
525 | ~~~~~~~~~~~~~~~~~~~~~~~ | |
526 | ||
527 | ``arm32`` | |
528 | ARM target generates 32-bit code. | |
529 | ||
530 | ``arm_little_endian`` | |
531 | ARM target that generates little-endian code. | |
532 | ||
533 | ``arm_eabi`` | |
534 | ARM target adheres to the ABI for the ARM Architecture. | |
535 | ||
536 | .. _arm_fp_ok: | |
537 | ||
538 | ``arm_fp_ok`` | |
539 | ARM target defines ``__ARM_FP`` using ``-mfloat-abi=softfp`` or | |
540 | equivalent options. Some multilibs may be incompatible with these | |
541 | options. | |
542 | ||
543 | .. _arm_fp_dp_ok: | |
544 | ||
545 | ``arm_fp_dp_ok`` | |
546 | ARM target defines ``__ARM_FP`` with double-precision support using | |
547 | ``-mfloat-abi=softfp`` or equivalent options. Some multilibs may | |
548 | be incompatible with these options. | |
549 | ||
550 | ``arm_hf_eabi`` | |
551 | ARM target adheres to the VFP and Advanced SIMD Register Arguments | |
552 | variant of the ABI for the ARM Architecture (as selected with | |
553 | ``-mfloat-abi=hard``). | |
554 | ||
555 | ``arm_softfloat`` | |
556 | ARM target uses emulated floating point operations. | |
557 | ||
558 | ``arm_hard_vfp_ok`` | |
559 | ARM target supports ``-mfpu=vfp -mfloat-abi=hard``. | |
560 | Some multilibs may be incompatible with these options. | |
561 | ||
562 | ``arm_iwmmxt_ok`` | |
563 | ARM target supports ``-mcpu=iwmmxt``. | |
564 | Some multilibs may be incompatible with this option. | |
565 | ||
566 | ``arm_neon`` | |
567 | ARM target supports generating NEON instructions. | |
568 | ||
569 | ``arm_tune_string_ops_prefer_neon`` | |
570 | Test CPU tune supports inlining string operations with NEON instructions. | |
571 | ||
572 | ``arm_neon_hw`` | |
573 | Test system supports executing NEON instructions. | |
574 | ||
575 | ``arm_neonv2_hw`` | |
576 | Test system supports executing NEON v2 instructions. | |
577 | ||
578 | .. _arm_neon_ok: | |
579 | ||
580 | ``arm_neon_ok`` | |
581 | ARM Target supports ``-mfpu=neon -mfloat-abi=softfp`` or compatible | |
582 | options. Some multilibs may be incompatible with these options. | |
583 | ||
584 | ``arm_neon_ok_no_float_abi`` | |
585 | ARM Target supports NEON with ``-mfpu=neon``, but without any | |
586 | -mfloat-abi= option. Some multilibs may be incompatible with this | |
587 | option. | |
588 | ||
589 | ``arm_neonv2_ok`` | |
590 | ARM Target supports ``-mfpu=neon-vfpv4 -mfloat-abi=softfp`` or compatible | |
591 | options. Some multilibs may be incompatible with these options. | |
592 | ||
593 | .. _arm_fp16_ok: | |
594 | ||
595 | ``arm_fp16_ok`` | |
596 | Target supports options to generate VFP half-precision floating-point | |
597 | instructions. Some multilibs may be incompatible with these | |
598 | options. This test is valid for ARM only. | |
599 | ||
600 | ``arm_fp16_hw`` | |
601 | Target supports executing VFP half-precision floating-point | |
602 | instructions. This test is valid for ARM only. | |
603 | ||
604 | .. _arm_neon_fp16_ok: | |
605 | ||
606 | ``arm_neon_fp16_ok`` | |
607 | ARM Target supports ``-mfpu=neon-fp16 -mfloat-abi=softfp`` or compatible | |
608 | options, including ``-mfp16-format=ieee`` if necessary to obtain the | |
609 | ``__fp16`` type. Some multilibs may be incompatible with these options. | |
610 | ||
611 | ``arm_neon_fp16_hw`` | |
612 | Test system supports executing Neon half-precision float instructions. | |
613 | (Implies previous.) | |
614 | ||
615 | ``arm_fp16_alternative_ok`` | |
616 | ARM target supports the ARM FP16 alternative format. Some multilibs | |
617 | may be incompatible with the options needed. | |
618 | ||
619 | ``arm_fp16_none_ok`` | |
620 | ARM target supports specifying none as the ARM FP16 format. | |
621 | ||
622 | ``arm_thumb1_ok`` | |
623 | ARM target generates Thumb-1 code for ``-mthumb``. | |
624 | ||
625 | ``arm_thumb2_ok`` | |
626 | ARM target generates Thumb-2 code for ``-mthumb``. | |
627 | ||
628 | ``arm_nothumb`` | |
629 | ARM target that is not using Thumb. | |
630 | ||
631 | ``arm_vfp_ok`` | |
632 | ARM target supports ``-mfpu=vfp -mfloat-abi=softfp``. | |
633 | Some multilibs may be incompatible with these options. | |
634 | ||
635 | .. _arm_vfp3_ok: | |
636 | ||
637 | ``arm_vfp3_ok`` | |
638 | ARM target supports ``-mfpu=vfp3 -mfloat-abi=softfp``. | |
639 | Some multilibs may be incompatible with these options. | |
640 | ||
641 | .. _arm_arch_v8a_hard_ok: | |
642 | ||
643 | ``arm_arch_v8a_hard_ok`` | |
644 | The compiler is targeting ``arm*-*-*`` and can compile and assemble code | |
645 | using the options ``-march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=hard``. | |
646 | This is not enough to guarantee that linking works. | |
647 | ||
648 | ``arm_arch_v8a_hard_multilib`` | |
649 | The compiler is targeting ``arm*-*-*`` and can build programs using | |
650 | the options ``-march=armv8-a -mfpu=neon-fp-armv8 -mfloat-abi=hard``. | |
651 | The target can also run the resulting binaries. | |
652 | ||
653 | ``arm_v8_vfp_ok`` | |
654 | ARM target supports ``-mfpu=fp-armv8 -mfloat-abi=softfp``. | |
655 | Some multilibs may be incompatible with these options. | |
656 | ||
657 | ``arm_v8_neon_ok`` | |
658 | ARM target supports ``-mfpu=neon-fp-armv8 -mfloat-abi=softfp``. | |
659 | Some multilibs may be incompatible with these options. | |
660 | ||
661 | .. _arm_v8_1a_neon_ok: | |
662 | ||
663 | ``arm_v8_1a_neon_ok`` | |
664 | ARM target supports options to generate ARMv8.1-A Adv.SIMD instructions. | |
665 | Some multilibs may be incompatible with these options. | |
666 | ||
667 | ``arm_v8_1a_neon_hw`` | |
668 | ARM target supports executing ARMv8.1-A Adv.SIMD instructions. Some | |
669 | multilibs may be incompatible with the options needed. Implies | |
670 | arm_v8_1a_neon_ok. | |
671 | ||
672 | ``arm_acq_rel`` | |
673 | ARM target supports acquire-release instructions. | |
674 | ||
675 | .. _arm_v8_2a_fp16_scalar_ok: | |
676 | ||
677 | ``arm_v8_2a_fp16_scalar_ok`` | |
678 | ARM target supports options to generate instructions for ARMv8.2-A and | |
679 | scalar instructions from the FP16 extension. Some multilibs may be | |
680 | incompatible with these options. | |
681 | ||
682 | ``arm_v8_2a_fp16_scalar_hw`` | |
683 | ARM target supports executing instructions for ARMv8.2-A and scalar | |
684 | instructions from the FP16 extension. Some multilibs may be | |
685 | incompatible with these options. Implies arm_v8_2a_fp16_neon_ok. | |
686 | ||
687 | .. _arm_v8_2a_fp16_neon_ok: | |
688 | ||
689 | ``arm_v8_2a_fp16_neon_ok`` | |
690 | ARM target supports options to generate instructions from ARMv8.2-A with | |
691 | the FP16 extension. Some multilibs may be incompatible with these | |
692 | options. Implies arm_v8_2a_fp16_scalar_ok. | |
693 | ||
694 | ``arm_v8_2a_fp16_neon_hw`` | |
695 | ARM target supports executing instructions from ARMv8.2-A with the FP16 | |
696 | extension. Some multilibs may be incompatible with these options. | |
697 | Implies arm_v8_2a_fp16_neon_ok and arm_v8_2a_fp16_scalar_hw. | |
698 | ||
699 | .. _arm_v8_2a_dotprod_neon_ok: | |
700 | ||
701 | ``arm_v8_2a_dotprod_neon_ok`` | |
702 | ARM target supports options to generate instructions from ARMv8.2-A with | |
703 | the Dot Product extension. Some multilibs may be incompatible with these | |
704 | options. | |
705 | ||
706 | ``arm_v8_2a_dotprod_neon_hw`` | |
707 | ARM target supports executing instructions from ARMv8.2-A with the Dot | |
708 | Product extension. Some multilibs may be incompatible with these options. | |
709 | Implies arm_v8_2a_dotprod_neon_ok. | |
710 | ||
711 | ``arm_v8_2a_i8mm_neon_hw`` | |
712 | ARM target supports executing instructions from ARMv8.2-A with the 8-bit | |
713 | Matrix Multiply extension. Some multilibs may be incompatible with these | |
714 | options. Implies arm_v8_2a_i8mm_ok. | |
715 | ||
716 | .. _arm_fp16fml_neon_ok: | |
717 | ||
718 | ``arm_fp16fml_neon_ok`` | |
719 | ARM target supports extensions to generate the ``VFMAL`` and ``VFMLS`` | |
720 | half-precision floating-point instructions available from ARMv8.2-A and | |
721 | onwards. Some multilibs may be incompatible with these options. | |
722 | ||
723 | ``arm_v8_2a_bf16_neon_ok`` | |
724 | ARM target supports options to generate instructions from ARMv8.2-A with | |
725 | the BFloat16 extension (bf16). Some multilibs may be incompatible with these | |
726 | options. | |
727 | ||
728 | ``arm_v8_2a_i8mm_ok`` | |
729 | ARM target supports options to generate instructions from ARMv8.2-A with | |
730 | the 8-Bit Integer Matrix Multiply extension (i8mm). Some multilibs may be | |
731 | incompatible with these options. | |
732 | ||
733 | ``arm_v8_1m_mve_ok`` | |
734 | ARM target supports options to generate instructions from ARMv8.1-M with | |
735 | the M-Profile Vector Extension (MVE). Some multilibs may be incompatible | |
736 | with these options. | |
737 | ||
738 | ``arm_v8_1m_mve_fp_ok`` | |
739 | ARM target supports options to generate instructions from ARMv8.1-M with | |
740 | the Half-precision floating-point instructions (HP), Floating-point Extension | |
741 | (FP) along with M-Profile Vector Extension (MVE). Some multilibs may be | |
742 | incompatible with these options. | |
743 | ||
744 | ``arm_mve_hw`` | |
745 | Test system supports executing MVE instructions. | |
746 | ||
747 | ``arm_v8m_main_cde`` | |
748 | ARM target supports options to generate instructions from ARMv8-M with | |
749 | the Custom Datapath Extension (CDE). Some multilibs may be incompatible | |
750 | with these options. | |
751 | ||
752 | ``arm_v8m_main_cde_fp`` | |
753 | ARM target supports options to generate instructions from ARMv8-M with | |
754 | the Custom Datapath Extension (CDE) and floating-point (VFP). | |
755 | Some multilibs may be incompatible with these options. | |
756 | ||
757 | ``arm_v8_1m_main_cde_mve`` | |
758 | ARM target supports options to generate instructions from ARMv8.1-M with | |
759 | the Custom Datapath Extension (CDE) and M-Profile Vector Extension (MVE). | |
760 | Some multilibs may be incompatible with these options. | |
761 | ||
762 | ``arm_prefer_ldrd_strd`` | |
763 | ARM target prefers ``LDRD`` and ``STRD`` instructions over | |
764 | ``LDM`` and ``STM`` instructions. | |
765 | ||
766 | ``arm_thumb1_movt_ok`` | |
767 | ARM target generates Thumb-1 code for ``-mthumb`` with ``MOVW`` | |
768 | and ``MOVT`` instructions available. | |
769 | ||
770 | ``arm_thumb1_cbz_ok`` | |
771 | ARM target generates Thumb-1 code for ``-mthumb`` with | |
772 | ``CBZ`` and ``CBNZ`` instructions available. | |
773 | ||
774 | ``arm_divmod_simode`` | |
775 | ARM target for which divmod transform is disabled, if it supports hardware | |
776 | div instruction. | |
777 | ||
778 | ``arm_cmse_ok`` | |
779 | ARM target supports ARMv8-M Security Extensions, enabled by the ``-mcmse`` | |
780 | option. | |
781 | ||
782 | ``arm_cmse_hw`` | |
783 | Test system supports executing CMSE instructions. | |
784 | ||
785 | .. _arm_coproc1_ok: | |
786 | ||
787 | ``arm_coproc1_ok`` | |
788 | ARM target supports the following coprocessor instructions: ``CDP``, | |
789 | ``LDC``, ``STC``, ``MCR`` and ``MRC``. | |
790 | ||
791 | .. _arm_coproc2_ok: | |
792 | ||
793 | ``arm_coproc2_ok`` | |
794 | ARM target supports all the coprocessor instructions also listed as supported | |
795 | in :ref:`_arm_coproc1_ok <arm_coproc1_ok>` in addition to the following: ``CDP2``, ``LDC2``, | |
796 | ``LDC2l``, ``STC2``, ``STC2l``, ``MCR2`` and ``MRC2``. | |
797 | ||
798 | .. _arm_coproc3_ok: | |
799 | ||
800 | ``arm_coproc3_ok`` | |
801 | ARM target supports all the coprocessor instructions also listed as supported | |
802 | in :ref:`arm_coproc2_ok <arm_coproc2_ok>` in addition the following: ``MCRR`` and ``MRRC``. | |
803 | ||
804 | ``arm_coproc4_ok`` | |
805 | ARM target supports all the coprocessor instructions also listed as supported | |
806 | in :ref:`arm_coproc3_ok <arm_coproc3_ok>` in addition the following: ``MCRR2`` and ``MRRC2``. | |
807 | ||
808 | ``arm_simd32_ok`` | |
809 | ARM Target supports options suitable for accessing the SIMD32 intrinsics from | |
810 | ``arm_acle.h``. | |
811 | Some multilibs may be incompatible with these options. | |
812 | ||
813 | ``arm_sat_ok`` | |
814 | ARM Target supports options suitable for accessing the saturation | |
815 | intrinsics from ``arm_acle.h``. | |
816 | Some multilibs may be incompatible with these options. | |
817 | ||
818 | .. _arm_dsp_ok: | |
819 | ||
820 | ``arm_dsp_ok`` | |
821 | ARM Target supports options suitable for accessing the DSP intrinsics | |
822 | from ``arm_acle.h``. | |
823 | Some multilibs may be incompatible with these options. | |
824 | ||
825 | ``arm_softfp_ok`` | |
826 | ARM target supports the ``-mfloat-abi=softfp`` option. | |
827 | ||
828 | ``arm_hard_ok`` | |
829 | ARM target supports the ``-mfloat-abi=hard`` option. | |
830 | ||
831 | ||
832 | .. _arm_mve: | |
833 | ||
834 | ``arm_mve`` | |
835 | ARM target supports generating MVE instructions. | |
836 | ||
837 | ``arm_v8_1_lob_ok`` | |
838 | ARM Target supports executing the Armv8.1-M Mainline Low Overhead Loop | |
839 | instructions ``DLS`` and ``LE``. | |
840 | Some multilibs may be incompatible with these options. | |
841 | ||
842 | ``arm_thumb2_no_arm_v8_1_lob`` | |
843 | ARM target where Thumb-2 is used without options but does not support | |
844 | executing the Armv8.1-M Mainline Low Overhead Loop instructions | |
845 | ``DLS`` and ``LE``. | |
846 | ||
847 | ``arm_thumb2_ok_no_arm_v8_1_lob`` | |
848 | ARM target generates Thumb-2 code for ``-mthumb`` but does not | |
849 | support executing the Armv8.1-M Mainline Low Overhead Loop | |
850 | instructions ``DLS`` and ``LE``. | |
851 | ||
852 | AArch64-specific attributes | |
853 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
854 | ||
855 | ``aarch64_asm_<ext>_ok`` | |
856 | AArch64 assembler supports the architecture extension ``ext`` via the | |
857 | ``.arch_extension`` pseudo-op. | |
858 | ||
859 | ``aarch64_tiny`` | |
860 | AArch64 target which generates instruction sequences for tiny memory model. | |
861 | ||
862 | ``aarch64_small`` | |
863 | AArch64 target which generates instruction sequences for small memory model. | |
864 | ||
865 | ``aarch64_large`` | |
866 | AArch64 target which generates instruction sequences for large memory model. | |
867 | ||
868 | ``aarch64_little_endian`` | |
869 | AArch64 target which generates instruction sequences for little endian. | |
870 | ||
871 | ``aarch64_big_endian`` | |
872 | AArch64 target which generates instruction sequences for big endian. | |
873 | ||
874 | ``aarch64_small_fpic`` | |
875 | Binutils installed on test system supports relocation types required by -fpic | |
876 | for AArch64 small memory model. | |
877 | ||
878 | ``aarch64_sve_hw`` | |
879 | AArch64 target that is able to generate and execute SVE code (regardless of | |
880 | whether it does so by default). | |
881 | ||
882 | ``aarch64_sve128_hw`` ``aarch64_sve256_hw`` ``aarch64_sve512_hw`` ``aarch64_sve1024_hw`` ``aarch64_sve2048_hw`` | |
883 | Like ``aarch64_sve_hw``, but also test for an exact hardware vector length. | |
884 | ||
885 | ``aarch64_fjcvtzs_hw`` | |
886 | AArch64 target that is able to generate and execute armv8.3-a FJCVTZS | |
887 | instruction. | |
888 | ||
889 | MIPS-specific attributes | |
890 | ~~~~~~~~~~~~~~~~~~~~~~~~ | |
891 | ||
892 | ``mips64`` | |
893 | MIPS target supports 64-bit instructions. | |
894 | ||
895 | ``nomips16`` | |
896 | MIPS target does not produce MIPS16 code. | |
897 | ||
898 | ``mips16_attribute`` | |
899 | MIPS target can generate MIPS16 code. | |
900 | ||
901 | ``mips_loongson`` | |
902 | MIPS target is a Loongson-2E or -2F target using an ABI that supports | |
903 | the Loongson vector modes. | |
904 | ||
905 | ``mips_msa`` | |
906 | MIPS target supports ``-mmsa``, MIPS SIMD Architecture (MSA). | |
907 | ||
908 | ``mips_newabi_large_long_double`` | |
909 | MIPS target supports ``long double`` larger than ``double`` | |
910 | when using the new ABI. | |
911 | ||
912 | ``mpaired_single`` | |
913 | MIPS target supports ``-mpaired-single``. | |
914 | ||
915 | MSP430-specific attributes | |
916 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
917 | ||
918 | ``msp430_small`` | |
919 | MSP430 target has the small memory model enabled (``-msmall``). | |
920 | ||
921 | ``msp430_large`` | |
922 | MSP430 target has the large memory model enabled (``-mlarge``). | |
923 | ||
924 | PowerPC-specific attributes | |
925 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
926 | ||
927 | ``dfp_hw`` | |
928 | PowerPC target supports executing hardware DFP instructions. | |
929 | ||
930 | ``p8vector_hw`` | |
931 | PowerPC target supports executing VSX instructions (ISA 2.07). | |
932 | ||
933 | ``powerpc64`` | |
934 | Test system supports executing 64-bit instructions. | |
935 | ||
936 | ``powerpc_altivec`` | |
937 | PowerPC target supports AltiVec. | |
938 | ||
939 | ``powerpc_altivec_ok`` | |
940 | PowerPC target supports ``-maltivec``. | |
941 | ||
942 | ``powerpc_eabi_ok`` | |
943 | PowerPC target supports ``-meabi``. | |
944 | ||
945 | ``powerpc_elfv2`` | |
946 | PowerPC target supports ``-mabi=elfv2``. | |
947 | ||
948 | ``powerpc_fprs`` | |
949 | PowerPC target supports floating-point registers. | |
950 | ||
951 | ``powerpc_hard_double`` | |
952 | PowerPC target supports hardware double-precision floating-point. | |
953 | ||
954 | ``powerpc_htm_ok`` | |
955 | PowerPC target supports ``-mhtm`` | |
956 | ||
957 | ``powerpc_p8vector_ok`` | |
958 | PowerPC target supports ``-mpower8-vector`` | |
959 | ||
960 | ``powerpc_popcntb_ok`` | |
961 | PowerPC target supports the ``popcntb`` instruction, indicating | |
962 | that this target supports ``-mcpu=power5``. | |
963 | ||
964 | ``powerpc_ppu_ok`` | |
965 | PowerPC target supports ``-mcpu=cell``. | |
966 | ||
967 | ``powerpc_spe`` | |
968 | PowerPC target supports PowerPC SPE. | |
969 | ||
970 | ``powerpc_spe_nocache`` | |
971 | Including the options used to compile this particular test, the | |
972 | PowerPC target supports PowerPC SPE. | |
973 | ||
974 | ``powerpc_spu`` | |
975 | PowerPC target supports PowerPC SPU. | |
976 | ||
977 | ``powerpc_vsx_ok`` | |
978 | PowerPC target supports ``-mvsx``. | |
979 | ||
980 | ``powerpc_405_nocache`` | |
981 | Including the options used to compile this particular test, the | |
982 | PowerPC target supports PowerPC 405. | |
983 | ||
984 | ``ppc_recip_hw`` | |
985 | PowerPC target supports executing reciprocal estimate instructions. | |
986 | ||
987 | ``vmx_hw`` | |
988 | PowerPC target supports executing AltiVec instructions. | |
989 | ||
990 | ``vsx_hw`` | |
991 | PowerPC target supports executing VSX instructions (ISA 2.06). | |
992 | ||
993 | ``has_arch_pwr5`` | |
994 | PowerPC target pre-defines macro _ARCH_PWR5 which means the ``-mcpu`` | |
995 | setting is Power5 or later. | |
996 | ||
997 | ``has_arch_pwr6`` | |
998 | PowerPC target pre-defines macro _ARCH_PWR6 which means the ``-mcpu`` | |
999 | setting is Power6 or later. | |
1000 | ||
1001 | ``has_arch_pwr7`` | |
1002 | PowerPC target pre-defines macro _ARCH_PWR7 which means the ``-mcpu`` | |
1003 | setting is Power7 or later. | |
1004 | ||
1005 | ``has_arch_pwr8`` | |
1006 | PowerPC target pre-defines macro _ARCH_PWR8 which means the ``-mcpu`` | |
1007 | setting is Power8 or later. | |
1008 | ||
1009 | ``has_arch_pwr9`` | |
1010 | PowerPC target pre-defines macro _ARCH_PWR9 which means the ``-mcpu`` | |
1011 | setting is Power9 or later. | |
1012 | ||
1013 | RISC-V specific attributes | |
1014 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
1015 | ||
1016 | ``rv32`` | |
1017 | Test system has an integer register width of 32 bits. | |
1018 | ||
1019 | ``rv64`` | |
1020 | Test system has an integer register width of 64 bits. | |
1021 | ||
1022 | Other hardware attributes | |
1023 | ~~~~~~~~~~~~~~~~~~~~~~~~~ | |
1024 | ||
1025 | .. Please keep this table sorted alphabetically. | |
1026 | ||
1027 | ``autoincdec`` | |
1028 | Target supports autoincrement/decrement addressing. | |
1029 | ||
1030 | ``avx`` | |
1031 | Target supports compiling ``avx`` instructions. | |
1032 | ||
1033 | ``avx_runtime`` | |
1034 | Target supports the execution of ``avx`` instructions. | |
1035 | ||
1036 | ``avx2`` | |
1037 | Target supports compiling ``avx2`` instructions. | |
1038 | ||
1039 | ``avx2_runtime`` | |
1040 | Target supports the execution of ``avx2`` instructions. | |
1041 | ||
1042 | ``avxvnni`` | |
1043 | Target supports the execution of ``avxvnni`` instructions. | |
1044 | ||
1045 | ``avx512f`` | |
1046 | Target supports compiling ``avx512f`` instructions. | |
1047 | ||
1048 | ``avx512f_runtime`` | |
1049 | Target supports the execution of ``avx512f`` instructions. | |
1050 | ||
1051 | ``avx512vp2intersect`` | |
1052 | Target supports the execution of ``avx512vp2intersect`` instructions. | |
1053 | ||
1054 | ``avxifma`` | |
1055 | Target supports the execution of ``avxifma`` instructions. | |
1056 | ||
1057 | ``avxneconvert`` | |
1058 | Target supports the execution of ``avxneconvert`` instructions. | |
1059 | ||
1060 | ``avxvnniint8`` | |
1061 | Target supports the execution of ``avxvnniint8`` instructions. | |
1062 | ||
1063 | ``amx_tile`` | |
1064 | Target supports the execution of ``amx-tile`` instructions. | |
1065 | ||
1066 | ``amx_int8`` | |
1067 | Target supports the execution of ``amx-int8`` instructions. | |
1068 | ||
1069 | ``amx_bf16`` | |
1070 | Target supports the execution of ``amx-bf16`` instructions. | |
1071 | ||
1072 | ``amx_fp16`` | |
1073 | Target supports the execution of ``amx-fp16`` instructions. | |
1074 | ||
1075 | ``cell_hw`` | |
1076 | Test system can execute AltiVec and Cell PPU instructions. | |
1077 | ||
1078 | ``cmpccxadd`` | |
1079 | Target supports the execution of ``cmpccxadd`` instructions. | |
1080 | ||
1081 | ``coldfire_fpu`` | |
1082 | Target uses a ColdFire FPU. | |
1083 | ||
1084 | ``divmod`` | |
1085 | Target supporting hardware divmod insn or divmod libcall. | |
1086 | ||
1087 | ``divmod_simode`` | |
1088 | Target supporting hardware divmod insn or divmod libcall for SImode. | |
1089 | ||
1090 | ``hard_float`` | |
1091 | Target supports FPU instructions. | |
1092 | ||
1093 | ``non_strict_align`` | |
1094 | Target does not require strict alignment. | |
1095 | ||
1096 | ``pie_copyreloc`` | |
1097 | The x86-64 target linker supports PIE with copy reloc. | |
1098 | ||
1099 | ``prefetchi`` | |
1100 | Target supports the execution of ``prefetchi`` instructions. | |
1101 | ||
1102 | ``raoint`` | |
1103 | Target supports the execution of ``raoint`` instructions. | |
1104 | ||
1105 | ``rdrand`` | |
1106 | Target supports x86 ``rdrand`` instruction. | |
1107 | ||
1108 | ``sqrt_insn`` | |
1109 | Target has a square root instruction that the compiler can generate. | |
1110 | ||
1111 | ``sse`` | |
1112 | Target supports compiling ``sse`` instructions. | |
1113 | ||
1114 | ``sse_runtime`` | |
1115 | Target supports the execution of ``sse`` instructions. | |
1116 | ||
1117 | ``sse2`` | |
1118 | Target supports compiling ``sse2`` instructions. | |
1119 | ||
1120 | ``sse2_runtime`` | |
1121 | Target supports the execution of ``sse2`` instructions. | |
1122 | ||
1123 | ``sync_char_short`` | |
1124 | Target supports atomic operations on ``char`` and ``short``. | |
1125 | ||
1126 | ``sync_int_long`` | |
1127 | Target supports atomic operations on ``int`` and ``long``. | |
1128 | ||
1129 | ``ultrasparc_hw`` | |
1130 | Test environment appears to run executables on a simulator that | |
1131 | accepts only ``EM_SPARC`` executables and chokes on ``EM_SPARC32PLUS`` | |
1132 | or ``EM_SPARCV9`` executables. | |
1133 | ||
1134 | ``vect_cmdline_needed`` | |
1135 | Target requires a command line argument to enable a SIMD instruction set. | |
1136 | ||
1137 | ``xorsign`` | |
1138 | Target supports the xorsign optab expansion. | |
1139 | ||
1140 | Environment attributes | |
1141 | ~~~~~~~~~~~~~~~~~~~~~~ | |
1142 | ||
1143 | ``c`` | |
1144 | The language for the compiler under test is C. | |
1145 | ||
1146 | ``c++`` | |
1147 | The language for the compiler under test is C++. | |
1148 | ||
1149 | ``c99_runtime`` | |
1150 | Target provides a full C99 runtime. | |
1151 | ||
1152 | ``correct_iso_cpp_string_wchar_protos`` | |
1153 | Target ``string.h`` and ``wchar.h`` headers provide C++ required | |
1154 | overloads for ``strchr`` etc. functions. | |
1155 | ||
1156 | ``d_runtime`` | |
1157 | Target provides the D runtime. | |
1158 | ||
1159 | ``d_runtime_has_std_library`` | |
1160 | Target provides the D standard library (Phobos). | |
1161 | ||
1162 | ``dummy_wcsftime`` | |
1163 | Target uses a dummy ``wcsftime`` function that always returns zero. | |
1164 | ||
1165 | ``fd_truncate`` | |
1166 | Target can truncate a file from a file descriptor, as used by | |
1167 | :samp:`libgfortran/io/unix.c:fd_truncate`; i.e. ``ftruncate`` or | |
1168 | ``chsize``. | |
1169 | ||
1170 | ``fenv`` | |
1171 | Target provides :samp:`fenv.h` include file. | |
1172 | ||
1173 | ``fenv_exceptions`` | |
1174 | Target supports :samp:`fenv.h` with all the standard IEEE exceptions | |
1175 | and floating-point exceptions are raised by arithmetic operations. | |
1176 | ||
1177 | ``fenv_exceptions_dfp`` | |
1178 | Target supports :samp:`fenv.h` with all the standard IEEE exceptions | |
1179 | and floating-point exceptions are raised by arithmetic operations for | |
1180 | decimal floating point. | |
1181 | ||
1182 | ``fileio`` | |
1183 | Target offers such file I/O library functions as ``fopen``, | |
1184 | ``fclose``, ``tmpnam``, and ``remove``. This is a link-time | |
1185 | requirement for the presence of the functions in the library; even if | |
1186 | they fail at runtime, the requirement is still regarded as satisfied. | |
1187 | ||
1188 | ``freestanding`` | |
1189 | Target is :samp:`freestanding` as defined in section 4 of the C99 standard. | |
1190 | Effectively, it is a target which supports no extra headers or libraries | |
1191 | other than what is considered essential. | |
1192 | ||
1193 | ``gettimeofday`` | |
1194 | Target supports ``gettimeofday``. | |
1195 | ||
1196 | ``init_priority`` | |
1197 | Target supports constructors with initialization priority arguments. | |
1198 | ||
1199 | ``inttypes_types`` | |
1200 | Target has the basic signed and unsigned types in ``inttypes.h``. | |
1201 | This is for tests that GCC's notions of these types agree with those | |
1202 | in the header, as some systems have only ``inttypes.h``. | |
1203 | ||
1204 | ``lax_strtofp`` | |
1205 | Target might have errors of a few ULP in string to floating-point | |
1206 | conversion functions and overflow is not always detected correctly by | |
1207 | those functions. | |
1208 | ||
1209 | ``mempcpy`` | |
1210 | Target provides ``mempcpy`` function. | |
1211 | ||
1212 | ``mmap`` | |
1213 | Target supports ``mmap``. | |
1214 | ||
1215 | ``newlib`` | |
1216 | Target supports Newlib. | |
1217 | ||
1218 | ``newlib_nano_io`` | |
1219 | GCC was configured with ``--enable-newlib-nano-formatted-io``, which reduces | |
1220 | the code size of Newlib formatted I/O functions. | |
1221 | ||
1222 | ``pow10`` | |
1223 | Target provides ``pow10`` function. | |
1224 | ||
1225 | ``pthread`` | |
1226 | Target can compile using ``pthread.h`` with no errors or warnings. | |
1227 | ||
1228 | ``pthread_h`` | |
1229 | Target has ``pthread.h``. | |
1230 | ||
1231 | ``run_expensive_tests`` | |
1232 | Expensive testcases (usually those that consume excessive amounts of CPU | |
1233 | time) should be run on this target. This can be enabled by setting the | |
1234 | :envvar:`GCC_TEST_RUN_EXPENSIVE` environment variable to a non-empty string. | |
1235 | ||
1236 | ``simulator`` | |
1237 | Test system runs executables on a simulator (i.e. slowly) rather than | |
1238 | hardware (i.e. fast). | |
1239 | ||
1240 | ``signal`` | |
1241 | Target has ``signal.h``. | |
1242 | ||
1243 | ``stabs`` | |
1244 | Target supports the stabs debugging format. | |
1245 | ||
1246 | ``stdint_types`` | |
1247 | Target has the basic signed and unsigned C types in ``stdint.h``. | |
1248 | This will be obsolete when GCC ensures a working ``stdint.h`` for | |
1249 | all targets. | |
1250 | ||
1251 | ``stdint_types_mbig_endian`` | |
1252 | Target accepts the option :option:`-mbig-endian` and ``stdint.h`` | |
1253 | can be included without error when :option:`-mbig-endian` is passed. | |
1254 | ||
1255 | ``stpcpy`` | |
1256 | Target provides ``stpcpy`` function. | |
1257 | ||
1258 | ``sysconf`` | |
1259 | Target supports ``sysconf``. | |
1260 | ||
1261 | ``trampolines`` | |
1262 | Target supports trampolines. | |
1263 | ||
1264 | ``two_plus_gigs`` | |
1265 | Target supports linking programs with 2+GiB of data. | |
1266 | ||
1267 | ``uclibc`` | |
1268 | Target supports uClibc. | |
1269 | ||
1270 | ``unwrapped`` | |
1271 | Target does not use a status wrapper. | |
1272 | ||
1273 | ``vxworks_kernel`` | |
1274 | Target is a VxWorks kernel. | |
1275 | ||
1276 | ``vxworks_rtp`` | |
1277 | Target is a VxWorks RTP. | |
1278 | ||
1279 | ``wchar`` | |
1280 | Target supports wide characters. | |
1281 | ||
1282 | Other attributes | |
1283 | ~~~~~~~~~~~~~~~~ | |
1284 | ||
1285 | ``R_flag_in_section`` | |
1286 | Target supports the 'R' flag in .section directive in assembly inputs. | |
1287 | ||
1288 | ``automatic_stack_alignment`` | |
1289 | Target supports automatic stack alignment. | |
1290 | ||
1291 | ``branch_cost`` | |
1292 | Target supports :option:`-branch-cost=N`. | |
1293 | ||
1294 | ``cxa_atexit`` | |
1295 | Target uses ``__cxa_atexit``. | |
1296 | ||
1297 | .. _default_packed: | |
1298 | ||
1299 | ``default_packed`` | |
1300 | Target has packed layout of structure members by default. | |
1301 | ||
1302 | ``exceptions`` | |
1303 | Target supports exceptions. | |
1304 | ||
1305 | ``exceptions_enabled`` | |
1306 | Target supports exceptions and they are enabled in the current | |
1307 | testing configuration. | |
1308 | ||
1309 | ``fgraphite`` | |
1310 | Target supports Graphite optimizations. | |
1311 | ||
1312 | ``fixed_point`` | |
1313 | Target supports fixed-point extension to C. | |
1314 | ||
1315 | ``fopenacc`` | |
1316 | Target supports OpenACC via :option:`-fopenacc`. | |
1317 | ||
1318 | ``fopenmp`` | |
1319 | Target supports OpenMP via :option:`-fopenmp`. | |
1320 | ||
1321 | ``fpic`` | |
1322 | Target supports :option:`-fpic` and :option:`-fPIC`. | |
1323 | ||
1324 | ``freorder`` | |
1325 | Target supports :option:`-freorder-blocks-and-partition`. | |
1326 | ||
1327 | ``fstack_protector`` | |
1328 | Target supports :option:`-fstack-protector`. | |
1329 | ||
1330 | ``gas`` | |
1331 | Target uses GNU :command:`as`. | |
1332 | ||
1333 | ``gc_sections`` | |
1334 | Target supports :option:`--gc-sections`. | |
1335 | ||
1336 | ``gld`` | |
1337 | Target uses GNU :command:`ld`. | |
1338 | ||
1339 | ``keeps_null_pointer_checks`` | |
1340 | Target keeps null pointer checks, either due to the use of | |
1341 | :option:`-fno-delete-null-pointer-checks` or hardwired into the target. | |
1342 | ||
1343 | ``llvm_binutils`` | |
1344 | Target is using an LLVM assembler and/or linker, instead of GNU Binutils. | |
1345 | ||
1346 | ``lra`` | |
1347 | Target supports local register allocator (LRA). | |
1348 | ||
1349 | ``lto`` | |
1350 | Compiler has been configured to support link-time optimization (LTO). | |
1351 | ||
1352 | ``lto_incremental`` | |
1353 | Compiler and linker support link-time optimization relocatable linking | |
1354 | with :option:`-r` and :option:`-flto` options. | |
1355 | ||
1356 | ``naked_functions`` | |
1357 | Target supports the ``naked`` function attribute. | |
1358 | ||
1359 | ``named_sections`` | |
1360 | Target supports named sections. | |
1361 | ||
1362 | ``natural_alignment_32`` | |
1363 | Target uses natural alignment (aligned to type size) for types of | |
1364 | 32 bits or less. | |
1365 | ||
1366 | ``target_natural_alignment_64`` | |
1367 | Target uses natural alignment (aligned to type size) for types of | |
1368 | 64 bits or less. | |
1369 | ||
1370 | ``no_alignment_constraints`` | |
1371 | Target defines __BIGGEST_ALIGNMENT__=1. Hence target imposes | |
1372 | no alignment constraints. This is similar, but not necessarily | |
1373 | the same as :ref:`default_packed`. Although ``BIGGEST_FIELD_ALIGNMENT`` | |
1374 | defaults to ``BIGGEST_ALIGNMENT`` for most targets, it is possible | |
1375 | for a target to set those two with different values and have different | |
1376 | alignment constraints for aggregate and non-aggregate types. | |
1377 | ||
1378 | ``noinit`` | |
1379 | Target supports the ``noinit`` variable attribute. | |
1380 | ||
1381 | ``nonpic`` | |
1382 | Target does not generate PIC by default. | |
1383 | ||
1384 | ``o_flag_in_section`` | |
1385 | Target supports the 'o' flag in .section directive in assembly inputs. | |
1386 | ||
1387 | ``offload_gcn`` | |
1388 | Target has been configured for OpenACC/OpenMP offloading on AMD GCN. | |
1389 | ||
1390 | ``persistent`` | |
1391 | Target supports the ``persistent`` variable attribute. | |
1392 | ||
1393 | ``pie_enabled`` | |
1394 | Target generates PIE by default. | |
1395 | ||
1396 | ``pcc_bitfield_type_matters`` | |
1397 | Target defines ``PCC_BITFIELD_TYPE_MATTERS``. | |
1398 | ||
1399 | ``pe_aligned_commons`` | |
1400 | Target supports :option:`-mpe-aligned-commons`. | |
1401 | ||
1402 | ``pie`` | |
1403 | Target supports :option:`-pie`, :option:`-fpie` and :option:`-fPIE`. | |
1404 | ||
1405 | ``rdynamic`` | |
1406 | Target supports :option:`-rdynamic`. | |
1407 | ||
1408 | ``scalar_all_fma`` | |
1409 | Target supports all four fused multiply-add optabs for both ``float`` | |
1410 | and ``double``. These optabs are: ``fma_optab``, ``fms_optab``, | |
1411 | ``fnma_optab`` and ``fnms_optab``. | |
1412 | ||
1413 | ``section_anchors`` | |
1414 | Target supports section anchors. | |
1415 | ||
1416 | ``short_enums`` | |
1417 | Target defaults to short enums. | |
1418 | ||
1419 | .. _stack_size_et: | |
1420 | ||
1421 | ``stack_size`` | |
1422 | Target has limited stack size. The stack size limit can be obtained using the | |
1423 | STACK_SIZE macro defined by :ref:`stack_size_ao`. | |
1424 | ||
1425 | ``static`` | |
1426 | Target supports :option:`-static`. | |
1427 | ||
1428 | ``static_libgfortran`` | |
1429 | Target supports statically linking :samp:`libgfortran`. | |
1430 | ||
1431 | ``string_merging`` | |
1432 | Target supports merging string constants at link time. | |
1433 | ||
1434 | ``ucn`` | |
1435 | Target supports compiling and assembling UCN. | |
1436 | ||
1437 | ``ucn_nocache`` | |
1438 | Including the options used to compile this particular test, the | |
1439 | target supports compiling and assembling UCN. | |
1440 | ||
1441 | ``unaligned_stack`` | |
1442 | Target does not guarantee that its ``STACK_BOUNDARY`` is greater than | |
1443 | or equal to the required vector alignment. | |
1444 | ||
1445 | ``vector_alignment_reachable`` | |
1446 | Vector alignment is reachable for types of 32 bits or less. | |
1447 | ||
1448 | ``vector_alignment_reachable_for_64bit`` | |
1449 | Vector alignment is reachable for types of 64 bits or less. | |
1450 | ||
1451 | ``vma_equals_lma`` | |
1452 | Target generates executable with VMA equal to LMA for .data section. | |
1453 | ||
1454 | ``wchar_t_char16_t_compatible`` | |
1455 | Target supports ``wchar_t`` that is compatible with ``char16_t``. | |
1456 | ||
1457 | ``wchar_t_char32_t_compatible`` | |
1458 | Target supports ``wchar_t`` that is compatible with ``char32_t``. | |
1459 | ||
1460 | ``comdat_group`` | |
1461 | Target uses comdat groups. | |
1462 | ||
1463 | ``indirect_calls`` | |
1464 | Target supports indirect calls, i.e. calls where the target is not | |
1465 | constant. | |
1466 | ||
1467 | ``lgccjit`` | |
1468 | Target supports -lgccjit, i.e. libgccjit.so can be linked into jit tests. | |
1469 | ||
1470 | ``__OPTIMIZE__`` | |
1471 | Optimizations are enabled (``__OPTIMIZE__``) per the current | |
1472 | compiler flags. | |
1473 | ||
1474 | Local to tests in gcc.target/i386 | |
1475 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
1476 | ||
1477 | ``3dnow`` | |
1478 | Target supports compiling ``3dnow`` instructions. | |
1479 | ||
1480 | ``aes`` | |
1481 | Target supports compiling ``aes`` instructions. | |
1482 | ||
1483 | ``fma4`` | |
1484 | Target supports compiling ``fma4`` instructions. | |
1485 | ||
1486 | ``mfentry`` | |
1487 | Target supports the ``-mfentry`` option that alters the | |
1488 | position of profiling calls such that they precede the prologue. | |
1489 | ||
1490 | ``ms_hook_prologue`` | |
1491 | Target supports attribute ``ms_hook_prologue``. | |
1492 | ||
1493 | ``pclmul`` | |
1494 | Target supports compiling ``pclmul`` instructions. | |
1495 | ||
1496 | ``sse3`` | |
1497 | Target supports compiling ``sse3`` instructions. | |
1498 | ||
1499 | ``sse4`` | |
1500 | Target supports compiling ``sse4`` instructions. | |
1501 | ||
1502 | ``sse4a`` | |
1503 | Target supports compiling ``sse4a`` instructions. | |
1504 | ||
1505 | ``ssse3`` | |
1506 | Target supports compiling ``ssse3`` instructions. | |
1507 | ||
1508 | ``vaes`` | |
1509 | Target supports compiling ``vaes`` instructions. | |
1510 | ||
1511 | ``vpclmul`` | |
1512 | Target supports compiling ``vpclmul`` instructions. | |
1513 | ||
1514 | ``xop`` | |
1515 | Target supports compiling ``xop`` instructions. | |
1516 | ||
1517 | Local to tests in gcc.test-framework | |
1518 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
1519 | ||
1520 | ``no`` | |
1521 | Always returns 0. | |
1522 | ||
1523 | ``yes`` | |
3ed1b4ce | 1524 | Always returns 1. |