]>
Commit | Line | Data |
---|---|---|
9d19df75 MS |
1 | /* Native-dependent code for GNU/Linux AArch64. |
2 | ||
213516ef | 3 | Copyright (C) 2011-2023 Free Software Foundation, Inc. |
9d19df75 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
d55e5aa6 | 23 | #include "inferior.h" |
4de283e4 TT |
24 | #include "gdbcore.h" |
25 | #include "regcache.h" | |
d55e5aa6 | 26 | #include "linux-nat.h" |
4de283e4 TT |
27 | #include "target-descriptions.h" |
28 | #include "auxv.h" | |
29 | #include "gdbcmd.h" | |
1570c37c | 30 | #include "aarch64-nat.h" |
4de283e4 TT |
31 | #include "aarch64-tdep.h" |
32 | #include "aarch64-linux-tdep.h" | |
33 | #include "aarch32-linux-nat.h" | |
d105cce5 | 34 | #include "aarch32-tdep.h" |
350fab54 | 35 | #include "arch/arm.h" |
d55e5aa6 | 36 | #include "nat/aarch64-linux.h" |
4de283e4 | 37 | #include "nat/aarch64-linux-hw-point.h" |
ba2d2bb2 | 38 | #include "nat/aarch64-sve-linux-ptrace.h" |
4de283e4 TT |
39 | |
40 | #include "elf/external.h" | |
41 | #include "elf/common.h" | |
42 | ||
5826e159 | 43 | #include "nat/gdb_ptrace.h" |
4de283e4 TT |
44 | #include <sys/utsname.h> |
45 | #include <asm/ptrace.h> | |
46 | ||
47 | #include "gregset.h" | |
48 | #include "linux-tdep.h" | |
396d2e56 | 49 | #include "arm-tdep.h" |
9d19df75 | 50 | |
9d19df75 MS |
51 | /* Defines ps_err_e, struct ps_prochandle. */ |
52 | #include "gdb_proc_service.h" | |
4da037ef | 53 | #include "arch-utils.h" |
9d19df75 | 54 | |
04245125 LM |
55 | #include "arch/aarch64-mte-linux.h" |
56 | ||
4601818e LM |
57 | #include "nat/aarch64-mte-linux-ptrace.h" |
58 | ||
9d19df75 MS |
59 | #ifndef TRAP_HWBKPT |
60 | #define TRAP_HWBKPT 0x0004 | |
61 | #endif | |
62 | ||
1570c37c JB |
63 | class aarch64_linux_nat_target final |
64 | : public aarch64_nat_target<linux_nat_target> | |
f6ac5f3d PA |
65 | { |
66 | public: | |
67 | /* Add our register access methods. */ | |
68 | void fetch_registers (struct regcache *, int) override; | |
69 | void store_registers (struct regcache *, int) override; | |
70 | ||
71 | const struct target_desc *read_description () override; | |
72 | ||
73 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
57810aa7 PA |
74 | bool stopped_by_watchpoint () override; |
75 | bool stopped_data_address (CORE_ADDR *) override; | |
f6ac5f3d PA |
76 | |
77 | int can_do_single_step () override; | |
78 | ||
79 | /* Override the GNU/Linux inferior startup hook. */ | |
80 | void post_startup_inferior (ptid_t) override; | |
135340af | 81 | |
8363f9d5 RB |
82 | /* Override the GNU/Linux post attach hook. */ |
83 | void post_attach (int pid) override; | |
84 | ||
135340af PA |
85 | /* These three defer to common nat/ code. */ |
86 | void low_new_thread (struct lwp_info *lp) override | |
87 | { aarch64_linux_new_thread (lp); } | |
88 | void low_delete_thread (struct arch_lwp_info *lp) override | |
89 | { aarch64_linux_delete_thread (lp); } | |
90 | void low_prepare_to_resume (struct lwp_info *lp) override | |
91 | { aarch64_linux_prepare_to_resume (lp); } | |
92 | ||
93 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; | |
94 | void low_forget_process (pid_t pid) override; | |
95 | ||
96 | /* Add our siginfo layout converter. */ | |
97 | bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) | |
98 | override; | |
4da037ef AH |
99 | |
100 | struct gdbarch *thread_architecture (ptid_t) override; | |
4601818e LM |
101 | |
102 | bool supports_memory_tagging () override; | |
103 | ||
104 | /* Read memory allocation tags from memory via PTRACE. */ | |
105 | bool fetch_memtags (CORE_ADDR address, size_t len, | |
106 | gdb::byte_vector &tags, int type) override; | |
107 | ||
108 | /* Write allocation tags to memory via PTRACE. */ | |
109 | bool store_memtags (CORE_ADDR address, size_t len, | |
110 | const gdb::byte_vector &tags, int type) override; | |
f6ac5f3d PA |
111 | }; |
112 | ||
113 | static aarch64_linux_nat_target the_aarch64_linux_nat_target; | |
114 | ||
d6c44983 YZ |
115 | /* Called whenever GDB is no longer debugging process PID. It deletes |
116 | data structures that keep track of debug register state. */ | |
9d19df75 | 117 | |
135340af PA |
118 | void |
119 | aarch64_linux_nat_target::low_forget_process (pid_t pid) | |
9d19df75 | 120 | { |
1570c37c | 121 | aarch64_remove_debug_reg_state (pid); |
9d19df75 MS |
122 | } |
123 | ||
9d19df75 MS |
124 | /* Fill GDB's register array with the general-purpose register values |
125 | from the current thread. */ | |
126 | ||
127 | static void | |
128 | fetch_gregs_from_thread (struct regcache *regcache) | |
129 | { | |
607685ec | 130 | int ret, tid; |
ac7936df | 131 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 MS |
132 | elf_gregset_t regs; |
133 | struct iovec iovec; | |
134 | ||
607685ec YQ |
135 | /* Make sure REGS can hold all registers contents on both aarch64 |
136 | and arm. */ | |
137 | gdb_static_assert (sizeof (regs) >= 18 * 4); | |
138 | ||
e38504b3 | 139 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
140 | |
141 | iovec.iov_base = ®s; | |
607685ec YQ |
142 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
143 | iovec.iov_len = 18 * 4; | |
144 | else | |
145 | iovec.iov_len = sizeof (regs); | |
9d19df75 MS |
146 | |
147 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
148 | if (ret < 0) | |
deb70aa0 | 149 | perror_with_name (_("Unable to fetch general registers")); |
9d19df75 | 150 | |
607685ec YQ |
151 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
152 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1); | |
153 | else | |
154 | { | |
155 | int regno; | |
156 | ||
157 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
73e1c03f | 158 | regcache->raw_supply (regno, ®s[regno - AARCH64_X0_REGNUM]); |
607685ec | 159 | } |
9d19df75 MS |
160 | } |
161 | ||
162 | /* Store to the current thread the valid general-purpose register | |
163 | values in the GDB's register array. */ | |
164 | ||
165 | static void | |
166 | store_gregs_to_thread (const struct regcache *regcache) | |
167 | { | |
607685ec | 168 | int ret, tid; |
9d19df75 MS |
169 | elf_gregset_t regs; |
170 | struct iovec iovec; | |
ac7936df | 171 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 | 172 | |
607685ec YQ |
173 | /* Make sure REGS can hold all registers contents on both aarch64 |
174 | and arm. */ | |
175 | gdb_static_assert (sizeof (regs) >= 18 * 4); | |
e38504b3 | 176 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
177 | |
178 | iovec.iov_base = ®s; | |
607685ec YQ |
179 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
180 | iovec.iov_len = 18 * 4; | |
181 | else | |
182 | iovec.iov_len = sizeof (regs); | |
9d19df75 MS |
183 | |
184 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
185 | if (ret < 0) | |
deb70aa0 | 186 | perror_with_name (_("Unable to fetch general registers")); |
9d19df75 | 187 | |
607685ec YQ |
188 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
189 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1); | |
190 | else | |
191 | { | |
192 | int regno; | |
193 | ||
194 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
0ec9f114 | 195 | if (REG_VALID == regcache->get_register_status (regno)) |
34a79281 | 196 | regcache->raw_collect (regno, ®s[regno - AARCH64_X0_REGNUM]); |
607685ec | 197 | } |
9d19df75 MS |
198 | |
199 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec); | |
200 | if (ret < 0) | |
deb70aa0 | 201 | perror_with_name (_("Unable to store general registers")); |
9d19df75 MS |
202 | } |
203 | ||
204 | /* Fill GDB's register array with the fp/simd register values | |
205 | from the current thread. */ | |
206 | ||
207 | static void | |
208 | fetch_fpregs_from_thread (struct regcache *regcache) | |
209 | { | |
607685ec | 210 | int ret, tid; |
9d19df75 MS |
211 | elf_fpregset_t regs; |
212 | struct iovec iovec; | |
ac7936df | 213 | struct gdbarch *gdbarch = regcache->arch (); |
607685ec YQ |
214 | |
215 | /* Make sure REGS can hold all VFP registers contents on both aarch64 | |
216 | and arm. */ | |
350fab54 | 217 | gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE); |
9d19df75 | 218 | |
e38504b3 | 219 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
220 | |
221 | iovec.iov_base = ®s; | |
9d19df75 | 222 | |
607685ec YQ |
223 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
224 | { | |
350fab54 | 225 | iovec.iov_len = ARM_VFP3_REGS_SIZE; |
607685ec YQ |
226 | |
227 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); | |
228 | if (ret < 0) | |
deb70aa0 | 229 | perror_with_name (_("Unable to fetch VFP registers")); |
607685ec YQ |
230 | |
231 | aarch32_vfp_regcache_supply (regcache, (gdb_byte *) ®s, 32); | |
232 | } | |
233 | else | |
234 | { | |
235 | int regno; | |
236 | ||
237 | iovec.iov_len = sizeof (regs); | |
9d19df75 | 238 | |
607685ec YQ |
239 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); |
240 | if (ret < 0) | |
deb70aa0 | 241 | perror_with_name (_("Unable to fetch vFP/SIMD registers")); |
9d19df75 | 242 | |
607685ec | 243 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) |
73e1c03f | 244 | regcache->raw_supply (regno, ®s.vregs[regno - AARCH64_V0_REGNUM]); |
607685ec | 245 | |
73e1c03f SM |
246 | regcache->raw_supply (AARCH64_FPSR_REGNUM, ®s.fpsr); |
247 | regcache->raw_supply (AARCH64_FPCR_REGNUM, ®s.fpcr); | |
607685ec | 248 | } |
9d19df75 MS |
249 | } |
250 | ||
251 | /* Store to the current thread the valid fp/simd register | |
252 | values in the GDB's register array. */ | |
253 | ||
254 | static void | |
255 | store_fpregs_to_thread (const struct regcache *regcache) | |
256 | { | |
607685ec | 257 | int ret, tid; |
9d19df75 MS |
258 | elf_fpregset_t regs; |
259 | struct iovec iovec; | |
ac7936df | 260 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 | 261 | |
607685ec YQ |
262 | /* Make sure REGS can hold all VFP registers contents on both aarch64 |
263 | and arm. */ | |
350fab54 | 264 | gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE); |
e38504b3 | 265 | tid = regcache->ptid ().lwp (); |
9d19df75 MS |
266 | |
267 | iovec.iov_base = ®s; | |
9d19df75 | 268 | |
607685ec YQ |
269 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
270 | { | |
350fab54 | 271 | iovec.iov_len = ARM_VFP3_REGS_SIZE; |
9d19df75 | 272 | |
607685ec YQ |
273 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
274 | if (ret < 0) | |
deb70aa0 | 275 | perror_with_name (_("Unable to fetch VFP registers")); |
9d19df75 | 276 | |
607685ec YQ |
277 | aarch32_vfp_regcache_collect (regcache, (gdb_byte *) ®s, 32); |
278 | } | |
279 | else | |
280 | { | |
281 | int regno; | |
9d19df75 | 282 | |
607685ec YQ |
283 | iovec.iov_len = sizeof (regs); |
284 | ||
285 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); | |
286 | if (ret < 0) | |
deb70aa0 | 287 | perror_with_name (_("Unable to fetch FP/SIMD registers")); |
607685ec YQ |
288 | |
289 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) | |
0ec9f114 | 290 | if (REG_VALID == regcache->get_register_status (regno)) |
34a79281 SM |
291 | regcache->raw_collect |
292 | (regno, (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); | |
607685ec | 293 | |
0ec9f114 | 294 | if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM)) |
34a79281 | 295 | regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); |
0ec9f114 | 296 | if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM)) |
34a79281 | 297 | regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); |
607685ec YQ |
298 | } |
299 | ||
300 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
301 | { | |
302 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec); | |
303 | if (ret < 0) | |
deb70aa0 | 304 | perror_with_name (_("Unable to store VFP registers")); |
607685ec YQ |
305 | } |
306 | else | |
307 | { | |
308 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec); | |
309 | if (ret < 0) | |
deb70aa0 | 310 | perror_with_name (_("Unable to store FP/SIMD registers")); |
607685ec | 311 | } |
9d19df75 MS |
312 | } |
313 | ||
e9902bfc AH |
314 | /* Fill GDB's register array with the sve register values |
315 | from the current thread. */ | |
316 | ||
317 | static void | |
318 | fetch_sveregs_from_thread (struct regcache *regcache) | |
319 | { | |
320 | std::unique_ptr<gdb_byte[]> base | |
e38504b3 | 321 | = aarch64_sve_get_sveregs (regcache->ptid ().lwp ()); |
e9902bfc AH |
322 | aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ()); |
323 | } | |
324 | ||
325 | /* Store to the current thread the valid sve register | |
326 | values in the GDB's register array. */ | |
327 | ||
328 | static void | |
329 | store_sveregs_to_thread (struct regcache *regcache) | |
330 | { | |
331 | int ret; | |
332 | struct iovec iovec; | |
e38504b3 | 333 | int tid = regcache->ptid ().lwp (); |
e9902bfc | 334 | |
48574d91 AH |
335 | /* First store vector length to the thread. This is done first to ensure the |
336 | ptrace buffers read from the kernel are the correct size. */ | |
337 | if (!aarch64_sve_set_vq (tid, regcache)) | |
deb70aa0 | 338 | perror_with_name (_("Unable to set VG register")); |
48574d91 | 339 | |
e9902bfc AH |
340 | /* Obtain a dump of SVE registers from ptrace. */ |
341 | std::unique_ptr<gdb_byte[]> base = aarch64_sve_get_sveregs (tid); | |
342 | ||
343 | /* Overwrite with regcache state. */ | |
344 | aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ()); | |
345 | ||
346 | /* Write back to the kernel. */ | |
347 | iovec.iov_base = base.get (); | |
348 | iovec.iov_len = ((struct user_sve_header *) base.get ())->size; | |
349 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec); | |
350 | ||
351 | if (ret < 0) | |
352 | perror_with_name (_("Unable to store sve registers")); | |
353 | } | |
354 | ||
76bed0fd AH |
355 | /* Fill GDB's register array with the pointer authentication mask values from |
356 | the current thread. */ | |
357 | ||
358 | static void | |
359 | fetch_pauth_masks_from_thread (struct regcache *regcache) | |
360 | { | |
aa70a99e | 361 | aarch64_gdbarch_tdep *tdep |
08106042 | 362 | = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ()); |
76bed0fd AH |
363 | int ret; |
364 | struct iovec iovec; | |
365 | uint64_t pauth_regset[2] = {0, 0}; | |
366 | int tid = regcache->ptid ().lwp (); | |
367 | ||
368 | iovec.iov_base = &pauth_regset; | |
369 | iovec.iov_len = sizeof (pauth_regset); | |
370 | ||
371 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec); | |
372 | if (ret != 0) | |
deb70aa0 | 373 | perror_with_name (_("unable to fetch pauth registers")); |
76bed0fd AH |
374 | |
375 | regcache->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base), | |
376 | &pauth_regset[0]); | |
377 | regcache->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base), | |
378 | &pauth_regset[1]); | |
379 | } | |
380 | ||
5e984dbf LM |
381 | /* Fill GDB's register array with the MTE register values from |
382 | the current thread. */ | |
383 | ||
384 | static void | |
385 | fetch_mteregs_from_thread (struct regcache *regcache) | |
386 | { | |
aa70a99e | 387 | aarch64_gdbarch_tdep *tdep |
08106042 | 388 | = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ()); |
5e984dbf LM |
389 | int regno = tdep->mte_reg_base; |
390 | ||
391 | gdb_assert (regno != -1); | |
392 | ||
393 | uint64_t tag_ctl = 0; | |
394 | struct iovec iovec; | |
395 | ||
396 | iovec.iov_base = &tag_ctl; | |
397 | iovec.iov_len = sizeof (tag_ctl); | |
398 | ||
399 | int tid = get_ptrace_pid (regcache->ptid ()); | |
400 | if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0) | |
deb70aa0 | 401 | perror_with_name (_("unable to fetch MTE registers")); |
5e984dbf LM |
402 | |
403 | regcache->raw_supply (regno, &tag_ctl); | |
404 | } | |
405 | ||
406 | /* Store to the current thread the valid MTE register set in the GDB's | |
407 | register array. */ | |
408 | ||
409 | static void | |
410 | store_mteregs_to_thread (struct regcache *regcache) | |
411 | { | |
aa70a99e | 412 | aarch64_gdbarch_tdep *tdep |
08106042 | 413 | = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ()); |
5e984dbf LM |
414 | int regno = tdep->mte_reg_base; |
415 | ||
416 | gdb_assert (regno != -1); | |
417 | ||
418 | uint64_t tag_ctl = 0; | |
419 | ||
420 | if (REG_VALID != regcache->get_register_status (regno)) | |
421 | return; | |
422 | ||
423 | regcache->raw_collect (regno, (char *) &tag_ctl); | |
424 | ||
425 | struct iovec iovec; | |
426 | ||
427 | iovec.iov_base = &tag_ctl; | |
428 | iovec.iov_len = sizeof (tag_ctl); | |
429 | ||
430 | int tid = get_ptrace_pid (regcache->ptid ()); | |
431 | if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0) | |
deb70aa0 | 432 | perror_with_name (_("unable to store MTE registers")); |
5e984dbf LM |
433 | } |
434 | ||
3b4b3e43 JB |
435 | /* Fill GDB's register array with the TLS register values from |
436 | the current thread. */ | |
437 | ||
438 | static void | |
439 | fetch_tlsregs_from_thread (struct regcache *regcache) | |
440 | { | |
441 | aarch64_gdbarch_tdep *tdep | |
08106042 | 442 | = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ()); |
ba60b963 | 443 | int regno = tdep->tls_regnum_base; |
3b4b3e43 JB |
444 | |
445 | gdb_assert (regno != -1); | |
ba60b963 | 446 | gdb_assert (tdep->tls_register_count > 0); |
3b4b3e43 | 447 | |
ba60b963 | 448 | uint64_t tpidrs[tdep->tls_register_count] = { 0 }; |
3b4b3e43 | 449 | struct iovec iovec; |
ba60b963 LM |
450 | iovec.iov_base = tpidrs; |
451 | iovec.iov_len = sizeof (tpidrs); | |
3b4b3e43 JB |
452 | |
453 | int tid = get_ptrace_pid (regcache->ptid ()); | |
454 | if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TLS, &iovec) != 0) | |
ba60b963 | 455 | perror_with_name (_("unable to fetch TLS registers")); |
3b4b3e43 | 456 | |
ba60b963 LM |
457 | for (int i = 0; i < tdep->tls_register_count; i++) |
458 | regcache->raw_supply (regno + i, &tpidrs[i]); | |
3b4b3e43 JB |
459 | } |
460 | ||
461 | /* Store to the current thread the valid TLS register set in GDB's | |
462 | register array. */ | |
463 | ||
464 | static void | |
465 | store_tlsregs_to_thread (struct regcache *regcache) | |
466 | { | |
467 | aarch64_gdbarch_tdep *tdep | |
08106042 | 468 | = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ()); |
ba60b963 | 469 | int regno = tdep->tls_regnum_base; |
3b4b3e43 JB |
470 | |
471 | gdb_assert (regno != -1); | |
ba60b963 | 472 | gdb_assert (tdep->tls_register_count > 0); |
3b4b3e43 | 473 | |
ba60b963 | 474 | uint64_t tpidrs[tdep->tls_register_count] = { 0 }; |
3b4b3e43 | 475 | |
ba60b963 LM |
476 | for (int i = 0; i < tdep->tls_register_count; i++) |
477 | { | |
478 | if (REG_VALID != regcache->get_register_status (regno + i)) | |
479 | continue; | |
3b4b3e43 | 480 | |
ba60b963 LM |
481 | regcache->raw_collect (regno + i, (char *) &tpidrs[i]); |
482 | } | |
3b4b3e43 JB |
483 | |
484 | struct iovec iovec; | |
ba60b963 LM |
485 | iovec.iov_base = &tpidrs; |
486 | iovec.iov_len = sizeof (tpidrs); | |
3b4b3e43 JB |
487 | |
488 | int tid = get_ptrace_pid (regcache->ptid ()); | |
489 | if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TLS, &iovec) != 0) | |
deb70aa0 | 490 | perror_with_name (_("unable to store TLS register")); |
3b4b3e43 JB |
491 | } |
492 | ||
396d2e56 AB |
493 | /* The AArch64 version of the "fetch_registers" target_ops method. Fetch |
494 | REGNO from the target and place the result into REGCACHE. */ | |
9d19df75 | 495 | |
396d2e56 AB |
496 | static void |
497 | aarch64_fetch_registers (struct regcache *regcache, int regno) | |
9d19df75 | 498 | { |
aa70a99e | 499 | aarch64_gdbarch_tdep *tdep |
08106042 | 500 | = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ()); |
e9902bfc | 501 | |
9d19df75 MS |
502 | if (regno == -1) |
503 | { | |
504 | fetch_gregs_from_thread (regcache); | |
e9902bfc AH |
505 | if (tdep->has_sve ()) |
506 | fetch_sveregs_from_thread (regcache); | |
507 | else | |
508 | fetch_fpregs_from_thread (regcache); | |
76bed0fd AH |
509 | |
510 | if (tdep->has_pauth ()) | |
511 | fetch_pauth_masks_from_thread (regcache); | |
5e984dbf LM |
512 | |
513 | if (tdep->has_mte ()) | |
514 | fetch_mteregs_from_thread (regcache); | |
3b4b3e43 JB |
515 | |
516 | if (tdep->has_tls ()) | |
517 | fetch_tlsregs_from_thread (regcache); | |
9d19df75 MS |
518 | } |
519 | else if (regno < AARCH64_V0_REGNUM) | |
520 | fetch_gregs_from_thread (regcache); | |
e9902bfc AH |
521 | else if (tdep->has_sve ()) |
522 | fetch_sveregs_from_thread (regcache); | |
9d19df75 MS |
523 | else |
524 | fetch_fpregs_from_thread (regcache); | |
76bed0fd AH |
525 | |
526 | if (tdep->has_pauth ()) | |
527 | { | |
528 | if (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base) | |
529 | || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)) | |
530 | fetch_pauth_masks_from_thread (regcache); | |
531 | } | |
5e984dbf LM |
532 | |
533 | /* Fetch individual MTE registers. */ | |
534 | if (tdep->has_mte () | |
535 | && (regno == tdep->mte_reg_base)) | |
536 | fetch_mteregs_from_thread (regcache); | |
3b4b3e43 | 537 | |
ba60b963 LM |
538 | if (tdep->has_tls () |
539 | && regno >= tdep->tls_regnum_base | |
540 | && regno < tdep->tls_regnum_base + tdep->tls_register_count) | |
3b4b3e43 | 541 | fetch_tlsregs_from_thread (regcache); |
9d19df75 MS |
542 | } |
543 | ||
396d2e56 AB |
544 | /* A version of the "fetch_registers" target_ops method used when running |
545 | 32-bit ARM code on an AArch64 target. Fetch REGNO from the target and | |
546 | place the result into REGCACHE. */ | |
547 | ||
548 | static void | |
549 | aarch32_fetch_registers (struct regcache *regcache, int regno) | |
550 | { | |
551 | arm_gdbarch_tdep *tdep | |
08106042 | 552 | = gdbarch_tdep<arm_gdbarch_tdep> (regcache->arch ()); |
396d2e56 AB |
553 | |
554 | if (regno == -1) | |
555 | { | |
556 | fetch_gregs_from_thread (regcache); | |
557 | if (tdep->vfp_register_count > 0) | |
558 | fetch_fpregs_from_thread (regcache); | |
559 | } | |
560 | else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) | |
561 | fetch_gregs_from_thread (regcache); | |
562 | else if (tdep->vfp_register_count > 0 | |
563 | && regno >= ARM_D0_REGNUM | |
564 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count | |
565 | || regno == ARM_FPSCR_REGNUM)) | |
566 | fetch_fpregs_from_thread (regcache); | |
567 | } | |
568 | ||
569 | /* Implement the "fetch_registers" target_ops method. */ | |
9d19df75 | 570 | |
f6ac5f3d | 571 | void |
396d2e56 | 572 | aarch64_linux_nat_target::fetch_registers (struct regcache *regcache, |
f6ac5f3d | 573 | int regno) |
396d2e56 AB |
574 | { |
575 | if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32) | |
576 | aarch32_fetch_registers (regcache, regno); | |
577 | else | |
578 | aarch64_fetch_registers (regcache, regno); | |
579 | } | |
580 | ||
581 | /* The AArch64 version of the "store_registers" target_ops method. Copy | |
582 | the value of register REGNO from REGCACHE into the the target. */ | |
583 | ||
584 | static void | |
585 | aarch64_store_registers (struct regcache *regcache, int regno) | |
9d19df75 | 586 | { |
aa70a99e | 587 | aarch64_gdbarch_tdep *tdep |
08106042 | 588 | = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ()); |
e9902bfc | 589 | |
9d19df75 MS |
590 | if (regno == -1) |
591 | { | |
592 | store_gregs_to_thread (regcache); | |
e9902bfc AH |
593 | if (tdep->has_sve ()) |
594 | store_sveregs_to_thread (regcache); | |
595 | else | |
596 | store_fpregs_to_thread (regcache); | |
5e984dbf LM |
597 | |
598 | if (tdep->has_mte ()) | |
599 | store_mteregs_to_thread (regcache); | |
3b4b3e43 JB |
600 | |
601 | if (tdep->has_tls ()) | |
602 | store_tlsregs_to_thread (regcache); | |
9d19df75 MS |
603 | } |
604 | else if (regno < AARCH64_V0_REGNUM) | |
605 | store_gregs_to_thread (regcache); | |
e9902bfc AH |
606 | else if (tdep->has_sve ()) |
607 | store_sveregs_to_thread (regcache); | |
9d19df75 MS |
608 | else |
609 | store_fpregs_to_thread (regcache); | |
5e984dbf LM |
610 | |
611 | /* Store MTE registers. */ | |
612 | if (tdep->has_mte () | |
613 | && (regno == tdep->mte_reg_base)) | |
614 | store_mteregs_to_thread (regcache); | |
3b4b3e43 | 615 | |
ba60b963 LM |
616 | if (tdep->has_tls () |
617 | && regno >= tdep->tls_regnum_base | |
618 | && regno < tdep->tls_regnum_base + tdep->tls_register_count) | |
3b4b3e43 | 619 | store_tlsregs_to_thread (regcache); |
9d19df75 MS |
620 | } |
621 | ||
396d2e56 AB |
622 | /* A version of the "store_registers" target_ops method used when running |
623 | 32-bit ARM code on an AArch64 target. Copy the value of register REGNO | |
624 | from REGCACHE into the the target. */ | |
625 | ||
626 | static void | |
627 | aarch32_store_registers (struct regcache *regcache, int regno) | |
628 | { | |
629 | arm_gdbarch_tdep *tdep | |
08106042 | 630 | = gdbarch_tdep<arm_gdbarch_tdep> (regcache->arch ()); |
396d2e56 AB |
631 | |
632 | if (regno == -1) | |
633 | { | |
634 | store_gregs_to_thread (regcache); | |
635 | if (tdep->vfp_register_count > 0) | |
636 | store_fpregs_to_thread (regcache); | |
637 | } | |
638 | else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) | |
639 | store_gregs_to_thread (regcache); | |
640 | else if (tdep->vfp_register_count > 0 | |
641 | && regno >= ARM_D0_REGNUM | |
642 | && (regno < ARM_D0_REGNUM + tdep->vfp_register_count | |
643 | || regno == ARM_FPSCR_REGNUM)) | |
644 | store_fpregs_to_thread (regcache); | |
645 | } | |
646 | ||
647 | /* Implement the "store_registers" target_ops method. */ | |
648 | ||
649 | void | |
650 | aarch64_linux_nat_target::store_registers (struct regcache *regcache, | |
651 | int regno) | |
652 | { | |
653 | if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32) | |
654 | aarch32_store_registers (regcache, regno); | |
655 | else | |
656 | aarch64_store_registers (regcache, regno); | |
657 | } | |
658 | ||
9d19df75 MS |
659 | /* Fill register REGNO (if it is a general-purpose register) in |
660 | *GREGSETPS with the value in GDB's register array. If REGNO is -1, | |
661 | do this for all registers. */ | |
662 | ||
663 | void | |
664 | fill_gregset (const struct regcache *regcache, | |
665 | gdb_gregset_t *gregsetp, int regno) | |
666 | { | |
d4d793bf AA |
667 | regcache_collect_regset (&aarch64_linux_gregset, regcache, |
668 | regno, (gdb_byte *) gregsetp, | |
669 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
670 | } |
671 | ||
672 | /* Fill GDB's register array with the general-purpose register values | |
673 | in *GREGSETP. */ | |
674 | ||
675 | void | |
676 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) | |
677 | { | |
d4d793bf AA |
678 | regcache_supply_regset (&aarch64_linux_gregset, regcache, -1, |
679 | (const gdb_byte *) gregsetp, | |
680 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
681 | } |
682 | ||
683 | /* Fill register REGNO (if it is a floating-point register) in | |
684 | *FPREGSETP with the value in GDB's register array. If REGNO is -1, | |
685 | do this for all registers. */ | |
686 | ||
687 | void | |
688 | fill_fpregset (const struct regcache *regcache, | |
689 | gdb_fpregset_t *fpregsetp, int regno) | |
690 | { | |
d4d793bf AA |
691 | regcache_collect_regset (&aarch64_linux_fpregset, regcache, |
692 | regno, (gdb_byte *) fpregsetp, | |
693 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
694 | } |
695 | ||
696 | /* Fill GDB's register array with the floating-point register values | |
697 | in *FPREGSETP. */ | |
698 | ||
699 | void | |
700 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) | |
701 | { | |
d4d793bf AA |
702 | regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1, |
703 | (const gdb_byte *) fpregsetp, | |
704 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
705 | } |
706 | ||
d6c44983 YZ |
707 | /* linux_nat_new_fork hook. */ |
708 | ||
135340af PA |
709 | void |
710 | aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent, | |
711 | pid_t child_pid) | |
d6c44983 YZ |
712 | { |
713 | pid_t parent_pid; | |
714 | struct aarch64_debug_reg_state *parent_state; | |
715 | struct aarch64_debug_reg_state *child_state; | |
716 | ||
717 | /* NULL means no watchpoint has ever been set in the parent. In | |
718 | that case, there's nothing to do. */ | |
719 | if (parent->arch_private == NULL) | |
720 | return; | |
721 | ||
722 | /* GDB core assumes the child inherits the watchpoints/hw | |
723 | breakpoints of the parent, and will remove them all from the | |
724 | forked off process. Copy the debug registers mirrors into the | |
725 | new process so that all breakpoints and watchpoints can be | |
726 | removed together. */ | |
727 | ||
e99b03dc | 728 | parent_pid = parent->ptid.pid (); |
d6c44983 YZ |
729 | parent_state = aarch64_get_debug_reg_state (parent_pid); |
730 | child_state = aarch64_get_debug_reg_state (child_pid); | |
731 | *child_state = *parent_state; | |
732 | } | |
9d19df75 MS |
733 | \f |
734 | ||
735 | /* Called by libthread_db. Returns a pointer to the thread local | |
736 | storage (or its descriptor). */ | |
737 | ||
738 | ps_err_e | |
754653a7 | 739 | ps_get_thread_area (struct ps_prochandle *ph, |
9d19df75 MS |
740 | lwpid_t lwpid, int idx, void **base) |
741 | { | |
a0cc84cd YQ |
742 | int is_64bit_p |
743 | = (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64); | |
9d19df75 | 744 | |
a0cc84cd | 745 | return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p); |
9d19df75 MS |
746 | } |
747 | \f | |
748 | ||
200fd287 | 749 | /* Implement the virtual inf_ptrace_target::post_startup_inferior method. */ |
9d19df75 | 750 | |
f6ac5f3d PA |
751 | void |
752 | aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid) | |
9d19df75 | 753 | { |
e99b03dc TT |
754 | low_forget_process (ptid.pid ()); |
755 | aarch64_linux_get_debug_reg_capacity (ptid.pid ()); | |
f6ac5f3d | 756 | linux_nat_target::post_startup_inferior (ptid); |
9d19df75 MS |
757 | } |
758 | ||
8363f9d5 RB |
759 | /* Implement the "post_attach" target_ops method. */ |
760 | ||
761 | void | |
762 | aarch64_linux_nat_target::post_attach (int pid) | |
763 | { | |
764 | low_forget_process (pid); | |
765 | /* Set the hardware debug register capacity. If | |
766 | aarch64_linux_get_debug_reg_capacity is not called | |
767 | (as it is in aarch64_linux_child_post_startup_inferior) then | |
768 | software watchpoints will be used instead of hardware | |
769 | watchpoints when attaching to a target. */ | |
770 | aarch64_linux_get_debug_reg_capacity (pid); | |
771 | linux_nat_target::post_attach (pid); | |
772 | } | |
773 | ||
f6ac5f3d | 774 | /* Implement the "read_description" target_ops method. */ |
9d19df75 | 775 | |
f6ac5f3d PA |
776 | const struct target_desc * |
777 | aarch64_linux_nat_target::read_description () | |
9d19df75 | 778 | { |
6f67973b | 779 | int ret, tid; |
350fab54 | 780 | gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; |
6f67973b | 781 | struct iovec iovec; |
607685ec | 782 | |
fbf3c4b9 | 783 | tid = inferior_ptid.pid (); |
607685ec | 784 | |
6f67973b | 785 | iovec.iov_base = regbuf; |
350fab54 | 786 | iovec.iov_len = ARM_VFP3_REGS_SIZE; |
607685ec | 787 | |
6f67973b YQ |
788 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
789 | if (ret == 0) | |
d105cce5 | 790 | return aarch32_read_description (); |
6dc0ebde | 791 | |
82d23ca8 SM |
792 | CORE_ADDR hwcap = linux_get_hwcap (); |
793 | CORE_ADDR hwcap2 = linux_get_hwcap2 (); | |
ee4fbcfa | 794 | |
0ee6b1c5 JB |
795 | aarch64_features features; |
796 | features.vq = aarch64_sve_get_vq (tid); | |
797 | features.pauth = hwcap & AARCH64_HWCAP_PACA; | |
798 | features.mte = hwcap2 & HWCAP2_MTE; | |
ba60b963 | 799 | features.tls = aarch64_tls_register_count (tid); |
c1bd443b | 800 | |
0ee6b1c5 | 801 | return aarch64_read_description (features); |
9d19df75 MS |
802 | } |
803 | ||
ade90bde YQ |
804 | /* Convert a native/host siginfo object, into/from the siginfo in the |
805 | layout of the inferiors' architecture. Returns true if any | |
806 | conversion was done; false otherwise. If DIRECTION is 1, then copy | |
807 | from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to | |
808 | INF. */ | |
809 | ||
135340af PA |
810 | bool |
811 | aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, | |
812 | int direction) | |
ade90bde YQ |
813 | { |
814 | struct gdbarch *gdbarch = get_frame_arch (get_current_frame ()); | |
815 | ||
816 | /* Is the inferior 32-bit? If so, then do fixup the siginfo | |
817 | object. */ | |
818 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
819 | { | |
820 | if (direction == 0) | |
821 | aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, | |
822 | native); | |
823 | else | |
824 | aarch64_siginfo_from_compat_siginfo (native, | |
825 | (struct compat_siginfo *) inf); | |
826 | ||
135340af | 827 | return true; |
ade90bde YQ |
828 | } |
829 | ||
135340af | 830 | return false; |
ade90bde YQ |
831 | } |
832 | ||
f6ac5f3d | 833 | /* Implement the "stopped_data_address" target_ops method. */ |
9d19df75 | 834 | |
57810aa7 | 835 | bool |
f6ac5f3d | 836 | aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
9d19df75 MS |
837 | { |
838 | siginfo_t siginfo; | |
9d19df75 MS |
839 | struct aarch64_debug_reg_state *state; |
840 | ||
841 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
57810aa7 | 842 | return false; |
9d19df75 MS |
843 | |
844 | /* This must be a hardware breakpoint. */ | |
845 | if (siginfo.si_signo != SIGTRAP | |
846 | || (siginfo.si_code & 0xffff) != TRAP_HWBKPT) | |
57810aa7 | 847 | return false; |
9d19df75 | 848 | |
19007d95 LM |
849 | /* Make sure to ignore the top byte, otherwise we may not recognize a |
850 | hardware watchpoint hit. The stopped data addresses coming from the | |
851 | kernel can potentially be tagged addresses. */ | |
852 | struct gdbarch *gdbarch = thread_architecture (inferior_ptid); | |
853 | const CORE_ADDR addr_trap | |
d88cb738 | 854 | = gdbarch_remove_non_address_bits (gdbarch, (CORE_ADDR) siginfo.si_addr); |
19007d95 | 855 | |
9d19df75 | 856 | /* Check if the address matches any watched address. */ |
e99b03dc | 857 | state = aarch64_get_debug_reg_state (inferior_ptid.pid ()); |
1570c37c | 858 | return aarch64_stopped_data_address (state, addr_trap, addr_p); |
9d19df75 MS |
859 | } |
860 | ||
f6ac5f3d | 861 | /* Implement the "stopped_by_watchpoint" target_ops method. */ |
9d19df75 | 862 | |
57810aa7 | 863 | bool |
f6ac5f3d | 864 | aarch64_linux_nat_target::stopped_by_watchpoint () |
9d19df75 MS |
865 | { |
866 | CORE_ADDR addr; | |
867 | ||
f6ac5f3d | 868 | return stopped_data_address (&addr); |
9d19df75 MS |
869 | } |
870 | ||
f6ac5f3d | 871 | /* Implement the "can_do_single_step" target_ops method. */ |
750ce8d1 | 872 | |
f6ac5f3d PA |
873 | int |
874 | aarch64_linux_nat_target::can_do_single_step () | |
750ce8d1 YQ |
875 | { |
876 | return 1; | |
877 | } | |
878 | ||
396d2e56 AB |
879 | /* Implement the "thread_architecture" target_ops method. |
880 | ||
881 | Returns the gdbarch for the thread identified by PTID. If the thread in | |
882 | question is a 32-bit ARM thread, then the architecture returned will be | |
883 | that of the process itself. | |
884 | ||
885 | If the thread is an AArch64 thread then we need to check the current | |
886 | vector length; if the vector length has changed then we need to lookup a | |
887 | new gdbarch that matches the new vector length. */ | |
4da037ef AH |
888 | |
889 | struct gdbarch * | |
890 | aarch64_linux_nat_target::thread_architecture (ptid_t ptid) | |
891 | { | |
396d2e56 | 892 | /* Find the current gdbarch the same way as process_stratum_target. */ |
5b6d1e4f | 893 | inferior *inf = find_inferior_ptid (this, ptid); |
4da037ef | 894 | gdb_assert (inf != NULL); |
396d2e56 AB |
895 | |
896 | /* If this is a 32-bit architecture, then this is ARM, not AArch64. | |
897 | There's no SVE vectors here, so just return the inferior | |
898 | architecture. */ | |
899 | if (gdbarch_bfd_arch_info (inf->gdbarch)->bits_per_word == 32) | |
900 | return inf->gdbarch; | |
901 | ||
902 | /* Only return it if the current vector length matches the one in the tdep. */ | |
aa70a99e | 903 | aarch64_gdbarch_tdep *tdep |
08106042 | 904 | = gdbarch_tdep<aarch64_gdbarch_tdep> (inf->gdbarch); |
396d2e56 | 905 | uint64_t vq = aarch64_sve_get_vq (ptid.lwp ()); |
aa70a99e | 906 | if (vq == tdep->vq) |
4da037ef AH |
907 | return inf->gdbarch; |
908 | ||
909 | /* We reach here if the vector length for the thread is different from its | |
910 | value at process start. Lookup gdbarch via info (potentially creating a | |
4f3681cc TJB |
911 | new one) by using a target description that corresponds to the new vq value |
912 | and the current architecture features. */ | |
913 | ||
914 | const struct target_desc *tdesc = gdbarch_target_desc (inf->gdbarch); | |
915 | aarch64_features features = aarch64_features_from_target_desc (tdesc); | |
916 | features.vq = vq; | |
917 | ||
4da037ef | 918 | struct gdbarch_info info; |
6a5206eb | 919 | info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64); |
4f3681cc | 920 | info.target_desc = aarch64_read_description (features); |
4da037ef AH |
921 | return gdbarch_find_by_info (info); |
922 | } | |
923 | ||
4601818e LM |
924 | /* Implement the "supports_memory_tagging" target_ops method. */ |
925 | ||
926 | bool | |
927 | aarch64_linux_nat_target::supports_memory_tagging () | |
928 | { | |
82d23ca8 | 929 | return (linux_get_hwcap2 () & HWCAP2_MTE) != 0; |
4601818e LM |
930 | } |
931 | ||
932 | /* Implement the "fetch_memtags" target_ops method. */ | |
933 | ||
934 | bool | |
935 | aarch64_linux_nat_target::fetch_memtags (CORE_ADDR address, size_t len, | |
936 | gdb::byte_vector &tags, int type) | |
937 | { | |
938 | int tid = get_ptrace_pid (inferior_ptid); | |
939 | ||
940 | /* Allocation tags? */ | |
941 | if (type == static_cast<int> (aarch64_memtag_type::mte_allocation)) | |
942 | return aarch64_mte_fetch_memtags (tid, address, len, tags); | |
943 | ||
944 | return false; | |
945 | } | |
946 | ||
947 | /* Implement the "store_memtags" target_ops method. */ | |
948 | ||
949 | bool | |
950 | aarch64_linux_nat_target::store_memtags (CORE_ADDR address, size_t len, | |
951 | const gdb::byte_vector &tags, int type) | |
952 | { | |
953 | int tid = get_ptrace_pid (inferior_ptid); | |
954 | ||
955 | /* Allocation tags? */ | |
956 | if (type == static_cast<int> (aarch64_memtag_type::mte_allocation)) | |
957 | return aarch64_mte_store_memtags (tid, address, len, tags); | |
958 | ||
959 | return false; | |
960 | } | |
961 | ||
6c265988 | 962 | void _initialize_aarch64_linux_nat (); |
9d19df75 | 963 | void |
6c265988 | 964 | _initialize_aarch64_linux_nat () |
9d19df75 | 965 | { |
1570c37c | 966 | aarch64_initialize_hw_point (); |
9d19df75 | 967 | |
9d19df75 | 968 | /* Register the target. */ |
f6ac5f3d | 969 | linux_target = &the_aarch64_linux_nat_target; |
d9f719f1 | 970 | add_inf_child_target (&the_aarch64_linux_nat_target); |
9d19df75 | 971 | } |