]>
Commit | Line | Data |
---|---|---|
c906108c SS |
1 | /* Target machine description for generic Motorola 88000, for GDB. |
2 | Copyright 1986, 1987, 1988, 1989, 1990, 1991, 1993 | |
3 | Free Software Foundation, Inc. | |
4 | ||
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* g++ support is not yet included. */ | |
23 | ||
24 | /* Define the bit, byte, and word ordering of the machine. */ | |
25 | #define TARGET_BYTE_ORDER BIG_ENDIAN | |
26 | ||
27 | /* We cache information about saved registers in the frame structure, | |
28 | to save us from having to re-scan function prologues every time | |
29 | a register in a non-current frame is accessed. */ | |
30 | ||
31 | #define EXTRA_FRAME_INFO \ | |
32 | struct frame_saved_regs *fsr; \ | |
33 | CORE_ADDR locals_pointer; \ | |
34 | CORE_ADDR args_pointer; | |
35 | ||
36 | /* Zero the frame_saved_regs pointer when the frame is initialized, | |
37 | so that FRAME_FIND_SAVED_REGS () will know to allocate and | |
38 | initialize a frame_saved_regs struct the first time it is called. | |
39 | Set the arg_pointer to -1, which is not valid; 0 and other values | |
40 | indicate real, cached values. */ | |
41 | ||
42 | #define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \ | |
43 | init_extra_frame_info (fromleaf, fi) | |
44 | extern void init_extra_frame_info (); | |
45 | ||
46 | #define IEEE_FLOAT | |
47 | ||
48 | /* Offset from address of function to start of its code. | |
49 | Zero on most machines. */ | |
50 | ||
51 | #define FUNCTION_START_OFFSET 0 | |
52 | ||
53 | /* Advance PC across any function entry prologue instructions | |
54 | to reach some "real" code. */ | |
55 | ||
b83266a0 SS |
56 | extern CORE_ADDR m88k_skip_prologue PARAMS ((CORE_ADDR)); |
57 | #define SKIP_PROLOGUE(frompc) (m88k_skip_prologue (frompc)) | |
c906108c SS |
58 | |
59 | /* The m88k kernel aligns all instructions on 4-byte boundaries. The | |
60 | kernel also uses the least significant two bits for its own hocus | |
61 | pocus. When gdb receives an address from the kernel, it needs to | |
62 | preserve those right-most two bits, but gdb also needs to be careful | |
63 | to realize that those two bits are not really a part of the address | |
64 | of an instruction. Shrug. */ | |
65 | ||
66 | extern CORE_ADDR m88k_addr_bits_remove PARAMS ((CORE_ADDR)); | |
67 | #define ADDR_BITS_REMOVE(addr) m88k_addr_bits_remove (addr) | |
68 | ||
69 | /* Immediately after a function call, return the saved pc. | |
70 | Can't always go through the frames for this because on some machines | |
71 | the new frame is not set up until the new function executes | |
72 | some instructions. */ | |
73 | ||
74 | #define SAVED_PC_AFTER_CALL(frame) \ | |
75 | (ADDR_BITS_REMOVE (read_register (SRP_REGNUM))) | |
76 | ||
77 | /* Stack grows downward. */ | |
78 | ||
79 | #define INNER_THAN(lhs,rhs) ((lhs) < (rhs)) | |
80 | ||
81 | /* Sequence of bytes for breakpoint instruction. */ | |
82 | ||
83 | /* instruction 0xF000D1FF is 'tb0 0,r0,511' | |
84 | If Bit bit 0 of r0 is clear (always true), | |
85 | initiate exception processing (trap). | |
86 | */ | |
87 | #define BREAKPOINT {0xF0, 0x00, 0xD1, 0xFF} | |
88 | ||
89 | /* Amount PC must be decremented by after a breakpoint. | |
90 | This is often the number of bytes in BREAKPOINT | |
91 | but not always. */ | |
92 | ||
93 | #define DECR_PC_AFTER_BREAK 0 | |
94 | ||
95 | /* Say how long (ordinary) registers are. This is a piece of bogosity | |
96 | used in push_word and a few other places; REGISTER_RAW_SIZE is the | |
97 | real way to know how big a register is. */ | |
98 | ||
99 | #define REGISTER_SIZE 4 | |
100 | ||
101 | /* Number of machine registers */ | |
102 | ||
103 | #define GP_REGS (38) | |
104 | #define FP_REGS (32) | |
105 | #define NUM_REGS (GP_REGS + FP_REGS) | |
106 | ||
107 | /* Initializer for an array of names of registers. | |
108 | There should be NUM_REGS strings in this initializer. */ | |
109 | ||
110 | #define REGISTER_NAMES {\ | |
111 | "r0",\ | |
112 | "r1",\ | |
113 | "r2",\ | |
114 | "r3",\ | |
115 | "r4",\ | |
116 | "r5",\ | |
117 | "r6",\ | |
118 | "r7",\ | |
119 | "r8",\ | |
120 | "r9",\ | |
121 | "r10",\ | |
122 | "r11",\ | |
123 | "r12",\ | |
124 | "r13",\ | |
125 | "r14",\ | |
126 | "r15",\ | |
127 | "r16",\ | |
128 | "r17",\ | |
129 | "r18",\ | |
130 | "r19",\ | |
131 | "r20",\ | |
132 | "r21",\ | |
133 | "r22",\ | |
134 | "r23",\ | |
135 | "r24",\ | |
136 | "r25",\ | |
137 | "r26",\ | |
138 | "r27",\ | |
139 | "r28",\ | |
140 | "r29",\ | |
141 | "r30",\ | |
142 | "r31",\ | |
143 | "psr",\ | |
144 | "fpsr",\ | |
145 | "fpcr",\ | |
146 | "sxip",\ | |
147 | "snip",\ | |
148 | "sfip",\ | |
149 | "x0",\ | |
150 | "x1",\ | |
151 | "x2",\ | |
152 | "x3",\ | |
153 | "x4",\ | |
154 | "x5",\ | |
155 | "x6",\ | |
156 | "x7",\ | |
157 | "x8",\ | |
158 | "x9",\ | |
159 | "x10",\ | |
160 | "x11",\ | |
161 | "x12",\ | |
162 | "x13",\ | |
163 | "x14",\ | |
164 | "x15",\ | |
165 | "x16",\ | |
166 | "x17",\ | |
167 | "x18",\ | |
168 | "x19",\ | |
169 | "x20",\ | |
170 | "x21",\ | |
171 | "x22",\ | |
172 | "x23",\ | |
173 | "x24",\ | |
174 | "x25",\ | |
175 | "x26",\ | |
176 | "x27",\ | |
177 | "x28",\ | |
178 | "x29",\ | |
179 | "x30",\ | |
180 | "x31",\ | |
181 | "vbr",\ | |
182 | "dmt0",\ | |
183 | "dmd0",\ | |
184 | "dma0",\ | |
185 | "dmt1",\ | |
186 | "dmd1",\ | |
187 | "dma1",\ | |
188 | "dmt2",\ | |
189 | "dmd2",\ | |
190 | "dma2",\ | |
191 | "sr0",\ | |
192 | "sr1",\ | |
193 | "sr2",\ | |
194 | "sr3",\ | |
195 | "fpecr",\ | |
196 | "fphs1",\ | |
197 | "fpls1",\ | |
198 | "fphs2",\ | |
199 | "fpls2",\ | |
200 | "fppt",\ | |
201 | "fprh",\ | |
202 | "fprl",\ | |
203 | "fpit",\ | |
204 | "fpsr",\ | |
205 | "fpcr",\ | |
206 | } | |
207 | ||
208 | ||
209 | /* Register numbers of various important registers. | |
210 | Note that some of these values are "real" register numbers, | |
211 | and correspond to the general registers of the machine, | |
212 | and some are "phony" register numbers which are too large | |
213 | to be actual register numbers as far as the user is concerned | |
214 | but do serve to get the desired values when passed to read_register. */ | |
215 | ||
216 | #define R0_REGNUM 0 /* Contains the constant zero */ | |
217 | #define SRP_REGNUM 1 /* Contains subroutine return pointer */ | |
218 | #define RV_REGNUM 2 /* Contains simple return values */ | |
219 | #define SRA_REGNUM 12 /* Contains address of struct return values */ | |
220 | #define SP_REGNUM 31 /* Contains address of top of stack */ | |
221 | ||
222 | /* Instruction pointer notes... | |
223 | ||
224 | On the m88100: | |
225 | ||
226 | * cr04 = sxip. On exception, contains the excepting pc (probably). | |
227 | On rte, is ignored. | |
228 | ||
229 | * cr05 = snip. On exception, contains the NPC (next pc). On rte, | |
230 | pc is loaded from here. | |
231 | ||
232 | * cr06 = sfip. On exception, contains the NNPC (next next pc). On | |
233 | rte, the NPC is loaded from here. | |
234 | ||
235 | * lower two bits of each are flag bits. Bit 1 is V means address | |
236 | is valid. If address is not valid, bit 0 is ignored. Otherwise, | |
237 | bit 0 is E and asks for an exception to be taken if this | |
238 | instruction is executed. | |
239 | ||
240 | On the m88110: | |
241 | ||
242 | * cr04 = exip. On exception, contains the address of the excepting | |
243 | pc (always). On rte, pc is loaded from here. Bit 0, aka the D | |
244 | bit, is a flag saying that the offending instruction was in a | |
245 | branch delay slot. If set, then cr05 contains the NPC. | |
246 | ||
247 | * cr05 = enip. On exception, if the instruction pointed to by cr04 | |
248 | was in a delay slot as indicated by the bit 0 of cr04, aka the D | |
249 | bit, the cr05 contains the NPC. Otherwise ignored. | |
250 | ||
251 | * cr06 is invalid */ | |
252 | ||
253 | /* Note that the Harris Unix kernels emulate the m88100's behavior on | |
254 | the m88110. */ | |
255 | ||
256 | #define SXIP_REGNUM 35 /* On m88100, Contains Shadow Execute | |
257 | Instruction Pointer. */ | |
258 | #define SNIP_REGNUM 36 /* On m88100, Contains Shadow Next | |
259 | Instruction Pointer. */ | |
260 | #define SFIP_REGNUM 37 /* On m88100, Contains Shadow Fetched | |
261 | Intruction pointer. */ | |
262 | ||
263 | #define EXIP_REGNUM 35 /* On m88110, Contains Exception | |
264 | Executing Instruction Pointer. */ | |
265 | #define ENIP_REGNUM 36 /* On m88110, Contains the Exception | |
266 | Next Instruction Pointer. */ | |
267 | ||
268 | #define PC_REGNUM SXIP_REGNUM /* Program Counter */ | |
269 | #define NPC_REGNUM SNIP_REGNUM /* Next Program Counter */ | |
c5aa993b | 270 | #define NNPC_REGNUM SFIP_REGNUM /* Next Next Program Counter */ |
c906108c | 271 | |
c5aa993b | 272 | #define PSR_REGNUM 32 /* Processor Status Register */ |
c906108c SS |
273 | #define FPSR_REGNUM 33 /* Floating Point Status Register */ |
274 | #define FPCR_REGNUM 34 /* Floating Point Control Register */ | |
275 | #define XFP_REGNUM 38 /* First Extended Float Register */ | |
276 | #define X0_REGNUM XFP_REGNUM /* Which also contains the constant zero */ | |
277 | ||
278 | /* This is rather a confusing lie. Our m88k port using a stack pointer value | |
279 | for the frame address. Hence, the frame address and the frame pointer are | |
280 | only indirectly related. The value of this macro is the register number | |
281 | fetched by the machine "independent" portions of gdb when they want to know | |
282 | about a frame address. Thus, we lie here and claim that FP_REGNUM is | |
283 | SP_REGNUM. */ | |
284 | #define FP_REGNUM SP_REGNUM /* Reg fetched to locate frame when pgm stops */ | |
285 | #define ACTUAL_FP_REGNUM 30 | |
286 | ||
287 | /* PSR status bit definitions. */ | |
288 | ||
289 | #define PSR_MODE 0x80000000 | |
290 | #define PSR_BYTE_ORDER 0x40000000 | |
291 | #define PSR_SERIAL_MODE 0x20000000 | |
292 | #define PSR_CARRY 0x10000000 | |
293 | #define PSR_SFU_DISABLE 0x000003f0 | |
294 | #define PSR_SFU1_DISABLE 0x00000008 | |
295 | #define PSR_MXM 0x00000004 | |
296 | #define PSR_IND 0x00000002 | |
297 | #define PSR_SFRZ 0x00000001 | |
298 | ||
299 | ||
300 | ||
301 | /* The following two comments come from the days prior to the m88110 | |
302 | port. The m88110 handles the instruction pointers differently. I | |
303 | do not know what any m88110 kernels do as the m88110 port I'm | |
304 | working with is for an embedded system. rich@cygnus.com | |
305 | 13-sept-93. */ | |
306 | ||
307 | /* BCS requires that the SXIP_REGNUM (or PC_REGNUM) contain the | |
308 | address of the next instr to be executed when a breakpoint occurs. | |
309 | Because the kernel gets the next instr (SNIP_REGNUM), the instr in | |
310 | SNIP needs to be put back into SFIP, and the instr in SXIP should | |
311 | be shifted to SNIP */ | |
312 | ||
313 | /* Are you sitting down? It turns out that the 88K BCS (binary | |
314 | compatibility standard) folks originally felt that the debugger | |
315 | should be responsible for backing up the IPs, not the kernel (as is | |
316 | usually done). Well, they have reversed their decision, and in | |
317 | future releases our kernel will be handling the backing up of the | |
318 | IPs. So, eventually, we won't need to do the SHIFT_INST_REGS | |
319 | stuff. But, for now, since there are 88K systems out there that do | |
320 | need the debugger to do the IP shifting, and since there will be | |
321 | systems where the kernel does the shifting, the code is a little | |
322 | more complex than perhaps it needs to be (we still go inside | |
323 | SHIFT_INST_REGS, and if the shifting hasn't occurred then gdb goes | |
324 | ahead and shifts). */ | |
325 | ||
326 | extern int target_is_m88110; | |
327 | #define SHIFT_INST_REGS() \ | |
328 | if (!target_is_m88110) \ | |
329 | { \ | |
330 | CORE_ADDR pc = read_register (PC_REGNUM); \ | |
331 | CORE_ADDR npc = read_register (NPC_REGNUM); \ | |
332 | if (pc != npc) \ | |
333 | { \ | |
334 | write_register (NNPC_REGNUM, npc); \ | |
335 | write_register (NPC_REGNUM, pc); \ | |
336 | } \ | |
337 | } | |
338 | ||
339 | /* Storing the following registers is a no-op. */ | |
340 | #define CANNOT_STORE_REGISTER(regno) (((regno) == R0_REGNUM) \ | |
341 | || ((regno) == X0_REGNUM)) | |
342 | ||
343 | /* Number of bytes of storage in the actual machine representation | |
344 | for register N. On the m88k, the general purpose registers are 4 | |
345 | bytes and the 88110 extended registers are 10 bytes. */ | |
346 | ||
347 | #define REGISTER_RAW_SIZE(N) ((N) < XFP_REGNUM ? 4 : 10) | |
348 | ||
349 | /* Total amount of space needed to store our copies of the machine's | |
350 | register state, the array `registers'. */ | |
351 | ||
352 | #define REGISTER_BYTES ((GP_REGS * REGISTER_RAW_SIZE(0)) \ | |
353 | + (FP_REGS * REGISTER_RAW_SIZE(XFP_REGNUM))) | |
354 | ||
355 | /* Index within `registers' of the first byte of the space for | |
356 | register N. */ | |
357 | ||
358 | #define REGISTER_BYTE(N) (((N) * REGISTER_RAW_SIZE(0)) \ | |
359 | + ((N) >= XFP_REGNUM \ | |
360 | ? (((N) - XFP_REGNUM) \ | |
361 | * REGISTER_RAW_SIZE(XFP_REGNUM)) \ | |
362 | : 0)) | |
363 | ||
364 | /* Number of bytes of storage in the program's representation for | |
365 | register N. On the m88k, all registers are 4 bytes excepting the | |
366 | m88110 extended registers which are 8 byte doubles. */ | |
367 | ||
368 | #define REGISTER_VIRTUAL_SIZE(N) ((N) < XFP_REGNUM ? 4 : 8) | |
369 | ||
370 | /* Largest value REGISTER_RAW_SIZE can have. */ | |
371 | ||
372 | #define MAX_REGISTER_RAW_SIZE (REGISTER_RAW_SIZE(XFP_REGNUM)) | |
373 | ||
374 | /* Largest value REGISTER_VIRTUAL_SIZE can have. | |
375 | Are FPS1, FPS2, FPR "virtual" regisers? */ | |
376 | ||
377 | #define MAX_REGISTER_VIRTUAL_SIZE (REGISTER_RAW_SIZE(XFP_REGNUM)) | |
378 | ||
379 | /* Nonzero if register N requires conversion | |
380 | from raw format to virtual format. */ | |
381 | ||
382 | #define REGISTER_CONVERTIBLE(N) ((N) >= XFP_REGNUM) | |
383 | ||
384 | #include "floatformat.h" | |
385 | ||
386 | /* Convert data from raw format for register REGNUM in buffer FROM | |
387 | to virtual format with type TYPE in buffer TO. */ | |
388 | ||
389 | #define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,TYPE,FROM,TO) \ | |
390 | { \ | |
391 | double val; \ | |
392 | floatformat_to_double (&floatformat_m88110_ext, (FROM), &val); \ | |
393 | store_floating ((TO), TYPE_LENGTH (TYPE), val); \ | |
394 | } | |
395 | ||
396 | /* Convert data from virtual format with type TYPE in buffer FROM | |
397 | to raw format for register REGNUM in buffer TO. */ | |
398 | ||
399 | #define REGISTER_CONVERT_TO_RAW(TYPE,REGNUM,FROM,TO) \ | |
400 | { \ | |
401 | double val = extract_floating ((FROM), TYPE_LENGTH (TYPE)); \ | |
402 | floatformat_from_double (&floatformat_m88110_ext, &val, (TO)); \ | |
403 | } | |
404 | ||
405 | /* Return the GDB type object for the "standard" data type | |
406 | of data in register N. */ | |
407 | ||
408 | #define REGISTER_VIRTUAL_TYPE(N) \ | |
409 | ((N) >= XFP_REGNUM \ | |
410 | ? builtin_type_double \ | |
411 | : ((N) == PC_REGNUM || (N) == FP_REGNUM || (N) == SP_REGNUM \ | |
412 | ? lookup_pointer_type (builtin_type_void) : builtin_type_int)) | |
413 | ||
414 | /* The 88k call/return conventions call for "small" values to be returned | |
415 | into consecutive registers starting from r2. */ | |
416 | ||
417 | #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \ | |
418 | memcpy ((VALBUF), &(((char *)REGBUF)[REGISTER_BYTE(RV_REGNUM)]), TYPE_LENGTH (TYPE)) | |
419 | ||
420 | #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) (*(int *)(REGBUF)) | |
421 | ||
422 | /* Write into appropriate registers a function return value | |
423 | of type TYPE, given in virtual format. */ | |
424 | ||
425 | #define STORE_RETURN_VALUE(TYPE,VALBUF) \ | |
426 | write_register_bytes (2*REGISTER_RAW_SIZE(0), (VALBUF), TYPE_LENGTH (TYPE)) | |
427 | ||
428 | /* In COFF, if PCC says a parameter is a short or a char, do not | |
429 | change it to int (it seems the convention is to change it). */ | |
430 | ||
431 | #define BELIEVE_PCC_PROMOTION 1 | |
432 | ||
433 | /* Describe the pointer in each stack frame to the previous stack frame | |
434 | (its caller). */ | |
435 | ||
436 | /* FRAME_CHAIN takes a frame's nominal address | |
437 | and produces the frame's chain-pointer. | |
438 | ||
439 | However, if FRAME_CHAIN_VALID returns zero, | |
440 | it means the given frame is the outermost one and has no caller. */ | |
441 | ||
442 | extern CORE_ADDR frame_chain (); | |
443 | extern int frame_chain_valid (); | |
444 | extern int frameless_function_invocation (); | |
445 | ||
446 | #define FRAME_CHAIN(thisframe) \ | |
447 | frame_chain (thisframe) | |
448 | ||
392a587b JM |
449 | #define FRAMELESS_FUNCTION_INVOCATION(frame) \ |
450 | (frameless_function_invocation (frame)) | |
c906108c SS |
451 | |
452 | /* Define other aspects of the stack frame. */ | |
453 | ||
454 | #define FRAME_SAVED_PC(FRAME) \ | |
455 | frame_saved_pc (FRAME) | |
456 | extern CORE_ADDR frame_saved_pc (); | |
457 | ||
458 | #define FRAME_ARGS_ADDRESS(fi) \ | |
459 | frame_args_address (fi) | |
460 | extern CORE_ADDR frame_args_address (); | |
461 | ||
462 | #define FRAME_LOCALS_ADDRESS(fi) \ | |
463 | frame_locals_address (fi) | |
464 | extern CORE_ADDR frame_locals_address (); | |
465 | ||
466 | /* Return number of args passed to a frame. | |
467 | Can return -1, meaning no way to tell. */ | |
468 | ||
392a587b | 469 | #define FRAME_NUM_ARGS(fi) (-1) |
c906108c SS |
470 | |
471 | /* Return number of bytes at start of arglist that are not really args. */ | |
472 | ||
473 | #define FRAME_ARGS_SKIP 0 | |
474 | ||
475 | /* Put here the code to store, into a struct frame_saved_regs, | |
476 | the addresses of the saved registers of frame described by FRAME_INFO. | |
477 | This includes special registers such as pc and fp saved in special | |
478 | ways in the stack frame. sp is even more special: | |
479 | the address we return for it IS the sp for the next frame. */ | |
480 | ||
481 | /* On the 88k, parameter registers get stored into the so called "homing" | |
482 | area. This *always* happens when you compiled with GCC and use -g. | |
483 | Also, (with GCC and -g) the saving of the parameter register values | |
484 | always happens right within the function prologue code, so these register | |
485 | values can generally be relied upon to be already copied into their | |
486 | respective homing slots by the time you will normally try to look at | |
487 | them (we hope). | |
488 | ||
489 | Note that homing area stack slots are always at *positive* offsets from | |
490 | the frame pointer. Thus, the homing area stack slots for the parameter | |
491 | registers (passed values) for a given function are actually part of the | |
492 | frame area of the caller. This is unusual, but it should not present | |
493 | any special problems for GDB. | |
494 | ||
495 | Note also that on the 88k, we are only interested in finding the | |
496 | registers that might have been saved in memory. This is a subset of | |
497 | the whole set of registers because the standard calling sequence allows | |
498 | the called routine to clobber many registers. | |
499 | ||
500 | We could manage to locate values for all of the so called "preserved" | |
501 | registers (some of which may get saved within any particular frame) but | |
502 | that would require decoding all of the tdesc information. That would be | |
503 | nice information for GDB to have, but it is not strictly manditory if we | |
504 | can live without the ability to look at values within (or backup to) | |
505 | previous frames. | |
c5aa993b | 506 | */ |
c906108c SS |
507 | |
508 | struct frame_saved_regs; | |
509 | struct frame_info; | |
510 | ||
c5aa993b JM |
511 | void frame_find_saved_regs PARAMS ((struct frame_info * fi, |
512 | struct frame_saved_regs * fsr)); | |
c906108c SS |
513 | |
514 | #define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \ | |
515 | frame_find_saved_regs (frame_info, &frame_saved_regs) | |
c906108c | 516 | \f |
c5aa993b | 517 | |
c906108c SS |
518 | #define POP_FRAME pop_frame () |
519 | extern void pop_frame (); | |
520 | ||
521 | /* Call function stuff contributed by Kevin Buettner of Motorola. */ | |
522 | ||
523 | #define CALL_DUMMY_LOCATION AFTER_TEXT_END | |
524 | ||
c5aa993b | 525 | extern void m88k_push_dummy_frame (); |
c906108c SS |
526 | #define PUSH_DUMMY_FRAME m88k_push_dummy_frame() |
527 | ||
528 | #define CALL_DUMMY { \ | |
529 | 0x67ff00c0, /* 0: subu #sp,#sp,0xc0 */ \ | |
530 | 0x243f0004, /* 4: st #r1,#sp,0x4 */ \ | |
531 | 0x245f0008, /* 8: st #r2,#sp,0x8 */ \ | |
532 | 0x247f000c, /* c: st #r3,#sp,0xc */ \ | |
533 | 0x249f0010, /* 10: st #r4,#sp,0x10 */ \ | |
534 | 0x24bf0014, /* 14: st #r5,#sp,0x14 */ \ | |
535 | 0x24df0018, /* 18: st #r6,#sp,0x18 */ \ | |
536 | 0x24ff001c, /* 1c: st #r7,#sp,0x1c */ \ | |
537 | 0x251f0020, /* 20: st #r8,#sp,0x20 */ \ | |
538 | 0x253f0024, /* 24: st #r9,#sp,0x24 */ \ | |
539 | 0x255f0028, /* 28: st #r10,#sp,0x28 */ \ | |
540 | 0x257f002c, /* 2c: st #r11,#sp,0x2c */ \ | |
541 | 0x259f0030, /* 30: st #r12,#sp,0x30 */ \ | |
542 | 0x25bf0034, /* 34: st #r13,#sp,0x34 */ \ | |
543 | 0x25df0038, /* 38: st #r14,#sp,0x38 */ \ | |
544 | 0x25ff003c, /* 3c: st #r15,#sp,0x3c */ \ | |
545 | 0x261f0040, /* 40: st #r16,#sp,0x40 */ \ | |
546 | 0x263f0044, /* 44: st #r17,#sp,0x44 */ \ | |
547 | 0x265f0048, /* 48: st #r18,#sp,0x48 */ \ | |
548 | 0x267f004c, /* 4c: st #r19,#sp,0x4c */ \ | |
549 | 0x269f0050, /* 50: st #r20,#sp,0x50 */ \ | |
550 | 0x26bf0054, /* 54: st #r21,#sp,0x54 */ \ | |
551 | 0x26df0058, /* 58: st #r22,#sp,0x58 */ \ | |
552 | 0x26ff005c, /* 5c: st #r23,#sp,0x5c */ \ | |
553 | 0x271f0060, /* 60: st #r24,#sp,0x60 */ \ | |
554 | 0x273f0064, /* 64: st #r25,#sp,0x64 */ \ | |
555 | 0x275f0068, /* 68: st #r26,#sp,0x68 */ \ | |
556 | 0x277f006c, /* 6c: st #r27,#sp,0x6c */ \ | |
557 | 0x279f0070, /* 70: st #r28,#sp,0x70 */ \ | |
558 | 0x27bf0074, /* 74: st #r29,#sp,0x74 */ \ | |
559 | 0x27df0078, /* 78: st #r30,#sp,0x78 */ \ | |
560 | 0x63df0000, /* 7c: addu #r30,#sp,0x0 */ \ | |
561 | 0x145f0000, /* 80: ld #r2,#sp,0x0 */ \ | |
562 | 0x147f0004, /* 84: ld #r3,#sp,0x4 */ \ | |
563 | 0x149f0008, /* 88: ld #r4,#sp,0x8 */ \ | |
564 | 0x14bf000c, /* 8c: ld #r5,#sp,0xc */ \ | |
565 | 0x14df0010, /* 90: ld #r6,#sp,0x10 */ \ | |
566 | 0x14ff0014, /* 94: ld #r7,#sp,0x14 */ \ | |
567 | 0x151f0018, /* 98: ld #r8,#sp,0x18 */ \ | |
568 | 0x153f001c, /* 9c: ld #r9,#sp,0x1c */ \ | |
569 | 0x5c200000, /* a0: or.u #r1,#r0,0x0 */ \ | |
570 | 0x58210000, /* a4: or #r1,#r1,0x0 */ \ | |
571 | 0xf400c801, /* a8: jsr #r1 */ \ | |
572 | 0xf000d1ff /* ac: tb0 0x0,#r0,0x1ff */ \ | |
573 | } | |
574 | ||
575 | #define CALL_DUMMY_START_OFFSET 0x80 | |
576 | #define CALL_DUMMY_LENGTH 0xb0 | |
577 | ||
578 | /* FIXME: byteswapping. */ | |
579 | #define FIX_CALL_DUMMY(dummy, pc, fun, nargs, args, type, gcc_p) \ | |
580 | { \ | |
581 | *(unsigned long *)((char *) (dummy) + 0xa0) |= \ | |
582 | (((unsigned long) (fun)) >> 16); \ | |
583 | *(unsigned long *)((char *) (dummy) + 0xa4) |= \ | |
584 | (((unsigned long) (fun)) & 0xffff); \ | |
585 | pc = text_end; \ | |
586 | } | |
587 | ||
588 | /* Stack must be aligned on 64-bit boundaries when synthesizing | |
589 | function calls. */ | |
590 | ||
591 | #define STACK_ALIGN(addr) (((addr) + 7) & -8) | |
592 | ||
593 | #define STORE_STRUCT_RETURN(addr, sp) \ | |
594 | write_register (SRA_REGNUM, (addr)) | |
595 | ||
596 | #define NEED_TEXT_START_END 1 | |
597 | ||
598 | /* According to the MC88100 RISC Microprocessor User's Manual, section | |
599 | 6.4.3.1.2: | |
600 | ||
c5aa993b JM |
601 | ... can be made to return to a particular instruction by placing a |
602 | valid instruction address in the SNIP and the next sequential | |
603 | instruction address in the SFIP (with V bits set and E bits clear). | |
604 | The rte resumes execution at the instruction pointed to by the | |
605 | SNIP, then the SFIP. | |
c906108c SS |
606 | |
607 | The E bit is the least significant bit (bit 0). The V (valid) bit is | |
608 | bit 1. This is why we logical or 2 into the values we are writing | |
609 | below. It turns out that SXIP plays no role when returning from an | |
610 | exception so nothing special has to be done with it. We could even | |
611 | (presumably) give it a totally bogus value. | |
612 | ||
613 | -- Kevin Buettner | |
c5aa993b JM |
614 | */ |
615 | ||
c906108c SS |
616 | #define TARGET_WRITE_PC(val, pid) { \ |
617 | write_register_pid(SXIP_REGNUM, (long) val, pid); \ | |
618 | write_register_pid(SNIP_REGNUM, (long) val | 2, pid); \ | |
619 | write_register_pid(SFIP_REGNUM, ((long) val | 2) + 4, pid); \ | |
620 | } |