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456f8b9d | 1 | /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger. |
0fd88904 | 2 | |
1d506c26 | 3 | Copyright (C) 2002-2024 Free Software Foundation, Inc. |
456f8b9d DB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
456f8b9d DB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
456f8b9d | 19 | |
ec452525 | 20 | #include "extract-store-integer.h" |
4de283e4 TT |
21 | #include "inferior.h" |
22 | #include "gdbcore.h" | |
456f8b9d | 23 | #include "arch-utils.h" |
4de283e4 TT |
24 | #include "regcache.h" |
25 | #include "frame.h" | |
26 | #include "frame-unwind.h" | |
27 | #include "frame-base.h" | |
28 | #include "trad-frame.h" | |
dcc6aaff | 29 | #include "dis-asm.h" |
4de283e4 | 30 | #include "sim-regno.h" |
d026e67e | 31 | #include "sim/sim-frv.h" |
4de283e4 | 32 | #include "symtab.h" |
7e295833 KB |
33 | #include "elf-bfd.h" |
34 | #include "elf/frv.h" | |
d55e5aa6 | 35 | #include "osabi.h" |
4de283e4 | 36 | #include "infcall.h" |
d55e5aa6 | 37 | #include "solib.h" |
4de283e4 TT |
38 | #include "frv-tdep.h" |
39 | #include "objfiles.h" | |
76eb8ef1 | 40 | #include "gdbarch.h" |
456f8b9d | 41 | |
883d90a0 TV |
42 | /* Make cgen names unique to prevent ODR conflicts with other targets. */ |
43 | #define GDB_CGEN_REMAP_PREFIX frv | |
44 | #include "cgen-remap.h" | |
ef0f16cc | 45 | #include "opcodes/frv-desc.h" |
883d90a0 | 46 | |
1cb761c7 | 47 | struct frv_unwind_cache /* was struct frame_extra_info */ |
456f8b9d | 48 | { |
1cb761c7 KB |
49 | /* The previous frame's inner-most stack address. Used as this |
50 | frame ID's stack_addr. */ | |
51 | CORE_ADDR prev_sp; | |
456f8b9d | 52 | |
1cb761c7 KB |
53 | /* The frame's base, optionally used by the high-level debug info. */ |
54 | CORE_ADDR base; | |
8baa6f92 KB |
55 | |
56 | /* Table indicating the location of each and every register. */ | |
098caef4 | 57 | trad_frame_saved_reg *saved_regs; |
456f8b9d DB |
58 | }; |
59 | ||
456f8b9d DB |
60 | /* A structure describing a particular variant of the FRV. |
61 | We allocate and initialize one of these structures when we create | |
62 | the gdbarch object for a variant. | |
63 | ||
64 | At the moment, all the FR variants we support differ only in which | |
65 | registers are present; the portable code of GDB knows that | |
66 | registers whose names are the empty string don't exist, so the | |
67 | `register_names' array captures all the per-variant information we | |
68 | need. | |
69 | ||
70 | in the future, if we need to have per-variant maps for raw size, | |
71 | virtual type, etc., we should replace register_names with an array | |
72 | of structures, each of which gives all the necessary info for one | |
73 | register. Don't stick parallel arrays in here --- that's so | |
74 | Fortran. */ | |
ab25d9bb | 75 | struct frv_gdbarch_tdep : gdbarch_tdep_base |
456f8b9d | 76 | { |
7e295833 | 77 | /* Which ABI is in use? */ |
345bd07c | 78 | enum frv_abi frv_abi {}; |
7e295833 | 79 | |
456f8b9d | 80 | /* How many general-purpose registers does this variant have? */ |
345bd07c | 81 | int num_gprs = 0; |
456f8b9d DB |
82 | |
83 | /* How many floating-point registers does this variant have? */ | |
345bd07c | 84 | int num_fprs = 0; |
456f8b9d DB |
85 | |
86 | /* How many hardware watchpoints can it support? */ | |
345bd07c | 87 | int num_hw_watchpoints = 0; |
456f8b9d DB |
88 | |
89 | /* How many hardware breakpoints can it support? */ | |
345bd07c | 90 | int num_hw_breakpoints = 0; |
456f8b9d DB |
91 | |
92 | /* Register names. */ | |
345bd07c | 93 | const char **register_names = nullptr; |
456f8b9d DB |
94 | }; |
95 | ||
2b16913c SM |
96 | using frv_gdbarch_tdep_up = std::unique_ptr<frv_gdbarch_tdep>; |
97 | ||
7e295833 KB |
98 | /* Return the FR-V ABI associated with GDBARCH. */ |
99 | enum frv_abi | |
100 | frv_abi (struct gdbarch *gdbarch) | |
101 | { | |
08106042 | 102 | frv_gdbarch_tdep *tdep = gdbarch_tdep<frv_gdbarch_tdep> (gdbarch); |
345bd07c | 103 | return tdep->frv_abi; |
7e295833 KB |
104 | } |
105 | ||
106 | /* Fetch the interpreter and executable loadmap addresses (for shared | |
107 | library support) for the FDPIC ABI. Return 0 if successful, -1 if | |
108 | not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */ | |
109 | int | |
110 | frv_fdpic_loadmap_addresses (struct gdbarch *gdbarch, CORE_ADDR *interp_addr, | |
dda83cd7 | 111 | CORE_ADDR *exec_addr) |
7e295833 KB |
112 | { |
113 | if (frv_abi (gdbarch) != FRV_ABI_FDPIC) | |
114 | return -1; | |
115 | else | |
116 | { | |
9c742269 | 117 | regcache *regcache = get_thread_regcache (inferior_thread ()); |
594f7785 | 118 | |
7e295833 KB |
119 | if (interp_addr != NULL) |
120 | { | |
121 | ULONGEST val; | |
594f7785 | 122 | regcache_cooked_read_unsigned (regcache, |
7e295833 KB |
123 | fdpic_loadmap_interp_regnum, &val); |
124 | *interp_addr = val; | |
125 | } | |
126 | if (exec_addr != NULL) | |
127 | { | |
128 | ULONGEST val; | |
594f7785 | 129 | regcache_cooked_read_unsigned (regcache, |
7e295833 KB |
130 | fdpic_loadmap_exec_regnum, &val); |
131 | *exec_addr = val; | |
132 | } | |
133 | return 0; | |
134 | } | |
135 | } | |
456f8b9d DB |
136 | |
137 | /* Allocate a new variant structure, and set up default values for all | |
138 | the fields. */ | |
2b16913c SM |
139 | static frv_gdbarch_tdep_up |
140 | new_variant () | |
456f8b9d | 141 | { |
456f8b9d | 142 | int r; |
456f8b9d | 143 | |
2b16913c | 144 | frv_gdbarch_tdep_up var (new frv_gdbarch_tdep); |
8d749320 | 145 | |
7e295833 | 146 | var->frv_abi = FRV_ABI_EABI; |
456f8b9d DB |
147 | var->num_gprs = 64; |
148 | var->num_fprs = 64; | |
149 | var->num_hw_watchpoints = 0; | |
150 | var->num_hw_breakpoints = 0; | |
151 | ||
152 | /* By default, don't supply any general-purpose or floating-point | |
153 | register names. */ | |
6a748db6 | 154 | var->register_names |
a121b7c1 PA |
155 | = (const char **) xmalloc ((frv_num_regs + frv_num_pseudo_regs) |
156 | * sizeof (const char *)); | |
6a748db6 | 157 | for (r = 0; r < frv_num_regs + frv_num_pseudo_regs; r++) |
456f8b9d DB |
158 | var->register_names[r] = ""; |
159 | ||
526eef89 | 160 | /* Do, however, supply default names for the known special-purpose |
456f8b9d | 161 | registers. */ |
456f8b9d DB |
162 | |
163 | var->register_names[pc_regnum] = "pc"; | |
164 | var->register_names[lr_regnum] = "lr"; | |
165 | var->register_names[lcr_regnum] = "lcr"; | |
166 | ||
167 | var->register_names[psr_regnum] = "psr"; | |
168 | var->register_names[ccr_regnum] = "ccr"; | |
169 | var->register_names[cccr_regnum] = "cccr"; | |
170 | var->register_names[tbr_regnum] = "tbr"; | |
171 | ||
172 | /* Debug registers. */ | |
173 | var->register_names[brr_regnum] = "brr"; | |
174 | var->register_names[dbar0_regnum] = "dbar0"; | |
175 | var->register_names[dbar1_regnum] = "dbar1"; | |
176 | var->register_names[dbar2_regnum] = "dbar2"; | |
177 | var->register_names[dbar3_regnum] = "dbar3"; | |
178 | ||
526eef89 KB |
179 | /* iacc0 (Only found on MB93405.) */ |
180 | var->register_names[iacc0h_regnum] = "iacc0h"; | |
181 | var->register_names[iacc0l_regnum] = "iacc0l"; | |
6a748db6 | 182 | var->register_names[iacc0_regnum] = "iacc0"; |
526eef89 | 183 | |
8b67aa36 KB |
184 | /* fsr0 (Found on FR555 and FR501.) */ |
185 | var->register_names[fsr0_regnum] = "fsr0"; | |
186 | ||
187 | /* acc0 - acc7. The architecture provides for the possibility of many | |
188 | more (up to 64 total), but we don't want to make that big of a hole | |
189 | in the G packet. If we need more in the future, we'll add them | |
190 | elsewhere. */ | |
191 | for (r = acc0_regnum; r <= acc7_regnum; r++) | |
8579fd13 AB |
192 | var->register_names[r] |
193 | = xstrprintf ("acc%d", r - acc0_regnum).release (); | |
8b67aa36 KB |
194 | |
195 | /* accg0 - accg7: These are one byte registers. The remote protocol | |
196 | provides the raw values packed four into a slot. accg0123 and | |
197 | accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively. | |
198 | We don't provide names for accg0123 and accg4567 since the user will | |
199 | likely not want to see these raw values. */ | |
200 | ||
201 | for (r = accg0_regnum; r <= accg7_regnum; r++) | |
8579fd13 AB |
202 | var->register_names[r] |
203 | = xstrprintf ("accg%d", r - accg0_regnum).release (); | |
8b67aa36 KB |
204 | |
205 | /* msr0 and msr1. */ | |
206 | ||
207 | var->register_names[msr0_regnum] = "msr0"; | |
208 | var->register_names[msr1_regnum] = "msr1"; | |
209 | ||
210 | /* gner and fner registers. */ | |
211 | var->register_names[gner0_regnum] = "gner0"; | |
212 | var->register_names[gner1_regnum] = "gner1"; | |
213 | var->register_names[fner0_regnum] = "fner0"; | |
214 | var->register_names[fner1_regnum] = "fner1"; | |
215 | ||
456f8b9d DB |
216 | return var; |
217 | } | |
218 | ||
219 | ||
220 | /* Indicate that the variant VAR has NUM_GPRS general-purpose | |
221 | registers, and fill in the names array appropriately. */ | |
222 | static void | |
345bd07c | 223 | set_variant_num_gprs (frv_gdbarch_tdep *var, int num_gprs) |
456f8b9d DB |
224 | { |
225 | int r; | |
226 | ||
227 | var->num_gprs = num_gprs; | |
228 | ||
229 | for (r = 0; r < num_gprs; ++r) | |
230 | { | |
231 | char buf[20]; | |
232 | ||
08850b56 | 233 | xsnprintf (buf, sizeof (buf), "gr%d", r); |
456f8b9d DB |
234 | var->register_names[first_gpr_regnum + r] = xstrdup (buf); |
235 | } | |
236 | } | |
237 | ||
238 | ||
239 | /* Indicate that the variant VAR has NUM_FPRS floating-point | |
240 | registers, and fill in the names array appropriately. */ | |
241 | static void | |
345bd07c | 242 | set_variant_num_fprs (frv_gdbarch_tdep *var, int num_fprs) |
456f8b9d DB |
243 | { |
244 | int r; | |
245 | ||
246 | var->num_fprs = num_fprs; | |
247 | ||
248 | for (r = 0; r < num_fprs; ++r) | |
249 | { | |
250 | char buf[20]; | |
251 | ||
08850b56 | 252 | xsnprintf (buf, sizeof (buf), "fr%d", r); |
456f8b9d DB |
253 | var->register_names[first_fpr_regnum + r] = xstrdup (buf); |
254 | } | |
255 | } | |
256 | ||
7e295833 | 257 | static void |
345bd07c | 258 | set_variant_abi_fdpic (frv_gdbarch_tdep *var) |
7e295833 KB |
259 | { |
260 | var->frv_abi = FRV_ABI_FDPIC; | |
261 | var->register_names[fdpic_loadmap_exec_regnum] = xstrdup ("loadmap_exec"); | |
0963b4bd MS |
262 | var->register_names[fdpic_loadmap_interp_regnum] |
263 | = xstrdup ("loadmap_interp"); | |
7e295833 | 264 | } |
456f8b9d | 265 | |
b2d6d697 | 266 | static void |
345bd07c | 267 | set_variant_scratch_registers (frv_gdbarch_tdep *var) |
b2d6d697 KB |
268 | { |
269 | var->register_names[scr0_regnum] = xstrdup ("scr0"); | |
270 | var->register_names[scr1_regnum] = xstrdup ("scr1"); | |
271 | var->register_names[scr2_regnum] = xstrdup ("scr2"); | |
272 | var->register_names[scr3_regnum] = xstrdup ("scr3"); | |
273 | } | |
274 | ||
456f8b9d | 275 | static const char * |
d93859e2 | 276 | frv_register_name (struct gdbarch *gdbarch, int reg) |
456f8b9d | 277 | { |
08106042 | 278 | frv_gdbarch_tdep *tdep = gdbarch_tdep<frv_gdbarch_tdep> (gdbarch); |
345bd07c | 279 | return tdep->register_names[reg]; |
456f8b9d DB |
280 | } |
281 | ||
526eef89 | 282 | |
456f8b9d | 283 | static struct type * |
7f398216 | 284 | frv_register_type (struct gdbarch *gdbarch, int reg) |
456f8b9d | 285 | { |
526eef89 | 286 | if (reg >= first_fpr_regnum && reg <= last_fpr_regnum) |
0dfff4cb | 287 | return builtin_type (gdbarch)->builtin_float; |
6a748db6 | 288 | else if (reg == iacc0_regnum) |
df4df182 | 289 | return builtin_type (gdbarch)->builtin_int64; |
456f8b9d | 290 | else |
df4df182 | 291 | return builtin_type (gdbarch)->builtin_int32; |
456f8b9d DB |
292 | } |
293 | ||
05d1431c | 294 | static enum register_status |
849d0ba8 | 295 | frv_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
dda83cd7 | 296 | int reg, gdb_byte *buffer) |
6a748db6 | 297 | { |
05d1431c PA |
298 | enum register_status status; |
299 | ||
6a748db6 KB |
300 | if (reg == iacc0_regnum) |
301 | { | |
03f50fc8 | 302 | status = regcache->raw_read (iacc0h_regnum, buffer); |
05d1431c | 303 | if (status == REG_VALID) |
03f50fc8 | 304 | status = regcache->raw_read (iacc0l_regnum, (bfd_byte *) buffer + 4); |
6a748db6 | 305 | } |
8b67aa36 KB |
306 | else if (accg0_regnum <= reg && reg <= accg7_regnum) |
307 | { | |
308 | /* The accg raw registers have four values in each slot with the | |
dda83cd7 | 309 | lowest register number occupying the first byte. */ |
8b67aa36 KB |
310 | |
311 | int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; | |
312 | int byte_num = (reg - accg0_regnum) % 4; | |
05d1431c | 313 | gdb_byte buf[4]; |
8b67aa36 | 314 | |
03f50fc8 | 315 | status = regcache->raw_read (raw_regnum, buf); |
05d1431c PA |
316 | if (status == REG_VALID) |
317 | { | |
318 | memset (buffer, 0, 4); | |
319 | /* FR-V is big endian, so put the requested byte in the | |
320 | first byte of the buffer allocated to hold the | |
321 | pseudo-register. */ | |
322 | buffer[0] = buf[byte_num]; | |
323 | } | |
8b67aa36 | 324 | } |
05d1431c PA |
325 | else |
326 | gdb_assert_not_reached ("invalid pseudo register number"); | |
327 | ||
328 | return status; | |
6a748db6 KB |
329 | } |
330 | ||
331 | static void | |
332 | frv_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
dda83cd7 | 333 | int reg, const gdb_byte *buffer) |
6a748db6 KB |
334 | { |
335 | if (reg == iacc0_regnum) | |
336 | { | |
10eaee5f SM |
337 | regcache->raw_write (iacc0h_regnum, buffer); |
338 | regcache->raw_write (iacc0l_regnum, (bfd_byte *) buffer + 4); | |
6a748db6 | 339 | } |
8b67aa36 KB |
340 | else if (accg0_regnum <= reg && reg <= accg7_regnum) |
341 | { | |
342 | /* The accg raw registers have four values in each slot with the | |
dda83cd7 | 343 | lowest register number occupying the first byte. */ |
8b67aa36 KB |
344 | |
345 | int raw_regnum = accg0123_regnum + (reg - accg0_regnum) / 4; | |
346 | int byte_num = (reg - accg0_regnum) % 4; | |
e362b510 | 347 | gdb_byte buf[4]; |
8b67aa36 | 348 | |
0b883586 | 349 | regcache->raw_read (raw_regnum, buf); |
8b67aa36 | 350 | buf[byte_num] = ((bfd_byte *) buffer)[0]; |
10eaee5f | 351 | regcache->raw_write (raw_regnum, buf); |
8b67aa36 | 352 | } |
6a748db6 KB |
353 | } |
354 | ||
526eef89 | 355 | static int |
e7faf938 | 356 | frv_register_sim_regno (struct gdbarch *gdbarch, int reg) |
526eef89 KB |
357 | { |
358 | static const int spr_map[] = | |
359 | { | |
360 | H_SPR_PSR, /* psr_regnum */ | |
361 | H_SPR_CCR, /* ccr_regnum */ | |
362 | H_SPR_CCCR, /* cccr_regnum */ | |
8b67aa36 KB |
363 | -1, /* fdpic_loadmap_exec_regnum */ |
364 | -1, /* fdpic_loadmap_interp_regnum */ | |
526eef89 KB |
365 | -1, /* 134 */ |
366 | H_SPR_TBR, /* tbr_regnum */ | |
367 | H_SPR_BRR, /* brr_regnum */ | |
368 | H_SPR_DBAR0, /* dbar0_regnum */ | |
369 | H_SPR_DBAR1, /* dbar1_regnum */ | |
370 | H_SPR_DBAR2, /* dbar2_regnum */ | |
371 | H_SPR_DBAR3, /* dbar3_regnum */ | |
8b67aa36 KB |
372 | H_SPR_SCR0, /* scr0_regnum */ |
373 | H_SPR_SCR1, /* scr1_regnum */ | |
374 | H_SPR_SCR2, /* scr2_regnum */ | |
375 | H_SPR_SCR3, /* scr3_regnum */ | |
526eef89 KB |
376 | H_SPR_LR, /* lr_regnum */ |
377 | H_SPR_LCR, /* lcr_regnum */ | |
378 | H_SPR_IACC0H, /* iacc0h_regnum */ | |
8b67aa36 KB |
379 | H_SPR_IACC0L, /* iacc0l_regnum */ |
380 | H_SPR_FSR0, /* fsr0_regnum */ | |
381 | /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */ | |
382 | -1, /* acc0_regnum */ | |
383 | -1, /* acc1_regnum */ | |
384 | -1, /* acc2_regnum */ | |
385 | -1, /* acc3_regnum */ | |
386 | -1, /* acc4_regnum */ | |
387 | -1, /* acc5_regnum */ | |
388 | -1, /* acc6_regnum */ | |
389 | -1, /* acc7_regnum */ | |
390 | -1, /* acc0123_regnum */ | |
391 | -1, /* acc4567_regnum */ | |
392 | H_SPR_MSR0, /* msr0_regnum */ | |
393 | H_SPR_MSR1, /* msr1_regnum */ | |
394 | H_SPR_GNER0, /* gner0_regnum */ | |
395 | H_SPR_GNER1, /* gner1_regnum */ | |
396 | H_SPR_FNER0, /* fner0_regnum */ | |
397 | H_SPR_FNER1, /* fner1_regnum */ | |
526eef89 KB |
398 | }; |
399 | ||
e7faf938 | 400 | gdb_assert (reg >= 0 && reg < gdbarch_num_regs (gdbarch)); |
526eef89 KB |
401 | |
402 | if (first_gpr_regnum <= reg && reg <= last_gpr_regnum) | |
403 | return reg - first_gpr_regnum + SIM_FRV_GR0_REGNUM; | |
404 | else if (first_fpr_regnum <= reg && reg <= last_fpr_regnum) | |
405 | return reg - first_fpr_regnum + SIM_FRV_FR0_REGNUM; | |
406 | else if (pc_regnum == reg) | |
407 | return SIM_FRV_PC_REGNUM; | |
408 | else if (reg >= first_spr_regnum | |
dda83cd7 | 409 | && reg < first_spr_regnum + sizeof (spr_map) / sizeof (spr_map[0])) |
526eef89 KB |
410 | { |
411 | int spr_reg_offset = spr_map[reg - first_spr_regnum]; | |
412 | ||
413 | if (spr_reg_offset < 0) | |
414 | return SIM_REGNO_DOES_NOT_EXIST; | |
415 | else | |
416 | return SIM_FRV_SPR0_REGNUM + spr_reg_offset; | |
417 | } | |
418 | ||
f34652de | 419 | internal_error (_("Bad register number %d"), reg); |
526eef89 KB |
420 | } |
421 | ||
04180708 | 422 | constexpr gdb_byte frv_break_insn[] = {0xc0, 0x70, 0x00, 0x01}; |
598cc9dc | 423 | |
04180708 | 424 | typedef BP_MANIPULATION (frv_break_insn) frv_breakpoint; |
456f8b9d | 425 | |
46a16dba KB |
426 | /* Define the maximum number of instructions which may be packed into a |
427 | bundle (VLIW instruction). */ | |
428 | static const int max_instrs_per_bundle = 8; | |
429 | ||
430 | /* Define the size (in bytes) of an FR-V instruction. */ | |
431 | static const int frv_instr_size = 4; | |
432 | ||
433 | /* Adjust a breakpoint's address to account for the FR-V architecture's | |
434 | constraint that a break instruction must not appear as any but the | |
435 | first instruction in the bundle. */ | |
436 | static CORE_ADDR | |
1208538e | 437 | frv_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) |
46a16dba KB |
438 | { |
439 | int count = max_instrs_per_bundle; | |
440 | CORE_ADDR addr = bpaddr - frv_instr_size; | |
441 | CORE_ADDR func_start = get_pc_function_start (bpaddr); | |
442 | ||
443 | /* Find the end of the previous packing sequence. This will be indicated | |
444 | by either attempting to access some inaccessible memory or by finding | |
0963b4bd | 445 | an instruction word whose packing bit is set to one. */ |
46a16dba KB |
446 | while (count-- > 0 && addr >= func_start) |
447 | { | |
948f8e3d | 448 | gdb_byte instr[frv_instr_size]; |
46a16dba KB |
449 | int status; |
450 | ||
8defab1a | 451 | status = target_read_memory (addr, instr, sizeof instr); |
46a16dba KB |
452 | |
453 | if (status != 0) | |
454 | break; | |
455 | ||
456 | /* This is a big endian architecture, so byte zero will have most | |
dda83cd7 SM |
457 | significant byte. The most significant bit of this byte is the |
458 | packing bit. */ | |
46a16dba KB |
459 | if (instr[0] & 0x80) |
460 | break; | |
461 | ||
462 | addr -= frv_instr_size; | |
463 | } | |
464 | ||
465 | if (count > 0) | |
466 | bpaddr = addr + frv_instr_size; | |
467 | ||
468 | return bpaddr; | |
469 | } | |
470 | ||
456f8b9d DB |
471 | |
472 | /* Return true if REG is a caller-saves ("scratch") register, | |
473 | false otherwise. */ | |
474 | static int | |
475 | is_caller_saves_reg (int reg) | |
476 | { | |
477 | return ((4 <= reg && reg <= 7) | |
dda83cd7 SM |
478 | || (14 <= reg && reg <= 15) |
479 | || (32 <= reg && reg <= 47)); | |
456f8b9d DB |
480 | } |
481 | ||
482 | ||
483 | /* Return true if REG is a callee-saves register, false otherwise. */ | |
484 | static int | |
485 | is_callee_saves_reg (int reg) | |
486 | { | |
487 | return ((16 <= reg && reg <= 31) | |
dda83cd7 | 488 | || (48 <= reg && reg <= 63)); |
456f8b9d DB |
489 | } |
490 | ||
491 | ||
492 | /* Return true if REG is an argument register, false otherwise. */ | |
493 | static int | |
494 | is_argument_reg (int reg) | |
495 | { | |
496 | return (8 <= reg && reg <= 13); | |
497 | } | |
498 | ||
456f8b9d DB |
499 | /* Scan an FR-V prologue, starting at PC, until frame->PC. |
500 | If FRAME is non-zero, fill in its saved_regs with appropriate addresses. | |
501 | We assume FRAME's saved_regs array has already been allocated and cleared. | |
502 | Return the first PC value after the prologue. | |
503 | ||
504 | Note that, for unoptimized code, we almost don't need this function | |
505 | at all; all arguments and locals live on the stack, so we just need | |
506 | the FP to find everything. The catch: structures passed by value | |
507 | have their addresses living in registers; they're never spilled to | |
508 | the stack. So if you ever want to be able to get to these | |
509 | arguments in any frame but the top, you'll need to do this serious | |
510 | prologue analysis. */ | |
511 | static CORE_ADDR | |
d80b854b | 512 | frv_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
8480a37e | 513 | const frame_info_ptr &this_frame, |
dda83cd7 | 514 | struct frv_unwind_cache *info) |
456f8b9d | 515 | { |
e17a4113 UW |
516 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
517 | ||
456f8b9d DB |
518 | /* When writing out instruction bitpatterns, we use the following |
519 | letters to label instruction fields: | |
520 | P - The parallel bit. We don't use this. | |
521 | J - The register number of GRj in the instruction description. | |
522 | K - The register number of GRk in the instruction description. | |
523 | I - The register number of GRi. | |
85102364 | 524 | S - a signed immediate offset. |
456f8b9d DB |
525 | U - an unsigned immediate offset. |
526 | ||
527 | The dots below the numbers indicate where hex digit boundaries | |
528 | fall, to make it easier to check the numbers. */ | |
529 | ||
530 | /* Non-zero iff we've seen the instruction that initializes the | |
531 | frame pointer for this function's frame. */ | |
532 | int fp_set = 0; | |
533 | ||
534 | /* If fp_set is non_zero, then this is the distance from | |
535 | the stack pointer to frame pointer: fp = sp + fp_offset. */ | |
536 | int fp_offset = 0; | |
537 | ||
0963b4bd | 538 | /* Total size of frame prior to any alloca operations. */ |
456f8b9d DB |
539 | int framesize = 0; |
540 | ||
1cb761c7 KB |
541 | /* Flag indicating if lr has been saved on the stack. */ |
542 | int lr_saved_on_stack = 0; | |
543 | ||
456f8b9d DB |
544 | /* The number of the general-purpose register we saved the return |
545 | address ("link register") in, or -1 if we haven't moved it yet. */ | |
546 | int lr_save_reg = -1; | |
547 | ||
1cb761c7 KB |
548 | /* Offset (from sp) at which lr has been saved on the stack. */ |
549 | ||
550 | int lr_sp_offset = 0; | |
456f8b9d DB |
551 | |
552 | /* If gr_saved[i] is non-zero, then we've noticed that general | |
553 | register i has been saved at gr_sp_offset[i] from the stack | |
554 | pointer. */ | |
555 | char gr_saved[64]; | |
556 | int gr_sp_offset[64]; | |
557 | ||
d40fcd7b KB |
558 | /* The address of the most recently scanned prologue instruction. */ |
559 | CORE_ADDR last_prologue_pc; | |
560 | ||
0963b4bd | 561 | /* The address of the next instruction. */ |
d40fcd7b KB |
562 | CORE_ADDR next_pc; |
563 | ||
564 | /* The upper bound to of the pc values to scan. */ | |
565 | CORE_ADDR lim_pc; | |
566 | ||
456f8b9d DB |
567 | memset (gr_saved, 0, sizeof (gr_saved)); |
568 | ||
d40fcd7b KB |
569 | last_prologue_pc = pc; |
570 | ||
571 | /* Try to compute an upper limit (on how far to scan) based on the | |
572 | line number info. */ | |
d80b854b | 573 | lim_pc = skip_prologue_using_sal (gdbarch, pc); |
d40fcd7b KB |
574 | /* If there's no line number info, lim_pc will be 0. In that case, |
575 | set the limit to be 100 instructions away from pc. Hopefully, this | |
576 | will be far enough away to account for the entire prologue. Don't | |
577 | worry about overshooting the end of the function. The scan loop | |
578 | below contains some checks to avoid scanning unreasonably far. */ | |
579 | if (lim_pc == 0) | |
580 | lim_pc = pc + 400; | |
581 | ||
582 | /* If we have a frame, we don't want to scan past the frame's pc. This | |
583 | will catch those cases where the pc is in the prologue. */ | |
94afd7a6 | 584 | if (this_frame) |
d40fcd7b | 585 | { |
94afd7a6 | 586 | CORE_ADDR frame_pc = get_frame_pc (this_frame); |
d40fcd7b KB |
587 | if (frame_pc < lim_pc) |
588 | lim_pc = frame_pc; | |
589 | } | |
590 | ||
591 | /* Scan the prologue. */ | |
592 | while (pc < lim_pc) | |
456f8b9d | 593 | { |
e362b510 | 594 | gdb_byte buf[frv_instr_size]; |
1ccda5e9 KB |
595 | LONGEST op; |
596 | ||
597 | if (target_read_memory (pc, buf, sizeof buf) != 0) | |
598 | break; | |
2a50938a | 599 | op = extract_signed_integer (buf, byte_order); |
1ccda5e9 | 600 | |
d40fcd7b | 601 | next_pc = pc + 4; |
456f8b9d DB |
602 | |
603 | /* The tests in this chain of ifs should be in order of | |
604 | decreasing selectivity, so that more particular patterns get | |
605 | to fire before less particular patterns. */ | |
606 | ||
d40fcd7b KB |
607 | /* Some sort of control transfer instruction: stop scanning prologue. |
608 | Integer Conditional Branch: | |
609 | X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX | |
610 | Floating-point / media Conditional Branch: | |
611 | X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX | |
612 | LCR Conditional Branch to LR | |
613 | X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX | |
614 | Integer conditional Branches to LR | |
615 | X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX | |
616 | X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX | |
617 | Floating-point/Media Branches to LR | |
618 | X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX | |
619 | X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX | |
620 | Jump and Link | |
621 | X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX | |
622 | X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX | |
623 | Call | |
624 | X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX | |
625 | Return from Trap | |
626 | X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX | |
627 | Integer Conditional Trap | |
628 | X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX | |
629 | X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX | |
630 | Floating-point /media Conditional Trap | |
631 | X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX | |
632 | X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX | |
633 | Break | |
634 | X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX | |
635 | Media Trap | |
636 | X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */ | |
637 | if ((op & 0x01d80000) == 0x00180000 /* Conditional branches and Call */ | |
dda83cd7 | 638 | || (op & 0x01f80000) == 0x00300000 /* Jump and Link */ |
d40fcd7b KB |
639 | || (op & 0x01f80000) == 0x00100000 /* Return from Trap, Trap */ |
640 | || (op & 0x01f80000) == 0x00700000) /* Trap immediate */ | |
641 | { | |
642 | /* Stop scanning; not in prologue any longer. */ | |
643 | break; | |
644 | } | |
645 | ||
646 | /* Loading something from memory into fp probably means that | |
dda83cd7 SM |
647 | we're in the epilogue. Stop scanning the prologue. |
648 | ld @(GRi, GRk), fp | |
d40fcd7b KB |
649 | X 000010 0000010 XXXXXX 000100 XXXXXX |
650 | ldi @(GRi, d12), fp | |
651 | X 000010 0110010 XXXXXX XXXXXXXXXXXX */ | |
652 | else if ((op & 0x7ffc0fc0) == 0x04080100 | |
dda83cd7 | 653 | || (op & 0x7ffc0000) == 0x04c80000) |
d40fcd7b KB |
654 | { |
655 | break; | |
656 | } | |
657 | ||
456f8b9d DB |
658 | /* Setting the FP from the SP: |
659 | ori sp, 0, fp | |
660 | P 000010 0100010 000001 000000000000 = 0x04881000 | |
661 | 0 111111 1111111 111111 111111111111 = 0x7fffffff | |
dda83cd7 | 662 | . . . . . . . . |
456f8b9d | 663 | We treat this as part of the prologue. */ |
d40fcd7b | 664 | else if ((op & 0x7fffffff) == 0x04881000) |
456f8b9d DB |
665 | { |
666 | fp_set = 1; | |
667 | fp_offset = 0; | |
d40fcd7b | 668 | last_prologue_pc = next_pc; |
456f8b9d DB |
669 | } |
670 | ||
671 | /* Move the link register to the scratch register grJ, before saving: | |
dda83cd7 SM |
672 | movsg lr, grJ |
673 | P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0 | |
674 | 0 111111 1111111 111111 111111 000000 = 0x7fffffc0 | |
675 | . . . . . . . . | |
456f8b9d DB |
676 | We treat this as part of the prologue. */ |
677 | else if ((op & 0x7fffffc0) == 0x080d01c0) | |
dda83cd7 SM |
678 | { |
679 | int gr_j = op & 0x3f; | |
456f8b9d | 680 | |
dda83cd7 SM |
681 | /* If we're moving it to a scratch register, that's fine. */ |
682 | if (is_caller_saves_reg (gr_j)) | |
d40fcd7b KB |
683 | { |
684 | lr_save_reg = gr_j; | |
685 | last_prologue_pc = next_pc; | |
686 | } | |
dda83cd7 | 687 | } |
456f8b9d DB |
688 | |
689 | /* To save multiple callee-saves registers on the stack, at | |
dda83cd7 | 690 | offset zero: |
456f8b9d DB |
691 | |
692 | std grK,@(sp,gr0) | |
693 | P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0 | |
694 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
695 | ||
696 | stq grK,@(sp,gr0) | |
697 | P KKKKKK 0000011 000001 000100 000000 = 0x000c1100 | |
698 | 0 000000 1111111 111111 111111 111111 = 0x01ffffff | |
dda83cd7 SM |
699 | . . . . . . . . |
700 | We treat this as part of the prologue, and record the register's | |
456f8b9d DB |
701 | saved address in the frame structure. */ |
702 | else if ((op & 0x01ffffff) == 0x000c10c0 | |
dda83cd7 | 703 | || (op & 0x01ffffff) == 0x000c1100) |
456f8b9d DB |
704 | { |
705 | int gr_k = ((op >> 25) & 0x3f); | |
706 | int ope = ((op >> 6) & 0x3f); | |
dda83cd7 | 707 | int count; |
456f8b9d DB |
708 | int i; |
709 | ||
dda83cd7 SM |
710 | /* Is it an std or an stq? */ |
711 | if (ope == 0x03) | |
712 | count = 2; | |
713 | else | |
714 | count = 4; | |
456f8b9d DB |
715 | |
716 | /* Is it really a callee-saves register? */ | |
717 | if (is_callee_saves_reg (gr_k)) | |
718 | { | |
719 | for (i = 0; i < count; i++) | |
dda83cd7 | 720 | { |
456f8b9d DB |
721 | gr_saved[gr_k + i] = 1; |
722 | gr_sp_offset[gr_k + i] = 4 * i; | |
723 | } | |
d40fcd7b | 724 | last_prologue_pc = next_pc; |
456f8b9d | 725 | } |
456f8b9d DB |
726 | } |
727 | ||
728 | /* Adjusting the stack pointer. (The stack pointer is GR1.) | |
729 | addi sp, S, sp | |
dda83cd7 SM |
730 | P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000 |
731 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
732 | . . . . . . . . | |
456f8b9d DB |
733 | We treat this as part of the prologue. */ |
734 | else if ((op & 0x7ffff000) == 0x02401000) | |
dda83cd7 | 735 | { |
d40fcd7b KB |
736 | if (framesize == 0) |
737 | { | |
738 | /* Sign-extend the twelve-bit field. | |
739 | (Isn't there a better way to do this?) */ | |
740 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
456f8b9d | 741 | |
d40fcd7b KB |
742 | framesize -= s; |
743 | last_prologue_pc = pc; | |
744 | } | |
745 | else | |
746 | { | |
747 | /* If the prologue is being adjusted again, we've | |
dda83cd7 | 748 | likely gone too far; i.e. we're probably in the |
d40fcd7b KB |
749 | epilogue. */ |
750 | break; | |
751 | } | |
456f8b9d DB |
752 | } |
753 | ||
754 | /* Setting the FP to a constant distance from the SP: | |
755 | addi sp, S, fp | |
dda83cd7 SM |
756 | P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000 |
757 | 0 111111 1111111 111111 000000000000 = 0x7ffff000 | |
758 | . . . . . . . . | |
456f8b9d DB |
759 | We treat this as part of the prologue. */ |
760 | else if ((op & 0x7ffff000) == 0x04401000) | |
761 | { | |
762 | /* Sign-extend the twelve-bit field. | |
763 | (Isn't there a better way to do this?) */ | |
764 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
765 | fp_set = 1; | |
766 | fp_offset = s; | |
d40fcd7b | 767 | last_prologue_pc = pc; |
456f8b9d DB |
768 | } |
769 | ||
770 | /* To spill an argument register to a scratch register: | |
771 | ori GRi, 0, GRk | |
772 | P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000 | |
773 | 0 000000 1111111 000000 111111111111 = 0x01fc0fff | |
774 | . . . . . . . . | |
775 | For the time being, we treat this as a prologue instruction, | |
776 | assuming that GRi is an argument register. This one's kind | |
777 | of suspicious, because it seems like it could be part of a | |
778 | legitimate body instruction. But we only come here when the | |
779 | source info wasn't helpful, so we have to do the best we can. | |
780 | Hopefully once GCC and GDB agree on how to emit line number | |
781 | info for prologues, then this code will never come into play. */ | |
782 | else if ((op & 0x01fc0fff) == 0x00880000) | |
783 | { | |
784 | int gr_i = ((op >> 12) & 0x3f); | |
785 | ||
dda83cd7 | 786 | /* Make sure that the source is an arg register; if it is, we'll |
d40fcd7b KB |
787 | treat it as a prologue instruction. */ |
788 | if (is_argument_reg (gr_i)) | |
789 | last_prologue_pc = next_pc; | |
456f8b9d DB |
790 | } |
791 | ||
792 | /* To spill 16-bit values to the stack: | |
793 | sthi GRk, @(fp, s) | |
794 | P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000 | |
795 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
dda83cd7 SM |
796 | . . . . . . . . |
797 | And for 8-bit values, we use STB instructions. | |
456f8b9d DB |
798 | stbi GRk, @(fp, s) |
799 | P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000 | |
800 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
801 | . . . . . . . . | |
dda83cd7 SM |
802 | We check that GRk is really an argument register, and treat |
803 | all such as part of the prologue. */ | |
456f8b9d DB |
804 | else if ( (op & 0x01fff000) == 0x01442000 |
805 | || (op & 0x01fff000) == 0x01402000) | |
806 | { | |
807 | int gr_k = ((op >> 25) & 0x3f); | |
808 | ||
dda83cd7 | 809 | /* Make sure that GRk is really an argument register; treat |
d40fcd7b KB |
810 | it as a prologue instruction if so. */ |
811 | if (is_argument_reg (gr_k)) | |
812 | last_prologue_pc = next_pc; | |
456f8b9d DB |
813 | } |
814 | ||
815 | /* To save multiple callee-saves register on the stack, at a | |
dda83cd7 | 816 | non-zero offset: |
456f8b9d DB |
817 | |
818 | stdi GRk, @(sp, s) | |
819 | P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000 | |
820 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
dda83cd7 | 821 | . . . . . . . . |
456f8b9d DB |
822 | stqi GRk, @(sp, s) |
823 | P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000 | |
824 | 0 000000 1111111 111111 000000000000 = 0x01fff000 | |
825 | . . . . . . . . | |
dda83cd7 | 826 | We treat this as part of the prologue, and record the register's |
456f8b9d DB |
827 | saved address in the frame structure. */ |
828 | else if ((op & 0x01fff000) == 0x014c1000 | |
dda83cd7 | 829 | || (op & 0x01fff000) == 0x01501000) |
456f8b9d DB |
830 | { |
831 | int gr_k = ((op >> 25) & 0x3f); | |
dda83cd7 | 832 | int count; |
456f8b9d DB |
833 | int i; |
834 | ||
dda83cd7 SM |
835 | /* Is it a stdi or a stqi? */ |
836 | if ((op & 0x01fff000) == 0x014c1000) | |
837 | count = 2; | |
838 | else | |
839 | count = 4; | |
456f8b9d DB |
840 | |
841 | /* Is it really a callee-saves register? */ | |
842 | if (is_callee_saves_reg (gr_k)) | |
843 | { | |
844 | /* Sign-extend the twelve-bit field. | |
845 | (Isn't there a better way to do this?) */ | |
846 | int s = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
847 | ||
848 | for (i = 0; i < count; i++) | |
849 | { | |
850 | gr_saved[gr_k + i] = 1; | |
851 | gr_sp_offset[gr_k + i] = s + (4 * i); | |
852 | } | |
d40fcd7b | 853 | last_prologue_pc = next_pc; |
456f8b9d | 854 | } |
456f8b9d DB |
855 | } |
856 | ||
857 | /* Storing any kind of integer register at any constant offset | |
dda83cd7 | 858 | from any other register. |
456f8b9d DB |
859 | |
860 | st GRk, @(GRi, gr0) | |
dda83cd7 SM |
861 | P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080 |
862 | 0 000000 1111111 000000 111111 111111 = 0x01fc0fff | |
863 | . . . . . . . . | |
456f8b9d DB |
864 | sti GRk, @(GRi, d12) |
865 | P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000 | |
866 | 0 000000 1111111 000000 000000000000 = 0x01fc0000 | |
dda83cd7 SM |
867 | . . . . . . . . |
868 | These could be almost anything, but a lot of prologue | |
869 | instructions fall into this pattern, so let's decode the | |
870 | instruction once, and then work at a higher level. */ | |
456f8b9d | 871 | else if (((op & 0x01fc0fff) == 0x000c0080) |
dda83cd7 SM |
872 | || ((op & 0x01fc0000) == 0x01480000)) |
873 | { | |
874 | int gr_k = ((op >> 25) & 0x3f); | |
875 | int gr_i = ((op >> 12) & 0x3f); | |
876 | int offset; | |
877 | ||
878 | /* Are we storing with gr0 as an offset, or using an | |
879 | immediate value? */ | |
880 | if ((op & 0x01fc0fff) == 0x000c0080) | |
881 | offset = 0; | |
882 | else | |
883 | offset = (((op & 0xfff) - 0x800) & 0xfff) - 0x800; | |
884 | ||
885 | /* If the address isn't relative to the SP or FP, it's not a | |
886 | prologue instruction. */ | |
887 | if (gr_i != sp_regnum && gr_i != fp_regnum) | |
d40fcd7b KB |
888 | { |
889 | /* Do nothing; not a prologue instruction. */ | |
890 | } | |
456f8b9d | 891 | |
dda83cd7 SM |
892 | /* Saving the old FP in the new frame (relative to the SP). */ |
893 | else if (gr_k == fp_regnum && gr_i == sp_regnum) | |
1cb761c7 KB |
894 | { |
895 | gr_saved[fp_regnum] = 1; | |
dda83cd7 | 896 | gr_sp_offset[fp_regnum] = offset; |
d40fcd7b | 897 | last_prologue_pc = next_pc; |
1cb761c7 | 898 | } |
456f8b9d | 899 | |
dda83cd7 SM |
900 | /* Saving callee-saves register(s) on the stack, relative to |
901 | the SP. */ | |
902 | else if (gr_i == sp_regnum | |
903 | && is_callee_saves_reg (gr_k)) | |
904 | { | |
905 | gr_saved[gr_k] = 1; | |
1cb761c7 KB |
906 | if (gr_i == sp_regnum) |
907 | gr_sp_offset[gr_k] = offset; | |
908 | else | |
909 | gr_sp_offset[gr_k] = offset + fp_offset; | |
d40fcd7b | 910 | last_prologue_pc = next_pc; |
dda83cd7 | 911 | } |
456f8b9d | 912 | |
dda83cd7 SM |
913 | /* Saving the scratch register holding the return address. */ |
914 | else if (lr_save_reg != -1 | |
915 | && gr_k == lr_save_reg) | |
1cb761c7 KB |
916 | { |
917 | lr_saved_on_stack = 1; | |
918 | if (gr_i == sp_regnum) | |
919 | lr_sp_offset = offset; | |
920 | else | |
dda83cd7 | 921 | lr_sp_offset = offset + fp_offset; |
d40fcd7b | 922 | last_prologue_pc = next_pc; |
1cb761c7 | 923 | } |
456f8b9d | 924 | |
dda83cd7 SM |
925 | /* Spilling int-sized arguments to the stack. */ |
926 | else if (is_argument_reg (gr_k)) | |
d40fcd7b | 927 | last_prologue_pc = next_pc; |
dda83cd7 | 928 | } |
d40fcd7b | 929 | pc = next_pc; |
456f8b9d DB |
930 | } |
931 | ||
94afd7a6 | 932 | if (this_frame && info) |
456f8b9d | 933 | { |
1cb761c7 KB |
934 | int i; |
935 | ULONGEST this_base; | |
456f8b9d DB |
936 | |
937 | /* If we know the relationship between the stack and frame | |
dda83cd7 SM |
938 | pointers, record the addresses of the registers we noticed. |
939 | Note that we have to do this as a separate step at the end, | |
940 | because instructions may save relative to the SP, but we need | |
941 | their addresses relative to the FP. */ | |
456f8b9d | 942 | if (fp_set) |
94afd7a6 | 943 | this_base = get_frame_register_unsigned (this_frame, fp_regnum); |
1cb761c7 | 944 | else |
94afd7a6 | 945 | this_base = get_frame_register_unsigned (this_frame, sp_regnum); |
456f8b9d | 946 | |
1cb761c7 KB |
947 | for (i = 0; i < 64; i++) |
948 | if (gr_saved[i]) | |
098caef4 LM |
949 | info->saved_regs[i].set_addr (this_base - fp_offset |
950 | + gr_sp_offset[i]); | |
456f8b9d | 951 | |
1cb761c7 KB |
952 | info->prev_sp = this_base - fp_offset + framesize; |
953 | info->base = this_base; | |
954 | ||
955 | /* If LR was saved on the stack, record its location. */ | |
956 | if (lr_saved_on_stack) | |
098caef4 LM |
957 | info->saved_regs[lr_regnum].set_addr (this_base - fp_offset |
958 | + lr_sp_offset); | |
1cb761c7 KB |
959 | |
960 | /* The call instruction moves the caller's PC in the callee's LR. | |
961 | Since this is an unwind, do the reverse. Copy the location of LR | |
962 | into PC (the address / regnum) so that a request for PC will be | |
963 | converted into a request for the LR. */ | |
964 | info->saved_regs[pc_regnum] = info->saved_regs[lr_regnum]; | |
965 | ||
966 | /* Save the previous frame's computed SP value. */ | |
a9a87d35 | 967 | info->saved_regs[sp_regnum].set_value (info->prev_sp); |
456f8b9d DB |
968 | } |
969 | ||
d40fcd7b | 970 | return last_prologue_pc; |
456f8b9d DB |
971 | } |
972 | ||
973 | ||
974 | static CORE_ADDR | |
6093d2eb | 975 | frv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
456f8b9d DB |
976 | { |
977 | CORE_ADDR func_addr, func_end, new_pc; | |
978 | ||
979 | new_pc = pc; | |
980 | ||
981 | /* If the line table has entry for a line *within* the function | |
982 | (i.e., not in the prologue, and not past the end), then that's | |
983 | our location. */ | |
984 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
985 | { | |
986 | struct symtab_and_line sal; | |
987 | ||
988 | sal = find_pc_line (func_addr, 0); | |
989 | ||
990 | if (sal.line != 0 && sal.end < func_end) | |
991 | { | |
992 | new_pc = sal.end; | |
993 | } | |
994 | } | |
995 | ||
996 | /* The FR-V prologue is at least five instructions long (twenty bytes). | |
997 | If we didn't find a real source location past that, then | |
998 | do a full analysis of the prologue. */ | |
999 | if (new_pc < pc + 20) | |
d80b854b | 1000 | new_pc = frv_analyze_prologue (gdbarch, pc, 0, 0); |
456f8b9d DB |
1001 | |
1002 | return new_pc; | |
1003 | } | |
1004 | ||
1cb761c7 | 1005 | |
9bc7b6c6 KB |
1006 | /* Examine the instruction pointed to by PC. If it corresponds to |
1007 | a call to __main, return the address of the next instruction. | |
1008 | Otherwise, return PC. */ | |
1009 | ||
1010 | static CORE_ADDR | |
1011 | frv_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1012 | { | |
e17a4113 | 1013 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
9bc7b6c6 KB |
1014 | gdb_byte buf[4]; |
1015 | unsigned long op; | |
1016 | CORE_ADDR orig_pc = pc; | |
1017 | ||
1018 | if (target_read_memory (pc, buf, 4)) | |
1019 | return pc; | |
e17a4113 | 1020 | op = extract_unsigned_integer (buf, 4, byte_order); |
9bc7b6c6 KB |
1021 | |
1022 | /* In PIC code, GR15 may be loaded from some offset off of FP prior | |
1023 | to the call instruction. | |
1024 | ||
1025 | Skip over this instruction if present. It won't be present in | |
0963b4bd | 1026 | non-PIC code, and even in PIC code, it might not be present. |
9bc7b6c6 KB |
1027 | (This is due to the fact that GR15, the FDPIC register, already |
1028 | contains the correct value.) | |
1029 | ||
1030 | The general form of the LDI is given first, followed by the | |
1031 | specific instruction with the GRi and GRk filled in as FP and | |
1032 | GR15. | |
1033 | ||
1034 | ldi @(GRi, d12), GRk | |
1035 | P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x00c80000 | |
1036 | 0 000000 1111111 000000 000000000000 = 0x01fc0000 | |
1037 | . . . . . . . . | |
1038 | ldi @(FP, d12), GR15 | |
1039 | P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x1ec82000 | |
1040 | 0 001111 1111111 000010 000000000000 = 0x7ffff000 | |
1041 | . . . . . . . . */ | |
1042 | ||
1043 | if ((op & 0x7ffff000) == 0x1ec82000) | |
1044 | { | |
1045 | pc += 4; | |
1046 | if (target_read_memory (pc, buf, 4)) | |
1047 | return orig_pc; | |
e17a4113 | 1048 | op = extract_unsigned_integer (buf, 4, byte_order); |
9bc7b6c6 KB |
1049 | } |
1050 | ||
1051 | /* The format of an FRV CALL instruction is as follows: | |
1052 | ||
1053 | call label24 | |
1054 | P HHHHHH 0001111 LLLLLLLLLLLLLLLLLL = 0x003c0000 | |
1055 | 0 000000 1111111 000000000000000000 = 0x01fc0000 | |
dda83cd7 | 1056 | . . . . . . . . |
9bc7b6c6 KB |
1057 | |
1058 | where label24 is constructed by concatenating the H bits with the | |
1059 | L bits. The call target is PC + (4 * sign_ext(label24)). */ | |
1060 | ||
1061 | if ((op & 0x01fc0000) == 0x003c0000) | |
1062 | { | |
1063 | LONGEST displ; | |
1064 | CORE_ADDR call_dest; | |
7cbd4a93 | 1065 | struct bound_minimal_symbol s; |
9bc7b6c6 KB |
1066 | |
1067 | displ = ((op & 0xfe000000) >> 7) | (op & 0x0003ffff); | |
1068 | if ((displ & 0x00800000) != 0) | |
1069 | displ |= ~((LONGEST) 0x00ffffff); | |
1070 | ||
1071 | call_dest = pc + 4 * displ; | |
1072 | s = lookup_minimal_symbol_by_pc (call_dest); | |
1073 | ||
7cbd4a93 | 1074 | if (s.minsym != NULL |
dda83cd7 | 1075 | && s.minsym->linkage_name () != NULL |
c9d95fa3 | 1076 | && strcmp (s.minsym->linkage_name (), "__main") == 0) |
9bc7b6c6 KB |
1077 | { |
1078 | pc += 4; | |
1079 | return pc; | |
1080 | } | |
1081 | } | |
1082 | return orig_pc; | |
1083 | } | |
1084 | ||
1085 | ||
1cb761c7 | 1086 | static struct frv_unwind_cache * |
8480a37e | 1087 | frv_frame_unwind_cache (const frame_info_ptr &this_frame, |
1cb761c7 | 1088 | void **this_prologue_cache) |
456f8b9d | 1089 | { |
94afd7a6 | 1090 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1cb761c7 | 1091 | struct frv_unwind_cache *info; |
8baa6f92 | 1092 | |
1cb761c7 | 1093 | if ((*this_prologue_cache)) |
9a3c8263 | 1094 | return (struct frv_unwind_cache *) (*this_prologue_cache); |
456f8b9d | 1095 | |
1cb761c7 KB |
1096 | info = FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache); |
1097 | (*this_prologue_cache) = info; | |
94afd7a6 | 1098 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
456f8b9d | 1099 | |
1cb761c7 | 1100 | /* Prologue analysis does the rest... */ |
d80b854b UW |
1101 | frv_analyze_prologue (gdbarch, |
1102 | get_frame_func (this_frame), this_frame, info); | |
456f8b9d | 1103 | |
1cb761c7 | 1104 | return info; |
456f8b9d DB |
1105 | } |
1106 | ||
456f8b9d | 1107 | static void |
cd31fb03 | 1108 | frv_extract_return_value (struct type *type, struct regcache *regcache, |
dda83cd7 | 1109 | gdb_byte *valbuf) |
456f8b9d | 1110 | { |
ac7936df | 1111 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1112 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
df86565b | 1113 | int len = type->length (); |
cd31fb03 KB |
1114 | |
1115 | if (len <= 4) | |
1116 | { | |
1117 | ULONGEST gpr8_val; | |
1118 | regcache_cooked_read_unsigned (regcache, 8, &gpr8_val); | |
e17a4113 | 1119 | store_unsigned_integer (valbuf, len, byte_order, gpr8_val); |
cd31fb03 KB |
1120 | } |
1121 | else if (len == 8) | |
1122 | { | |
1123 | ULONGEST regval; | |
0963b4bd | 1124 | |
cd31fb03 | 1125 | regcache_cooked_read_unsigned (regcache, 8, ®val); |
e17a4113 | 1126 | store_unsigned_integer (valbuf, 4, byte_order, regval); |
cd31fb03 | 1127 | regcache_cooked_read_unsigned (regcache, 9, ®val); |
e17a4113 | 1128 | store_unsigned_integer ((bfd_byte *) valbuf + 4, 4, byte_order, regval); |
cd31fb03 KB |
1129 | } |
1130 | else | |
f34652de | 1131 | internal_error (_("Illegal return value length: %d"), len); |
456f8b9d DB |
1132 | } |
1133 | ||
1cb761c7 KB |
1134 | static CORE_ADDR |
1135 | frv_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
456f8b9d | 1136 | { |
1cb761c7 | 1137 | /* Require dword alignment. */ |
5b03f266 | 1138 | return align_down (sp, 8); |
456f8b9d DB |
1139 | } |
1140 | ||
c4d10515 KB |
1141 | static CORE_ADDR |
1142 | find_func_descr (struct gdbarch *gdbarch, CORE_ADDR entry_point) | |
1143 | { | |
e17a4113 | 1144 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c4d10515 | 1145 | CORE_ADDR descr; |
948f8e3d | 1146 | gdb_byte valbuf[4]; |
35e08e03 KB |
1147 | CORE_ADDR start_addr; |
1148 | ||
1149 | /* If we can't find the function in the symbol table, then we assume | |
1150 | that the function address is already in descriptor form. */ | |
1151 | if (!find_pc_partial_function (entry_point, NULL, &start_addr, NULL) | |
1152 | || entry_point != start_addr) | |
1153 | return entry_point; | |
c4d10515 KB |
1154 | |
1155 | descr = frv_fdpic_find_canonical_descriptor (entry_point); | |
1156 | ||
1157 | if (descr != 0) | |
1158 | return descr; | |
1159 | ||
1160 | /* Construct a non-canonical descriptor from space allocated on | |
1161 | the stack. */ | |
1162 | ||
1163 | descr = value_as_long (value_allocate_space_in_inferior (8)); | |
e17a4113 | 1164 | store_unsigned_integer (valbuf, 4, byte_order, entry_point); |
c4d10515 | 1165 | write_memory (descr, valbuf, 4); |
e17a4113 | 1166 | store_unsigned_integer (valbuf, 4, byte_order, |
dda83cd7 | 1167 | frv_fdpic_find_global_pointer (entry_point)); |
c4d10515 KB |
1168 | write_memory (descr + 4, valbuf, 4); |
1169 | return descr; | |
1170 | } | |
1171 | ||
1172 | static CORE_ADDR | |
1173 | frv_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr, | |
dda83cd7 | 1174 | struct target_ops *targ) |
c4d10515 | 1175 | { |
e17a4113 | 1176 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c4d10515 KB |
1177 | CORE_ADDR entry_point; |
1178 | CORE_ADDR got_address; | |
1179 | ||
e17a4113 UW |
1180 | entry_point = get_target_memory_unsigned (targ, addr, 4, byte_order); |
1181 | got_address = get_target_memory_unsigned (targ, addr + 4, 4, byte_order); | |
c4d10515 KB |
1182 | |
1183 | if (got_address == frv_fdpic_find_global_pointer (entry_point)) | |
1184 | return entry_point; | |
1185 | else | |
1186 | return addr; | |
1187 | } | |
1188 | ||
456f8b9d | 1189 | static CORE_ADDR |
7d9b040b | 1190 | frv_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
dda83cd7 SM |
1191 | struct regcache *regcache, CORE_ADDR bp_addr, |
1192 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
1193 | function_call_return_method return_method, |
1194 | CORE_ADDR struct_addr) | |
456f8b9d | 1195 | { |
e17a4113 | 1196 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
456f8b9d DB |
1197 | int argreg; |
1198 | int argnum; | |
948f8e3d PA |
1199 | const gdb_byte *val; |
1200 | gdb_byte valbuf[4]; | |
456f8b9d DB |
1201 | struct value *arg; |
1202 | struct type *arg_type; | |
1203 | int len; | |
1204 | enum type_code typecode; | |
1205 | CORE_ADDR regval; | |
1206 | int stack_space; | |
1207 | int stack_offset; | |
c4d10515 | 1208 | enum frv_abi abi = frv_abi (gdbarch); |
7d9b040b | 1209 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
456f8b9d DB |
1210 | |
1211 | #if 0 | |
1212 | printf("Push %d args at sp = %x, struct_return=%d (%x)\n", | |
1213 | nargs, (int) sp, struct_return, struct_addr); | |
1214 | #endif | |
1215 | ||
1216 | stack_space = 0; | |
1217 | for (argnum = 0; argnum < nargs; ++argnum) | |
d0c97917 | 1218 | stack_space += align_up (args[argnum]->type ()->length (), 4); |
456f8b9d DB |
1219 | |
1220 | stack_space -= (6 * 4); | |
1221 | if (stack_space > 0) | |
1222 | sp -= stack_space; | |
1223 | ||
0963b4bd | 1224 | /* Make sure stack is dword aligned. */ |
5b03f266 | 1225 | sp = align_down (sp, 8); |
456f8b9d DB |
1226 | |
1227 | stack_offset = 0; | |
1228 | ||
1229 | argreg = 8; | |
1230 | ||
cf84fa6b | 1231 | if (return_method == return_method_struct) |
1cb761c7 | 1232 | regcache_cooked_write_unsigned (regcache, struct_return_regnum, |
dda83cd7 | 1233 | struct_addr); |
456f8b9d DB |
1234 | |
1235 | for (argnum = 0; argnum < nargs; ++argnum) | |
1236 | { | |
1237 | arg = args[argnum]; | |
d0c97917 | 1238 | arg_type = check_typedef (arg->type ()); |
df86565b | 1239 | len = arg_type->length (); |
78134374 | 1240 | typecode = arg_type->code (); |
456f8b9d DB |
1241 | |
1242 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
1243 | { | |
e17a4113 | 1244 | store_unsigned_integer (valbuf, 4, byte_order, |
9feb2d07 | 1245 | arg->address ()); |
456f8b9d DB |
1246 | typecode = TYPE_CODE_PTR; |
1247 | len = 4; | |
1248 | val = valbuf; | |
1249 | } | |
c4d10515 KB |
1250 | else if (abi == FRV_ABI_FDPIC |
1251 | && len == 4 | |
dda83cd7 | 1252 | && typecode == TYPE_CODE_PTR |
27710edb | 1253 | && arg_type->target_type ()->code () == TYPE_CODE_FUNC) |
c4d10515 KB |
1254 | { |
1255 | /* The FDPIC ABI requires function descriptors to be passed instead | |
1256 | of entry points. */ | |
e17a4113 | 1257 | CORE_ADDR addr = extract_unsigned_integer |
efaf1ae0 | 1258 | (arg->contents ().data (), 4, byte_order); |
e17a4113 UW |
1259 | addr = find_func_descr (gdbarch, addr); |
1260 | store_unsigned_integer (valbuf, 4, byte_order, addr); | |
c4d10515 KB |
1261 | typecode = TYPE_CODE_PTR; |
1262 | len = 4; | |
1263 | val = valbuf; | |
1264 | } | |
456f8b9d DB |
1265 | else |
1266 | { | |
efaf1ae0 | 1267 | val = arg->contents ().data (); |
456f8b9d DB |
1268 | } |
1269 | ||
1270 | while (len > 0) | |
1271 | { | |
1272 | int partial_len = (len < 4 ? len : 4); | |
1273 | ||
1274 | if (argreg < 14) | |
1275 | { | |
e17a4113 | 1276 | regval = extract_unsigned_integer (val, partial_len, byte_order); |
456f8b9d DB |
1277 | #if 0 |
1278 | printf(" Argnum %d data %x -> reg %d\n", | |
1279 | argnum, (int) regval, argreg); | |
1280 | #endif | |
1cb761c7 | 1281 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
456f8b9d DB |
1282 | ++argreg; |
1283 | } | |
1284 | else | |
1285 | { | |
1286 | #if 0 | |
1287 | printf(" Argnum %d data %x -> offset %d (%x)\n", | |
0963b4bd MS |
1288 | argnum, *((int *)val), stack_offset, |
1289 | (int) (sp + stack_offset)); | |
456f8b9d DB |
1290 | #endif |
1291 | write_memory (sp + stack_offset, val, partial_len); | |
5b03f266 | 1292 | stack_offset += align_up (partial_len, 4); |
456f8b9d DB |
1293 | } |
1294 | len -= partial_len; | |
1295 | val += partial_len; | |
1296 | } | |
1297 | } | |
456f8b9d | 1298 | |
1cb761c7 KB |
1299 | /* Set the return address. For the frv, the return breakpoint is |
1300 | always at BP_ADDR. */ | |
1301 | regcache_cooked_write_unsigned (regcache, lr_regnum, bp_addr); | |
1302 | ||
c4d10515 KB |
1303 | if (abi == FRV_ABI_FDPIC) |
1304 | { | |
1305 | /* Set the GOT register for the FDPIC ABI. */ | |
1306 | regcache_cooked_write_unsigned | |
1307 | (regcache, first_gpr_regnum + 15, | |
dda83cd7 | 1308 | frv_fdpic_find_global_pointer (func_addr)); |
c4d10515 KB |
1309 | } |
1310 | ||
1cb761c7 KB |
1311 | /* Finally, update the SP register. */ |
1312 | regcache_cooked_write_unsigned (regcache, sp_regnum, sp); | |
1313 | ||
456f8b9d DB |
1314 | return sp; |
1315 | } | |
1316 | ||
1317 | static void | |
cd31fb03 | 1318 | frv_store_return_value (struct type *type, struct regcache *regcache, |
dda83cd7 | 1319 | const gdb_byte *valbuf) |
456f8b9d | 1320 | { |
df86565b | 1321 | int len = type->length (); |
cd31fb03 KB |
1322 | |
1323 | if (len <= 4) | |
1324 | { | |
1325 | bfd_byte val[4]; | |
1326 | memset (val, 0, sizeof (val)); | |
1327 | memcpy (val + (4 - len), valbuf, len); | |
b66f5587 | 1328 | regcache->cooked_write (8, val); |
cd31fb03 KB |
1329 | } |
1330 | else if (len == 8) | |
1331 | { | |
b66f5587 SM |
1332 | regcache->cooked_write (8, valbuf); |
1333 | regcache->cooked_write (9, (bfd_byte *) valbuf + 4); | |
cd31fb03 | 1334 | } |
456f8b9d | 1335 | else |
f34652de | 1336 | internal_error (_("Don't know how to return a %d-byte value."), len); |
456f8b9d DB |
1337 | } |
1338 | ||
63807e1d | 1339 | static enum return_value_convention |
6a3a010b | 1340 | frv_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1341 | struct type *valtype, struct regcache *regcache, |
1342 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
4c8b6ae0 | 1343 | { |
78134374 SM |
1344 | int struct_return = valtype->code () == TYPE_CODE_STRUCT |
1345 | || valtype->code () == TYPE_CODE_UNION | |
1346 | || valtype->code () == TYPE_CODE_ARRAY; | |
4c8b6ae0 UW |
1347 | |
1348 | if (writebuf != NULL) | |
1349 | { | |
1350 | gdb_assert (!struct_return); | |
1351 | frv_store_return_value (valtype, regcache, writebuf); | |
1352 | } | |
1353 | ||
1354 | if (readbuf != NULL) | |
1355 | { | |
1356 | gdb_assert (!struct_return); | |
1357 | frv_extract_return_value (valtype, regcache, readbuf); | |
1358 | } | |
1359 | ||
1360 | if (struct_return) | |
1361 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1362 | else | |
1363 | return RETURN_VALUE_REGISTER_CONVENTION; | |
456f8b9d DB |
1364 | } |
1365 | ||
1cb761c7 KB |
1366 | /* Given a GDB frame, determine the address of the calling function's |
1367 | frame. This will be used to create a new GDB frame struct. */ | |
1368 | ||
1369 | static void | |
8480a37e | 1370 | frv_frame_this_id (const frame_info_ptr &this_frame, |
1cb761c7 KB |
1371 | void **this_prologue_cache, struct frame_id *this_id) |
1372 | { | |
1373 | struct frv_unwind_cache *info | |
94afd7a6 | 1374 | = frv_frame_unwind_cache (this_frame, this_prologue_cache); |
1cb761c7 KB |
1375 | CORE_ADDR base; |
1376 | CORE_ADDR func; | |
3b7344d5 | 1377 | struct bound_minimal_symbol msym_stack; |
1cb761c7 KB |
1378 | struct frame_id id; |
1379 | ||
1380 | /* The FUNC is easy. */ | |
94afd7a6 | 1381 | func = get_frame_func (this_frame); |
1cb761c7 | 1382 | |
1cb761c7 KB |
1383 | /* Check if the stack is empty. */ |
1384 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
4aeddc50 | 1385 | if (msym_stack.minsym && info->base == msym_stack.value_address ()) |
1cb761c7 KB |
1386 | return; |
1387 | ||
1388 | /* Hopefully the prologue analysis either correctly determined the | |
1389 | frame's base (which is the SP from the previous frame), or set | |
1390 | that base to "NULL". */ | |
1391 | base = info->prev_sp; | |
1392 | if (base == 0) | |
1393 | return; | |
1394 | ||
1395 | id = frame_id_build (base, func); | |
1cb761c7 KB |
1396 | (*this_id) = id; |
1397 | } | |
1398 | ||
94afd7a6 | 1399 | static struct value * |
8480a37e | 1400 | frv_frame_prev_register (const frame_info_ptr &this_frame, |
94afd7a6 | 1401 | void **this_prologue_cache, int regnum) |
1cb761c7 KB |
1402 | { |
1403 | struct frv_unwind_cache *info | |
94afd7a6 UW |
1404 | = frv_frame_unwind_cache (this_frame, this_prologue_cache); |
1405 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
1cb761c7 KB |
1406 | } |
1407 | ||
1408 | static const struct frame_unwind frv_frame_unwind = { | |
a154d838 | 1409 | "frv prologue", |
1cb761c7 | 1410 | NORMAL_FRAME, |
8fbca658 | 1411 | default_frame_unwind_stop_reason, |
1cb761c7 | 1412 | frv_frame_this_id, |
94afd7a6 UW |
1413 | frv_frame_prev_register, |
1414 | NULL, | |
1415 | default_frame_sniffer | |
1cb761c7 KB |
1416 | }; |
1417 | ||
1cb761c7 | 1418 | static CORE_ADDR |
8480a37e | 1419 | frv_frame_base_address (const frame_info_ptr &this_frame, void **this_cache) |
1cb761c7 KB |
1420 | { |
1421 | struct frv_unwind_cache *info | |
94afd7a6 | 1422 | = frv_frame_unwind_cache (this_frame, this_cache); |
1cb761c7 KB |
1423 | return info->base; |
1424 | } | |
1425 | ||
1426 | static const struct frame_base frv_frame_base = { | |
1427 | &frv_frame_unwind, | |
1428 | frv_frame_base_address, | |
1429 | frv_frame_base_address, | |
1430 | frv_frame_base_address | |
1431 | }; | |
1432 | ||
456f8b9d DB |
1433 | static struct gdbarch * |
1434 | frv_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1435 | { | |
7e295833 | 1436 | int elf_flags = 0; |
456f8b9d DB |
1437 | |
1438 | /* Check to see if we've already built an appropriate architecture | |
1439 | object for this executable. */ | |
1440 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1441 | if (arches) | |
1442 | return arches->gdbarch; | |
1443 | ||
1444 | /* Select the right tdep structure for this variant. */ | |
2b16913c SM |
1445 | gdbarch *gdbarch = gdbarch_alloc (&info, new_variant ()); |
1446 | frv_gdbarch_tdep *var = gdbarch_tdep<frv_gdbarch_tdep> (gdbarch); | |
1447 | ||
456f8b9d DB |
1448 | switch (info.bfd_arch_info->mach) |
1449 | { | |
1450 | case bfd_mach_frv: | |
1451 | case bfd_mach_frvsimple: | |
087ccc6a | 1452 | case bfd_mach_fr300: |
456f8b9d DB |
1453 | case bfd_mach_fr500: |
1454 | case bfd_mach_frvtomcat: | |
251a3ae3 | 1455 | case bfd_mach_fr550: |
456f8b9d DB |
1456 | set_variant_num_gprs (var, 64); |
1457 | set_variant_num_fprs (var, 64); | |
1458 | break; | |
1459 | ||
1460 | case bfd_mach_fr400: | |
b2d6d697 | 1461 | case bfd_mach_fr450: |
456f8b9d DB |
1462 | set_variant_num_gprs (var, 32); |
1463 | set_variant_num_fprs (var, 32); | |
1464 | break; | |
1465 | ||
1466 | default: | |
1467 | /* Never heard of this variant. */ | |
1468 | return 0; | |
1469 | } | |
7e295833 KB |
1470 | |
1471 | /* Extract the ELF flags, if available. */ | |
1472 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
1473 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
1474 | ||
1475 | if (elf_flags & EF_FRV_FDPIC) | |
1476 | set_variant_abi_fdpic (var); | |
1477 | ||
b2d6d697 KB |
1478 | if (elf_flags & EF_FRV_CPU_FR450) |
1479 | set_variant_scratch_registers (var); | |
1480 | ||
456f8b9d DB |
1481 | set_gdbarch_short_bit (gdbarch, 16); |
1482 | set_gdbarch_int_bit (gdbarch, 32); | |
1483 | set_gdbarch_long_bit (gdbarch, 32); | |
1484 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1485 | set_gdbarch_float_bit (gdbarch, 32); | |
1486 | set_gdbarch_double_bit (gdbarch, 64); | |
1487 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1488 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1489 | ||
1490 | set_gdbarch_num_regs (gdbarch, frv_num_regs); | |
6a748db6 KB |
1491 | set_gdbarch_num_pseudo_regs (gdbarch, frv_num_pseudo_regs); |
1492 | ||
456f8b9d | 1493 | set_gdbarch_sp_regnum (gdbarch, sp_regnum); |
0ba6dca9 | 1494 | set_gdbarch_deprecated_fp_regnum (gdbarch, fp_regnum); |
456f8b9d DB |
1495 | set_gdbarch_pc_regnum (gdbarch, pc_regnum); |
1496 | ||
1497 | set_gdbarch_register_name (gdbarch, frv_register_name); | |
7f398216 | 1498 | set_gdbarch_register_type (gdbarch, frv_register_type); |
526eef89 | 1499 | set_gdbarch_register_sim_regno (gdbarch, frv_register_sim_regno); |
456f8b9d | 1500 | |
6a748db6 | 1501 | set_gdbarch_pseudo_register_read (gdbarch, frv_pseudo_register_read); |
7f0f3b0f SM |
1502 | set_gdbarch_deprecated_pseudo_register_write (gdbarch, |
1503 | frv_pseudo_register_write); | |
6a748db6 | 1504 | |
456f8b9d | 1505 | set_gdbarch_skip_prologue (gdbarch, frv_skip_prologue); |
9bc7b6c6 | 1506 | set_gdbarch_skip_main_prologue (gdbarch, frv_skip_main_prologue); |
04180708 YQ |
1507 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, frv_breakpoint::kind_from_pc); |
1508 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, frv_breakpoint::bp_from_kind); | |
1208538e MK |
1509 | set_gdbarch_adjust_breakpoint_address |
1510 | (gdbarch, frv_adjust_breakpoint_address); | |
456f8b9d | 1511 | |
4c8b6ae0 | 1512 | set_gdbarch_return_value (gdbarch, frv_return_value); |
456f8b9d | 1513 | |
1cb761c7 | 1514 | /* Frame stuff. */ |
1cb761c7 | 1515 | set_gdbarch_frame_align (gdbarch, frv_frame_align); |
1cb761c7 | 1516 | frame_base_set_default (gdbarch, &frv_frame_base); |
5ecb7103 KB |
1517 | /* We set the sniffer lower down after the OSABI hooks have been |
1518 | established. */ | |
456f8b9d | 1519 | |
1cb761c7 KB |
1520 | /* Settings for calling functions in the inferior. */ |
1521 | set_gdbarch_push_dummy_call (gdbarch, frv_push_dummy_call); | |
456f8b9d DB |
1522 | |
1523 | /* Settings that should be unnecessary. */ | |
1524 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1525 | ||
456f8b9d DB |
1526 | /* Hardware watchpoint / breakpoint support. */ |
1527 | switch (info.bfd_arch_info->mach) | |
1528 | { | |
1529 | case bfd_mach_frv: | |
1530 | case bfd_mach_frvsimple: | |
087ccc6a | 1531 | case bfd_mach_fr300: |
456f8b9d DB |
1532 | case bfd_mach_fr500: |
1533 | case bfd_mach_frvtomcat: | |
1534 | /* fr500-style hardware debugging support. */ | |
1535 | var->num_hw_watchpoints = 4; | |
1536 | var->num_hw_breakpoints = 4; | |
1537 | break; | |
1538 | ||
1539 | case bfd_mach_fr400: | |
b2d6d697 | 1540 | case bfd_mach_fr450: |
456f8b9d DB |
1541 | /* fr400-style hardware debugging support. */ |
1542 | var->num_hw_watchpoints = 2; | |
1543 | var->num_hw_breakpoints = 4; | |
1544 | break; | |
1545 | ||
1546 | default: | |
1547 | /* Otherwise, assume we don't have hardware debugging support. */ | |
1548 | var->num_hw_watchpoints = 0; | |
1549 | var->num_hw_breakpoints = 0; | |
1550 | break; | |
1551 | } | |
1552 | ||
c4d10515 KB |
1553 | if (frv_abi (gdbarch) == FRV_ABI_FDPIC) |
1554 | set_gdbarch_convert_from_func_ptr_addr (gdbarch, | |
1555 | frv_convert_from_func_ptr_addr); | |
36482093 | 1556 | |
9e468e95 | 1557 | set_gdbarch_so_ops (gdbarch, &frv_so_ops); |
917630e4 | 1558 | |
5ecb7103 KB |
1559 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1560 | gdbarch_init_osabi (info, gdbarch); | |
1561 | ||
5ecb7103 | 1562 | /* Set the fallback (prologue based) frame sniffer. */ |
94afd7a6 | 1563 | frame_unwind_append_unwinder (gdbarch, &frv_frame_unwind); |
5ecb7103 | 1564 | |
186993b4 KB |
1565 | /* Enable TLS support. */ |
1566 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
dda83cd7 | 1567 | frv_fetch_objfile_link_map); |
186993b4 | 1568 | |
456f8b9d DB |
1569 | return gdbarch; |
1570 | } | |
1571 | ||
6c265988 | 1572 | void _initialize_frv_tdep (); |
456f8b9d | 1573 | void |
6c265988 | 1574 | _initialize_frv_tdep () |
456f8b9d | 1575 | { |
ec29a63c | 1576 | gdbarch_register (bfd_arch_frv, frv_gdbarch_init); |
456f8b9d | 1577 | } |