[thirdparty/binutils-gdb.git] / gdb / gdbserver / linux-mips-low.c

/* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
   Copyright (C) 1995-2013 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "server.h"
#include "linux-low.h"

#include <sys/ptrace.h>
#include <endian.h>

#include "gdb_proc_service.h"

/* Defined in auto-generated file mips-linux.c.  */
void init_registers_mips_linux (void);
/* Defined in auto-generated file mips-dsp-linux.c.  */
void init_registers_mips_dsp_linux (void);
/* Defined in auto-generated file mips64-linux.c.  */
void init_registers_mips64_linux (void);
/* Defined in auto-generated file mips64-dsp-linux.c.  */
void init_registers_mips64_dsp_linux (void);

#ifdef __mips64
#define init_registers_mips_linux init_registers_mips64_linux
#define init_registers_mips_dsp_linux init_registers_mips64_dsp_linux
#endif

#ifndef PTRACE_GET_THREAD_AREA
#define PTRACE_GET_THREAD_AREA 25
#endif

#ifdef HAVE_SYS_REG_H
#include <sys/reg.h>
#endif

#define mips_num_regs 73
#define mips_dsp_num_regs 80

#include <asm/ptrace.h>

#ifndef DSP_BASE
#define DSP_BASE 71
#define DSP_CONTROL 77
#endif

union mips_register
{
  unsigned char buf[8];

  /* Deliberately signed, for proper sign extension.  */
  int reg32;
  long long reg64;
};

/* Return the ptrace ``address'' of register REGNO. */

#define mips_base_regs							\
  -1,  1,  2,  3,  4,  5,  6,  7,					\
  8,  9,  10, 11, 12, 13, 14, 15,					\
  16, 17, 18, 19, 20, 21, 22, 23,					\
  24, 25, 26, 27, 28, 29, 30, 31,					\
									\
  -1, MMLO, MMHI, BADVADDR, CAUSE, PC,					\
									\
  FPR_BASE,      FPR_BASE + 1,  FPR_BASE + 2,  FPR_BASE + 3,		\
  FPR_BASE + 4,  FPR_BASE + 5,  FPR_BASE + 6,  FPR_BASE + 7,		\
  FPR_BASE + 8,  FPR_BASE + 9,  FPR_BASE + 10, FPR_BASE + 11,		\
  FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15,		\
  FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19,		\
  FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23,		\
  FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27,		\
  FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31,		\
  FPC_CSR, FPC_EIR

#define mips_dsp_regs							\
  DSP_BASE,      DSP_BASE + 1,  DSP_BASE + 2,  DSP_BASE + 3,		\
  DSP_BASE + 4,  DSP_BASE + 5,						\
  DSP_CONTROL

static int mips_regmap[mips_num_regs] = {
  mips_base_regs,
  0
};

static int mips_dsp_regmap[mips_dsp_num_regs] = {
  mips_base_regs,
  mips_dsp_regs,
  0
};

/* DSP registers are not in any regset and can only be accessed
   individually.  */

static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
  0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
};

/* Try peeking at an arbitrarily chosen DSP register and pick the available
   user register set accordingly.  */

static void
mips_arch_setup (void)
{
  static void (*init_registers) (void);

  gdb_assert (current_inferior);

  if (init_registers == NULL)
    {
      int pid = lwpid_of (get_thread_lwp (current_inferior));

      ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
      switch (errno)
	{
	case 0:
	  the_low_target.num_regs = mips_dsp_num_regs;
	  the_low_target.regmap = mips_dsp_regmap;
	  the_low_target.regset_bitmap = mips_dsp_regset_bitmap;
	  init_registers = init_registers_mips_dsp_linux;
	  break;
	case EIO:
	  the_low_target.num_regs = mips_num_regs;
	  the_low_target.regmap = mips_regmap;
	  the_low_target.regset_bitmap = NULL;
	  init_registers = init_registers_mips_linux;
	  break;
	default:
	  perror_with_name ("ptrace");
	  break;
	}
    }
  init_registers ();
}

/* From mips-linux-nat.c.  */

/* Pseudo registers can not be read.  ptrace does not provide a way to
   read (or set) PS_REGNUM, and there's no point in reading or setting
   ZERO_REGNUM.  We also can not set BADVADDR, CAUSE, or FCRIR via
   ptrace().  */

static int
mips_cannot_fetch_register (int regno)
{
  if (the_low_target.regmap[regno] == -1)
    return 1;

  if (find_regno ("r0") == regno)
    return 1;

  return 0;
}

static int
mips_cannot_store_register (int regno)
{
  if (the_low_target.regmap[regno] == -1)
    return 1;

  if (find_regno ("r0") == regno)
    return 1;

  if (find_regno ("cause") == regno)
    return 1;

  if (find_regno ("badvaddr") == regno)
    return 1;

  if (find_regno ("fir") == regno)
    return 1;

  return 0;
}

static CORE_ADDR
mips_get_pc (struct regcache *regcache)
{
  union mips_register pc;
  collect_register_by_name (regcache, "pc", pc.buf);
  return register_size (0) == 4 ? pc.reg32 : pc.reg64;
}

static void
mips_set_pc (struct regcache *regcache, CORE_ADDR pc)
{
  union mips_register newpc;
  if (register_size (0) == 4)
    newpc.reg32 = pc;
  else
    newpc.reg64 = pc;

  supply_register_by_name (regcache, "pc", newpc.buf);
}

/* Correct in either endianness.  */
static const unsigned int mips_breakpoint = 0x0005000d;
#define mips_breakpoint_len 4

/* We only place breakpoints in empty marker functions, and thread locking
   is outside of the function.  So rather than importing software single-step,
   we can just run until exit.  */
static CORE_ADDR
mips_reinsert_addr (void)
{
  struct regcache *regcache = get_thread_regcache (current_inferior, 1);
  union mips_register ra;
  collect_register_by_name (regcache, "r31", ra.buf);
  return register_size (0) == 4 ? ra.reg32 : ra.reg64;
}

static int
mips_breakpoint_at (CORE_ADDR where)
{
  unsigned int insn;

  (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
  if (insn == mips_breakpoint)
    return 1;

  /* If necessary, recognize more trap instructions here.  GDB only uses the
     one.  */
  return 0;
}

/* Fetch the thread-local storage pointer for libthread_db.  */

ps_err_e
ps_get_thread_area (const struct ps_prochandle *ph,
		    lwpid_t lwpid, int idx, void **base)
{
  if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
    return PS_ERR;

  /* IDX is the bias from the thread pointer to the beginning of the
     thread descriptor.  It has to be subtracted due to implementation
     quirks in libthread_db.  */
  *base = (void *) ((char *)*base - idx);

  return PS_OK;
}

#ifdef HAVE_PTRACE_GETREGS

static void
mips_collect_register (struct regcache *regcache,
		       int use_64bit, int regno, union mips_register *reg)
{
  union mips_register tmp_reg;

  if (use_64bit)
    {
      collect_register (regcache, regno, &tmp_reg.reg64);
      *reg = tmp_reg;
    }
  else
    {
      collect_register (regcache, regno, &tmp_reg.reg32);
      reg->reg64 = tmp_reg.reg32;
    }
}

static void
mips_supply_register (struct regcache *regcache,
		      int use_64bit, int regno, const union mips_register *reg)
{
  int offset = 0;

  /* For big-endian 32-bit targets, ignore the high four bytes of each
     eight-byte slot.  */
  if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
    offset = 4;

  supply_register (regcache, regno, reg->buf + offset);
}

static void
mips_collect_register_32bit (struct regcache *regcache,
			     int use_64bit, int regno, unsigned char *buf)
{
  union mips_register tmp_reg;
  int reg32;

  mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
  reg32 = tmp_reg.reg64;
  memcpy (buf, &reg32, 4);
}

static void
mips_supply_register_32bit (struct regcache *regcache,
			    int use_64bit, int regno, const unsigned char *buf)
{
  union mips_register tmp_reg;
  int reg32;

  memcpy (&reg32, buf, 4);
  tmp_reg.reg64 = reg32;
  mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
}

static void
mips_fill_gregset (struct regcache *regcache, void *buf)
{
  union mips_register *regset = buf;
  int i, use_64bit;

  use_64bit = (register_size (0) == 8);

  for (i = 1; i < 32; i++)
    mips_collect_register (regcache, use_64bit, i, regset + i);

  mips_collect_register (regcache, use_64bit,
			 find_regno ("lo"), regset + 32);
  mips_collect_register (regcache, use_64bit,
			 find_regno ("hi"), regset + 33);
  mips_collect_register (regcache, use_64bit,
			 find_regno ("pc"), regset + 34);
  mips_collect_register (regcache, use_64bit,
			 find_regno ("badvaddr"), regset + 35);
  mips_collect_register (regcache, use_64bit,
			 find_regno ("status"), regset + 36);
  mips_collect_register (regcache, use_64bit,
			 find_regno ("cause"), regset + 37);

  mips_collect_register (regcache, use_64bit,
			 find_regno ("restart"), regset + 0);
}

static void
mips_store_gregset (struct regcache *regcache, const void *buf)
{
  const union mips_register *regset = buf;
  int i, use_64bit;

  use_64bit = (register_size (0) == 8);

  for (i = 0; i < 32; i++)
    mips_supply_register (regcache, use_64bit, i, regset + i);

  mips_supply_register (regcache, use_64bit, find_regno ("lo"), regset + 32);
  mips_supply_register (regcache, use_64bit, find_regno ("hi"), regset + 33);
  mips_supply_register (regcache, use_64bit, find_regno ("pc"), regset + 34);
  mips_supply_register (regcache, use_64bit,
			find_regno ("badvaddr"), regset + 35);
  mips_supply_register (regcache, use_64bit,
			find_regno ("status"), regset + 36);
  mips_supply_register (regcache, use_64bit,
			find_regno ("cause"), regset + 37);

  mips_supply_register (regcache, use_64bit,
			find_regno ("restart"), regset + 0);
}

static void
mips_fill_fpregset (struct regcache *regcache, void *buf)
{
  union mips_register *regset = buf;
  int i, use_64bit, first_fp, big_endian;

  use_64bit = (register_size (0) == 8);
  first_fp = find_regno ("f0");
  big_endian = (__BYTE_ORDER == __BIG_ENDIAN);

  /* See GDB for a discussion of this peculiar layout.  */
  for (i = 0; i < 32; i++)
    if (use_64bit)
      collect_register (regcache, first_fp + i, regset[i].buf);
    else
      collect_register (regcache, first_fp + i,
			regset[i & ~1].buf + 4 * (big_endian != (i & 1)));

  mips_collect_register_32bit (regcache, use_64bit,
			       find_regno ("fcsr"), regset[32].buf);
  mips_collect_register_32bit (regcache, use_64bit, find_regno ("fir"),
			       regset[32].buf + 4);
}

static void
mips_store_fpregset (struct regcache *regcache, const void *buf)
{
  const union mips_register *regset = buf;
  int i, use_64bit, first_fp, big_endian;

  use_64bit = (register_size (0) == 8);
  first_fp = find_regno ("f0");
  big_endian = (__BYTE_ORDER == __BIG_ENDIAN);

  /* See GDB for a discussion of this peculiar layout.  */
  for (i = 0; i < 32; i++)
    if (use_64bit)
      supply_register (regcache, first_fp + i, regset[i].buf);
    else
      supply_register (regcache, first_fp + i,
		       regset[i & ~1].buf + 4 * (big_endian != (i & 1)));

  mips_supply_register_32bit (regcache, use_64bit,
			      find_regno ("fcsr"), regset[32].buf);
  mips_supply_register_32bit (regcache, use_64bit, find_regno ("fir"),
			      regset[32].buf + 4);
}
#endif /* HAVE_PTRACE_GETREGS */

struct regset_info target_regsets[] = {
#ifdef HAVE_PTRACE_GETREGS
  { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
    mips_fill_gregset, mips_store_gregset },
  { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
    mips_fill_fpregset, mips_store_fpregset },
#endif /* HAVE_PTRACE_GETREGS */
  { 0, 0, 0, -1, -1, NULL, NULL }
};

struct linux_target_ops the_low_target = {
  mips_arch_setup,
  -1,
  NULL,
  NULL,
  mips_cannot_fetch_register,
  mips_cannot_store_register,
  NULL, /* fetch_register */
  mips_get_pc,
  mips_set_pc,
  (const unsigned char *) &mips_breakpoint,
  mips_breakpoint_len,
  mips_reinsert_addr,
  0,
  mips_breakpoint_at,
};
Commit	Line	Data
0a30fbc4	1	/* GNU/Linux/MIPS specific low level interface, for the remote server for GDB.
28e7fd62	2	Copyright (C) 1995-2013 Free Software Foundation, Inc.
0a30fbc4 DJ	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
a9762ec7	8	the Free Software Foundation; either version 3 of the License, or
0a30fbc4 DJ	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
a9762ec7	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
0a30fbc4 DJ	18
0a30fbc4 DJ	19	#include "server.h"
58caa3dc	20	#include "linux-low.h"
0a30fbc4	21
21b0f40c	22	#include <sys/ptrace.h>
186947f7	23	#include <endian.h>
21b0f40c DJ	24
	25	#include "gdb_proc_service.h"
	26
d05b4ac3 UW	27	/* Defined in auto-generated file mips-linux.c. */
d05b4ac3 UW	28	void init_registers_mips_linux (void);
1faeff08 MR	29	/* Defined in auto-generated file mips-dsp-linux.c. */
1faeff08 MR	30	void init_registers_mips_dsp_linux (void);
d05b4ac3 UW	31	/* Defined in auto-generated file mips64-linux.c. */
d05b4ac3 UW	32	void init_registers_mips64_linux (void);
1faeff08 MR	33	/* Defined in auto-generated file mips64-dsp-linux.c. */
	34	void init_registers_mips64_dsp_linux (void);
	35
	36	#ifdef __mips64
	37	#define init_registers_mips_linux init_registers_mips64_linux
	38	#define init_registers_mips_dsp_linux init_registers_mips64_dsp_linux
	39	#endif
d05b4ac3	40
21b0f40c DJ	41	#ifndef PTRACE_GET_THREAD_AREA
	42	#define PTRACE_GET_THREAD_AREA 25
	43	#endif
	44
0a30fbc4 DJ	45	#ifdef HAVE_SYS_REG_H
	46	#include <sys/reg.h>
	47	#endif
	48
117ce543	49	#define mips_num_regs 73
1faeff08	50	#define mips_dsp_num_regs 80
0a30fbc4 DJ	51
	52	#include <asm/ptrace.h>
	53
1faeff08 MR	54	#ifndef DSP_BASE
	55	#define DSP_BASE 71
	56	#define DSP_CONTROL 77
	57	#endif
	58
186947f7 DJ	59	union mips_register
	60	{
	61	unsigned char buf[8];
	62
	63	/* Deliberately signed, for proper sign extension. */
	64	int reg32;
	65	long long reg64;
	66	};
	67
0a30fbc4 DJ	68	/* Return the ptrace ``address'' of register REGNO. */
0a30fbc4 DJ	69
1faeff08 MR	70	#define mips_base_regs \
	71	-1, 1, 2, 3, 4, 5, 6, 7, \
	72	8, 9, 10, 11, 12, 13, 14, 15, \
	73	16, 17, 18, 19, 20, 21, 22, 23, \
	74	24, 25, 26, 27, 28, 29, 30, 31, \
	75	\
	76	-1, MMLO, MMHI, BADVADDR, CAUSE, PC, \
	77	\
	78	FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3, \
	79	FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7, \
	80	FPR_BASE + 8, FPR_BASE + 9, FPR_BASE + 10, FPR_BASE + 11, \
	81	FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15, \
	82	FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19, \
	83	FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23, \
	84	FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27, \
	85	FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31, \
	86	FPC_CSR, FPC_EIR
	87
	88	#define mips_dsp_regs \
	89	DSP_BASE, DSP_BASE + 1, DSP_BASE + 2, DSP_BASE + 3, \
	90	DSP_BASE + 4, DSP_BASE + 5, \
	91	DSP_CONTROL
	92
	93	static int mips_regmap[mips_num_regs] = {
	94	mips_base_regs,
	95	0
	96	};
0a30fbc4	97
1faeff08 MR	98	static int mips_dsp_regmap[mips_dsp_num_regs] = {
	99	mips_base_regs,
	100	mips_dsp_regs,
	101	0
	102	};
0a30fbc4	103
1faeff08 MR	104	/* DSP registers are not in any regset and can only be accessed
1faeff08 MR	105	individually. */
0a30fbc4	106
1faeff08 MR	107	static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = {
1faeff08 MR	108	0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80
0a30fbc4 DJ	109	};
0a30fbc4 DJ	110
1faeff08 MR	111	/* Try peeking at an arbitrarily chosen DSP register and pick the available
	112	user register set accordingly. */
	113
	114	static void
	115	mips_arch_setup (void)
	116	{
	117	static void (*init_registers) (void);
	118
	119	gdb_assert (current_inferior);
	120
	121	if (init_registers == NULL)
	122	{
	123	int pid = lwpid_of (get_thread_lwp (current_inferior));
	124
	125	ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0);
	126	switch (errno)
	127	{
	128	case 0:
	129	the_low_target.num_regs = mips_dsp_num_regs;
	130	the_low_target.regmap = mips_dsp_regmap;
	131	the_low_target.regset_bitmap = mips_dsp_regset_bitmap;
	132	init_registers = init_registers_mips_dsp_linux;
	133	break;
	134	case EIO:
	135	the_low_target.num_regs = mips_num_regs;
	136	the_low_target.regmap = mips_regmap;
	137	the_low_target.regset_bitmap = NULL;
	138	init_registers = init_registers_mips_linux;
	139	break;
	140	default:
	141	perror_with_name ("ptrace");
	142	break;
	143	}
	144	}
	145	init_registers ();
	146	}
	147
0a30fbc4 DJ	148	/* From mips-linux-nat.c. */
	149
	150	/* Pseudo registers can not be read. ptrace does not provide a way to
	151	read (or set) PS_REGNUM, and there's no point in reading or setting
	152	ZERO_REGNUM. We also can not set BADVADDR, CAUSE, or FCRIR via
	153	ptrace(). */
	154
2ec06d2e DJ	155	static int
2ec06d2e DJ	156	mips_cannot_fetch_register (int regno)
0a30fbc4	157	{
1faeff08	158	if (the_low_target.regmap[regno] == -1)
0a30fbc4 DJ	159	return 1;
0a30fbc4 DJ	160
117ce543	161	if (find_regno ("r0") == regno)
0a30fbc4 DJ	162	return 1;
	163
	164	return 0;
	165	}
	166
2ec06d2e DJ	167	static int
2ec06d2e DJ	168	mips_cannot_store_register (int regno)
0a30fbc4	169	{
1faeff08	170	if (the_low_target.regmap[regno] == -1)
0a30fbc4 DJ	171	return 1;
0a30fbc4 DJ	172
117ce543	173	if (find_regno ("r0") == regno)
0a30fbc4 DJ	174	return 1;
0a30fbc4 DJ	175
1d33e73a	176	if (find_regno ("cause") == regno)
0a30fbc4 DJ	177	return 1;
0a30fbc4 DJ	178
117ce543	179	if (find_regno ("badvaddr") == regno)
0a30fbc4 DJ	180	return 1;
0a30fbc4 DJ	181
1d33e73a	182	if (find_regno ("fir") == regno)
0a30fbc4 DJ	183	return 1;
	184
	185	return 0;
	186	}
2ec06d2e	187
0d62e5e8	188	static CORE_ADDR
442ea881	189	mips_get_pc (struct regcache *regcache)
0d62e5e8	190	{
186947f7	191	union mips_register pc;
442ea881	192	collect_register_by_name (regcache, "pc", pc.buf);
186947f7	193	return register_size (0) == 4 ? pc.reg32 : pc.reg64;
0d62e5e8 DJ	194	}
	195
	196	static void
442ea881	197	mips_set_pc (struct regcache *regcache, CORE_ADDR pc)
0d62e5e8	198	{
186947f7 DJ	199	union mips_register newpc;
	200	if (register_size (0) == 4)
	201	newpc.reg32 = pc;
	202	else
	203	newpc.reg64 = pc;
	204
442ea881	205	supply_register_by_name (regcache, "pc", newpc.buf);
0d62e5e8 DJ	206	}
	207
	208	/* Correct in either endianness. */
186947f7	209	static const unsigned int mips_breakpoint = 0x0005000d;
0d62e5e8 DJ	210	#define mips_breakpoint_len 4
	211
	212	/* We only place breakpoints in empty marker functions, and thread locking
	213	is outside of the function. So rather than importing software single-step,
	214	we can just run until exit. */
	215	static CORE_ADDR
442ea881	216	mips_reinsert_addr (void)
0d62e5e8	217	{
442ea881	218	struct regcache *regcache = get_thread_regcache (current_inferior, 1);
186947f7	219	union mips_register ra;
442ea881	220	collect_register_by_name (regcache, "r31", ra.buf);
186947f7	221	return register_size (0) == 4 ? ra.reg32 : ra.reg64;
0d62e5e8 DJ	222	}
	223
	224	static int
	225	mips_breakpoint_at (CORE_ADDR where)
	226	{
186947f7	227	unsigned int insn;
0d62e5e8	228
f450004a	229	(the_target->read_memory) (where, (unsigned char ) &insn, 4);
0d62e5e8 DJ	230	if (insn == mips_breakpoint)
	231	return 1;
	232
	233	/* If necessary, recognize more trap instructions here. GDB only uses the
	234	one. */
	235	return 0;
	236	}
	237
21b0f40c DJ	238	/* Fetch the thread-local storage pointer for libthread_db. */
	239
	240	ps_err_e
	241	ps_get_thread_area (const struct ps_prochandle *ph,
1b3f6016	242	lwpid_t lwpid, int idx, void **base)
21b0f40c DJ	243	{
	244	if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
	245	return PS_ERR;
	246
	247	/* IDX is the bias from the thread pointer to the beginning of the
	248	thread descriptor. It has to be subtracted due to implementation
	249	quirks in libthread_db. */
	250	base = (void ) ((char )base - idx);
	251
	252	return PS_OK;
	253	}
	254
186947f7 DJ	255	#ifdef HAVE_PTRACE_GETREGS
	256
	257	static void
442ea881 PA	258	mips_collect_register (struct regcache *regcache,
442ea881 PA	259	int use_64bit, int regno, union mips_register *reg)
186947f7 DJ	260	{
	261	union mips_register tmp_reg;
	262
	263	if (use_64bit)
	264	{
442ea881	265	collect_register (regcache, regno, &tmp_reg.reg64);
186947f7 DJ	266	*reg = tmp_reg;
	267	}
	268	else
	269	{
442ea881	270	collect_register (regcache, regno, &tmp_reg.reg32);
186947f7 DJ	271	reg->reg64 = tmp_reg.reg32;
	272	}
	273	}
	274
	275	static void
442ea881 PA	276	mips_supply_register (struct regcache *regcache,
442ea881 PA	277	int use_64bit, int regno, const union mips_register *reg)
186947f7 DJ	278	{
	279	int offset = 0;
	280
	281	/* For big-endian 32-bit targets, ignore the high four bytes of each
	282	eight-byte slot. */
	283	if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit)
	284	offset = 4;
	285
442ea881	286	supply_register (regcache, regno, reg->buf + offset);
186947f7 DJ	287	}
	288
	289	static void
442ea881 PA	290	mips_collect_register_32bit (struct regcache *regcache,
442ea881 PA	291	int use_64bit, int regno, unsigned char *buf)
186947f7 DJ	292	{
	293	union mips_register tmp_reg;
	294	int reg32;
	295
442ea881	296	mips_collect_register (regcache, use_64bit, regno, &tmp_reg);
186947f7 DJ	297	reg32 = tmp_reg.reg64;
	298	memcpy (buf, &reg32, 4);
	299	}
	300
	301	static void
442ea881 PA	302	mips_supply_register_32bit (struct regcache *regcache,
442ea881 PA	303	int use_64bit, int regno, const unsigned char *buf)
186947f7 DJ	304	{
	305	union mips_register tmp_reg;
	306	int reg32;
	307
	308	memcpy (&reg32, buf, 4);
	309	tmp_reg.reg64 = reg32;
442ea881	310	mips_supply_register (regcache, use_64bit, regno, &tmp_reg);
186947f7 DJ	311	}
	312
	313	static void
442ea881	314	mips_fill_gregset (struct regcache regcache, void buf)
186947f7 DJ	315	{
	316	union mips_register *regset = buf;
	317	int i, use_64bit;
	318
	319	use_64bit = (register_size (0) == 8);
	320
117ce543	321	for (i = 1; i < 32; i++)
442ea881 PA	322	mips_collect_register (regcache, use_64bit, i, regset + i);
	323
	324	mips_collect_register (regcache, use_64bit,
	325	find_regno ("lo"), regset + 32);
	326	mips_collect_register (regcache, use_64bit,
	327	find_regno ("hi"), regset + 33);
	328	mips_collect_register (regcache, use_64bit,
	329	find_regno ("pc"), regset + 34);
	330	mips_collect_register (regcache, use_64bit,
	331	find_regno ("badvaddr"), regset + 35);
	332	mips_collect_register (regcache, use_64bit,
	333	find_regno ("status"), regset + 36);
	334	mips_collect_register (regcache, use_64bit,
	335	find_regno ("cause"), regset + 37);
	336
	337	mips_collect_register (regcache, use_64bit,
	338	find_regno ("restart"), regset + 0);
186947f7 DJ	339	}
	340
	341	static void
442ea881	342	mips_store_gregset (struct regcache regcache, const void buf)
186947f7 DJ	343	{
	344	const union mips_register *regset = buf;
	345	int i, use_64bit;
	346
	347	use_64bit = (register_size (0) == 8);
	348
	349	for (i = 0; i < 32; i++)
442ea881 PA	350	mips_supply_register (regcache, use_64bit, i, regset + i);
	351
	352	mips_supply_register (regcache, use_64bit, find_regno ("lo"), regset + 32);
	353	mips_supply_register (regcache, use_64bit, find_regno ("hi"), regset + 33);
	354	mips_supply_register (regcache, use_64bit, find_regno ("pc"), regset + 34);
	355	mips_supply_register (regcache, use_64bit,
	356	find_regno ("badvaddr"), regset + 35);
	357	mips_supply_register (regcache, use_64bit,
	358	find_regno ("status"), regset + 36);
	359	mips_supply_register (regcache, use_64bit,
	360	find_regno ("cause"), regset + 37);
	361
	362	mips_supply_register (regcache, use_64bit,
	363	find_regno ("restart"), regset + 0);
186947f7 DJ	364	}
	365
	366	static void
442ea881	367	mips_fill_fpregset (struct regcache regcache, void buf)
186947f7 DJ	368	{
	369	union mips_register *regset = buf;
	370	int i, use_64bit, first_fp, big_endian;
	371
	372	use_64bit = (register_size (0) == 8);
	373	first_fp = find_regno ("f0");
	374	big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
	375
	376	/* See GDB for a discussion of this peculiar layout. */
	377	for (i = 0; i < 32; i++)
	378	if (use_64bit)
442ea881	379	collect_register (regcache, first_fp + i, regset[i].buf);
186947f7	380	else
442ea881	381	collect_register (regcache, first_fp + i,
186947f7 DJ	382	regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
186947f7 DJ	383
442ea881 PA	384	mips_collect_register_32bit (regcache, use_64bit,
	385	find_regno ("fcsr"), regset[32].buf);
	386	mips_collect_register_32bit (regcache, use_64bit, find_regno ("fir"),
186947f7 DJ	387	regset[32].buf + 4);
	388	}
	389
	390	static void
442ea881	391	mips_store_fpregset (struct regcache regcache, const void buf)
186947f7 DJ	392	{
	393	const union mips_register *regset = buf;
	394	int i, use_64bit, first_fp, big_endian;
	395
	396	use_64bit = (register_size (0) == 8);
	397	first_fp = find_regno ("f0");
	398	big_endian = (__BYTE_ORDER == __BIG_ENDIAN);
	399
	400	/* See GDB for a discussion of this peculiar layout. */
	401	for (i = 0; i < 32; i++)
	402	if (use_64bit)
442ea881	403	supply_register (regcache, first_fp + i, regset[i].buf);
186947f7	404	else
442ea881	405	supply_register (regcache, first_fp + i,
186947f7 DJ	406	regset[i & ~1].buf + 4 * (big_endian != (i & 1)));
186947f7 DJ	407
442ea881 PA	408	mips_supply_register_32bit (regcache, use_64bit,
	409	find_regno ("fcsr"), regset[32].buf);
	410	mips_supply_register_32bit (regcache, use_64bit, find_regno ("fir"),
186947f7 DJ	411	regset[32].buf + 4);
	412	}
	413	#endif /* HAVE_PTRACE_GETREGS */
	414
	415	struct regset_info target_regsets[] = {
	416	#ifdef HAVE_PTRACE_GETREGS
1570b33e	417	{ PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS,
186947f7	418	mips_fill_gregset, mips_store_gregset },
1570b33e	419	{ PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS,
186947f7 DJ	420	mips_fill_fpregset, mips_store_fpregset },
186947f7 DJ	421	#endif /* HAVE_PTRACE_GETREGS */
1570b33e	422	{ 0, 0, 0, -1, -1, NULL, NULL }
186947f7 DJ	423	};
186947f7 DJ	424
2ec06d2e	425	struct linux_target_ops the_low_target = {
1faeff08 MR	426	mips_arch_setup,
	427	-1,
	428	NULL,
	429	NULL,
2ec06d2e DJ	430	mips_cannot_fetch_register,
2ec06d2e DJ	431	mips_cannot_store_register,
c14dfd32	432	NULL, /* fetch_register */
0d62e5e8 DJ	433	mips_get_pc,
0d62e5e8 DJ	434	mips_set_pc,
f450004a	435	(const unsigned char *) &mips_breakpoint,
0d62e5e8 DJ	436	mips_breakpoint_len,
	437	mips_reinsert_addr,
	438	0,
	439	mips_breakpoint_at,
2ec06d2e	440	};