[thirdparty/binutils-gdb.git] / gdb / i386-tdep.h

/* Target-dependent code for the i386.

   Copyright (C) 2001-2021 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef I386_TDEP_H
#define I386_TDEP_H

#include "gdbarch.h"
#include "infrun.h"
#include "expression.h"

struct frame_info;
struct gdbarch;
struct reggroup;
struct regset;
struct regcache;

/* GDB's i386 target supports both the 32-bit Intel Architecture
   (IA-32) and the 64-bit AMD x86-64 architecture.  Internally it uses
   a similar register layout for both.

   - General purpose registers
   - FPU data registers
   - FPU control registers
   - SSE data registers
   - SSE control register

   The general purpose registers for the x86-64 architecture are quite
   different from IA-32.  Therefore, gdbarch_fp0_regnum
   determines the register number at which the FPU data registers
   start.  The number of FPU data and control registers is the same
   for both architectures.  The number of SSE registers however,
   differs and is determined by the num_xmm_regs member of `struct
   gdbarch_tdep'.  */

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* i386 architecture specific information.  */
struct gdbarch_tdep
{
  /* General-purpose registers.  */
  int *gregset_reg_offset;
  int gregset_num_regs;
  size_t sizeof_gregset;

  /* Floating-point registers.  */
  size_t sizeof_fpregset;

  /* Register number for %st(0).  The register numbers for the other
     registers follow from this one.  Set this to -1 to indicate the
     absence of an FPU.  */
  int st0_regnum;

  /* Number of MMX registers.  */
  int num_mmx_regs;

  /* Register number for %mm0.  Set this to -1 to indicate the absence
     of MMX support.  */
  int mm0_regnum;

  /* Number of pseudo YMM registers.  */
  int num_ymm_regs;

  /* Register number for %ymm0.  Set this to -1 to indicate the absence
     of pseudo YMM register support.  */
  int ymm0_regnum;

  /* Number of AVX512 OpMask registers (K-registers)  */
  int num_k_regs;

  /* Register number for %k0.  Set this to -1 to indicate the absence
     of AVX512 OpMask register support.  */
  int k0_regnum;

  /* Number of pseudo ZMM registers ($zmm0-$zmm31).  */
  int num_zmm_regs;

  /* Register number for %zmm0.  Set this to -1 to indicate the absence
     of pseudo ZMM register support.  */
  int zmm0_regnum;

  /* Number of byte registers.  */
  int num_byte_regs;

  /* Register pseudo number for %al.  */
  int al_regnum;

  /* Number of pseudo word registers.  */
  int num_word_regs;

  /* Register number for %ax.  */
  int ax_regnum;

  /* Number of pseudo dword registers.  */
  int num_dword_regs;

  /* Register number for %eax.  Set this to -1 to indicate the absence
     of pseudo dword register support.  */
  int eax_regnum;

  /* Number of core registers.  */
  int num_core_regs;

  /* Number of SSE registers.  */
  int num_xmm_regs;

  /* Number of SSE registers added in AVX512.  */
  int num_xmm_avx512_regs;

  /* Register number of XMM16, the first XMM register added in AVX512.  */
  int xmm16_regnum;

  /* Number of YMM registers added in AVX512.  */
  int num_ymm_avx512_regs;

  /* Register number of YMM16, the first YMM register added in AVX512.  */
  int ymm16_regnum;

  /* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK
     register), excluding the x87 bit, which are supported by this GDB.  */

  uint64_t xcr0;

  /* Offset of XCR0 in XSAVE extended state.  */
  int xsave_xcr0_offset;

  /* Register names.  */
  const char * const *register_names;

  /* Register number for %ymm0h.  Set this to -1 to indicate the absence
     of upper YMM register support.  */
  int ymm0h_regnum;

  /* Upper YMM register names.  Only used for tdesc_numbered_register.  */
  const char * const *ymmh_register_names;

  /* Register number for %ymm16h.  Set this to -1 to indicate the absence
  of support for YMM16-31.  */
  int ymm16h_regnum;

  /* YMM16-31 register names.  Only used for tdesc_numbered_register.  */
  const char * const *ymm16h_register_names;

  /* Register number for %bnd0r.  Set this to -1 to indicate the absence
     bound registers.  */
  int bnd0r_regnum;

  /* Register number for pseudo register %bnd0.  Set this to -1 to indicate the absence
     bound registers.  */
  int bnd0_regnum;

  /* Register number for %bndcfgu. Set this to -1 to indicate the absence
     bound control registers.  */
  int bndcfgu_regnum;

  /* MPX register names.  Only used for tdesc_numbered_register.  */
  const char * const *mpx_register_names;

  /* Register number for %zmm0h.  Set this to -1 to indicate the absence
     of ZMM_HI256 register support.  */
  int zmm0h_regnum;

  /* OpMask register names.  */
  const char * const *k_register_names;

  /* ZMM register names.  Only used for tdesc_numbered_register.  */
  const char * const *zmmh_register_names;

  /* XMM16-31 register names.  Only used for tdesc_numbered_register.  */
  const char * const *xmm_avx512_register_names;

  /* YMM16-31 register names.  Only used for tdesc_numbered_register.  */
  const char * const *ymm_avx512_register_names;

  /* Number of PKEYS registers.  */
  int num_pkeys_regs;

  /* Register number for PKRU register.  */
  int pkru_regnum;

  /* PKEYS register names.  */
  const char * const *pkeys_register_names;

  /* Register number for %fsbase.  Set this to -1 to indicate the
     absence of segment base registers.  */
  int fsbase_regnum;

  /* Target description.  */
  const struct target_desc *tdesc;

  /* Register group function.  */
  gdbarch_register_reggroup_p_ftype *register_reggroup_p;

  /* Offset of saved PC in jmp_buf.  */
  int jb_pc_offset;

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* Address range where sigtramp lives.  */
  CORE_ADDR sigtramp_start;
  CORE_ADDR sigtramp_end;

  /* Detect sigtramp.  */
  int (*sigtramp_p) (struct frame_info *);

  /* Get address of sigcontext for sigtramp.  */
  CORE_ADDR (*sigcontext_addr) (struct frame_info *);

  /* Offset of registers in `struct sigcontext'.  */
  int *sc_reg_offset;
  int sc_num_regs;

  /* Offset of saved PC and SP in `struct sigcontext'.  Usage of these
     is deprecated, please use `sc_reg_offset' instead.  */
  int sc_pc_offset;
  int sc_sp_offset;

  /* ISA-specific data types.  */
  struct type *i386_mmx_type;
  struct type *i386_ymm_type;
  struct type *i386_zmm_type;
  struct type *i387_ext_type;
  struct type *i386_bnd_type;

  /* Process record/replay target.  */
  /* The map for registers because the AMD64's registers order
     in GDB is not same as I386 instructions.  */
  const int *record_regmap;
  /* Parse intx80 args.  */
  int (*i386_intx80_record) (struct regcache *regcache);
  /* Parse sysenter args.  */
  int (*i386_sysenter_record) (struct regcache *regcache);
  /* Parse syscall args.  */
  int (*i386_syscall_record) (struct regcache *regcache);

  /* Regsets. */
  const struct regset *fpregset;
};

/* Floating-point registers.  */

/* All FPU control registers (except for FIOFF and FOOFF) are 16-bit
   (at most) in the FPU, but are zero-extended to 32 bits in GDB's
   register cache.  */

/* Return non-zero if REGNUM matches the FP register and the FP
   register set is active.  */
extern int i386_fp_regnum_p (struct gdbarch *, int);
extern int i386_fpc_regnum_p (struct gdbarch *, int);

/* Register numbers of various important registers.  */

enum i386_regnum
{
  I386_EAX_REGNUM,		/* %eax */
  I386_ECX_REGNUM,		/* %ecx */
  I386_EDX_REGNUM,		/* %edx */
  I386_EBX_REGNUM,		/* %ebx */
  I386_ESP_REGNUM,		/* %esp */
  I386_EBP_REGNUM,		/* %ebp */
  I386_ESI_REGNUM,		/* %esi */
  I386_EDI_REGNUM,		/* %edi */
  I386_EIP_REGNUM,		/* %eip */
  I386_EFLAGS_REGNUM,		/* %eflags */
  I386_CS_REGNUM,		/* %cs */
  I386_SS_REGNUM,		/* %ss */
  I386_DS_REGNUM,		/* %ds */
  I386_ES_REGNUM,		/* %es */
  I386_FS_REGNUM,		/* %fs */
  I386_GS_REGNUM,		/* %gs */
  I386_ST0_REGNUM,		/* %st(0) */
  I386_MXCSR_REGNUM = 40,	/* %mxcsr */ 
  I386_YMM0H_REGNUM,		/* %ymm0h */
  I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7,
  I386_BND0R_REGNUM,
  I386_BND3R_REGNUM = I386_BND0R_REGNUM + 3,
  I386_BNDCFGU_REGNUM,
  I386_BNDSTATUS_REGNUM,
  I386_K0_REGNUM,		/* %k0 */
  I386_K7_REGNUM = I386_K0_REGNUM + 7,
  I386_ZMM0H_REGNUM,		/* %zmm0h */
  I386_ZMM7H_REGNUM = I386_ZMM0H_REGNUM + 7,
  I386_PKRU_REGNUM,
  I386_FSBASE_REGNUM,
  I386_GSBASE_REGNUM
};

/* Register numbers of RECORD_REGMAP.  */

enum record_i386_regnum
{
  X86_RECORD_REAX_REGNUM,
  X86_RECORD_RECX_REGNUM,
  X86_RECORD_REDX_REGNUM,
  X86_RECORD_REBX_REGNUM,
  X86_RECORD_RESP_REGNUM,
  X86_RECORD_REBP_REGNUM,
  X86_RECORD_RESI_REGNUM,
  X86_RECORD_REDI_REGNUM,
  X86_RECORD_R8_REGNUM,
  X86_RECORD_R9_REGNUM,
  X86_RECORD_R10_REGNUM,
  X86_RECORD_R11_REGNUM,
  X86_RECORD_R12_REGNUM,
  X86_RECORD_R13_REGNUM,
  X86_RECORD_R14_REGNUM,
  X86_RECORD_R15_REGNUM,
  X86_RECORD_REIP_REGNUM,
  X86_RECORD_EFLAGS_REGNUM,
  X86_RECORD_CS_REGNUM,
  X86_RECORD_SS_REGNUM,
  X86_RECORD_DS_REGNUM,
  X86_RECORD_ES_REGNUM,
  X86_RECORD_FS_REGNUM,
  X86_RECORD_GS_REGNUM,
};

#define I386_NUM_GREGS	16
#define I386_NUM_XREGS  9

#define I386_SSE_NUM_REGS	(I386_MXCSR_REGNUM + 1)
#define I386_AVX_NUM_REGS	(I386_YMM7H_REGNUM + 1)
#define I386_MPX_NUM_REGS	(I386_BNDSTATUS_REGNUM + 1)
#define I386_AVX512_NUM_REGS	(I386_ZMM7H_REGNUM + 1)
#define I386_PKEYS_NUM_REGS	(I386_PKRU_REGNUM + 1)
#define I386_NUM_REGS		(I386_GSBASE_REGNUM + 1)

/* Size of the largest register.  */
#define I386_MAX_REGISTER_SIZE	64

/* Types for i386-specific registers.  */
extern struct type *i387_ext_type (struct gdbarch *gdbarch);

/* Checks of different pseudo-registers.  */
extern int i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_word_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_xmm_avx512_regnum_p (struct gdbarch * gdbarch, int regnum);
extern int i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_k_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum);
extern bool i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum);

extern const char *i386_pseudo_register_name (struct gdbarch *gdbarch,
					      int regnum);
extern struct type *i386_pseudo_register_type (struct gdbarch *gdbarch,
					       int regnum);

extern void i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
						  readable_regcache *regcache,
						  int regnum,
						  struct value *result);

extern void i386_pseudo_register_write (struct gdbarch *gdbarch,
					struct regcache *regcache,
					int regnum, const gdb_byte *buf);

extern int i386_ax_pseudo_register_collect (struct gdbarch *gdbarch,
					    struct agent_expr *ax,
					    int regnum);

/* Segment selectors.  */
#define I386_SEL_RPL	0x0003  /* Requester's Privilege Level mask.  */
#define I386_SEL_UPL	0x0003	/* User Privilige Level.  */
#define I386_SEL_KPL	0x0000	/* Kernel Privilige Level.  */

/* The length of the longest i386 instruction (according to
   include/asm-i386/kprobes.h in Linux 2.6.  */
#define I386_MAX_INSN_LEN (16)

/* Functions exported from i386-tdep.c.  */
extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
					       CORE_ADDR pc, char *name);
extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch,
					  CORE_ADDR pc);

/* The "push_dummy_call" gdbarch method, optionally with the thiscall
   calling convention.  */
extern CORE_ADDR i386_thiscall_push_dummy_call (struct gdbarch *gdbarch,
						struct value *function,
						struct regcache *regcache,
						CORE_ADDR bp_addr,
						int nargs, struct value **args,
						CORE_ADDR sp,
						function_call_return_method
						return_method,
						CORE_ADDR struct_addr,
						bool thiscall);

/* Return whether the THIS_FRAME corresponds to a sigtramp routine.  */
extern int i386_sigtramp_p (struct frame_info *this_frame);

/* Return non-zero if REGNUM is a member of the specified group.  */
extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
				     struct reggroup *group);

/* Supply register REGNUM from the general-purpose register set REGSET
   to register cache REGCACHE.  If REGNUM is -1, do this for all
   registers in REGSET.  */
extern void i386_supply_gregset (const struct regset *regset,
				 struct regcache *regcache, int regnum,
				 const void *gregs, size_t len);

/* General-purpose register set. */
extern const struct regset i386_gregset;

/* Floating-point register set. */
extern const struct regset i386_fpregset;

/* Default iterator over core file register note sections.  */
extern void
  i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
				     iterate_over_regset_sections_cb *cb,
				     void *cb_data,
				     const struct regcache *regcache);

typedef buf_displaced_step_copy_insn_closure
  i386_displaced_step_copy_insn_closure;

extern displaced_step_copy_insn_closure_up i386_displaced_step_copy_insn
  (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
   struct regcache *regs);
extern void i386_displaced_step_fixup
  (struct gdbarch *gdbarch, displaced_step_copy_insn_closure *closure,
   CORE_ADDR from, CORE_ADDR to, regcache *regs);

/* Initialize a basic ELF architecture variant.  */
extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);

/* Initialize a SVR4 architecture variant.  */
extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);

/* Convert SVR4 register number REG to the appropriate register number
   used by GDB.  */
extern int i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg);

extern int i386_process_record (struct gdbarch *gdbarch,
				struct regcache *regcache, CORE_ADDR addr);
extern const struct target_desc *i386_target_description (uint64_t xcr0,
							  bool segments);

/* Return true iff the current target is MPX enabled.  */
extern int i386_mpx_enabled (void);
\f

/* Functions and variables exported from i386-bsd-tdep.c.  */

extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
extern CORE_ADDR i386fbsd_sigtramp_start_addr;
extern CORE_ADDR i386fbsd_sigtramp_end_addr;
extern CORE_ADDR i386obsd_sigtramp_start_addr;
extern CORE_ADDR i386obsd_sigtramp_end_addr;
extern int i386fbsd4_sc_reg_offset[];
extern int i386fbsd_sc_reg_offset[];
extern int i386obsd_sc_reg_offset[];
extern int i386bsd_sc_reg_offset[];

/* SystemTap related functions.  */

extern int i386_stap_is_single_operand (struct gdbarch *gdbarch,
					const char *s);

extern expr::operation_up i386_stap_parse_special_token
     (struct gdbarch *gdbarch, struct stap_parse_info *p);

#endif /* i386-tdep.h */
Commit	Line	Data
5716833c MK	1	/* Target-dependent code for the i386.
5716833c MK	2
3666a048	3	Copyright (C) 2001-2021 Free Software Foundation, Inc.
9a82579f JS	4
	5	This file is part of GDB.
	6
	7	This program is free software; you can redistribute it and/or modify
	8	it under the terms of the GNU General Public License as published by
a9762ec7	9	the Free Software Foundation; either version 3 of the License, or
9a82579f JS	10	(at your option) any later version.
	11
	12	This program is distributed in the hope that it will be useful,
	13	but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
a9762ec7	18	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9a82579f JS	19
	20	#ifndef I386_TDEP_H
	21	#define I386_TDEP_H
	22
0d12e84c	23	#include "gdbarch.h"
cfba9872	24	#include "infrun.h"
4c5e7a93	25	#include "expression.h"
cfba9872	26
da3331ec	27	struct frame_info;
5716833c MK	28	struct gdbarch;
5716833c MK	29	struct reggroup;
c783cbd6	30	struct regset;
5439edaa	31	struct regcache;
da3331ec	32
96297dab MK	33	/* GDB's i386 target supports both the 32-bit Intel Architecture
	34	(IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
	35	a similar register layout for both.
	36
	37	- General purpose registers
	38	- FPU data registers
	39	- FPU control registers
	40	- SSE data registers
	41	- SSE control register
	42
	43	The general purpose registers for the x86-64 architecture are quite
3e8c568d	44	different from IA-32. Therefore, gdbarch_fp0_regnum
96297dab MK	45	determines the register number at which the FPU data registers
	46	start. The number of FPU data and control registers is the same
	47	for both architectures. The number of SSE registers however,
	48	differs and is determined by the num_xmm_regs member of `struct
	49	gdbarch_tdep'. */
	50
8201327c	51	/* Convention for returning structures. */
3ce1502b	52
8201327c MK	53	enum struct_return
	54	{
	55	pcc_struct_return, /* Return "short" structures in memory. */
	56	reg_struct_return /* Return "short" structures in registers. */
3ce1502b MK	57	};
3ce1502b MK	58
96297dab MK	59	/* i386 architecture specific information. */
	60	struct gdbarch_tdep
	61	{
473f17b0	62	/* General-purpose registers. */
473f17b0 MK	63	int *gregset_reg_offset;
	64	int gregset_num_regs;
	65	size_t sizeof_gregset;
	66
	67	/* Floating-point registers. */
473f17b0 MK	68	size_t sizeof_fpregset;
473f17b0 MK	69
5716833c MK	70	/* Register number for %st(0). The register numbers for the other
	71	registers follow from this one. Set this to -1 to indicate the
	72	absence of an FPU. */
	73	int st0_regnum;
	74
1ba53b71 L	75	/* Number of MMX registers. */
	76	int num_mmx_regs;
	77
5716833c MK	78	/* Register number for %mm0. Set this to -1 to indicate the absence
	79	of MMX support. */
	80	int mm0_regnum;
	81
c131fcee L	82	/* Number of pseudo YMM registers. */
	83	int num_ymm_regs;
	84
	85	/* Register number for %ymm0. Set this to -1 to indicate the absence
	86	of pseudo YMM register support. */
	87	int ymm0_regnum;
	88
01f9f808 MS	89	/* Number of AVX512 OpMask registers (K-registers) */
	90	int num_k_regs;
	91
	92	/* Register number for %k0. Set this to -1 to indicate the absence
	93	of AVX512 OpMask register support. */
	94	int k0_regnum;
	95
	96	/* Number of pseudo ZMM registers ($zmm0-$zmm31). */
	97	int num_zmm_regs;
	98
	99	/* Register number for %zmm0. Set this to -1 to indicate the absence
	100	of pseudo ZMM register support. */
	101	int zmm0_regnum;
	102
1ba53b71 L	103	/* Number of byte registers. */
	104	int num_byte_regs;
	105
	106	/* Register pseudo number for %al. */
	107	int al_regnum;
	108
	109	/* Number of pseudo word registers. */
	110	int num_word_regs;
	111
	112	/* Register number for %ax. */
	113	int ax_regnum;
	114
	115	/* Number of pseudo dword registers. */
	116	int num_dword_regs;
	117
	118	/* Register number for %eax. Set this to -1 to indicate the absence
	119	of pseudo dword register support. */
	120	int eax_regnum;
	121
90884b2b L	122	/* Number of core registers. */
	123	int num_core_regs;
	124
96297dab MK	125	/* Number of SSE registers. */
96297dab MK	126	int num_xmm_regs;
8201327c	127
01f9f808 MS	128	/* Number of SSE registers added in AVX512. */
	129	int num_xmm_avx512_regs;
	130
	131	/* Register number of XMM16, the first XMM register added in AVX512. */
	132	int xmm16_regnum;
	133
	134	/* Number of YMM registers added in AVX512. */
	135	int num_ymm_avx512_regs;
	136
	137	/* Register number of YMM16, the first YMM register added in AVX512. */
	138	int ymm16_regnum;
	139
c131fcee	140	/* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK
1777feb0 MS	141	register), excluding the x87 bit, which are supported by this GDB. */
1777feb0 MS	142
c131fcee L	143	uint64_t xcr0;
	144
	145	/* Offset of XCR0 in XSAVE extended state. */
	146	int xsave_xcr0_offset;
	147
90884b2b	148	/* Register names. */
27087b7f	149	const char * const *register_names;
90884b2b	150
c131fcee L	151	/* Register number for %ymm0h. Set this to -1 to indicate the absence
	152	of upper YMM register support. */
	153	int ymm0h_regnum;
	154
	155	/* Upper YMM register names. Only used for tdesc_numbered_register. */
27087b7f	156	const char * const *ymmh_register_names;
c131fcee	157
01f9f808 MS	158	/* Register number for %ymm16h. Set this to -1 to indicate the absence
	159	of support for YMM16-31. */
	160	int ymm16h_regnum;
	161
	162	/* YMM16-31 register names. Only used for tdesc_numbered_register. */
27087b7f	163	const char * const *ymm16h_register_names;
01f9f808	164
1dbcd68c WT	165	/* Register number for %bnd0r. Set this to -1 to indicate the absence
	166	bound registers. */
	167	int bnd0r_regnum;
	168
	169	/* Register number for pseudo register %bnd0. Set this to -1 to indicate the absence
	170	bound registers. */
	171	int bnd0_regnum;
	172
	173	/* Register number for %bndcfgu. Set this to -1 to indicate the absence
	174	bound control registers. */
	175	int bndcfgu_regnum;
	176
	177	/* MPX register names. Only used for tdesc_numbered_register. */
27087b7f	178	const char * const *mpx_register_names;
1dbcd68c	179
01f9f808 MS	180	/* Register number for %zmm0h. Set this to -1 to indicate the absence
	181	of ZMM_HI256 register support. */
	182	int zmm0h_regnum;
	183
	184	/* OpMask register names. */
27087b7f	185	const char * const *k_register_names;
01f9f808 MS	186
01f9f808 MS	187	/* ZMM register names. Only used for tdesc_numbered_register. */
27087b7f	188	const char * const *zmmh_register_names;
01f9f808 MS	189
01f9f808 MS	190	/* XMM16-31 register names. Only used for tdesc_numbered_register. */
27087b7f	191	const char * const *xmm_avx512_register_names;
01f9f808 MS	192
01f9f808 MS	193	/* YMM16-31 register names. Only used for tdesc_numbered_register. */
27087b7f	194	const char * const *ymm_avx512_register_names;
01f9f808	195
51547df6 MS	196	/* Number of PKEYS registers. */
	197	int num_pkeys_regs;
	198
	199	/* Register number for PKRU register. */
	200	int pkru_regnum;
	201
	202	/* PKEYS register names. */
27087b7f	203	const char * const *pkeys_register_names;
51547df6	204
1163a4b7 JB	205	/* Register number for %fsbase. Set this to -1 to indicate the
	206	absence of segment base registers. */
	207	int fsbase_regnum;
	208
90884b2b L	209	/* Target description. */
	210	const struct target_desc *tdesc;
	211
	212	/* Register group function. */
c5bcd278	213	gdbarch_register_reggroup_p_ftype *register_reggroup_p;
90884b2b	214
8201327c MK	215	/* Offset of saved PC in jmp_buf. */
	216	int jb_pc_offset;
	217
	218	/* Convention for returning structures. */
	219	enum struct_return struct_return;
	220
8201327c MK	221	/* Address range where sigtramp lives. */
	222	CORE_ADDR sigtramp_start;
	223	CORE_ADDR sigtramp_end;
	224
911bc6ee MK	225	/* Detect sigtramp. */
	226	int (sigtramp_p) (struct frame_info );
	227
21d0e8a4 MK	228	/* Get address of sigcontext for sigtramp. */
	229	CORE_ADDR (sigcontext_addr) (struct frame_info );
	230
a3386186 MK	231	/* Offset of registers in `struct sigcontext'. */
	232	int *sc_reg_offset;
	233	int sc_num_regs;
	234
	235	/* Offset of saved PC and SP in `struct sigcontext'. Usage of these
	236	is deprecated, please use `sc_reg_offset' instead. */
8201327c	237	int sc_pc_offset;
21d0e8a4	238	int sc_sp_offset;
794ac428 UW	239
	240	/* ISA-specific data types. */
	241	struct type *i386_mmx_type;
c131fcee	242	struct type *i386_ymm_type;
01f9f808	243	struct type *i386_zmm_type;
27067745	244	struct type *i387_ext_type;
1dbcd68c	245	struct type *i386_bnd_type;
7ad10968 HZ	246
7ad10968 HZ	247	/* Process record/replay target. */
cf648174 HZ	248	/* The map for registers because the AMD64's registers order
	249	in GDB is not same as I386 instructions. */
	250	const int *record_regmap;
7ad10968 HZ	251	/* Parse intx80 args. */
	252	int (i386_intx80_record) (struct regcache regcache);
	253	/* Parse sysenter args. */
	254	int (i386_sysenter_record) (struct regcache regcache);
cf648174 HZ	255	/* Parse syscall args. */
cf648174 HZ	256	int (i386_syscall_record) (struct regcache regcache);
8f0435f7 AA	257
	258	/* Regsets. */
	259	const struct regset *fpregset;
96297dab MK	260	};
	261
	262	/* Floating-point registers. */
	263
30baf67b	264	/* All FPU control registers (except for FIOFF and FOOFF) are 16-bit
96297dab MK	265	(at most) in the FPU, but are zero-extended to 32 bits in GDB's
	266	register cache. */
	267
23a34459 AC	268	/* Return non-zero if REGNUM matches the FP register and the FP
23a34459 AC	269	register set is active. */
20a6ec49 MD	270	extern int i386_fp_regnum_p (struct gdbarch *, int);
20a6ec49 MD	271	extern int i386_fpc_regnum_p (struct gdbarch *, int);
96297dab	272
a3386186 MK	273	/* Register numbers of various important registers. */
a3386186 MK	274
bcf48cc7 MK	275	enum i386_regnum
	276	{
	277	I386_EAX_REGNUM, /* %eax */
	278	I386_ECX_REGNUM, /* %ecx */
	279	I386_EDX_REGNUM, /* %edx */
	280	I386_EBX_REGNUM, /* %ebx */
	281	I386_ESP_REGNUM, /* %esp */
	282	I386_EBP_REGNUM, /* %ebp */
	283	I386_ESI_REGNUM, /* %esi */
	284	I386_EDI_REGNUM, /* %edi */
	285	I386_EIP_REGNUM, /* %eip */
	286	I386_EFLAGS_REGNUM, /* %eflags */
2666fb59 MK	287	I386_CS_REGNUM, /* %cs */
2666fb59 MK	288	I386_SS_REGNUM, /* %ss */
e9ff708b AC	289	I386_DS_REGNUM, /* %ds */
	290	I386_ES_REGNUM, /* %es */
	291	I386_FS_REGNUM, /* %fs */
	292	I386_GS_REGNUM, /* %gs */
90884b2b	293	I386_ST0_REGNUM, /* %st(0) */
c131fcee L	294	I386_MXCSR_REGNUM = 40, /* %mxcsr */
c131fcee L	295	I386_YMM0H_REGNUM, /* %ymm0h */
1dbcd68c WT	296	I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7,
	297	I386_BND0R_REGNUM,
	298	I386_BND3R_REGNUM = I386_BND0R_REGNUM + 3,
	299	I386_BNDCFGU_REGNUM,
01f9f808 MS	300	I386_BNDSTATUS_REGNUM,
	301	I386_K0_REGNUM, /* %k0 */
	302	I386_K7_REGNUM = I386_K0_REGNUM + 7,
	303	I386_ZMM0H_REGNUM, /* %zmm0h */
51547df6	304	I386_ZMM7H_REGNUM = I386_ZMM0H_REGNUM + 7,
1163a4b7 JB	305	I386_PKRU_REGNUM,
	306	I386_FSBASE_REGNUM,
	307	I386_GSBASE_REGNUM
bcf48cc7	308	};
a3386186	309
cf648174 HZ	310	/* Register numbers of RECORD_REGMAP. */
	311
	312	enum record_i386_regnum
	313	{
	314	X86_RECORD_REAX_REGNUM,
	315	X86_RECORD_RECX_REGNUM,
	316	X86_RECORD_REDX_REGNUM,
	317	X86_RECORD_REBX_REGNUM,
	318	X86_RECORD_RESP_REGNUM,
	319	X86_RECORD_REBP_REGNUM,
	320	X86_RECORD_RESI_REGNUM,
	321	X86_RECORD_REDI_REGNUM,
	322	X86_RECORD_R8_REGNUM,
	323	X86_RECORD_R9_REGNUM,
	324	X86_RECORD_R10_REGNUM,
	325	X86_RECORD_R11_REGNUM,
	326	X86_RECORD_R12_REGNUM,
	327	X86_RECORD_R13_REGNUM,
	328	X86_RECORD_R14_REGNUM,
	329	X86_RECORD_R15_REGNUM,
	330	X86_RECORD_REIP_REGNUM,
	331	X86_RECORD_EFLAGS_REGNUM,
	332	X86_RECORD_CS_REGNUM,
	333	X86_RECORD_SS_REGNUM,
	334	X86_RECORD_DS_REGNUM,
	335	X86_RECORD_ES_REGNUM,
	336	X86_RECORD_FS_REGNUM,
	337	X86_RECORD_GS_REGNUM,
	338	};
	339
8201327c	340	#define I386_NUM_GREGS 16
8201327c MK	341	#define I386_NUM_XREGS 9
8201327c MK	342
90884b2b	343	#define I386_SSE_NUM_REGS (I386_MXCSR_REGNUM + 1)
c131fcee	344	#define I386_AVX_NUM_REGS (I386_YMM7H_REGNUM + 1)
1dbcd68c	345	#define I386_MPX_NUM_REGS (I386_BNDSTATUS_REGNUM + 1)
01f9f808	346	#define I386_AVX512_NUM_REGS (I386_ZMM7H_REGNUM + 1)
51547df6	347	#define I386_PKEYS_NUM_REGS (I386_PKRU_REGNUM + 1)
1163a4b7	348	#define I386_NUM_REGS (I386_GSBASE_REGNUM + 1)
8201327c	349
00f8375e	350	/* Size of the largest register. */
01f9f808	351	#define I386_MAX_REGISTER_SIZE 64
00f8375e	352
5ae96ec1	353	/* Types for i386-specific registers. */
27067745	354	extern struct type i387_ext_type (struct gdbarch gdbarch);
794ac428	355
1ba53b71 L	356	/* Checks of different pseudo-registers. */
	357	extern int i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum);
	358	extern int i386_word_regnum_p (struct gdbarch *gdbarch, int regnum);
	359	extern int i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum);
c131fcee	360	extern int i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum);
01f9f808	361	extern int i386_xmm_avx512_regnum_p (struct gdbarch * gdbarch, int regnum);
c131fcee	362	extern int i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum);
01f9f808	363	extern int i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum);
1dbcd68c	364	extern int i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum);
01f9f808 MS	365	extern int i386_k_regnum_p (struct gdbarch *gdbarch, int regnum);
	366	extern int i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum);
	367	extern int i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum);
51547df6	368	extern bool i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum);
1ba53b71 L	369
	370	extern const char i386_pseudo_register_name (struct gdbarch gdbarch,
	371	int regnum);
fff4548b MK	372	extern struct type i386_pseudo_register_type (struct gdbarch gdbarch,
fff4548b MK	373	int regnum);
1ba53b71	374
3543a589	375	extern void i386_pseudo_register_read_into_value (struct gdbarch *gdbarch,
849d0ba8	376	readable_regcache *regcache,
3543a589 TT	377	int regnum,
	378	struct value *result);
	379
1ba53b71 L	380	extern void i386_pseudo_register_write (struct gdbarch *gdbarch,
	381	struct regcache *regcache,
	382	int regnum, const gdb_byte *buf);
	383
62e5fd57 MK	384	extern int i386_ax_pseudo_register_collect (struct gdbarch *gdbarch,
	385	struct agent_expr *ax,
	386	int regnum);
	387
508fbfea MK	388	/* Segment selectors. */
508fbfea MK	389	#define I386_SEL_RPL 0x0003 /* Requester's Privilege Level mask. */
1777feb0 MS	390	#define I386_SEL_UPL 0x0003 /* User Privilige Level. */
1777feb0 MS	391	#define I386_SEL_KPL 0x0000 /* Kernel Privilige Level. */
508fbfea	392
237fc4c9 PA	393	/* The length of the longest i386 instruction (according to
	394	include/asm-i386/kprobes.h in Linux 2.6. */
	395	#define I386_MAX_INSN_LEN (16)
	396
1cce71eb	397	/* Functions exported from i386-tdep.c. */
e17a4113 UW	398	extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
e17a4113 UW	399	CORE_ADDR pc, char *name);
1777feb0 MS	400	extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch,
1777feb0 MS	401	CORE_ADDR pc);
1cce71eb	402
627c7fb8 HD	403	/* The "push_dummy_call" gdbarch method, optionally with the thiscall
	404	calling convention. */
	405	extern CORE_ADDR i386_thiscall_push_dummy_call (struct gdbarch *gdbarch,
	406	struct value *function,
	407	struct regcache *regcache,
	408	CORE_ADDR bp_addr,
	409	int nargs, struct value **args,
	410	CORE_ADDR sp,
	411	function_call_return_method
	412	return_method,
	413	CORE_ADDR struct_addr,
	414	bool thiscall);
	415
4bd207ef TG	416	/* Return whether the THIS_FRAME corresponds to a sigtramp routine. */
	417	extern int i386_sigtramp_p (struct frame_info *this_frame);
	418
38c968cf AC	419	/* Return non-zero if REGNUM is a member of the specified group. */
	420	extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
	421	struct reggroup *group);
	422
20187ed5 MK	423	/* Supply register REGNUM from the general-purpose register set REGSET
	424	to register cache REGCACHE. If REGNUM is -1, do this for all
	425	registers in REGSET. */
	426	extern void i386_supply_gregset (const struct regset *regset,
	427	struct regcache *regcache, int regnum,
	428	const void *gregs, size_t len);
3d171c85	429
ecc37a5a AA	430	/* General-purpose register set. */
ecc37a5a AA	431	extern const struct regset i386_gregset;
20187ed5	432
8f0435f7 AA	433	/* Floating-point register set. */
	434	extern const struct regset i386_fpregset;
	435
490496c3 AA	436	/* Default iterator over core file register note sections. */
	437	extern void
	438	i386_iterate_over_regset_sections (struct gdbarch *gdbarch,
	439	iterate_over_regset_sections_cb *cb,
	440	void *cb_data,
	441	const struct regcache *regcache);
237fc4c9	442
1152d984 SM	443	typedef buf_displaced_step_copy_insn_closure
1152d984 SM	444	i386_displaced_step_copy_insn_closure;
cfba9872	445
1152d984	446	extern displaced_step_copy_insn_closure_up i386_displaced_step_copy_insn
b55078be DE	447	(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
b55078be DE	448	struct regcache *regs);
1152d984 SM	449	extern void i386_displaced_step_fixup
	450	(struct gdbarch gdbarch, displaced_step_copy_insn_closure closure,
	451	CORE_ADDR from, CORE_ADDR to, regcache *regs);
237fc4c9	452
8201327c MK	453	/* Initialize a basic ELF architecture variant. */
	454	extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);
	455
	456	/* Initialize a SVR4 architecture variant. */
	457	extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);
a6b808b4	458
8f10c932 PA	459	/* Convert SVR4 register number REG to the appropriate register number
	460	used by GDB. */
	461	extern int i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg);
	462
a6b808b4	463	extern int i386_process_record (struct gdbarch *gdbarch,
dda83cd7	464	struct regcache *regcache, CORE_ADDR addr);
1163a4b7 JB	465	extern const struct target_desc *i386_target_description (uint64_t xcr0,
1163a4b7 JB	466	bool segments);
55aa24fb	467
012b3a21 WT	468	/* Return true iff the current target is MPX enabled. */
012b3a21 WT	469	extern int i386_mpx_enabled (void);
de0b6abb	470	\f
8201327c	471
03b62bbb	472	/* Functions and variables exported from i386-bsd-tdep.c. */
8201327c	473
3cac699e	474	extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
5d93ae8c MK	475	extern CORE_ADDR i386fbsd_sigtramp_start_addr;
	476	extern CORE_ADDR i386fbsd_sigtramp_end_addr;
	477	extern CORE_ADDR i386obsd_sigtramp_start_addr;
	478	extern CORE_ADDR i386obsd_sigtramp_end_addr;
de0b6abb MK	479	extern int i386fbsd4_sc_reg_offset[];
de0b6abb MK	480	extern int i386fbsd_sc_reg_offset[];
de0b6abb MK	481	extern int i386obsd_sc_reg_offset[];
de0b6abb MK	482	extern int i386bsd_sc_reg_offset[];
3ce1502b	483
55aa24fb SDJ	484	/* SystemTap related functions. */
	485
	486	extern int i386_stap_is_single_operand (struct gdbarch *gdbarch,
	487	const char *s);
	488
4c5e7a93 TT	489	extern expr::operation_up i386_stap_parse_special_token
4c5e7a93 TT	490	(struct gdbarch gdbarch, struct stap_parse_info p);
55aa24fb	491
96297dab	492	#endif /* i386-tdep.h */