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[thirdparty/binutils-gdb.git] / gdb / ia64-tdep.c
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16461d7d 1/* Target-dependent code for the IA-64 for GDB, the GNU debugger.
ca557f44 2
6aba47ca 3 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
13547ab6 4 Free Software Foundation, Inc.
16461d7d
KB		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ		 20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
16461d7d
KB		 22
23#include "defs.h"
24#include "inferior.h"
16461d7d 25#include "gdbcore.h"
8064c6ae 26#include "arch-utils.h"
16461d7d 27#include "floatformat.h"
4e052eda 28#include "regcache.h"
004d836a
JJ		 29#include "reggroups.h"
30#include "frame.h"
31#include "frame-base.h"
32#include "frame-unwind.h"
d16aafd8 33#include "doublest.h"
fd0407d6 34#include "value.h"
bd1ce8ba 35#include "gdb_assert.h"
16461d7d
KB		 36#include "objfiles.h"
37#include "elf/common.h" /* for DT_PLTGOT value */
244bc108 38#include "elf-bfd.h"
a89aa300 39#include "dis-asm.h"
7d9b040b 40#include "infcall.h"
b33e8514 41#include "osabi.h"
9fc9f5e2 42#include "ia64-tdep.h"
0d5de010 43#include "cp-abi.h"
16461d7d 44
968d1cb4 45#ifdef HAVE_LIBUNWIND_IA64_H
8973ff21 46#include "elf/ia64.h" /* for PT_IA_64_UNWIND value */
968d1cb4
JJ		 47#include "libunwind-frame.h"
48#include "libunwind-ia64.h"
c5a27d9c
JJ		 49
50/* Note: KERNEL_START is supposed to be an address which is not going
51 to ever contain any valid unwind info. For ia64 linux, the choice
52 of 0xc000000000000000 is fairly safe since that's uncached space.
53
54 We use KERNEL_START as follows: after obtaining the kernel's
55 unwind table via getunwind(), we project its unwind data into
56 address-range KERNEL_START-(KERNEL_START+ktab_size) and then
57 when ia64_access_mem() sees a memory access to this
58 address-range, we redirect it to ktab instead.
59
60 None of this hackery is needed with a modern kernel/libcs
61 which uses the kernel virtual DSO to provide access to the
62 kernel's unwind info. In that case, ktab_size remains 0 and
63 hence the value of KERNEL_START doesn't matter. */
64
65#define KERNEL_START 0xc000000000000000ULL
66
67static size_t ktab_size = 0;
68struct ia64_table_entry
69 {
70 uint64_t start_offset;
71 uint64_t end_offset;
72 uint64_t info_offset;
73 };
74
75static struct ia64_table_entry *ktab = NULL;
76
968d1cb4
JJ		 77#endif
78
698cb3f0
KB		 79/* An enumeration of the different IA-64 instruction types. */
80
16461d7d
KB		 81typedef enum instruction_type
82{
83 A, /* Integer ALU ; I-unit or M-unit */
84 I, /* Non-ALU integer; I-unit */
85 M, /* Memory ; M-unit */
86 F, /* Floating-point ; F-unit */
87 B, /* Branch ; B-unit */
88 L, /* Extended (L+X) ; I-unit */
89 X, /* Extended (L+X) ; I-unit */
90 undefined /* undefined or reserved */
91} instruction_type;
92
93/* We represent IA-64 PC addresses as the value of the instruction
94 pointer or'd with some bit combination in the low nibble which
95 represents the slot number in the bundle addressed by the
96 instruction pointer. The problem is that the Linux kernel
97 multiplies its slot numbers (for exceptions) by one while the
98 disassembler multiplies its slot numbers by 6. In addition, I've
99 heard it said that the simulator uses 1 as the multiplier.
100
101 I've fixed the disassembler so that the bytes_per_line field will
102 be the slot multiplier. If bytes_per_line comes in as zero, it
103 is set to six (which is how it was set up initially). -- objdump
104 displays pretty disassembly dumps with this value. For our purposes,
105 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
106 never want to also display the raw bytes the way objdump does. */
107
108#define SLOT_MULTIPLIER 1
109
110/* Length in bytes of an instruction bundle */
111
112#define BUNDLE_LEN 16
113
16461d7d
KB		 114static gdbarch_init_ftype ia64_gdbarch_init;
115
116static gdbarch_register_name_ftype ia64_register_name;
004d836a 117static gdbarch_register_type_ftype ia64_register_type;
16461d7d 118static gdbarch_breakpoint_from_pc_ftype ia64_breakpoint_from_pc;
16461d7d 119static gdbarch_skip_prologue_ftype ia64_skip_prologue;
64a5b29c 120static struct type *is_float_or_hfa_type (struct type *t);
b33e8514 121static CORE_ADDR ia64_find_global_pointer (CORE_ADDR faddr);
16461d7d 122
004d836a
JJ		 123static struct type *builtin_type_ia64_ext;
124
125#define NUM_IA64_RAW_REGS 462
16461d7d 126
16461d7d
KB		 127static int sp_regnum = IA64_GR12_REGNUM;
128static int fp_regnum = IA64_VFP_REGNUM;
129static int lr_regnum = IA64_VRAP_REGNUM;
130
004d836a 131/* NOTE: we treat the register stack registers r32-r127 as pseudo-registers because
4afcc598 132 they may not be accessible via the ptrace register get/set interfaces. */
004d836a
JJ		 133enum pseudo_regs { FIRST_PSEUDO_REGNUM = NUM_IA64_RAW_REGS, VBOF_REGNUM = IA64_NAT127_REGNUM + 1, V32_REGNUM,
134 V127_REGNUM = V32_REGNUM + 95,
135 VP0_REGNUM, VP16_REGNUM = VP0_REGNUM + 16, VP63_REGNUM = VP0_REGNUM + 63, LAST_PSEUDO_REGNUM };
16461d7d
KB		 136
137/* Array of register names; There should be ia64_num_regs strings in
138 the initializer. */
139
140static char *ia64_register_names[] =
141{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
143 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
144 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
004d836a
JJ		 145 "", "", "", "", "", "", "", "",
146 "", "", "", "", "", "", "", "",
147 "", "", "", "", "", "", "", "",
148 "", "", "", "", "", "", "", "",
149 "", "", "", "", "", "", "", "",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
152 "", "", "", "", "", "", "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 "", "", "", "", "", "", "", "",
16461d7d
KB		 157
158 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
159 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
160 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
161 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
162 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
163 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
164 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
165 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
166 "f64", "f65", "f66", "f67", "f68", "f69", "f70", "f71",
167 "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79",
168 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87",
169 "f88", "f89", "f90", "f91", "f92", "f93", "f94", "f95",
170 "f96", "f97", "f98", "f99", "f100", "f101", "f102", "f103",
171 "f104", "f105", "f106", "f107", "f108", "f109", "f110", "f111",
172 "f112", "f113", "f114", "f115", "f116", "f117", "f118", "f119",
173 "f120", "f121", "f122", "f123", "f124", "f125", "f126", "f127",
174
004d836a
JJ		 175 "", "", "", "", "", "", "", "",
176 "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
179 "", "", "", "", "", "", "", "",
180 "", "", "", "", "", "", "", "",
181 "", "", "", "", "", "", "", "",
182 "", "", "", "", "", "", "", "",
16461d7d
KB		 183
184 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",
185
186 "vfp", "vrap",
187
188 "pr", "ip", "psr", "cfm",
189
190 "kr0", "kr1", "kr2", "kr3", "kr4", "kr5", "kr6", "kr7",
191 "", "", "", "", "", "", "", "",
192 "rsc", "bsp", "bspstore", "rnat",
193 "", "fcr", "", "",
194 "eflag", "csd", "ssd", "cflg", "fsr", "fir", "fdr", "",
195 "ccv", "", "", "", "unat", "", "", "",
196 "fpsr", "", "", "", "itc",
197 "", "", "", "", "", "", "", "", "", "",
198 "", "", "", "", "", "", "", "", "",
199 "pfs", "lc", "ec",
200 "", "", "", "", "", "", "", "", "", "",
201 "", "", "", "", "", "", "", "", "", "",
202 "", "", "", "", "", "", "", "", "", "",
203 "", "", "", "", "", "", "", "", "", "",
204 "", "", "", "", "", "", "", "", "", "",
205 "", "", "", "", "", "", "", "", "", "",
206 "",
207 "nat0", "nat1", "nat2", "nat3", "nat4", "nat5", "nat6", "nat7",
208 "nat8", "nat9", "nat10", "nat11", "nat12", "nat13", "nat14", "nat15",
209 "nat16", "nat17", "nat18", "nat19", "nat20", "nat21", "nat22", "nat23",
210 "nat24", "nat25", "nat26", "nat27", "nat28", "nat29", "nat30", "nat31",
211 "nat32", "nat33", "nat34", "nat35", "nat36", "nat37", "nat38", "nat39",
212 "nat40", "nat41", "nat42", "nat43", "nat44", "nat45", "nat46", "nat47",
213 "nat48", "nat49", "nat50", "nat51", "nat52", "nat53", "nat54", "nat55",
214 "nat56", "nat57", "nat58", "nat59", "nat60", "nat61", "nat62", "nat63",
215 "nat64", "nat65", "nat66", "nat67", "nat68", "nat69", "nat70", "nat71",
216 "nat72", "nat73", "nat74", "nat75", "nat76", "nat77", "nat78", "nat79",
217 "nat80", "nat81", "nat82", "nat83", "nat84", "nat85", "nat86", "nat87",
218 "nat88", "nat89", "nat90", "nat91", "nat92", "nat93", "nat94", "nat95",
219 "nat96", "nat97", "nat98", "nat99", "nat100","nat101","nat102","nat103",
220 "nat104","nat105","nat106","nat107","nat108","nat109","nat110","nat111",
221 "nat112","nat113","nat114","nat115","nat116","nat117","nat118","nat119",
222 "nat120","nat121","nat122","nat123","nat124","nat125","nat126","nat127",
004d836a
JJ		 223
224 "bof",
225
226 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
227 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
228 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
229 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
230 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
231 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
232 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
233 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
234 "r96", "r97", "r98", "r99", "r100", "r101", "r102", "r103",
235 "r104", "r105", "r106", "r107", "r108", "r109", "r110", "r111",
236 "r112", "r113", "r114", "r115", "r116", "r117", "r118", "r119",
237 "r120", "r121", "r122", "r123", "r124", "r125", "r126", "r127",
238
239 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7",
240 "p8", "p9", "p10", "p11", "p12", "p13", "p14", "p15",
241 "p16", "p17", "p18", "p19", "p20", "p21", "p22", "p23",
242 "p24", "p25", "p26", "p27", "p28", "p29", "p30", "p31",
243 "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39",
244 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47",
245 "p48", "p49", "p50", "p51", "p52", "p53", "p54", "p55",
246 "p56", "p57", "p58", "p59", "p60", "p61", "p62", "p63",
16461d7d
KB		 247};
248
004d836a
JJ		 249struct ia64_frame_cache
250{
251 CORE_ADDR base; /* frame pointer base for frame */
252 CORE_ADDR pc; /* function start pc for frame */
253 CORE_ADDR saved_sp; /* stack pointer for frame */
254 CORE_ADDR bsp; /* points at r32 for the current frame */
255 CORE_ADDR cfm; /* cfm value for current frame */
4afcc598 256 CORE_ADDR prev_cfm; /* cfm value for previous frame */
004d836a
JJ		 257 int frameless;
258 int sof; /* Size of frame (decoded from cfm value) */
259 int sol; /* Size of locals (decoded from cfm value) */
260 int sor; /* Number of rotating registers. (decoded from cfm value) */
261 CORE_ADDR after_prologue;
262 /* Address of first instruction after the last
263 prologue instruction; Note that there may
264 be instructions from the function's body
265 intermingled with the prologue. */
266 int mem_stack_frame_size;
267 /* Size of the memory stack frame (may be zero),
268 or -1 if it has not been determined yet. */
269 int fp_reg; /* Register number (if any) used a frame pointer
244bc108 270 for this frame. 0 if no register is being used
16461d7d 271 as the frame pointer. */
004d836a
JJ		 272
273 /* Saved registers. */
274 CORE_ADDR saved_regs[NUM_IA64_RAW_REGS];
275
276};
244bc108 277
698cb3f0
KB		 278#define SIGCONTEXT_REGISTER_ADDRESS \
279 (gdbarch_tdep (current_gdbarch)->sigcontext_register_address)
16461d7d 280
004d836a
JJ		 281int
282ia64_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
283 struct reggroup *group)
16461d7d 284{
004d836a
JJ		 285 int vector_p;
286 int float_p;
287 int raw_p;
288 if (group == all_reggroup)
289 return 1;
290 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum));
291 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT;
292 raw_p = regnum < NUM_IA64_RAW_REGS;
293 if (group == float_reggroup)
294 return float_p;
295 if (group == vector_reggroup)
296 return vector_p;
297 if (group == general_reggroup)
298 return (!vector_p && !float_p);
299 if (group == save_reggroup || group == restore_reggroup)
300 return raw_p;
301 return 0;
16461d7d
KB		 302}
303
004d836a
JJ		 304static const char *
305ia64_register_name (int reg)
16461d7d 306{
004d836a 307 return ia64_register_names[reg];
16461d7d
KB		 308}
309
004d836a
JJ		 310struct type *
311ia64_register_type (struct gdbarch *arch, int reg)
16461d7d 312{
004d836a
JJ		 313 if (reg >= IA64_FR0_REGNUM && reg <= IA64_FR127_REGNUM)
314 return builtin_type_ia64_ext;
315 else
316 return builtin_type_long;
16461d7d
KB		 317}
318
a78f21af 319static int
004d836a 320ia64_dwarf_reg_to_regnum (int reg)
16461d7d 321{
004d836a
JJ		 322 if (reg >= IA64_GR32_REGNUM && reg <= IA64_GR127_REGNUM)
323 return V32_REGNUM + (reg - IA64_GR32_REGNUM);
324 return reg;
16461d7d
KB		 325}
326
4afcc598 327static int
2fda21a6 328floatformat_valid (const struct floatformat *fmt, const void *from)
4afcc598
JJ		 329{
330 return 1;
331}
332
16461d7d
KB		 333const struct floatformat floatformat_ia64_ext =
334{
335 floatformat_little, 82, 0, 1, 17, 65535, 0x1ffff, 18, 64,
4afcc598 336 floatformat_intbit_yes, "floatformat_ia64_ext", floatformat_valid
16461d7d
KB		 337};
338
16461d7d
KB		 339
340/* Extract ``len'' bits from an instruction bundle starting at
341 bit ``from''. */
342
244bc108 343static long long
16461d7d
KB		 344extract_bit_field (char *bundle, int from, int len)
345{
346 long long result = 0LL;
347 int to = from + len;
348 int from_byte = from / 8;
349 int to_byte = to / 8;
350 unsigned char *b = (unsigned char *) bundle;
351 unsigned char c;
352 int lshift;
353 int i;
354
355 c = b[from_byte];
356 if (from_byte == to_byte)
357 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
358 result = c >> (from % 8);
359 lshift = 8 - (from % 8);
360
361 for (i = from_byte+1; i < to_byte; i++)
362 {
363 result |= ((long long) b[i]) << lshift;
364 lshift += 8;
365 }
366
367 if (from_byte < to_byte && (to % 8 != 0))
368 {
369 c = b[to_byte];
370 c = ((unsigned char) (c << (8 - to % 8))) >> (8 - to % 8);
371 result |= ((long long) c) << lshift;
372 }
373
374 return result;
375}
376
377/* Replace the specified bits in an instruction bundle */
378
244bc108 379static void
16461d7d
KB		 380replace_bit_field (char *bundle, long long val, int from, int len)
381{
382 int to = from + len;
383 int from_byte = from / 8;
384 int to_byte = to / 8;
385 unsigned char *b = (unsigned char *) bundle;
386 unsigned char c;
387
388 if (from_byte == to_byte)
389 {
390 unsigned char left, right;
391 c = b[from_byte];
392 left = (c >> (to % 8)) << (to % 8);
393 right = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
394 c = (unsigned char) (val & 0xff);
395 c = (unsigned char) (c << (from % 8 + 8 - to % 8)) >> (8 - to % 8);
396 c |= right | left;
397 b[from_byte] = c;
398 }
399 else
400 {
401 int i;
402 c = b[from_byte];
403 c = ((unsigned char) (c << (8 - from % 8))) >> (8 - from % 8);
404 c = c | (val << (from % 8));
405 b[from_byte] = c;
406 val >>= 8 - from % 8;
407
408 for (i = from_byte+1; i < to_byte; i++)
409 {
410 c = val & 0xff;
411 val >>= 8;
412 b[i] = c;
413 }
414
415 if (to % 8 != 0)
416 {
417 unsigned char cv = (unsigned char) val;
418 c = b[to_byte];
419 c = c >> (to % 8) << (to % 8);
420 c |= ((unsigned char) (cv << (8 - to % 8))) >> (8 - to % 8);
421 b[to_byte] = c;
422 }
423 }
424}
425
426/* Return the contents of slot N (for N = 0, 1, or 2) in
427 and instruction bundle */
428
244bc108 429static long long
2fc3ac7e 430slotN_contents (char *bundle, int slotnum)
16461d7d
KB		 431{
432 return extract_bit_field (bundle, 5+41*slotnum, 41);
433}
434
435/* Store an instruction in an instruction bundle */
436
244bc108 437static void
2fc3ac7e 438replace_slotN_contents (char *bundle, long long instr, int slotnum)
16461d7d
KB		 439{
440 replace_bit_field (bundle, instr, 5+41*slotnum, 41);
441}
442
64a5b29c 443static enum instruction_type template_encoding_table[32][3] =
16461d7d
KB		 444{
445 { M, I, I }, /* 00 */
446 { M, I, I }, /* 01 */
447 { M, I, I }, /* 02 */
448 { M, I, I }, /* 03 */
449 { M, L, X }, /* 04 */
450 { M, L, X }, /* 05 */
451 { undefined, undefined, undefined }, /* 06 */
452 { undefined, undefined, undefined }, /* 07 */
453 { M, M, I }, /* 08 */
454 { M, M, I }, /* 09 */
455 { M, M, I }, /* 0A */
456 { M, M, I }, /* 0B */
457 { M, F, I }, /* 0C */
458 { M, F, I }, /* 0D */
459 { M, M, F }, /* 0E */
460 { M, M, F }, /* 0F */
461 { M, I, B }, /* 10 */
462 { M, I, B }, /* 11 */
463 { M, B, B }, /* 12 */
464 { M, B, B }, /* 13 */
465 { undefined, undefined, undefined }, /* 14 */
466 { undefined, undefined, undefined }, /* 15 */
467 { B, B, B }, /* 16 */
468 { B, B, B }, /* 17 */
469 { M, M, B }, /* 18 */
470 { M, M, B }, /* 19 */
471 { undefined, undefined, undefined }, /* 1A */
472 { undefined, undefined, undefined }, /* 1B */
473 { M, F, B }, /* 1C */
474 { M, F, B }, /* 1D */
475 { undefined, undefined, undefined }, /* 1E */
476 { undefined, undefined, undefined }, /* 1F */
477};
478
479/* Fetch and (partially) decode an instruction at ADDR and return the
480 address of the next instruction to fetch. */
481
482static CORE_ADDR
483fetch_instruction (CORE_ADDR addr, instruction_type *it, long long *instr)
484{
485 char bundle[BUNDLE_LEN];
486 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
487 long long template;
488 int val;
489
c26e1c2b
KB		 490 /* Warn about slot numbers greater than 2. We used to generate
491 an error here on the assumption that the user entered an invalid
492 address. But, sometimes GDB itself requests an invalid address.
493 This can (easily) happen when execution stops in a function for
494 which there are no symbols. The prologue scanner will attempt to
495 find the beginning of the function - if the nearest symbol
496 happens to not be aligned on a bundle boundary (16 bytes), the
497 resulting starting address will cause GDB to think that the slot
498 number is too large.
499
500 So we warn about it and set the slot number to zero. It is
501 not necessarily a fatal condition, particularly if debugging
502 at the assembly language level. */
16461d7d 503 if (slotnum > 2)
c26e1c2b 504 {
8a3fe4f8
AC		 505 warning (_("Can't fetch instructions for slot numbers greater than 2.\n"
506 "Using slot 0 instead"));
c26e1c2b
KB		 507 slotnum = 0;
508 }
16461d7d
KB		 509
510 addr &= ~0x0f;
511
512 val = target_read_memory (addr, bundle, BUNDLE_LEN);
513
514 if (val != 0)
515 return 0;
516
517 *instr = slotN_contents (bundle, slotnum);
518 template = extract_bit_field (bundle, 0, 5);
519 *it = template_encoding_table[(int)template][slotnum];
520
64a5b29c 521 if (slotnum == 2 || (slotnum == 1 && *it == L))
16461d7d
KB		 522 addr += 16;
523 else
524 addr += (slotnum + 1) * SLOT_MULTIPLIER;
525
526 return addr;
527}
528
529/* There are 5 different break instructions (break.i, break.b,
530 break.m, break.f, and break.x), but they all have the same
531 encoding. (The five bit template in the low five bits of the
532 instruction bundle distinguishes one from another.)
533
534 The runtime architecture manual specifies that break instructions
535 used for debugging purposes must have the upper two bits of the 21
536 bit immediate set to a 0 and a 1 respectively. A breakpoint
537 instruction encodes the most significant bit of its 21 bit
538 immediate at bit 36 of the 41 bit instruction. The penultimate msb
539 is at bit 25 which leads to the pattern below.
540
541 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
542 it turns out that 0x80000 was used as the syscall break in the early
543 simulators. So I changed the pattern slightly to do "break.i 0x080001"
544 instead. But that didn't work either (I later found out that this
545 pattern was used by the simulator that I was using.) So I ended up
546 using the pattern seen below. */
547
548#if 0
aaab4dba 549#define IA64_BREAKPOINT 0x00002000040LL
16461d7d 550#endif
aaab4dba 551#define IA64_BREAKPOINT 0x00003333300LL
16461d7d
KB		 552
553static int
8181d85f 554ia64_memory_insert_breakpoint (struct bp_target_info *bp_tgt)
16461d7d 555{
8181d85f 556 CORE_ADDR addr = bp_tgt->placed_address;
16461d7d
KB		 557 char bundle[BUNDLE_LEN];
558 int slotnum = (int) (addr & 0x0f) / SLOT_MULTIPLIER;
559 long long instr;
560 int val;
126fa72d 561 int template;
16461d7d
KB		 562
563 if (slotnum > 2)
8a3fe4f8 564 error (_("Can't insert breakpoint for slot numbers greater than 2."));
16461d7d
KB		 565
566 addr &= ~0x0f;
567
568 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 569
570 /* Check for L type instruction in 2nd slot, if present then
571 bump up the slot number to the 3rd slot */
572 template = extract_bit_field (bundle, 0, 5);
573 if (slotnum == 1 && template_encoding_table[template][1] == L)
574 {
575 slotnum = 2;
576 }
577
16461d7d 578 instr = slotN_contents (bundle, slotnum);
8181d85f
DJ		 579 memcpy (bp_tgt->shadow_contents, &instr, sizeof (instr));
580 bp_tgt->placed_size = bp_tgt->shadow_len = sizeof (instr);
aaab4dba 581 replace_slotN_contents (bundle, IA64_BREAKPOINT, slotnum);
16461d7d
KB		 582 if (val == 0)
583 target_write_memory (addr, bundle, BUNDLE_LEN);
584
585 return val;
586}
587
588static int
8181d85f 589ia64_memory_remove_breakpoint (struct bp_target_info *bp_tgt)
16461d7d 590{
8181d85f 591 CORE_ADDR addr = bp_tgt->placed_address;
16461d7d
KB		 592 char bundle[BUNDLE_LEN];
593 int slotnum = (addr & 0x0f) / SLOT_MULTIPLIER;
594 long long instr;
595 int val;
126fa72d 596 int template;
16461d7d
KB		 597
598 addr &= ~0x0f;
599
600 val = target_read_memory (addr, bundle, BUNDLE_LEN);
126fa72d
PS		 601
602 /* Check for L type instruction in 2nd slot, if present then
603 bump up the slot number to the 3rd slot */
604 template = extract_bit_field (bundle, 0, 5);
605 if (slotnum == 1 && template_encoding_table[template][1] == L)
606 {
607 slotnum = 2;
608 }
609
8181d85f 610 memcpy (&instr, bp_tgt->shadow_contents, sizeof instr);
16461d7d
KB		 611 replace_slotN_contents (bundle, instr, slotnum);
612 if (val == 0)
613 target_write_memory (addr, bundle, BUNDLE_LEN);
614
615 return val;
616}
617
618/* We don't really want to use this, but remote.c needs to call it in order
619 to figure out if Z-packets are supported or not. Oh, well. */
f4f9705a 620const unsigned char *
fba45db2 621ia64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
16461d7d
KB		 622{
623 static unsigned char breakpoint[] =
624 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
625 *lenptr = sizeof (breakpoint);
626#if 0
627 *pcptr &= ~0x0f;
628#endif
629 return breakpoint;
630}
631
a78f21af 632static CORE_ADDR
39f77062 633ia64_read_pc (ptid_t ptid)
16461d7d 634{
39f77062
KB		 635 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
636 CORE_ADDR pc_value = read_register_pid (IA64_IP_REGNUM, ptid);
16461d7d
KB		 637 int slot_num = (psr_value >> 41) & 3;
638
639 return pc_value | (slot_num * SLOT_MULTIPLIER);
640}
641
54a5c8d8 642void
39f77062 643ia64_write_pc (CORE_ADDR new_pc, ptid_t ptid)
16461d7d
KB		 644{
645 int slot_num = (int) (new_pc & 0xf) / SLOT_MULTIPLIER;
39f77062 646 CORE_ADDR psr_value = read_register_pid (IA64_PSR_REGNUM, ptid);
16461d7d
KB		 647 psr_value &= ~(3LL << 41);
648 psr_value |= (CORE_ADDR)(slot_num & 0x3) << 41;
649
650 new_pc &= ~0xfLL;
651
39f77062
KB		 652 write_register_pid (IA64_PSR_REGNUM, psr_value, ptid);
653 write_register_pid (IA64_IP_REGNUM, new_pc, ptid);
16461d7d
KB		 654}
655
656#define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
657
658/* Returns the address of the slot that's NSLOTS slots away from
659 the address ADDR. NSLOTS may be positive or negative. */
660static CORE_ADDR
661rse_address_add(CORE_ADDR addr, int nslots)
662{
663 CORE_ADDR new_addr;
664 int mandatory_nat_slots = nslots / 63;
665 int direction = nslots < 0 ? -1 : 1;
666
667 new_addr = addr + 8 * (nslots + mandatory_nat_slots);
668
669 if ((new_addr >> 9) != ((addr + 8 * 64 * mandatory_nat_slots) >> 9))
670 new_addr += 8 * direction;
671
672 if (IS_NaT_COLLECTION_ADDR(new_addr))
673 new_addr += 8 * direction;
674
675 return new_addr;
676}
677
004d836a
JJ		 678static void
679ia64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 680 int regnum, gdb_byte *buf)
16461d7d 681{
004d836a 682 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 683 {
88d82102 684#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c
JJ		 685 /* First try and use the libunwind special reg accessor, otherwise fallback to
686 standard logic. */
687 if (!libunwind_is_initialized ()
688 || libunwind_get_reg_special (gdbarch, regnum, buf) != 0)
88d82102 689#endif
004d836a 690 {
c5a27d9c
JJ		 691 /* The fallback position is to assume that r32-r127 are found sequentially
692 in memory starting at $bof. This isn't always true, but without libunwind,
693 this is the best we can do. */
694 ULONGEST cfm;
695 ULONGEST bsp;
696 CORE_ADDR reg;
697 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
698 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
699
700 /* The bsp points at the end of the register frame so we
701 subtract the size of frame from it to get start of register frame. */
702 bsp = rse_address_add (bsp, -(cfm & 0x7f));
703
704 if ((cfm & 0x7f) > regnum - V32_REGNUM)
705 {
706 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
707 reg = read_memory_integer ((CORE_ADDR)reg_addr, 8);
708 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), reg);
709 }
710 else
711 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), 0);
004d836a 712 }
004d836a
JJ		 713 }
714 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
715 {
716 ULONGEST unatN_val;
717 ULONGEST unat;
718 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
719 unatN_val = (unat & (1LL << (regnum - IA64_NAT0_REGNUM))) != 0;
aa2a9a3c 720 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), unatN_val);
004d836a
JJ		 721 }
722 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
723 {
724 ULONGEST natN_val = 0;
725 ULONGEST bsp;
726 ULONGEST cfm;
727 CORE_ADDR gr_addr = 0;
728 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
729 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
730
731 /* The bsp points at the end of the register frame so we
732 subtract the size of frame from it to get start of register frame. */
733 bsp = rse_address_add (bsp, -(cfm & 0x7f));
734
735 if ((cfm & 0x7f) > regnum - V32_REGNUM)
736 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
737
738 if (gr_addr != 0)
739 {
740 /* Compute address of nat collection bits. */
741 CORE_ADDR nat_addr = gr_addr | 0x1f8;
742 CORE_ADDR nat_collection;
743 int nat_bit;
744 /* If our nat collection address is bigger than bsp, we have to get
745 the nat collection from rnat. Otherwise, we fetch the nat
746 collection from the computed address. */
747 if (nat_addr >= bsp)
748 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
749 else
750 nat_collection = read_memory_integer (nat_addr, 8);
751 nat_bit = (gr_addr >> 3) & 0x3f;
752 natN_val = (nat_collection >> nat_bit) & 1;
753 }
754
aa2a9a3c 755 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), natN_val);
244bc108 756 }
004d836a
JJ		 757 else if (regnum == VBOF_REGNUM)
758 {
759 /* A virtual register frame start is provided for user convenience.
760 It can be calculated as the bsp - sof (sizeof frame). */
761 ULONGEST bsp, vbsp;
762 ULONGEST cfm;
763 CORE_ADDR reg;
764 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
765 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
766
767 /* The bsp points at the end of the register frame so we
768 subtract the size of frame from it to get beginning of frame. */
769 vbsp = rse_address_add (bsp, -(cfm & 0x7f));
aa2a9a3c 770 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), vbsp);
004d836a
JJ		 771 }
772 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
773 {
774 ULONGEST pr;
775 ULONGEST cfm;
776 ULONGEST prN_val;
777 CORE_ADDR reg;
778 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
779 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
780
781 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
782 {
783 /* Fetch predicate register rename base from current frame
784 marker for this frame. */
785 int rrb_pr = (cfm >> 32) & 0x3f;
786
787 /* Adjust the register number to account for register rotation. */
788 regnum = VP16_REGNUM
789 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
790 }
791 prN_val = (pr & (1LL << (regnum - VP0_REGNUM))) != 0;
aa2a9a3c 792 store_unsigned_integer (buf, register_size (current_gdbarch, regnum), prN_val);
004d836a
JJ		 793 }
794 else
aa2a9a3c 795 memset (buf, 0, register_size (current_gdbarch, regnum));
16461d7d
KB		 796}
797
004d836a
JJ		 798static void
799ia64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
88d82102 800 int regnum, const gdb_byte *buf)
16461d7d 801{
004d836a 802 if (regnum >= V32_REGNUM && regnum <= V127_REGNUM)
244bc108 803 {
004d836a
JJ		 804 ULONGEST bsp;
805 ULONGEST cfm;
806 CORE_ADDR reg;
807 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
808 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
809
810 bsp = rse_address_add (bsp, -(cfm & 0x7f));
811
812 if ((cfm & 0x7f) > regnum - V32_REGNUM)
813 {
814 ULONGEST reg_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
815 write_memory (reg_addr, (void *)buf, 8);
816 }
817 }
818 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
819 {
820 ULONGEST unatN_val, unat, unatN_mask;
821 regcache_cooked_read_unsigned (regcache, IA64_UNAT_REGNUM, &unat);
aa2a9a3c 822 unatN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 823 unatN_mask = (1LL << (regnum - IA64_NAT0_REGNUM));
824 if (unatN_val == 0)
825 unat &= ~unatN_mask;
826 else if (unatN_val == 1)
827 unat |= unatN_mask;
828 regcache_cooked_write_unsigned (regcache, IA64_UNAT_REGNUM, unat);
829 }
830 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
831 {
832 ULONGEST natN_val;
833 ULONGEST bsp;
834 ULONGEST cfm;
835 CORE_ADDR gr_addr = 0;
836 regcache_cooked_read_unsigned (regcache, IA64_BSP_REGNUM, &bsp);
837 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
838
839 /* The bsp points at the end of the register frame so we
840 subtract the size of frame from it to get start of register frame. */
841 bsp = rse_address_add (bsp, -(cfm & 0x7f));
842
843 if ((cfm & 0x7f) > regnum - V32_REGNUM)
844 gr_addr = rse_address_add (bsp, (regnum - V32_REGNUM));
845
aa2a9a3c 846 natN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 847
848 if (gr_addr != 0 && (natN_val == 0 || natN_val == 1))
849 {
850 /* Compute address of nat collection bits. */
851 CORE_ADDR nat_addr = gr_addr | 0x1f8;
852 CORE_ADDR nat_collection;
853 int natN_bit = (gr_addr >> 3) & 0x3f;
854 ULONGEST natN_mask = (1LL << natN_bit);
855 /* If our nat collection address is bigger than bsp, we have to get
856 the nat collection from rnat. Otherwise, we fetch the nat
857 collection from the computed address. */
858 if (nat_addr >= bsp)
859 {
860 regcache_cooked_read_unsigned (regcache, IA64_RNAT_REGNUM, &nat_collection);
861 if (natN_val)
862 nat_collection |= natN_mask;
863 else
864 nat_collection &= ~natN_mask;
865 regcache_cooked_write_unsigned (regcache, IA64_RNAT_REGNUM, nat_collection);
866 }
867 else
868 {
869 char nat_buf[8];
870 nat_collection = read_memory_integer (nat_addr, 8);
871 if (natN_val)
872 nat_collection |= natN_mask;
873 else
874 nat_collection &= ~natN_mask;
aa2a9a3c 875 store_unsigned_integer (nat_buf, register_size (current_gdbarch, regnum), nat_collection);
004d836a
JJ		 876 write_memory (nat_addr, nat_buf, 8);
877 }
878 }
879 }
880 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
881 {
882 ULONGEST pr;
883 ULONGEST cfm;
884 ULONGEST prN_val;
885 ULONGEST prN_mask;
886
887 regcache_cooked_read_unsigned (regcache, IA64_PR_REGNUM, &pr);
888 regcache_cooked_read_unsigned (regcache, IA64_CFM_REGNUM, &cfm);
889
890 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
891 {
892 /* Fetch predicate register rename base from current frame
893 marker for this frame. */
894 int rrb_pr = (cfm >> 32) & 0x3f;
895
896 /* Adjust the register number to account for register rotation. */
897 regnum = VP16_REGNUM
898 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
899 }
aa2a9a3c 900 prN_val = extract_unsigned_integer (buf, register_size (current_gdbarch, regnum));
004d836a
JJ		 901 prN_mask = (1LL << (regnum - VP0_REGNUM));
902 if (prN_val == 0)
903 pr &= ~prN_mask;
904 else if (prN_val == 1)
905 pr |= prN_mask;
906 regcache_cooked_write_unsigned (regcache, IA64_PR_REGNUM, pr);
244bc108 907 }
16461d7d
KB		 908}
909
004d836a
JJ		 910/* The ia64 needs to convert between various ieee floating-point formats
911 and the special ia64 floating point register format. */
912
913static int
914ia64_convert_register_p (int regno, struct type *type)
915{
916 return (regno >= IA64_FR0_REGNUM && regno <= IA64_FR127_REGNUM);
917}
918
919static void
920ia64_register_to_value (struct frame_info *frame, int regnum,
88d82102 921 struct type *valtype, gdb_byte *out)
004d836a
JJ		 922{
923 char in[MAX_REGISTER_SIZE];
924 frame_register_read (frame, regnum, in);
925 convert_typed_floating (in, builtin_type_ia64_ext, out, valtype);
926}
927
928static void
929ia64_value_to_register (struct frame_info *frame, int regnum,
88d82102 930 struct type *valtype, const gdb_byte *in)
004d836a
JJ		 931{
932 char out[MAX_REGISTER_SIZE];
933 convert_typed_floating (in, valtype, out, builtin_type_ia64_ext);
934 put_frame_register (frame, regnum, out);
935}
936
937
58ab00f9
KB		 938/* Limit the number of skipped non-prologue instructions since examining
939 of the prologue is expensive. */
5ea2bd7f 940static int max_skip_non_prologue_insns = 40;
58ab00f9
KB		 941
942/* Given PC representing the starting address of a function, and
943 LIM_PC which is the (sloppy) limit to which to scan when looking
944 for a prologue, attempt to further refine this limit by using
945 the line data in the symbol table. If successful, a better guess
946 on where the prologue ends is returned, otherwise the previous
947 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
948 which will be set to indicate whether the returned limit may be
949 used with no further scanning in the event that the function is
950 frameless. */
951
634aa483
AC		 952/* FIXME: cagney/2004-02-14: This function and logic have largely been
953 superseded by skip_prologue_using_sal. */
954
58ab00f9
KB		 955static CORE_ADDR
956refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc, int *trust_limit)
957{
958 struct symtab_and_line prologue_sal;
959 CORE_ADDR start_pc = pc;
960
961 /* Start off not trusting the limit. */
962 *trust_limit = 0;
963
964 prologue_sal = find_pc_line (pc, 0);
965 if (prologue_sal.line != 0)
966 {
967 int i;
968 CORE_ADDR addr = prologue_sal.end;
969
970 /* Handle the case in which compiler's optimizer/scheduler
971 has moved instructions into the prologue. We scan ahead
972 in the function looking for address ranges whose corresponding
973 line number is less than or equal to the first one that we
974 found for the function. (It can be less than when the
975 scheduler puts a body instruction before the first prologue
976 instruction.) */
977 for (i = 2 * max_skip_non_prologue_insns;
978 i > 0 && (lim_pc == 0 || addr < lim_pc);
979 i--)
980 {
981 struct symtab_and_line sal;
982
983 sal = find_pc_line (addr, 0);
984 if (sal.line == 0)
985 break;
986 if (sal.line <= prologue_sal.line
987 && sal.symtab == prologue_sal.symtab)
988 {
989 prologue_sal = sal;
990 }
991 addr = sal.end;
992 }
993
994 if (lim_pc == 0 || prologue_sal.end < lim_pc)
995 {
996 lim_pc = prologue_sal.end;
997 if (start_pc == get_pc_function_start (lim_pc))
998 *trust_limit = 1;
999 }
1000 }
1001 return lim_pc;
1002}
1003
16461d7d
KB		 1004#define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1005 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1006 || (14 <= (_regnum_) && (_regnum_) <= 31))
1007#define imm9(_instr_) \
1008 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1009 | (((_instr_) & 0x00008000000LL) >> 20) \
1010 | (((_instr_) & 0x00000001fc0LL) >> 6))
1011
004d836a
JJ		 1012/* Allocate and initialize a frame cache. */
1013
1014static struct ia64_frame_cache *
1015ia64_alloc_frame_cache (void)
1016{
1017 struct ia64_frame_cache *cache;
1018 int i;
1019
1020 cache = FRAME_OBSTACK_ZALLOC (struct ia64_frame_cache);
1021
1022 /* Base address. */
1023 cache->base = 0;
1024 cache->pc = 0;
1025 cache->cfm = 0;
4afcc598 1026 cache->prev_cfm = 0;
004d836a
JJ		 1027 cache->sof = 0;
1028 cache->sol = 0;
1029 cache->sor = 0;
1030 cache->bsp = 0;
1031 cache->fp_reg = 0;
1032 cache->frameless = 1;
1033
1034 for (i = 0; i < NUM_IA64_RAW_REGS; i++)
1035 cache->saved_regs[i] = 0;
1036
1037 return cache;
1038}
1039
16461d7d 1040static CORE_ADDR
004d836a 1041examine_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct frame_info *next_frame, struct ia64_frame_cache *cache)
16461d7d
KB		 1042{
1043 CORE_ADDR next_pc;
1044 CORE_ADDR last_prologue_pc = pc;
16461d7d
KB		 1045 instruction_type it;
1046 long long instr;
16461d7d
KB		 1047 int cfm_reg = 0;
1048 int ret_reg = 0;
1049 int fp_reg = 0;
1050 int unat_save_reg = 0;
1051 int pr_save_reg = 0;
1052 int mem_stack_frame_size = 0;
1053 int spill_reg = 0;
1054 CORE_ADDR spill_addr = 0;
0927a22b
KB		 1055 char instores[8];
1056 char infpstores[8];
5ea2bd7f 1057 char reg_contents[256];
58ab00f9 1058 int trust_limit;
004d836a
JJ		 1059 int frameless = 1;
1060 int i;
1061 CORE_ADDR addr;
1062 char buf[8];
1063 CORE_ADDR bof, sor, sol, sof, cfm, rrb_gr;
0927a22b
KB		 1064
1065 memset (instores, 0, sizeof instores);
1066 memset (infpstores, 0, sizeof infpstores);
5ea2bd7f 1067 memset (reg_contents, 0, sizeof reg_contents);
16461d7d 1068
004d836a
JJ		 1069 if (cache->after_prologue != 0
1070 && cache->after_prologue <= lim_pc)
1071 return cache->after_prologue;
16461d7d 1072
58ab00f9 1073 lim_pc = refine_prologue_limit (pc, lim_pc, &trust_limit);
16461d7d 1074 next_pc = fetch_instruction (pc, &it, &instr);
5ea2bd7f
JJ		 1075
1076 /* We want to check if we have a recognizable function start before we
1077 look ahead for a prologue. */
16461d7d
KB		 1078 if (pc < lim_pc && next_pc
1079 && it == M && ((instr & 0x1ee0000003fLL) == 0x02c00000000LL))
1080 {
5ea2bd7f 1081 /* alloc - start of a regular function. */
16461d7d
KB		 1082 int sor = (int) ((instr & 0x00078000000LL) >> 27);
1083 int sol = (int) ((instr & 0x00007f00000LL) >> 20);
1084 int sof = (int) ((instr & 0x000000fe000LL) >> 13);
16461d7d 1085 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
004d836a
JJ		 1086
1087 /* Verify that the current cfm matches what we think is the
1088 function start. If we have somehow jumped within a function,
1089 we do not want to interpret the prologue and calculate the
1090 addresses of various registers such as the return address.
1091 We will instead treat the frame as frameless. */
1092 if (!next_frame ||
1093 (sof == (cache->cfm & 0x7f) &&
1094 sol == ((cache->cfm >> 7) & 0x7f)))
1095 frameless = 0;
1096
16461d7d
KB		 1097 cfm_reg = rN;
1098 last_prologue_pc = next_pc;
1099 pc = next_pc;
1100 }
1101 else
58ab00f9 1102 {
5ea2bd7f
JJ		 1103 /* Look for a leaf routine. */
1104 if (pc < lim_pc && next_pc
1105 && (it == I || it == M)
1106 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1107 {
1108 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1109 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1110 | ((instr & 0x001f8000000LL) >> 20)
1111 | ((instr & 0x000000fe000LL) >> 13));
1112 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1113 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1114 int qp = (int) (instr & 0x0000000003fLL);
1115 if (qp == 0 && rN == 2 && imm == 0 && rM == 12 && fp_reg == 0)
1116 {
1117 /* mov r2, r12 - beginning of leaf routine */
1118 fp_reg = rN;
5ea2bd7f
JJ		 1119 last_prologue_pc = next_pc;
1120 }
1121 }
1122
1123 /* If we don't recognize a regular function or leaf routine, we are
1124 done. */
1125 if (!fp_reg)
1126 {
1127 pc = lim_pc;
1128 if (trust_limit)
1129 last_prologue_pc = lim_pc;
1130 }
58ab00f9 1131 }
16461d7d
KB		 1132
1133 /* Loop, looking for prologue instructions, keeping track of
1134 where preserved registers were spilled. */
1135 while (pc < lim_pc)
1136 {
1137 next_pc = fetch_instruction (pc, &it, &instr);
1138 if (next_pc == 0)
1139 break;
1140
594706e6 1141 if (it == B && ((instr & 0x1e1f800003fLL) != 0x04000000000LL))
0927a22b 1142 {
102d615a
JJ		 1143 /* Exit loop upon hitting a non-nop branch instruction. */
1144 if (trust_limit)
1145 lim_pc = pc;
1146 break;
1147 }
1148 else if (((instr & 0x3fLL) != 0LL) &&
1149 (frameless || ret_reg != 0))
1150 {
1151 /* Exit loop upon hitting a predicated instruction if
1152 we already have the return register or if we are frameless. */
5ea2bd7f
JJ		 1153 if (trust_limit)
1154 lim_pc = pc;
0927a22b
KB		 1155 break;
1156 }
1157 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00188000000LL))
16461d7d
KB		 1158 {
1159 /* Move from BR */
1160 int b2 = (int) ((instr & 0x0000000e000LL) >> 13);
1161 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1162 int qp = (int) (instr & 0x0000000003f);
1163
1164 if (qp == 0 && b2 == 0 && rN >= 32 && ret_reg == 0)
1165 {
1166 ret_reg = rN;
1167 last_prologue_pc = next_pc;
1168 }
1169 }
1170 else if ((it == I || it == M)
1171 && ((instr & 0x1ee00000000LL) == 0x10800000000LL))
1172 {
1173 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1174 int imm = (int) ((((instr & 0x01000000000LL) ? -1 : 0) << 13)
1175 | ((instr & 0x001f8000000LL) >> 20)
1176 | ((instr & 0x000000fe000LL) >> 13));
1177 int rM = (int) ((instr & 0x00007f00000LL) >> 20);
1178 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1179 int qp = (int) (instr & 0x0000000003fLL);
1180
1181 if (qp == 0 && rN >= 32 && imm == 0 && rM == 12 && fp_reg == 0)
1182 {
1183 /* mov rN, r12 */
1184 fp_reg = rN;
1185 last_prologue_pc = next_pc;
1186 }
1187 else if (qp == 0 && rN == 12 && rM == 12)
1188 {
1189 /* adds r12, -mem_stack_frame_size, r12 */
1190 mem_stack_frame_size -= imm;
1191 last_prologue_pc = next_pc;
1192 }
1193 else if (qp == 0 && rN == 2
1194 && ((rM == fp_reg && fp_reg != 0) || rM == 12))
1195 {
004d836a
JJ		 1196 char buf[MAX_REGISTER_SIZE];
1197 CORE_ADDR saved_sp = 0;
16461d7d
KB		 1198 /* adds r2, spilloffset, rFramePointer
1199 or
1200 adds r2, spilloffset, r12
1201
1202 Get ready for stf.spill or st8.spill instructions.
1203 The address to start spilling at is loaded into r2.
1204 FIXME: Why r2? That's what gcc currently uses; it
1205 could well be different for other compilers. */
1206
1207 /* Hmm... whether or not this will work will depend on
1208 where the pc is. If it's still early in the prologue
1209 this'll be wrong. FIXME */
004d836a
JJ		 1210 if (next_frame)
1211 {
1212 frame_unwind_register (next_frame, sp_regnum, buf);
1213 saved_sp = extract_unsigned_integer (buf, 8);
1214 }
1215 spill_addr = saved_sp
16461d7d
KB		 1216 + (rM == 12 ? 0 : mem_stack_frame_size)
1217 + imm;
1218 spill_reg = rN;
1219 last_prologue_pc = next_pc;
1220 }
5ea2bd7f
JJ		 1221 else if (qp == 0 && rM >= 32 && rM < 40 && !instores[rM] &&
1222 rN < 256 && imm == 0)
1223 {
1224 /* mov rN, rM where rM is an input register */
1225 reg_contents[rN] = rM;
1226 last_prologue_pc = next_pc;
1227 }
1228 else if (frameless && qp == 0 && rN == fp_reg && imm == 0 &&
1229 rM == 2)
1230 {
1231 /* mov r12, r2 */
1232 last_prologue_pc = next_pc;
1233 break;
1234 }
16461d7d
KB		 1235 }
1236 else if (it == M
1237 && ( ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
1238 || ((instr & 0x1ffc8000000LL) == 0x0cec0000000LL) ))
1239 {
1240 /* stf.spill [rN] = fM, imm9
1241 or
1242 stf.spill [rN] = fM */
1243
1244 int imm = imm9(instr);
1245 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1246 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1247 int qp = (int) (instr & 0x0000000003fLL);
1248 if (qp == 0 && rN == spill_reg && spill_addr != 0
1249 && ((2 <= fM && fM <= 5) || (16 <= fM && fM <= 31)))
1250 {
004d836a 1251 cache->saved_regs[IA64_FR0_REGNUM + fM] = spill_addr;
16461d7d 1252
594706e6 1253 if ((instr & 0x1efc0000000LL) == 0x0eec0000000LL)
16461d7d
KB		 1254 spill_addr += imm;
1255 else
1256 spill_addr = 0; /* last one; must be done */
1257 last_prologue_pc = next_pc;
1258 }
1259 }
1260 else if ((it == M && ((instr & 0x1eff8000000LL) == 0x02110000000LL))
1261 || (it == I && ((instr & 0x1eff8000000LL) == 0x00050000000LL)) )
1262 {
1263 /* mov.m rN = arM
1264 or
1265 mov.i rN = arM */
1266
1267 int arM = (int) ((instr & 0x00007f00000LL) >> 20);
1268 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1269 int qp = (int) (instr & 0x0000000003fLL);
1270 if (qp == 0 && isScratch (rN) && arM == 36 /* ar.unat */)
1271 {
1272 /* We have something like "mov.m r3 = ar.unat". Remember the
1273 r3 (or whatever) and watch for a store of this register... */
1274 unat_save_reg = rN;
1275 last_prologue_pc = next_pc;
1276 }
1277 }
1278 else if (it == I && ((instr & 0x1eff8000000LL) == 0x00198000000LL))
1279 {
1280 /* mov rN = pr */
1281 int rN = (int) ((instr & 0x00000001fc0LL) >> 6);
1282 int qp = (int) (instr & 0x0000000003fLL);
1283 if (qp == 0 && isScratch (rN))
1284 {
1285 pr_save_reg = rN;
1286 last_prologue_pc = next_pc;
1287 }
1288 }
1289 else if (it == M
1290 && ( ((instr & 0x1ffc8000000LL) == 0x08cc0000000LL)
1291 || ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)))
1292 {
1293 /* st8 [rN] = rM
1294 or
1295 st8 [rN] = rM, imm9 */
1296 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1297 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1298 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1299 int indirect = rM < 256 ? reg_contents[rM] : 0;
16461d7d
KB		 1300 if (qp == 0 && rN == spill_reg && spill_addr != 0
1301 && (rM == unat_save_reg || rM == pr_save_reg))
1302 {
1303 /* We've found a spill of either the UNAT register or the PR
1304 register. (Well, not exactly; what we've actually found is
1305 a spill of the register that UNAT or PR was moved to).
1306 Record that fact and move on... */
1307 if (rM == unat_save_reg)
1308 {
1309 /* Track UNAT register */
004d836a 1310 cache->saved_regs[IA64_UNAT_REGNUM] = spill_addr;
16461d7d
KB		 1311 unat_save_reg = 0;
1312 }
1313 else
1314 {
1315 /* Track PR register */
004d836a 1316 cache->saved_regs[IA64_PR_REGNUM] = spill_addr;
16461d7d
KB		 1317 pr_save_reg = 0;
1318 }
1319 if ((instr & 0x1efc0000000LL) == 0x0acc0000000LL)
1320 /* st8 [rN] = rM, imm9 */
1321 spill_addr += imm9(instr);
1322 else
1323 spill_addr = 0; /* must be done spilling */
1324 last_prologue_pc = next_pc;
1325 }
0927a22b
KB		 1326 else if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1327 {
1328 /* Allow up to one store of each input register. */
1329 instores[rM-32] = 1;
1330 last_prologue_pc = next_pc;
1331 }
5ea2bd7f
JJ		 1332 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1333 !instores[indirect-32])
1334 {
1335 /* Allow an indirect store of an input register. */
1336 instores[indirect-32] = 1;
1337 last_prologue_pc = next_pc;
1338 }
0927a22b
KB		 1339 }
1340 else if (it == M && ((instr & 0x1ff08000000LL) == 0x08c00000000LL))
1341 {
1342 /* One of
1343 st1 [rN] = rM
1344 st2 [rN] = rM
1345 st4 [rN] = rM
1346 st8 [rN] = rM
1347 Note that the st8 case is handled in the clause above.
1348
1349 Advance over stores of input registers. One store per input
1350 register is permitted. */
1351 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1352 int qp = (int) (instr & 0x0000000003fLL);
5ea2bd7f 1353 int indirect = rM < 256 ? reg_contents[rM] : 0;
0927a22b
KB		 1354 if (qp == 0 && 32 <= rM && rM < 40 && !instores[rM-32])
1355 {
1356 instores[rM-32] = 1;
1357 last_prologue_pc = next_pc;
1358 }
5ea2bd7f
JJ		 1359 else if (qp == 0 && 32 <= indirect && indirect < 40 &&
1360 !instores[indirect-32])
1361 {
1362 /* Allow an indirect store of an input register. */
1363 instores[indirect-32] = 1;
1364 last_prologue_pc = next_pc;
1365 }
0927a22b
KB		 1366 }
1367 else if (it == M && ((instr & 0x1ff88000000LL) == 0x0cc80000000LL))
1368 {
1369 /* Either
1370 stfs [rN] = fM
1371 or
1372 stfd [rN] = fM
1373
1374 Advance over stores of floating point input registers. Again
1375 one store per register is permitted */
1376 int fM = (int) ((instr & 0x000000fe000LL) >> 13);
1377 int qp = (int) (instr & 0x0000000003fLL);
1378 if (qp == 0 && 8 <= fM && fM < 16 && !infpstores[fM - 8])
1379 {
1380 infpstores[fM-8] = 1;
1381 last_prologue_pc = next_pc;
1382 }
16461d7d
KB		 1383 }
1384 else if (it == M
1385 && ( ((instr & 0x1ffc8000000LL) == 0x08ec0000000LL)
1386 || ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)))
1387 {
1388 /* st8.spill [rN] = rM
1389 or
1390 st8.spill [rN] = rM, imm9 */
1391 int rN = (int) ((instr & 0x00007f00000LL) >> 20);
1392 int rM = (int) ((instr & 0x000000fe000LL) >> 13);
1393 int qp = (int) (instr & 0x0000000003fLL);
1394 if (qp == 0 && rN == spill_reg && 4 <= rM && rM <= 7)
1395 {
1396 /* We've found a spill of one of the preserved general purpose
1397 regs. Record the spill address and advance the spill
1398 register if appropriate. */
004d836a 1399 cache->saved_regs[IA64_GR0_REGNUM + rM] = spill_addr;
16461d7d
KB		 1400 if ((instr & 0x1efc0000000LL) == 0x0aec0000000LL)
1401 /* st8.spill [rN] = rM, imm9 */
1402 spill_addr += imm9(instr);
1403 else
1404 spill_addr = 0; /* Done spilling */
1405 last_prologue_pc = next_pc;
1406 }
1407 }
16461d7d
KB		 1408
1409 pc = next_pc;
1410 }
1411
004d836a
JJ		 1412 /* If not frameless and we aren't called by skip_prologue, then we need to calculate
1413 registers for the previous frame which will be needed later. */
16461d7d 1414
004d836a 1415 if (!frameless && next_frame)
da50a4b7 1416 {
004d836a
JJ		 1417 /* Extract the size of the rotating portion of the stack
1418 frame and the register rename base from the current
1419 frame marker. */
1420 cfm = cache->cfm;
1421 sor = cache->sor;
1422 sof = cache->sof;
1423 sol = cache->sol;
1424 rrb_gr = (cfm >> 18) & 0x7f;
1425
1426 /* Find the bof (beginning of frame). */
1427 bof = rse_address_add (cache->bsp, -sof);
1428
1429 for (i = 0, addr = bof;
1430 i < sof;
1431 i++, addr += 8)
1432 {
1433 if (IS_NaT_COLLECTION_ADDR (addr))
1434 {
1435 addr += 8;
1436 }
1437 if (i+32 == cfm_reg)
1438 cache->saved_regs[IA64_CFM_REGNUM] = addr;
1439 if (i+32 == ret_reg)
1440 cache->saved_regs[IA64_VRAP_REGNUM] = addr;
1441 if (i+32 == fp_reg)
1442 cache->saved_regs[IA64_VFP_REGNUM] = addr;
1443 }
16461d7d 1444
004d836a
JJ		 1445 /* For the previous argument registers we require the previous bof.
1446 If we can't find the previous cfm, then we can do nothing. */
4afcc598 1447 cfm = 0;
004d836a
JJ		 1448 if (cache->saved_regs[IA64_CFM_REGNUM] != 0)
1449 {
1450 cfm = read_memory_integer (cache->saved_regs[IA64_CFM_REGNUM], 8);
4afcc598
JJ		 1451 }
1452 else if (cfm_reg != 0)
1453 {
1454 frame_unwind_register (next_frame, cfm_reg, buf);
1455 cfm = extract_unsigned_integer (buf, 8);
1456 }
1457 cache->prev_cfm = cfm;
1458
1459 if (cfm != 0)
1460 {
004d836a
JJ		 1461 sor = ((cfm >> 14) & 0xf) * 8;
1462 sof = (cfm & 0x7f);
1463 sol = (cfm >> 7) & 0x7f;
1464 rrb_gr = (cfm >> 18) & 0x7f;
1465
1466 /* The previous bof only requires subtraction of the sol (size of locals)
1467 due to the overlap between output and input of subsequent frames. */
1468 bof = rse_address_add (bof, -sol);
1469
1470 for (i = 0, addr = bof;
1471 i < sof;
1472 i++, addr += 8)
1473 {
1474 if (IS_NaT_COLLECTION_ADDR (addr))
1475 {
1476 addr += 8;
1477 }
1478 if (i < sor)
1479 cache->saved_regs[IA64_GR32_REGNUM + ((i + (sor - rrb_gr)) % sor)]
1480 = addr;
1481 else
1482 cache->saved_regs[IA64_GR32_REGNUM + i] = addr;
1483 }
1484
1485 }
1486 }
1487
5ea2bd7f
JJ		 1488 /* Try and trust the lim_pc value whenever possible. */
1489 if (trust_limit && lim_pc >= last_prologue_pc)
004d836a
JJ		 1490 last_prologue_pc = lim_pc;
1491
1492 cache->frameless = frameless;
1493 cache->after_prologue = last_prologue_pc;
1494 cache->mem_stack_frame_size = mem_stack_frame_size;
1495 cache->fp_reg = fp_reg;
5ea2bd7f 1496
16461d7d
KB		 1497 return last_prologue_pc;
1498}
1499
1500CORE_ADDR
1501ia64_skip_prologue (CORE_ADDR pc)
1502{
004d836a
JJ		 1503 struct ia64_frame_cache cache;
1504 cache.base = 0;
1505 cache.after_prologue = 0;
1506 cache.cfm = 0;
1507 cache.bsp = 0;
1508
1509 /* Call examine_prologue with - as third argument since we don't have a next frame pointer to send. */
1510 return examine_prologue (pc, pc+1024, 0, &cache);
16461d7d
KB		 1511}
1512
004d836a
JJ		 1513
1514/* Normal frames. */
1515
1516static struct ia64_frame_cache *
1517ia64_frame_cache (struct frame_info *next_frame, void **this_cache)
16461d7d 1518{
004d836a
JJ		 1519 struct ia64_frame_cache *cache;
1520 char buf[8];
1521 CORE_ADDR cfm, sof, sol, bsp, psr;
1522 int i;
16461d7d 1523
004d836a
JJ		 1524 if (*this_cache)
1525 return *this_cache;
16461d7d 1526
004d836a
JJ		 1527 cache = ia64_alloc_frame_cache ();
1528 *this_cache = cache;
16461d7d 1529
004d836a
JJ		 1530 frame_unwind_register (next_frame, sp_regnum, buf);
1531 cache->saved_sp = extract_unsigned_integer (buf, 8);
16461d7d 1532
004d836a
JJ		 1533 /* We always want the bsp to point to the end of frame.
1534 This way, we can always get the beginning of frame (bof)
1535 by subtracting frame size. */
1536 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1537 cache->bsp = extract_unsigned_integer (buf, 8);
1538
1539 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1540 psr = extract_unsigned_integer (buf, 8);
1541
1542 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1543 cfm = extract_unsigned_integer (buf, 8);
1544
1545 cache->sof = (cfm & 0x7f);
1546 cache->sol = (cfm >> 7) & 0x7f;
1547 cache->sor = ((cfm >> 14) & 0xf) * 8;
1548
1549 cache->cfm = cfm;
1550
1551 cache->pc = frame_func_unwind (next_frame);
1552
1553 if (cache->pc != 0)
1554 examine_prologue (cache->pc, frame_pc_unwind (next_frame), next_frame, cache);
1555
1556 cache->base = cache->saved_sp + cache->mem_stack_frame_size;
1557
1558 return cache;
16461d7d
KB		 1559}
1560
a78f21af 1561static void
004d836a
JJ		 1562ia64_frame_this_id (struct frame_info *next_frame, void **this_cache,
1563 struct frame_id *this_id)
16461d7d 1564{
004d836a
JJ		 1565 struct ia64_frame_cache *cache =
1566 ia64_frame_cache (next_frame, this_cache);
16461d7d 1567
c5a27d9c 1568 /* If outermost frame, mark with null frame id. */
004d836a 1569 if (cache->base == 0)
c5a27d9c
JJ		 1570 (*this_id) = null_frame_id;
1571 else
1572 (*this_id) = frame_id_build_special (cache->base, cache->pc, cache->bsp);
4afcc598
JJ		 1573 if (gdbarch_debug >= 1)
1574 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1575 "regular frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1576 paddr_nz (this_id->code_addr),
1577 paddr_nz (this_id->stack_addr),
1578 paddr_nz (cache->bsp), next_frame);
004d836a 1579}
244bc108 1580
004d836a
JJ		 1581static void
1582ia64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1583 int regnum, int *optimizedp,
1584 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 1585 int *realnump, gdb_byte *valuep)
004d836a
JJ		 1586{
1587 struct ia64_frame_cache *cache =
1588 ia64_frame_cache (next_frame, this_cache);
1589 char dummy_valp[MAX_REGISTER_SIZE];
1590 char buf[8];
1591
1592 gdb_assert (regnum >= 0);
244bc108 1593
004d836a 1594 if (!target_has_registers)
8a3fe4f8 1595 error (_("No registers."));
244bc108 1596
004d836a
JJ		 1597 *optimizedp = 0;
1598 *addrp = 0;
1599 *lvalp = not_lval;
1600 *realnump = -1;
244bc108 1601
004d836a
JJ		 1602 /* Rather than check each time if valuep is non-null, supply a dummy buffer
1603 when valuep is not supplied. */
1604 if (!valuep)
1605 valuep = dummy_valp;
1606
aa2a9a3c 1607 memset (valuep, 0, register_size (current_gdbarch, regnum));
004d836a
JJ		 1608
1609 if (regnum == SP_REGNUM)
16461d7d
KB		 1610 {
1611 /* Handle SP values for all frames but the topmost. */
aa2a9a3c 1612 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a 1613 cache->base);
16461d7d
KB		 1614 }
1615 else if (regnum == IA64_BSP_REGNUM)
1616 {
004d836a
JJ		 1617 char cfm_valuep[MAX_REGISTER_SIZE];
1618 int cfm_optim;
1619 int cfm_realnum;
1620 enum lval_type cfm_lval;
1621 CORE_ADDR cfm_addr;
1622 CORE_ADDR bsp, prev_cfm, prev_bsp;
1623
1624 /* We want to calculate the previous bsp as the end of the previous register stack frame.
1625 This corresponds to what the hardware bsp register will be if we pop the frame
1626 back which is why we might have been called. We know the beginning of the current
aa2a9a3c 1627 frame is cache->bsp - cache->sof. This value in the previous frame points to
004d836a
JJ		 1628 the start of the output registers. We can calculate the end of that frame by adding
1629 the size of output (sof (size of frame) - sol (size of locals)). */
1630 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1631 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
1632 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
1633
1634 bsp = rse_address_add (cache->bsp, -(cache->sof));
1635 prev_bsp = rse_address_add (bsp, (prev_cfm & 0x7f) - ((prev_cfm >> 7) & 0x7f));
1636
aa2a9a3c 1637 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
004d836a
JJ		 1638 prev_bsp);
1639 }
1640 else if (regnum == IA64_CFM_REGNUM)
1641 {
4afcc598
JJ		 1642 CORE_ADDR addr = cache->saved_regs[IA64_CFM_REGNUM];
1643
1644 if (addr != 0)
004d836a 1645 {
4afcc598
JJ		 1646 *lvalp = lval_memory;
1647 *addrp = addr;
1648 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a 1649 }
4afcc598
JJ		 1650 else if (cache->prev_cfm)
1651 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), cache->prev_cfm);
1652 else if (cache->frameless)
004d836a 1653 {
4afcc598
JJ		 1654 CORE_ADDR cfm = 0;
1655 frame_unwind_register (next_frame, IA64_PFS_REGNUM, valuep);
004d836a 1656 }
16461d7d
KB		 1657 }
1658 else if (regnum == IA64_VFP_REGNUM)
1659 {
1660 /* If the function in question uses an automatic register (r32-r127)
1661 for the frame pointer, it'll be found by ia64_find_saved_register()
1662 above. If the function lacks one of these frame pointers, we can
004d836a
JJ		 1663 still provide a value since we know the size of the frame. */
1664 CORE_ADDR vfp = cache->base;
aa2a9a3c 1665 store_unsigned_integer (valuep, register_size (current_gdbarch, IA64_VFP_REGNUM), vfp);
16461d7d 1666 }
004d836a 1667 else if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
16461d7d 1668 {
004d836a 1669 char pr_valuep[MAX_REGISTER_SIZE];
16461d7d 1670 int pr_optim;
004d836a 1671 int pr_realnum;
16461d7d
KB		 1672 enum lval_type pr_lval;
1673 CORE_ADDR pr_addr;
004d836a
JJ		 1674 ULONGEST prN_val;
1675 ia64_frame_prev_register (next_frame, this_cache, IA64_PR_REGNUM,
1676 &pr_optim, &pr_lval, &pr_addr, &pr_realnum, pr_valuep);
1677 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
3a854e23
KB		 1678 {
1679 /* Fetch predicate register rename base from current frame
004d836a
JJ		 1680 marker for this frame. */
1681 int rrb_pr = (cache->cfm >> 32) & 0x3f;
3a854e23 1682
004d836a
JJ		 1683 /* Adjust the register number to account for register rotation. */
1684 regnum = VP16_REGNUM
1685 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
3a854e23 1686 }
004d836a
JJ		 1687 prN_val = extract_bit_field ((unsigned char *) pr_valuep,
1688 regnum - VP0_REGNUM, 1);
aa2a9a3c 1689 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
16461d7d
KB		 1690 }
1691 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT31_REGNUM)
1692 {
004d836a 1693 char unat_valuep[MAX_REGISTER_SIZE];
16461d7d 1694 int unat_optim;
004d836a 1695 int unat_realnum;
16461d7d
KB		 1696 enum lval_type unat_lval;
1697 CORE_ADDR unat_addr;
004d836a
JJ		 1698 ULONGEST unatN_val;
1699 ia64_frame_prev_register (next_frame, this_cache, IA64_UNAT_REGNUM,
1700 &unat_optim, &unat_lval, &unat_addr, &unat_realnum, unat_valuep);
1701 unatN_val = extract_bit_field ((unsigned char *) unat_valuep,
16461d7d 1702 regnum - IA64_NAT0_REGNUM, 1);
aa2a9a3c 1703 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
16461d7d 1704 unatN_val);
16461d7d
KB		 1705 }
1706 else if (IA64_NAT32_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
1707 {
1708 int natval = 0;
1709 /* Find address of general register corresponding to nat bit we're
004d836a
JJ		 1710 interested in. */
1711 CORE_ADDR gr_addr;
244bc108 1712
004d836a
JJ		 1713 gr_addr = cache->saved_regs[regnum - IA64_NAT0_REGNUM
1714 + IA64_GR0_REGNUM];
1715 if (gr_addr != 0)
244bc108 1716 {
004d836a 1717 /* Compute address of nat collection bits. */
16461d7d 1718 CORE_ADDR nat_addr = gr_addr | 0x1f8;
004d836a 1719 CORE_ADDR bsp;
16461d7d
KB		 1720 CORE_ADDR nat_collection;
1721 int nat_bit;
1722 /* If our nat collection address is bigger than bsp, we have to get
1723 the nat collection from rnat. Otherwise, we fetch the nat
004d836a
JJ		 1724 collection from the computed address. */
1725 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1726 bsp = extract_unsigned_integer (buf, 8);
16461d7d 1727 if (nat_addr >= bsp)
004d836a
JJ		 1728 {
1729 frame_unwind_register (next_frame, IA64_RNAT_REGNUM, buf);
1730 nat_collection = extract_unsigned_integer (buf, 8);
1731 }
16461d7d
KB		 1732 else
1733 nat_collection = read_memory_integer (nat_addr, 8);
1734 nat_bit = (gr_addr >> 3) & 0x3f;
1735 natval = (nat_collection >> nat_bit) & 1;
1736 }
004d836a 1737
aa2a9a3c 1738 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), natval);
244bc108
KB		 1739 }
1740 else if (regnum == IA64_IP_REGNUM)
1741 {
004d836a 1742 CORE_ADDR pc = 0;
4afcc598 1743 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a 1744
4afcc598 1745 if (addr != 0)
004d836a 1746 {
4afcc598
JJ		 1747 *lvalp = lval_memory;
1748 *addrp = addr;
1749 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a
JJ		 1750 pc = extract_unsigned_integer (buf, 8);
1751 }
4afcc598 1752 else if (cache->frameless)
004d836a 1753 {
4afcc598
JJ		 1754 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1755 pc = extract_unsigned_integer (buf, 8);
244bc108 1756 }
004d836a
JJ		 1757 pc &= ~0xf;
1758 store_unsigned_integer (valuep, 8, pc);
244bc108 1759 }
004d836a 1760 else if (regnum == IA64_PSR_REGNUM)
244bc108 1761 {
4afcc598
JJ		 1762 /* We don't know how to get the complete previous PSR, but we need it for
1763 the slot information when we unwind the pc (pc is formed of IP register
1764 plus slot information from PSR). To get the previous slot information,
1765 we mask it off the return address. */
004d836a
JJ		 1766 ULONGEST slot_num = 0;
1767 CORE_ADDR pc= 0;
1768 CORE_ADDR psr = 0;
4afcc598 1769 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
004d836a
JJ		 1770
1771 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
1772 psr = extract_unsigned_integer (buf, 8);
1773
4afcc598 1774 if (addr != 0)
244bc108 1775 {
4afcc598
JJ		 1776 *lvalp = lval_memory;
1777 *addrp = addr;
1778 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
004d836a 1779 pc = extract_unsigned_integer (buf, 8);
244bc108 1780 }
4afcc598 1781 else if (cache->frameless)
004d836a 1782 {
4afcc598
JJ		 1783 CORE_ADDR pc;
1784 frame_unwind_register (next_frame, IA64_BR0_REGNUM, buf);
1785 pc = extract_unsigned_integer (buf, 8);
004d836a
JJ		 1786 }
1787 psr &= ~(3LL << 41);
1788 slot_num = pc & 0x3LL;
1789 psr |= (CORE_ADDR)slot_num << 41;
1790 store_unsigned_integer (valuep, 8, psr);
1791 }
4afcc598
JJ		 1792 else if (regnum == IA64_BR0_REGNUM)
1793 {
1794 CORE_ADDR br0 = 0;
1795 CORE_ADDR addr = cache->saved_regs[IA64_BR0_REGNUM];
1796 if (addr != 0)
1797 {
1798 *lvalp = lval_memory;
1799 *addrp = addr;
1800 read_memory (addr, buf, register_size (current_gdbarch, IA64_BR0_REGNUM));
1801 br0 = extract_unsigned_integer (buf, 8);
1802 }
1803 store_unsigned_integer (valuep, 8, br0);
1804 }
004d836a
JJ		 1805 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
1806 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
1807 {
1808 CORE_ADDR addr = 0;
1809 if (regnum >= V32_REGNUM)
1810 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1811 addr = cache->saved_regs[regnum];
244bc108
KB		 1812 if (addr != 0)
1813 {
004d836a
JJ		 1814 *lvalp = lval_memory;
1815 *addrp = addr;
aa2a9a3c 1816 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1817 }
004d836a 1818 else if (cache->frameless)
244bc108 1819 {
004d836a
JJ		 1820 char r_valuep[MAX_REGISTER_SIZE];
1821 int r_optim;
1822 int r_realnum;
1823 enum lval_type r_lval;
1824 CORE_ADDR r_addr;
1825 CORE_ADDR prev_cfm, prev_bsp, prev_bof;
1826 CORE_ADDR addr = 0;
1827 if (regnum >= V32_REGNUM)
1828 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
1829 ia64_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
1830 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1831 prev_cfm = extract_unsigned_integer (r_valuep, 8);
1832 ia64_frame_prev_register (next_frame, this_cache, IA64_BSP_REGNUM,
1833 &r_optim, &r_lval, &r_addr, &r_realnum, r_valuep);
1834 prev_bsp = extract_unsigned_integer (r_valuep, 8);
1835 prev_bof = rse_address_add (prev_bsp, -(prev_cfm & 0x7f));
1836
1837 addr = rse_address_add (prev_bof, (regnum - IA64_GR32_REGNUM));
1838 *lvalp = lval_memory;
1839 *addrp = addr;
aa2a9a3c 1840 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
244bc108 1841 }
16461d7d
KB		 1842 }
1843 else
1844 {
004d836a 1845 CORE_ADDR addr = 0;
3a854e23
KB		 1846 if (IA64_FR32_REGNUM <= regnum && regnum <= IA64_FR127_REGNUM)
1847 {
1848 /* Fetch floating point register rename base from current
004d836a
JJ		 1849 frame marker for this frame. */
1850 int rrb_fr = (cache->cfm >> 25) & 0x7f;
3a854e23
KB		 1851
1852 /* Adjust the floating point register number to account for
004d836a 1853 register rotation. */
3a854e23
KB		 1854 regnum = IA64_FR32_REGNUM
1855 + ((regnum - IA64_FR32_REGNUM) + rrb_fr) % 96;
1856 }
1857
004d836a
JJ		 1858 /* If we have stored a memory address, access the register. */
1859 addr = cache->saved_regs[regnum];
1860 if (addr != 0)
1861 {
1862 *lvalp = lval_memory;
1863 *addrp = addr;
aa2a9a3c 1864 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
004d836a
JJ		 1865 }
1866 /* Otherwise, punt and get the current value of the register. */
1867 else
1868 frame_unwind_register (next_frame, regnum, valuep);
16461d7d 1869 }
4afcc598
JJ		 1870
1871 if (gdbarch_debug >= 1)
1872 fprintf_unfiltered (gdb_stdlog,
78ced177 1873 "regular prev register <%d> <%s> is 0x%s\n", regnum,
4afcc598 1874 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 1875 ? ia64_register_names[regnum] : "r??"),
1876 paddr_nz (extract_unsigned_integer (valuep, 8)));
16461d7d 1877}
004d836a
JJ		 1878
1879static const struct frame_unwind ia64_frame_unwind =
1880{
1881 NORMAL_FRAME,
1882 &ia64_frame_this_id,
1883 &ia64_frame_prev_register
1884};
1885
1886static const struct frame_unwind *
1887ia64_frame_sniffer (struct frame_info *next_frame)
1888{
1889 return &ia64_frame_unwind;
1890}
1891
1892/* Signal trampolines. */
1893
1894static void
1895ia64_sigtramp_frame_init_saved_regs (struct ia64_frame_cache *cache)
1896{
1897 if (SIGCONTEXT_REGISTER_ADDRESS)
1898 {
1899 int regno;
1900
1901 cache->saved_regs[IA64_VRAP_REGNUM] =
1902 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_IP_REGNUM);
1903 cache->saved_regs[IA64_CFM_REGNUM] =
1904 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CFM_REGNUM);
1905 cache->saved_regs[IA64_PSR_REGNUM] =
1906 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PSR_REGNUM);
004d836a 1907 cache->saved_regs[IA64_BSP_REGNUM] =
4afcc598 1908 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_BSP_REGNUM);
004d836a
JJ		 1909 cache->saved_regs[IA64_RNAT_REGNUM] =
1910 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_RNAT_REGNUM);
1911 cache->saved_regs[IA64_CCV_REGNUM] =
1912 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_CCV_REGNUM);
1913 cache->saved_regs[IA64_UNAT_REGNUM] =
1914 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_UNAT_REGNUM);
1915 cache->saved_regs[IA64_FPSR_REGNUM] =
1916 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_FPSR_REGNUM);
1917 cache->saved_regs[IA64_PFS_REGNUM] =
1918 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_PFS_REGNUM);
1919 cache->saved_regs[IA64_LC_REGNUM] =
1920 SIGCONTEXT_REGISTER_ADDRESS (cache->base, IA64_LC_REGNUM);
1921 for (regno = IA64_GR1_REGNUM; regno <= IA64_GR31_REGNUM; regno++)
4afcc598
JJ		 1922 cache->saved_regs[regno] =
1923 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
004d836a
JJ		 1924 for (regno = IA64_BR0_REGNUM; regno <= IA64_BR7_REGNUM; regno++)
1925 cache->saved_regs[regno] =
1926 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
932644f0 1927 for (regno = IA64_FR2_REGNUM; regno <= IA64_FR31_REGNUM; regno++)
004d836a
JJ		 1928 cache->saved_regs[regno] =
1929 SIGCONTEXT_REGISTER_ADDRESS (cache->base, regno);
1930 }
1931}
1932
1933static struct ia64_frame_cache *
1934ia64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache)
1935{
1936 struct ia64_frame_cache *cache;
1937 CORE_ADDR addr;
1938 char buf[8];
1939 int i;
1940
1941 if (*this_cache)
1942 return *this_cache;
1943
1944 cache = ia64_alloc_frame_cache ();
1945
1946 frame_unwind_register (next_frame, sp_regnum, buf);
4afcc598
JJ		 1947 /* Note that frame size is hard-coded below. We cannot calculate it
1948 via prologue examination. */
1949 cache->base = extract_unsigned_integer (buf, 8) + 16;
1950
1951 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
1952 cache->bsp = extract_unsigned_integer (buf, 8);
1953
1954 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
1955 cache->cfm = extract_unsigned_integer (buf, 8);
1956 cache->sof = cache->cfm & 0x7f;
004d836a
JJ		 1957
1958 ia64_sigtramp_frame_init_saved_regs (cache);
1959
1960 *this_cache = cache;
1961 return cache;
1962}
1963
1964static void
1965ia64_sigtramp_frame_this_id (struct frame_info *next_frame,
1966 void **this_cache, struct frame_id *this_id)
1967{
1968 struct ia64_frame_cache *cache =
1969 ia64_sigtramp_frame_cache (next_frame, this_cache);
1970
4afcc598
JJ		 1971 (*this_id) = frame_id_build_special (cache->base, frame_pc_unwind (next_frame), cache->bsp);
1972 if (gdbarch_debug >= 1)
1973 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 1974 "sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
1975 paddr_nz (this_id->code_addr),
1976 paddr_nz (this_id->stack_addr),
1977 paddr_nz (cache->bsp), next_frame);
004d836a
JJ		 1978}
1979
1980static void
1981ia64_sigtramp_frame_prev_register (struct frame_info *next_frame,
1982 void **this_cache,
1983 int regnum, int *optimizedp,
1984 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 1985 int *realnump, gdb_byte *valuep)
004d836a 1986{
4afcc598
JJ		 1987 char dummy_valp[MAX_REGISTER_SIZE];
1988 char buf[MAX_REGISTER_SIZE];
1989
1990 struct ia64_frame_cache *cache =
1991 ia64_sigtramp_frame_cache (next_frame, this_cache);
1992
1993 gdb_assert (regnum >= 0);
1994
1995 if (!target_has_registers)
8a3fe4f8 1996 error (_("No registers."));
4afcc598
JJ		 1997
1998 *optimizedp = 0;
1999 *addrp = 0;
2000 *lvalp = not_lval;
2001 *realnump = -1;
2002
2003 /* Rather than check each time if valuep is non-null, supply a dummy buffer
2004 when valuep is not supplied. */
2005 if (!valuep)
2006 valuep = dummy_valp;
2007
2008 memset (valuep, 0, register_size (current_gdbarch, regnum));
2009
2010 if (regnum == IA64_IP_REGNUM)
2011 {
2012 CORE_ADDR pc = 0;
2013 CORE_ADDR addr = cache->saved_regs[IA64_VRAP_REGNUM];
2014
2015 if (addr != 0)
2016 {
2017 *lvalp = lval_memory;
2018 *addrp = addr;
2019 read_memory (addr, buf, register_size (current_gdbarch, IA64_IP_REGNUM));
2020 pc = extract_unsigned_integer (buf, 8);
2021 }
2022 pc &= ~0xf;
2023 store_unsigned_integer (valuep, 8, pc);
2024 }
2025 else if ((regnum >= IA64_GR32_REGNUM && regnum <= IA64_GR127_REGNUM) ||
2026 (regnum >= V32_REGNUM && regnum <= V127_REGNUM))
2027 {
2028 CORE_ADDR addr = 0;
2029 if (regnum >= V32_REGNUM)
2030 regnum = IA64_GR32_REGNUM + (regnum - V32_REGNUM);
2031 addr = cache->saved_regs[regnum];
2032 if (addr != 0)
2033 {
2034 *lvalp = lval_memory;
2035 *addrp = addr;
2036 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2037 }
2038 }
2039 else
2040 {
2041 /* All other registers not listed above. */
2042 CORE_ADDR addr = cache->saved_regs[regnum];
2043 if (addr != 0)
2044 {
2045 *lvalp = lval_memory;
2046 *addrp = addr;
2047 read_memory (addr, valuep, register_size (current_gdbarch, regnum));
2048 }
2049 }
004d836a 2050
4afcc598
JJ		 2051 if (gdbarch_debug >= 1)
2052 fprintf_unfiltered (gdb_stdlog,
78ced177 2053 "sigtramp prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2054 (regnum < IA64_GR32_REGNUM
2055 || (regnum > IA64_GR127_REGNUM
2056 && regnum < LAST_PSEUDO_REGNUM))
2057 ? ia64_register_names[regnum]
2058 : (regnum < LAST_PSEUDO_REGNUM
2059 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2060 : "OUT_OF_RANGE"),
78ced177 2061 paddr_nz (extract_unsigned_integer (valuep, 8)));
004d836a
JJ		 2062}
2063
2064static const struct frame_unwind ia64_sigtramp_frame_unwind =
2065{
2066 SIGTRAMP_FRAME,
2067 ia64_sigtramp_frame_this_id,
2068 ia64_sigtramp_frame_prev_register
2069};
2070
2071static const struct frame_unwind *
2072ia64_sigtramp_frame_sniffer (struct frame_info *next_frame)
2073{
2074 char *name;
2075 CORE_ADDR pc = frame_pc_unwind (next_frame);
2076
2077 find_pc_partial_function (pc, &name, NULL, NULL);
0b281939 2078 if (legacy_pc_in_sigtramp (pc, name))
004d836a
JJ		 2079 return &ia64_sigtramp_frame_unwind;
2080
2081 return NULL;
2082}
2083\f
2084
2085static CORE_ADDR
2086ia64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2087{
2088 struct ia64_frame_cache *cache =
2089 ia64_frame_cache (next_frame, this_cache);
2090
2091 return cache->base;
2092}
2093
2094static const struct frame_base ia64_frame_base =
2095{
2096 &ia64_frame_unwind,
2097 ia64_frame_base_address,
2098 ia64_frame_base_address,
2099 ia64_frame_base_address
2100};
16461d7d 2101
968d1cb4
JJ		 2102#ifdef HAVE_LIBUNWIND_IA64_H
2103
2104struct ia64_unwind_table_entry
2105 {
2106 unw_word_t start_offset;
2107 unw_word_t end_offset;
2108 unw_word_t info_offset;
2109 };
2110
2111static __inline__ uint64_t
2112ia64_rse_slot_num (uint64_t addr)
2113{
2114 return (addr >> 3) & 0x3f;
2115}
2116
2117/* Skip over a designated number of registers in the backing
2118 store, remembering every 64th position is for NAT. */
2119static __inline__ uint64_t
2120ia64_rse_skip_regs (uint64_t addr, long num_regs)
2121{
2122 long delta = ia64_rse_slot_num(addr) + num_regs;
2123
2124 if (num_regs < 0)
2125 delta -= 0x3e;
2126 return addr + ((num_regs + delta/0x3f) << 3);
2127}
2128
2129/* Gdb libunwind-frame callback function to convert from an ia64 gdb register
2130 number to a libunwind register number. */
2131static int
2132ia64_gdb2uw_regnum (int regnum)
2133{
2134 if (regnum == sp_regnum)
2135 return UNW_IA64_SP;
2136 else if (regnum == IA64_BSP_REGNUM)
2137 return UNW_IA64_BSP;
2138 else if ((unsigned) (regnum - IA64_GR0_REGNUM) < 128)
2139 return UNW_IA64_GR + (regnum - IA64_GR0_REGNUM);
2140 else if ((unsigned) (regnum - V32_REGNUM) < 95)
2141 return UNW_IA64_GR + 32 + (regnum - V32_REGNUM);
2142 else if ((unsigned) (regnum - IA64_FR0_REGNUM) < 128)
2143 return UNW_IA64_FR + (regnum - IA64_FR0_REGNUM);
2144 else if ((unsigned) (regnum - IA64_PR0_REGNUM) < 64)
2145 return -1;
2146 else if ((unsigned) (regnum - IA64_BR0_REGNUM) < 8)
2147 return UNW_IA64_BR + (regnum - IA64_BR0_REGNUM);
2148 else if (regnum == IA64_PR_REGNUM)
2149 return UNW_IA64_PR;
2150 else if (regnum == IA64_IP_REGNUM)
2151 return UNW_REG_IP;
2152 else if (regnum == IA64_CFM_REGNUM)
2153 return UNW_IA64_CFM;
2154 else if ((unsigned) (regnum - IA64_AR0_REGNUM) < 128)
2155 return UNW_IA64_AR + (regnum - IA64_AR0_REGNUM);
2156 else if ((unsigned) (regnum - IA64_NAT0_REGNUM) < 128)
2157 return UNW_IA64_NAT + (regnum - IA64_NAT0_REGNUM);
2158 else
2159 return -1;
2160}
2161
2162/* Gdb libunwind-frame callback function to convert from a libunwind register
2163 number to a ia64 gdb register number. */
2164static int
2165ia64_uw2gdb_regnum (int uw_regnum)
2166{
2167 if (uw_regnum == UNW_IA64_SP)
2168 return sp_regnum;
2169 else if (uw_regnum == UNW_IA64_BSP)
2170 return IA64_BSP_REGNUM;
2171 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 32)
2172 return IA64_GR0_REGNUM + (uw_regnum - UNW_IA64_GR);
2173 else if ((unsigned) (uw_regnum - UNW_IA64_GR) < 128)
2174 return V32_REGNUM + (uw_regnum - (IA64_GR0_REGNUM + 32));
2175 else if ((unsigned) (uw_regnum - UNW_IA64_FR) < 128)
2176 return IA64_FR0_REGNUM + (uw_regnum - UNW_IA64_FR);
2177 else if ((unsigned) (uw_regnum - UNW_IA64_BR) < 8)
2178 return IA64_BR0_REGNUM + (uw_regnum - UNW_IA64_BR);
2179 else if (uw_regnum == UNW_IA64_PR)
2180 return IA64_PR_REGNUM;
2181 else if (uw_regnum == UNW_REG_IP)
2182 return IA64_IP_REGNUM;
2183 else if (uw_regnum == UNW_IA64_CFM)
2184 return IA64_CFM_REGNUM;
2185 else if ((unsigned) (uw_regnum - UNW_IA64_AR) < 128)
2186 return IA64_AR0_REGNUM + (uw_regnum - UNW_IA64_AR);
2187 else if ((unsigned) (uw_regnum - UNW_IA64_NAT) < 128)
2188 return IA64_NAT0_REGNUM + (uw_regnum - UNW_IA64_NAT);
2189 else
2190 return -1;
2191}
2192
2193/* Gdb libunwind-frame callback function to reveal if register is a float
2194 register or not. */
2195static int
2196ia64_is_fpreg (int uw_regnum)
2197{
2198 return unw_is_fpreg (uw_regnum);
2199}
2200
2201/* Libunwind callback accessor function for general registers. */
2202static int
2203ia64_access_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2204 int write, void *arg)
2205{
2206 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2207 unw_word_t bsp, sof, sol, cfm, psr, ip;
2208 struct frame_info *next_frame = arg;
2209 long new_sof, old_sof;
2210 char buf[MAX_REGISTER_SIZE];
2211
2212 if (write)
2213 {
2214 if (regnum < 0)
2215 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2216 return 0;
2217
2218 switch (uw_regnum)
2219 {
2220 case UNW_REG_IP:
2221 ia64_write_pc (*val, inferior_ptid);
2222 break;
2223
2224 case UNW_IA64_AR_BSPSTORE:
2225 write_register (IA64_BSP_REGNUM, *val);
2226 break;
2227
2228 case UNW_IA64_AR_BSP:
2229 case UNW_IA64_BSP:
2230 /* Account for the fact that ptrace() expects bsp to point
2231 after the current register frame. */
2232 cfm = read_register (IA64_CFM_REGNUM);
2233 sof = (cfm & 0x7f);
2234 bsp = ia64_rse_skip_regs (*val, sof);
2235 write_register (IA64_BSP_REGNUM, bsp);
2236 break;
2237
2238 case UNW_IA64_CFM:
2239 /* If we change CFM, we need to adjust ptrace's notion of
2240 bsp accordingly, so that the real bsp remains
2241 unchanged. */
2242 bsp = read_register (IA64_BSP_REGNUM);
2243 cfm = read_register (IA64_CFM_REGNUM);
2244 old_sof = (cfm & 0x7f);
2245 new_sof = (*val & 0x7f);
2246 if (old_sof != new_sof)
2247 {
2248 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2249 write_register (IA64_BSP_REGNUM, bsp);
2250 }
2251 write_register (IA64_CFM_REGNUM, *val);
2252 break;
2253
2254 default:
2255 write_register (regnum, *val);
2256 break;
2257 }
2258 if (gdbarch_debug >= 1)
2259 fprintf_unfiltered (gdb_stdlog,
78ced177 2260 " access_reg: to cache: %4s=0x%s\n",
968d1cb4 2261 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2262 ? ia64_register_names[regnum] : "r??"),
2263 paddr_nz (*val));
968d1cb4
JJ		 2264 }
2265 else
2266 {
2267 switch (uw_regnum)
2268 {
2269 case UNW_REG_IP:
2270 /* Libunwind expects to see the pc value which means the slot number
2271 from the psr must be merged with the ip word address. */
2272 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
2273 ip = extract_unsigned_integer (buf, 8);
2274 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
2275 psr = extract_unsigned_integer (buf, 8);
2276 *val = ip | ((psr >> 41) & 0x3);
2277 break;
2278
2279 case UNW_IA64_AR_BSP:
2280 /* Libunwind expects to see the beginning of the current register
2281 frame so we must account for the fact that ptrace() will return a value
2282 for bsp that points *after* the current register frame. */
2283 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2284 bsp = extract_unsigned_integer (buf, 8);
2285 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2286 cfm = extract_unsigned_integer (buf, 8);
2287 sof = (cfm & 0x7f);
2288 *val = ia64_rse_skip_regs (bsp, -sof);
2289 break;
2290
2291 case UNW_IA64_AR_BSPSTORE:
2292 /* Libunwind wants bspstore to be after the current register frame.
2293 This is what ptrace() and gdb treats as the regular bsp value. */
2294 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2295 *val = extract_unsigned_integer (buf, 8);
2296 break;
2297
2298 default:
2299 /* For all other registers, just unwind the value directly. */
2300 frame_unwind_register (next_frame, regnum, buf);
2301 *val = extract_unsigned_integer (buf, 8);
2302 break;
2303 }
2304
2305 if (gdbarch_debug >= 1)
2306 fprintf_unfiltered (gdb_stdlog,
78ced177 2307 " access_reg: from cache: %4s=0x%s\n",
968d1cb4 2308 (((unsigned) regnum <= IA64_NAT127_REGNUM)
78ced177
JJ		 2309 ? ia64_register_names[regnum] : "r??"),
2310 paddr_nz (*val));
968d1cb4
JJ		 2311 }
2312 return 0;
2313}
2314
2315/* Libunwind callback accessor function for floating-point registers. */
2316static int
2317ia64_access_fpreg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_fpreg_t *val,
2318 int write, void *arg)
2319{
2320 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2321
2322 if (write)
2323 regcache_cooked_write (current_regcache, regnum, (char *) val);
2324 else
2325 regcache_cooked_read (current_regcache, regnum, (char *) val);
2326 return 0;
2327}
2328
c5a27d9c
JJ		 2329/* Libunwind callback accessor function for top-level rse registers. */
2330static int
2331ia64_access_rse_reg (unw_addr_space_t as, unw_regnum_t uw_regnum, unw_word_t *val,
2332 int write, void *arg)
2333{
2334 int regnum = ia64_uw2gdb_regnum (uw_regnum);
2335 unw_word_t bsp, sof, sol, cfm, psr, ip;
2336 long new_sof, old_sof;
2337
2338 if (write)
2339 {
2340 if (regnum < 0)
2341 /* ignore writes to pseudo-registers such as UNW_IA64_PROC_STARTI. */
2342 return 0;
2343
2344 switch (uw_regnum)
2345 {
2346 case UNW_REG_IP:
2347 ia64_write_pc (*val, inferior_ptid);
2348 break;
2349
2350 case UNW_IA64_AR_BSPSTORE:
2351 write_register (IA64_BSP_REGNUM, *val);
2352 break;
2353
2354 case UNW_IA64_AR_BSP:
2355 case UNW_IA64_BSP:
2356 /* Account for the fact that ptrace() expects bsp to point
2357 after the current register frame. */
2358 cfm = read_register (IA64_CFM_REGNUM);
2359 sof = (cfm & 0x7f);
2360 bsp = ia64_rse_skip_regs (*val, sof);
2361 write_register (IA64_BSP_REGNUM, bsp);
2362 break;
2363
2364 case UNW_IA64_CFM:
2365 /* If we change CFM, we need to adjust ptrace's notion of
2366 bsp accordingly, so that the real bsp remains
2367 unchanged. */
2368 bsp = read_register (IA64_BSP_REGNUM);
2369 cfm = read_register (IA64_CFM_REGNUM);
2370 old_sof = (cfm & 0x7f);
2371 new_sof = (*val & 0x7f);
2372 if (old_sof != new_sof)
2373 {
2374 bsp = ia64_rse_skip_regs (bsp, -old_sof + new_sof);
2375 write_register (IA64_BSP_REGNUM, bsp);
2376 }
2377 write_register (IA64_CFM_REGNUM, *val);
2378 break;
2379
2380 default:
2381 write_register (regnum, *val);
2382 break;
2383 }
2384 if (gdbarch_debug >= 1)
2385 fprintf_unfiltered (gdb_stdlog,
2386 " access_rse_reg: to cache: %4s=0x%s\n",
2387 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2388 ? ia64_register_names[regnum] : "r??"),
2389 paddr_nz (*val));
2390 }
2391 else
2392 {
2393 switch (uw_regnum)
2394 {
2395 case UNW_REG_IP:
2396 /* Libunwind expects to see the pc value which means the slot number
2397 from the psr must be merged with the ip word address. */
2398 ip = read_register (IA64_IP_REGNUM);
2399 psr = read_register (IA64_PSR_REGNUM);
2400 *val = ip | ((psr >> 41) & 0x3);
2401 break;
2402
2403 case UNW_IA64_AR_BSP:
2404 /* Libunwind expects to see the beginning of the current register
2405 frame so we must account for the fact that ptrace() will return a value
2406 for bsp that points *after* the current register frame. */
2407 bsp = read_register (IA64_BSP_REGNUM);
2408 cfm = read_register (IA64_CFM_REGNUM);
2409 sof = (cfm & 0x7f);
2410 *val = ia64_rse_skip_regs (bsp, -sof);
2411 break;
2412
2413 case UNW_IA64_AR_BSPSTORE:
2414 /* Libunwind wants bspstore to be after the current register frame.
2415 This is what ptrace() and gdb treats as the regular bsp value. */
2416 *val = read_register (IA64_BSP_REGNUM);
2417 break;
2418
2419 default:
2420 /* For all other registers, just read the value directly. */
2421 *val = read_register (regnum);
2422 break;
2423 }
2424 }
2425
2426 if (gdbarch_debug >= 1)
2427 fprintf_unfiltered (gdb_stdlog,
2428 " access_rse_reg: from cache: %4s=0x%s\n",
2429 (((unsigned) regnum <= IA64_NAT127_REGNUM)
2430 ? ia64_register_names[regnum] : "r??"),
2431 paddr_nz (*val));
2432
2433 return 0;
2434}
2435
968d1cb4
JJ		 2436/* Libunwind callback accessor function for accessing memory. */
2437static int
2438ia64_access_mem (unw_addr_space_t as,
2439 unw_word_t addr, unw_word_t *val,
2440 int write, void *arg)
2441{
c5a27d9c
JJ		 2442 if (addr - KERNEL_START < ktab_size)
2443 {
2444 unw_word_t *laddr = (unw_word_t*) ((char *) ktab
2445 + (addr - KERNEL_START));
2446
2447 if (write)
2448 *laddr = *val;
2449 else
2450 *val = *laddr;
2451 return 0;
2452 }
2453
968d1cb4
JJ		 2454 /* XXX do we need to normalize byte-order here? */
2455 if (write)
2456 return target_write_memory (addr, (char *) val, sizeof (unw_word_t));
2457 else
2458 return target_read_memory (addr, (char *) val, sizeof (unw_word_t));
2459}
2460
2461/* Call low-level function to access the kernel unwind table. */
13547ab6
DJ		 2462static LONGEST
2463getunwind_table (gdb_byte **buf_p)
968d1cb4
JJ		 2464{
2465 LONGEST x;
c5a27d9c 2466
10d6c8cd
DJ		 2467 /* FIXME drow/2005-09-10: This code used to call
2468 ia64_linux_xfer_unwind_table directly to fetch the unwind table
2469 for the currently running ia64-linux kernel. That data should
2470 come from the core file and be accessed via the auxv vector; if
2471 we want to preserve fall back to the running kernel's table, then
2472 we should find a way to override the corefile layer's
2473 xfer_partial method. */
968d1cb4 2474
13547ab6
DJ		 2475 x = target_read_alloc (&current_target, TARGET_OBJECT_UNWIND_TABLE,
2476 NULL, buf_p);
2477
2478 return x;
968d1cb4 2479}
10d6c8cd 2480
968d1cb4
JJ		 2481/* Get the kernel unwind table. */
2482static int
2483get_kernel_table (unw_word_t ip, unw_dyn_info_t *di)
2484{
c5a27d9c 2485 static struct ia64_table_entry *etab;
968d1cb4 2486
c5a27d9c 2487 if (!ktab)
968d1cb4 2488 {
13547ab6 2489 gdb_byte *ktab_buf;
eeec829c 2490 LONGEST size;
13547ab6 2491
eeec829c
DJ		 2492 size = getunwind_table (&ktab_buf);
2493 if (size <= 0)
13547ab6 2494 return -UNW_ENOINFO;
eeec829c
DJ		 2495
2496 ktab = (struct ia64_table_entry *) ktab_buf;
2497 ktab_size = size;
13547ab6 2498
968d1cb4 2499 for (etab = ktab; etab->start_offset; ++etab)
c5a27d9c 2500 etab->info_offset += KERNEL_START;
968d1cb4
JJ		 2501 }
2502
2503 if (ip < ktab[0].start_offset || ip >= etab[-1].end_offset)
2504 return -UNW_ENOINFO;
2505
2506 di->format = UNW_INFO_FORMAT_TABLE;
2507 di->gp = 0;
2508 di->start_ip = ktab[0].start_offset;
2509 di->end_ip = etab[-1].end_offset;
2510 di->u.ti.name_ptr = (unw_word_t) "<kernel>";
2511 di->u.ti.segbase = 0;
2512 di->u.ti.table_len = ((char *) etab - (char *) ktab) / sizeof (unw_word_t);
2513 di->u.ti.table_data = (unw_word_t *) ktab;
2514
2515 if (gdbarch_debug >= 1)
2516 fprintf_unfiltered (gdb_stdlog, "get_kernel_table: found table `%s': "
78ced177
JJ		 2517 "segbase=0x%s, length=%s, gp=0x%s\n",
2518 (char *) di->u.ti.name_ptr,
2519 paddr_nz (di->u.ti.segbase),
2520 paddr_u (di->u.ti.table_len),
2521 paddr_nz (di->gp));
968d1cb4
JJ		 2522 return 0;
2523}
2524
2525/* Find the unwind table entry for a specified address. */
2526static int
2527ia64_find_unwind_table (struct objfile *objfile, unw_word_t ip,
2528 unw_dyn_info_t *dip, void **buf)
2529{
2530 Elf_Internal_Phdr *phdr, *p_text = NULL, *p_unwind = NULL;
2531 Elf_Internal_Ehdr *ehdr;
2532 unw_word_t segbase = 0;
2533 CORE_ADDR load_base;
2534 bfd *bfd;
2535 int i;
2536
2537 bfd = objfile->obfd;
2538
2539 ehdr = elf_tdata (bfd)->elf_header;
2540 phdr = elf_tdata (bfd)->phdr;
2541
2542 load_base = ANOFFSET (objfile->section_offsets, SECT_OFF_TEXT (objfile));
2543
2544 for (i = 0; i < ehdr->e_phnum; ++i)
2545 {
2546 switch (phdr[i].p_type)
2547 {
2548 case PT_LOAD:
2549 if ((unw_word_t) (ip - load_base - phdr[i].p_vaddr)
2550 < phdr[i].p_memsz)
2551 p_text = phdr + i;
2552 break;
2553
2554 case PT_IA_64_UNWIND:
2555 p_unwind = phdr + i;
2556 break;
2557
2558 default:
2559 break;
2560 }
2561 }
2562
c5a27d9c 2563 if (!p_text || !p_unwind)
968d1cb4
JJ		 2564 return -UNW_ENOINFO;
2565
c5a27d9c
JJ		 2566 /* Verify that the segment that contains the IP also contains
2567 the static unwind table. If not, we may be in the Linux kernel's
2568 DSO gate page in which case the unwind table is another segment.
2569 Otherwise, we are dealing with runtime-generated code, for which we
2570 have no info here. */
968d1cb4
JJ		 2571 segbase = p_text->p_vaddr + load_base;
2572
c5a27d9c
JJ		 2573 if ((p_unwind->p_vaddr - p_text->p_vaddr) >= p_text->p_memsz)
2574 {
2575 int ok = 0;
2576 for (i = 0; i < ehdr->e_phnum; ++i)
2577 {
2578 if (phdr[i].p_type == PT_LOAD
2579 && (p_unwind->p_vaddr - phdr[i].p_vaddr) < phdr[i].p_memsz)
2580 {
2581 ok = 1;
2582 /* Get the segbase from the section containing the
2583 libunwind table. */
2584 segbase = phdr[i].p_vaddr + load_base;
2585 }
2586 }
2587 if (!ok)
2588 return -UNW_ENOINFO;
2589 }
2590
2591 dip->start_ip = p_text->p_vaddr + load_base;
968d1cb4 2592 dip->end_ip = dip->start_ip + p_text->p_memsz;
b33e8514 2593 dip->gp = ia64_find_global_pointer (ip);
503ff15d
KB		 2594 dip->format = UNW_INFO_FORMAT_REMOTE_TABLE;
2595 dip->u.rti.name_ptr = (unw_word_t) bfd_get_filename (bfd);
2596 dip->u.rti.segbase = segbase;
2597 dip->u.rti.table_len = p_unwind->p_memsz / sizeof (unw_word_t);
2598 dip->u.rti.table_data = p_unwind->p_vaddr + load_base;
968d1cb4
JJ		 2599
2600 return 0;
2601}
2602
2603/* Libunwind callback accessor function to acquire procedure unwind-info. */
2604static int
2605ia64_find_proc_info_x (unw_addr_space_t as, unw_word_t ip, unw_proc_info_t *pi,
2606 int need_unwind_info, void *arg)
2607{
2608 struct obj_section *sec = find_pc_section (ip);
2609 unw_dyn_info_t di;
2610 int ret;
2611 void *buf = NULL;
2612
2613 if (!sec)
2614 {
2615 /* XXX This only works if the host and the target architecture are
2616 both ia64 and if the have (more or less) the same kernel
2617 version. */
2618 if (get_kernel_table (ip, &di) < 0)
2619 return -UNW_ENOINFO;
503ff15d
KB		 2620
2621 if (gdbarch_debug >= 1)
78ced177
JJ		 2622 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2623 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2624 "length=%s,data=0x%s)\n",
2625 paddr_nz (ip), (char *)di.u.ti.name_ptr,
2626 paddr_nz (di.u.ti.segbase),
2627 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2628 paddr_nz (di.gp),
2629 paddr_u (di.u.ti.table_len),
2630 paddr_nz ((CORE_ADDR)di.u.ti.table_data));
968d1cb4
JJ		 2631 }
2632 else
2633 {
2634 ret = ia64_find_unwind_table (sec->objfile, ip, &di, &buf);
2635 if (ret < 0)
2636 return ret;
968d1cb4 2637
503ff15d 2638 if (gdbarch_debug >= 1)
78ced177
JJ		 2639 fprintf_unfiltered (gdb_stdlog, "ia64_find_proc_info_x: 0x%s -> "
2640 "(name=`%s',segbase=0x%s,start=0x%s,end=0x%s,gp=0x%s,"
2641 "length=%s,data=0x%s)\n",
2642 paddr_nz (ip), (char *)di.u.rti.name_ptr,
2643 paddr_nz (di.u.rti.segbase),
2644 paddr_nz (di.start_ip), paddr_nz (di.end_ip),
2645 paddr_nz (di.gp),
2646 paddr_u (di.u.rti.table_len),
2647 paddr_nz (di.u.rti.table_data));
503ff15d 2648 }
968d1cb4 2649
503ff15d
KB		 2650 ret = libunwind_search_unwind_table (&as, ip, &di, pi, need_unwind_info,
2651 arg);
968d1cb4
JJ		 2652
2653 /* We no longer need the dyn info storage so free it. */
2654 xfree (buf);
2655
2656 return ret;
2657}
2658
2659/* Libunwind callback accessor function for cleanup. */
2660static void
2661ia64_put_unwind_info (unw_addr_space_t as,
2662 unw_proc_info_t *pip, void *arg)
2663{
2664 /* Nothing required for now. */
2665}
2666
2667/* Libunwind callback accessor function to get head of the dynamic
2668 unwind-info registration list. */
2669static int
2670ia64_get_dyn_info_list (unw_addr_space_t as,
2671 unw_word_t *dilap, void *arg)
2672{
2673 struct obj_section *text_sec;
2674 struct objfile *objfile;
2675 unw_word_t ip, addr;
2676 unw_dyn_info_t di;
2677 int ret;
2678
2679 if (!libunwind_is_initialized ())
2680 return -UNW_ENOINFO;
2681
2682 for (objfile = object_files; objfile; objfile = objfile->next)
2683 {
2684 void *buf = NULL;
2685
2686 text_sec = objfile->sections + SECT_OFF_TEXT (objfile);
2687 ip = text_sec->addr;
2688 ret = ia64_find_unwind_table (objfile, ip, &di, &buf);
2689 if (ret >= 0)
2690 {
503ff15d 2691 addr = libunwind_find_dyn_list (as, &di, arg);
968d1cb4
JJ		 2692 /* We no longer need the dyn info storage so free it. */
2693 xfree (buf);
2694
2695 if (addr)
2696 {
2697 if (gdbarch_debug >= 1)
2698 fprintf_unfiltered (gdb_stdlog,
2699 "dynamic unwind table in objfile %s "
78ced177 2700 "at 0x%s (gp=0x%s)\n",
968d1cb4 2701 bfd_get_filename (objfile->obfd),
78ced177 2702 paddr_nz (addr), paddr_nz (di.gp));
968d1cb4
JJ		 2703 *dilap = addr;
2704 return 0;
2705 }
2706 }
2707 }
2708 return -UNW_ENOINFO;
2709}
2710
2711
2712/* Frame interface functions for libunwind. */
2713
2714static void
2715ia64_libunwind_frame_this_id (struct frame_info *next_frame, void **this_cache,
7166c4a9 2716 struct frame_id *this_id)
968d1cb4
JJ		 2717{
2718 char buf[8];
2719 CORE_ADDR bsp;
2720 struct frame_id id;
c5a27d9c
JJ		 2721 CORE_ADDR prev_ip, addr;
2722 int realnum, optimized;
2723 enum lval_type lval;
2724
968d1cb4
JJ		 2725
2726 libunwind_frame_this_id (next_frame, this_cache, &id);
c5a27d9c
JJ		 2727 if (frame_id_eq (id, null_frame_id))
2728 {
2729 (*this_id) = null_frame_id;
2730 return;
2731 }
968d1cb4 2732
c5a27d9c
JJ		 2733 /* We must add the bsp as the special address for frame comparison
2734 purposes. */
968d1cb4
JJ		 2735 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2736 bsp = extract_unsigned_integer (buf, 8);
2737
c5a27d9c
JJ		 2738 /* If the previous frame pc value is 0, then we are at the end of the stack
2739 and don't want to unwind past this frame. We return a null frame_id to
2740 indicate this. */
2741 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
f1b4b38e
AS		 2742 &optimized, &lval, &addr, &realnum, buf);
2743 prev_ip = extract_unsigned_integer (buf, 8);
c5a27d9c
JJ		 2744
2745 if (prev_ip != 0)
2746 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2747 else
2748 (*this_id) = null_frame_id;
968d1cb4
JJ		 2749
2750 if (gdbarch_debug >= 1)
2751 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 2752 "libunwind frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2753 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2754 paddr_nz (bsp), next_frame);
968d1cb4
JJ		 2755}
2756
2757static void
2758ia64_libunwind_frame_prev_register (struct frame_info *next_frame,
2759 void **this_cache,
2760 int regnum, int *optimizedp,
2761 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2762 int *realnump, gdb_byte *valuep)
968d1cb4
JJ		 2763{
2764 int reg = regnum;
2765
2766 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2767 reg = IA64_PR_REGNUM;
2768 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2769 reg = IA64_UNAT_REGNUM;
2770
2771 /* Let libunwind do most of the work. */
2772 libunwind_frame_prev_register (next_frame, this_cache, reg,
2773 optimizedp, lvalp, addrp, realnump, valuep);
2774
6672f2ae
AS		 2775 /* No more to do if the value is not supposed to be supplied. */
2776 if (!valuep)
2777 return;
2778
968d1cb4
JJ		 2779 if (VP0_REGNUM <= regnum && regnum <= VP63_REGNUM)
2780 {
2781 ULONGEST prN_val;
2782
2783 if (VP16_REGNUM <= regnum && regnum <= VP63_REGNUM)
2784 {
2785 int rrb_pr = 0;
2786 ULONGEST cfm;
2787 unsigned char buf[MAX_REGISTER_SIZE];
2788
2789 /* Fetch predicate register rename base from current frame
2790 marker for this frame. */
2791 frame_unwind_register (next_frame, IA64_CFM_REGNUM, buf);
2792 cfm = extract_unsigned_integer (buf, 8);
2793 rrb_pr = (cfm >> 32) & 0x3f;
2794
2795 /* Adjust the register number to account for register rotation. */
2796 regnum = VP16_REGNUM
2797 + ((regnum - VP16_REGNUM) + rrb_pr) % 48;
2798 }
2799 prN_val = extract_bit_field ((unsigned char *) valuep,
2800 regnum - VP0_REGNUM, 1);
2801 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum), prN_val);
2802 }
2803 else if (IA64_NAT0_REGNUM <= regnum && regnum <= IA64_NAT127_REGNUM)
2804 {
2805 ULONGEST unatN_val;
2806
2807 unatN_val = extract_bit_field ((unsigned char *) valuep,
2808 regnum - IA64_NAT0_REGNUM, 1);
2809 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2810 unatN_val);
2811 }
2812 else if (regnum == IA64_BSP_REGNUM)
2813 {
2814 char cfm_valuep[MAX_REGISTER_SIZE];
2815 int cfm_optim;
2816 int cfm_realnum;
2817 enum lval_type cfm_lval;
2818 CORE_ADDR cfm_addr;
2819 CORE_ADDR bsp, prev_cfm, prev_bsp;
2820
2821 /* We want to calculate the previous bsp as the end of the previous register stack frame.
2822 This corresponds to what the hardware bsp register will be if we pop the frame
2823 back which is why we might have been called. We know that libunwind will pass us back
2824 the beginning of the current frame so we should just add sof to it. */
2825 prev_bsp = extract_unsigned_integer (valuep, 8);
2826 libunwind_frame_prev_register (next_frame, this_cache, IA64_CFM_REGNUM,
2827 &cfm_optim, &cfm_lval, &cfm_addr, &cfm_realnum, cfm_valuep);
2828 prev_cfm = extract_unsigned_integer (cfm_valuep, 8);
2829 prev_bsp = rse_address_add (prev_bsp, (prev_cfm & 0x7f));
2830
2831 store_unsigned_integer (valuep, register_size (current_gdbarch, regnum),
2832 prev_bsp);
2833 }
2834
2835 if (gdbarch_debug >= 1)
2836 fprintf_unfiltered (gdb_stdlog,
78ced177 2837 "libunwind prev register <%s> is 0x%s\n",
c5a27d9c
JJ		 2838 (regnum < IA64_GR32_REGNUM
2839 || (regnum > IA64_GR127_REGNUM
2840 && regnum < LAST_PSEUDO_REGNUM))
2841 ? ia64_register_names[regnum]
2842 : (regnum < LAST_PSEUDO_REGNUM
2843 ? ia64_register_names[regnum-IA64_GR32_REGNUM+V32_REGNUM]
2844 : "OUT_OF_RANGE"),
78ced177 2845 paddr_nz (extract_unsigned_integer (valuep, 8)));
968d1cb4
JJ		 2846}
2847
2848static const struct frame_unwind ia64_libunwind_frame_unwind =
2849{
2850 NORMAL_FRAME,
2851 ia64_libunwind_frame_this_id,
2852 ia64_libunwind_frame_prev_register
2853};
2854
2855static const struct frame_unwind *
2856ia64_libunwind_frame_sniffer (struct frame_info *next_frame)
2857{
2858 if (libunwind_is_initialized () && libunwind_frame_sniffer (next_frame))
2859 return &ia64_libunwind_frame_unwind;
2860
2861 return NULL;
2862}
2863
c5a27d9c
JJ		 2864static void
2865ia64_libunwind_sigtramp_frame_this_id (struct frame_info *next_frame, void **this_cache,
2866 struct frame_id *this_id)
2867{
2868 char buf[8];
2869 CORE_ADDR bsp;
2870 struct frame_id id;
2871 CORE_ADDR prev_ip;
2872
2873 libunwind_frame_this_id (next_frame, this_cache, &id);
2874 if (frame_id_eq (id, null_frame_id))
2875 {
2876 (*this_id) = null_frame_id;
2877 return;
2878 }
2879
2880 /* We must add the bsp as the special address for frame comparison
2881 purposes. */
2882 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
2883 bsp = extract_unsigned_integer (buf, 8);
2884
2885 /* For a sigtramp frame, we don't make the check for previous ip being 0. */
2886 (*this_id) = frame_id_build_special (id.stack_addr, id.code_addr, bsp);
2887
2888 if (gdbarch_debug >= 1)
2889 fprintf_unfiltered (gdb_stdlog,
2890 "libunwind sigtramp frame id: code 0x%s, stack 0x%s, special 0x%s, next_frame %p\n",
2891 paddr_nz (id.code_addr), paddr_nz (id.stack_addr),
2892 paddr_nz (bsp), next_frame);
2893}
2894
2895static void
2896ia64_libunwind_sigtramp_frame_prev_register (struct frame_info *next_frame,
2897 void **this_cache,
2898 int regnum, int *optimizedp,
2899 enum lval_type *lvalp, CORE_ADDR *addrp,
88d82102 2900 int *realnump, gdb_byte *valuep)
c5a27d9c
JJ		 2901
2902{
f1b4b38e 2903 gdb_byte buf[8];
c5a27d9c
JJ		 2904 CORE_ADDR prev_ip, addr;
2905 int realnum, optimized;
2906 enum lval_type lval;
2907
2908
2909 /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
2910 method of getting previous registers. */
2911 libunwind_frame_prev_register (next_frame, this_cache, IA64_IP_REGNUM,
f1b4b38e
AS		 2912 &optimized, &lval, &addr, &realnum, buf);
2913 prev_ip = extract_unsigned_integer (buf, 8);
c5a27d9c
JJ		 2914
2915 if (prev_ip == 0)
2916 {
2917 void *tmp_cache = NULL;
2918 ia64_sigtramp_frame_prev_register (next_frame, &tmp_cache, regnum, optimizedp, lvalp,
2919 addrp, realnump, valuep);
2920 }
2921 else
2922 ia64_libunwind_frame_prev_register (next_frame, this_cache, regnum, optimizedp, lvalp,
2923 addrp, realnump, valuep);
2924}
2925
2926static const struct frame_unwind ia64_libunwind_sigtramp_frame_unwind =
2927{
2928 SIGTRAMP_FRAME,
2929 ia64_libunwind_sigtramp_frame_this_id,
2930 ia64_libunwind_sigtramp_frame_prev_register
2931};
2932
2933static const struct frame_unwind *
2934ia64_libunwind_sigtramp_frame_sniffer (struct frame_info *next_frame)
2935{
2936 if (libunwind_is_initialized ())
2937 {
2938 if (libunwind_sigtramp_frame_sniffer (next_frame))
2939 return &ia64_libunwind_sigtramp_frame_unwind;
2940 return NULL;
2941 }
2942 else
2943 return ia64_sigtramp_frame_sniffer (next_frame);
2944}
2945
968d1cb4
JJ		 2946/* Set of libunwind callback acccessor functions. */
2947static unw_accessors_t ia64_unw_accessors =
2948{
2949 ia64_find_proc_info_x,
2950 ia64_put_unwind_info,
2951 ia64_get_dyn_info_list,
2952 ia64_access_mem,
2953 ia64_access_reg,
2954 ia64_access_fpreg,
2955 /* resume */
2956 /* get_proc_name */
2957};
2958
c5a27d9c
JJ		 2959/* Set of special libunwind callback acccessor functions specific for accessing
2960 the rse registers. At the top of the stack, we want libunwind to figure out
2961 how to read r32 - r127. Though usually they are found sequentially in memory
2962 starting from $bof, this is not always true. */
2963static unw_accessors_t ia64_unw_rse_accessors =
2964{
2965 ia64_find_proc_info_x,
2966 ia64_put_unwind_info,
2967 ia64_get_dyn_info_list,
2968 ia64_access_mem,
2969 ia64_access_rse_reg,
2970 ia64_access_fpreg,
2971 /* resume */
2972 /* get_proc_name */
2973};
2974
968d1cb4
JJ		 2975/* Set of ia64 gdb libunwind-frame callbacks and data for generic libunwind-frame code to use. */
2976static struct libunwind_descr ia64_libunwind_descr =
2977{
2978 ia64_gdb2uw_regnum,
2979 ia64_uw2gdb_regnum,
2980 ia64_is_fpreg,
2981 &ia64_unw_accessors,
c5a27d9c 2982 &ia64_unw_rse_accessors,
968d1cb4
JJ		 2983};
2984
2985#endif /* HAVE_LIBUNWIND_IA64_H */
2986
74055713
AC		 2987/* Should we use DEPRECATED_EXTRACT_STRUCT_VALUE_ADDRESS instead of
2988 EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc and TYPE
2989 is the type (which is known to be struct, union or array). */
16461d7d
KB		 2990int
2991ia64_use_struct_convention (int gcc_p, struct type *type)
2992{
64a5b29c
KB		 2993 struct type *float_elt_type;
2994
2995 /* HFAs are structures (or arrays) consisting entirely of floating
2996 point values of the same length. Up to 8 of these are returned
2997 in registers. Don't use the struct convention when this is the
004d836a 2998 case. */
64a5b29c
KB		 2999 float_elt_type = is_float_or_hfa_type (type);
3000 if (float_elt_type != NULL
3001 && TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type) <= 8)
3002 return 0;
3003
3004 /* Other structs of length 32 or less are returned in r8-r11.
004d836a 3005 Don't use the struct convention for those either. */
16461d7d
KB		 3006 return TYPE_LENGTH (type) > 32;
3007}
3008
3009void
2d522557
AC		 3010ia64_extract_return_value (struct type *type, struct regcache *regcache,
3011 gdb_byte *valbuf)
16461d7d 3012{
64a5b29c
KB		 3013 struct type *float_elt_type;
3014
3015 float_elt_type = is_float_or_hfa_type (type);
3016 if (float_elt_type != NULL)
3017 {
004d836a 3018 char from[MAX_REGISTER_SIZE];
64a5b29c
KB		 3019 int offset = 0;
3020 int regnum = IA64_FR8_REGNUM;
3021 int n = TYPE_LENGTH (type) / TYPE_LENGTH (float_elt_type);
3022
3023 while (n-- > 0)
3024 {
004d836a
JJ		 3025 regcache_cooked_read (regcache, regnum, from);
3026 convert_typed_floating (from, builtin_type_ia64_ext,
3027 (char *)valbuf + offset, float_elt_type);
64a5b29c
KB		 3028 offset += TYPE_LENGTH (float_elt_type);
3029 regnum++;
3030 }
3031 }
16461d7d 3032 else
004d836a
JJ		 3033 {
3034 ULONGEST val;
3035 int offset = 0;
3036 int regnum = IA64_GR8_REGNUM;
3037 int reglen = TYPE_LENGTH (ia64_register_type (NULL, IA64_GR8_REGNUM));
3038 int n = TYPE_LENGTH (type) / reglen;
3039 int m = TYPE_LENGTH (type) % reglen;
16461d7d 3040
004d836a
JJ		 3041 while (n-- > 0)
3042 {
3043 ULONGEST val;
3044 regcache_cooked_read_unsigned (regcache, regnum, &val);
3045 memcpy ((char *)valbuf + offset, &val, reglen);
3046 offset += reglen;
3047 regnum++;
3048 }
16461d7d 3049
004d836a
JJ		 3050 if (m)
3051 {
3052 regcache_cooked_read_unsigned (regcache, regnum, &val);
3053 memcpy ((char *)valbuf + offset, &val, m);
3054 }
3055 }
16461d7d
KB		 3056}
3057
3058CORE_ADDR
004d836a 3059ia64_extract_struct_value_address (struct regcache *regcache)
16461d7d 3060{
8a3fe4f8 3061 error (_("ia64_extract_struct_value_address called and cannot get struct value address"));
004d836a 3062 return 0;
16461d7d
KB		 3063}
3064
16461d7d 3065
64a5b29c
KB		 3066static int
3067is_float_or_hfa_type_recurse (struct type *t, struct type **etp)
3068{
3069 switch (TYPE_CODE (t))
3070 {
3071 case TYPE_CODE_FLT:
3072 if (*etp)
3073 return TYPE_LENGTH (*etp) == TYPE_LENGTH (t);
3074 else
3075 {
3076 *etp = t;
3077 return 1;
3078 }
3079 break;
3080 case TYPE_CODE_ARRAY:
98f96ba1
KB		 3081 return
3082 is_float_or_hfa_type_recurse (check_typedef (TYPE_TARGET_TYPE (t)),
3083 etp);
64a5b29c
KB		 3084 break;
3085 case TYPE_CODE_STRUCT:
3086 {
3087 int i;
3088
3089 for (i = 0; i < TYPE_NFIELDS (t); i++)
98f96ba1
KB		 3090 if (!is_float_or_hfa_type_recurse
3091 (check_typedef (TYPE_FIELD_TYPE (t, i)), etp))
64a5b29c
KB		 3092 return 0;
3093 return 1;
3094 }
3095 break;
3096 default:
3097 return 0;
3098 break;
3099 }
3100}
3101
3102/* Determine if the given type is one of the floating point types or
3103 and HFA (which is a struct, array, or combination thereof whose
004d836a 3104 bottom-most elements are all of the same floating point type). */
64a5b29c
KB		 3105
3106static struct type *
3107is_float_or_hfa_type (struct type *t)
3108{
3109 struct type *et = 0;
3110
3111 return is_float_or_hfa_type_recurse (t, &et) ? et : 0;
3112}
3113
3114
98f96ba1
KB		 3115/* Return 1 if the alignment of T is such that the next even slot
3116 should be used. Return 0, if the next available slot should
3117 be used. (See section 8.5.1 of the IA-64 Software Conventions
004d836a 3118 and Runtime manual). */
98f96ba1
KB		 3119
3120static int
3121slot_alignment_is_next_even (struct type *t)
3122{
3123 switch (TYPE_CODE (t))
3124 {
3125 case TYPE_CODE_INT:
3126 case TYPE_CODE_FLT:
3127 if (TYPE_LENGTH (t) > 8)
3128 return 1;
3129 else
3130 return 0;
3131 case TYPE_CODE_ARRAY:
3132 return
3133 slot_alignment_is_next_even (check_typedef (TYPE_TARGET_TYPE (t)));
3134 case TYPE_CODE_STRUCT:
3135 {
3136 int i;
3137
3138 for (i = 0; i < TYPE_NFIELDS (t); i++)
3139 if (slot_alignment_is_next_even
3140 (check_typedef (TYPE_FIELD_TYPE (t, i))))
3141 return 1;
3142 return 0;
3143 }
3144 default:
3145 return 0;
3146 }
3147}
3148
64a5b29c
KB		 3149/* Attempt to find (and return) the global pointer for the given
3150 function.
3151
3152 This is a rather nasty bit of code searchs for the .dynamic section
3153 in the objfile corresponding to the pc of the function we're trying
3154 to call. Once it finds the addresses at which the .dynamic section
3155 lives in the child process, it scans the Elf64_Dyn entries for a
3156 DT_PLTGOT tag. If it finds one of these, the corresponding
3157 d_un.d_ptr value is the global pointer. */
3158
3159static CORE_ADDR
b33e8514 3160ia64_find_global_pointer (CORE_ADDR faddr)
64a5b29c 3161{
76d689a6 3162 struct obj_section *faddr_sect;
64a5b29c 3163
76d689a6
KB		 3164 faddr_sect = find_pc_section (faddr);
3165 if (faddr_sect != NULL)
64a5b29c
KB		 3166 {
3167 struct obj_section *osect;
3168
76d689a6 3169 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3170 {
3171 if (strcmp (osect->the_bfd_section->name, ".dynamic") == 0)
3172 break;
3173 }
3174
76d689a6 3175 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3176 {
3177 CORE_ADDR addr;
3178
3179 addr = osect->addr;
3180 while (addr < osect->endaddr)
3181 {
3182 int status;
3183 LONGEST tag;
3184 char buf[8];
3185
3186 status = target_read_memory (addr, buf, sizeof (buf));
3187 if (status != 0)
3188 break;
3189 tag = extract_signed_integer (buf, sizeof (buf));
3190
3191 if (tag == DT_PLTGOT)
3192 {
3193 CORE_ADDR global_pointer;
3194
3195 status = target_read_memory (addr + 8, buf, sizeof (buf));
3196 if (status != 0)
3197 break;
7c0b4a20 3198 global_pointer = extract_unsigned_integer (buf, sizeof (buf));
64a5b29c
KB		 3199
3200 /* The payoff... */
3201 return global_pointer;
3202 }
3203
3204 if (tag == DT_NULL)
3205 break;
3206
3207 addr += 16;
3208 }
3209 }
3210 }
3211 return 0;
3212}
3213
3214/* Given a function's address, attempt to find (and return) the
3215 corresponding (canonical) function descriptor. Return 0 if
004d836a 3216 not found. */
64a5b29c
KB		 3217static CORE_ADDR
3218find_extant_func_descr (CORE_ADDR faddr)
3219{
76d689a6 3220 struct obj_section *faddr_sect;
64a5b29c 3221
004d836a 3222 /* Return early if faddr is already a function descriptor. */
76d689a6
KB		 3223 faddr_sect = find_pc_section (faddr);
3224 if (faddr_sect && strcmp (faddr_sect->the_bfd_section->name, ".opd") == 0)
64a5b29c
KB		 3225 return faddr;
3226
76d689a6 3227 if (faddr_sect != NULL)
64a5b29c 3228 {
76d689a6
KB		 3229 struct obj_section *osect;
3230 ALL_OBJFILE_OSECTIONS (faddr_sect->objfile, osect)
64a5b29c
KB		 3231 {
3232 if (strcmp (osect->the_bfd_section->name, ".opd") == 0)
3233 break;
3234 }
3235
76d689a6 3236 if (osect < faddr_sect->objfile->sections_end)
64a5b29c
KB		 3237 {
3238 CORE_ADDR addr;
3239
3240 addr = osect->addr;
3241 while (addr < osect->endaddr)
3242 {
3243 int status;
3244 LONGEST faddr2;
3245 char buf[8];
3246
3247 status = target_read_memory (addr, buf, sizeof (buf));
3248 if (status != 0)
3249 break;
3250 faddr2 = extract_signed_integer (buf, sizeof (buf));
3251
3252 if (faddr == faddr2)
3253 return addr;
3254
3255 addr += 16;
3256 }
3257 }
3258 }
3259 return 0;
3260}
3261
3262/* Attempt to find a function descriptor corresponding to the
3263 given address. If none is found, construct one on the
004d836a 3264 stack using the address at fdaptr. */
64a5b29c
KB		 3265
3266static CORE_ADDR
3267find_func_descr (CORE_ADDR faddr, CORE_ADDR *fdaptr)
3268{
3269 CORE_ADDR fdesc;
3270
3271 fdesc = find_extant_func_descr (faddr);
3272
3273 if (fdesc == 0)
3274 {
3275 CORE_ADDR global_pointer;
3276 char buf[16];
3277
3278 fdesc = *fdaptr;
3279 *fdaptr += 16;
3280
b33e8514 3281 global_pointer = ia64_find_global_pointer (faddr);
64a5b29c
KB		 3282
3283 if (global_pointer == 0)
3284 global_pointer = read_register (IA64_GR1_REGNUM);
3285
fbd9dcd3
AC		 3286 store_unsigned_integer (buf, 8, faddr);
3287 store_unsigned_integer (buf + 8, 8, global_pointer);
64a5b29c
KB		 3288
3289 write_memory (fdesc, buf, 16);
3290 }
3291
3292 return fdesc;
3293}
16461d7d 3294
af8b88dd
JJ		 3295/* Use the following routine when printing out function pointers
3296 so the user can see the function address rather than just the
3297 function descriptor. */
3298static CORE_ADDR
e2d0e7eb
AC		 3299ia64_convert_from_func_ptr_addr (struct gdbarch *gdbarch, CORE_ADDR addr,
3300 struct target_ops *targ)
af8b88dd
JJ		 3301{
3302 struct obj_section *s;
3303
3304 s = find_pc_section (addr);
3305
3306 /* check if ADDR points to a function descriptor. */
3307 if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
3308 return read_memory_unsigned_integer (addr, 8);
3309
0d5de010
DJ		 3310 /* There are also descriptors embedded in vtables. */
3311 if (s)
3312 {
3313 struct minimal_symbol *minsym;
3314
3315 minsym = lookup_minimal_symbol_by_pc (addr);
3316
3317 if (minsym && is_vtable_name (SYMBOL_LINKAGE_NAME (minsym)))
3318 return read_memory_unsigned_integer (addr, 8);
3319 }
3320
af8b88dd
JJ		 3321 return addr;
3322}
3323
a78f21af 3324static CORE_ADDR
004d836a
JJ		 3325ia64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
3326{
3327 return sp & ~0xfLL;
3328}
3329
3330static CORE_ADDR
7d9b040b 3331ia64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
8dd5115e
AS		 3332 struct regcache *regcache, CORE_ADDR bp_addr,
3333 int nargs, struct value **args, CORE_ADDR sp,
3334 int struct_return, CORE_ADDR struct_addr)
16461d7d
KB		 3335{
3336 int argno;
ea7c478f 3337 struct value *arg;
16461d7d
KB		 3338 struct type *type;
3339 int len, argoffset;
64a5b29c 3340 int nslots, rseslots, memslots, slotnum, nfuncargs;
16461d7d 3341 int floatreg;
004d836a 3342 CORE_ADDR bsp, cfm, pfs, new_bsp, funcdescaddr, pc, global_pointer;
7d9b040b 3343 CORE_ADDR func_addr = find_function_addr (function, NULL);
16461d7d
KB		 3344
3345 nslots = 0;
64a5b29c 3346 nfuncargs = 0;
004d836a 3347 /* Count the number of slots needed for the arguments. */
16461d7d
KB		 3348 for (argno = 0; argno < nargs; argno++)
3349 {
3350 arg = args[argno];
4991999e 3351 type = check_typedef (value_type (arg));
16461d7d
KB		 3352 len = TYPE_LENGTH (type);
3353
98f96ba1 3354 if ((nslots & 1) && slot_alignment_is_next_even (type))
16461d7d
KB		 3355 nslots++;
3356
64a5b29c
KB		 3357 if (TYPE_CODE (type) == TYPE_CODE_FUNC)
3358 nfuncargs++;
3359
16461d7d
KB		 3360 nslots += (len + 7) / 8;
3361 }
3362
004d836a 3363 /* Divvy up the slots between the RSE and the memory stack. */
16461d7d
KB		 3364 rseslots = (nslots > 8) ? 8 : nslots;
3365 memslots = nslots - rseslots;
3366
004d836a
JJ		 3367 /* Allocate a new RSE frame. */
3368 cfm = read_register (IA64_CFM_REGNUM);
16461d7d 3369
004d836a 3370 bsp = read_register (IA64_BSP_REGNUM);
16461d7d 3371 new_bsp = rse_address_add (bsp, rseslots);
004d836a 3372 write_register (IA64_BSP_REGNUM, new_bsp);
16461d7d 3373
004d836a 3374 pfs = read_register (IA64_PFS_REGNUM);
16461d7d
KB		 3375 pfs &= 0xc000000000000000LL;
3376 pfs |= (cfm & 0xffffffffffffLL);
004d836a 3377 write_register (IA64_PFS_REGNUM, pfs);
16461d7d
KB		 3378
3379 cfm &= 0xc000000000000000LL;
3380 cfm |= rseslots;
004d836a 3381 write_register (IA64_CFM_REGNUM, cfm);
16461d7d 3382
64a5b29c
KB		 3383 /* We will attempt to find function descriptors in the .opd segment,
3384 but if we can't we'll construct them ourselves. That being the
004d836a 3385 case, we'll need to reserve space on the stack for them. */
64a5b29c
KB		 3386 funcdescaddr = sp - nfuncargs * 16;
3387 funcdescaddr &= ~0xfLL;
3388
3389 /* Adjust the stack pointer to it's new value. The calling conventions
3390 require us to have 16 bytes of scratch, plus whatever space is
004d836a 3391 necessary for the memory slots and our function descriptors. */
64a5b29c 3392 sp = sp - 16 - (memslots + nfuncargs) * 8;
004d836a 3393 sp &= ~0xfLL; /* Maintain 16 byte alignment. */
16461d7d 3394
64a5b29c
KB		 3395 /* Place the arguments where they belong. The arguments will be
3396 either placed in the RSE backing store or on the memory stack.
3397 In addition, floating point arguments or HFAs are placed in
004d836a 3398 floating point registers. */
16461d7d
KB		 3399 slotnum = 0;
3400 floatreg = IA64_FR8_REGNUM;
3401 for (argno = 0; argno < nargs; argno++)
3402 {
64a5b29c
KB		 3403 struct type *float_elt_type;
3404
16461d7d 3405 arg = args[argno];
4991999e 3406 type = check_typedef (value_type (arg));
16461d7d 3407 len = TYPE_LENGTH (type);
64a5b29c 3408
004d836a 3409 /* Special handling for function parameters. */
64a5b29c
KB		 3410 if (len == 8
3411 && TYPE_CODE (type) == TYPE_CODE_PTR
3412 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
3413 {
3414 char val_buf[8];
3415
fbd9dcd3 3416 store_unsigned_integer (val_buf, 8,
0fd88904 3417 find_func_descr (extract_unsigned_integer (value_contents (arg), 8),
fbd9dcd3 3418 &funcdescaddr));
64a5b29c
KB		 3419 if (slotnum < rseslots)
3420 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3421 else
3422 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3423 slotnum++;
3424 continue;
3425 }
3426
004d836a 3427 /* Normal slots. */
98f96ba1
KB		 3428
3429 /* Skip odd slot if necessary... */
3430 if ((slotnum & 1) && slot_alignment_is_next_even (type))
16461d7d 3431 slotnum++;
98f96ba1 3432
16461d7d
KB		 3433 argoffset = 0;
3434 while (len > 0)
3435 {
3436 char val_buf[8];
3437
3438 memset (val_buf, 0, 8);
0fd88904 3439 memcpy (val_buf, value_contents (arg) + argoffset, (len > 8) ? 8 : len);
16461d7d
KB		 3440
3441 if (slotnum < rseslots)
3442 write_memory (rse_address_add (bsp, slotnum), val_buf, 8);
3443 else
3444 write_memory (sp + 16 + 8 * (slotnum - rseslots), val_buf, 8);
3445
3446 argoffset += 8;
3447 len -= 8;
3448 slotnum++;
3449 }
64a5b29c 3450
004d836a 3451 /* Handle floating point types (including HFAs). */
64a5b29c
KB		 3452 float_elt_type = is_float_or_hfa_type (type);
3453 if (float_elt_type != NULL)
3454 {
3455 argoffset = 0;
3456 len = TYPE_LENGTH (type);
3457 while (len > 0 && floatreg < IA64_FR16_REGNUM)
3458 {
004d836a 3459 char to[MAX_REGISTER_SIZE];
0fd88904 3460 convert_typed_floating (value_contents (arg) + argoffset, float_elt_type,
004d836a
JJ		 3461 to, builtin_type_ia64_ext);
3462 regcache_cooked_write (regcache, floatreg, (void *)to);
64a5b29c
KB		 3463 floatreg++;
3464 argoffset += TYPE_LENGTH (float_elt_type);
3465 len -= TYPE_LENGTH (float_elt_type);
3466 }
16461d7d
KB		 3467 }
3468 }
3469
004d836a 3470 /* Store the struct return value in r8 if necessary. */
16461d7d
KB		 3471 if (struct_return)
3472 {
004d836a 3473 regcache_cooked_write_unsigned (regcache, IA64_GR8_REGNUM, (ULONGEST)struct_addr);
16461d7d
KB		 3474 }
3475
b33e8514 3476 global_pointer = ia64_find_global_pointer (func_addr);
8dd5115e 3477
004d836a
JJ		 3478 if (global_pointer != 0)
3479 write_register (IA64_GR1_REGNUM, global_pointer);
a59fe496 3480
004d836a 3481 write_register (IA64_BR0_REGNUM, bp_addr);
16461d7d 3482
004d836a 3483 write_register (sp_regnum, sp);
16461d7d
KB		 3484
3485 return sp;
3486}
3487
004d836a
JJ		 3488static struct frame_id
3489ia64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3490{
004d836a 3491 char buf[8];
4afcc598 3492 CORE_ADDR sp, bsp;
004d836a
JJ		 3493
3494 frame_unwind_register (next_frame, sp_regnum, buf);
3495 sp = extract_unsigned_integer (buf, 8);
3496
4afcc598
JJ		 3497 frame_unwind_register (next_frame, IA64_BSP_REGNUM, buf);
3498 bsp = extract_unsigned_integer (buf, 8);
3499
3500 if (gdbarch_debug >= 1)
3501 fprintf_unfiltered (gdb_stdlog,
78ced177
JJ		 3502 "dummy frame id: code 0x%s, stack 0x%s, special 0x%s\n",
3503 paddr_nz (frame_pc_unwind (next_frame)),
3504 paddr_nz (sp), paddr_nz (bsp));
4afcc598
JJ		 3505
3506 return frame_id_build_special (sp, frame_pc_unwind (next_frame), bsp);
16461d7d
KB		 3507}
3508
004d836a
JJ		 3509static CORE_ADDR
3510ia64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
16461d7d 3511{
004d836a
JJ		 3512 char buf[8];
3513 CORE_ADDR ip, psr, pc;
3514
3515 frame_unwind_register (next_frame, IA64_IP_REGNUM, buf);
3516 ip = extract_unsigned_integer (buf, 8);
3517 frame_unwind_register (next_frame, IA64_PSR_REGNUM, buf);
3518 psr = extract_unsigned_integer (buf, 8);
3519
3520 pc = (ip & ~0xf) | ((psr >> 41) & 3);
3521 return pc;
16461d7d
KB		 3522}
3523
3524static void
88d82102
JJ		 3525ia64_store_return_value (struct type *type, struct regcache *regcache,
3526 const gdb_byte *valbuf)
16461d7d 3527{
004d836a 3528 if (TYPE_CODE (type) == TYPE_CODE_FLT)
16461d7d 3529 {
004d836a
JJ		 3530 char to[MAX_REGISTER_SIZE];
3531 convert_typed_floating (valbuf, type, to, builtin_type_ia64_ext);
3532 regcache_cooked_write (regcache, IA64_FR8_REGNUM, (void *)to);
3533 target_store_registers (IA64_FR8_REGNUM);
16461d7d
KB		 3534 }
3535 else
004d836a 3536 regcache_cooked_write (regcache, IA64_GR8_REGNUM, valbuf);
16461d7d
KB		 3537}
3538
3539static void
1750fa04
AC		 3540ia64_remote_translate_xfer_address (struct gdbarch *gdbarch,
3541 struct regcache *regcache,
3542 CORE_ADDR memaddr, int nr_bytes,
16461d7d
KB		 3543 CORE_ADDR *targ_addr, int *targ_len)
3544{
3545 *targ_addr = memaddr;
3546 *targ_len = nr_bytes;
3547}
3548
6926787d
AS		 3549static int
3550ia64_print_insn (bfd_vma memaddr, struct disassemble_info *info)
3551{
3552 info->bytes_per_line = SLOT_MULTIPLIER;
3553 return print_insn_ia64 (memaddr, info);
3554}
3555
16461d7d
KB		 3556static struct gdbarch *
3557ia64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3558{
3559 struct gdbarch *gdbarch;
244bc108 3560 struct gdbarch_tdep *tdep;
244bc108 3561
85bf2b91
JJ		 3562 /* If there is already a candidate, use it. */
3563 arches = gdbarch_list_lookup_by_info (arches, &info);
3564 if (arches != NULL)
3565 return arches->gdbarch;
16461d7d 3566
244bc108
KB		 3567 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3568 gdbarch = gdbarch_alloc (&info, tdep);
244bc108 3569
b33e8514 3570 tdep->sigcontext_register_address = 0;
698cb3f0 3571
004d836a
JJ		 3572 /* Define the ia64 floating-point format to gdb. */
3573 builtin_type_ia64_ext =
3574 init_type (TYPE_CODE_FLT, 128 / 8,
3575 0, "builtin_type_ia64_ext", NULL);
3576 TYPE_FLOATFORMAT (builtin_type_ia64_ext) = &floatformat_ia64_ext;
3577
5439edaa
AC		 3578 /* According to the ia64 specs, instructions that store long double
3579 floats in memory use a long-double format different than that
3580 used in the floating registers. The memory format matches the
3581 x86 extended float format which is 80 bits. An OS may choose to
3582 use this format (e.g. GNU/Linux) or choose to use a different
3583 format for storing long doubles (e.g. HPUX). In the latter case,
3584 the setting of the format may be moved/overridden in an
3585 OS-specific tdep file. */
32edc941
JJ		 3586 set_gdbarch_long_double_format (gdbarch, &floatformat_i387_ext);
3587
16461d7d
KB		 3588 set_gdbarch_short_bit (gdbarch, 16);
3589 set_gdbarch_int_bit (gdbarch, 32);
3590 set_gdbarch_long_bit (gdbarch, 64);
3591 set_gdbarch_long_long_bit (gdbarch, 64);
3592 set_gdbarch_float_bit (gdbarch, 32);
3593 set_gdbarch_double_bit (gdbarch, 64);
33c08150 3594 set_gdbarch_long_double_bit (gdbarch, 128);
16461d7d
KB		 3595 set_gdbarch_ptr_bit (gdbarch, 64);
3596
004d836a
JJ		 3597 set_gdbarch_num_regs (gdbarch, NUM_IA64_RAW_REGS);
3598 set_gdbarch_num_pseudo_regs (gdbarch, LAST_PSEUDO_REGNUM - FIRST_PSEUDO_REGNUM);
16461d7d 3599 set_gdbarch_sp_regnum (gdbarch, sp_regnum);
698cb3f0 3600 set_gdbarch_fp0_regnum (gdbarch, IA64_FR0_REGNUM);
16461d7d
KB		 3601
3602 set_gdbarch_register_name (gdbarch, ia64_register_name);
004d836a
JJ		 3603 /* FIXME: Following interface should not be needed, however, without it recurse.exp
3604 gets a number of extra failures. */
b1e29e33 3605 set_gdbarch_deprecated_register_size (gdbarch, 8);
004d836a 3606 set_gdbarch_register_type (gdbarch, ia64_register_type);
16461d7d 3607
004d836a
JJ		 3608 set_gdbarch_pseudo_register_read (gdbarch, ia64_pseudo_register_read);
3609 set_gdbarch_pseudo_register_write (gdbarch, ia64_pseudo_register_write);
3610 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, ia64_dwarf_reg_to_regnum);
3611 set_gdbarch_register_reggroup_p (gdbarch, ia64_register_reggroup_p);
3612 set_gdbarch_convert_register_p (gdbarch, ia64_convert_register_p);
3613 set_gdbarch_register_to_value (gdbarch, ia64_register_to_value);
3614 set_gdbarch_value_to_register (gdbarch, ia64_value_to_register);
16461d7d 3615
004d836a 3616 set_gdbarch_skip_prologue (gdbarch, ia64_skip_prologue);
16461d7d 3617
b5622e8d 3618 set_gdbarch_deprecated_use_struct_convention (gdbarch, ia64_use_struct_convention);
004d836a 3619 set_gdbarch_extract_return_value (gdbarch, ia64_extract_return_value);
16461d7d 3620
004d836a 3621 set_gdbarch_store_return_value (gdbarch, ia64_store_return_value);
74055713 3622 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, ia64_extract_struct_value_address);
16461d7d
KB		 3623
3624 set_gdbarch_memory_insert_breakpoint (gdbarch, ia64_memory_insert_breakpoint);
3625 set_gdbarch_memory_remove_breakpoint (gdbarch, ia64_memory_remove_breakpoint);
3626 set_gdbarch_breakpoint_from_pc (gdbarch, ia64_breakpoint_from_pc);
3627 set_gdbarch_read_pc (gdbarch, ia64_read_pc);
b33e8514 3628 set_gdbarch_write_pc (gdbarch, ia64_write_pc);
16461d7d
KB		 3629
3630 /* Settings for calling functions in the inferior. */
8dd5115e 3631 set_gdbarch_push_dummy_call (gdbarch, ia64_push_dummy_call);
004d836a
JJ		 3632 set_gdbarch_frame_align (gdbarch, ia64_frame_align);
3633 set_gdbarch_unwind_dummy_id (gdbarch, ia64_unwind_dummy_id);
16461d7d 3634
004d836a 3635 set_gdbarch_unwind_pc (gdbarch, ia64_unwind_pc);
968d1cb4 3636#ifdef HAVE_LIBUNWIND_IA64_H
c5a27d9c 3637 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_sigtramp_frame_sniffer);
968d1cb4
JJ		 3638 frame_unwind_append_sniffer (gdbarch, ia64_libunwind_frame_sniffer);
3639 libunwind_frame_set_descr (gdbarch, &ia64_libunwind_descr);
c5a27d9c
JJ		 3640#else
3641 frame_unwind_append_sniffer (gdbarch, ia64_sigtramp_frame_sniffer);
968d1cb4 3642#endif
004d836a
JJ		 3643 frame_unwind_append_sniffer (gdbarch, ia64_frame_sniffer);
3644 frame_base_set_default (gdbarch, &ia64_frame_base);
16461d7d
KB		 3645
3646 /* Settings that should be unnecessary. */
3647 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3648
16461d7d
KB		 3649 set_gdbarch_remote_translate_xfer_address (
3650 gdbarch, ia64_remote_translate_xfer_address);
3651
6926787d 3652 set_gdbarch_print_insn (gdbarch, ia64_print_insn);
af8b88dd 3653 set_gdbarch_convert_from_func_ptr_addr (gdbarch, ia64_convert_from_func_ptr_addr);
6926787d 3654
0d5de010
DJ		 3655 /* The virtual table contains 16-byte descriptors, not pointers to
3656 descriptors. */
3657 set_gdbarch_vtable_function_descriptors (gdbarch, 1);
3658
b33e8514
AS		 3659 /* Hook in ABI-specific overrides, if they have been registered. */
3660 gdbarch_init_osabi (info, gdbarch);
3661
16461d7d
KB		 3662 return gdbarch;
3663}
3664
a78f21af
AC		 3665extern initialize_file_ftype _initialize_ia64_tdep; /* -Wmissing-prototypes */
3666
16461d7d
KB		 3667void
3668_initialize_ia64_tdep (void)
3669{
b33e8514 3670 gdbarch_register (bfd_arch_ia64, ia64_gdbarch_init, NULL);
16461d7d 3671}
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