[thirdparty/binutils-gdb.git] / gdb / lm32-tdep.c

/* Target-dependent code for Lattice Mico32 processor, for GDB.
   Contributed by Jon Beniston <jon@beniston.com>

   Copyright (C) 2009-2016 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#include "defs.h"
#include "frame.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "inferior.h"
#include "dis-asm.h"
#include "symfile.h"
#include "remote.h"
#include "gdbcore.h"
#include "gdb/sim-lm32.h"
#include "gdb/callback.h"
#include "gdb/remote-sim.h"
#include "sim-regno.h"
#include "arch-utils.h"
#include "regcache.h"
#include "trad-frame.h"
#include "reggroups.h"
#include "opcodes/lm32-desc.h"

/* Macros to extract fields from an instruction.  */
#define LM32_OPCODE(insn)       ((insn >> 26) & 0x3f)
#define LM32_REG0(insn)         ((insn >> 21) & 0x1f)
#define LM32_REG1(insn)         ((insn >> 16) & 0x1f)
#define LM32_REG2(insn)         ((insn >> 11) & 0x1f)
#define LM32_IMM16(insn)        ((((long)insn & 0xffff) << 16) >> 16)

struct gdbarch_tdep
{
  /* gdbarch target dependent data here.  Currently unused for LM32.  */
};

struct lm32_frame_cache
{
  /* The frame's base.  Used when constructing a frame ID.  */
  CORE_ADDR base;
  CORE_ADDR pc;
  /* Size of frame.  */
  int size;
  /* Table indicating the location of each and every register.  */
  struct trad_frame_saved_reg *saved_regs;
};

/* Add the available register groups.  */

static void
lm32_add_reggroups (struct gdbarch *gdbarch)
{
  reggroup_add (gdbarch, general_reggroup);
  reggroup_add (gdbarch, all_reggroup);
  reggroup_add (gdbarch, system_reggroup);
}

/* Return whether a given register is in a given group.  */

static int
lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
			  struct reggroup *group)
{
  if (group == general_reggroup)
    return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
      || (regnum == SIM_LM32_PC_REGNUM);
  else if (group == system_reggroup)
    return ((regnum >= SIM_LM32_EA_REGNUM) && (regnum <= SIM_LM32_BA_REGNUM))
      || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
  return default_register_reggroup_p (gdbarch, regnum, group);
}

/* Return a name that corresponds to the given register number.  */

static const char *
lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
{
  static char *register_names[] = {
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
    "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
    "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
    "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
    "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
  };

  if ((reg_nr < 0) || (reg_nr >= ARRAY_SIZE (register_names)))
    return NULL;
  else
    return register_names[reg_nr];
}

/* Return type of register.  */

static struct type *
lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
{
  return builtin_type (gdbarch)->builtin_int32;
}

/* Return non-zero if a register can't be written.  */

static int
lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
{
  return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
}

/* Analyze a function's prologue.  */

static CORE_ADDR
lm32_analyze_prologue (struct gdbarch *gdbarch,
		       CORE_ADDR pc, CORE_ADDR limit,
		       struct lm32_frame_cache *info)
{
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  unsigned long instruction;

  /* Keep reading though instructions, until we come across an instruction 
     that isn't likely to be part of the prologue.  */
  info->size = 0;
  for (; pc < limit; pc += 4)
    {

      /* Read an instruction.  */
      instruction = read_memory_integer (pc, 4, byte_order);

      if ((LM32_OPCODE (instruction) == OP_SW)
	  && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
	{
	  /* Any stack displaced store is likely part of the prologue.
	     Record that the register is being saved, and the offset 
	     into the stack.  */
	  info->saved_regs[LM32_REG1 (instruction)].addr =
	    LM32_IMM16 (instruction);
	}
      else if ((LM32_OPCODE (instruction) == OP_ADDI)
	       && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
	{
	  /* An add to the SP is likely to be part of the prologue.
	     Adjust stack size by whatever the instruction adds to the sp.  */
	  info->size -= LM32_IMM16 (instruction);
	}
      else if (			/* add fp,fp,sp */
		((LM32_OPCODE (instruction) == OP_ADD)
		 && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
		 && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
		 && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
		/* mv fp,imm */
		|| ((LM32_OPCODE (instruction) == OP_ADDI)
		    && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
		    && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
	{
	  /* Likely to be in the prologue for functions that require 
	     a frame pointer.  */
	}
      else
	{
	  /* Any other instruction is likely not to be part of the
	     prologue.  */
	  break;
	}
    }

  return pc;
}

/* Return PC of first non prologue instruction, for the function at the 
   specified address.  */

static CORE_ADDR
lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
  CORE_ADDR func_addr, limit_pc;
  struct lm32_frame_cache frame_info;
  struct trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];

  /* See if we can determine the end of the prologue via the symbol table.
     If so, then return either PC, or the PC after the prologue, whichever
     is greater.  */
  if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
    {
      CORE_ADDR post_prologue_pc
	= skip_prologue_using_sal (gdbarch, func_addr);
      if (post_prologue_pc != 0)
	return max (pc, post_prologue_pc);
    }

  /* Can't determine prologue from the symbol table, need to examine
     instructions.  */

  /* Find an upper limit on the function prologue using the debug
     information.  If the debug information could not be used to provide
     that bound, then use an arbitrary large number as the upper bound.  */
  limit_pc = skip_prologue_using_sal (gdbarch, pc);
  if (limit_pc == 0)
    limit_pc = pc + 100;	/* Magic.  */

  frame_info.saved_regs = saved_regs;
  return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
}

/* Create a breakpoint instruction.  */

static const gdb_byte *
lm32_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
			 int *lenptr)
{
  static const gdb_byte breakpoint[4] = { OP_RAISE << 2, 0, 0, 2 };

  *lenptr = sizeof (breakpoint);
  return breakpoint;
}

/* Setup registers and stack for faking a call to a function in the 
   inferior.  */

static CORE_ADDR
lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
		      struct regcache *regcache, CORE_ADDR bp_addr,
		      int nargs, struct value **args, CORE_ADDR sp,
		      int struct_return, CORE_ADDR struct_addr)
{
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  int first_arg_reg = SIM_LM32_R1_REGNUM;
  int num_arg_regs = 8;
  int i;

  /* Set the return address.  */
  regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);

  /* If we're returning a large struct, a pointer to the address to
     store it at is passed as a first hidden parameter.  */
  if (struct_return)
    {
      regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
      first_arg_reg++;
      num_arg_regs--;
      sp -= 4;
    }

  /* Setup parameters.  */
  for (i = 0; i < nargs; i++)
    {
      struct value *arg = args[i];
      struct type *arg_type = check_typedef (value_type (arg));
      gdb_byte *contents;
      ULONGEST val;

      /* Promote small integer types to int.  */
      switch (TYPE_CODE (arg_type))
	{
	case TYPE_CODE_INT:
	case TYPE_CODE_BOOL:
	case TYPE_CODE_CHAR:
	case TYPE_CODE_RANGE:
	case TYPE_CODE_ENUM:
	  if (TYPE_LENGTH (arg_type) < 4)
	    {
	      arg_type = builtin_type (gdbarch)->builtin_int32;
	      arg = value_cast (arg_type, arg);
	    }
	  break;
	}

      /* FIXME: Handle structures.  */

      contents = (gdb_byte *) value_contents (arg);
      val = extract_unsigned_integer (contents, TYPE_LENGTH (arg_type),
				      byte_order);

      /* First num_arg_regs parameters are passed by registers, 
         and the rest are passed on the stack.  */
      if (i < num_arg_regs)
	regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
      else
	{
	  write_memory_unsigned_integer (sp, TYPE_LENGTH (arg_type), byte_order,
					 val);
	  sp -= 4;
	}
    }

  /* Update stack pointer.  */
  regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);

  /* Return adjusted stack pointer.  */
  return sp;
}

/* Extract return value after calling a function in the inferior.  */

static void
lm32_extract_return_value (struct type *type, struct regcache *regcache,
			   gdb_byte *valbuf)
{
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  ULONGEST l;
  CORE_ADDR return_buffer;

  if (TYPE_CODE (type) != TYPE_CODE_STRUCT
      && TYPE_CODE (type) != TYPE_CODE_UNION
      && TYPE_CODE (type) != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4)
    {
      /* Return value is returned in a single register.  */
      regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
      store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l);
    }
  else if ((TYPE_CODE (type) == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8))
    {
      /* 64-bit values are returned in a register pair.  */
      regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
      memcpy (valbuf, &l, 4);
      regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
      memcpy (valbuf + 4, &l, 4);
    }
  else
    {
      /* Aggregate types greater than a single register are returned
         in memory.  FIXME: Unless they are only 2 regs?.  */
      regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
      return_buffer = l;
      read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
    }
}

/* Write into appropriate registers a function return value of type
   TYPE, given in virtual format.  */
static void
lm32_store_return_value (struct type *type, struct regcache *regcache,
			 const gdb_byte *valbuf)
{
  struct gdbarch *gdbarch = get_regcache_arch (regcache);
  enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
  ULONGEST val;
  int len = TYPE_LENGTH (type);

  if (len <= 4)
    {
      val = extract_unsigned_integer (valbuf, len, byte_order);
      regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
    }
  else if (len <= 8)
    {
      val = extract_unsigned_integer (valbuf, 4, byte_order);
      regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
      val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
      regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
    }
  else
    error (_("lm32_store_return_value: type length too large."));
}

/* Determine whether a functions return value is in a register or memory.  */
static enum return_value_convention
lm32_return_value (struct gdbarch *gdbarch, struct value *function,
		   struct type *valtype, struct regcache *regcache,
		   gdb_byte *readbuf, const gdb_byte *writebuf)
{
  enum type_code code = TYPE_CODE (valtype);

  if (code == TYPE_CODE_STRUCT
      || code == TYPE_CODE_UNION
      || code == TYPE_CODE_ARRAY || TYPE_LENGTH (valtype) > 8)
    return RETURN_VALUE_STRUCT_CONVENTION;

  if (readbuf)
    lm32_extract_return_value (valtype, regcache, readbuf);
  if (writebuf)
    lm32_store_return_value (valtype, regcache, writebuf);

  return RETURN_VALUE_REGISTER_CONVENTION;
}

static CORE_ADDR
lm32_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
  return frame_unwind_register_unsigned (next_frame, SIM_LM32_PC_REGNUM);
}

static CORE_ADDR
lm32_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
{
  return frame_unwind_register_unsigned (next_frame, SIM_LM32_SP_REGNUM);
}

static struct frame_id
lm32_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
{
  CORE_ADDR sp = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);

  return frame_id_build (sp, get_frame_pc (this_frame));
}

/* Put here the code to store, into fi->saved_regs, the addresses of
   the saved registers of frame described by FRAME_INFO.  This
   includes special registers such as pc and fp saved in special ways
   in the stack frame.  sp is even more special: the address we return
   for it IS the sp for the next frame.  */

static struct lm32_frame_cache *
lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache)
{
  CORE_ADDR current_pc;
  ULONGEST prev_sp;
  ULONGEST this_base;
  struct lm32_frame_cache *info;
  int i;

  if ((*this_prologue_cache))
    return (struct lm32_frame_cache *) (*this_prologue_cache);

  info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
  (*this_prologue_cache) = info;
  info->saved_regs = trad_frame_alloc_saved_regs (this_frame);

  info->pc = get_frame_func (this_frame);
  current_pc = get_frame_pc (this_frame);
  lm32_analyze_prologue (get_frame_arch (this_frame),
			 info->pc, current_pc, info);

  /* Compute the frame's base, and the previous frame's SP.  */
  this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
  prev_sp = this_base + info->size;
  info->base = this_base;

  /* Convert callee save offsets into addresses.  */
  for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
    {
      if (trad_frame_addr_p (info->saved_regs, i))
	info->saved_regs[i].addr = this_base + info->saved_regs[i].addr;
    }

  /* The call instruction moves the caller's PC in the callee's RA register.
     Since this is an unwind, do the reverse.  Copy the location of RA register
     into PC (the address / regnum) so that a request for PC will be
     converted into a request for the RA register.  */
  info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];

  /* The previous frame's SP needed to be computed.  Save the computed
     value.  */
  trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp);

  return info;
}

static void
lm32_frame_this_id (struct frame_info *this_frame, void **this_cache,
		    struct frame_id *this_id)
{
  struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);

  /* This marks the outermost frame.  */
  if (cache->base == 0)
    return;

  (*this_id) = frame_id_build (cache->base, cache->pc);
}

static struct value *
lm32_frame_prev_register (struct frame_info *this_frame,
			  void **this_prologue_cache, int regnum)
{
  struct lm32_frame_cache *info;

  info = lm32_frame_cache (this_frame, this_prologue_cache);
  return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
}

static const struct frame_unwind lm32_frame_unwind = {
  NORMAL_FRAME,
  default_frame_unwind_stop_reason,
  lm32_frame_this_id,
  lm32_frame_prev_register,
  NULL,
  default_frame_sniffer
};

static CORE_ADDR
lm32_frame_base_address (struct frame_info *this_frame, void **this_cache)
{
  struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);

  return info->base;
}

static const struct frame_base lm32_frame_base = {
  &lm32_frame_unwind,
  lm32_frame_base_address,
  lm32_frame_base_address,
  lm32_frame_base_address
};

static CORE_ADDR
lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
{
  /* Align to the size of an instruction (so that they can safely be
     pushed onto the stack.  */
  return sp & ~3;
}

static struct gdbarch *
lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
{
  struct gdbarch *gdbarch;
  struct gdbarch_tdep *tdep;

  /* If there is already a candidate, use it.  */
  arches = gdbarch_list_lookup_by_info (arches, &info);
  if (arches != NULL)
    return arches->gdbarch;

  /* None found, create a new architecture from the information provided.  */
  tdep = XNEW (struct gdbarch_tdep);
  gdbarch = gdbarch_alloc (&info, tdep);

  /* Type sizes.  */
  set_gdbarch_short_bit (gdbarch, 16);
  set_gdbarch_int_bit (gdbarch, 32);
  set_gdbarch_long_bit (gdbarch, 32);
  set_gdbarch_long_long_bit (gdbarch, 64);
  set_gdbarch_float_bit (gdbarch, 32);
  set_gdbarch_double_bit (gdbarch, 64);
  set_gdbarch_long_double_bit (gdbarch, 64);
  set_gdbarch_ptr_bit (gdbarch, 32);

  /* Register info.  */
  set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
  set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
  set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
  set_gdbarch_register_name (gdbarch, lm32_register_name);
  set_gdbarch_register_type (gdbarch, lm32_register_type);
  set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);

  /* Frame info.  */
  set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
  set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
  set_gdbarch_decr_pc_after_break (gdbarch, 0);
  set_gdbarch_frame_args_skip (gdbarch, 0);

  /* Frame unwinding.  */
  set_gdbarch_frame_align (gdbarch, lm32_frame_align);
  frame_base_set_default (gdbarch, &lm32_frame_base);
  set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc);
  set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp);
  set_gdbarch_dummy_id (gdbarch, lm32_dummy_id);
  frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);

  /* Breakpoints.  */
  set_gdbarch_breakpoint_from_pc (gdbarch, lm32_breakpoint_from_pc);
  set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);

  /* Calling functions in the inferior.  */
  set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
  set_gdbarch_return_value (gdbarch, lm32_return_value);

  /* Instruction disassembler.  */
  set_gdbarch_print_insn (gdbarch, print_insn_lm32);

  lm32_add_reggroups (gdbarch);
  set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);

  return gdbarch;
}

/* -Wmissing-prototypes */
extern initialize_file_ftype _initialize_lm32_tdep;

void
_initialize_lm32_tdep (void)
{
  register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);
}
Commit	Line	Data
c28c63d8 JB	1	/* Target-dependent code for Lattice Mico32 processor, for GDB.
	2	Contributed by Jon Beniston <jon@beniston.com>
	3
618f726f	4	Copyright (C) 2009-2016 Free Software Foundation, Inc.
c28c63d8 JB	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 3 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
	20
	21	#include "defs.h"
	22	#include "frame.h"
	23	#include "frame-unwind.h"
	24	#include "frame-base.h"
	25	#include "inferior.h"
	26	#include "dis-asm.h"
	27	#include "symfile.h"
	28	#include "remote.h"
	29	#include "gdbcore.h"
	30	#include "gdb/sim-lm32.h"
	31	#include "gdb/callback.h"
	32	#include "gdb/remote-sim.h"
	33	#include "sim-regno.h"
	34	#include "arch-utils.h"
	35	#include "regcache.h"
	36	#include "trad-frame.h"
	37	#include "reggroups.h"
	38	#include "opcodes/lm32-desc.h"
	39
c28c63d8 JB	40	/* Macros to extract fields from an instruction. */
	41	#define LM32_OPCODE(insn) ((insn >> 26) & 0x3f)
	42	#define LM32_REG0(insn) ((insn >> 21) & 0x1f)
	43	#define LM32_REG1(insn) ((insn >> 16) & 0x1f)
	44	#define LM32_REG2(insn) ((insn >> 11) & 0x1f)
	45	#define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16)
	46
	47	struct gdbarch_tdep
	48	{
1777feb0	49	/* gdbarch target dependent data here. Currently unused for LM32. */
c28c63d8 JB	50	};
	51
	52	struct lm32_frame_cache
	53	{
	54	/* The frame's base. Used when constructing a frame ID. */
	55	CORE_ADDR base;
	56	CORE_ADDR pc;
	57	/* Size of frame. */
	58	int size;
	59	/* Table indicating the location of each and every register. */
	60	struct trad_frame_saved_reg *saved_regs;
	61	};
	62
	63	/* Add the available register groups. */
	64
	65	static void
	66	lm32_add_reggroups (struct gdbarch *gdbarch)
	67	{
	68	reggroup_add (gdbarch, general_reggroup);
	69	reggroup_add (gdbarch, all_reggroup);
	70	reggroup_add (gdbarch, system_reggroup);
	71	}
	72
	73	/* Return whether a given register is in a given group. */
	74
	75	static int
	76	lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
	77	struct reggroup *group)
	78	{
	79	if (group == general_reggroup)
	80	return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
	81	\|\| (regnum == SIM_LM32_PC_REGNUM);
	82	else if (group == system_reggroup)
	83	return ((regnum >= SIM_LM32_EA_REGNUM) && (regnum <= SIM_LM32_BA_REGNUM))
	84	\|\| ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
	85	return default_register_reggroup_p (gdbarch, regnum, group);
	86	}
	87
	88	/* Return a name that corresponds to the given register number. */
	89
	90	static const char *
	91	lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
	92	{
	93	static char *register_names[] = {
	94	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
	95	"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
	96	"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
	97	"r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
	98	"PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
	99	};
	100
	101	if ((reg_nr < 0) \|\| (reg_nr >= ARRAY_SIZE (register_names)))
	102	return NULL;
	103	else
	104	return register_names[reg_nr];
	105	}
	106
	107	/* Return type of register. */
	108
	109	static struct type *
	110	lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
	111	{
df4df182	112	return builtin_type (gdbarch)->builtin_int32;
c28c63d8 JB	113	}
	114
	115	/* Return non-zero if a register can't be written. */
	116
	117	static int
	118	lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
	119	{
	120	return (regno == SIM_LM32_R0_REGNUM) \|\| (regno == SIM_LM32_EID_REGNUM);
	121	}
	122
	123	/* Analyze a function's prologue. */
	124
	125	static CORE_ADDR
e17a4113 UW	126	lm32_analyze_prologue (struct gdbarch *gdbarch,
e17a4113 UW	127	CORE_ADDR pc, CORE_ADDR limit,
c28c63d8 JB	128	struct lm32_frame_cache *info)
c28c63d8 JB	129	{
e17a4113	130	enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c28c63d8 JB	131	unsigned long instruction;
	132
	133	/* Keep reading though instructions, until we come across an instruction
	134	that isn't likely to be part of the prologue. */
	135	info->size = 0;
	136	for (; pc < limit; pc += 4)
	137	{
	138
	139	/* Read an instruction. */
e17a4113	140	instruction = read_memory_integer (pc, 4, byte_order);
c28c63d8 JB	141
	142	if ((LM32_OPCODE (instruction) == OP_SW)
	143	&& (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
	144	{
1777feb0	145	/* Any stack displaced store is likely part of the prologue.
c28c63d8 JB	146	Record that the register is being saved, and the offset
	147	into the stack. */
	148	info->saved_regs[LM32_REG1 (instruction)].addr =
	149	LM32_IMM16 (instruction);
	150	}
	151	else if ((LM32_OPCODE (instruction) == OP_ADDI)
	152	&& (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
	153	{
1777feb0	154	/* An add to the SP is likely to be part of the prologue.
c28c63d8 JB	155	Adjust stack size by whatever the instruction adds to the sp. */
	156	info->size -= LM32_IMM16 (instruction);
	157	}
	158	else if ( /* add fp,fp,sp */
	159	((LM32_OPCODE (instruction) == OP_ADD)
	160	&& (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
	161	&& (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
	162	&& (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
	163	/* mv fp,imm */
	164	\|\| ((LM32_OPCODE (instruction) == OP_ADDI)
	165	&& (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
	166	&& (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
	167	{
	168	/* Likely to be in the prologue for functions that require
	169	a frame pointer. */
	170	}
	171	else
	172	{
1777feb0 MS	173	/* Any other instruction is likely not to be part of the
1777feb0 MS	174	prologue. */
c28c63d8 JB	175	break;
	176	}
	177	}
	178
	179	return pc;
	180	}
	181
	182	/* Return PC of first non prologue instruction, for the function at the
	183	specified address. */
	184
	185	static CORE_ADDR
	186	lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
	187	{
	188	CORE_ADDR func_addr, limit_pc;
c28c63d8 JB	189	struct lm32_frame_cache frame_info;
	190	struct trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
	191
	192	/* See if we can determine the end of the prologue via the symbol table.
	193	If so, then return either PC, or the PC after the prologue, whichever
	194	is greater. */
	195	if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
	196	{
d80b854b UW	197	CORE_ADDR post_prologue_pc
d80b854b UW	198	= skip_prologue_using_sal (gdbarch, func_addr);
c28c63d8 JB	199	if (post_prologue_pc != 0)
	200	return max (pc, post_prologue_pc);
	201	}
	202
	203	/* Can't determine prologue from the symbol table, need to examine
	204	instructions. */
	205
	206	/* Find an upper limit on the function prologue using the debug
	207	information. If the debug information could not be used to provide
	208	that bound, then use an arbitrary large number as the upper bound. */
d80b854b	209	limit_pc = skip_prologue_using_sal (gdbarch, pc);
c28c63d8 JB	210	if (limit_pc == 0)
	211	limit_pc = pc + 100; /* Magic. */
	212
	213	frame_info.saved_regs = saved_regs;
e17a4113	214	return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
c28c63d8 JB	215	}
	216
	217	/* Create a breakpoint instruction. */
	218
	219	static const gdb_byte *
	220	lm32_breakpoint_from_pc (struct gdbarch gdbarch, CORE_ADDR pcptr,
	221	int *lenptr)
	222	{
	223	static const gdb_byte breakpoint[4] = { OP_RAISE << 2, 0, 0, 2 };
	224
	225	*lenptr = sizeof (breakpoint);
	226	return breakpoint;
	227	}
	228
	229	/* Setup registers and stack for faking a call to a function in the
	230	inferior. */
	231
	232	static CORE_ADDR
	233	lm32_push_dummy_call (struct gdbarch gdbarch, struct value function,
	234	struct regcache *regcache, CORE_ADDR bp_addr,
	235	int nargs, struct value **args, CORE_ADDR sp,
	236	int struct_return, CORE_ADDR struct_addr)
	237	{
e17a4113	238	enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c28c63d8 JB	239	int first_arg_reg = SIM_LM32_R1_REGNUM;
	240	int num_arg_regs = 8;
	241	int i;
	242
	243	/* Set the return address. */
	244	regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
	245
	246	/* If we're returning a large struct, a pointer to the address to
	247	store it at is passed as a first hidden parameter. */
	248	if (struct_return)
	249	{
	250	regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
	251	first_arg_reg++;
	252	num_arg_regs--;
	253	sp -= 4;
	254	}
	255
	256	/* Setup parameters. */
	257	for (i = 0; i < nargs; i++)
	258	{
	259	struct value *arg = args[i];
	260	struct type *arg_type = check_typedef (value_type (arg));
	261	gdb_byte *contents;
c28c63d8 JB	262	ULONGEST val;
	263
	264	/* Promote small integer types to int. */
	265	switch (TYPE_CODE (arg_type))
	266	{
	267	case TYPE_CODE_INT:
	268	case TYPE_CODE_BOOL:
	269	case TYPE_CODE_CHAR:
	270	case TYPE_CODE_RANGE:
	271	case TYPE_CODE_ENUM:
	272	if (TYPE_LENGTH (arg_type) < 4)
	273	{
df4df182	274	arg_type = builtin_type (gdbarch)->builtin_int32;
c28c63d8 JB	275	arg = value_cast (arg_type, arg);
	276	}
	277	break;
	278	}
	279
	280	/* FIXME: Handle structures. */
	281
	282	contents = (gdb_byte *) value_contents (arg);
744a8059 SP	283	val = extract_unsigned_integer (contents, TYPE_LENGTH (arg_type),
744a8059 SP	284	byte_order);
c28c63d8 JB	285
	286	/* First num_arg_regs parameters are passed by registers,
	287	and the rest are passed on the stack. */
	288	if (i < num_arg_regs)
	289	regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
	290	else
	291	{
4666fec3 SM	292	write_memory_unsigned_integer (sp, TYPE_LENGTH (arg_type), byte_order,
4666fec3 SM	293	val);
c28c63d8 JB	294	sp -= 4;
	295	}
	296	}
	297
	298	/* Update stack pointer. */
	299	regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
	300
	301	/* Return adjusted stack pointer. */
	302	return sp;
	303	}
	304
	305	/* Extract return value after calling a function in the inferior. */
	306
	307	static void
	308	lm32_extract_return_value (struct type type, struct regcache regcache,
	309	gdb_byte *valbuf)
	310	{
e17a4113 UW	311	struct gdbarch *gdbarch = get_regcache_arch (regcache);
e17a4113 UW	312	enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c28c63d8 JB	313	ULONGEST l;
	314	CORE_ADDR return_buffer;
	315
	316	if (TYPE_CODE (type) != TYPE_CODE_STRUCT
	317	&& TYPE_CODE (type) != TYPE_CODE_UNION
	318	&& TYPE_CODE (type) != TYPE_CODE_ARRAY && TYPE_LENGTH (type) <= 4)
	319	{
	320	/* Return value is returned in a single register. */
	321	regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
e17a4113	322	store_unsigned_integer (valbuf, TYPE_LENGTH (type), byte_order, l);
c28c63d8 JB	323	}
	324	else if ((TYPE_CODE (type) == TYPE_CODE_INT) && (TYPE_LENGTH (type) == 8))
	325	{
	326	/* 64-bit values are returned in a register pair. */
	327	regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
	328	memcpy (valbuf, &l, 4);
	329	regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
	330	memcpy (valbuf + 4, &l, 4);
	331	}
	332	else
	333	{
1777feb0 MS	334	/* Aggregate types greater than a single register are returned
1777feb0 MS	335	in memory. FIXME: Unless they are only 2 regs?. */
c28c63d8 JB	336	regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
	337	return_buffer = l;
	338	read_memory (return_buffer, valbuf, TYPE_LENGTH (type));
	339	}
	340	}
	341
	342	/* Write into appropriate registers a function return value of type
	343	TYPE, given in virtual format. */
	344	static void
	345	lm32_store_return_value (struct type type, struct regcache regcache,
	346	const gdb_byte *valbuf)
	347	{
e17a4113 UW	348	struct gdbarch *gdbarch = get_regcache_arch (regcache);
e17a4113 UW	349	enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
c28c63d8	350	ULONGEST val;
bad43aa5	351	int len = TYPE_LENGTH (type);
c28c63d8	352
bad43aa5	353	if (len <= 4)
c28c63d8	354	{
bad43aa5	355	val = extract_unsigned_integer (valbuf, len, byte_order);
c28c63d8 JB	356	regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
c28c63d8 JB	357	}
bad43aa5	358	else if (len <= 8)
c28c63d8	359	{
e17a4113	360	val = extract_unsigned_integer (valbuf, 4, byte_order);
c28c63d8	361	regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
bad43aa5	362	val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
c28c63d8 JB	363	regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
	364	}
	365	else
	366	error (_("lm32_store_return_value: type length too large."));
	367	}
	368
	369	/* Determine whether a functions return value is in a register or memory. */
	370	static enum return_value_convention
6a3a010b	371	lm32_return_value (struct gdbarch gdbarch, struct value function,
c28c63d8 JB	372	struct type valtype, struct regcache regcache,
	373	gdb_byte readbuf, const gdb_byte writebuf)
	374	{
	375	enum type_code code = TYPE_CODE (valtype);
	376
	377	if (code == TYPE_CODE_STRUCT
	378	\|\| code == TYPE_CODE_UNION
	379	\|\| code == TYPE_CODE_ARRAY \|\| TYPE_LENGTH (valtype) > 8)
	380	return RETURN_VALUE_STRUCT_CONVENTION;
	381
	382	if (readbuf)
	383	lm32_extract_return_value (valtype, regcache, readbuf);
	384	if (writebuf)
	385	lm32_store_return_value (valtype, regcache, writebuf);
	386
	387	return RETURN_VALUE_REGISTER_CONVENTION;
	388	}
	389
	390	static CORE_ADDR
	391	lm32_unwind_pc (struct gdbarch gdbarch, struct frame_info next_frame)
	392	{
	393	return frame_unwind_register_unsigned (next_frame, SIM_LM32_PC_REGNUM);
	394	}
	395
	396	static CORE_ADDR
	397	lm32_unwind_sp (struct gdbarch gdbarch, struct frame_info next_frame)
	398	{
	399	return frame_unwind_register_unsigned (next_frame, SIM_LM32_SP_REGNUM);
	400	}
	401
	402	static struct frame_id
	403	lm32_dummy_id (struct gdbarch gdbarch, struct frame_info this_frame)
	404	{
	405	CORE_ADDR sp = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
	406
	407	return frame_id_build (sp, get_frame_pc (this_frame));
	408	}
	409
	410	/* Put here the code to store, into fi->saved_regs, the addresses of
	411	the saved registers of frame described by FRAME_INFO. This
	412	includes special registers such as pc and fp saved in special ways
	413	in the stack frame. sp is even more special: the address we return
	414	for it IS the sp for the next frame. */
	415
	416	static struct lm32_frame_cache *
	417	lm32_frame_cache (struct frame_info this_frame, void *this_prologue_cache)
	418	{
c28c63d8 JB	419	CORE_ADDR current_pc;
	420	ULONGEST prev_sp;
	421	ULONGEST this_base;
	422	struct lm32_frame_cache *info;
c28c63d8	423	int i;
c28c63d8 JB	424
c28c63d8 JB	425	if ((*this_prologue_cache))
9a3c8263	426	return (struct lm32_frame_cache ) (this_prologue_cache);
c28c63d8 JB	427
	428	info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
	429	(*this_prologue_cache) = info;
	430	info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
	431
	432	info->pc = get_frame_func (this_frame);
	433	current_pc = get_frame_pc (this_frame);
e17a4113 UW	434	lm32_analyze_prologue (get_frame_arch (this_frame),
e17a4113 UW	435	info->pc, current_pc, info);
c28c63d8 JB	436
	437	/* Compute the frame's base, and the previous frame's SP. */
	438	this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
	439	prev_sp = this_base + info->size;
	440	info->base = this_base;
	441
	442	/* Convert callee save offsets into addresses. */
	443	for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
	444	{
	445	if (trad_frame_addr_p (info->saved_regs, i))
	446	info->saved_regs[i].addr = this_base + info->saved_regs[i].addr;
	447	}
	448
	449	/* The call instruction moves the caller's PC in the callee's RA register.
	450	Since this is an unwind, do the reverse. Copy the location of RA register
	451	into PC (the address / regnum) so that a request for PC will be
	452	converted into a request for the RA register. */
	453	info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
	454
1777feb0 MS	455	/* The previous frame's SP needed to be computed. Save the computed
1777feb0 MS	456	value. */
c28c63d8 JB	457	trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp);
	458
	459	return info;
	460	}
	461
	462	static void
	463	lm32_frame_this_id (struct frame_info this_frame, void *this_cache,
	464	struct frame_id *this_id)
	465	{
	466	struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
	467
	468	/* This marks the outermost frame. */
	469	if (cache->base == 0)
	470	return;
	471
	472	(*this_id) = frame_id_build (cache->base, cache->pc);
	473	}
	474
	475	static struct value *
	476	lm32_frame_prev_register (struct frame_info *this_frame,
	477	void **this_prologue_cache, int regnum)
	478	{
	479	struct lm32_frame_cache *info;
	480
	481	info = lm32_frame_cache (this_frame, this_prologue_cache);
	482	return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
	483	}
	484
	485	static const struct frame_unwind lm32_frame_unwind = {
	486	NORMAL_FRAME,
8fbca658	487	default_frame_unwind_stop_reason,
c28c63d8 JB	488	lm32_frame_this_id,
	489	lm32_frame_prev_register,
	490	NULL,
	491	default_frame_sniffer
	492	};
	493
	494	static CORE_ADDR
	495	lm32_frame_base_address (struct frame_info this_frame, void *this_cache)
	496	{
	497	struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
	498
	499	return info->base;
	500	}
	501
	502	static const struct frame_base lm32_frame_base = {
	503	&lm32_frame_unwind,
	504	lm32_frame_base_address,
	505	lm32_frame_base_address,
	506	lm32_frame_base_address
	507	};
	508
	509	static CORE_ADDR
	510	lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
	511	{
	512	/* Align to the size of an instruction (so that they can safely be
	513	pushed onto the stack. */
	514	return sp & ~3;
	515	}
	516
	517	static struct gdbarch *
	518	lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
	519	{
	520	struct gdbarch *gdbarch;
	521	struct gdbarch_tdep *tdep;
	522
	523	/* If there is already a candidate, use it. */
	524	arches = gdbarch_list_lookup_by_info (arches, &info);
	525	if (arches != NULL)
	526	return arches->gdbarch;
	527
	528	/* None found, create a new architecture from the information provided. */
70ba0933	529	tdep = XNEW (struct gdbarch_tdep);
c28c63d8 JB	530	gdbarch = gdbarch_alloc (&info, tdep);
	531
	532	/* Type sizes. */
	533	set_gdbarch_short_bit (gdbarch, 16);
	534	set_gdbarch_int_bit (gdbarch, 32);
	535	set_gdbarch_long_bit (gdbarch, 32);
	536	set_gdbarch_long_long_bit (gdbarch, 64);
	537	set_gdbarch_float_bit (gdbarch, 32);
	538	set_gdbarch_double_bit (gdbarch, 64);
	539	set_gdbarch_long_double_bit (gdbarch, 64);
	540	set_gdbarch_ptr_bit (gdbarch, 32);
	541
	542	/* Register info. */
	543	set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
	544	set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
	545	set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
	546	set_gdbarch_register_name (gdbarch, lm32_register_name);
	547	set_gdbarch_register_type (gdbarch, lm32_register_type);
	548	set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
	549
	550	/* Frame info. */
	551	set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
	552	set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
	553	set_gdbarch_decr_pc_after_break (gdbarch, 0);
	554	set_gdbarch_frame_args_skip (gdbarch, 0);
	555
	556	/* Frame unwinding. */
	557	set_gdbarch_frame_align (gdbarch, lm32_frame_align);
	558	frame_base_set_default (gdbarch, &lm32_frame_base);
	559	set_gdbarch_unwind_pc (gdbarch, lm32_unwind_pc);
	560	set_gdbarch_unwind_sp (gdbarch, lm32_unwind_sp);
	561	set_gdbarch_dummy_id (gdbarch, lm32_dummy_id);
	562	frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
	563
	564	/* Breakpoints. */
	565	set_gdbarch_breakpoint_from_pc (gdbarch, lm32_breakpoint_from_pc);
	566	set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
	567
	568	/* Calling functions in the inferior. */
	569	set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
	570	set_gdbarch_return_value (gdbarch, lm32_return_value);
	571
	572	/* Instruction disassembler. */
	573	set_gdbarch_print_insn (gdbarch, print_insn_lm32);
	574
	575	lm32_add_reggroups (gdbarch);
	576	set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
	577
	578	return gdbarch;
	579	}
	580
693be288 JK	581	/* -Wmissing-prototypes */
	582	extern initialize_file_ftype _initialize_lm32_tdep;
	583
c28c63d8 JB	584	void
	585	_initialize_lm32_tdep (void)
	586	{
	587	register_gdbarch_init (bfd_arch_lm32, lm32_gdbarch_init);
	588	}