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96309189 MS |
1 | /* Renesas M32C target-dependent code for GDB, the GNU debugger. |
2 | ||
3666a048 | 3 | Copyright (C) 2004-2021 Free Software Foundation, Inc. |
96309189 MS |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
96309189 MS |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
96309189 MS |
19 | |
20 | #include "defs.h" | |
96309189 | 21 | #include "gdb/sim-m32c.h" |
96309189 MS |
22 | #include "gdbtypes.h" |
23 | #include "regcache.h" | |
24 | #include "arch-utils.h" | |
25 | #include "frame.h" | |
26 | #include "frame-unwind.h" | |
96309189 MS |
27 | #include "symtab.h" |
28 | #include "gdbcore.h" | |
29 | #include "value.h" | |
30 | #include "reggroups.h" | |
31 | #include "prologue-value.h" | |
77e371c0 | 32 | #include "objfiles.h" |
76eb8ef1 | 33 | #include "gdbarch.h" |
96309189 MS |
34 | |
35 | \f | |
36 | /* The m32c tdep structure. */ | |
37 | ||
38 | static struct reggroup *m32c_dma_reggroup; | |
39 | ||
96309189 MS |
40 | /* The type of a function that moves the value of REG between CACHE or |
41 | BUF --- in either direction. */ | |
6da660c7 SM |
42 | typedef enum register_status (m32c_write_reg_t) (struct m32c_reg *reg, |
43 | struct regcache *cache, | |
44 | const gdb_byte *buf); | |
45 | ||
46 | typedef enum register_status (m32c_read_reg_t) (struct m32c_reg *reg, | |
849d0ba8 | 47 | readable_regcache *cache, |
6da660c7 | 48 | gdb_byte *buf); |
96309189 MS |
49 | |
50 | struct m32c_reg | |
51 | { | |
52 | /* The name of this register. */ | |
53 | const char *name; | |
54 | ||
55 | /* Its type. */ | |
56 | struct type *type; | |
57 | ||
58 | /* The architecture this register belongs to. */ | |
59 | struct gdbarch *arch; | |
60 | ||
61 | /* Its GDB register number. */ | |
62 | int num; | |
63 | ||
64 | /* Its sim register number. */ | |
65 | int sim_num; | |
66 | ||
67 | /* Its DWARF register number, or -1 if it doesn't have one. */ | |
68 | int dwarf_num; | |
69 | ||
70 | /* Register group memberships. */ | |
71 | unsigned int general_p : 1; | |
72 | unsigned int dma_p : 1; | |
73 | unsigned int system_p : 1; | |
74 | unsigned int save_restore_p : 1; | |
75 | ||
76 | /* Functions to read its value from a regcache, and write its value | |
77 | to a regcache. */ | |
6da660c7 SM |
78 | m32c_read_reg_t *read; |
79 | m32c_write_reg_t *write; | |
96309189 MS |
80 | |
81 | /* Data for READ and WRITE functions. The exact meaning depends on | |
82 | the specific functions selected; see the comments for those | |
83 | functions. */ | |
84 | struct m32c_reg *rx, *ry; | |
85 | int n; | |
86 | }; | |
87 | ||
88 | ||
89 | /* An overestimate of the number of raw and pseudoregisters we will | |
90 | have. The exact answer depends on the variant of the architecture | |
91 | at hand, but we can use this to declare statically allocated | |
92 | arrays, and bump it up when needed. */ | |
93 | #define M32C_MAX_NUM_REGS (75) | |
94 | ||
95 | /* The largest assigned DWARF register number. */ | |
96 | #define M32C_MAX_DWARF_REGNUM (40) | |
97 | ||
98 | ||
345bd07c | 99 | struct m32c_gdbarch_tdep : gdbarch_tdep |
96309189 MS |
100 | { |
101 | /* All the registers for this variant, indexed by GDB register | |
102 | number, and the number of registers present. */ | |
345bd07c | 103 | struct m32c_reg regs[M32C_MAX_NUM_REGS] {}; |
96309189 MS |
104 | |
105 | /* The number of valid registers. */ | |
345bd07c | 106 | int num_regs = 0; |
96309189 MS |
107 | |
108 | /* Interesting registers. These are pointers into REGS. */ | |
345bd07c SM |
109 | struct m32c_reg *pc = nullptr, *flg = nullptr; |
110 | struct m32c_reg *r0 = nullptr, *r1 = nullptr, *r2 = nullptr, *r3 = nullptr, | |
111 | *a0 = nullptr, *a1 = nullptr; | |
112 | struct m32c_reg *r2r0 = nullptr, *r3r2r1r0 = nullptr, *r3r1r2r0 = nullptr; | |
113 | struct m32c_reg *sb = nullptr, *fb = nullptr, *sp = nullptr; | |
96309189 MS |
114 | |
115 | /* A table indexed by DWARF register numbers, pointing into | |
116 | REGS. */ | |
345bd07c | 117 | struct m32c_reg *dwarf_regs[M32C_MAX_DWARF_REGNUM + 1] {}; |
96309189 MS |
118 | |
119 | /* Types for this architecture. We can't use the builtin_type_foo | |
120 | types, because they're not initialized when building a gdbarch | |
121 | structure. */ | |
345bd07c SM |
122 | struct type *voyd = nullptr, *ptr_voyd = nullptr, *func_voyd = nullptr; |
123 | struct type *uint8 = nullptr, *uint16 = nullptr; | |
124 | struct type *int8 = nullptr, *int16 = nullptr, *int32 = nullptr, | |
125 | *int64 = nullptr; | |
96309189 MS |
126 | |
127 | /* The types for data address and code address registers. */ | |
345bd07c | 128 | struct type *data_addr_reg_type = nullptr, *code_addr_reg_type = nullptr; |
96309189 MS |
129 | |
130 | /* The number of bytes a return address pushed by a 'jsr' instruction | |
131 | occupies on the stack. */ | |
345bd07c | 132 | int ret_addr_bytes = 0; |
96309189 MS |
133 | |
134 | /* The number of bytes an address register occupies on the stack | |
135 | when saved by an 'enter' or 'pushm' instruction. */ | |
345bd07c | 136 | int push_addr_bytes = 0; |
96309189 MS |
137 | }; |
138 | ||
139 | \f | |
140 | /* Types. */ | |
141 | ||
142 | static void | |
143 | make_types (struct gdbarch *arch) | |
144 | { | |
345bd07c | 145 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); |
96309189 MS |
146 | unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; |
147 | int data_addr_reg_bits, code_addr_reg_bits; | |
148 | char type_name[50]; | |
149 | ||
150 | #if 0 | |
151 | /* This is used to clip CORE_ADDR values, so this value is | |
152 | appropriate both on the m32c, where pointers are 32 bits long, | |
153 | and on the m16c, where pointers are sixteen bits long, but there | |
154 | may be code above the 64k boundary. */ | |
155 | set_gdbarch_addr_bit (arch, 24); | |
156 | #else | |
157 | /* GCC uses 32 bits for addrs in the dwarf info, even though | |
158 | only 16/24 bits are used. Setting addr_bit to 24 causes | |
159 | errors in reading the dwarf addresses. */ | |
160 | set_gdbarch_addr_bit (arch, 32); | |
161 | #endif | |
162 | ||
163 | set_gdbarch_int_bit (arch, 16); | |
164 | switch (mach) | |
165 | { | |
166 | case bfd_mach_m16c: | |
167 | data_addr_reg_bits = 16; | |
168 | code_addr_reg_bits = 24; | |
169 | set_gdbarch_ptr_bit (arch, 16); | |
170 | tdep->ret_addr_bytes = 3; | |
171 | tdep->push_addr_bytes = 2; | |
172 | break; | |
173 | ||
174 | case bfd_mach_m32c: | |
175 | data_addr_reg_bits = 24; | |
176 | code_addr_reg_bits = 24; | |
177 | set_gdbarch_ptr_bit (arch, 32); | |
178 | tdep->ret_addr_bytes = 4; | |
179 | tdep->push_addr_bytes = 4; | |
180 | break; | |
181 | ||
182 | default: | |
f3574227 | 183 | gdb_assert_not_reached ("unexpected mach"); |
96309189 MS |
184 | } |
185 | ||
186 | /* The builtin_type_mumble variables are sometimes uninitialized when | |
187 | this is called, so we avoid using them. */ | |
77b7c781 | 188 | tdep->voyd = arch_type (arch, TYPE_CODE_VOID, TARGET_CHAR_BIT, "void"); |
e9bb382b | 189 | tdep->ptr_voyd |
88dfca6c | 190 | = arch_pointer_type (arch, gdbarch_ptr_bit (arch), NULL, tdep->voyd); |
96309189 MS |
191 | tdep->func_voyd = lookup_function_type (tdep->voyd); |
192 | ||
8c042590 PM |
193 | xsnprintf (type_name, sizeof (type_name), "%s_data_addr_t", |
194 | gdbarch_bfd_arch_info (arch)->printable_name); | |
96309189 | 195 | tdep->data_addr_reg_type |
88dfca6c | 196 | = arch_pointer_type (arch, data_addr_reg_bits, type_name, tdep->voyd); |
96309189 | 197 | |
8c042590 PM |
198 | xsnprintf (type_name, sizeof (type_name), "%s_code_addr_t", |
199 | gdbarch_bfd_arch_info (arch)->printable_name); | |
96309189 | 200 | tdep->code_addr_reg_type |
88dfca6c | 201 | = arch_pointer_type (arch, code_addr_reg_bits, type_name, tdep->func_voyd); |
e9bb382b UW |
202 | |
203 | tdep->uint8 = arch_integer_type (arch, 8, 1, "uint8_t"); | |
204 | tdep->uint16 = arch_integer_type (arch, 16, 1, "uint16_t"); | |
205 | tdep->int8 = arch_integer_type (arch, 8, 0, "int8_t"); | |
206 | tdep->int16 = arch_integer_type (arch, 16, 0, "int16_t"); | |
207 | tdep->int32 = arch_integer_type (arch, 32, 0, "int32_t"); | |
208 | tdep->int64 = arch_integer_type (arch, 64, 0, "int64_t"); | |
96309189 MS |
209 | } |
210 | ||
211 | ||
212 | \f | |
213 | /* Register set. */ | |
214 | ||
215 | static const char * | |
d93859e2 | 216 | m32c_register_name (struct gdbarch *gdbarch, int num) |
96309189 | 217 | { |
345bd07c SM |
218 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
219 | return tdep->regs[num].name; | |
96309189 MS |
220 | } |
221 | ||
222 | ||
223 | static struct type * | |
224 | m32c_register_type (struct gdbarch *arch, int reg_nr) | |
225 | { | |
345bd07c SM |
226 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); |
227 | return tdep->regs[reg_nr].type; | |
96309189 MS |
228 | } |
229 | ||
230 | ||
231 | static int | |
e7faf938 | 232 | m32c_register_sim_regno (struct gdbarch *gdbarch, int reg_nr) |
96309189 | 233 | { |
345bd07c SM |
234 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
235 | return tdep->regs[reg_nr].sim_num; | |
96309189 MS |
236 | } |
237 | ||
238 | ||
239 | static int | |
d3f73121 | 240 | m32c_debug_info_reg_to_regnum (struct gdbarch *gdbarch, int reg_nr) |
96309189 | 241 | { |
345bd07c | 242 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
96309189 MS |
243 | if (0 <= reg_nr && reg_nr <= M32C_MAX_DWARF_REGNUM |
244 | && tdep->dwarf_regs[reg_nr]) | |
245 | return tdep->dwarf_regs[reg_nr]->num; | |
246 | else | |
247 | /* The DWARF CFI code expects to see -1 for invalid register | |
248 | numbers. */ | |
249 | return -1; | |
250 | } | |
251 | ||
252 | ||
63807e1d | 253 | static int |
96309189 MS |
254 | m32c_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
255 | struct reggroup *group) | |
256 | { | |
345bd07c | 257 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
96309189 MS |
258 | struct m32c_reg *reg = &tdep->regs[regnum]; |
259 | ||
260 | /* The anonymous raw registers aren't in any groups. */ | |
261 | if (! reg->name) | |
262 | return 0; | |
263 | ||
264 | if (group == all_reggroup) | |
265 | return 1; | |
266 | ||
267 | if (group == general_reggroup | |
268 | && reg->general_p) | |
269 | return 1; | |
270 | ||
271 | if (group == m32c_dma_reggroup | |
272 | && reg->dma_p) | |
273 | return 1; | |
274 | ||
275 | if (group == system_reggroup | |
276 | && reg->system_p) | |
277 | return 1; | |
278 | ||
279 | /* Since the m32c DWARF register numbers refer to cooked registers, not | |
280 | raw registers, and frame_pop depends on the save and restore groups | |
281 | containing registers the DWARF CFI will actually mention, our save | |
282 | and restore groups are cooked registers, not raw registers. (This is | |
283 | why we can't use the default reggroup function.) */ | |
284 | if ((group == save_reggroup | |
285 | || group == restore_reggroup) | |
286 | && reg->save_restore_p) | |
287 | return 1; | |
288 | ||
289 | return 0; | |
290 | } | |
291 | ||
292 | ||
293 | /* Register move functions. We declare them here using | |
6da660c7 SM |
294 | m32c_{read,write}_reg_t to check the types. */ |
295 | static m32c_read_reg_t m32c_raw_read; | |
296 | static m32c_read_reg_t m32c_banked_read; | |
297 | static m32c_read_reg_t m32c_sb_read; | |
298 | static m32c_read_reg_t m32c_part_read; | |
299 | static m32c_read_reg_t m32c_cat_read; | |
300 | static m32c_read_reg_t m32c_r3r2r1r0_read; | |
301 | ||
302 | static m32c_write_reg_t m32c_raw_write; | |
303 | static m32c_write_reg_t m32c_banked_write; | |
304 | static m32c_write_reg_t m32c_sb_write; | |
305 | static m32c_write_reg_t m32c_part_write; | |
306 | static m32c_write_reg_t m32c_cat_write; | |
307 | static m32c_write_reg_t m32c_r3r2r1r0_write; | |
96309189 MS |
308 | |
309 | /* Copy the value of the raw register REG from CACHE to BUF. */ | |
05d1431c | 310 | static enum register_status |
849d0ba8 | 311 | m32c_raw_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 | 312 | { |
03f50fc8 | 313 | return cache->raw_read (reg->num, buf); |
96309189 MS |
314 | } |
315 | ||
316 | ||
317 | /* Copy the value of the raw register REG from BUF to CACHE. */ | |
05d1431c | 318 | static enum register_status |
6da660c7 SM |
319 | m32c_raw_write (struct m32c_reg *reg, struct regcache *cache, |
320 | const gdb_byte *buf) | |
96309189 | 321 | { |
10eaee5f | 322 | cache->raw_write (reg->num, buf); |
05d1431c PA |
323 | |
324 | return REG_VALID; | |
96309189 MS |
325 | } |
326 | ||
327 | ||
328 | /* Return the value of the 'flg' register in CACHE. */ | |
329 | static int | |
849d0ba8 | 330 | m32c_read_flg (readable_regcache *cache) |
96309189 | 331 | { |
345bd07c SM |
332 | gdbarch *arch = cache->arch (); |
333 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
96309189 | 334 | ULONGEST flg; |
03f50fc8 YQ |
335 | |
336 | cache->raw_read (tdep->flg->num, &flg); | |
96309189 MS |
337 | return flg & 0xffff; |
338 | } | |
339 | ||
340 | ||
7830cb4f CV |
341 | /* Evaluate the real register number of a banked register. */ |
342 | static struct m32c_reg * | |
849d0ba8 | 343 | m32c_banked_register (struct m32c_reg *reg, readable_regcache *cache) |
7830cb4f CV |
344 | { |
345 | return ((m32c_read_flg (cache) & reg->n) ? reg->ry : reg->rx); | |
346 | } | |
347 | ||
348 | ||
96309189 MS |
349 | /* Move the value of a banked register from CACHE to BUF. |
350 | If the value of the 'flg' register in CACHE has any of the bits | |
351 | masked in REG->n set, then read REG->ry. Otherwise, read | |
352 | REG->rx. */ | |
05d1431c | 353 | static enum register_status |
849d0ba8 | 354 | m32c_banked_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 | 355 | { |
7830cb4f | 356 | struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); |
03f50fc8 | 357 | return cache->raw_read (bank_reg->num, buf); |
96309189 MS |
358 | } |
359 | ||
360 | ||
361 | /* Move the value of a banked register from BUF to CACHE. | |
362 | If the value of the 'flg' register in CACHE has any of the bits | |
363 | masked in REG->n set, then write REG->ry. Otherwise, write | |
364 | REG->rx. */ | |
05d1431c | 365 | static enum register_status |
6da660c7 SM |
366 | m32c_banked_write (struct m32c_reg *reg, struct regcache *cache, |
367 | const gdb_byte *buf) | |
96309189 | 368 | { |
7830cb4f | 369 | struct m32c_reg *bank_reg = m32c_banked_register (reg, cache); |
10eaee5f | 370 | cache->raw_write (bank_reg->num, buf); |
05d1431c PA |
371 | |
372 | return REG_VALID; | |
96309189 MS |
373 | } |
374 | ||
375 | ||
376 | /* Move the value of SB from CACHE to BUF. On bfd_mach_m32c, SB is a | |
377 | banked register; on bfd_mach_m16c, it's not. */ | |
05d1431c | 378 | static enum register_status |
849d0ba8 | 379 | m32c_sb_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 MS |
380 | { |
381 | if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) | |
05d1431c | 382 | return m32c_raw_read (reg->rx, cache, buf); |
96309189 | 383 | else |
05d1431c | 384 | return m32c_banked_read (reg, cache, buf); |
96309189 MS |
385 | } |
386 | ||
387 | ||
388 | /* Move the value of SB from BUF to CACHE. On bfd_mach_m32c, SB is a | |
389 | banked register; on bfd_mach_m16c, it's not. */ | |
05d1431c | 390 | static enum register_status |
6da660c7 | 391 | m32c_sb_write (struct m32c_reg *reg, struct regcache *cache, const gdb_byte *buf) |
96309189 MS |
392 | { |
393 | if (gdbarch_bfd_arch_info (reg->arch)->mach == bfd_mach_m16c) | |
394 | m32c_raw_write (reg->rx, cache, buf); | |
395 | else | |
396 | m32c_banked_write (reg, cache, buf); | |
05d1431c PA |
397 | |
398 | return REG_VALID; | |
96309189 MS |
399 | } |
400 | ||
401 | ||
402 | /* Assuming REG uses m32c_part_read and m32c_part_write, set *OFFSET_P | |
403 | and *LEN_P to the offset and length, in bytes, of the part REG | |
404 | occupies in its underlying register. The offset is from the | |
405 | lower-addressed end, regardless of the architecture's endianness. | |
406 | (The M32C family is always little-endian, but let's keep those | |
407 | assumptions out of here.) */ | |
408 | static void | |
409 | m32c_find_part (struct m32c_reg *reg, int *offset_p, int *len_p) | |
410 | { | |
411 | /* The length of the containing register, of which REG is one part. */ | |
412 | int containing_len = TYPE_LENGTH (reg->rx->type); | |
413 | ||
414 | /* The length of one "element" in our imaginary array. */ | |
415 | int elt_len = TYPE_LENGTH (reg->type); | |
416 | ||
417 | /* The offset of REG's "element" from the least significant end of | |
418 | the containing register. */ | |
419 | int elt_offset = reg->n * elt_len; | |
420 | ||
421 | /* If we extend off the end, trim the length of the element. */ | |
422 | if (elt_offset + elt_len > containing_len) | |
423 | { | |
424 | elt_len = containing_len - elt_offset; | |
425 | /* We shouldn't be declaring partial registers that go off the | |
426 | end of their containing registers. */ | |
427 | gdb_assert (elt_len > 0); | |
428 | } | |
429 | ||
430 | /* Flip the offset around if we're big-endian. */ | |
431 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) | |
432 | elt_offset = TYPE_LENGTH (reg->rx->type) - elt_offset - elt_len; | |
433 | ||
434 | *offset_p = elt_offset; | |
435 | *len_p = elt_len; | |
436 | } | |
437 | ||
438 | ||
439 | /* Move the value of a partial register (r0h, intbl, etc.) from CACHE | |
440 | to BUF. Treating the value of the register REG->rx as an array of | |
441 | REG->type values, where higher indices refer to more significant | |
442 | bits, read the value of the REG->n'th element. */ | |
05d1431c | 443 | static enum register_status |
849d0ba8 | 444 | m32c_part_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 MS |
445 | { |
446 | int offset, len; | |
05d1431c | 447 | |
96309189 MS |
448 | memset (buf, 0, TYPE_LENGTH (reg->type)); |
449 | m32c_find_part (reg, &offset, &len); | |
03f50fc8 | 450 | return cache->cooked_read_part (reg->rx->num, offset, len, buf); |
96309189 MS |
451 | } |
452 | ||
453 | ||
454 | /* Move the value of a banked register from BUF to CACHE. | |
455 | Treating the value of the register REG->rx as an array of REG->type | |
456 | values, where higher indices refer to more significant bits, write | |
457 | the value of the REG->n'th element. */ | |
05d1431c | 458 | static enum register_status |
6da660c7 SM |
459 | m32c_part_write (struct m32c_reg *reg, struct regcache *cache, |
460 | const gdb_byte *buf) | |
96309189 MS |
461 | { |
462 | int offset, len; | |
05d1431c | 463 | |
96309189 | 464 | m32c_find_part (reg, &offset, &len); |
e4c4a59b | 465 | cache->cooked_write_part (reg->rx->num, offset, len, buf); |
05d1431c PA |
466 | |
467 | return REG_VALID; | |
96309189 MS |
468 | } |
469 | ||
470 | ||
471 | /* Move the value of REG from CACHE to BUF. REG's value is the | |
472 | concatenation of the values of the registers REG->rx and REG->ry, | |
473 | with REG->rx contributing the more significant bits. */ | |
05d1431c | 474 | static enum register_status |
849d0ba8 | 475 | m32c_cat_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 MS |
476 | { |
477 | int high_bytes = TYPE_LENGTH (reg->rx->type); | |
478 | int low_bytes = TYPE_LENGTH (reg->ry->type); | |
05d1431c | 479 | enum register_status status; |
96309189 MS |
480 | |
481 | gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes); | |
482 | ||
483 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) | |
484 | { | |
11f57cb6 | 485 | status = cache->cooked_read (reg->rx->num, buf); |
05d1431c | 486 | if (status == REG_VALID) |
11f57cb6 | 487 | status = cache->cooked_read (reg->ry->num, buf + high_bytes); |
96309189 MS |
488 | } |
489 | else | |
490 | { | |
11f57cb6 | 491 | status = cache->cooked_read (reg->rx->num, buf + low_bytes); |
05d1431c | 492 | if (status == REG_VALID) |
11f57cb6 | 493 | status = cache->cooked_read (reg->ry->num, buf); |
96309189 | 494 | } |
05d1431c | 495 | return status; |
96309189 MS |
496 | } |
497 | ||
498 | ||
499 | /* Move the value of REG from CACHE to BUF. REG's value is the | |
500 | concatenation of the values of the registers REG->rx and REG->ry, | |
501 | with REG->rx contributing the more significant bits. */ | |
05d1431c | 502 | static enum register_status |
6da660c7 SM |
503 | m32c_cat_write (struct m32c_reg *reg, struct regcache *cache, |
504 | const gdb_byte *buf) | |
96309189 MS |
505 | { |
506 | int high_bytes = TYPE_LENGTH (reg->rx->type); | |
507 | int low_bytes = TYPE_LENGTH (reg->ry->type); | |
96309189 MS |
508 | |
509 | gdb_assert (TYPE_LENGTH (reg->type) == high_bytes + low_bytes); | |
510 | ||
511 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) | |
512 | { | |
b66f5587 SM |
513 | cache->cooked_write (reg->rx->num, buf); |
514 | cache->cooked_write (reg->ry->num, buf + high_bytes); | |
96309189 MS |
515 | } |
516 | else | |
517 | { | |
b66f5587 SM |
518 | cache->cooked_write (reg->rx->num, buf + low_bytes); |
519 | cache->cooked_write (reg->ry->num, buf); | |
96309189 | 520 | } |
05d1431c PA |
521 | |
522 | return REG_VALID; | |
96309189 MS |
523 | } |
524 | ||
525 | ||
526 | /* Copy the value of the raw register REG from CACHE to BUF. REG is | |
527 | the concatenation (from most significant to least) of r3, r2, r1, | |
528 | and r0. */ | |
05d1431c | 529 | static enum register_status |
849d0ba8 | 530 | m32c_r3r2r1r0_read (struct m32c_reg *reg, readable_regcache *cache, gdb_byte *buf) |
96309189 | 531 | { |
345bd07c SM |
532 | gdbarch *arch = reg->arch; |
533 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
96309189 | 534 | int len = TYPE_LENGTH (tdep->r0->type); |
05d1431c | 535 | enum register_status status; |
96309189 | 536 | |
96309189 MS |
537 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) |
538 | { | |
11f57cb6 | 539 | status = cache->cooked_read (tdep->r0->num, buf + len * 3); |
05d1431c | 540 | if (status == REG_VALID) |
11f57cb6 | 541 | status = cache->cooked_read (tdep->r1->num, buf + len * 2); |
05d1431c | 542 | if (status == REG_VALID) |
11f57cb6 | 543 | status = cache->cooked_read (tdep->r2->num, buf + len * 1); |
05d1431c | 544 | if (status == REG_VALID) |
11f57cb6 | 545 | status = cache->cooked_read (tdep->r3->num, buf); |
96309189 MS |
546 | } |
547 | else | |
548 | { | |
11f57cb6 | 549 | status = cache->cooked_read (tdep->r0->num, buf); |
05d1431c | 550 | if (status == REG_VALID) |
11f57cb6 | 551 | status = cache->cooked_read (tdep->r1->num, buf + len * 1); |
05d1431c | 552 | if (status == REG_VALID) |
11f57cb6 | 553 | status = cache->cooked_read (tdep->r2->num, buf + len * 2); |
05d1431c | 554 | if (status == REG_VALID) |
11f57cb6 | 555 | status = cache->cooked_read (tdep->r3->num, buf + len * 3); |
96309189 | 556 | } |
05d1431c PA |
557 | |
558 | return status; | |
96309189 MS |
559 | } |
560 | ||
561 | ||
562 | /* Copy the value of the raw register REG from BUF to CACHE. REG is | |
563 | the concatenation (from most significant to least) of r3, r2, r1, | |
564 | and r0. */ | |
05d1431c | 565 | static enum register_status |
6da660c7 SM |
566 | m32c_r3r2r1r0_write (struct m32c_reg *reg, struct regcache *cache, |
567 | const gdb_byte *buf) | |
96309189 | 568 | { |
345bd07c SM |
569 | gdbarch *arch = reg->arch; |
570 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
96309189 MS |
571 | int len = TYPE_LENGTH (tdep->r0->type); |
572 | ||
96309189 MS |
573 | if (gdbarch_byte_order (reg->arch) == BFD_ENDIAN_BIG) |
574 | { | |
b66f5587 SM |
575 | cache->cooked_write (tdep->r0->num, buf + len * 3); |
576 | cache->cooked_write (tdep->r1->num, buf + len * 2); | |
577 | cache->cooked_write (tdep->r2->num, buf + len * 1); | |
578 | cache->cooked_write (tdep->r3->num, buf); | |
96309189 MS |
579 | } |
580 | else | |
581 | { | |
b66f5587 SM |
582 | cache->cooked_write (tdep->r0->num, buf); |
583 | cache->cooked_write (tdep->r1->num, buf + len * 1); | |
584 | cache->cooked_write (tdep->r2->num, buf + len * 2); | |
585 | cache->cooked_write (tdep->r3->num, buf + len * 3); | |
96309189 | 586 | } |
05d1431c PA |
587 | |
588 | return REG_VALID; | |
96309189 MS |
589 | } |
590 | ||
591 | ||
05d1431c | 592 | static enum register_status |
96309189 | 593 | m32c_pseudo_register_read (struct gdbarch *arch, |
849d0ba8 | 594 | readable_regcache *cache, |
96309189 MS |
595 | int cookednum, |
596 | gdb_byte *buf) | |
597 | { | |
345bd07c | 598 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); |
96309189 MS |
599 | struct m32c_reg *reg; |
600 | ||
601 | gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); | |
ac7936df | 602 | gdb_assert (arch == cache->arch ()); |
96309189 MS |
603 | gdb_assert (arch == tdep->regs[cookednum].arch); |
604 | reg = &tdep->regs[cookednum]; | |
605 | ||
05d1431c | 606 | return reg->read (reg, cache, buf); |
96309189 MS |
607 | } |
608 | ||
609 | ||
610 | static void | |
611 | m32c_pseudo_register_write (struct gdbarch *arch, | |
612 | struct regcache *cache, | |
613 | int cookednum, | |
614 | const gdb_byte *buf) | |
615 | { | |
345bd07c | 616 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); |
96309189 MS |
617 | struct m32c_reg *reg; |
618 | ||
619 | gdb_assert (0 <= cookednum && cookednum < tdep->num_regs); | |
ac7936df | 620 | gdb_assert (arch == cache->arch ()); |
96309189 MS |
621 | gdb_assert (arch == tdep->regs[cookednum].arch); |
622 | reg = &tdep->regs[cookednum]; | |
623 | ||
6da660c7 | 624 | reg->write (reg, cache, buf); |
96309189 MS |
625 | } |
626 | ||
627 | ||
628 | /* Add a register with the given fields to the end of ARCH's table. | |
629 | Return a pointer to the newly added register. */ | |
630 | static struct m32c_reg * | |
631 | add_reg (struct gdbarch *arch, | |
632 | const char *name, | |
633 | struct type *type, | |
634 | int sim_num, | |
6da660c7 SM |
635 | m32c_read_reg_t *read, |
636 | m32c_write_reg_t *write, | |
96309189 MS |
637 | struct m32c_reg *rx, |
638 | struct m32c_reg *ry, | |
639 | int n) | |
640 | { | |
345bd07c | 641 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); |
96309189 MS |
642 | struct m32c_reg *r = &tdep->regs[tdep->num_regs]; |
643 | ||
644 | gdb_assert (tdep->num_regs < M32C_MAX_NUM_REGS); | |
645 | ||
646 | r->name = name; | |
647 | r->type = type; | |
648 | r->arch = arch; | |
649 | r->num = tdep->num_regs; | |
650 | r->sim_num = sim_num; | |
651 | r->dwarf_num = -1; | |
652 | r->general_p = 0; | |
653 | r->dma_p = 0; | |
654 | r->system_p = 0; | |
655 | r->save_restore_p = 0; | |
656 | r->read = read; | |
657 | r->write = write; | |
658 | r->rx = rx; | |
659 | r->ry = ry; | |
660 | r->n = n; | |
661 | ||
662 | tdep->num_regs++; | |
663 | ||
664 | return r; | |
665 | } | |
666 | ||
667 | ||
668 | /* Record NUM as REG's DWARF register number. */ | |
669 | static void | |
670 | set_dwarf_regnum (struct m32c_reg *reg, int num) | |
671 | { | |
672 | gdb_assert (num < M32C_MAX_NUM_REGS); | |
673 | ||
674 | /* Update the reg->DWARF mapping. Only count the first number | |
675 | assigned to this register. */ | |
676 | if (reg->dwarf_num == -1) | |
677 | reg->dwarf_num = num; | |
678 | ||
679 | /* Update the DWARF->reg mapping. */ | |
345bd07c SM |
680 | gdbarch *arch = reg->arch; |
681 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
682 | tdep->dwarf_regs[num] = reg; | |
96309189 MS |
683 | } |
684 | ||
685 | ||
686 | /* Mark REG as a general-purpose register, and return it. */ | |
687 | static struct m32c_reg * | |
688 | mark_general (struct m32c_reg *reg) | |
689 | { | |
690 | reg->general_p = 1; | |
691 | return reg; | |
692 | } | |
693 | ||
694 | ||
374fd1fd TT |
695 | /* Mark REG as a DMA register. */ |
696 | static void | |
96309189 MS |
697 | mark_dma (struct m32c_reg *reg) |
698 | { | |
699 | reg->dma_p = 1; | |
96309189 MS |
700 | } |
701 | ||
702 | ||
703 | /* Mark REG as a SYSTEM register, and return it. */ | |
704 | static struct m32c_reg * | |
705 | mark_system (struct m32c_reg *reg) | |
706 | { | |
707 | reg->system_p = 1; | |
708 | return reg; | |
709 | } | |
710 | ||
711 | ||
712 | /* Mark REG as a save-restore register, and return it. */ | |
713 | static struct m32c_reg * | |
714 | mark_save_restore (struct m32c_reg *reg) | |
715 | { | |
716 | reg->save_restore_p = 1; | |
717 | return reg; | |
718 | } | |
719 | ||
720 | ||
721 | #define FLAGBIT_B 0x0010 | |
722 | #define FLAGBIT_U 0x0080 | |
723 | ||
724 | /* Handy macros for declaring registers. These all evaluate to | |
725 | pointers to the register declared. Macros that define two | |
726 | registers evaluate to a pointer to the first. */ | |
727 | ||
728 | /* A raw register named NAME, with type TYPE and sim number SIM_NUM. */ | |
729 | #define R(name, type, sim_num) \ | |
730 | (add_reg (arch, (name), (type), (sim_num), \ | |
731 | m32c_raw_read, m32c_raw_write, NULL, NULL, 0)) | |
732 | ||
733 | /* The simulator register number for a raw register named NAME. */ | |
734 | #define SIM(name) (m32c_sim_reg_ ## name) | |
735 | ||
736 | /* A raw unsigned 16-bit data register named NAME. | |
737 | NAME should be an identifier, not a string. */ | |
738 | #define R16U(name) \ | |
739 | (R(#name, tdep->uint16, SIM (name))) | |
740 | ||
741 | /* A raw data address register named NAME. | |
742 | NAME should be an identifier, not a string. */ | |
743 | #define RA(name) \ | |
744 | (R(#name, tdep->data_addr_reg_type, SIM (name))) | |
745 | ||
746 | /* A raw code address register named NAME. NAME should | |
747 | be an identifier, not a string. */ | |
748 | #define RC(name) \ | |
749 | (R(#name, tdep->code_addr_reg_type, SIM (name))) | |
750 | ||
751 | /* A pair of raw registers named NAME0 and NAME1, with type TYPE. | |
752 | NAME should be an identifier, not a string. */ | |
753 | #define RP(name, type) \ | |
754 | (R(#name "0", (type), SIM (name ## 0)), \ | |
755 | R(#name "1", (type), SIM (name ## 1)) - 1) | |
756 | ||
757 | /* A raw banked general-purpose data register named NAME. | |
758 | NAME should be an identifier, not a string. */ | |
759 | #define RBD(name) \ | |
760 | (R(NULL, tdep->int16, SIM (name ## _bank0)), \ | |
761 | R(NULL, tdep->int16, SIM (name ## _bank1)) - 1) | |
762 | ||
763 | /* A raw banked data address register named NAME. | |
764 | NAME should be an identifier, not a string. */ | |
765 | #define RBA(name) \ | |
766 | (R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank0)), \ | |
767 | R(NULL, tdep->data_addr_reg_type, SIM (name ## _bank1)) - 1) | |
768 | ||
769 | /* A cooked register named NAME referring to a raw banked register | |
770 | from the bank selected by the current value of FLG. RAW_PAIR | |
771 | should be a pointer to the first register in the banked pair. | |
772 | NAME must be an identifier, not a string. */ | |
773 | #define CB(name, raw_pair) \ | |
774 | (add_reg (arch, #name, (raw_pair)->type, 0, \ | |
775 | m32c_banked_read, m32c_banked_write, \ | |
dda83cd7 | 776 | (raw_pair), (raw_pair + 1), FLAGBIT_B)) |
96309189 MS |
777 | |
778 | /* A pair of registers named NAMEH and NAMEL, of type TYPE, that | |
779 | access the top and bottom halves of the register pointed to by | |
780 | NAME. NAME should be an identifier. */ | |
781 | #define CHL(name, type) \ | |
782 | (add_reg (arch, #name "h", (type), 0, \ | |
783 | m32c_part_read, m32c_part_write, name, NULL, 1), \ | |
784 | add_reg (arch, #name "l", (type), 0, \ | |
785 | m32c_part_read, m32c_part_write, name, NULL, 0) - 1) | |
786 | ||
787 | /* A register constructed by concatenating the two registers HIGH and | |
788 | LOW, whose name is HIGHLOW and whose type is TYPE. */ | |
789 | #define CCAT(high, low, type) \ | |
790 | (add_reg (arch, #high #low, (type), 0, \ | |
791 | m32c_cat_read, m32c_cat_write, (high), (low), 0)) | |
792 | ||
793 | /* Abbreviations for marking register group membership. */ | |
794 | #define G(reg) (mark_general (reg)) | |
795 | #define S(reg) (mark_system (reg)) | |
796 | #define DMA(reg) (mark_dma (reg)) | |
797 | ||
798 | ||
799 | /* Construct the register set for ARCH. */ | |
800 | static void | |
801 | make_regs (struct gdbarch *arch) | |
802 | { | |
345bd07c | 803 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); |
96309189 | 804 | int mach = gdbarch_bfd_arch_info (arch)->mach; |
f79b9530 DJ |
805 | int num_raw_regs; |
806 | int num_cooked_regs; | |
807 | ||
808 | struct m32c_reg *r0; | |
809 | struct m32c_reg *r1; | |
810 | struct m32c_reg *r2; | |
811 | struct m32c_reg *r3; | |
812 | struct m32c_reg *a0; | |
813 | struct m32c_reg *a1; | |
814 | struct m32c_reg *fb; | |
815 | struct m32c_reg *sb; | |
816 | struct m32c_reg *sp; | |
817 | struct m32c_reg *r0hl; | |
818 | struct m32c_reg *r1hl; | |
f79b9530 DJ |
819 | struct m32c_reg *r2r0; |
820 | struct m32c_reg *r3r1; | |
821 | struct m32c_reg *r3r1r2r0; | |
822 | struct m32c_reg *r3r2r1r0; | |
823 | struct m32c_reg *a1a0; | |
96309189 MS |
824 | |
825 | struct m32c_reg *raw_r0_pair = RBD (r0); | |
826 | struct m32c_reg *raw_r1_pair = RBD (r1); | |
827 | struct m32c_reg *raw_r2_pair = RBD (r2); | |
828 | struct m32c_reg *raw_r3_pair = RBD (r3); | |
829 | struct m32c_reg *raw_a0_pair = RBA (a0); | |
830 | struct m32c_reg *raw_a1_pair = RBA (a1); | |
831 | struct m32c_reg *raw_fb_pair = RBA (fb); | |
832 | ||
833 | /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. | |
834 | We always declare both raw registers, and deal with the distinction | |
835 | in the pseudoregister. */ | |
836 | struct m32c_reg *raw_sb_pair = RBA (sb); | |
837 | ||
838 | struct m32c_reg *usp = S (RA (usp)); | |
839 | struct m32c_reg *isp = S (RA (isp)); | |
840 | struct m32c_reg *intb = S (RC (intb)); | |
841 | struct m32c_reg *pc = G (RC (pc)); | |
842 | struct m32c_reg *flg = G (R16U (flg)); | |
843 | ||
844 | if (mach == bfd_mach_m32c) | |
845 | { | |
374fd1fd TT |
846 | S (R16U (svf)); |
847 | S (RC (svp)); | |
848 | S (RC (vct)); | |
849 | ||
850 | DMA (RP (dmd, tdep->uint8)); | |
851 | DMA (RP (dct, tdep->uint16)); | |
852 | DMA (RP (drc, tdep->uint16)); | |
853 | DMA (RP (dma, tdep->data_addr_reg_type)); | |
854 | DMA (RP (dsa, tdep->data_addr_reg_type)); | |
855 | DMA (RP (dra, tdep->data_addr_reg_type)); | |
96309189 MS |
856 | } |
857 | ||
f79b9530 | 858 | num_raw_regs = tdep->num_regs; |
96309189 | 859 | |
f79b9530 DJ |
860 | r0 = G (CB (r0, raw_r0_pair)); |
861 | r1 = G (CB (r1, raw_r1_pair)); | |
862 | r2 = G (CB (r2, raw_r2_pair)); | |
863 | r3 = G (CB (r3, raw_r3_pair)); | |
864 | a0 = G (CB (a0, raw_a0_pair)); | |
865 | a1 = G (CB (a1, raw_a1_pair)); | |
866 | fb = G (CB (fb, raw_fb_pair)); | |
96309189 MS |
867 | |
868 | /* sb is banked on the bfd_mach_m32c, but not on bfd_mach_m16c. | |
869 | Specify custom read/write functions that do the right thing. */ | |
f79b9530 DJ |
870 | sb = G (add_reg (arch, "sb", raw_sb_pair->type, 0, |
871 | m32c_sb_read, m32c_sb_write, | |
872 | raw_sb_pair, raw_sb_pair + 1, 0)); | |
96309189 MS |
873 | |
874 | /* The current sp is either usp or isp, depending on the value of | |
875 | the FLG register's U bit. */ | |
f79b9530 DJ |
876 | sp = G (add_reg (arch, "sp", usp->type, 0, |
877 | m32c_banked_read, m32c_banked_write, | |
878 | isp, usp, FLAGBIT_U)); | |
96309189 | 879 | |
f79b9530 DJ |
880 | r0hl = CHL (r0, tdep->int8); |
881 | r1hl = CHL (r1, tdep->int8); | |
ac298888 TT |
882 | CHL (r2, tdep->int8); |
883 | CHL (r3, tdep->int8); | |
884 | CHL (intb, tdep->int16); | |
96309189 | 885 | |
f79b9530 DJ |
886 | r2r0 = CCAT (r2, r0, tdep->int32); |
887 | r3r1 = CCAT (r3, r1, tdep->int32); | |
888 | r3r1r2r0 = CCAT (r3r1, r2r0, tdep->int64); | |
96309189 | 889 | |
f79b9530 | 890 | r3r2r1r0 |
96309189 MS |
891 | = add_reg (arch, "r3r2r1r0", tdep->int64, 0, |
892 | m32c_r3r2r1r0_read, m32c_r3r2r1r0_write, NULL, NULL, 0); | |
893 | ||
96309189 MS |
894 | if (mach == bfd_mach_m16c) |
895 | a1a0 = CCAT (a1, a0, tdep->int32); | |
896 | else | |
897 | a1a0 = NULL; | |
898 | ||
f79b9530 | 899 | num_cooked_regs = tdep->num_regs - num_raw_regs; |
96309189 MS |
900 | |
901 | tdep->pc = pc; | |
902 | tdep->flg = flg; | |
903 | tdep->r0 = r0; | |
904 | tdep->r1 = r1; | |
905 | tdep->r2 = r2; | |
906 | tdep->r3 = r3; | |
907 | tdep->r2r0 = r2r0; | |
908 | tdep->r3r2r1r0 = r3r2r1r0; | |
909 | tdep->r3r1r2r0 = r3r1r2r0; | |
910 | tdep->a0 = a0; | |
911 | tdep->a1 = a1; | |
912 | tdep->sb = sb; | |
913 | tdep->fb = fb; | |
914 | tdep->sp = sp; | |
915 | ||
916 | /* Set up the DWARF register table. */ | |
917 | memset (tdep->dwarf_regs, 0, sizeof (tdep->dwarf_regs)); | |
918 | set_dwarf_regnum (r0hl + 1, 0x01); | |
919 | set_dwarf_regnum (r0hl + 0, 0x02); | |
920 | set_dwarf_regnum (r1hl + 1, 0x03); | |
921 | set_dwarf_regnum (r1hl + 0, 0x04); | |
922 | set_dwarf_regnum (r0, 0x05); | |
923 | set_dwarf_regnum (r1, 0x06); | |
924 | set_dwarf_regnum (r2, 0x07); | |
925 | set_dwarf_regnum (r3, 0x08); | |
926 | set_dwarf_regnum (a0, 0x09); | |
927 | set_dwarf_regnum (a1, 0x0a); | |
928 | set_dwarf_regnum (fb, 0x0b); | |
929 | set_dwarf_regnum (sp, 0x0c); | |
930 | set_dwarf_regnum (pc, 0x0d); /* GCC's invention */ | |
931 | set_dwarf_regnum (sb, 0x13); | |
932 | set_dwarf_regnum (r2r0, 0x15); | |
933 | set_dwarf_regnum (r3r1, 0x16); | |
934 | if (a1a0) | |
935 | set_dwarf_regnum (a1a0, 0x17); | |
936 | ||
937 | /* Enumerate the save/restore register group. | |
938 | ||
939 | The regcache_save and regcache_restore functions apply their read | |
940 | function to each register in this group. | |
941 | ||
942 | Since frame_pop supplies frame_unwind_register as its read | |
943 | function, the registers meaningful to the Dwarf unwinder need to | |
944 | be in this group. | |
945 | ||
946 | On the other hand, when we make inferior calls, save_inferior_status | |
947 | and restore_inferior_status use them to preserve the current register | |
948 | values across the inferior call. For this, you'd kind of like to | |
949 | preserve all the raw registers, to protect the interrupted code from | |
950 | any sort of bank switching the callee might have done. But we handle | |
951 | those cases so badly anyway --- for example, it matters whether we | |
952 | restore FLG before or after we restore the general-purpose registers, | |
953 | but there's no way to express that --- that it isn't worth worrying | |
954 | about. | |
955 | ||
956 | We omit control registers like inthl: if you call a function that | |
957 | changes those, it's probably because you wanted that change to be | |
958 | visible to the interrupted code. */ | |
959 | mark_save_restore (r0); | |
960 | mark_save_restore (r1); | |
961 | mark_save_restore (r2); | |
962 | mark_save_restore (r3); | |
963 | mark_save_restore (a0); | |
964 | mark_save_restore (a1); | |
965 | mark_save_restore (sb); | |
966 | mark_save_restore (fb); | |
967 | mark_save_restore (sp); | |
968 | mark_save_restore (pc); | |
969 | mark_save_restore (flg); | |
970 | ||
971 | set_gdbarch_num_regs (arch, num_raw_regs); | |
972 | set_gdbarch_num_pseudo_regs (arch, num_cooked_regs); | |
973 | set_gdbarch_pc_regnum (arch, pc->num); | |
974 | set_gdbarch_sp_regnum (arch, sp->num); | |
975 | set_gdbarch_register_name (arch, m32c_register_name); | |
976 | set_gdbarch_register_type (arch, m32c_register_type); | |
977 | set_gdbarch_pseudo_register_read (arch, m32c_pseudo_register_read); | |
978 | set_gdbarch_pseudo_register_write (arch, m32c_pseudo_register_write); | |
979 | set_gdbarch_register_sim_regno (arch, m32c_register_sim_regno); | |
980 | set_gdbarch_stab_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); | |
96309189 MS |
981 | set_gdbarch_dwarf2_reg_to_regnum (arch, m32c_debug_info_reg_to_regnum); |
982 | set_gdbarch_register_reggroup_p (arch, m32c_register_reggroup_p); | |
983 | ||
984 | reggroup_add (arch, general_reggroup); | |
985 | reggroup_add (arch, all_reggroup); | |
986 | reggroup_add (arch, save_reggroup); | |
987 | reggroup_add (arch, restore_reggroup); | |
988 | reggroup_add (arch, system_reggroup); | |
989 | reggroup_add (arch, m32c_dma_reggroup); | |
990 | } | |
991 | ||
992 | ||
993 | \f | |
994 | /* Breakpoints. */ | |
04180708 | 995 | constexpr gdb_byte m32c_break_insn[] = { 0x00 }; /* brk */ |
96309189 | 996 | |
04180708 | 997 | typedef BP_MANIPULATION (m32c_break_insn) m32c_breakpoint; |
96309189 MS |
998 | |
999 | \f | |
1000 | /* Prologue analysis. */ | |
1001 | ||
52059ffd TT |
1002 | enum m32c_prologue_kind |
1003 | { | |
1004 | /* This function uses a frame pointer. */ | |
1005 | prologue_with_frame_ptr, | |
1006 | ||
1007 | /* This function has no frame pointer. */ | |
1008 | prologue_sans_frame_ptr, | |
1009 | ||
1010 | /* This function sets up the stack, so its frame is the first | |
1011 | frame on the stack. */ | |
1012 | prologue_first_frame | |
1013 | }; | |
1014 | ||
96309189 MS |
1015 | struct m32c_prologue |
1016 | { | |
1017 | /* For consistency with the DWARF 2 .debug_frame info generated by | |
1018 | GCC, a frame's CFA is the address immediately after the saved | |
1019 | return address. */ | |
1020 | ||
1021 | /* The architecture for which we generated this prologue info. */ | |
1022 | struct gdbarch *arch; | |
1023 | ||
52059ffd | 1024 | enum m32c_prologue_kind kind; |
96309189 MS |
1025 | |
1026 | /* If KIND is prologue_with_frame_ptr, this is the offset from the | |
1027 | CFA to where the frame pointer points. This is always zero or | |
1028 | negative. */ | |
1029 | LONGEST frame_ptr_offset; | |
1030 | ||
1031 | /* If KIND is prologue_sans_frame_ptr, the offset from the CFA to | |
1032 | the stack pointer --- always zero or negative. | |
1033 | ||
1034 | Calling this a "size" is a bit misleading, but given that the | |
1035 | stack grows downwards, using offsets for everything keeps one | |
1036 | from going completely sign-crazy: you never change anything's | |
1037 | sign for an ADD instruction; always change the second operand's | |
1038 | sign for a SUB instruction; and everything takes care of | |
1039 | itself. | |
1040 | ||
1041 | Functions that use alloca don't have a constant frame size. But | |
1042 | they always have frame pointers, so we must use that to find the | |
1043 | CFA (and perhaps to unwind the stack pointer). */ | |
1044 | LONGEST frame_size; | |
1045 | ||
1046 | /* The address of the first instruction at which the frame has been | |
1047 | set up and the arguments are where the debug info says they are | |
1048 | --- as best as we can tell. */ | |
1049 | CORE_ADDR prologue_end; | |
1050 | ||
1051 | /* reg_offset[R] is the offset from the CFA at which register R is | |
1052 | saved, or 1 if register R has not been saved. (Real values are | |
1053 | always zero or negative.) */ | |
1054 | LONGEST reg_offset[M32C_MAX_NUM_REGS]; | |
1055 | }; | |
1056 | ||
1057 | ||
1058 | /* The longest I've seen, anyway. */ | |
1059 | #define M32C_MAX_INSN_LEN (9) | |
1060 | ||
1061 | /* Processor state, for the prologue analyzer. */ | |
1062 | struct m32c_pv_state | |
1063 | { | |
1064 | struct gdbarch *arch; | |
1065 | pv_t r0, r1, r2, r3; | |
1066 | pv_t a0, a1; | |
1067 | pv_t sb, fb, sp; | |
1068 | pv_t pc; | |
1069 | struct pv_area *stack; | |
1070 | ||
1071 | /* Bytes from the current PC, the address they were read from, | |
1072 | and the address of the next unconsumed byte. */ | |
1073 | gdb_byte insn[M32C_MAX_INSN_LEN]; | |
1074 | CORE_ADDR scan_pc, next_addr; | |
1075 | }; | |
1076 | ||
1077 | ||
1078 | /* Push VALUE on STATE's stack, occupying SIZE bytes. Return zero if | |
1079 | all went well, or non-zero if simulating the action would trash our | |
1080 | state. */ | |
1081 | static int | |
1082 | m32c_pv_push (struct m32c_pv_state *state, pv_t value, int size) | |
1083 | { | |
f7b7ed97 | 1084 | if (state->stack->store_would_trash (state->sp)) |
96309189 MS |
1085 | return 1; |
1086 | ||
1087 | state->sp = pv_add_constant (state->sp, -size); | |
f7b7ed97 | 1088 | state->stack->store (state->sp, size, value); |
96309189 MS |
1089 | |
1090 | return 0; | |
1091 | } | |
1092 | ||
1093 | ||
52059ffd TT |
1094 | enum srcdest_kind |
1095 | { | |
1096 | srcdest_reg, | |
1097 | srcdest_partial_reg, | |
1098 | srcdest_mem | |
1099 | }; | |
1100 | ||
96309189 MS |
1101 | /* A source or destination location for an m16c or m32c |
1102 | instruction. */ | |
1103 | struct srcdest | |
1104 | { | |
1105 | /* If srcdest_reg, the location is a register pointed to by REG. | |
1106 | If srcdest_partial_reg, the location is part of a register pointed | |
1107 | to by REG. We don't try to handle this too well. | |
1108 | If srcdest_mem, the location is memory whose address is ADDR. */ | |
52059ffd | 1109 | enum srcdest_kind kind; |
96309189 MS |
1110 | pv_t *reg, addr; |
1111 | }; | |
1112 | ||
1113 | ||
1114 | /* Return the SIZE-byte value at LOC in STATE. */ | |
1115 | static pv_t | |
1116 | m32c_srcdest_fetch (struct m32c_pv_state *state, struct srcdest loc, int size) | |
1117 | { | |
1118 | if (loc.kind == srcdest_mem) | |
f7b7ed97 | 1119 | return state->stack->fetch (loc.addr, size); |
96309189 MS |
1120 | else if (loc.kind == srcdest_partial_reg) |
1121 | return pv_unknown (); | |
1122 | else | |
1123 | return *loc.reg; | |
1124 | } | |
1125 | ||
1126 | ||
1127 | /* Write VALUE, a SIZE-byte value, to LOC in STATE. Return zero if | |
1128 | all went well, or non-zero if simulating the store would trash our | |
1129 | state. */ | |
1130 | static int | |
1131 | m32c_srcdest_store (struct m32c_pv_state *state, struct srcdest loc, | |
1132 | pv_t value, int size) | |
1133 | { | |
1134 | if (loc.kind == srcdest_mem) | |
1135 | { | |
f7b7ed97 | 1136 | if (state->stack->store_would_trash (loc.addr)) |
96309189 | 1137 | return 1; |
f7b7ed97 | 1138 | state->stack->store (loc.addr, size, value); |
96309189 MS |
1139 | } |
1140 | else if (loc.kind == srcdest_partial_reg) | |
1141 | *loc.reg = pv_unknown (); | |
1142 | else | |
1143 | *loc.reg = value; | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | ||
1149 | static int | |
1150 | m32c_sign_ext (int v, int bits) | |
1151 | { | |
1152 | int mask = 1 << (bits - 1); | |
1153 | return (v ^ mask) - mask; | |
1154 | } | |
1155 | ||
1156 | static unsigned int | |
1157 | m32c_next_byte (struct m32c_pv_state *st) | |
1158 | { | |
1159 | gdb_assert (st->next_addr - st->scan_pc < sizeof (st->insn)); | |
1160 | return st->insn[st->next_addr++ - st->scan_pc]; | |
1161 | } | |
1162 | ||
1163 | static int | |
1164 | m32c_udisp8 (struct m32c_pv_state *st) | |
1165 | { | |
1166 | return m32c_next_byte (st); | |
1167 | } | |
1168 | ||
1169 | ||
1170 | static int | |
1171 | m32c_sdisp8 (struct m32c_pv_state *st) | |
1172 | { | |
1173 | return m32c_sign_ext (m32c_next_byte (st), 8); | |
1174 | } | |
1175 | ||
1176 | ||
1177 | static int | |
1178 | m32c_udisp16 (struct m32c_pv_state *st) | |
1179 | { | |
1180 | int low = m32c_next_byte (st); | |
1181 | int high = m32c_next_byte (st); | |
1182 | ||
1183 | return low + (high << 8); | |
1184 | } | |
1185 | ||
1186 | ||
1187 | static int | |
1188 | m32c_sdisp16 (struct m32c_pv_state *st) | |
1189 | { | |
1190 | int low = m32c_next_byte (st); | |
1191 | int high = m32c_next_byte (st); | |
1192 | ||
1193 | return m32c_sign_ext (low + (high << 8), 16); | |
1194 | } | |
1195 | ||
1196 | ||
1197 | static int | |
1198 | m32c_udisp24 (struct m32c_pv_state *st) | |
1199 | { | |
1200 | int low = m32c_next_byte (st); | |
1201 | int mid = m32c_next_byte (st); | |
1202 | int high = m32c_next_byte (st); | |
1203 | ||
1204 | return low + (mid << 8) + (high << 16); | |
1205 | } | |
1206 | ||
1207 | ||
1208 | /* Extract the 'source' field from an m32c MOV.size:G-format instruction. */ | |
1209 | static int | |
1210 | m32c_get_src23 (unsigned char *i) | |
1211 | { | |
1212 | return (((i[0] & 0x70) >> 2) | |
1213 | | ((i[1] & 0x30) >> 4)); | |
1214 | } | |
1215 | ||
1216 | ||
1217 | /* Extract the 'dest' field from an m32c MOV.size:G-format instruction. */ | |
1218 | static int | |
1219 | m32c_get_dest23 (unsigned char *i) | |
1220 | { | |
1221 | return (((i[0] & 0x0e) << 1) | |
1222 | | ((i[1] & 0xc0) >> 6)); | |
1223 | } | |
1224 | ||
1225 | ||
1226 | static struct srcdest | |
1227 | m32c_decode_srcdest4 (struct m32c_pv_state *st, | |
1228 | int code, int size) | |
1229 | { | |
1230 | struct srcdest sd; | |
1231 | ||
1232 | if (code < 6) | |
1233 | sd.kind = (size == 2 ? srcdest_reg : srcdest_partial_reg); | |
1234 | else | |
1235 | sd.kind = srcdest_mem; | |
1236 | ||
d56874a7 DD |
1237 | sd.addr = pv_unknown (); |
1238 | sd.reg = 0; | |
1239 | ||
96309189 MS |
1240 | switch (code) |
1241 | { | |
a4497d2f | 1242 | case 0x0: sd.reg = &st->r0; break; |
96309189 MS |
1243 | case 0x1: sd.reg = (size == 1 ? &st->r0 : &st->r1); break; |
1244 | case 0x2: sd.reg = (size == 1 ? &st->r1 : &st->r2); break; | |
1245 | case 0x3: sd.reg = (size == 1 ? &st->r1 : &st->r3); break; | |
1246 | ||
1247 | case 0x4: sd.reg = &st->a0; break; | |
1248 | case 0x5: sd.reg = &st->a1; break; | |
1249 | ||
1250 | case 0x6: sd.addr = st->a0; break; | |
1251 | case 0x7: sd.addr = st->a1; break; | |
1252 | ||
1253 | case 0x8: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; | |
1254 | case 0x9: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; | |
1255 | case 0xa: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; | |
1256 | case 0xb: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; | |
1257 | ||
1258 | case 0xc: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; | |
1259 | case 0xd: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; | |
1260 | case 0xe: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; | |
1261 | case 0xf: sd.addr = pv_constant (m32c_udisp16 (st)); break; | |
1262 | ||
1263 | default: | |
f3574227 | 1264 | gdb_assert_not_reached ("unexpected srcdest4"); |
96309189 MS |
1265 | } |
1266 | ||
1267 | return sd; | |
1268 | } | |
1269 | ||
1270 | ||
1271 | static struct srcdest | |
1272 | m32c_decode_sd23 (struct m32c_pv_state *st, int code, int size, int ind) | |
1273 | { | |
1274 | struct srcdest sd; | |
1275 | ||
d56874a7 DD |
1276 | sd.addr = pv_unknown (); |
1277 | sd.reg = 0; | |
1278 | ||
96309189 MS |
1279 | switch (code) |
1280 | { | |
1281 | case 0x12: | |
1282 | case 0x13: | |
1283 | case 0x10: | |
1284 | case 0x11: | |
1285 | sd.kind = (size == 1) ? srcdest_partial_reg : srcdest_reg; | |
1286 | break; | |
1287 | ||
1288 | case 0x02: | |
1289 | case 0x03: | |
1290 | sd.kind = (size == 4) ? srcdest_reg : srcdest_partial_reg; | |
1291 | break; | |
1292 | ||
1293 | default: | |
1294 | sd.kind = srcdest_mem; | |
1295 | break; | |
1296 | ||
1297 | } | |
1298 | ||
1299 | switch (code) | |
1300 | { | |
1301 | case 0x12: sd.reg = &st->r0; break; | |
1302 | case 0x13: sd.reg = &st->r1; break; | |
1303 | case 0x10: sd.reg = ((size == 1) ? &st->r0 : &st->r2); break; | |
1304 | case 0x11: sd.reg = ((size == 1) ? &st->r1 : &st->r3); break; | |
1305 | case 0x02: sd.reg = &st->a0; break; | |
1306 | case 0x03: sd.reg = &st->a1; break; | |
1307 | ||
1308 | case 0x00: sd.addr = st->a0; break; | |
1309 | case 0x01: sd.addr = st->a1; break; | |
1310 | case 0x04: sd.addr = pv_add_constant (st->a0, m32c_udisp8 (st)); break; | |
1311 | case 0x05: sd.addr = pv_add_constant (st->a1, m32c_udisp8 (st)); break; | |
1312 | case 0x06: sd.addr = pv_add_constant (st->sb, m32c_udisp8 (st)); break; | |
1313 | case 0x07: sd.addr = pv_add_constant (st->fb, m32c_sdisp8 (st)); break; | |
1314 | case 0x08: sd.addr = pv_add_constant (st->a0, m32c_udisp16 (st)); break; | |
1315 | case 0x09: sd.addr = pv_add_constant (st->a1, m32c_udisp16 (st)); break; | |
1316 | case 0x0a: sd.addr = pv_add_constant (st->sb, m32c_udisp16 (st)); break; | |
1317 | case 0x0b: sd.addr = pv_add_constant (st->fb, m32c_sdisp16 (st)); break; | |
1318 | case 0x0c: sd.addr = pv_add_constant (st->a0, m32c_udisp24 (st)); break; | |
1319 | case 0x0d: sd.addr = pv_add_constant (st->a1, m32c_udisp24 (st)); break; | |
1320 | case 0x0f: sd.addr = pv_constant (m32c_udisp16 (st)); break; | |
1321 | case 0x0e: sd.addr = pv_constant (m32c_udisp24 (st)); break; | |
1322 | default: | |
f3574227 | 1323 | gdb_assert_not_reached ("unexpected sd23"); |
96309189 MS |
1324 | } |
1325 | ||
1326 | if (ind) | |
1327 | { | |
1328 | sd.addr = m32c_srcdest_fetch (st, sd, 4); | |
1329 | sd.kind = srcdest_mem; | |
1330 | } | |
1331 | ||
1332 | return sd; | |
1333 | } | |
1334 | ||
1335 | ||
1336 | /* The r16c and r32c machines have instructions with similar | |
1337 | semantics, but completely different machine language encodings. So | |
1338 | we break out the semantics into their own functions, and leave | |
1339 | machine-specific decoding in m32c_analyze_prologue. | |
1340 | ||
1341 | The following functions all expect their arguments already decoded, | |
1342 | and they all return zero if analysis should continue past this | |
1343 | instruction, or non-zero if analysis should stop. */ | |
1344 | ||
1345 | ||
1346 | /* Simulate an 'enter SIZE' instruction in STATE. */ | |
1347 | static int | |
1348 | m32c_pv_enter (struct m32c_pv_state *state, int size) | |
1349 | { | |
96309189 MS |
1350 | /* If simulating this store would require us to forget |
1351 | everything we know about the stack frame in the name of | |
1352 | accuracy, it would be better to just quit now. */ | |
f7b7ed97 | 1353 | if (state->stack->store_would_trash (state->sp)) |
96309189 MS |
1354 | return 1; |
1355 | ||
345bd07c SM |
1356 | gdbarch *arch = state->arch; |
1357 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
96309189 MS |
1358 | if (m32c_pv_push (state, state->fb, tdep->push_addr_bytes)) |
1359 | return 1; | |
345bd07c | 1360 | |
96309189 MS |
1361 | state->fb = state->sp; |
1362 | state->sp = pv_add_constant (state->sp, -size); | |
1363 | ||
1364 | return 0; | |
1365 | } | |
1366 | ||
1367 | ||
1368 | static int | |
1369 | m32c_pv_pushm_one (struct m32c_pv_state *state, pv_t reg, | |
1370 | int bit, int src, int size) | |
1371 | { | |
1372 | if (bit & src) | |
1373 | { | |
1374 | if (m32c_pv_push (state, reg, size)) | |
1375 | return 1; | |
1376 | } | |
1377 | ||
1378 | return 0; | |
1379 | } | |
1380 | ||
1381 | ||
1382 | /* Simulate a 'pushm SRC' instruction in STATE. */ | |
1383 | static int | |
1384 | m32c_pv_pushm (struct m32c_pv_state *state, int src) | |
1385 | { | |
345bd07c SM |
1386 | gdbarch *arch = state->arch; |
1387 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
96309189 MS |
1388 | |
1389 | /* The bits in SRC indicating which registers to save are: | |
1390 | r0 r1 r2 r3 a0 a1 sb fb */ | |
1391 | return | |
1392 | ( m32c_pv_pushm_one (state, state->fb, 0x01, src, tdep->push_addr_bytes) | |
1393 | || m32c_pv_pushm_one (state, state->sb, 0x02, src, tdep->push_addr_bytes) | |
1394 | || m32c_pv_pushm_one (state, state->a1, 0x04, src, tdep->push_addr_bytes) | |
1395 | || m32c_pv_pushm_one (state, state->a0, 0x08, src, tdep->push_addr_bytes) | |
1396 | || m32c_pv_pushm_one (state, state->r3, 0x10, src, 2) | |
1397 | || m32c_pv_pushm_one (state, state->r2, 0x20, src, 2) | |
1398 | || m32c_pv_pushm_one (state, state->r1, 0x40, src, 2) | |
1399 | || m32c_pv_pushm_one (state, state->r0, 0x80, src, 2)); | |
1400 | } | |
1401 | ||
1402 | /* Return non-zero if VALUE is the first incoming argument register. */ | |
1403 | ||
1404 | static int | |
1405 | m32c_is_1st_arg_reg (struct m32c_pv_state *state, pv_t value) | |
1406 | { | |
345bd07c SM |
1407 | gdbarch *arch = state->arch; |
1408 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
1409 | ||
96309189 | 1410 | return (value.kind == pvk_register |
dda83cd7 | 1411 | && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c |
96309189 MS |
1412 | ? (value.reg == tdep->r1->num) |
1413 | : (value.reg == tdep->r0->num)) | |
dda83cd7 | 1414 | && value.k == 0); |
96309189 MS |
1415 | } |
1416 | ||
1417 | /* Return non-zero if VALUE is an incoming argument register. */ | |
1418 | ||
1419 | static int | |
1420 | m32c_is_arg_reg (struct m32c_pv_state *state, pv_t value) | |
1421 | { | |
345bd07c SM |
1422 | gdbarch *arch = state->arch; |
1423 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
1424 | ||
96309189 | 1425 | return (value.kind == pvk_register |
dda83cd7 | 1426 | && (gdbarch_bfd_arch_info (state->arch)->mach == bfd_mach_m16c |
96309189 MS |
1427 | ? (value.reg == tdep->r1->num || value.reg == tdep->r2->num) |
1428 | : (value.reg == tdep->r0->num)) | |
dda83cd7 | 1429 | && value.k == 0); |
96309189 MS |
1430 | } |
1431 | ||
1432 | /* Return non-zero if a store of VALUE to LOC is probably spilling an | |
1433 | argument register to its stack slot in STATE. Such instructions | |
1434 | should be included in the prologue, if possible. | |
1435 | ||
1436 | The store is a spill if: | |
1437 | - the value being stored is the original value of an argument register; | |
1438 | - the value has not already been stored somewhere in STACK; and | |
1439 | - LOC is a stack slot (e.g., a memory location whose address is | |
1440 | relative to the original value of the SP). */ | |
1441 | ||
1442 | static int | |
1443 | m32c_is_arg_spill (struct m32c_pv_state *st, | |
1444 | struct srcdest loc, | |
1445 | pv_t value) | |
1446 | { | |
345bd07c SM |
1447 | gdbarch *arch = st->arch; |
1448 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
96309189 MS |
1449 | |
1450 | return (m32c_is_arg_reg (st, value) | |
1451 | && loc.kind == srcdest_mem | |
dda83cd7 SM |
1452 | && pv_is_register (loc.addr, tdep->sp->num) |
1453 | && ! st->stack->find_reg (st->arch, value.reg, 0)); | |
96309189 MS |
1454 | } |
1455 | ||
1456 | /* Return non-zero if a store of VALUE to LOC is probably | |
1457 | copying the struct return address into an address register | |
1458 | for immediate use. This is basically a "spill" into the | |
1459 | address register, instead of onto the stack. | |
1460 | ||
1461 | The prerequisites are: | |
1462 | - value being stored is original value of the FIRST arg register; | |
1463 | - value has not already been stored on stack; and | |
1464 | - LOC is an address register (a0 or a1). */ | |
1465 | ||
1466 | static int | |
1467 | m32c_is_struct_return (struct m32c_pv_state *st, | |
1468 | struct srcdest loc, | |
1469 | pv_t value) | |
1470 | { | |
345bd07c SM |
1471 | gdbarch *arch = st->arch; |
1472 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
96309189 MS |
1473 | |
1474 | return (m32c_is_1st_arg_reg (st, value) | |
f7b7ed97 | 1475 | && !st->stack->find_reg (st->arch, value.reg, 0) |
96309189 MS |
1476 | && loc.kind == srcdest_reg |
1477 | && (pv_is_register (*loc.reg, tdep->a0->num) | |
1478 | || pv_is_register (*loc.reg, tdep->a1->num))); | |
1479 | } | |
1480 | ||
1481 | /* Return non-zero if a 'pushm' saving the registers indicated by SRC | |
1482 | was a register save: | |
1483 | - all the named registers should have their original values, and | |
1484 | - the stack pointer should be at a constant offset from the | |
1485 | original stack pointer. */ | |
1486 | static int | |
1487 | m32c_pushm_is_reg_save (struct m32c_pv_state *st, int src) | |
1488 | { | |
345bd07c SM |
1489 | gdbarch *arch = st->arch; |
1490 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
1491 | ||
96309189 MS |
1492 | /* The bits in SRC indicating which registers to save are: |
1493 | r0 r1 r2 r3 a0 a1 sb fb */ | |
1494 | return | |
1495 | (pv_is_register (st->sp, tdep->sp->num) | |
1496 | && (! (src & 0x01) || pv_is_register_k (st->fb, tdep->fb->num, 0)) | |
1497 | && (! (src & 0x02) || pv_is_register_k (st->sb, tdep->sb->num, 0)) | |
1498 | && (! (src & 0x04) || pv_is_register_k (st->a1, tdep->a1->num, 0)) | |
1499 | && (! (src & 0x08) || pv_is_register_k (st->a0, tdep->a0->num, 0)) | |
1500 | && (! (src & 0x10) || pv_is_register_k (st->r3, tdep->r3->num, 0)) | |
1501 | && (! (src & 0x20) || pv_is_register_k (st->r2, tdep->r2->num, 0)) | |
1502 | && (! (src & 0x40) || pv_is_register_k (st->r1, tdep->r1->num, 0)) | |
1503 | && (! (src & 0x80) || pv_is_register_k (st->r0, tdep->r0->num, 0))); | |
1504 | } | |
1505 | ||
1506 | ||
1507 | /* Function for finding saved registers in a 'struct pv_area'; we pass | |
f7b7ed97 | 1508 | this to pv_area::scan. |
96309189 MS |
1509 | |
1510 | If VALUE is a saved register, ADDR says it was saved at a constant | |
1511 | offset from the frame base, and SIZE indicates that the whole | |
1512 | register was saved, record its offset in RESULT_UNTYPED. */ | |
1513 | static void | |
1514 | check_for_saved (void *prologue_untyped, pv_t addr, CORE_ADDR size, pv_t value) | |
1515 | { | |
1516 | struct m32c_prologue *prologue = (struct m32c_prologue *) prologue_untyped; | |
1517 | struct gdbarch *arch = prologue->arch; | |
345bd07c | 1518 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); |
96309189 MS |
1519 | |
1520 | /* Is this the unchanged value of some register being saved on the | |
1521 | stack? */ | |
1522 | if (value.kind == pvk_register | |
1523 | && value.k == 0 | |
1524 | && pv_is_register (addr, tdep->sp->num)) | |
1525 | { | |
1526 | /* Some registers require special handling: they're saved as a | |
1527 | larger value than the register itself. */ | |
1528 | CORE_ADDR saved_size = register_size (arch, value.reg); | |
1529 | ||
1530 | if (value.reg == tdep->pc->num) | |
1531 | saved_size = tdep->ret_addr_bytes; | |
7b9ee6a8 | 1532 | else if (register_type (arch, value.reg) |
96309189 MS |
1533 | == tdep->data_addr_reg_type) |
1534 | saved_size = tdep->push_addr_bytes; | |
1535 | ||
1536 | if (size == saved_size) | |
1537 | { | |
1538 | /* Find which end of the saved value corresponds to our | |
1539 | register. */ | |
1540 | if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) | |
1541 | prologue->reg_offset[value.reg] | |
1542 | = (addr.k + saved_size - register_size (arch, value.reg)); | |
1543 | else | |
1544 | prologue->reg_offset[value.reg] = addr.k; | |
1545 | } | |
1546 | } | |
1547 | } | |
1548 | ||
1549 | ||
1550 | /* Analyze the function prologue for ARCH at START, going no further | |
1551 | than LIMIT, and place a description of what we found in | |
1552 | PROLOGUE. */ | |
63807e1d | 1553 | static void |
96309189 MS |
1554 | m32c_analyze_prologue (struct gdbarch *arch, |
1555 | CORE_ADDR start, CORE_ADDR limit, | |
1556 | struct m32c_prologue *prologue) | |
1557 | { | |
345bd07c | 1558 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); |
96309189 MS |
1559 | unsigned long mach = gdbarch_bfd_arch_info (arch)->mach; |
1560 | CORE_ADDR after_last_frame_related_insn; | |
96309189 MS |
1561 | struct m32c_pv_state st; |
1562 | ||
1563 | st.arch = arch; | |
1564 | st.r0 = pv_register (tdep->r0->num, 0); | |
1565 | st.r1 = pv_register (tdep->r1->num, 0); | |
1566 | st.r2 = pv_register (tdep->r2->num, 0); | |
1567 | st.r3 = pv_register (tdep->r3->num, 0); | |
1568 | st.a0 = pv_register (tdep->a0->num, 0); | |
1569 | st.a1 = pv_register (tdep->a1->num, 0); | |
1570 | st.sb = pv_register (tdep->sb->num, 0); | |
1571 | st.fb = pv_register (tdep->fb->num, 0); | |
1572 | st.sp = pv_register (tdep->sp->num, 0); | |
1573 | st.pc = pv_register (tdep->pc->num, 0); | |
f7b7ed97 TT |
1574 | pv_area stack (tdep->sp->num, gdbarch_addr_bit (arch)); |
1575 | st.stack = &stack; | |
96309189 MS |
1576 | |
1577 | /* Record that the call instruction has saved the return address on | |
1578 | the stack. */ | |
1579 | m32c_pv_push (&st, st.pc, tdep->ret_addr_bytes); | |
1580 | ||
1581 | memset (prologue, 0, sizeof (*prologue)); | |
1582 | prologue->arch = arch; | |
1583 | { | |
1584 | int i; | |
1585 | for (i = 0; i < M32C_MAX_NUM_REGS; i++) | |
1586 | prologue->reg_offset[i] = 1; | |
1587 | } | |
1588 | ||
1589 | st.scan_pc = after_last_frame_related_insn = start; | |
1590 | ||
1591 | while (st.scan_pc < limit) | |
1592 | { | |
1593 | pv_t pre_insn_fb = st.fb; | |
1594 | pv_t pre_insn_sp = st.sp; | |
1595 | ||
1596 | /* In theory we could get in trouble by trying to read ahead | |
1597 | here, when we only know we're expecting one byte. In | |
1598 | practice I doubt anyone will care, and it makes the rest of | |
1599 | the code easier. */ | |
1600 | if (target_read_memory (st.scan_pc, st.insn, sizeof (st.insn))) | |
1601 | /* If we can't fetch the instruction from memory, stop here | |
1602 | and hope for the best. */ | |
1603 | break; | |
1604 | st.next_addr = st.scan_pc; | |
1605 | ||
1606 | /* The assembly instructions are written as they appear in the | |
1607 | section of the processor manuals that describe the | |
1608 | instruction encodings. | |
1609 | ||
1610 | When a single assembly language instruction has several | |
1611 | different machine-language encodings, the manual | |
1612 | distinguishes them by a number in parens, before the | |
1613 | mnemonic. Those numbers are included, as well. | |
1614 | ||
1615 | The srcdest decoding instructions have the same names as the | |
1616 | analogous functions in the simulator. */ | |
1617 | if (mach == bfd_mach_m16c) | |
1618 | { | |
1619 | /* (1) ENTER #imm8 */ | |
1620 | if (st.insn[0] == 0x7c && st.insn[1] == 0xf2) | |
1621 | { | |
1622 | if (m32c_pv_enter (&st, st.insn[2])) | |
1623 | break; | |
1624 | st.next_addr += 3; | |
1625 | } | |
1626 | /* (1) PUSHM src */ | |
1627 | else if (st.insn[0] == 0xec) | |
1628 | { | |
1629 | int src = st.insn[1]; | |
1630 | if (m32c_pv_pushm (&st, src)) | |
1631 | break; | |
1632 | st.next_addr += 2; | |
1633 | ||
1634 | if (m32c_pushm_is_reg_save (&st, src)) | |
1635 | after_last_frame_related_insn = st.next_addr; | |
1636 | } | |
1637 | ||
1638 | /* (6) MOV.size:G src, dest */ | |
1639 | else if ((st.insn[0] & 0xfe) == 0x72) | |
1640 | { | |
1641 | int size = (st.insn[0] & 0x01) ? 2 : 1; | |
f79b9530 DJ |
1642 | struct srcdest src; |
1643 | struct srcdest dest; | |
1644 | pv_t src_value; | |
96309189 MS |
1645 | st.next_addr += 2; |
1646 | ||
f79b9530 | 1647 | src |
96309189 | 1648 | = m32c_decode_srcdest4 (&st, (st.insn[1] >> 4) & 0xf, size); |
f79b9530 | 1649 | dest |
96309189 | 1650 | = m32c_decode_srcdest4 (&st, st.insn[1] & 0xf, size); |
f79b9530 | 1651 | src_value = m32c_srcdest_fetch (&st, src, size); |
96309189 MS |
1652 | |
1653 | if (m32c_is_arg_spill (&st, dest, src_value)) | |
1654 | after_last_frame_related_insn = st.next_addr; | |
1655 | else if (m32c_is_struct_return (&st, dest, src_value)) | |
1656 | after_last_frame_related_insn = st.next_addr; | |
1657 | ||
1658 | if (m32c_srcdest_store (&st, dest, src_value, size)) | |
1659 | break; | |
1660 | } | |
1661 | ||
1662 | /* (1) LDC #IMM16, sp */ | |
1663 | else if (st.insn[0] == 0xeb | |
1664 | && st.insn[1] == 0x50) | |
1665 | { | |
1666 | st.next_addr += 2; | |
1667 | st.sp = pv_constant (m32c_udisp16 (&st)); | |
1668 | } | |
1669 | ||
1670 | else | |
1671 | /* We've hit some instruction we don't know how to simulate. | |
1672 | Strictly speaking, we should set every value we're | |
1673 | tracking to "unknown". But we'll be optimistic, assume | |
1674 | that we have enough information already, and stop | |
1675 | analysis here. */ | |
1676 | break; | |
1677 | } | |
1678 | else | |
1679 | { | |
1680 | int src_indirect = 0; | |
1681 | int dest_indirect = 0; | |
1682 | int i = 0; | |
1683 | ||
1684 | gdb_assert (mach == bfd_mach_m32c); | |
1685 | ||
1686 | /* Check for prefix bytes indicating indirect addressing. */ | |
1687 | if (st.insn[0] == 0x41) | |
1688 | { | |
1689 | src_indirect = 1; | |
1690 | i++; | |
1691 | } | |
1692 | else if (st.insn[0] == 0x09) | |
1693 | { | |
1694 | dest_indirect = 1; | |
1695 | i++; | |
1696 | } | |
1697 | else if (st.insn[0] == 0x49) | |
1698 | { | |
1699 | src_indirect = dest_indirect = 1; | |
1700 | i++; | |
1701 | } | |
1702 | ||
1703 | /* (1) ENTER #imm8 */ | |
1704 | if (st.insn[i] == 0xec) | |
1705 | { | |
1706 | if (m32c_pv_enter (&st, st.insn[i + 1])) | |
1707 | break; | |
1708 | st.next_addr += 2; | |
1709 | } | |
1710 | ||
1711 | /* (1) PUSHM src */ | |
1712 | else if (st.insn[i] == 0x8f) | |
1713 | { | |
1714 | int src = st.insn[i + 1]; | |
1715 | if (m32c_pv_pushm (&st, src)) | |
1716 | break; | |
1717 | st.next_addr += 2; | |
1718 | ||
1719 | if (m32c_pushm_is_reg_save (&st, src)) | |
1720 | after_last_frame_related_insn = st.next_addr; | |
1721 | } | |
1722 | ||
1723 | /* (7) MOV.size:G src, dest */ | |
1724 | else if ((st.insn[i] & 0x80) == 0x80 | |
1725 | && (st.insn[i + 1] & 0x0f) == 0x0b | |
1726 | && m32c_get_src23 (&st.insn[i]) < 20 | |
1727 | && m32c_get_dest23 (&st.insn[i]) < 20) | |
1728 | { | |
f79b9530 DJ |
1729 | struct srcdest src; |
1730 | struct srcdest dest; | |
1731 | pv_t src_value; | |
96309189 MS |
1732 | int bw = st.insn[i] & 0x01; |
1733 | int size = bw ? 2 : 1; | |
96309189 MS |
1734 | st.next_addr += 2; |
1735 | ||
f79b9530 | 1736 | src |
96309189 MS |
1737 | = m32c_decode_sd23 (&st, m32c_get_src23 (&st.insn[i]), |
1738 | size, src_indirect); | |
f79b9530 | 1739 | dest |
96309189 MS |
1740 | = m32c_decode_sd23 (&st, m32c_get_dest23 (&st.insn[i]), |
1741 | size, dest_indirect); | |
f79b9530 | 1742 | src_value = m32c_srcdest_fetch (&st, src, size); |
96309189 MS |
1743 | |
1744 | if (m32c_is_arg_spill (&st, dest, src_value)) | |
1745 | after_last_frame_related_insn = st.next_addr; | |
1746 | ||
1747 | if (m32c_srcdest_store (&st, dest, src_value, size)) | |
1748 | break; | |
1749 | } | |
1750 | /* (2) LDC #IMM24, sp */ | |
1751 | else if (st.insn[i] == 0xd5 | |
1752 | && st.insn[i + 1] == 0x29) | |
1753 | { | |
1754 | st.next_addr += 2; | |
1755 | st.sp = pv_constant (m32c_udisp24 (&st)); | |
1756 | } | |
1757 | else | |
1758 | /* We've hit some instruction we don't know how to simulate. | |
1759 | Strictly speaking, we should set every value we're | |
1760 | tracking to "unknown". But we'll be optimistic, assume | |
1761 | that we have enough information already, and stop | |
1762 | analysis here. */ | |
1763 | break; | |
1764 | } | |
1765 | ||
1766 | /* If this instruction changed the FB or decreased the SP (i.e., | |
dda83cd7 SM |
1767 | allocated more stack space), then this may be a good place to |
1768 | declare the prologue finished. However, there are some | |
1769 | exceptions: | |
96309189 | 1770 | |
dda83cd7 SM |
1771 | - If the instruction just changed the FB back to its original |
1772 | value, then that's probably a restore instruction. The | |
1773 | prologue should definitely end before that. | |
96309189 | 1774 | |
dda83cd7 SM |
1775 | - If the instruction increased the value of the SP (that is, |
1776 | shrunk the frame), then it's probably part of a frame | |
1777 | teardown sequence, and the prologue should end before | |
1778 | that. */ | |
96309189 MS |
1779 | |
1780 | if (! pv_is_identical (st.fb, pre_insn_fb)) | |
dda83cd7 SM |
1781 | { |
1782 | if (! pv_is_register_k (st.fb, tdep->fb->num, 0)) | |
1783 | after_last_frame_related_insn = st.next_addr; | |
1784 | } | |
96309189 | 1785 | else if (! pv_is_identical (st.sp, pre_insn_sp)) |
dda83cd7 SM |
1786 | { |
1787 | /* The comparison of the constants looks odd, there, because | |
1788 | .k is unsigned. All it really means is that the SP is | |
1789 | lower than it was before the instruction. */ | |
1790 | if ( pv_is_register (pre_insn_sp, tdep->sp->num) | |
1791 | && pv_is_register (st.sp, tdep->sp->num) | |
1792 | && ((pre_insn_sp.k - st.sp.k) < (st.sp.k - pre_insn_sp.k))) | |
1793 | after_last_frame_related_insn = st.next_addr; | |
1794 | } | |
96309189 MS |
1795 | |
1796 | st.scan_pc = st.next_addr; | |
1797 | } | |
1798 | ||
1799 | /* Did we load a constant value into the stack pointer? */ | |
1800 | if (pv_is_constant (st.sp)) | |
1801 | prologue->kind = prologue_first_frame; | |
1802 | ||
1803 | /* Alternatively, did we initialize the frame pointer? Remember | |
1804 | that the CFA is the address after the return address. */ | |
1805 | if (pv_is_register (st.fb, tdep->sp->num)) | |
1806 | { | |
1807 | prologue->kind = prologue_with_frame_ptr; | |
1808 | prologue->frame_ptr_offset = st.fb.k; | |
1809 | } | |
1810 | ||
1811 | /* Is the frame size a known constant? Remember that frame_size is | |
1812 | actually the offset from the CFA to the SP (i.e., a negative | |
1813 | value). */ | |
1814 | else if (pv_is_register (st.sp, tdep->sp->num)) | |
1815 | { | |
1816 | prologue->kind = prologue_sans_frame_ptr; | |
1817 | prologue->frame_size = st.sp.k; | |
1818 | } | |
1819 | ||
1820 | /* We haven't been able to make sense of this function's frame. Treat | |
1821 | it as the first frame. */ | |
1822 | else | |
1823 | prologue->kind = prologue_first_frame; | |
1824 | ||
1825 | /* Record where all the registers were saved. */ | |
f7b7ed97 | 1826 | st.stack->scan (check_for_saved, (void *) prologue); |
96309189 MS |
1827 | |
1828 | prologue->prologue_end = after_last_frame_related_insn; | |
96309189 MS |
1829 | } |
1830 | ||
1831 | ||
1832 | static CORE_ADDR | |
6093d2eb | 1833 | m32c_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR ip) |
96309189 | 1834 | { |
2c02bd72 | 1835 | const char *name; |
96309189 MS |
1836 | CORE_ADDR func_addr, func_end, sal_end; |
1837 | struct m32c_prologue p; | |
1838 | ||
1839 | /* Try to find the extent of the function that contains IP. */ | |
1840 | if (! find_pc_partial_function (ip, &name, &func_addr, &func_end)) | |
1841 | return ip; | |
1842 | ||
1843 | /* Find end by prologue analysis. */ | |
6093d2eb | 1844 | m32c_analyze_prologue (gdbarch, ip, func_end, &p); |
96309189 | 1845 | /* Find end by line info. */ |
d80b854b | 1846 | sal_end = skip_prologue_using_sal (gdbarch, ip); |
96309189 MS |
1847 | /* Return whichever is lower. */ |
1848 | if (sal_end != 0 && sal_end != ip && sal_end < p.prologue_end) | |
1849 | return sal_end; | |
1850 | else | |
1851 | return p.prologue_end; | |
1852 | } | |
1853 | ||
1854 | ||
1855 | \f | |
1856 | /* Stack unwinding. */ | |
1857 | ||
1858 | static struct m32c_prologue * | |
94afd7a6 | 1859 | m32c_analyze_frame_prologue (struct frame_info *this_frame, |
96309189 MS |
1860 | void **this_prologue_cache) |
1861 | { | |
1862 | if (! *this_prologue_cache) | |
1863 | { | |
94afd7a6 UW |
1864 | CORE_ADDR func_start = get_frame_func (this_frame); |
1865 | CORE_ADDR stop_addr = get_frame_pc (this_frame); | |
96309189 MS |
1866 | |
1867 | /* If we couldn't find any function containing the PC, then | |
dda83cd7 | 1868 | just initialize the prologue cache, but don't do anything. */ |
96309189 | 1869 | if (! func_start) |
dda83cd7 | 1870 | stop_addr = func_start; |
96309189 MS |
1871 | |
1872 | *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct m32c_prologue); | |
94afd7a6 | 1873 | m32c_analyze_prologue (get_frame_arch (this_frame), |
9a3c8263 SM |
1874 | func_start, stop_addr, |
1875 | (struct m32c_prologue *) *this_prologue_cache); | |
96309189 MS |
1876 | } |
1877 | ||
9a3c8263 | 1878 | return (struct m32c_prologue *) *this_prologue_cache; |
96309189 MS |
1879 | } |
1880 | ||
1881 | ||
1882 | static CORE_ADDR | |
94afd7a6 | 1883 | m32c_frame_base (struct frame_info *this_frame, |
dda83cd7 | 1884 | void **this_prologue_cache) |
96309189 MS |
1885 | { |
1886 | struct m32c_prologue *p | |
94afd7a6 | 1887 | = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); |
345bd07c SM |
1888 | gdbarch *arch = get_frame_arch (this_frame); |
1889 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
96309189 MS |
1890 | |
1891 | /* In functions that use alloca, the distance between the stack | |
1892 | pointer and the frame base varies dynamically, so we can't use | |
1893 | the SP plus static information like prologue analysis to find the | |
1894 | frame base. However, such functions must have a frame pointer, | |
1895 | to be able to restore the SP on exit. So whenever we do have a | |
1896 | frame pointer, use that to find the base. */ | |
1897 | switch (p->kind) | |
1898 | { | |
1899 | case prologue_with_frame_ptr: | |
1900 | { | |
1901 | CORE_ADDR fb | |
94afd7a6 | 1902 | = get_frame_register_unsigned (this_frame, tdep->fb->num); |
96309189 MS |
1903 | return fb - p->frame_ptr_offset; |
1904 | } | |
1905 | ||
1906 | case prologue_sans_frame_ptr: | |
1907 | { | |
1908 | CORE_ADDR sp | |
94afd7a6 | 1909 | = get_frame_register_unsigned (this_frame, tdep->sp->num); |
96309189 MS |
1910 | return sp - p->frame_size; |
1911 | } | |
1912 | ||
1913 | case prologue_first_frame: | |
1914 | return 0; | |
1915 | ||
1916 | default: | |
f3574227 | 1917 | gdb_assert_not_reached ("unexpected prologue kind"); |
96309189 MS |
1918 | } |
1919 | } | |
1920 | ||
1921 | ||
1922 | static void | |
94afd7a6 | 1923 | m32c_this_id (struct frame_info *this_frame, |
96309189 MS |
1924 | void **this_prologue_cache, |
1925 | struct frame_id *this_id) | |
1926 | { | |
94afd7a6 | 1927 | CORE_ADDR base = m32c_frame_base (this_frame, this_prologue_cache); |
96309189 MS |
1928 | |
1929 | if (base) | |
94afd7a6 | 1930 | *this_id = frame_id_build (base, get_frame_func (this_frame)); |
96309189 MS |
1931 | /* Otherwise, leave it unset, and that will terminate the backtrace. */ |
1932 | } | |
1933 | ||
1934 | ||
94afd7a6 UW |
1935 | static struct value * |
1936 | m32c_prev_register (struct frame_info *this_frame, | |
1937 | void **this_prologue_cache, int regnum) | |
96309189 | 1938 | { |
345bd07c SM |
1939 | gdbarch *arch = get_frame_arch (this_frame); |
1940 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (arch); | |
96309189 | 1941 | struct m32c_prologue *p |
94afd7a6 UW |
1942 | = m32c_analyze_frame_prologue (this_frame, this_prologue_cache); |
1943 | CORE_ADDR frame_base = m32c_frame_base (this_frame, this_prologue_cache); | |
96309189 MS |
1944 | |
1945 | if (regnum == tdep->sp->num) | |
94afd7a6 | 1946 | return frame_unwind_got_constant (this_frame, regnum, frame_base); |
96309189 MS |
1947 | |
1948 | /* If prologue analysis says we saved this register somewhere, | |
1949 | return a description of the stack slot holding it. */ | |
94afd7a6 UW |
1950 | if (p->reg_offset[regnum] != 1) |
1951 | return frame_unwind_got_memory (this_frame, regnum, | |
dda83cd7 | 1952 | frame_base + p->reg_offset[regnum]); |
96309189 MS |
1953 | |
1954 | /* Otherwise, presume we haven't changed the value of this | |
1955 | register, and get it from the next frame. */ | |
94afd7a6 | 1956 | return frame_unwind_got_register (this_frame, regnum, regnum); |
96309189 MS |
1957 | } |
1958 | ||
1959 | ||
1960 | static const struct frame_unwind m32c_unwind = { | |
a154d838 | 1961 | "m32c prologue", |
96309189 | 1962 | NORMAL_FRAME, |
8fbca658 | 1963 | default_frame_unwind_stop_reason, |
96309189 | 1964 | m32c_this_id, |
94afd7a6 UW |
1965 | m32c_prev_register, |
1966 | NULL, | |
1967 | default_frame_sniffer | |
96309189 MS |
1968 | }; |
1969 | ||
96309189 MS |
1970 | \f |
1971 | /* Inferior calls. */ | |
1972 | ||
1973 | /* The calling conventions, according to GCC: | |
1974 | ||
1975 | r8c, m16c | |
1976 | --------- | |
1977 | First arg may be passed in r1l or r1 if it (1) fits (QImode or | |
1978 | HImode), (2) is named, and (3) is an integer or pointer type (no | |
1979 | structs, floats, etc). Otherwise, it's passed on the stack. | |
1980 | ||
1981 | Second arg may be passed in r2, same restrictions (but not QImode), | |
1982 | even if the first arg is passed on the stack. | |
1983 | ||
1984 | Third and further args are passed on the stack. No padding is | |
1985 | used, stack "alignment" is 8 bits. | |
1986 | ||
1987 | m32cm, m32c | |
1988 | ----------- | |
1989 | ||
1990 | First arg may be passed in r0l or r0, same restrictions as above. | |
1991 | ||
1992 | Second and further args are passed on the stack. Padding is used | |
1993 | after QImode parameters (i.e. lower-addressed byte is the value, | |
1994 | higher-addressed byte is the padding), stack "alignment" is 16 | |
1995 | bits. */ | |
1996 | ||
1997 | ||
1998 | /* Return true if TYPE is a type that can be passed in registers. (We | |
1999 | ignore the size, and pay attention only to the type code; | |
2000 | acceptable sizes depends on which register is being considered to | |
2001 | hold it.) */ | |
2002 | static int | |
2003 | m32c_reg_arg_type (struct type *type) | |
2004 | { | |
78134374 | 2005 | enum type_code code = type->code (); |
96309189 MS |
2006 | |
2007 | return (code == TYPE_CODE_INT | |
2008 | || code == TYPE_CODE_ENUM | |
2009 | || code == TYPE_CODE_PTR | |
aa006118 | 2010 | || TYPE_IS_REFERENCE (type) |
96309189 MS |
2011 | || code == TYPE_CODE_BOOL |
2012 | || code == TYPE_CODE_CHAR); | |
2013 | } | |
2014 | ||
2015 | ||
2016 | static CORE_ADDR | |
2017 | m32c_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
2018 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
cf84fa6b AH |
2019 | struct value **args, CORE_ADDR sp, |
2020 | function_call_return_method return_method, | |
96309189 MS |
2021 | CORE_ADDR struct_addr) |
2022 | { | |
345bd07c | 2023 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
e17a4113 | 2024 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96309189 MS |
2025 | unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; |
2026 | CORE_ADDR cfa; | |
2027 | int i; | |
2028 | ||
2029 | /* The number of arguments given in this function's prototype, or | |
2030 | zero if it has a non-prototyped function type. The m32c ABI | |
2031 | passes arguments mentioned in the prototype differently from | |
2032 | those in the ellipsis of a varargs function, or from those passed | |
2033 | to a non-prototyped function. */ | |
2034 | int num_prototyped_args = 0; | |
2035 | ||
2036 | { | |
2037 | struct type *func_type = value_type (function); | |
2038 | ||
ed09d7da | 2039 | /* Dereference function pointer types. */ |
78134374 | 2040 | if (func_type->code () == TYPE_CODE_PTR) |
ed09d7da KB |
2041 | func_type = TYPE_TARGET_TYPE (func_type); |
2042 | ||
78134374 SM |
2043 | gdb_assert (func_type->code () == TYPE_CODE_FUNC || |
2044 | func_type->code () == TYPE_CODE_METHOD); | |
96309189 MS |
2045 | |
2046 | #if 0 | |
2047 | /* The ABI description in gcc/config/m32c/m32c.abi says that | |
2048 | we need to handle prototyped and non-prototyped functions | |
2049 | separately, but the code in GCC doesn't actually do so. */ | |
2050 | if (TYPE_PROTOTYPED (func_type)) | |
2051 | #endif | |
1f704f76 | 2052 | num_prototyped_args = func_type->num_fields (); |
96309189 MS |
2053 | } |
2054 | ||
2055 | /* First, if the function returns an aggregate by value, push a | |
2056 | pointer to a buffer for it. This doesn't affect the way | |
2057 | subsequent arguments are allocated to registers. */ | |
cf84fa6b | 2058 | if (return_method == return_method_struct) |
96309189 MS |
2059 | { |
2060 | int ptr_len = TYPE_LENGTH (tdep->ptr_voyd); | |
2061 | sp -= ptr_len; | |
e17a4113 | 2062 | write_memory_unsigned_integer (sp, ptr_len, byte_order, struct_addr); |
96309189 MS |
2063 | } |
2064 | ||
2065 | /* Push the arguments. */ | |
2066 | for (i = nargs - 1; i >= 0; i--) | |
2067 | { | |
2068 | struct value *arg = args[i]; | |
50888e42 | 2069 | const gdb_byte *arg_bits = value_contents (arg).data (); |
96309189 MS |
2070 | struct type *arg_type = value_type (arg); |
2071 | ULONGEST arg_size = TYPE_LENGTH (arg_type); | |
2072 | ||
2073 | /* Can it go in r1 or r1l (for m16c) or r0 or r0l (for m32c)? */ | |
2074 | if (i == 0 | |
2075 | && arg_size <= 2 | |
2076 | && i < num_prototyped_args | |
2077 | && m32c_reg_arg_type (arg_type)) | |
2078 | { | |
2079 | /* Extract and re-store as an integer as a terse way to make | |
2080 | sure it ends up in the least significant end of r1. (GDB | |
2081 | should avoid assuming endianness, even on uni-endian | |
2082 | processors.) */ | |
e17a4113 UW |
2083 | ULONGEST u = extract_unsigned_integer (arg_bits, arg_size, |
2084 | byte_order); | |
96309189 MS |
2085 | struct m32c_reg *reg = (mach == bfd_mach_m16c) ? tdep->r1 : tdep->r0; |
2086 | regcache_cooked_write_unsigned (regcache, reg->num, u); | |
2087 | } | |
2088 | ||
2089 | /* Can it go in r2? */ | |
2090 | else if (mach == bfd_mach_m16c | |
2091 | && i == 1 | |
2092 | && arg_size == 2 | |
2093 | && i < num_prototyped_args | |
2094 | && m32c_reg_arg_type (arg_type)) | |
b66f5587 | 2095 | regcache->cooked_write (tdep->r2->num, arg_bits); |
96309189 MS |
2096 | |
2097 | /* Everything else goes on the stack. */ | |
2098 | else | |
2099 | { | |
2100 | sp -= arg_size; | |
2101 | ||
2102 | /* Align the stack. */ | |
2103 | if (mach == bfd_mach_m32c) | |
2104 | sp &= ~1; | |
2105 | ||
2106 | write_memory (sp, arg_bits, arg_size); | |
2107 | } | |
2108 | } | |
2109 | ||
2110 | /* This is the CFA we use to identify the dummy frame. */ | |
2111 | cfa = sp; | |
2112 | ||
2113 | /* Push the return address. */ | |
2114 | sp -= tdep->ret_addr_bytes; | |
e17a4113 UW |
2115 | write_memory_unsigned_integer (sp, tdep->ret_addr_bytes, byte_order, |
2116 | bp_addr); | |
96309189 MS |
2117 | |
2118 | /* Update the stack pointer. */ | |
2119 | regcache_cooked_write_unsigned (regcache, tdep->sp->num, sp); | |
2120 | ||
2121 | /* We need to borrow an odd trick from the i386 target here. | |
2122 | ||
2123 | The value we return from this function gets used as the stack | |
2124 | address (the CFA) for the dummy frame's ID. The obvious thing is | |
2125 | to return the new TOS. However, that points at the return | |
2126 | address, saved on the stack, which is inconsistent with the CFA's | |
2127 | described by GCC's DWARF 2 .debug_frame information: DWARF 2 | |
2128 | .debug_frame info uses the address immediately after the saved | |
2129 | return address. So you end up with a dummy frame whose CFA | |
2130 | points at the return address, but the frame for the function | |
2131 | being called has a CFA pointing after the return address: the | |
2132 | younger CFA is *greater than* the older CFA. The sanity checks | |
2133 | in frame.c don't like that. | |
2134 | ||
2135 | So we try to be consistent with the CFA's used by DWARF 2. | |
2136 | Having a dummy frame and a real frame with the *same* CFA is | |
2137 | tolerable. */ | |
2138 | return cfa; | |
2139 | } | |
2140 | ||
2141 | ||
96309189 MS |
2142 | \f |
2143 | /* Return values. */ | |
2144 | ||
2145 | /* Return value conventions, according to GCC: | |
2146 | ||
2147 | r8c, m16c | |
2148 | --------- | |
2149 | ||
2150 | QImode in r0l | |
2151 | HImode in r0 | |
2152 | SImode in r2r0 | |
2153 | near pointer in r0 | |
2154 | far pointer in r2r0 | |
2155 | ||
2156 | Aggregate values (regardless of size) are returned by pushing a | |
2157 | pointer to a temporary area on the stack after the args are pushed. | |
2158 | The function fills in this area with the value. Note that this | |
2159 | pointer on the stack does not affect how register arguments, if any, | |
2160 | are configured. | |
2161 | ||
2162 | m32cm, m32c | |
2163 | ----------- | |
2164 | Same. */ | |
2165 | ||
2166 | /* Return non-zero if values of type TYPE are returned by storing them | |
2167 | in a buffer whose address is passed on the stack, ahead of the | |
2168 | other arguments. */ | |
2169 | static int | |
2170 | m32c_return_by_passed_buf (struct type *type) | |
2171 | { | |
78134374 | 2172 | enum type_code code = type->code (); |
96309189 MS |
2173 | |
2174 | return (code == TYPE_CODE_STRUCT | |
2175 | || code == TYPE_CODE_UNION); | |
2176 | } | |
2177 | ||
2178 | static enum return_value_convention | |
2179 | m32c_return_value (struct gdbarch *gdbarch, | |
6a3a010b | 2180 | struct value *function, |
96309189 MS |
2181 | struct type *valtype, |
2182 | struct regcache *regcache, | |
2183 | gdb_byte *readbuf, | |
2184 | const gdb_byte *writebuf) | |
2185 | { | |
345bd07c | 2186 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
e17a4113 | 2187 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96309189 MS |
2188 | enum return_value_convention conv; |
2189 | ULONGEST valtype_len = TYPE_LENGTH (valtype); | |
2190 | ||
2191 | if (m32c_return_by_passed_buf (valtype)) | |
2192 | conv = RETURN_VALUE_STRUCT_CONVENTION; | |
2193 | else | |
2194 | conv = RETURN_VALUE_REGISTER_CONVENTION; | |
2195 | ||
2196 | if (readbuf) | |
2197 | { | |
2198 | /* We should never be called to find values being returned by | |
2199 | RETURN_VALUE_STRUCT_CONVENTION. Those can't be located, | |
2200 | unless we made the call ourselves. */ | |
2201 | gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); | |
2202 | ||
2203 | gdb_assert (valtype_len <= 8); | |
2204 | ||
2205 | /* Anything that fits in r0 is returned there. */ | |
2206 | if (valtype_len <= TYPE_LENGTH (tdep->r0->type)) | |
2207 | { | |
2208 | ULONGEST u; | |
2209 | regcache_cooked_read_unsigned (regcache, tdep->r0->num, &u); | |
e17a4113 | 2210 | store_unsigned_integer (readbuf, valtype_len, byte_order, u); |
96309189 MS |
2211 | } |
2212 | else | |
2213 | { | |
2214 | /* Everything else is passed in mem0, using as many bytes as | |
2215 | needed. This is not what the Renesas tools do, but it's | |
2216 | what GCC does at the moment. */ | |
3b7344d5 | 2217 | struct bound_minimal_symbol mem0 |
96309189 MS |
2218 | = lookup_minimal_symbol ("mem0", NULL, NULL); |
2219 | ||
3b7344d5 | 2220 | if (! mem0.minsym) |
a73c6dcd MS |
2221 | error (_("The return value is stored in memory at 'mem0', " |
2222 | "but GDB cannot find\n" | |
2223 | "its address.")); | |
77e371c0 | 2224 | read_memory (BMSYMBOL_VALUE_ADDRESS (mem0), readbuf, valtype_len); |
96309189 MS |
2225 | } |
2226 | } | |
2227 | ||
2228 | if (writebuf) | |
2229 | { | |
2230 | /* We should never be called to store values to be returned | |
2231 | using RETURN_VALUE_STRUCT_CONVENTION. We have no way of | |
2232 | finding the buffer, unless we made the call ourselves. */ | |
2233 | gdb_assert (conv == RETURN_VALUE_REGISTER_CONVENTION); | |
2234 | ||
2235 | gdb_assert (valtype_len <= 8); | |
2236 | ||
2237 | /* Anything that fits in r0 is returned there. */ | |
2238 | if (valtype_len <= TYPE_LENGTH (tdep->r0->type)) | |
2239 | { | |
e17a4113 UW |
2240 | ULONGEST u = extract_unsigned_integer (writebuf, valtype_len, |
2241 | byte_order); | |
96309189 MS |
2242 | regcache_cooked_write_unsigned (regcache, tdep->r0->num, u); |
2243 | } | |
2244 | else | |
2245 | { | |
2246 | /* Everything else is passed in mem0, using as many bytes as | |
2247 | needed. This is not what the Renesas tools do, but it's | |
2248 | what GCC does at the moment. */ | |
3b7344d5 | 2249 | struct bound_minimal_symbol mem0 |
96309189 MS |
2250 | = lookup_minimal_symbol ("mem0", NULL, NULL); |
2251 | ||
3b7344d5 | 2252 | if (! mem0.minsym) |
a73c6dcd MS |
2253 | error (_("The return value is stored in memory at 'mem0', " |
2254 | "but GDB cannot find\n" | |
2255 | " its address.")); | |
77e371c0 | 2256 | write_memory (BMSYMBOL_VALUE_ADDRESS (mem0), writebuf, valtype_len); |
96309189 MS |
2257 | } |
2258 | } | |
2259 | ||
2260 | return conv; | |
2261 | } | |
2262 | ||
2263 | ||
2264 | \f | |
2265 | /* Trampolines. */ | |
2266 | ||
2267 | /* The m16c and m32c use a trampoline function for indirect function | |
2268 | calls. An indirect call looks like this: | |
2269 | ||
2270 | ... push arguments ... | |
2271 | ... push target function address ... | |
2272 | jsr.a m32c_jsri16 | |
2273 | ||
2274 | The code for m32c_jsri16 looks like this: | |
2275 | ||
2276 | m32c_jsri16: | |
2277 | ||
dda83cd7 | 2278 | # Save return address. |
96309189 MS |
2279 | pop.w m32c_jsri_ret |
2280 | pop.b m32c_jsri_ret+2 | |
2281 | ||
dda83cd7 | 2282 | # Store target function address. |
96309189 MS |
2283 | pop.w m32c_jsri_addr |
2284 | ||
2285 | # Re-push return address. | |
2286 | push.b m32c_jsri_ret+2 | |
2287 | push.w m32c_jsri_ret | |
2288 | ||
2289 | # Call the target function. | |
2290 | jmpi.a m32c_jsri_addr | |
2291 | ||
2292 | Without further information, GDB will treat calls to m32c_jsri16 | |
2293 | like calls to any other function. Since m32c_jsri16 doesn't have | |
2294 | debugging information, that normally means that GDB sets a step- | |
2295 | resume breakpoint and lets the program continue --- which is not | |
2296 | what the user wanted. (Giving the trampoline debugging info | |
2297 | doesn't help: the user expects the program to stop in the function | |
2298 | their program is calling, not in some trampoline code they've never | |
2299 | seen before.) | |
2300 | ||
e76f05fa | 2301 | The gdbarch_skip_trampoline_code method tells GDB how to step |
96309189 MS |
2302 | through such trampoline functions transparently to the user. When |
2303 | given the address of a trampoline function's first instruction, | |
e76f05fa | 2304 | gdbarch_skip_trampoline_code should return the address of the first |
96309189 MS |
2305 | instruction of the function really being called. If GDB decides it |
2306 | wants to step into that function, it will set a breakpoint there | |
2307 | and silently continue to it. | |
2308 | ||
2309 | We recognize the trampoline by name, and extract the target address | |
2310 | directly from the stack. This isn't great, but recognizing by its | |
2311 | code sequence seems more fragile. */ | |
2312 | ||
2313 | static CORE_ADDR | |
52f729a7 | 2314 | m32c_skip_trampoline_code (struct frame_info *frame, CORE_ADDR stop_pc) |
96309189 | 2315 | { |
e17a4113 | 2316 | struct gdbarch *gdbarch = get_frame_arch (frame); |
345bd07c | 2317 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
e17a4113 | 2318 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
96309189 MS |
2319 | |
2320 | /* It would be nicer to simply look up the addresses of known | |
2321 | trampolines once, and then compare stop_pc with them. However, | |
2322 | we'd need to ensure that that cached address got invalidated when | |
2323 | someone loaded a new executable, and I'm not quite sure of the | |
2324 | best way to do that. find_pc_partial_function does do some | |
2325 | caching, so we'll see how this goes. */ | |
2c02bd72 | 2326 | const char *name; |
96309189 MS |
2327 | CORE_ADDR start, end; |
2328 | ||
2329 | if (find_pc_partial_function (stop_pc, &name, &start, &end)) | |
2330 | { | |
2331 | /* Are we stopped at the beginning of the trampoline function? */ | |
2332 | if (strcmp (name, "m32c_jsri16") == 0 | |
2333 | && stop_pc == start) | |
2334 | { | |
2335 | /* Get the stack pointer. The return address is at the top, | |
2336 | and the target function's address is just below that. We | |
2337 | know it's a two-byte address, since the trampoline is | |
2338 | m32c_jsri*16*. */ | |
2339 | CORE_ADDR sp = get_frame_sp (get_current_frame ()); | |
2340 | CORE_ADDR target | |
e17a4113 UW |
2341 | = read_memory_unsigned_integer (sp + tdep->ret_addr_bytes, |
2342 | 2, byte_order); | |
96309189 MS |
2343 | |
2344 | /* What we have now is the address of a jump instruction. | |
2345 | What we need is the destination of that jump. | |
025bb325 MS |
2346 | The opcode is 1 byte, and the destination is the next 3 bytes. */ |
2347 | ||
e17a4113 | 2348 | target = read_memory_unsigned_integer (target + 1, 3, byte_order); |
96309189 MS |
2349 | return target; |
2350 | } | |
2351 | } | |
2352 | ||
2353 | return 0; | |
2354 | } | |
2355 | ||
2356 | ||
2357 | /* Address/pointer conversions. */ | |
2358 | ||
2359 | /* On the m16c, there is a 24-bit address space, but only a very few | |
2360 | instructions can generate addresses larger than 0xffff: jumps, | |
2361 | jumps to subroutines, and the lde/std (load/store extended) | |
2362 | instructions. | |
2363 | ||
2364 | Since GCC can only support one size of pointer, we can't have | |
2365 | distinct 'near' and 'far' pointer types; we have to pick one size | |
2366 | for everything. If we wanted to use 24-bit pointers, then GCC | |
2367 | would have to use lde and ste for all memory references, which | |
2368 | would be terrible for performance and code size. So the GNU | |
2369 | toolchain uses 16-bit pointers for everything, and gives up the | |
2370 | ability to have pointers point outside the first 64k of memory. | |
2371 | ||
2372 | However, as a special hack, we let the linker place functions at | |
2373 | addresses above 0xffff, as long as it also places a trampoline in | |
2374 | the low 64k for every function whose address is taken. Each | |
2375 | trampoline consists of a single jmp.a instruction that jumps to the | |
2376 | function's real entry point. Pointers to functions can be 16 bits | |
2377 | long, even though the functions themselves are at higher addresses: | |
2378 | the pointers refer to the trampolines, not the functions. | |
2379 | ||
2380 | This complicates things for GDB, however: given the address of a | |
2381 | function (from debug info or linker symbols, say) which could be | |
2382 | anywhere in the 24-bit address space, how can we find an | |
2383 | appropriate 16-bit value to use as a pointer to it? | |
2384 | ||
2385 | If the linker has not generated a trampoline for the function, | |
2386 | we're out of luck. Well, I guess we could malloc some space and | |
2387 | write a jmp.a instruction to it, but I'm not going to get into that | |
2388 | at the moment. | |
2389 | ||
2390 | If the linker has generated a trampoline for the function, then it | |
2391 | also emitted a symbol for the trampoline: if the function's linker | |
2392 | symbol is named NAME, then the function's trampoline's linker | |
2393 | symbol is named NAME.plt. | |
2394 | ||
2395 | So, given a code address: | |
2396 | - We try to find a linker symbol at that address. | |
2397 | - If we find such a symbol named NAME, we look for a linker symbol | |
2398 | named NAME.plt. | |
2399 | - If we find such a symbol, we assume it is a trampoline, and use | |
2400 | its address as the pointer value. | |
2401 | ||
2402 | And, given a function pointer: | |
2403 | - We try to find a linker symbol at that address named NAME.plt. | |
2404 | - If we find such a symbol, we look for a linker symbol named NAME. | |
2405 | - If we find that, we provide that as the function's address. | |
2406 | - If any of the above steps fail, we return the original address | |
2407 | unchanged; it might really be a function in the low 64k. | |
2408 | ||
2409 | See? You *knew* there was a reason you wanted to be a computer | |
2410 | programmer! :) */ | |
2411 | ||
2412 | static void | |
9898f801 UW |
2413 | m32c_m16c_address_to_pointer (struct gdbarch *gdbarch, |
2414 | struct type *type, gdb_byte *buf, CORE_ADDR addr) | |
96309189 | 2415 | { |
e17a4113 | 2416 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
f79b9530 | 2417 | enum type_code target_code; |
78134374 | 2418 | gdb_assert (type->code () == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type)); |
96309189 | 2419 | |
78134374 | 2420 | target_code = TYPE_TARGET_TYPE (type)->code (); |
96309189 MS |
2421 | |
2422 | if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) | |
2423 | { | |
0d5cff50 | 2424 | const char *func_name; |
f79b9530 | 2425 | char *tramp_name; |
3b7344d5 | 2426 | struct bound_minimal_symbol tramp_msym; |
f79b9530 | 2427 | |
96309189 | 2428 | /* Try to find a linker symbol at this address. */ |
7cbd4a93 TT |
2429 | struct bound_minimal_symbol func_msym |
2430 | = lookup_minimal_symbol_by_pc (addr); | |
96309189 | 2431 | |
7cbd4a93 | 2432 | if (! func_msym.minsym) |
dda83cd7 SM |
2433 | error (_("Cannot convert code address %s to function pointer:\n" |
2434 | "couldn't find a symbol at that address, to find trampoline."), | |
2435 | paddress (gdbarch, addr)); | |
96309189 | 2436 | |
c9d95fa3 | 2437 | func_name = func_msym.minsym->linkage_name (); |
224c3ddb | 2438 | tramp_name = (char *) xmalloc (strlen (func_name) + 5); |
96309189 MS |
2439 | strcpy (tramp_name, func_name); |
2440 | strcat (tramp_name, ".plt"); | |
2441 | ||
2442 | /* Try to find a linker symbol for the trampoline. */ | |
f79b9530 | 2443 | tramp_msym = lookup_minimal_symbol (tramp_name, NULL, NULL); |
96309189 MS |
2444 | |
2445 | /* We've either got another copy of the name now, or don't need | |
dda83cd7 | 2446 | the name any more. */ |
96309189 MS |
2447 | xfree (tramp_name); |
2448 | ||
3b7344d5 | 2449 | if (! tramp_msym.minsym) |
d77b48cf KB |
2450 | { |
2451 | CORE_ADDR ptrval; | |
2452 | ||
2453 | /* No PLT entry found. Mask off the upper bits of the address | |
2454 | to make a pointer. As noted in the warning to the user | |
2455 | below, this value might be useful if converted back into | |
2456 | an address by GDB, but will otherwise, almost certainly, | |
2457 | be garbage. | |
2458 | ||
2459 | Using this masked result does seem to be useful | |
2460 | in gdb.cp/cplusfuncs.exp in which ~40 FAILs turn into | |
2461 | PASSes. These results appear to be correct as well. | |
2462 | ||
2463 | We print a warning here so that the user can make a | |
2464 | determination about whether the result is useful or not. */ | |
2465 | ptrval = addr & 0xffff; | |
2466 | ||
2467 | warning (_("Cannot convert code address %s to function pointer:\n" | |
2468 | "couldn't find trampoline named '%s.plt'.\n" | |
2469 | "Returning pointer value %s instead; this may produce\n" | |
2470 | "a useful result if converted back into an address by GDB,\n" | |
422186a9 | 2471 | "but will most likely not be useful otherwise."), |
d77b48cf KB |
2472 | paddress (gdbarch, addr), func_name, |
2473 | paddress (gdbarch, ptrval)); | |
2474 | ||
2475 | addr = ptrval; | |
96309189 | 2476 | |
d77b48cf KB |
2477 | } |
2478 | else | |
2479 | { | |
2480 | /* The trampoline's address is our pointer. */ | |
77e371c0 | 2481 | addr = BMSYMBOL_VALUE_ADDRESS (tramp_msym); |
d77b48cf | 2482 | } |
96309189 MS |
2483 | } |
2484 | ||
e17a4113 | 2485 | store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, addr); |
96309189 MS |
2486 | } |
2487 | ||
2488 | ||
2489 | static CORE_ADDR | |
9898f801 UW |
2490 | m32c_m16c_pointer_to_address (struct gdbarch *gdbarch, |
2491 | struct type *type, const gdb_byte *buf) | |
96309189 | 2492 | { |
e17a4113 | 2493 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
f79b9530 DJ |
2494 | CORE_ADDR ptr; |
2495 | enum type_code target_code; | |
2496 | ||
78134374 | 2497 | gdb_assert (type->code () == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type)); |
96309189 | 2498 | |
e17a4113 | 2499 | ptr = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order); |
96309189 | 2500 | |
78134374 | 2501 | target_code = TYPE_TARGET_TYPE (type)->code (); |
96309189 MS |
2502 | |
2503 | if (target_code == TYPE_CODE_FUNC || target_code == TYPE_CODE_METHOD) | |
2504 | { | |
2505 | /* See if there is a minimal symbol at that address whose name is | |
dda83cd7 | 2506 | "NAME.plt". */ |
7cbd4a93 | 2507 | struct bound_minimal_symbol ptr_msym = lookup_minimal_symbol_by_pc (ptr); |
96309189 | 2508 | |
7cbd4a93 | 2509 | if (ptr_msym.minsym) |
dda83cd7 SM |
2510 | { |
2511 | const char *ptr_msym_name = ptr_msym.minsym->linkage_name (); | |
2512 | int len = strlen (ptr_msym_name); | |
96309189 | 2513 | |
dda83cd7 SM |
2514 | if (len > 4 |
2515 | && strcmp (ptr_msym_name + len - 4, ".plt") == 0) | |
2516 | { | |
3b7344d5 | 2517 | struct bound_minimal_symbol func_msym; |
dda83cd7 SM |
2518 | /* We have a .plt symbol; try to find the symbol for the |
2519 | corresponding function. | |
2520 | ||
2521 | Since the trampoline contains a jump instruction, we | |
2522 | could also just extract the jump's target address. I | |
2523 | don't see much advantage one way or the other. */ | |
2524 | char *func_name = (char *) xmalloc (len - 4 + 1); | |
2525 | memcpy (func_name, ptr_msym_name, len - 4); | |
2526 | func_name[len - 4] = '\0'; | |
2527 | func_msym | |
2528 | = lookup_minimal_symbol (func_name, NULL, NULL); | |
2529 | ||
2530 | /* If we do have such a symbol, return its value as the | |
2531 | function's true address. */ | |
2532 | if (func_msym.minsym) | |
2533 | ptr = BMSYMBOL_VALUE_ADDRESS (func_msym); | |
2534 | } | |
2535 | } | |
d77b48cf KB |
2536 | else |
2537 | { | |
2538 | int aspace; | |
2539 | ||
2540 | for (aspace = 1; aspace <= 15; aspace++) | |
2541 | { | |
2542 | ptr_msym = lookup_minimal_symbol_by_pc ((aspace << 16) | ptr); | |
2543 | ||
7cbd4a93 | 2544 | if (ptr_msym.minsym) |
d77b48cf KB |
2545 | ptr |= aspace << 16; |
2546 | } | |
2547 | } | |
96309189 MS |
2548 | } |
2549 | ||
2550 | return ptr; | |
2551 | } | |
2552 | ||
63807e1d | 2553 | static void |
a54fba4c | 2554 | m32c_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, |
7830cb4f CV |
2555 | int *frame_regnum, |
2556 | LONGEST *frame_offset) | |
2557 | { | |
2c02bd72 | 2558 | const char *name; |
22e048c9 | 2559 | CORE_ADDR func_addr, func_end; |
7830cb4f CV |
2560 | struct m32c_prologue p; |
2561 | ||
594f7785 | 2562 | struct regcache *regcache = get_current_regcache (); |
345bd07c | 2563 | m32c_gdbarch_tdep *tdep = (m32c_gdbarch_tdep *) gdbarch_tdep (gdbarch); |
7830cb4f CV |
2564 | |
2565 | if (!find_pc_partial_function (pc, &name, &func_addr, &func_end)) | |
025bb325 MS |
2566 | internal_error (__FILE__, __LINE__, |
2567 | _("No virtual frame pointer available")); | |
7830cb4f | 2568 | |
a54fba4c | 2569 | m32c_analyze_prologue (gdbarch, func_addr, pc, &p); |
7830cb4f CV |
2570 | switch (p.kind) |
2571 | { | |
2572 | case prologue_with_frame_ptr: | |
594f7785 | 2573 | *frame_regnum = m32c_banked_register (tdep->fb, regcache)->num; |
7830cb4f CV |
2574 | *frame_offset = p.frame_ptr_offset; |
2575 | break; | |
2576 | case prologue_sans_frame_ptr: | |
594f7785 | 2577 | *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; |
7830cb4f CV |
2578 | *frame_offset = p.frame_size; |
2579 | break; | |
2580 | default: | |
594f7785 | 2581 | *frame_regnum = m32c_banked_register (tdep->sp, regcache)->num; |
7830cb4f CV |
2582 | *frame_offset = 0; |
2583 | break; | |
2584 | } | |
2585 | /* Sanity check */ | |
a54fba4c | 2586 | if (*frame_regnum > gdbarch_num_regs (gdbarch)) |
025bb325 MS |
2587 | internal_error (__FILE__, __LINE__, |
2588 | _("No virtual frame pointer available")); | |
7830cb4f | 2589 | } |
96309189 MS |
2590 | |
2591 | \f | |
2592 | /* Initialization. */ | |
2593 | ||
2594 | static struct gdbarch * | |
2595 | m32c_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2596 | { | |
97ce08cb | 2597 | struct gdbarch *gdbarch; |
96309189 MS |
2598 | unsigned long mach = info.bfd_arch_info->mach; |
2599 | ||
2600 | /* Find a candidate among the list of architectures we've created | |
2601 | already. */ | |
2602 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
2603 | arches != NULL; | |
2604 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
2605 | return arches->gdbarch; | |
2606 | ||
345bd07c | 2607 | m32c_gdbarch_tdep *tdep = new m32c_gdbarch_tdep; |
97ce08cb | 2608 | gdbarch = gdbarch_alloc (&info, tdep); |
96309189 MS |
2609 | |
2610 | /* Essential types. */ | |
97ce08cb | 2611 | make_types (gdbarch); |
96309189 MS |
2612 | |
2613 | /* Address/pointer conversions. */ | |
2614 | if (mach == bfd_mach_m16c) | |
2615 | { | |
97ce08cb YQ |
2616 | set_gdbarch_address_to_pointer (gdbarch, m32c_m16c_address_to_pointer); |
2617 | set_gdbarch_pointer_to_address (gdbarch, m32c_m16c_pointer_to_address); | |
96309189 MS |
2618 | } |
2619 | ||
2620 | /* Register set. */ | |
97ce08cb | 2621 | make_regs (gdbarch); |
96309189 | 2622 | |
96309189 | 2623 | /* Breakpoints. */ |
04180708 YQ |
2624 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, m32c_breakpoint::kind_from_pc); |
2625 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, m32c_breakpoint::bp_from_kind); | |
96309189 MS |
2626 | |
2627 | /* Prologue analysis and unwinding. */ | |
97ce08cb YQ |
2628 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
2629 | set_gdbarch_skip_prologue (gdbarch, m32c_skip_prologue); | |
96309189 MS |
2630 | #if 0 |
2631 | /* I'm dropping the dwarf2 sniffer because it has a few problems. | |
2632 | They may be in the dwarf2 cfi code in GDB, or they may be in | |
2633 | the debug info emitted by the upstream toolchain. I don't | |
2634 | know which, but I do know that the prologue analyzer works better. | |
025bb325 | 2635 | MVS 04/13/06 */ |
97ce08cb | 2636 | dwarf2_append_sniffers (gdbarch); |
96309189 | 2637 | #endif |
97ce08cb | 2638 | frame_unwind_append_unwinder (gdbarch, &m32c_unwind); |
96309189 MS |
2639 | |
2640 | /* Inferior calls. */ | |
97ce08cb YQ |
2641 | set_gdbarch_push_dummy_call (gdbarch, m32c_push_dummy_call); |
2642 | set_gdbarch_return_value (gdbarch, m32c_return_value); | |
96309189 MS |
2643 | |
2644 | /* Trampolines. */ | |
97ce08cb | 2645 | set_gdbarch_skip_trampoline_code (gdbarch, m32c_skip_trampoline_code); |
96309189 | 2646 | |
97ce08cb | 2647 | set_gdbarch_virtual_frame_pointer (gdbarch, m32c_virtual_frame_pointer); |
7830cb4f | 2648 | |
ed09d7da KB |
2649 | /* m32c function boundary addresses are not necessarily even. |
2650 | Therefore, the `vbit', which indicates a pointer to a virtual | |
2651 | member function, is stored in the delta field, rather than as | |
025bb325 | 2652 | the low bit of a function pointer address. |
ed09d7da KB |
2653 | |
2654 | In order to verify this, see the definition of | |
2655 | TARGET_PTRMEMFUNC_VBIT_LOCATION in gcc/defaults.h along with the | |
2656 | definition of FUNCTION_BOUNDARY in gcc/config/m32c/m32c.h. */ | |
97ce08cb | 2657 | set_gdbarch_vbit_in_delta (gdbarch, 1); |
ed09d7da | 2658 | |
97ce08cb | 2659 | return gdbarch; |
96309189 MS |
2660 | } |
2661 | ||
6c265988 | 2662 | void _initialize_m32c_tdep (); |
96309189 | 2663 | void |
6c265988 | 2664 | _initialize_m32c_tdep () |
96309189 MS |
2665 | { |
2666 | register_gdbarch_init (bfd_arch_m32c, m32c_gdbarch_init); | |
2667 | ||
2668 | m32c_dma_reggroup = reggroup_new ("dma", USER_REGGROUP); | |
2669 | } |