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Commit | Line | Data |
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d95a8903 AC |
1 | /* Target-dependent code for Renesas M32R, for GDB. |
2 | ||
1d506c26 | 3 | Copyright (C) 1996-2024 Free Software Foundation, Inc. |
d95a8903 AC |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
d95a8903 AC |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
d95a8903 | 19 | |
ec452525 | 20 | #include "extract-store-integer.h" |
d95a8903 AC |
21 | #include "frame.h" |
22 | #include "frame-unwind.h" | |
23 | #include "frame-base.h" | |
24 | #include "symtab.h" | |
25 | #include "gdbtypes.h" | |
5b9707eb | 26 | #include "cli/cli-cmds.h" |
d95a8903 | 27 | #include "gdbcore.h" |
d95a8903 AC |
28 | #include "value.h" |
29 | #include "inferior.h" | |
30 | #include "symfile.h" | |
31 | #include "objfiles.h" | |
c46b0409 | 32 | #include "osabi.h" |
d95a8903 AC |
33 | #include "language.h" |
34 | #include "arch-utils.h" | |
35 | #include "regcache.h" | |
36 | #include "trad-frame.h" | |
73e8eb51 | 37 | #include "dis-asm.h" |
9b32d526 | 38 | #include "m32r-tdep.h" |
325fac50 | 39 | #include <algorithm> |
d95a8903 | 40 | |
ab0538b8 AH |
41 | /* The size of the argument registers (r0 - r3) in bytes. */ |
42 | #define M32R_ARG_REGISTER_SIZE 4 | |
43 | ||
d95a8903 AC |
44 | /* Local functions */ |
45 | ||
d95a8903 AC |
46 | static CORE_ADDR |
47 | m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
48 | { | |
49 | /* Align to the size of an instruction (so that they can safely be | |
50 | pushed onto the stack. */ | |
51 | return sp & ~3; | |
52 | } | |
53 | ||
d95a8903 | 54 | |
9f0b0322 KI |
55 | /* Breakpoints |
56 | ||
025bb325 | 57 | The little endian mode of M32R is unique. In most of architectures, |
9f0b0322 KI |
58 | two 16-bit instructions, A and B, are placed as the following: |
59 | ||
60 | Big endian: | |
61 | A0 A1 B0 B1 | |
62 | ||
63 | Little endian: | |
64 | A1 A0 B1 B0 | |
65 | ||
66 | In M32R, they are placed like this: | |
67 | ||
68 | Big endian: | |
69 | A0 A1 B0 B1 | |
70 | ||
71 | Little endian: | |
72 | B1 B0 A1 A0 | |
73 | ||
74 | This is because M32R always fetches instructions in 32-bit. | |
75 | ||
025bb325 | 76 | The following functions take care of this behavior. */ |
d95a8903 AC |
77 | |
78 | static int | |
ae4b2284 MD |
79 | m32r_memory_insert_breakpoint (struct gdbarch *gdbarch, |
80 | struct bp_target_info *bp_tgt) | |
d95a8903 | 81 | { |
0d5ed153 | 82 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
d95a8903 | 83 | int val; |
16ac4ab5 | 84 | gdb_byte buf[4]; |
35c63cd8 | 85 | gdb_byte contents_cache[4]; |
16ac4ab5 | 86 | gdb_byte bp_entry[] = { 0x10, 0xf1 }; /* dpt */ |
d95a8903 AC |
87 | |
88 | /* Save the memory contents. */ | |
9f0b0322 | 89 | val = target_read_memory (addr & 0xfffffffc, contents_cache, 4); |
d95a8903 AC |
90 | if (val != 0) |
91 | return val; /* return error */ | |
92 | ||
35c63cd8 | 93 | memcpy (bp_tgt->shadow_contents, contents_cache, 4); |
cd6c3b4f | 94 | bp_tgt->shadow_len = 4; |
8181d85f | 95 | |
d95a8903 | 96 | /* Determine appropriate breakpoint contents and size for this address. */ |
ae4b2284 | 97 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 98 | { |
9f0b0322 | 99 | if ((addr & 3) == 0) |
d95a8903 | 100 | { |
9f0b0322 KI |
101 | buf[0] = bp_entry[0]; |
102 | buf[1] = bp_entry[1]; | |
103 | buf[2] = contents_cache[2] & 0x7f; | |
104 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
105 | } |
106 | else | |
107 | { | |
9f0b0322 KI |
108 | buf[0] = contents_cache[0]; |
109 | buf[1] = contents_cache[1]; | |
110 | buf[2] = bp_entry[0]; | |
111 | buf[3] = bp_entry[1]; | |
d95a8903 AC |
112 | } |
113 | } | |
9f0b0322 KI |
114 | else /* little-endian */ |
115 | { | |
116 | if ((addr & 3) == 0) | |
d95a8903 | 117 | { |
9f0b0322 KI |
118 | buf[0] = contents_cache[0]; |
119 | buf[1] = contents_cache[1] & 0x7f; | |
120 | buf[2] = bp_entry[1]; | |
121 | buf[3] = bp_entry[0]; | |
d95a8903 AC |
122 | } |
123 | else | |
124 | { | |
9f0b0322 KI |
125 | buf[0] = bp_entry[1]; |
126 | buf[1] = bp_entry[0]; | |
127 | buf[2] = contents_cache[2]; | |
128 | buf[3] = contents_cache[3]; | |
d95a8903 AC |
129 | } |
130 | } | |
131 | ||
132 | /* Write the breakpoint. */ | |
9f0b0322 | 133 | val = target_write_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
134 | return val; |
135 | } | |
136 | ||
137 | static int | |
ae4b2284 MD |
138 | m32r_memory_remove_breakpoint (struct gdbarch *gdbarch, |
139 | struct bp_target_info *bp_tgt) | |
d95a8903 | 140 | { |
8181d85f | 141 | CORE_ADDR addr = bp_tgt->placed_address; |
d95a8903 | 142 | int val; |
16ac4ab5 | 143 | gdb_byte buf[4]; |
8181d85f | 144 | gdb_byte *contents_cache = bp_tgt->shadow_contents; |
d95a8903 | 145 | |
9f0b0322 KI |
146 | buf[0] = contents_cache[0]; |
147 | buf[1] = contents_cache[1]; | |
148 | buf[2] = contents_cache[2]; | |
149 | buf[3] = contents_cache[3]; | |
150 | ||
151 | /* Remove parallel bit. */ | |
ae4b2284 | 152 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d95a8903 | 153 | { |
9f0b0322 KI |
154 | if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0) |
155 | buf[2] &= 0x7f; | |
d95a8903 | 156 | } |
9f0b0322 | 157 | else /* little-endian */ |
d95a8903 | 158 | { |
9f0b0322 KI |
159 | if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0) |
160 | buf[1] &= 0x7f; | |
d95a8903 AC |
161 | } |
162 | ||
163 | /* Write contents. */ | |
dd110abf | 164 | val = target_write_raw_memory (addr & 0xfffffffc, buf, 4); |
d95a8903 AC |
165 | return val; |
166 | } | |
167 | ||
cd6c3b4f YQ |
168 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
169 | ||
d19280ad YQ |
170 | static int |
171 | m32r_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
172 | { | |
173 | if ((*pcptr & 3) == 0) | |
174 | return 4; | |
175 | else | |
176 | return 2; | |
177 | } | |
178 | ||
cd6c3b4f YQ |
179 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
180 | ||
16ac4ab5 | 181 | static const gdb_byte * |
d19280ad | 182 | m32r_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) |
d95a8903 | 183 | { |
025bb325 MS |
184 | static gdb_byte be_bp_entry[] = { |
185 | 0x10, 0xf1, 0x70, 0x00 | |
186 | }; /* dpt -> nop */ | |
187 | static gdb_byte le_bp_entry[] = { | |
188 | 0x00, 0x70, 0xf1, 0x10 | |
189 | }; /* dpt -> nop */ | |
d19280ad YQ |
190 | |
191 | *size = kind; | |
d95a8903 AC |
192 | |
193 | /* Determine appropriate breakpoint. */ | |
67d57894 | 194 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
d19280ad | 195 | return be_bp_entry; |
d95a8903 AC |
196 | else |
197 | { | |
d19280ad YQ |
198 | if (kind == 4) |
199 | return le_bp_entry; | |
d95a8903 | 200 | else |
d19280ad | 201 | return le_bp_entry + 2; |
d95a8903 | 202 | } |
d95a8903 AC |
203 | } |
204 | ||
27087b7f | 205 | static const char * const m32r_register_names[] = { |
d95a8903 AC |
206 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
207 | "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", | |
208 | "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", | |
209 | "evb" | |
210 | }; | |
211 | ||
d95a8903 | 212 | static const char * |
d93859e2 | 213 | m32r_register_name (struct gdbarch *gdbarch, int reg_nr) |
d95a8903 | 214 | { |
69f6730d | 215 | static_assert (ARRAY_SIZE (m32r_register_names) == M32R_NUM_REGS); |
d95a8903 AC |
216 | return m32r_register_names[reg_nr]; |
217 | } | |
218 | ||
219 | ||
220 | /* Return the GDB type object for the "standard" data type | |
221 | of data in register N. */ | |
222 | ||
223 | static struct type * | |
224 | m32r_register_type (struct gdbarch *gdbarch, int reg_nr) | |
225 | { | |
226 | if (reg_nr == M32R_PC_REGNUM) | |
0dfff4cb | 227 | return builtin_type (gdbarch)->builtin_func_ptr; |
d95a8903 | 228 | else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) |
0dfff4cb | 229 | return builtin_type (gdbarch)->builtin_data_ptr; |
d95a8903 | 230 | else |
df4df182 | 231 | return builtin_type (gdbarch)->builtin_int32; |
d95a8903 AC |
232 | } |
233 | ||
234 | ||
235 | /* Write into appropriate registers a function return value | |
025bb325 | 236 | of type TYPE, given in virtual format. |
d95a8903 | 237 | |
025bb325 | 238 | Things always get returned in RET1_REGNUM, RET2_REGNUM. */ |
d95a8903 AC |
239 | |
240 | static void | |
241 | m32r_store_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 242 | const gdb_byte *valbuf) |
d95a8903 | 243 | { |
ac7936df | 244 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 245 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 | 246 | CORE_ADDR regval; |
df86565b | 247 | int len = type->length (); |
d95a8903 | 248 | |
e17a4113 | 249 | regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len, byte_order); |
d95a8903 AC |
250 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); |
251 | ||
252 | if (len > 4) | |
253 | { | |
7c543f7b | 254 | regval = extract_unsigned_integer (valbuf + 4, |
e17a4113 | 255 | len - 4, byte_order); |
d95a8903 AC |
256 | regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); |
257 | } | |
258 | } | |
259 | ||
025bb325 | 260 | /* This is required by skip_prologue. The results of decoding a prologue |
d95a8903 AC |
261 | should be cached because this thrashing is getting nuts. */ |
262 | ||
cea15572 | 263 | static int |
e17a4113 UW |
264 | decode_prologue (struct gdbarch *gdbarch, |
265 | CORE_ADDR start_pc, CORE_ADDR scan_limit, | |
cea15572 | 266 | CORE_ADDR *pl_endptr, unsigned long *framelength) |
d95a8903 | 267 | { |
e17a4113 | 268 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
269 | unsigned long framesize; |
270 | int insn; | |
271 | int op1; | |
d95a8903 | 272 | CORE_ADDR after_prologue = 0; |
cea15572 | 273 | CORE_ADDR after_push = 0; |
d95a8903 AC |
274 | CORE_ADDR after_stack_adjust = 0; |
275 | CORE_ADDR current_pc; | |
cea15572 | 276 | LONGEST return_value; |
d95a8903 AC |
277 | |
278 | framesize = 0; | |
279 | after_prologue = 0; | |
280 | ||
281 | for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) | |
282 | { | |
025bb325 | 283 | /* Check if current pc's location is readable. */ |
e17a4113 | 284 | if (!safe_read_memory_integer (current_pc, 2, byte_order, &return_value)) |
cea15572 KI |
285 | return -1; |
286 | ||
e17a4113 | 287 | insn = read_memory_unsigned_integer (current_pc, 2, byte_order); |
d95a8903 | 288 | |
cea15572 KI |
289 | if (insn == 0x0000) |
290 | break; | |
291 | ||
d95a8903 | 292 | /* If this is a 32 bit instruction, we dont want to examine its |
dda83cd7 | 293 | immediate data as though it were an instruction. */ |
d95a8903 AC |
294 | if (current_pc & 0x02) |
295 | { | |
025bb325 | 296 | /* Decode this instruction further. */ |
d95a8903 AC |
297 | insn &= 0x7fff; |
298 | } | |
299 | else | |
300 | { | |
d95a8903 AC |
301 | if (insn & 0x8000) |
302 | { | |
303 | if (current_pc == scan_limit) | |
304 | scan_limit += 2; /* extend the search */ | |
cea15572 | 305 | |
d95a8903 | 306 | current_pc += 2; /* skip the immediate data */ |
cea15572 | 307 | |
025bb325 | 308 | /* Check if current pc's location is readable. */ |
e17a4113 UW |
309 | if (!safe_read_memory_integer (current_pc, 2, byte_order, |
310 | &return_value)) | |
cea15572 KI |
311 | return -1; |
312 | ||
d95a8903 AC |
313 | if (insn == 0x8faf) /* add3 sp, sp, xxxx */ |
314 | /* add 16 bit sign-extended offset */ | |
315 | { | |
316 | framesize += | |
e17a4113 UW |
317 | -((short) read_memory_unsigned_integer (current_pc, |
318 | 2, byte_order)); | |
d95a8903 AC |
319 | } |
320 | else | |
321 | { | |
025bb325 | 322 | if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ |
e17a4113 UW |
323 | && safe_read_memory_integer (current_pc + 2, |
324 | 2, byte_order, | |
cea15572 | 325 | &return_value) |
7e3dd49e | 326 | && read_memory_unsigned_integer (current_pc + 2, |
e17a4113 UW |
327 | 2, byte_order) |
328 | == 0x0f24) | |
d95a8903 | 329 | { |
025bb325 | 330 | /* Subtract 24 bit sign-extended negative-offset. */ |
e17a4113 UW |
331 | insn = read_memory_unsigned_integer (current_pc - 2, |
332 | 4, byte_order); | |
d95a8903 AC |
333 | if (insn & 0x00800000) /* sign extend */ |
334 | insn |= 0xff000000; /* negative */ | |
335 | else | |
336 | insn &= 0x00ffffff; /* positive */ | |
337 | framesize += insn; | |
338 | } | |
339 | } | |
cea15572 | 340 | after_push = current_pc + 2; |
d95a8903 AC |
341 | continue; |
342 | } | |
343 | } | |
025bb325 | 344 | op1 = insn & 0xf000; /* Isolate just the first nibble. */ |
d95a8903 AC |
345 | |
346 | if ((insn & 0xf0ff) == 0x207f) | |
347 | { /* st reg, @-sp */ | |
d95a8903 | 348 | framesize += 4; |
d95a8903 AC |
349 | after_prologue = 0; |
350 | continue; | |
351 | } | |
352 | if ((insn >> 8) == 0x4f) /* addi sp, xx */ | |
025bb325 | 353 | /* Add 8 bit sign-extended offset. */ |
d95a8903 | 354 | { |
9ffbf372 | 355 | int stack_adjust = (signed char) (insn & 0xff); |
d95a8903 AC |
356 | |
357 | /* there are probably two of these stack adjustments: | |
358 | 1) A negative one in the prologue, and | |
359 | 2) A positive one in the epilogue. | |
360 | We are only interested in the first one. */ | |
361 | ||
362 | if (stack_adjust < 0) | |
363 | { | |
364 | framesize -= stack_adjust; | |
365 | after_prologue = 0; | |
366 | /* A frameless function may have no "mv fp, sp". | |
dda83cd7 | 367 | In that case, this is the end of the prologue. */ |
d95a8903 AC |
368 | after_stack_adjust = current_pc + 2; |
369 | } | |
370 | continue; | |
371 | } | |
372 | if (insn == 0x1d8f) | |
373 | { /* mv fp, sp */ | |
374 | after_prologue = current_pc + 2; | |
375 | break; /* end of stack adjustments */ | |
376 | } | |
cea15572 | 377 | |
025bb325 | 378 | /* Nop looks like a branch, continue explicitly. */ |
d95a8903 AC |
379 | if (insn == 0x7000) |
380 | { | |
381 | after_prologue = current_pc + 2; | |
025bb325 | 382 | continue; /* nop occurs between pushes. */ |
d95a8903 | 383 | } |
025bb325 | 384 | /* End of prolog if any of these are trap instructions. */ |
cea15572 KI |
385 | if ((insn & 0xfff0) == 0x10f0) |
386 | { | |
387 | after_prologue = current_pc; | |
388 | break; | |
389 | } | |
025bb325 | 390 | /* End of prolog if any of these are branch instructions. */ |
d95a8903 AC |
391 | if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) |
392 | { | |
393 | after_prologue = current_pc; | |
d95a8903 AC |
394 | continue; |
395 | } | |
025bb325 | 396 | /* Some of the branch instructions are mixed with other types. */ |
d95a8903 AC |
397 | if (op1 == 0x1000) |
398 | { | |
399 | int subop = insn & 0x0ff0; | |
400 | if ((subop == 0x0ec0) || (subop == 0x0fc0)) | |
401 | { | |
402 | after_prologue = current_pc; | |
d95a8903 AC |
403 | continue; /* jmp , jl */ |
404 | } | |
405 | } | |
406 | } | |
407 | ||
cea15572 KI |
408 | if (framelength) |
409 | *framelength = framesize; | |
410 | ||
d95a8903 AC |
411 | if (current_pc >= scan_limit) |
412 | { | |
413 | if (pl_endptr) | |
414 | { | |
415 | if (after_stack_adjust != 0) | |
416 | /* We did not find a "mv fp,sp", but we DID find | |
417 | a stack_adjust. Is it safe to use that as the | |
025bb325 | 418 | end of the prologue? I just don't know. */ |
d95a8903 AC |
419 | { |
420 | *pl_endptr = after_stack_adjust; | |
421 | } | |
cea15572 KI |
422 | else if (after_push != 0) |
423 | /* We did not find a "mv fp,sp", but we DID find | |
424 | a push. Is it safe to use that as the | |
025bb325 | 425 | end of the prologue? I just don't know. */ |
cea15572 KI |
426 | { |
427 | *pl_endptr = after_push; | |
428 | } | |
d95a8903 AC |
429 | else |
430 | /* We reached the end of the loop without finding the end | |
025bb325 MS |
431 | of the prologue. No way to win -- we should report |
432 | failure. The way we do that is to return the original | |
433 | start_pc. GDB will set a breakpoint at the start of | |
434 | the function (etc.) */ | |
d95a8903 AC |
435 | *pl_endptr = start_pc; |
436 | } | |
cea15572 | 437 | return 0; |
d95a8903 | 438 | } |
cea15572 | 439 | |
d95a8903 AC |
440 | if (after_prologue == 0) |
441 | after_prologue = current_pc; | |
442 | ||
443 | if (pl_endptr) | |
444 | *pl_endptr = after_prologue; | |
cea15572 KI |
445 | |
446 | return 0; | |
d95a8903 AC |
447 | } /* decode_prologue */ |
448 | ||
449 | /* Function: skip_prologue | |
025bb325 | 450 | Find end of function prologue. */ |
d95a8903 | 451 | |
cea15572 | 452 | #define DEFAULT_SEARCH_LIMIT 128 |
d95a8903 | 453 | |
63807e1d | 454 | static CORE_ADDR |
6093d2eb | 455 | m32r_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
d95a8903 | 456 | { |
e17a4113 | 457 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
458 | CORE_ADDR func_addr, func_end; |
459 | struct symtab_and_line sal; | |
cea15572 | 460 | LONGEST return_value; |
d95a8903 | 461 | |
025bb325 | 462 | /* See what the symbol table says. */ |
d95a8903 AC |
463 | |
464 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
465 | { | |
466 | sal = find_pc_line (func_addr, 0); | |
467 | ||
468 | if (sal.line != 0 && sal.end <= func_end) | |
469 | { | |
470 | func_end = sal.end; | |
471 | } | |
472 | else | |
473 | /* Either there's no line info, or the line after the prologue is after | |
474 | the end of the function. In this case, there probably isn't a | |
475 | prologue. */ | |
476 | { | |
325fac50 | 477 | func_end = std::min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); |
d95a8903 AC |
478 | } |
479 | } | |
480 | else | |
481 | func_end = pc + DEFAULT_SEARCH_LIMIT; | |
cea15572 | 482 | |
025bb325 | 483 | /* If pc's location is not readable, just quit. */ |
e17a4113 | 484 | if (!safe_read_memory_integer (pc, 4, byte_order, &return_value)) |
cea15572 KI |
485 | return pc; |
486 | ||
487 | /* Find the end of prologue. */ | |
e17a4113 | 488 | if (decode_prologue (gdbarch, pc, func_end, &sal.end, NULL) < 0) |
cea15572 KI |
489 | return pc; |
490 | ||
d95a8903 AC |
491 | return sal.end; |
492 | } | |
493 | ||
d95a8903 AC |
494 | struct m32r_unwind_cache |
495 | { | |
496 | /* The previous frame's inner most stack address. Used as this | |
497 | frame ID's stack_addr. */ | |
498 | CORE_ADDR prev_sp; | |
499 | /* The frame's base, optionally used by the high-level debug info. */ | |
500 | CORE_ADDR base; | |
501 | int size; | |
502 | /* How far the SP and r13 (FP) have been offset from the start of | |
503 | the stack frame (as defined by the previous frame's stack | |
504 | pointer). */ | |
505 | LONGEST sp_offset; | |
506 | LONGEST r13_offset; | |
507 | int uses_frame; | |
508 | /* Table indicating the location of each and every register. */ | |
098caef4 | 509 | trad_frame_saved_reg *saved_regs; |
d95a8903 AC |
510 | }; |
511 | ||
512 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
513 | the saved registers of frame described by FRAME_INFO. This | |
514 | includes special registers such as pc and fp saved in special ways | |
515 | in the stack frame. sp is even more special: the address we return | |
025bb325 | 516 | for it IS the sp for the next frame. */ |
d95a8903 AC |
517 | |
518 | static struct m32r_unwind_cache * | |
8480a37e | 519 | m32r_frame_unwind_cache (const frame_info_ptr &this_frame, |
d95a8903 AC |
520 | void **this_prologue_cache) |
521 | { | |
cea15572 | 522 | CORE_ADDR pc, scan_limit; |
d95a8903 AC |
523 | ULONGEST prev_sp; |
524 | ULONGEST this_base; | |
22e048c9 | 525 | unsigned long op; |
d95a8903 AC |
526 | int i; |
527 | struct m32r_unwind_cache *info; | |
528 | ||
cea15572 | 529 | |
d95a8903 | 530 | if ((*this_prologue_cache)) |
9a3c8263 | 531 | return (struct m32r_unwind_cache *) (*this_prologue_cache); |
d95a8903 AC |
532 | |
533 | info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); | |
534 | (*this_prologue_cache) = info; | |
94afd7a6 | 535 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
d95a8903 AC |
536 | |
537 | info->size = 0; | |
538 | info->sp_offset = 0; | |
d95a8903 | 539 | info->uses_frame = 0; |
cea15572 | 540 | |
94afd7a6 UW |
541 | scan_limit = get_frame_pc (this_frame); |
542 | for (pc = get_frame_func (this_frame); | |
cea15572 | 543 | pc > 0 && pc < scan_limit; pc += 2) |
d95a8903 AC |
544 | { |
545 | if ((pc & 2) == 0) | |
546 | { | |
94afd7a6 | 547 | op = get_frame_memory_unsigned (this_frame, pc, 4); |
d95a8903 AC |
548 | if ((op & 0x80000000) == 0x80000000) |
549 | { | |
550 | /* 32-bit instruction */ | |
551 | if ((op & 0xffff0000) == 0x8faf0000) | |
552 | { | |
553 | /* add3 sp,sp,xxxx */ | |
554 | short n = op & 0xffff; | |
555 | info->sp_offset += n; | |
556 | } | |
cea15572 | 557 | else if (((op >> 8) == 0xe4) |
94afd7a6 | 558 | && get_frame_memory_unsigned (this_frame, pc + 2, |
7e3dd49e | 559 | 2) == 0x0f24) |
d95a8903 | 560 | { |
cea15572 | 561 | /* ld24 r4, xxxxxx; sub sp, r4 */ |
d95a8903 AC |
562 | unsigned long n = op & 0xffffff; |
563 | info->sp_offset += n; | |
cea15572 | 564 | pc += 2; /* skip sub instruction */ |
d95a8903 | 565 | } |
d95a8903 | 566 | |
cea15572 KI |
567 | if (pc == scan_limit) |
568 | scan_limit += 2; /* extend the search */ | |
569 | pc += 2; /* skip the immediate data */ | |
d95a8903 AC |
570 | continue; |
571 | } | |
572 | } | |
573 | ||
574 | /* 16-bit instructions */ | |
94afd7a6 | 575 | op = get_frame_memory_unsigned (this_frame, pc, 2) & 0x7fff; |
d95a8903 AC |
576 | if ((op & 0xf0ff) == 0x207f) |
577 | { | |
578 | /* st rn, @-sp */ | |
579 | int regno = ((op >> 8) & 0xf); | |
580 | info->sp_offset -= 4; | |
098caef4 | 581 | info->saved_regs[regno].set_addr (info->sp_offset); |
d95a8903 AC |
582 | } |
583 | else if ((op & 0xff00) == 0x4f00) | |
584 | { | |
585 | /* addi sp, xx */ | |
9ffbf372 | 586 | int n = (signed char) (op & 0xff); |
d95a8903 AC |
587 | info->sp_offset += n; |
588 | } | |
589 | else if (op == 0x1d8f) | |
590 | { | |
591 | /* mv fp, sp */ | |
592 | info->uses_frame = 1; | |
593 | info->r13_offset = info->sp_offset; | |
cea15572 KI |
594 | break; /* end of stack adjustments */ |
595 | } | |
596 | else if ((op & 0xfff0) == 0x10f0) | |
597 | { | |
025bb325 MS |
598 | /* End of prologue if this is a trap instruction. */ |
599 | break; /* End of stack adjustments. */ | |
d95a8903 | 600 | } |
d95a8903 AC |
601 | } |
602 | ||
603 | info->size = -info->sp_offset; | |
604 | ||
605 | /* Compute the previous frame's stack pointer (which is also the | |
606 | frame's ID's stack address), and this frame's base pointer. */ | |
607 | if (info->uses_frame) | |
608 | { | |
609 | /* The SP was moved to the FP. This indicates that a new frame | |
dda83cd7 SM |
610 | was created. Get THIS frame's FP value by unwinding it from |
611 | the next frame. */ | |
94afd7a6 | 612 | this_base = get_frame_register_unsigned (this_frame, M32R_FP_REGNUM); |
d95a8903 | 613 | /* The FP points at the last saved register. Adjust the FP back |
dda83cd7 | 614 | to before the first saved register giving the SP. */ |
d95a8903 AC |
615 | prev_sp = this_base + info->size; |
616 | } | |
617 | else | |
618 | { | |
619 | /* Assume that the FP is this frame's SP but with that pushed | |
dda83cd7 | 620 | stack space added back. */ |
94afd7a6 | 621 | this_base = get_frame_register_unsigned (this_frame, M32R_SP_REGNUM); |
d95a8903 AC |
622 | prev_sp = this_base + info->size; |
623 | } | |
624 | ||
625 | /* Convert that SP/BASE into real addresses. */ | |
626 | info->prev_sp = prev_sp; | |
627 | info->base = this_base; | |
628 | ||
629 | /* Adjust all the saved registers so that they contain addresses and | |
630 | not offsets. */ | |
94afd7a6 | 631 | for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) |
a9a87d35 | 632 | if (info->saved_regs[i].is_addr ()) |
098caef4 LM |
633 | info->saved_regs[i].set_addr (info->prev_sp |
634 | + info->saved_regs[i].addr ()); | |
d95a8903 AC |
635 | |
636 | /* The call instruction moves the caller's PC in the callee's LR. | |
637 | Since this is an unwind, do the reverse. Copy the location of LR | |
638 | into PC (the address / regnum) so that a request for PC will be | |
639 | converted into a request for the LR. */ | |
640 | info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; | |
641 | ||
642 | /* The previous frame's SP needed to be computed. Save the computed | |
643 | value. */ | |
a9a87d35 | 644 | info->saved_regs[M32R_SP_REGNUM].set_value (prev_sp); |
d95a8903 AC |
645 | |
646 | return info; | |
647 | } | |
648 | ||
d95a8903 | 649 | static CORE_ADDR |
7d9b040b | 650 | m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
d95a8903 | 651 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, |
cf84fa6b AH |
652 | struct value **args, CORE_ADDR sp, |
653 | function_call_return_method return_method, | |
d95a8903 AC |
654 | CORE_ADDR struct_addr) |
655 | { | |
e17a4113 | 656 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d95a8903 AC |
657 | int stack_offset, stack_alloc; |
658 | int argreg = ARG1_REGNUM; | |
659 | int argnum; | |
660 | struct type *type; | |
661 | enum type_code typecode; | |
662 | CORE_ADDR regval; | |
16ac4ab5 | 663 | gdb_byte *val; |
ab0538b8 | 664 | gdb_byte valbuf[M32R_ARG_REGISTER_SIZE]; |
d95a8903 | 665 | int len; |
d95a8903 | 666 | |
025bb325 | 667 | /* First force sp to a 4-byte alignment. */ |
d95a8903 AC |
668 | sp = sp & ~3; |
669 | ||
670 | /* Set the return address. For the m32r, the return breakpoint is | |
671 | always at BP_ADDR. */ | |
672 | regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); | |
673 | ||
674 | /* If STRUCT_RETURN is true, then the struct return address (in | |
675 | STRUCT_ADDR) will consume the first argument-passing register. | |
676 | Both adjust the register count and store that value. */ | |
cf84fa6b | 677 | if (return_method == return_method_struct) |
d95a8903 AC |
678 | { |
679 | regcache_cooked_write_unsigned (regcache, argreg, struct_addr); | |
680 | argreg++; | |
681 | } | |
682 | ||
025bb325 | 683 | /* Now make sure there's space on the stack. */ |
d95a8903 | 684 | for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) |
d0c97917 | 685 | stack_alloc += ((args[argnum]->type ()->length () + 3) & ~3); |
025bb325 | 686 | sp -= stack_alloc; /* Make room on stack for args. */ |
d95a8903 AC |
687 | |
688 | for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) | |
689 | { | |
d0c97917 | 690 | type = args[argnum]->type (); |
78134374 | 691 | typecode = type->code (); |
df86565b | 692 | len = type->length (); |
d95a8903 AC |
693 | |
694 | memset (valbuf, 0, sizeof (valbuf)); | |
695 | ||
696 | /* Passes structures that do not fit in 2 registers by reference. */ | |
697 | if (len > 8 | |
698 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
699 | { | |
e17a4113 | 700 | store_unsigned_integer (valbuf, 4, byte_order, |
9feb2d07 | 701 | args[argnum]->address ()); |
d95a8903 AC |
702 | typecode = TYPE_CODE_PTR; |
703 | len = 4; | |
704 | val = valbuf; | |
705 | } | |
706 | else if (len < 4) | |
707 | { | |
025bb325 | 708 | /* Value gets right-justified in the register or stack word. */ |
7e3dd49e | 709 | memcpy (valbuf + (register_size (gdbarch, argreg) - len), |
efaf1ae0 | 710 | (gdb_byte *) args[argnum]->contents ().data (), len); |
d95a8903 AC |
711 | val = valbuf; |
712 | } | |
713 | else | |
efaf1ae0 | 714 | val = (gdb_byte *) args[argnum]->contents ().data (); |
d95a8903 AC |
715 | |
716 | while (len > 0) | |
717 | { | |
718 | if (argreg > ARGN_REGNUM) | |
719 | { | |
025bb325 | 720 | /* Must go on the stack. */ |
d95a8903 AC |
721 | write_memory (sp + stack_offset, val, 4); |
722 | stack_offset += 4; | |
723 | } | |
724 | else if (argreg <= ARGN_REGNUM) | |
725 | { | |
025bb325 | 726 | /* There's room in a register. */ |
d95a8903 | 727 | regval = |
7e3dd49e | 728 | extract_unsigned_integer (val, |
e17a4113 UW |
729 | register_size (gdbarch, argreg), |
730 | byte_order); | |
d95a8903 AC |
731 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
732 | } | |
733 | ||
734 | /* Store the value 4 bytes at a time. This means that things | |
735 | larger than 4 bytes may go partly in registers and partly | |
736 | on the stack. */ | |
7e3dd49e AC |
737 | len -= register_size (gdbarch, argreg); |
738 | val += register_size (gdbarch, argreg); | |
d95a8903 AC |
739 | } |
740 | } | |
741 | ||
742 | /* Finally, update the SP register. */ | |
743 | regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); | |
744 | ||
745 | return sp; | |
746 | } | |
747 | ||
748 | ||
749 | /* Given a return value in `regbuf' with a type `valtype', | |
750 | extract and copy its value into `valbuf'. */ | |
751 | ||
752 | static void | |
753 | m32r_extract_return_value (struct type *type, struct regcache *regcache, | |
7c543f7b | 754 | gdb_byte *dst) |
d95a8903 | 755 | { |
ac7936df | 756 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 757 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
df86565b | 758 | int len = type->length (); |
d95a8903 AC |
759 | ULONGEST tmp; |
760 | ||
761 | /* By using store_unsigned_integer we avoid having to do | |
762 | anything special for small big-endian values. */ | |
763 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); | |
7c543f7b | 764 | store_unsigned_integer (dst, (len > 4 ? len - 4 : len), byte_order, tmp); |
d95a8903 AC |
765 | |
766 | /* Ignore return values more than 8 bytes in size because the m32r | |
025bb325 | 767 | returns anything more than 8 bytes in the stack. */ |
d95a8903 AC |
768 | if (len > 4) |
769 | { | |
770 | regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); | |
7c543f7b | 771 | store_unsigned_integer (dst + len - 4, 4, byte_order, tmp); |
d95a8903 AC |
772 | } |
773 | } | |
774 | ||
63807e1d | 775 | static enum return_value_convention |
6a3a010b | 776 | m32r_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
777 | struct type *valtype, struct regcache *regcache, |
778 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
14588880 | 779 | { |
df86565b | 780 | if (valtype->length () > 8) |
14588880 KI |
781 | return RETURN_VALUE_STRUCT_CONVENTION; |
782 | else | |
783 | { | |
784 | if (readbuf != NULL) | |
785 | m32r_extract_return_value (valtype, regcache, readbuf); | |
786 | if (writebuf != NULL) | |
787 | m32r_store_return_value (valtype, regcache, writebuf); | |
788 | return RETURN_VALUE_REGISTER_CONVENTION; | |
789 | } | |
790 | } | |
791 | ||
d95a8903 AC |
792 | /* Given a GDB frame, determine the address of the calling function's |
793 | frame. This will be used to create a new GDB frame struct. */ | |
794 | ||
795 | static void | |
8480a37e | 796 | m32r_frame_this_id (const frame_info_ptr &this_frame, |
d95a8903 AC |
797 | void **this_prologue_cache, struct frame_id *this_id) |
798 | { | |
799 | struct m32r_unwind_cache *info | |
94afd7a6 | 800 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
d95a8903 AC |
801 | CORE_ADDR base; |
802 | CORE_ADDR func; | |
3b7344d5 | 803 | struct bound_minimal_symbol msym_stack; |
d95a8903 AC |
804 | struct frame_id id; |
805 | ||
806 | /* The FUNC is easy. */ | |
94afd7a6 | 807 | func = get_frame_func (this_frame); |
d95a8903 | 808 | |
d95a8903 AC |
809 | /* Check if the stack is empty. */ |
810 | msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); | |
4aeddc50 | 811 | if (msym_stack.minsym && info->base == msym_stack.value_address ()) |
d95a8903 AC |
812 | return; |
813 | ||
814 | /* Hopefully the prologue analysis either correctly determined the | |
815 | frame's base (which is the SP from the previous frame), or set | |
816 | that base to "NULL". */ | |
817 | base = info->prev_sp; | |
818 | if (base == 0) | |
819 | return; | |
820 | ||
821 | id = frame_id_build (base, func); | |
d95a8903 AC |
822 | (*this_id) = id; |
823 | } | |
824 | ||
94afd7a6 | 825 | static struct value * |
8480a37e | 826 | m32r_frame_prev_register (const frame_info_ptr &this_frame, |
94afd7a6 | 827 | void **this_prologue_cache, int regnum) |
d95a8903 AC |
828 | { |
829 | struct m32r_unwind_cache *info | |
94afd7a6 UW |
830 | = m32r_frame_unwind_cache (this_frame, this_prologue_cache); |
831 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
d95a8903 AC |
832 | } |
833 | ||
834 | static const struct frame_unwind m32r_frame_unwind = { | |
a154d838 | 835 | "m32r prologue", |
d95a8903 | 836 | NORMAL_FRAME, |
8fbca658 | 837 | default_frame_unwind_stop_reason, |
d95a8903 | 838 | m32r_frame_this_id, |
94afd7a6 UW |
839 | m32r_frame_prev_register, |
840 | NULL, | |
841 | default_frame_sniffer | |
d95a8903 AC |
842 | }; |
843 | ||
d95a8903 | 844 | static CORE_ADDR |
8480a37e | 845 | m32r_frame_base_address (const frame_info_ptr &this_frame, void **this_cache) |
d95a8903 AC |
846 | { |
847 | struct m32r_unwind_cache *info | |
94afd7a6 | 848 | = m32r_frame_unwind_cache (this_frame, this_cache); |
d95a8903 AC |
849 | return info->base; |
850 | } | |
851 | ||
852 | static const struct frame_base m32r_frame_base = { | |
853 | &m32r_frame_unwind, | |
854 | m32r_frame_base_address, | |
855 | m32r_frame_base_address, | |
856 | m32r_frame_base_address | |
857 | }; | |
858 | ||
d95a8903 AC |
859 | static gdbarch_init_ftype m32r_gdbarch_init; |
860 | ||
861 | static struct gdbarch * | |
862 | m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
863 | { | |
d95a8903 AC |
864 | /* If there is already a candidate, use it. */ |
865 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
866 | if (arches != NULL) | |
867 | return arches->gdbarch; | |
868 | ||
869 | /* Allocate space for the new architecture. */ | |
2b16913c SM |
870 | gdbarch *gdbarch |
871 | = gdbarch_alloc (&info, gdbarch_tdep_up (new m32r_gdbarch_tdep)); | |
d95a8903 | 872 | |
53375380 PA |
873 | set_gdbarch_wchar_bit (gdbarch, 16); |
874 | set_gdbarch_wchar_signed (gdbarch, 0); | |
875 | ||
e839132d | 876 | set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); |
d27b54ad | 877 | set_gdbarch_pc_regnum (gdbarch, M32R_PC_REGNUM); |
d95a8903 AC |
878 | set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); |
879 | set_gdbarch_register_name (gdbarch, m32r_register_name); | |
880 | set_gdbarch_register_type (gdbarch, m32r_register_type); | |
881 | ||
d95a8903 | 882 | set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); |
14588880 | 883 | set_gdbarch_return_value (gdbarch, m32r_return_value); |
d95a8903 AC |
884 | |
885 | set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); | |
886 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
04180708 YQ |
887 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, m32r_breakpoint_kind_from_pc); |
888 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, m32r_sw_breakpoint_from_kind); | |
d95a8903 AC |
889 | set_gdbarch_memory_insert_breakpoint (gdbarch, |
890 | m32r_memory_insert_breakpoint); | |
891 | set_gdbarch_memory_remove_breakpoint (gdbarch, | |
892 | m32r_memory_remove_breakpoint); | |
893 | ||
d95a8903 AC |
894 | set_gdbarch_frame_align (gdbarch, m32r_frame_align); |
895 | ||
d95a8903 AC |
896 | frame_base_set_default (gdbarch, &m32r_frame_base); |
897 | ||
c46b0409 KI |
898 | /* Hook in ABI-specific overrides, if they have been registered. */ |
899 | gdbarch_init_osabi (info, gdbarch); | |
900 | ||
901 | /* Hook in the default unwinders. */ | |
94afd7a6 | 902 | frame_unwind_append_unwinder (gdbarch, &m32r_frame_unwind); |
c46b0409 | 903 | |
1c772458 UW |
904 | /* Support simple overlay manager. */ |
905 | set_gdbarch_overlay_update (gdbarch, simple_overlay_update); | |
906 | ||
d95a8903 AC |
907 | return gdbarch; |
908 | } | |
909 | ||
6c265988 | 910 | void _initialize_m32r_tdep (); |
d95a8903 | 911 | void |
6c265988 | 912 | _initialize_m32r_tdep () |
d95a8903 | 913 | { |
ec29a63c | 914 | gdbarch_register (bfd_arch_m32r, m32r_gdbarch_init); |
d95a8903 | 915 | } |