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1 | /* Target-dependent code for the Toshiba MeP for GDB, the GNU debugger. |
2 | ||
213516ef | 3 | Copyright (C) 2001-2023 Free Software Foundation, Inc. |
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4 | |
5 | Contributed by Red Hat, Inc. | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 11 | the Free Software Foundation; either version 3 of the License, or |
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12 | (at your option) any later version. |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
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21 | |
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "frame-unwind.h" | |
25 | #include "frame-base.h" | |
26 | #include "symtab.h" | |
27 | #include "gdbtypes.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "gdbcore.h" | |
aeb43123 KB |
30 | #include "value.h" |
31 | #include "inferior.h" | |
32 | #include "dis-asm.h" | |
33 | #include "symfile.h" | |
34 | #include "objfiles.h" | |
35 | #include "language.h" | |
36 | #include "arch-utils.h" | |
37 | #include "regcache.h" | |
38 | #include "remote.h" | |
aeb43123 | 39 | #include "sim-regno.h" |
aeb43123 KB |
40 | #include "trad-frame.h" |
41 | #include "reggroups.h" | |
42 | #include "elf-bfd.h" | |
43 | #include "elf/mep.h" | |
44 | #include "prologue-value.h" | |
342b5fef | 45 | #include "cgen/bitset.h" |
aeb43123 | 46 | #include "infcall.h" |
76eb8ef1 | 47 | #include "gdbarch.h" |
aeb43123 | 48 | |
aeb43123 | 49 | /* Get the user's customized MeP coprocessor register names from |
883d90a0 TV |
50 | libopcodes. Make cgen names unique to prevent ODR conflicts with other |
51 | targets. */ | |
52 | #define GDB_CGEN_REMAP_PREFIX mep | |
53 | #include "cgen-remap.h" | |
f16f7b7c TT |
54 | #include "opcodes/mep-desc.h" |
55 | #include "opcodes/mep-opc.h" | |
aeb43123 KB |
56 | |
57 | \f | |
58 | /* The gdbarch_tdep structure. */ | |
59 | ||
60 | /* A quick recap for GDB hackers not familiar with the whole Toshiba | |
61 | Media Processor story: | |
62 | ||
63 | The MeP media engine is a configureable processor: users can design | |
64 | their own coprocessors, implement custom instructions, adjust cache | |
65 | sizes, select optional standard facilities like add-and-saturate | |
66 | instructions, and so on. Then, they can build custom versions of | |
67 | the GNU toolchain to support their customized chips. The | |
68 | MeP-Integrator program (see utils/mep) takes a GNU toolchain source | |
69 | tree, and a config file pointing to various files provided by the | |
70 | user describing their customizations, and edits the source tree to | |
71 | produce a compiler that can generate their custom instructions, an | |
72 | assembler that can assemble them and recognize their custom | |
73 | register names, and so on. | |
74 | ||
75 | Furthermore, the user can actually specify several of these custom | |
76 | configurations, called 'me_modules', and get a toolchain which can | |
77 | produce code for any of them, given a compiler/assembler switch; | |
78 | you say something like 'gcc -mconfig=mm_max' to generate code for | |
79 | the me_module named 'mm_max'. | |
80 | ||
81 | GDB, in particular, needs to: | |
82 | ||
83 | - use the coprocessor control register names provided by the user | |
84 | in their hardware description, in expressions, 'info register' | |
85 | output, and disassembly, | |
86 | ||
87 | - know the number, names, and types of the coprocessor's | |
88 | general-purpose registers, adjust the 'info all-registers' output | |
89 | accordingly, and print error messages if the user refers to one | |
90 | that doesn't exist | |
91 | ||
92 | - allow access to the control bus space only when the configuration | |
93 | actually has a control bus, and recognize which regions of the | |
94 | control bus space are actually populated, | |
95 | ||
96 | - disassemble using the user's provided mnemonics for their custom | |
97 | instructions, and | |
98 | ||
99 | - recognize whether the $hi and $lo registers are present, and | |
100 | allow access to them only when they are actually there. | |
101 | ||
102 | There are three sources of information about what sort of me_module | |
103 | we're actually dealing with: | |
104 | ||
105 | - A MeP executable file indicates which me_module it was compiled | |
106 | for, and libopcodes has tables describing each module. So, given | |
107 | an executable file, we can find out about the processor it was | |
108 | compiled for. | |
109 | ||
110 | - There are SID command-line options to select a particular | |
111 | me_module, overriding the one specified in the ELF file. SID | |
112 | provides GDB with a fake read-only register, 'module', which | |
113 | indicates which me_module GDB is communicating with an instance | |
114 | of. | |
115 | ||
116 | - There are SID command-line options to enable or disable certain | |
117 | optional processor features, overriding the defaults for the | |
118 | selected me_module. The MeP $OPT register indicates which | |
119 | options are present on the current processor. */ | |
120 | ||
121 | ||
ab25d9bb | 122 | struct mep_gdbarch_tdep : gdbarch_tdep_base |
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123 | { |
124 | /* A CGEN cpu descriptor for this BFD architecture and machine. | |
125 | ||
126 | Note: this is *not* customized for any particular me_module; the | |
127 | MeP libopcodes machinery actually puts off module-specific | |
128 | customization until the last minute. So this contains | |
129 | information about all supported me_modules. */ | |
345bd07c | 130 | CGEN_CPU_DESC cpu_desc = nullptr; |
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131 | |
132 | /* The me_module index from the ELF file we used to select this | |
133 | architecture, or CONFIG_NONE if there was none. | |
134 | ||
135 | Note that we should prefer to use the me_module number available | |
136 | via the 'module' register, whenever we're actually talking to a | |
137 | real target. | |
138 | ||
139 | In the absence of live information, we'd like to get the | |
140 | me_module number from the ELF file. But which ELF file: the | |
141 | executable file, the core file, ... ? The answer is, "the last | |
142 | ELF file we used to set the current architecture". Thus, we | |
143 | create a separate instance of the gdbarch structure for each | |
144 | me_module value mep_gdbarch_init sees, and store the me_module | |
145 | value from the ELF file here. */ | |
345bd07c | 146 | CONFIG_ATTR me_module {}; |
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147 | }; |
148 | ||
149 | ||
150 | \f | |
151 | /* Getting me_module information from the CGEN tables. */ | |
152 | ||
153 | ||
154 | /* Find an entry in the DESC's hardware table whose name begins with | |
155 | PREFIX, and whose ISA mask intersects COPRO_ISA_MASK, but does not | |
156 | intersect with GENERIC_ISA_MASK. If there is no matching entry, | |
157 | return zero. */ | |
158 | static const CGEN_HW_ENTRY * | |
159 | find_hw_entry_by_prefix_and_isa (CGEN_CPU_DESC desc, | |
dda83cd7 SM |
160 | const char *prefix, |
161 | CGEN_BITSET *copro_isa_mask, | |
162 | CGEN_BITSET *generic_isa_mask) | |
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163 | { |
164 | int prefix_len = strlen (prefix); | |
165 | int i; | |
166 | ||
167 | for (i = 0; i < desc->hw_table.num_entries; i++) | |
168 | { | |
169 | const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i]; | |
170 | if (strncmp (prefix, hw->name, prefix_len) == 0) | |
dda83cd7 SM |
171 | { |
172 | CGEN_BITSET *hw_isa_mask | |
173 | = ((CGEN_BITSET *) | |
174 | &CGEN_ATTR_CGEN_HW_ISA_VALUE (CGEN_HW_ATTRS (hw))); | |
175 | ||
176 | if (cgen_bitset_intersect_p (hw_isa_mask, copro_isa_mask) | |
177 | && ! cgen_bitset_intersect_p (hw_isa_mask, generic_isa_mask)) | |
178 | return hw; | |
179 | } | |
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180 | } |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | ||
186 | /* Find an entry in DESC's hardware table whose type is TYPE. Return | |
187 | zero if there is none. */ | |
188 | static const CGEN_HW_ENTRY * | |
189 | find_hw_entry_by_type (CGEN_CPU_DESC desc, CGEN_HW_TYPE type) | |
190 | { | |
191 | int i; | |
192 | ||
193 | for (i = 0; i < desc->hw_table.num_entries; i++) | |
194 | { | |
195 | const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i]; | |
196 | ||
197 | if (hw->type == type) | |
dda83cd7 | 198 | return hw; |
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199 | } |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
204 | ||
205 | /* Return the CGEN hardware table entry for the coprocessor register | |
206 | set for ME_MODULE, whose name prefix is PREFIX. If ME_MODULE has | |
207 | no such register set, return zero. If ME_MODULE is the generic | |
208 | me_module CONFIG_NONE, return the table entry for the register set | |
209 | whose hardware type is GENERIC_TYPE. */ | |
210 | static const CGEN_HW_ENTRY * | |
211 | me_module_register_set (CONFIG_ATTR me_module, | |
dda83cd7 SM |
212 | const char *prefix, |
213 | CGEN_HW_TYPE generic_type) | |
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214 | { |
215 | /* This is kind of tricky, because the hardware table is constructed | |
216 | in a way that isn't very helpful. Perhaps we can fix that, but | |
217 | here's how it works at the moment: | |
218 | ||
219 | The configuration map, `mep_config_map', is indexed by me_module | |
220 | number, and indicates which coprocessor and core ISAs that | |
221 | me_module supports. The 'core_isa' mask includes all the core | |
222 | ISAs, and the 'cop_isa' mask includes all the coprocessor ISAs. | |
223 | The entry for the generic me_module, CONFIG_NONE, has an empty | |
224 | 'cop_isa', and its 'core_isa' selects only the standard MeP | |
225 | instruction set. | |
226 | ||
227 | The CGEN CPU descriptor's hardware table, desc->hw_table, has | |
228 | entries for all the register sets, for all me_modules. Each | |
229 | entry has a mask indicating which ISAs use that register set. | |
230 | So, if an me_module supports some coprocessor ISA, we can find | |
231 | applicable register sets by scanning the hardware table for | |
232 | register sets whose masks include (at least some of) those ISAs. | |
233 | ||
234 | Each hardware table entry also has a name, whose prefix says | |
235 | whether it's a general-purpose ("h-cr") or control ("h-ccr") | |
236 | coprocessor register set. It might be nicer to have an attribute | |
237 | indicating what sort of register set it was, that we could use | |
238 | instead of pattern-matching on the name. | |
239 | ||
240 | When there is no hardware table entry whose mask includes a | |
241 | particular coprocessor ISA and whose name starts with a given | |
242 | prefix, then that means that that coprocessor doesn't have any | |
243 | registers of that type. In such cases, this function must return | |
244 | a null pointer. | |
245 | ||
246 | Coprocessor register sets' masks may or may not include the core | |
247 | ISA for the me_module they belong to. Those generated by a2cgen | |
248 | do, but the sample me_module included in the unconfigured tree, | |
249 | 'ccfx', does not. | |
250 | ||
251 | There are generic coprocessor register sets, intended only for | |
252 | use with the generic me_module. Unfortunately, their masks | |
253 | include *all* ISAs --- even those for coprocessors that don't | |
254 | have such register sets. This makes detecting the case where a | |
255 | coprocessor lacks a particular register set more complicated. | |
256 | ||
257 | So, here's the approach we take: | |
258 | ||
259 | - For CONFIG_NONE, we return the generic coprocessor register set. | |
260 | ||
261 | - For any other me_module, we search for a register set whose | |
262 | mask contains any of the me_module's coprocessor ISAs, | |
263 | specifically excluding the generic coprocessor register sets. */ | |
264 | ||
345bd07c | 265 | mep_gdbarch_tdep *tdep |
99d9c3b9 | 266 | = gdbarch_tdep<mep_gdbarch_tdep> (current_inferior ()->arch ()); |
345bd07c | 267 | CGEN_CPU_DESC desc = tdep->cpu_desc; |
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268 | const CGEN_HW_ENTRY *hw; |
269 | ||
270 | if (me_module == CONFIG_NONE) | |
271 | hw = find_hw_entry_by_type (desc, generic_type); | |
272 | else | |
273 | { | |
274 | CGEN_BITSET *cop = &mep_config_map[me_module].cop_isa; | |
275 | CGEN_BITSET *core = &mep_config_map[me_module].core_isa; | |
276 | CGEN_BITSET *generic = &mep_config_map[CONFIG_NONE].core_isa; | |
277 | CGEN_BITSET *cop_and_core; | |
278 | ||
279 | /* The coprocessor ISAs include the ISA for the specific core which | |
280 | has that coprocessor. */ | |
281 | cop_and_core = cgen_bitset_copy (cop); | |
282 | cgen_bitset_union (cop, core, cop_and_core); | |
283 | hw = find_hw_entry_by_prefix_and_isa (desc, prefix, cop_and_core, generic); | |
284 | } | |
285 | ||
286 | return hw; | |
287 | } | |
288 | ||
289 | ||
290 | /* Given a hardware table entry HW representing a register set, return | |
291 | a pointer to the keyword table with all the register names. If HW | |
85102364 | 292 | is NULL, return NULL, to propagate the "no such register set" info |
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293 | along. */ |
294 | static CGEN_KEYWORD * | |
295 | register_set_keyword_table (const CGEN_HW_ENTRY *hw) | |
296 | { | |
297 | if (! hw) | |
298 | return NULL; | |
299 | ||
300 | /* Check that HW is actually a keyword table. */ | |
301 | gdb_assert (hw->asm_type == CGEN_ASM_KEYWORD); | |
302 | ||
303 | /* The 'asm_data' field of a register set's hardware table entry | |
304 | refers to a keyword table. */ | |
305 | return (CGEN_KEYWORD *) hw->asm_data; | |
306 | } | |
307 | ||
308 | ||
309 | /* Given a keyword table KEYWORD and a register number REGNUM, return | |
310 | the name of the register, or "" if KEYWORD contains no register | |
311 | whose number is REGNUM. */ | |
a121b7c1 | 312 | static const char * |
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313 | register_name_from_keyword (CGEN_KEYWORD *keyword_table, int regnum) |
314 | { | |
315 | const CGEN_KEYWORD_ENTRY *entry | |
316 | = cgen_keyword_lookup_value (keyword_table, regnum); | |
317 | ||
318 | if (entry) | |
319 | { | |
320 | char *name = entry->name; | |
321 | ||
322 | /* The CGEN keyword entries for register names include the | |
dda83cd7 SM |
323 | leading $, which appears in MeP assembly as well as in GDB. |
324 | But we don't want to return that; GDB core code adds that | |
325 | itself. */ | |
aeb43123 | 326 | if (name[0] == '$') |
dda83cd7 | 327 | name++; |
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328 | |
329 | return name; | |
330 | } | |
331 | else | |
332 | return ""; | |
333 | } | |
334 | ||
335 | ||
336 | /* Masks for option bits in the OPT special-purpose register. */ | |
337 | enum { | |
338 | MEP_OPT_DIV = 1 << 25, /* 32-bit divide instruction option */ | |
339 | MEP_OPT_MUL = 1 << 24, /* 32-bit multiply instruction option */ | |
340 | MEP_OPT_BIT = 1 << 23, /* bit manipulation instruction option */ | |
341 | MEP_OPT_SAT = 1 << 22, /* saturation instruction option */ | |
342 | MEP_OPT_CLP = 1 << 21, /* clip instruction option */ | |
343 | MEP_OPT_MIN = 1 << 20, /* min/max instruction option */ | |
344 | MEP_OPT_AVE = 1 << 19, /* average instruction option */ | |
345 | MEP_OPT_ABS = 1 << 18, /* absolute difference instruction option */ | |
346 | MEP_OPT_LDZ = 1 << 16, /* leading zero instruction option */ | |
347 | MEP_OPT_VL64 = 1 << 6, /* 64-bit VLIW operation mode option */ | |
348 | MEP_OPT_VL32 = 1 << 5, /* 32-bit VLIW operation mode option */ | |
349 | MEP_OPT_COP = 1 << 4, /* coprocessor option */ | |
350 | MEP_OPT_DSP = 1 << 2, /* DSP option */ | |
351 | MEP_OPT_UCI = 1 << 1, /* UCI option */ | |
352 | MEP_OPT_DBG = 1 << 0, /* DBG function option */ | |
353 | }; | |
354 | ||
355 | ||
356 | /* Given the option_mask value for a particular entry in | |
357 | mep_config_map, produce the value the processor's OPT register | |
358 | would use to represent the same set of options. */ | |
359 | static unsigned int | |
360 | opt_from_option_mask (unsigned int option_mask) | |
361 | { | |
362 | /* A table mapping OPT register bits onto CGEN config map option | |
363 | bits. */ | |
364 | struct { | |
365 | unsigned int opt_bit, option_mask_bit; | |
366 | } bits[] = { | |
367 | { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN }, | |
368 | { MEP_OPT_MUL, 1 << CGEN_INSN_OPTIONAL_MUL_INSN }, | |
369 | { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN }, | |
370 | { MEP_OPT_DBG, 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN }, | |
371 | { MEP_OPT_LDZ, 1 << CGEN_INSN_OPTIONAL_LDZ_INSN }, | |
372 | { MEP_OPT_ABS, 1 << CGEN_INSN_OPTIONAL_ABS_INSN }, | |
373 | { MEP_OPT_AVE, 1 << CGEN_INSN_OPTIONAL_AVE_INSN }, | |
374 | { MEP_OPT_MIN, 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN }, | |
375 | { MEP_OPT_CLP, 1 << CGEN_INSN_OPTIONAL_CLIP_INSN }, | |
376 | { MEP_OPT_SAT, 1 << CGEN_INSN_OPTIONAL_SAT_INSN }, | |
377 | { MEP_OPT_UCI, 1 << CGEN_INSN_OPTIONAL_UCI_INSN }, | |
378 | { MEP_OPT_DSP, 1 << CGEN_INSN_OPTIONAL_DSP_INSN }, | |
379 | { MEP_OPT_COP, 1 << CGEN_INSN_OPTIONAL_CP_INSN }, | |
380 | }; | |
381 | ||
382 | int i; | |
383 | unsigned int opt = 0; | |
384 | ||
385 | for (i = 0; i < (sizeof (bits) / sizeof (bits[0])); i++) | |
386 | if (option_mask & bits[i].option_mask_bit) | |
387 | opt |= bits[i].opt_bit; | |
388 | ||
389 | return opt; | |
390 | } | |
391 | ||
392 | ||
393 | /* Return the value the $OPT register would use to represent the set | |
394 | of options for ME_MODULE. */ | |
395 | static unsigned int | |
396 | me_module_opt (CONFIG_ATTR me_module) | |
397 | { | |
398 | return opt_from_option_mask (mep_config_map[me_module].option_mask); | |
399 | } | |
400 | ||
401 | ||
402 | /* Return the width of ME_MODULE's coprocessor data bus, in bits. | |
403 | This is either 32 or 64. */ | |
404 | static int | |
405 | me_module_cop_data_bus_width (CONFIG_ATTR me_module) | |
406 | { | |
407 | if (mep_config_map[me_module].option_mask | |
408 | & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) | |
409 | return 64; | |
410 | else | |
411 | return 32; | |
412 | } | |
413 | ||
414 | ||
415 | /* Return true if ME_MODULE is big-endian, false otherwise. */ | |
416 | static int | |
417 | me_module_big_endian (CONFIG_ATTR me_module) | |
418 | { | |
419 | return mep_config_map[me_module].big_endian; | |
420 | } | |
421 | ||
422 | ||
423 | /* Return the name of ME_MODULE, or NULL if it has no name. */ | |
424 | static const char * | |
425 | me_module_name (CONFIG_ATTR me_module) | |
426 | { | |
427 | /* The default me_module has "" as its name, but it's easier for our | |
428 | callers to test for NULL. */ | |
429 | if (! mep_config_map[me_module].name | |
430 | || mep_config_map[me_module].name[0] == '\0') | |
431 | return NULL; | |
432 | else | |
433 | return mep_config_map[me_module].name; | |
434 | } | |
435 | \f | |
436 | /* Register set. */ | |
437 | ||
438 | ||
439 | /* The MeP spec defines the following registers: | |
440 | 16 general purpose registers (r0-r15) | |
441 | 32 control/special registers (csr0-csr31) | |
442 | 32 coprocessor general-purpose registers (c0 -- c31) | |
443 | 64 coprocessor control registers (ccr0 -- ccr63) | |
444 | ||
445 | For the raw registers, we assign numbers here explicitly, instead | |
446 | of letting the enum assign them for us; the numbers are a matter of | |
447 | external protocol, and shouldn't shift around as things are edited. | |
448 | ||
449 | We access the control/special registers via pseudoregisters, to | |
450 | enforce read-only portions that some registers have. | |
451 | ||
452 | We access the coprocessor general purpose and control registers via | |
453 | pseudoregisters, to make sure they appear in the proper order in | |
454 | the 'info all-registers' command (which uses the register number | |
455 | ordering), and also to allow them to be renamed and resized | |
456 | depending on the me_module in use. | |
457 | ||
458 | The MeP allows coprocessor general-purpose registers to be either | |
459 | 32 or 64 bits long, depending on the configuration. Since we don't | |
460 | want the format of the 'g' packet to vary from one core to another, | |
461 | the raw coprocessor GPRs are always 64 bits. GDB doesn't allow the | |
462 | types of registers to change (see the implementation of | |
463 | register_type), so we have four banks of pseudoregisters for the | |
464 | coprocessor gprs --- 32-bit vs. 64-bit, and integer | |
465 | vs. floating-point --- and we show or hide them depending on the | |
466 | configuration. */ | |
467 | enum | |
468 | { | |
469 | MEP_FIRST_RAW_REGNUM = 0, | |
470 | ||
471 | MEP_FIRST_GPR_REGNUM = 0, | |
472 | MEP_R0_REGNUM = 0, | |
473 | MEP_R1_REGNUM = 1, | |
474 | MEP_R2_REGNUM = 2, | |
475 | MEP_R3_REGNUM = 3, | |
476 | MEP_R4_REGNUM = 4, | |
477 | MEP_R5_REGNUM = 5, | |
478 | MEP_R6_REGNUM = 6, | |
479 | MEP_R7_REGNUM = 7, | |
480 | MEP_R8_REGNUM = 8, | |
481 | MEP_R9_REGNUM = 9, | |
482 | MEP_R10_REGNUM = 10, | |
483 | MEP_R11_REGNUM = 11, | |
484 | MEP_R12_REGNUM = 12, | |
485 | MEP_FP_REGNUM = MEP_R8_REGNUM, | |
486 | MEP_R13_REGNUM = 13, | |
487 | MEP_TP_REGNUM = MEP_R13_REGNUM, /* (r13) Tiny data pointer */ | |
488 | MEP_R14_REGNUM = 14, | |
489 | MEP_GP_REGNUM = MEP_R14_REGNUM, /* (r14) Global pointer */ | |
490 | MEP_R15_REGNUM = 15, | |
491 | MEP_SP_REGNUM = MEP_R15_REGNUM, /* (r15) Stack pointer */ | |
492 | MEP_LAST_GPR_REGNUM = MEP_R15_REGNUM, | |
493 | ||
494 | /* The raw control registers. These are the values as received via | |
495 | the remote protocol, directly from the target; we only let user | |
496 | code touch the via the pseudoregisters, which enforce read-only | |
497 | bits. */ | |
498 | MEP_FIRST_RAW_CSR_REGNUM = 16, | |
499 | MEP_RAW_PC_REGNUM = 16, /* Program counter */ | |
500 | MEP_RAW_LP_REGNUM = 17, /* Link pointer */ | |
501 | MEP_RAW_SAR_REGNUM = 18, /* Raw shift amount */ | |
502 | MEP_RAW_CSR3_REGNUM = 19, /* csr3: reserved */ | |
503 | MEP_RAW_RPB_REGNUM = 20, /* Raw repeat begin address */ | |
504 | MEP_RAW_RPE_REGNUM = 21, /* Repeat end address */ | |
505 | MEP_RAW_RPC_REGNUM = 22, /* Repeat count */ | |
506 | MEP_RAW_HI_REGNUM = 23, /* Upper 32 bits of result of 64 bit mult/div */ | |
507 | MEP_RAW_LO_REGNUM = 24, /* Lower 32 bits of result of 64 bit mult/div */ | |
508 | MEP_RAW_CSR9_REGNUM = 25, /* csr3: reserved */ | |
509 | MEP_RAW_CSR10_REGNUM = 26, /* csr3: reserved */ | |
510 | MEP_RAW_CSR11_REGNUM = 27, /* csr3: reserved */ | |
511 | MEP_RAW_MB0_REGNUM = 28, /* Raw modulo begin address 0 */ | |
512 | MEP_RAW_ME0_REGNUM = 29, /* Raw modulo end address 0 */ | |
513 | MEP_RAW_MB1_REGNUM = 30, /* Raw modulo begin address 1 */ | |
514 | MEP_RAW_ME1_REGNUM = 31, /* Raw modulo end address 1 */ | |
515 | MEP_RAW_PSW_REGNUM = 32, /* Raw program status word */ | |
516 | MEP_RAW_ID_REGNUM = 33, /* Raw processor ID/revision */ | |
517 | MEP_RAW_TMP_REGNUM = 34, /* Temporary */ | |
518 | MEP_RAW_EPC_REGNUM = 35, /* Exception program counter */ | |
519 | MEP_RAW_EXC_REGNUM = 36, /* Raw exception cause */ | |
520 | MEP_RAW_CFG_REGNUM = 37, /* Raw processor configuration*/ | |
521 | MEP_RAW_CSR22_REGNUM = 38, /* csr3: reserved */ | |
522 | MEP_RAW_NPC_REGNUM = 39, /* Nonmaskable interrupt PC */ | |
523 | MEP_RAW_DBG_REGNUM = 40, /* Raw debug */ | |
524 | MEP_RAW_DEPC_REGNUM = 41, /* Debug exception PC */ | |
525 | MEP_RAW_OPT_REGNUM = 42, /* Raw options */ | |
526 | MEP_RAW_RCFG_REGNUM = 43, /* Raw local ram config */ | |
527 | MEP_RAW_CCFG_REGNUM = 44, /* Raw cache config */ | |
528 | MEP_RAW_CSR29_REGNUM = 45, /* csr3: reserved */ | |
529 | MEP_RAW_CSR30_REGNUM = 46, /* csr3: reserved */ | |
530 | MEP_RAW_CSR31_REGNUM = 47, /* csr3: reserved */ | |
531 | MEP_LAST_RAW_CSR_REGNUM = MEP_RAW_CSR31_REGNUM, | |
532 | ||
533 | /* The raw coprocessor general-purpose registers. These are all 64 | |
534 | bits wide. */ | |
535 | MEP_FIRST_RAW_CR_REGNUM = 48, | |
536 | MEP_LAST_RAW_CR_REGNUM = MEP_FIRST_RAW_CR_REGNUM + 31, | |
537 | ||
538 | MEP_FIRST_RAW_CCR_REGNUM = 80, | |
539 | MEP_LAST_RAW_CCR_REGNUM = MEP_FIRST_RAW_CCR_REGNUM + 63, | |
540 | ||
541 | /* The module number register. This is the index of the me_module | |
542 | of which the current target is an instance. (This is not a real | |
543 | MeP-specified register; it's provided by SID.) */ | |
544 | MEP_MODULE_REGNUM, | |
545 | ||
546 | MEP_LAST_RAW_REGNUM = MEP_MODULE_REGNUM, | |
547 | ||
548 | MEP_NUM_RAW_REGS = MEP_LAST_RAW_REGNUM + 1, | |
549 | ||
550 | /* Pseudoregisters. See mep_pseudo_register_read and | |
551 | mep_pseudo_register_write. */ | |
552 | MEP_FIRST_PSEUDO_REGNUM = MEP_NUM_RAW_REGS, | |
553 | ||
554 | /* We have a pseudoregister for every control/special register, to | |
555 | implement registers with read-only bits. */ | |
556 | MEP_FIRST_CSR_REGNUM = MEP_FIRST_PSEUDO_REGNUM, | |
557 | MEP_PC_REGNUM = MEP_FIRST_CSR_REGNUM, /* Program counter */ | |
558 | MEP_LP_REGNUM, /* Link pointer */ | |
559 | MEP_SAR_REGNUM, /* shift amount */ | |
560 | MEP_CSR3_REGNUM, /* csr3: reserved */ | |
561 | MEP_RPB_REGNUM, /* repeat begin address */ | |
562 | MEP_RPE_REGNUM, /* Repeat end address */ | |
563 | MEP_RPC_REGNUM, /* Repeat count */ | |
564 | MEP_HI_REGNUM, /* Upper 32 bits of the result of 64 bit mult/div */ | |
565 | MEP_LO_REGNUM, /* Lower 32 bits of the result of 64 bit mult/div */ | |
566 | MEP_CSR9_REGNUM, /* csr3: reserved */ | |
567 | MEP_CSR10_REGNUM, /* csr3: reserved */ | |
568 | MEP_CSR11_REGNUM, /* csr3: reserved */ | |
569 | MEP_MB0_REGNUM, /* modulo begin address 0 */ | |
570 | MEP_ME0_REGNUM, /* modulo end address 0 */ | |
571 | MEP_MB1_REGNUM, /* modulo begin address 1 */ | |
572 | MEP_ME1_REGNUM, /* modulo end address 1 */ | |
573 | MEP_PSW_REGNUM, /* program status word */ | |
574 | MEP_ID_REGNUM, /* processor ID/revision */ | |
575 | MEP_TMP_REGNUM, /* Temporary */ | |
576 | MEP_EPC_REGNUM, /* Exception program counter */ | |
577 | MEP_EXC_REGNUM, /* exception cause */ | |
578 | MEP_CFG_REGNUM, /* processor configuration*/ | |
579 | MEP_CSR22_REGNUM, /* csr3: reserved */ | |
580 | MEP_NPC_REGNUM, /* Nonmaskable interrupt PC */ | |
581 | MEP_DBG_REGNUM, /* debug */ | |
582 | MEP_DEPC_REGNUM, /* Debug exception PC */ | |
583 | MEP_OPT_REGNUM, /* options */ | |
584 | MEP_RCFG_REGNUM, /* local ram config */ | |
585 | MEP_CCFG_REGNUM, /* cache config */ | |
586 | MEP_CSR29_REGNUM, /* csr3: reserved */ | |
587 | MEP_CSR30_REGNUM, /* csr3: reserved */ | |
588 | MEP_CSR31_REGNUM, /* csr3: reserved */ | |
589 | MEP_LAST_CSR_REGNUM = MEP_CSR31_REGNUM, | |
590 | ||
591 | /* The 32-bit integer view of the coprocessor GPR's. */ | |
592 | MEP_FIRST_CR32_REGNUM, | |
593 | MEP_LAST_CR32_REGNUM = MEP_FIRST_CR32_REGNUM + 31, | |
594 | ||
595 | /* The 32-bit floating-point view of the coprocessor GPR's. */ | |
596 | MEP_FIRST_FP_CR32_REGNUM, | |
597 | MEP_LAST_FP_CR32_REGNUM = MEP_FIRST_FP_CR32_REGNUM + 31, | |
598 | ||
599 | /* The 64-bit integer view of the coprocessor GPR's. */ | |
600 | MEP_FIRST_CR64_REGNUM, | |
601 | MEP_LAST_CR64_REGNUM = MEP_FIRST_CR64_REGNUM + 31, | |
602 | ||
603 | /* The 64-bit floating-point view of the coprocessor GPR's. */ | |
604 | MEP_FIRST_FP_CR64_REGNUM, | |
605 | MEP_LAST_FP_CR64_REGNUM = MEP_FIRST_FP_CR64_REGNUM + 31, | |
606 | ||
607 | MEP_FIRST_CCR_REGNUM, | |
608 | MEP_LAST_CCR_REGNUM = MEP_FIRST_CCR_REGNUM + 63, | |
609 | ||
610 | MEP_LAST_PSEUDO_REGNUM = MEP_LAST_CCR_REGNUM, | |
611 | ||
612 | MEP_NUM_PSEUDO_REGS = (MEP_LAST_PSEUDO_REGNUM - MEP_LAST_RAW_REGNUM), | |
613 | ||
614 | MEP_NUM_REGS = MEP_NUM_RAW_REGS + MEP_NUM_PSEUDO_REGS | |
615 | }; | |
616 | ||
617 | ||
618 | #define IN_SET(set, n) \ | |
619 | (MEP_FIRST_ ## set ## _REGNUM <= (n) && (n) <= MEP_LAST_ ## set ## _REGNUM) | |
620 | ||
621 | #define IS_GPR_REGNUM(n) (IN_SET (GPR, (n))) | |
622 | #define IS_RAW_CSR_REGNUM(n) (IN_SET (RAW_CSR, (n))) | |
623 | #define IS_RAW_CR_REGNUM(n) (IN_SET (RAW_CR, (n))) | |
624 | #define IS_RAW_CCR_REGNUM(n) (IN_SET (RAW_CCR, (n))) | |
625 | ||
626 | #define IS_CSR_REGNUM(n) (IN_SET (CSR, (n))) | |
627 | #define IS_CR32_REGNUM(n) (IN_SET (CR32, (n))) | |
628 | #define IS_FP_CR32_REGNUM(n) (IN_SET (FP_CR32, (n))) | |
629 | #define IS_CR64_REGNUM(n) (IN_SET (CR64, (n))) | |
630 | #define IS_FP_CR64_REGNUM(n) (IN_SET (FP_CR64, (n))) | |
631 | #define IS_CR_REGNUM(n) (IS_CR32_REGNUM (n) || IS_FP_CR32_REGNUM (n) \ | |
dda83cd7 | 632 | || IS_CR64_REGNUM (n) || IS_FP_CR64_REGNUM (n)) |
aeb43123 KB |
633 | #define IS_CCR_REGNUM(n) (IN_SET (CCR, (n))) |
634 | ||
635 | #define IS_RAW_REGNUM(n) (IN_SET (RAW, (n))) | |
636 | #define IS_PSEUDO_REGNUM(n) (IN_SET (PSEUDO, (n))) | |
637 | ||
638 | #define NUM_REGS_IN_SET(set) \ | |
639 | (MEP_LAST_ ## set ## _REGNUM - MEP_FIRST_ ## set ## _REGNUM + 1) | |
640 | ||
641 | #define MEP_GPR_SIZE (4) /* Size of a MeP general-purpose register. */ | |
642 | #define MEP_PSW_SIZE (4) /* Size of the PSW register. */ | |
643 | #define MEP_LP_SIZE (4) /* Size of the LP register. */ | |
644 | ||
645 | ||
646 | /* Many of the control/special registers contain bits that cannot be | |
647 | written to; some are entirely read-only. So we present them all as | |
648 | pseudoregisters. | |
649 | ||
650 | The following table describes the special properties of each CSR. */ | |
651 | struct mep_csr_register | |
652 | { | |
653 | /* The number of this CSR's raw register. */ | |
654 | int raw; | |
655 | ||
656 | /* The number of this CSR's pseudoregister. */ | |
657 | int pseudo; | |
658 | ||
659 | /* A mask of the bits that are writeable: if a bit is set here, then | |
660 | it can be modified; if the bit is clear, then it cannot. */ | |
661 | LONGEST writeable_bits; | |
662 | }; | |
663 | ||
664 | ||
665 | /* mep_csr_registers[i] describes the i'th CSR. | |
666 | We just list the register numbers here explicitly to help catch | |
667 | typos. */ | |
668 | #define CSR(name) MEP_RAW_ ## name ## _REGNUM, MEP_ ## name ## _REGNUM | |
6bd434d6 | 669 | static mep_csr_register mep_csr_registers[] = { |
aeb43123 KB |
670 | { CSR(PC), 0xffffffff }, /* manual says r/o, but we can write it */ |
671 | { CSR(LP), 0xffffffff }, | |
672 | { CSR(SAR), 0x0000003f }, | |
673 | { CSR(CSR3), 0xffffffff }, | |
674 | { CSR(RPB), 0xfffffffe }, | |
675 | { CSR(RPE), 0xffffffff }, | |
676 | { CSR(RPC), 0xffffffff }, | |
677 | { CSR(HI), 0xffffffff }, | |
678 | { CSR(LO), 0xffffffff }, | |
679 | { CSR(CSR9), 0xffffffff }, | |
680 | { CSR(CSR10), 0xffffffff }, | |
681 | { CSR(CSR11), 0xffffffff }, | |
682 | { CSR(MB0), 0x0000ffff }, | |
683 | { CSR(ME0), 0x0000ffff }, | |
684 | { CSR(MB1), 0x0000ffff }, | |
685 | { CSR(ME1), 0x0000ffff }, | |
686 | { CSR(PSW), 0x000003ff }, | |
687 | { CSR(ID), 0x00000000 }, | |
688 | { CSR(TMP), 0xffffffff }, | |
689 | { CSR(EPC), 0xffffffff }, | |
690 | { CSR(EXC), 0x000030f0 }, | |
691 | { CSR(CFG), 0x00c0001b }, | |
692 | { CSR(CSR22), 0xffffffff }, | |
693 | { CSR(NPC), 0xffffffff }, | |
694 | { CSR(DBG), 0x00000580 }, | |
695 | { CSR(DEPC), 0xffffffff }, | |
696 | { CSR(OPT), 0x00000000 }, | |
697 | { CSR(RCFG), 0x00000000 }, | |
698 | { CSR(CCFG), 0x00000000 }, | |
699 | { CSR(CSR29), 0xffffffff }, | |
700 | { CSR(CSR30), 0xffffffff }, | |
701 | { CSR(CSR31), 0xffffffff }, | |
702 | }; | |
703 | ||
704 | ||
705 | /* If R is the number of a raw register, then mep_raw_to_pseudo[R] is | |
706 | the number of the corresponding pseudoregister. Otherwise, | |
707 | mep_raw_to_pseudo[R] == R. */ | |
708 | static int mep_raw_to_pseudo[MEP_NUM_REGS]; | |
709 | ||
710 | /* If R is the number of a pseudoregister, then mep_pseudo_to_raw[R] | |
711 | is the number of the underlying raw register. Otherwise | |
712 | mep_pseudo_to_raw[R] == R. */ | |
713 | static int mep_pseudo_to_raw[MEP_NUM_REGS]; | |
714 | ||
715 | static void | |
716 | mep_init_pseudoregister_maps (void) | |
717 | { | |
718 | int i; | |
719 | ||
720 | /* Verify that mep_csr_registers covers all the CSRs, in order. */ | |
721 | gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (CSR)); | |
722 | gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (RAW_CSR)); | |
723 | ||
724 | /* Verify that the raw and pseudo ranges have matching sizes. */ | |
725 | gdb_assert (NUM_REGS_IN_SET (RAW_CSR) == NUM_REGS_IN_SET (CSR)); | |
726 | gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR32)); | |
727 | gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR64)); | |
728 | gdb_assert (NUM_REGS_IN_SET (RAW_CCR) == NUM_REGS_IN_SET (CCR)); | |
729 | ||
730 | for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++) | |
731 | { | |
732 | struct mep_csr_register *r = &mep_csr_registers[i]; | |
733 | ||
734 | gdb_assert (r->pseudo == MEP_FIRST_CSR_REGNUM + i); | |
735 | gdb_assert (r->raw == MEP_FIRST_RAW_CSR_REGNUM + i); | |
736 | } | |
737 | ||
738 | /* Set up the initial raw<->pseudo mappings. */ | |
739 | for (i = 0; i < MEP_NUM_REGS; i++) | |
740 | { | |
741 | mep_raw_to_pseudo[i] = i; | |
742 | mep_pseudo_to_raw[i] = i; | |
743 | } | |
744 | ||
745 | /* Add the CSR raw<->pseudo mappings. */ | |
746 | for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++) | |
747 | { | |
748 | struct mep_csr_register *r = &mep_csr_registers[i]; | |
749 | ||
750 | mep_raw_to_pseudo[r->raw] = r->pseudo; | |
751 | mep_pseudo_to_raw[r->pseudo] = r->raw; | |
752 | } | |
753 | ||
754 | /* Add the CR raw<->pseudo mappings. */ | |
755 | for (i = 0; i < NUM_REGS_IN_SET (RAW_CR); i++) | |
756 | { | |
757 | int raw = MEP_FIRST_RAW_CR_REGNUM + i; | |
758 | int pseudo32 = MEP_FIRST_CR32_REGNUM + i; | |
759 | int pseudofp32 = MEP_FIRST_FP_CR32_REGNUM + i; | |
760 | int pseudo64 = MEP_FIRST_CR64_REGNUM + i; | |
761 | int pseudofp64 = MEP_FIRST_FP_CR64_REGNUM + i; | |
762 | ||
763 | /* Truly, the raw->pseudo mapping depends on the current module. | |
dda83cd7 SM |
764 | But we use the raw->pseudo mapping when we read the debugging |
765 | info; at that point, we don't know what module we'll actually | |
766 | be running yet. So, we always supply the 64-bit register | |
767 | numbers; GDB knows how to pick a smaller value out of a | |
768 | larger register properly. */ | |
aeb43123 KB |
769 | mep_raw_to_pseudo[raw] = pseudo64; |
770 | mep_pseudo_to_raw[pseudo32] = raw; | |
771 | mep_pseudo_to_raw[pseudofp32] = raw; | |
772 | mep_pseudo_to_raw[pseudo64] = raw; | |
773 | mep_pseudo_to_raw[pseudofp64] = raw; | |
774 | } | |
775 | ||
776 | /* Add the CCR raw<->pseudo mappings. */ | |
777 | for (i = 0; i < NUM_REGS_IN_SET (CCR); i++) | |
778 | { | |
779 | int raw = MEP_FIRST_RAW_CCR_REGNUM + i; | |
780 | int pseudo = MEP_FIRST_CCR_REGNUM + i; | |
781 | mep_raw_to_pseudo[raw] = pseudo; | |
782 | mep_pseudo_to_raw[pseudo] = raw; | |
783 | } | |
784 | } | |
785 | ||
786 | ||
787 | static int | |
d3f73121 | 788 | mep_debug_reg_to_regnum (struct gdbarch *gdbarch, int debug_reg) |
aeb43123 KB |
789 | { |
790 | /* The debug info uses the raw register numbers. */ | |
0fde2c53 DE |
791 | if (debug_reg >= 0 && debug_reg < ARRAY_SIZE (mep_raw_to_pseudo)) |
792 | return mep_raw_to_pseudo[debug_reg]; | |
793 | return -1; | |
aeb43123 KB |
794 | } |
795 | ||
796 | ||
797 | /* Return the size, in bits, of the coprocessor pseudoregister | |
798 | numbered PSEUDO. */ | |
799 | static int | |
800 | mep_pseudo_cr_size (int pseudo) | |
801 | { | |
802 | if (IS_CR32_REGNUM (pseudo) | |
803 | || IS_FP_CR32_REGNUM (pseudo)) | |
804 | return 32; | |
805 | else if (IS_CR64_REGNUM (pseudo) | |
dda83cd7 | 806 | || IS_FP_CR64_REGNUM (pseudo)) |
aeb43123 KB |
807 | return 64; |
808 | else | |
f3574227 | 809 | gdb_assert_not_reached ("unexpected coprocessor pseudo register"); |
aeb43123 KB |
810 | } |
811 | ||
812 | ||
813 | /* If the coprocessor pseudoregister numbered PSEUDO is a | |
814 | floating-point register, return non-zero; if it is an integer | |
815 | register, return zero. */ | |
816 | static int | |
817 | mep_pseudo_cr_is_float (int pseudo) | |
818 | { | |
819 | return (IS_FP_CR32_REGNUM (pseudo) | |
dda83cd7 | 820 | || IS_FP_CR64_REGNUM (pseudo)); |
aeb43123 KB |
821 | } |
822 | ||
823 | ||
824 | /* Given a coprocessor GPR pseudoregister number, return its index | |
825 | within that register bank. */ | |
826 | static int | |
827 | mep_pseudo_cr_index (int pseudo) | |
828 | { | |
829 | if (IS_CR32_REGNUM (pseudo)) | |
830 | return pseudo - MEP_FIRST_CR32_REGNUM; | |
831 | else if (IS_FP_CR32_REGNUM (pseudo)) | |
832 | return pseudo - MEP_FIRST_FP_CR32_REGNUM; | |
833 | else if (IS_CR64_REGNUM (pseudo)) | |
834 | return pseudo - MEP_FIRST_CR64_REGNUM; | |
835 | else if (IS_FP_CR64_REGNUM (pseudo)) | |
836 | return pseudo - MEP_FIRST_FP_CR64_REGNUM; | |
837 | else | |
f3574227 | 838 | gdb_assert_not_reached ("unexpected coprocessor pseudo register"); |
aeb43123 KB |
839 | } |
840 | ||
841 | ||
842 | /* Return the me_module index describing the current target. | |
843 | ||
844 | If the current target has registers (e.g., simulator, remote | |
845 | target), then this uses the value of the 'module' register, raw | |
846 | register MEP_MODULE_REGNUM. Otherwise, this retrieves the value | |
847 | from the ELF header's e_flags field of the current executable | |
848 | file. */ | |
849 | static CONFIG_ATTR | |
eeae04df | 850 | current_me_module (void) |
aeb43123 | 851 | { |
9dccd06e | 852 | if (target_has_registers ()) |
3d1a74ac UW |
853 | { |
854 | ULONGEST regval; | |
594f7785 | 855 | regcache_cooked_read_unsigned (get_current_regcache (), |
3d1a74ac | 856 | MEP_MODULE_REGNUM, ®val); |
f54b226f | 857 | return (CONFIG_ATTR) regval; |
3d1a74ac | 858 | } |
aeb43123 | 859 | else |
345bd07c SM |
860 | { |
861 | mep_gdbarch_tdep *tdep | |
99d9c3b9 | 862 | = gdbarch_tdep<mep_gdbarch_tdep> (current_inferior ()->arch ()); |
345bd07c SM |
863 | return tdep->me_module; |
864 | } | |
aeb43123 KB |
865 | } |
866 | ||
867 | ||
868 | /* Return the set of options for the current target, in the form that | |
869 | the OPT register would use. | |
870 | ||
871 | If the current target has registers (e.g., simulator, remote | |
872 | target), then this is the actual value of the OPT register. If the | |
873 | current target does not have registers (e.g., an executable file), | |
874 | then use the 'module_opt' field we computed when we build the | |
875 | gdbarch object for this module. */ | |
876 | static unsigned int | |
eeae04df | 877 | current_options (void) |
aeb43123 | 878 | { |
9dccd06e | 879 | if (target_has_registers ()) |
3d1a74ac UW |
880 | { |
881 | ULONGEST regval; | |
594f7785 | 882 | regcache_cooked_read_unsigned (get_current_regcache (), |
3d1a74ac UW |
883 | MEP_OPT_REGNUM, ®val); |
884 | return regval; | |
885 | } | |
aeb43123 KB |
886 | else |
887 | return me_module_opt (current_me_module ()); | |
888 | } | |
889 | ||
890 | ||
891 | /* Return the width of the current me_module's coprocessor data bus, | |
892 | in bits. This is either 32 or 64. */ | |
893 | static int | |
eeae04df | 894 | current_cop_data_bus_width (void) |
aeb43123 KB |
895 | { |
896 | return me_module_cop_data_bus_width (current_me_module ()); | |
897 | } | |
898 | ||
899 | ||
900 | /* Return the keyword table of coprocessor general-purpose register | |
901 | names appropriate for the me_module we're dealing with. */ | |
902 | static CGEN_KEYWORD * | |
eeae04df | 903 | current_cr_names (void) |
aeb43123 KB |
904 | { |
905 | const CGEN_HW_ENTRY *hw | |
906 | = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR); | |
907 | ||
908 | return register_set_keyword_table (hw); | |
909 | } | |
910 | ||
911 | ||
912 | /* Return non-zero if the coprocessor general-purpose registers are | |
913 | floating-point values, zero otherwise. */ | |
914 | static int | |
eeae04df | 915 | current_cr_is_float (void) |
aeb43123 KB |
916 | { |
917 | const CGEN_HW_ENTRY *hw | |
918 | = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR); | |
919 | ||
920 | return CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE (CGEN_HW_ATTRS (hw)); | |
921 | } | |
922 | ||
923 | ||
924 | /* Return the keyword table of coprocessor control register names | |
925 | appropriate for the me_module we're dealing with. */ | |
926 | static CGEN_KEYWORD * | |
eeae04df | 927 | current_ccr_names (void) |
aeb43123 KB |
928 | { |
929 | const CGEN_HW_ENTRY *hw | |
930 | = me_module_register_set (current_me_module (), "h-ccr-", HW_H_CCR); | |
931 | ||
932 | return register_set_keyword_table (hw); | |
933 | } | |
934 | ||
935 | ||
936 | static const char * | |
d93859e2 | 937 | mep_register_name (struct gdbarch *gdbarch, int regnr) |
aeb43123 | 938 | { |
aeb43123 KB |
939 | /* General-purpose registers. */ |
940 | static const char *gpr_names[] = { | |
941 | "r0", "r1", "r2", "r3", /* 0 */ | |
942 | "r4", "r5", "r6", "r7", /* 4 */ | |
943 | "fp", "r9", "r10", "r11", /* 8 */ | |
944 | "r12", "tp", "gp", "sp" /* 12 */ | |
945 | }; | |
946 | ||
947 | /* Special-purpose registers. */ | |
948 | static const char *csr_names[] = { | |
949 | "pc", "lp", "sar", "", /* 0 csr3: reserved */ | |
950 | "rpb", "rpe", "rpc", "hi", /* 4 */ | |
951 | "lo", "", "", "", /* 8 csr9-csr11: reserved */ | |
952 | "mb0", "me0", "mb1", "me1", /* 12 */ | |
953 | ||
954 | "psw", "id", "tmp", "epc", /* 16 */ | |
955 | "exc", "cfg", "", "npc", /* 20 csr22: reserved */ | |
956 | "dbg", "depc", "opt", "rcfg", /* 24 */ | |
957 | "ccfg", "", "", "" /* 28 csr29-csr31: reserved */ | |
958 | }; | |
959 | ||
960 | if (IS_GPR_REGNUM (regnr)) | |
961 | return gpr_names[regnr - MEP_R0_REGNUM]; | |
962 | else if (IS_CSR_REGNUM (regnr)) | |
963 | { | |
964 | /* The 'hi' and 'lo' registers are only present on processors | |
dda83cd7 | 965 | that have the 'MUL' or 'DIV' instructions enabled. */ |
aeb43123 | 966 | if ((regnr == MEP_HI_REGNUM || regnr == MEP_LO_REGNUM) |
dda83cd7 SM |
967 | && (! (current_options () & (MEP_OPT_MUL | MEP_OPT_DIV)))) |
968 | return ""; | |
aeb43123 KB |
969 | |
970 | return csr_names[regnr - MEP_FIRST_CSR_REGNUM]; | |
971 | } | |
972 | else if (IS_CR_REGNUM (regnr)) | |
973 | { | |
974 | CGEN_KEYWORD *names; | |
975 | int cr_size; | |
976 | int cr_is_float; | |
977 | ||
978 | /* Does this module have a coprocessor at all? */ | |
979 | if (! (current_options () & MEP_OPT_COP)) | |
dda83cd7 | 980 | return ""; |
aeb43123 KB |
981 | |
982 | names = current_cr_names (); | |
983 | if (! names) | |
dda83cd7 SM |
984 | /* This module's coprocessor has no general-purpose registers. */ |
985 | return ""; | |
aeb43123 KB |
986 | |
987 | cr_size = current_cop_data_bus_width (); | |
988 | if (cr_size != mep_pseudo_cr_size (regnr)) | |
dda83cd7 SM |
989 | /* This module's coprocessor's GPR's are of a different size. */ |
990 | return ""; | |
aeb43123 KB |
991 | |
992 | cr_is_float = current_cr_is_float (); | |
993 | /* The extra ! operators ensure we get boolean equality, not | |
dda83cd7 | 994 | numeric equality. */ |
aeb43123 | 995 | if (! cr_is_float != ! mep_pseudo_cr_is_float (regnr)) |
dda83cd7 SM |
996 | /* This module's coprocessor's GPR's are of a different type. */ |
997 | return ""; | |
aeb43123 KB |
998 | |
999 | return register_name_from_keyword (names, mep_pseudo_cr_index (regnr)); | |
1000 | } | |
1001 | else if (IS_CCR_REGNUM (regnr)) | |
1002 | { | |
1003 | /* Does this module have a coprocessor at all? */ | |
1004 | if (! (current_options () & MEP_OPT_COP)) | |
dda83cd7 | 1005 | return ""; |
aeb43123 KB |
1006 | |
1007 | { | |
dda83cd7 | 1008 | CGEN_KEYWORD *names = current_ccr_names (); |
aeb43123 | 1009 | |
dda83cd7 SM |
1010 | if (! names) |
1011 | /* This me_module's coprocessor has no control registers. */ | |
1012 | return ""; | |
aeb43123 | 1013 | |
dda83cd7 | 1014 | return register_name_from_keyword (names, regnr-MEP_FIRST_CCR_REGNUM); |
aeb43123 KB |
1015 | } |
1016 | } | |
1017 | ||
1018 | /* It might be nice to give the 'module' register a name, but that | |
1019 | would affect the output of 'info all-registers', which would | |
1020 | disturb the test suites. So we leave it invisible. */ | |
1021 | else | |
9a972b54 | 1022 | return ""; |
aeb43123 KB |
1023 | } |
1024 | ||
1025 | ||
1026 | /* Custom register groups for the MeP. */ | |
e7fe1011 AB |
1027 | static const reggroup *mep_csr_reggroup; /* control/special */ |
1028 | static const reggroup *mep_cr_reggroup; /* coprocessor general-purpose */ | |
1029 | static const reggroup *mep_ccr_reggroup; /* coprocessor control */ | |
aeb43123 KB |
1030 | |
1031 | ||
1032 | static int | |
1033 | mep_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 1034 | const struct reggroup *group) |
aeb43123 KB |
1035 | { |
1036 | /* Filter reserved or unused register numbers. */ | |
1037 | { | |
d93859e2 | 1038 | const char *name = mep_register_name (gdbarch, regnum); |
aeb43123 KB |
1039 | |
1040 | if (! name || name[0] == '\0') | |
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | /* We could separate the GPRs and the CSRs. Toshiba has approved of | |
1045 | the existing behavior, so we'd want to run that by them. */ | |
1046 | if (group == general_reggroup) | |
1047 | return (IS_GPR_REGNUM (regnum) | |
dda83cd7 | 1048 | || IS_CSR_REGNUM (regnum)); |
aeb43123 KB |
1049 | |
1050 | /* Everything is in the 'all' reggroup, except for the raw CSR's. */ | |
1051 | else if (group == all_reggroup) | |
1052 | return (IS_GPR_REGNUM (regnum) | |
dda83cd7 SM |
1053 | || IS_CSR_REGNUM (regnum) |
1054 | || IS_CR_REGNUM (regnum) | |
1055 | || IS_CCR_REGNUM (regnum)); | |
aeb43123 KB |
1056 | |
1057 | /* All registers should be saved and restored, except for the raw | |
1058 | CSR's. | |
1059 | ||
1060 | This is probably right if the coprocessor is something like a | |
1061 | floating-point unit, but would be wrong if the coprocessor is | |
1062 | something that does I/O, where register accesses actually cause | |
1063 | externally-visible actions. But I get the impression that the | |
1064 | coprocessor isn't supposed to do things like that --- you'd use a | |
1065 | hardware engine, perhaps. */ | |
1066 | else if (group == save_reggroup || group == restore_reggroup) | |
1067 | return (IS_GPR_REGNUM (regnum) | |
dda83cd7 SM |
1068 | || IS_CSR_REGNUM (regnum) |
1069 | || IS_CR_REGNUM (regnum) | |
1070 | || IS_CCR_REGNUM (regnum)); | |
aeb43123 KB |
1071 | |
1072 | else if (group == mep_csr_reggroup) | |
1073 | return IS_CSR_REGNUM (regnum); | |
1074 | else if (group == mep_cr_reggroup) | |
1075 | return IS_CR_REGNUM (regnum); | |
1076 | else if (group == mep_ccr_reggroup) | |
1077 | return IS_CCR_REGNUM (regnum); | |
1078 | else | |
1079 | return 0; | |
1080 | } | |
1081 | ||
1082 | ||
1083 | static struct type * | |
1084 | mep_register_type (struct gdbarch *gdbarch, int reg_nr) | |
1085 | { | |
1086 | /* Coprocessor general-purpose registers may be either 32 or 64 bits | |
1087 | long. So for them, the raw registers are always 64 bits long (to | |
1088 | keep the 'g' packet format fixed), and the pseudoregisters vary | |
1089 | in length. */ | |
1090 | if (IS_RAW_CR_REGNUM (reg_nr)) | |
df4df182 | 1091 | return builtin_type (gdbarch)->builtin_uint64; |
aeb43123 KB |
1092 | |
1093 | /* Since GDB doesn't allow registers to change type, we have two | |
1094 | banks of pseudoregisters for the coprocessor general-purpose | |
1095 | registers: one that gives a 32-bit view, and one that gives a | |
1096 | 64-bit view. We hide or show one or the other depending on the | |
1097 | current module. */ | |
1098 | if (IS_CR_REGNUM (reg_nr)) | |
1099 | { | |
1100 | int size = mep_pseudo_cr_size (reg_nr); | |
1101 | if (size == 32) | |
dda83cd7 SM |
1102 | { |
1103 | if (mep_pseudo_cr_is_float (reg_nr)) | |
1104 | return builtin_type (gdbarch)->builtin_float; | |
1105 | else | |
1106 | return builtin_type (gdbarch)->builtin_uint32; | |
1107 | } | |
aeb43123 | 1108 | else if (size == 64) |
dda83cd7 SM |
1109 | { |
1110 | if (mep_pseudo_cr_is_float (reg_nr)) | |
1111 | return builtin_type (gdbarch)->builtin_double; | |
1112 | else | |
1113 | return builtin_type (gdbarch)->builtin_uint64; | |
1114 | } | |
aeb43123 | 1115 | else |
dda83cd7 | 1116 | gdb_assert_not_reached ("unexpected cr size"); |
aeb43123 KB |
1117 | } |
1118 | ||
1119 | /* All other registers are 32 bits long. */ | |
1120 | else | |
df4df182 | 1121 | return builtin_type (gdbarch)->builtin_uint32; |
aeb43123 KB |
1122 | } |
1123 | ||
05d1431c | 1124 | static enum register_status |
aeb43123 | 1125 | mep_pseudo_cr32_read (struct gdbarch *gdbarch, |
849d0ba8 | 1126 | readable_regcache *regcache, |
dda83cd7 SM |
1127 | int cookednum, |
1128 | gdb_byte *buf) | |
aeb43123 | 1129 | { |
05d1431c | 1130 | enum register_status status; |
e17a4113 | 1131 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
aeb43123 KB |
1132 | /* Read the raw register into a 64-bit buffer, and then return the |
1133 | appropriate end of that buffer. */ | |
1134 | int rawnum = mep_pseudo_to_raw[cookednum]; | |
e362b510 | 1135 | gdb_byte buf64[8]; |
aeb43123 | 1136 | |
df86565b SM |
1137 | gdb_assert (register_type (gdbarch, rawnum)->length () == sizeof (buf64)); |
1138 | gdb_assert (register_type (gdbarch, cookednum)->length () == 4); | |
03f50fc8 | 1139 | status = regcache->raw_read (rawnum, buf64); |
05d1431c PA |
1140 | if (status == REG_VALID) |
1141 | { | |
1142 | /* Slow, but legible. */ | |
1143 | store_unsigned_integer (buf, 4, byte_order, | |
1144 | extract_unsigned_integer (buf64, 8, byte_order)); | |
1145 | } | |
1146 | return status; | |
aeb43123 KB |
1147 | } |
1148 | ||
1149 | ||
05d1431c | 1150 | static enum register_status |
aeb43123 | 1151 | mep_pseudo_cr64_read (struct gdbarch *gdbarch, |
dda83cd7 SM |
1152 | readable_regcache *regcache, |
1153 | int cookednum, | |
1154 | gdb_byte *buf) | |
aeb43123 | 1155 | { |
03f50fc8 | 1156 | return regcache->raw_read (mep_pseudo_to_raw[cookednum], buf); |
aeb43123 KB |
1157 | } |
1158 | ||
1159 | ||
05d1431c | 1160 | static enum register_status |
aeb43123 | 1161 | mep_pseudo_register_read (struct gdbarch *gdbarch, |
849d0ba8 | 1162 | readable_regcache *regcache, |
dda83cd7 SM |
1163 | int cookednum, |
1164 | gdb_byte *buf) | |
aeb43123 KB |
1165 | { |
1166 | if (IS_CSR_REGNUM (cookednum) | |
1167 | || IS_CCR_REGNUM (cookednum)) | |
03f50fc8 | 1168 | return regcache->raw_read (mep_pseudo_to_raw[cookednum], buf); |
aeb43123 | 1169 | else if (IS_CR32_REGNUM (cookednum) |
dda83cd7 | 1170 | || IS_FP_CR32_REGNUM (cookednum)) |
05d1431c | 1171 | return mep_pseudo_cr32_read (gdbarch, regcache, cookednum, buf); |
aeb43123 | 1172 | else if (IS_CR64_REGNUM (cookednum) |
dda83cd7 | 1173 | || IS_FP_CR64_REGNUM (cookednum)) |
05d1431c | 1174 | return mep_pseudo_cr64_read (gdbarch, regcache, cookednum, buf); |
aeb43123 | 1175 | else |
f3574227 | 1176 | gdb_assert_not_reached ("unexpected pseudo register"); |
aeb43123 KB |
1177 | } |
1178 | ||
1179 | ||
1180 | static void | |
1181 | mep_pseudo_csr_write (struct gdbarch *gdbarch, | |
dda83cd7 SM |
1182 | struct regcache *regcache, |
1183 | int cookednum, | |
1184 | const gdb_byte *buf) | |
aeb43123 | 1185 | { |
e17a4113 | 1186 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
aeb43123 KB |
1187 | int size = register_size (gdbarch, cookednum); |
1188 | struct mep_csr_register *r | |
1189 | = &mep_csr_registers[cookednum - MEP_FIRST_CSR_REGNUM]; | |
1190 | ||
1191 | if (r->writeable_bits == 0) | |
1192 | /* A completely read-only register; avoid the read-modify- | |
1193 | write cycle, and juts ignore the entire write. */ | |
1194 | ; | |
1195 | else | |
1196 | { | |
1197 | /* A partially writeable register; do a read-modify-write cycle. */ | |
1198 | ULONGEST old_bits; | |
1199 | ULONGEST new_bits; | |
1200 | ULONGEST mixed_bits; | |
dda83cd7 | 1201 | |
aeb43123 | 1202 | regcache_raw_read_unsigned (regcache, r->raw, &old_bits); |
e17a4113 | 1203 | new_bits = extract_unsigned_integer (buf, size, byte_order); |
aeb43123 | 1204 | mixed_bits = ((r->writeable_bits & new_bits) |
dda83cd7 | 1205 | | (~r->writeable_bits & old_bits)); |
aeb43123 KB |
1206 | regcache_raw_write_unsigned (regcache, r->raw, mixed_bits); |
1207 | } | |
1208 | } | |
dda83cd7 | 1209 | |
aeb43123 KB |
1210 | |
1211 | static void | |
1212 | mep_pseudo_cr32_write (struct gdbarch *gdbarch, | |
dda83cd7 SM |
1213 | struct regcache *regcache, |
1214 | int cookednum, | |
1215 | const gdb_byte *buf) | |
aeb43123 | 1216 | { |
e17a4113 | 1217 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
aeb43123 KB |
1218 | /* Expand the 32-bit value into a 64-bit value, and write that to |
1219 | the pseudoregister. */ | |
1220 | int rawnum = mep_pseudo_to_raw[cookednum]; | |
e362b510 | 1221 | gdb_byte buf64[8]; |
aeb43123 | 1222 | |
df86565b SM |
1223 | gdb_assert (register_type (gdbarch, rawnum)->length () == sizeof (buf64)); |
1224 | gdb_assert (register_type (gdbarch, cookednum)->length () == 4); | |
aeb43123 | 1225 | /* Slow, but legible. */ |
e17a4113 UW |
1226 | store_unsigned_integer (buf64, 8, byte_order, |
1227 | extract_unsigned_integer (buf, 4, byte_order)); | |
10eaee5f | 1228 | regcache->raw_write (rawnum, buf64); |
aeb43123 KB |
1229 | } |
1230 | ||
1231 | ||
1232 | static void | |
1233 | mep_pseudo_cr64_write (struct gdbarch *gdbarch, | |
dda83cd7 SM |
1234 | struct regcache *regcache, |
1235 | int cookednum, | |
1236 | const gdb_byte *buf) | |
aeb43123 | 1237 | { |
10eaee5f | 1238 | regcache->raw_write (mep_pseudo_to_raw[cookednum], buf); |
aeb43123 KB |
1239 | } |
1240 | ||
1241 | ||
1242 | static void | |
1243 | mep_pseudo_register_write (struct gdbarch *gdbarch, | |
dda83cd7 SM |
1244 | struct regcache *regcache, |
1245 | int cookednum, | |
1246 | const gdb_byte *buf) | |
aeb43123 KB |
1247 | { |
1248 | if (IS_CSR_REGNUM (cookednum)) | |
1249 | mep_pseudo_csr_write (gdbarch, regcache, cookednum, buf); | |
1250 | else if (IS_CR32_REGNUM (cookednum) | |
dda83cd7 | 1251 | || IS_FP_CR32_REGNUM (cookednum)) |
aeb43123 KB |
1252 | mep_pseudo_cr32_write (gdbarch, regcache, cookednum, buf); |
1253 | else if (IS_CR64_REGNUM (cookednum) | |
dda83cd7 | 1254 | || IS_FP_CR64_REGNUM (cookednum)) |
aeb43123 KB |
1255 | mep_pseudo_cr64_write (gdbarch, regcache, cookednum, buf); |
1256 | else if (IS_CCR_REGNUM (cookednum)) | |
10eaee5f | 1257 | regcache->raw_write (mep_pseudo_to_raw[cookednum], buf); |
aeb43123 | 1258 | else |
f3574227 | 1259 | gdb_assert_not_reached ("unexpected pseudo register"); |
aeb43123 KB |
1260 | } |
1261 | ||
1262 | ||
1263 | \f | |
1264 | /* Disassembly. */ | |
1265 | ||
63807e1d | 1266 | static int |
aeb43123 KB |
1267 | mep_gdb_print_insn (bfd_vma pc, disassemble_info * info) |
1268 | { | |
1269 | struct obj_section * s = find_pc_section (pc); | |
1270 | ||
8cafda32 | 1271 | info->arch = bfd_arch_mep; |
aeb43123 KB |
1272 | if (s) |
1273 | { | |
1274 | /* The libopcodes disassembly code uses the section to find the | |
dda83cd7 SM |
1275 | BFD, the BFD to find the ELF header, the ELF header to find |
1276 | the me_module index, and the me_module index to select the | |
1277 | right instructions to print. */ | |
aeb43123 | 1278 | info->section = s->the_bfd_section; |
aeb43123 | 1279 | } |
8cafda32 YQ |
1280 | |
1281 | return print_insn_mep (pc, info); | |
aeb43123 KB |
1282 | } |
1283 | ||
1284 | \f | |
1285 | /* Prologue analysis. */ | |
1286 | ||
1287 | ||
1288 | /* The MeP has two classes of instructions: "core" instructions, which | |
1289 | are pretty normal RISC chip stuff, and "coprocessor" instructions, | |
1290 | which are mostly concerned with moving data in and out of | |
1291 | coprocessor registers, and branching on coprocessor condition | |
1292 | codes. There's space in the instruction set for custom coprocessor | |
1293 | instructions, too. | |
1294 | ||
1295 | Instructions can be 16 or 32 bits long; the top two bits of the | |
1296 | first byte indicate the length. The coprocessor instructions are | |
1297 | mixed in with the core instructions, and there's no easy way to | |
1298 | distinguish them; you have to completely decode them to tell one | |
1299 | from the other. | |
1300 | ||
1301 | The MeP also supports a "VLIW" operation mode, where instructions | |
1302 | always occur in fixed-width bundles. The bundles are either 32 | |
1303 | bits or 64 bits long, depending on a fixed configuration flag. You | |
1304 | decode the first part of the bundle as normal; if it's a core | |
1305 | instruction, and there's any space left in the bundle, the | |
1306 | remainder of the bundle is a coprocessor instruction, which will | |
1307 | execute in parallel with the core instruction. If the first part | |
1308 | of the bundle is a coprocessor instruction, it occupies the entire | |
1309 | bundle. | |
1310 | ||
1311 | So, here are all the cases: | |
1312 | ||
1313 | - 32-bit VLIW mode: | |
1314 | Every bundle is four bytes long, and naturally aligned, and can hold | |
1315 | one or two instructions: | |
1316 | - 16-bit core instruction; 16-bit coprocessor instruction | |
025bb325 | 1317 | These execute in parallel. |
aeb43123 KB |
1318 | - 32-bit core instruction |
1319 | - 32-bit coprocessor instruction | |
1320 | ||
1321 | - 64-bit VLIW mode: | |
1322 | Every bundle is eight bytes long, and naturally aligned, and can hold | |
1323 | one or two instructions: | |
1324 | - 16-bit core instruction; 48-bit (!) coprocessor instruction | |
025bb325 | 1325 | These execute in parallel. |
aeb43123 | 1326 | - 32-bit core instruction; 32-bit coprocessor instruction |
025bb325 | 1327 | These execute in parallel. |
aeb43123 KB |
1328 | - 64-bit coprocessor instruction |
1329 | ||
1330 | Now, the MeP manual doesn't define any 48- or 64-bit coprocessor | |
1331 | instruction, so I don't really know what's up there; perhaps these | |
1332 | are always the user-defined coprocessor instructions. */ | |
1333 | ||
1334 | ||
1335 | /* Return non-zero if PC is in a VLIW code section, zero | |
1336 | otherwise. */ | |
1337 | static int | |
1338 | mep_pc_in_vliw_section (CORE_ADDR pc) | |
1339 | { | |
1340 | struct obj_section *s = find_pc_section (pc); | |
1341 | if (s) | |
1342 | return (s->the_bfd_section->flags & SEC_MEP_VLIW); | |
1343 | return 0; | |
1344 | } | |
1345 | ||
1346 | ||
1347 | /* Set *INSN to the next core instruction at PC, and return the | |
1348 | address of the next instruction. | |
1349 | ||
1350 | The MeP instruction encoding is endian-dependent. 16- and 32-bit | |
1351 | instructions are encoded as one or two two-byte parts, and each | |
1352 | part is byte-swapped independently. Thus: | |
1353 | ||
1354 | void | |
1355 | foo (void) | |
1356 | { | |
dda83cd7 SM |
1357 | asm ("movu $1, 0x123456"); |
1358 | asm ("sb $1,0x5678($2)"); | |
1359 | asm ("clip $1, 19"); | |
aeb43123 KB |
1360 | } |
1361 | ||
1362 | compiles to this big-endian code: | |
1363 | ||
1364 | 0: d1 56 12 34 movu $1,0x123456 | |
1365 | 4: c1 28 56 78 sb $1,22136($2) | |
1366 | 8: f1 01 10 98 clip $1,0x13 | |
1367 | c: 70 02 ret | |
1368 | ||
1369 | and this little-endian code: | |
1370 | ||
1371 | 0: 56 d1 34 12 movu $1,0x123456 | |
1372 | 4: 28 c1 78 56 sb $1,22136($2) | |
1373 | 8: 01 f1 98 10 clip $1,0x13 | |
1374 | c: 02 70 ret | |
1375 | ||
1376 | Instructions are returned in *INSN in an endian-independent form: a | |
1377 | given instruction always appears in *INSN the same way, regardless | |
1378 | of whether the instruction stream is big-endian or little-endian. | |
1379 | ||
1380 | *INSN's most significant 16 bits are the first (i.e., at lower | |
1381 | addresses) 16 bit part of the instruction. Its least significant | |
1382 | 16 bits are the second (i.e., higher-addressed) 16 bit part of the | |
1383 | instruction, or zero for a 16-bit instruction. Both 16-bit parts | |
1384 | are fetched using the current endianness. | |
1385 | ||
1386 | So, the *INSN values for the instruction sequence above would be | |
1387 | the following, in either endianness: | |
1388 | ||
1389 | 0xd1561234 movu $1,0x123456 | |
1390 | 0xc1285678 sb $1,22136($2) | |
1391 | 0xf1011098 clip $1,0x13 | |
1392 | 0x70020000 ret | |
1393 | ||
1394 | (In a sense, it would be more natural to return 16-bit instructions | |
1395 | in the least significant 16 bits of *INSN, but that would be | |
1396 | ambiguous. In order to tell whether you're looking at a 16- or a | |
1397 | 32-bit instruction, you have to consult the major opcode field --- | |
1398 | the most significant four bits of the instruction's first 16-bit | |
1399 | part. But if we put 16-bit instructions at the least significant | |
1400 | end of *INSN, then you don't know where to find the major opcode | |
1401 | field until you know if it's a 16- or a 32-bit instruction --- | |
1402 | which is where we started.) | |
1403 | ||
1404 | If PC points to a core / coprocessor bundle in a VLIW section, set | |
1405 | *INSN to the core instruction, and return the address of the next | |
1406 | bundle. This has the effect of skipping the bundled coprocessor | |
1407 | instruction. That's okay, since coprocessor instructions aren't | |
1408 | significant to prologue analysis --- for the time being, | |
1409 | anyway. */ | |
1410 | ||
1411 | static CORE_ADDR | |
9d1dd0e2 | 1412 | mep_get_insn (struct gdbarch *gdbarch, CORE_ADDR pc, unsigned long *insn) |
aeb43123 | 1413 | { |
e17a4113 | 1414 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
aeb43123 KB |
1415 | int pc_in_vliw_section; |
1416 | int vliw_mode; | |
1417 | int insn_len; | |
e362b510 | 1418 | gdb_byte buf[2]; |
aeb43123 KB |
1419 | |
1420 | *insn = 0; | |
1421 | ||
1422 | /* Are we in a VLIW section? */ | |
1423 | pc_in_vliw_section = mep_pc_in_vliw_section (pc); | |
1424 | if (pc_in_vliw_section) | |
1425 | { | |
1426 | /* Yes, find out which bundle size. */ | |
1427 | vliw_mode = current_options () & (MEP_OPT_VL32 | MEP_OPT_VL64); | |
1428 | ||
1429 | /* If PC is in a VLIW section, but the current core doesn't say | |
dda83cd7 SM |
1430 | that it supports either VLIW mode, then we don't have enough |
1431 | information to parse the instruction stream it contains. | |
1432 | Since the "undifferentiated" standard core doesn't have | |
1433 | either VLIW mode bit set, this could happen. | |
aeb43123 | 1434 | |
dda83cd7 SM |
1435 | But it shouldn't be an error to (say) set a breakpoint in a |
1436 | VLIW section, if you know you'll never reach it. (Perhaps | |
1437 | you have a script that sets a bunch of standard breakpoints.) | |
aeb43123 | 1438 | |
dda83cd7 | 1439 | So we'll just return zero here, and hope for the best. */ |
aeb43123 | 1440 | if (! (vliw_mode & (MEP_OPT_VL32 | MEP_OPT_VL64))) |
dda83cd7 | 1441 | return 0; |
aeb43123 KB |
1442 | |
1443 | /* If both VL32 and VL64 are set, that's bogus, too. */ | |
1444 | if (vliw_mode == (MEP_OPT_VL32 | MEP_OPT_VL64)) | |
dda83cd7 | 1445 | return 0; |
aeb43123 KB |
1446 | } |
1447 | else | |
1448 | vliw_mode = 0; | |
1449 | ||
1450 | read_memory (pc, buf, sizeof (buf)); | |
e17a4113 | 1451 | *insn = extract_unsigned_integer (buf, 2, byte_order) << 16; |
aeb43123 KB |
1452 | |
1453 | /* The major opcode --- the top four bits of the first 16-bit | |
1454 | part --- indicates whether this instruction is 16 or 32 bits | |
1455 | long. All 32-bit instructions have a major opcode whose top | |
1456 | two bits are 11; all the rest are 16-bit instructions. */ | |
1457 | if ((*insn & 0xc0000000) == 0xc0000000) | |
1458 | { | |
1459 | /* Fetch the second 16-bit part of the instruction. */ | |
1460 | read_memory (pc + 2, buf, sizeof (buf)); | |
e17a4113 | 1461 | *insn = *insn | extract_unsigned_integer (buf, 2, byte_order); |
aeb43123 KB |
1462 | } |
1463 | ||
1464 | /* If we're in VLIW code, then the VLIW width determines the address | |
1465 | of the next instruction. */ | |
1466 | if (vliw_mode) | |
1467 | { | |
1468 | /* In 32-bit VLIW code, all bundles are 32 bits long. We ignore the | |
dda83cd7 | 1469 | coprocessor half of a core / copro bundle. */ |
aeb43123 | 1470 | if (vliw_mode == MEP_OPT_VL32) |
dda83cd7 | 1471 | insn_len = 4; |
aeb43123 KB |
1472 | |
1473 | /* In 64-bit VLIW code, all bundles are 64 bits long. We ignore the | |
dda83cd7 | 1474 | coprocessor half of a core / copro bundle. */ |
aeb43123 | 1475 | else if (vliw_mode == MEP_OPT_VL64) |
dda83cd7 | 1476 | insn_len = 8; |
aeb43123 KB |
1477 | |
1478 | /* We'd better be in either core, 32-bit VLIW, or 64-bit VLIW mode. */ | |
1479 | else | |
dda83cd7 | 1480 | gdb_assert_not_reached ("unexpected vliw mode"); |
aeb43123 KB |
1481 | } |
1482 | ||
1483 | /* Otherwise, the top two bits of the major opcode are (again) what | |
1484 | we need to check. */ | |
1485 | else if ((*insn & 0xc0000000) == 0xc0000000) | |
1486 | insn_len = 4; | |
1487 | else | |
1488 | insn_len = 2; | |
1489 | ||
1490 | return pc + insn_len; | |
1491 | } | |
1492 | ||
1493 | ||
1494 | /* Sign-extend the LEN-bit value N. */ | |
1495 | #define SEXT(n, len) ((((int) (n)) ^ (1 << ((len) - 1))) - (1 << ((len) - 1))) | |
1496 | ||
1497 | /* Return the LEN-bit field at POS from I. */ | |
1498 | #define FIELD(i, pos, len) (((i) >> (pos)) & ((1 << (len)) - 1)) | |
1499 | ||
1500 | /* Like FIELD, but sign-extend the field's value. */ | |
1501 | #define SFIELD(i, pos, len) (SEXT (FIELD ((i), (pos), (len)), (len))) | |
1502 | ||
1503 | ||
1504 | /* Macros for decoding instructions. | |
1505 | ||
1506 | Remember that 16-bit instructions are placed in bits 16..31 of i, | |
1507 | not at the least significant end; this means that the major opcode | |
1508 | field is always in the same place, regardless of the width of the | |
1509 | instruction. As a reminder of this, we show the lower 16 bits of a | |
1510 | 16-bit instruction as xxxx_xxxx_xxxx_xxxx. */ | |
1511 | ||
1512 | /* SB Rn,(Rm) 0000_nnnn_mmmm_1000 */ | |
1513 | /* SH Rn,(Rm) 0000_nnnn_mmmm_1001 */ | |
1514 | /* SW Rn,(Rm) 0000_nnnn_mmmm_1010 */ | |
1515 | ||
1516 | /* SW Rn,disp16(Rm) 1100_nnnn_mmmm_1010 dddd_dddd_dddd_dddd */ | |
1517 | #define IS_SW(i) (((i) & 0xf00f0000) == 0xc00a0000) | |
1518 | /* SB Rn,disp16(Rm) 1100_nnnn_mmmm_1000 dddd_dddd_dddd_dddd */ | |
1519 | #define IS_SB(i) (((i) & 0xf00f0000) == 0xc0080000) | |
1520 | /* SH Rn,disp16(Rm) 1100_nnnn_mmmm_1001 dddd_dddd_dddd_dddd */ | |
1521 | #define IS_SH(i) (((i) & 0xf00f0000) == 0xc0090000) | |
1522 | #define SWBH_32_BASE(i) (FIELD (i, 20, 4)) | |
1523 | #define SWBH_32_SOURCE(i) (FIELD (i, 24, 4)) | |
1524 | #define SWBH_32_OFFSET(i) (SFIELD (i, 0, 16)) | |
1525 | ||
1526 | /* SW Rn,disp7.align4(SP) 0100_nnnn_0ddd_dd10 xxxx_xxxx_xxxx_xxxx */ | |
1527 | #define IS_SW_IMMD(i) (((i) & 0xf0830000) == 0x40020000) | |
1528 | #define SW_IMMD_SOURCE(i) (FIELD (i, 24, 4)) | |
1529 | #define SW_IMMD_OFFSET(i) (FIELD (i, 18, 5) << 2) | |
1530 | ||
1531 | /* SW Rn,(Rm) 0000_nnnn_mmmm_1010 xxxx_xxxx_xxxx_xxxx */ | |
1532 | #define IS_SW_REG(i) (((i) & 0xf00f0000) == 0x000a0000) | |
1533 | #define SW_REG_SOURCE(i) (FIELD (i, 24, 4)) | |
1534 | #define SW_REG_BASE(i) (FIELD (i, 20, 4)) | |
1535 | ||
1536 | /* ADD3 Rl,Rn,Rm 1001_nnnn_mmmm_llll xxxx_xxxx_xxxx_xxxx */ | |
1537 | #define IS_ADD3_16_REG(i) (((i) & 0xf0000000) == 0x90000000) | |
1538 | #define ADD3_16_REG_SRC1(i) (FIELD (i, 20, 4)) /* n */ | |
1539 | #define ADD3_16_REG_SRC2(i) (FIELD (i, 24, 4)) /* m */ | |
1540 | ||
1541 | /* ADD3 Rn,Rm,imm16 1100_nnnn_mmmm_0000 iiii_iiii_iiii_iiii */ | |
1542 | #define IS_ADD3_32(i) (((i) & 0xf00f0000) == 0xc0000000) | |
1543 | #define ADD3_32_TARGET(i) (FIELD (i, 24, 4)) | |
1544 | #define ADD3_32_SOURCE(i) (FIELD (i, 20, 4)) | |
1545 | #define ADD3_32_OFFSET(i) (SFIELD (i, 0, 16)) | |
1546 | ||
1547 | /* ADD3 Rn,SP,imm7.align4 0100_nnnn_0iii_ii00 xxxx_xxxx_xxxx_xxxx */ | |
1548 | #define IS_ADD3_16(i) (((i) & 0xf0830000) == 0x40000000) | |
1549 | #define ADD3_16_TARGET(i) (FIELD (i, 24, 4)) | |
1550 | #define ADD3_16_OFFSET(i) (FIELD (i, 18, 5) << 2) | |
1551 | ||
1552 | /* ADD Rn,imm6 0110_nnnn_iiii_ii00 xxxx_xxxx_xxxx_xxxx */ | |
1553 | #define IS_ADD(i) (((i) & 0xf0030000) == 0x60000000) | |
1554 | #define ADD_TARGET(i) (FIELD (i, 24, 4)) | |
1555 | #define ADD_OFFSET(i) (SFIELD (i, 18, 6)) | |
1556 | ||
1557 | /* LDC Rn,imm5 0111_nnnn_iiii_101I xxxx_xxxx_xxxx_xxxx | |
dda83cd7 | 1558 | imm5 = I||i[7:4] */ |
aeb43123 KB |
1559 | #define IS_LDC(i) (((i) & 0xf00e0000) == 0x700a0000) |
1560 | #define LDC_IMM(i) ((FIELD (i, 16, 1) << 4) | FIELD (i, 20, 4)) | |
1561 | #define LDC_TARGET(i) (FIELD (i, 24, 4)) | |
1562 | ||
1563 | /* LW Rn,disp16(Rm) 1100_nnnn_mmmm_1110 dddd_dddd_dddd_dddd */ | |
1564 | #define IS_LW(i) (((i) & 0xf00f0000) == 0xc00e0000) | |
1565 | #define LW_TARGET(i) (FIELD (i, 24, 4)) | |
1566 | #define LW_BASE(i) (FIELD (i, 20, 4)) | |
1567 | #define LW_OFFSET(i) (SFIELD (i, 0, 16)) | |
1568 | ||
1569 | /* MOV Rn,Rm 0000_nnnn_mmmm_0000 xxxx_xxxx_xxxx_xxxx */ | |
1570 | #define IS_MOV(i) (((i) & 0xf00f0000) == 0x00000000) | |
1571 | #define MOV_TARGET(i) (FIELD (i, 24, 4)) | |
1572 | #define MOV_SOURCE(i) (FIELD (i, 20, 4)) | |
1573 | ||
1ba3e7a3 KB |
1574 | /* BRA disp12.align2 1011_dddd_dddd_ddd0 xxxx_xxxx_xxxx_xxxx */ |
1575 | #define IS_BRA(i) (((i) & 0xf0010000) == 0xb0000000) | |
1576 | #define BRA_DISP(i) (SFIELD (i, 17, 11) << 1) | |
1577 | ||
aeb43123 KB |
1578 | |
1579 | /* This structure holds the results of a prologue analysis. */ | |
1580 | struct mep_prologue | |
1581 | { | |
9dacea90 UW |
1582 | /* The architecture for which we generated this prologue info. */ |
1583 | struct gdbarch *gdbarch; | |
1584 | ||
aeb43123 KB |
1585 | /* The offset from the frame base to the stack pointer --- always |
1586 | zero or negative. | |
1587 | ||
1588 | Calling this a "size" is a bit misleading, but given that the | |
1589 | stack grows downwards, using offsets for everything keeps one | |
1590 | from going completely sign-crazy: you never change anything's | |
1591 | sign for an ADD instruction; always change the second operand's | |
1592 | sign for a SUB instruction; and everything takes care of | |
1593 | itself. */ | |
1594 | int frame_size; | |
1595 | ||
1596 | /* Non-zero if this function has initialized the frame pointer from | |
1597 | the stack pointer, zero otherwise. */ | |
1598 | int has_frame_ptr; | |
1599 | ||
1600 | /* If has_frame_ptr is non-zero, this is the offset from the frame | |
1601 | base to where the frame pointer points. This is always zero or | |
1602 | negative. */ | |
1603 | int frame_ptr_offset; | |
1604 | ||
1605 | /* The address of the first instruction at which the frame has been | |
1606 | set up and the arguments are where the debug info says they are | |
1607 | --- as best as we can tell. */ | |
1608 | CORE_ADDR prologue_end; | |
1609 | ||
1610 | /* reg_offset[R] is the offset from the CFA at which register R is | |
1611 | saved, or 1 if register R has not been saved. (Real values are | |
1612 | always zero or negative.) */ | |
1613 | int reg_offset[MEP_NUM_REGS]; | |
1614 | }; | |
1615 | ||
1616 | /* Return non-zero if VALUE is an incoming argument register. */ | |
1617 | ||
1618 | static int | |
1619 | is_arg_reg (pv_t value) | |
1620 | { | |
1621 | return (value.kind == pvk_register | |
dda83cd7 SM |
1622 | && MEP_R1_REGNUM <= value.reg && value.reg <= MEP_R4_REGNUM |
1623 | && value.k == 0); | |
aeb43123 KB |
1624 | } |
1625 | ||
1626 | /* Return non-zero if a store of REG's current value VALUE to ADDR is | |
1627 | probably spilling an argument register to its stack slot in STACK. | |
1628 | Such instructions should be included in the prologue, if possible. | |
1629 | ||
1630 | The store is a spill if: | |
1631 | - the value being stored is REG's original value; | |
1632 | - the value has not already been stored somewhere in STACK; and | |
1633 | - ADDR is a stack slot's address (e.g., relative to the original | |
1634 | value of the SP). */ | |
1635 | static int | |
9dacea90 UW |
1636 | is_arg_spill (struct gdbarch *gdbarch, pv_t value, pv_t addr, |
1637 | struct pv_area *stack) | |
aeb43123 KB |
1638 | { |
1639 | return (is_arg_reg (value) | |
dda83cd7 SM |
1640 | && pv_is_register (addr, MEP_SP_REGNUM) |
1641 | && ! stack->find_reg (gdbarch, value.reg, 0)); | |
aeb43123 KB |
1642 | } |
1643 | ||
1644 | ||
1645 | /* Function for finding saved registers in a 'struct pv_area'; we pass | |
f7b7ed97 | 1646 | this to pv_area::scan. |
aeb43123 KB |
1647 | |
1648 | If VALUE is a saved register, ADDR says it was saved at a constant | |
1649 | offset from the frame base, and SIZE indicates that the whole | |
1650 | register was saved, record its offset in RESULT_UNTYPED. */ | |
1651 | static void | |
1652 | check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value) | |
1653 | { | |
1654 | struct mep_prologue *result = (struct mep_prologue *) result_untyped; | |
1655 | ||
1656 | if (value.kind == pvk_register | |
1657 | && value.k == 0 | |
1658 | && pv_is_register (addr, MEP_SP_REGNUM) | |
9dacea90 | 1659 | && size == register_size (result->gdbarch, value.reg)) |
aeb43123 KB |
1660 | result->reg_offset[value.reg] = addr.k; |
1661 | } | |
1662 | ||
1663 | ||
1664 | /* Analyze a prologue starting at START_PC, going no further than | |
1665 | LIMIT_PC. Fill in RESULT as appropriate. */ | |
1666 | static void | |
9dacea90 UW |
1667 | mep_analyze_prologue (struct gdbarch *gdbarch, |
1668 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
dda83cd7 | 1669 | struct mep_prologue *result) |
aeb43123 KB |
1670 | { |
1671 | CORE_ADDR pc; | |
1672 | unsigned long insn; | |
aeb43123 | 1673 | pv_t reg[MEP_NUM_REGS]; |
aeb43123 KB |
1674 | CORE_ADDR after_last_frame_setup_insn = start_pc; |
1675 | ||
1676 | memset (result, 0, sizeof (*result)); | |
9dacea90 | 1677 | result->gdbarch = gdbarch; |
aeb43123 | 1678 | |
b926417a | 1679 | for (int rn = 0; rn < MEP_NUM_REGS; rn++) |
aeb43123 KB |
1680 | { |
1681 | reg[rn] = pv_register (rn, 0); | |
1682 | result->reg_offset[rn] = 1; | |
1683 | } | |
1684 | ||
f7b7ed97 | 1685 | pv_area stack (MEP_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
aeb43123 KB |
1686 | |
1687 | pc = start_pc; | |
1688 | while (pc < limit_pc) | |
1689 | { | |
1690 | CORE_ADDR next_pc; | |
1691 | pv_t pre_insn_fp, pre_insn_sp; | |
1692 | ||
e17a4113 | 1693 | next_pc = mep_get_insn (gdbarch, pc, &insn); |
aeb43123 KB |
1694 | |
1695 | /* A zero return from mep_get_insn means that either we weren't | |
dda83cd7 SM |
1696 | able to read the instruction from memory, or that we don't |
1697 | have enough information to be able to reliably decode it. So | |
1698 | we'll store here and hope for the best. */ | |
aeb43123 | 1699 | if (! next_pc) |
dda83cd7 | 1700 | break; |
aeb43123 KB |
1701 | |
1702 | /* Note the current values of the SP and FP, so we can tell if | |
dda83cd7 | 1703 | this instruction changed them, below. */ |
aeb43123 KB |
1704 | pre_insn_fp = reg[MEP_FP_REGNUM]; |
1705 | pre_insn_sp = reg[MEP_SP_REGNUM]; | |
1706 | ||
1707 | if (IS_ADD (insn)) | |
dda83cd7 SM |
1708 | { |
1709 | int rn = ADD_TARGET (insn); | |
1710 | CORE_ADDR imm6 = ADD_OFFSET (insn); | |
aeb43123 | 1711 | |
dda83cd7 SM |
1712 | reg[rn] = pv_add_constant (reg[rn], imm6); |
1713 | } | |
aeb43123 KB |
1714 | else if (IS_ADD3_16 (insn)) |
1715 | { | |
dda83cd7 SM |
1716 | int rn = ADD3_16_TARGET (insn); |
1717 | int imm7 = ADD3_16_OFFSET (insn); | |
aeb43123 | 1718 | |
dda83cd7 SM |
1719 | reg[rn] = pv_add_constant (reg[MEP_SP_REGNUM], imm7); |
1720 | } | |
aeb43123 KB |
1721 | else if (IS_ADD3_32 (insn)) |
1722 | { | |
dda83cd7 SM |
1723 | int rn = ADD3_32_TARGET (insn); |
1724 | int rm = ADD3_32_SOURCE (insn); | |
1725 | int imm16 = ADD3_32_OFFSET (insn); | |
aeb43123 | 1726 | |
dda83cd7 | 1727 | reg[rn] = pv_add_constant (reg[rm], imm16); |
aeb43123 KB |
1728 | } |
1729 | else if (IS_SW_REG (insn)) | |
dda83cd7 SM |
1730 | { |
1731 | int rn = SW_REG_SOURCE (insn); | |
1732 | int rm = SW_REG_BASE (insn); | |
1733 | ||
1734 | /* If simulating this store would require us to forget | |
1735 | everything we know about the stack frame in the name of | |
1736 | accuracy, it would be better to just quit now. */ | |
1737 | if (stack.store_would_trash (reg[rm])) | |
1738 | break; | |
1739 | ||
1740 | if (is_arg_spill (gdbarch, reg[rn], reg[rm], &stack)) | |
1741 | after_last_frame_setup_insn = next_pc; | |
1742 | ||
1743 | stack.store (reg[rm], 4, reg[rn]); | |
1744 | } | |
aeb43123 | 1745 | else if (IS_SW_IMMD (insn)) |
dda83cd7 SM |
1746 | { |
1747 | int rn = SW_IMMD_SOURCE (insn); | |
1748 | int offset = SW_IMMD_OFFSET (insn); | |
1749 | pv_t addr = pv_add_constant (reg[MEP_SP_REGNUM], offset); | |
1750 | ||
1751 | /* If simulating this store would require us to forget | |
1752 | everything we know about the stack frame in the name of | |
1753 | accuracy, it would be better to just quit now. */ | |
1754 | if (stack.store_would_trash (addr)) | |
1755 | break; | |
1756 | ||
1757 | if (is_arg_spill (gdbarch, reg[rn], addr, &stack)) | |
1758 | after_last_frame_setup_insn = next_pc; | |
1759 | ||
1760 | stack.store (addr, 4, reg[rn]); | |
1761 | } | |
aeb43123 KB |
1762 | else if (IS_MOV (insn)) |
1763 | { | |
dda83cd7 SM |
1764 | int rn = MOV_TARGET (insn); |
1765 | int rm = MOV_SOURCE (insn); | |
aeb43123 | 1766 | |
dda83cd7 | 1767 | reg[rn] = reg[rm]; |
aeb43123 KB |
1768 | |
1769 | if (pv_is_register (reg[rm], rm) && is_arg_reg (reg[rm])) | |
1770 | after_last_frame_setup_insn = next_pc; | |
1771 | } | |
1772 | else if (IS_SB (insn) || IS_SH (insn) || IS_SW (insn)) | |
1773 | { | |
dda83cd7 SM |
1774 | int rn = SWBH_32_SOURCE (insn); |
1775 | int rm = SWBH_32_BASE (insn); | |
1776 | int disp = SWBH_32_OFFSET (insn); | |
1777 | int size = (IS_SB (insn) ? 1 | |
1778 | : IS_SH (insn) ? 2 | |
1779 | : (gdb_assert (IS_SW (insn)), 4)); | |
1780 | pv_t addr = pv_add_constant (reg[rm], disp); | |
1781 | ||
1782 | if (stack.store_would_trash (addr)) | |
1783 | break; | |
1784 | ||
1785 | if (is_arg_spill (gdbarch, reg[rn], addr, &stack)) | |
1786 | after_last_frame_setup_insn = next_pc; | |
aeb43123 | 1787 | |
dda83cd7 | 1788 | stack.store (addr, size, reg[rn]); |
aeb43123 KB |
1789 | } |
1790 | else if (IS_LDC (insn)) | |
1791 | { | |
dda83cd7 SM |
1792 | int rn = LDC_TARGET (insn); |
1793 | int cr = LDC_IMM (insn) + MEP_FIRST_CSR_REGNUM; | |
aeb43123 | 1794 | |
dda83cd7 | 1795 | reg[rn] = reg[cr]; |
aeb43123 KB |
1796 | } |
1797 | else if (IS_LW (insn)) | |
dda83cd7 SM |
1798 | { |
1799 | int rn = LW_TARGET (insn); | |
1800 | int rm = LW_BASE (insn); | |
1801 | int offset = LW_OFFSET (insn); | |
1802 | pv_t addr = pv_add_constant (reg[rm], offset); | |
1803 | ||
1804 | reg[rn] = stack.fetch (addr, 4); | |
1805 | } | |
1ba3e7a3 KB |
1806 | else if (IS_BRA (insn) && BRA_DISP (insn) > 0) |
1807 | { | |
f219aedc | 1808 | /* When a loop appears as the first statement of a function |
1ba3e7a3 KB |
1809 | body, gcc 4.x will use a BRA instruction to branch to the |
1810 | loop condition checking code. This BRA instruction is | |
1811 | marked as part of the prologue. We therefore set next_pc | |
025bb325 | 1812 | to this branch target and also stop the prologue scan. |
1ba3e7a3 | 1813 | The instructions at and beyond the branch target should |
f219aedc KB |
1814 | no longer be associated with the prologue. |
1815 | ||
1816 | Note that we only consider forward branches here. We | |
1817 | presume that a forward branch is being used to skip over | |
1818 | a loop body. | |
1819 | ||
1820 | A backwards branch is covered by the default case below. | |
1821 | If we were to encounter a backwards branch, that would | |
1822 | most likely mean that we've scanned through a loop body. | |
1823 | We definitely want to stop the prologue scan when this | |
1824 | happens and that is precisely what is done by the default | |
1825 | case below. */ | |
1ba3e7a3 KB |
1826 | next_pc = pc + BRA_DISP (insn); |
1827 | after_last_frame_setup_insn = next_pc; | |
1828 | break; | |
1829 | } | |
aeb43123 | 1830 | else |
dda83cd7 SM |
1831 | /* We've hit some instruction we don't know how to simulate. |
1832 | Strictly speaking, we should set every value we're | |
1833 | tracking to "unknown". But we'll be optimistic, assume | |
1834 | that we have enough information already, and stop | |
1835 | analysis here. */ | |
1836 | break; | |
aeb43123 KB |
1837 | |
1838 | /* If this instruction changed the FP or decreased the SP (i.e., | |
dda83cd7 SM |
1839 | allocated more stack space), then this may be a good place to |
1840 | declare the prologue finished. However, there are some | |
1841 | exceptions: | |
aeb43123 | 1842 | |
dda83cd7 SM |
1843 | - If the instruction just changed the FP back to its original |
1844 | value, then that's probably a restore instruction. The | |
1845 | prologue should definitely end before that. | |
aeb43123 | 1846 | |
dda83cd7 SM |
1847 | - If the instruction increased the value of the SP (that is, |
1848 | shrunk the frame), then it's probably part of a frame | |
1849 | teardown sequence, and the prologue should end before that. */ | |
aeb43123 KB |
1850 | |
1851 | if (! pv_is_identical (reg[MEP_FP_REGNUM], pre_insn_fp)) | |
dda83cd7 SM |
1852 | { |
1853 | if (! pv_is_register_k (reg[MEP_FP_REGNUM], MEP_FP_REGNUM, 0)) | |
1854 | after_last_frame_setup_insn = next_pc; | |
1855 | } | |
aeb43123 | 1856 | else if (! pv_is_identical (reg[MEP_SP_REGNUM], pre_insn_sp)) |
dda83cd7 SM |
1857 | { |
1858 | /* The comparison of constants looks odd, there, because .k | |
1859 | is unsigned. All it really means is that the new value | |
1860 | is lower than it was before the instruction. */ | |
1861 | if (pv_is_register (pre_insn_sp, MEP_SP_REGNUM) | |
1862 | && pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM) | |
1863 | && ((pre_insn_sp.k - reg[MEP_SP_REGNUM].k) | |
1864 | < (reg[MEP_SP_REGNUM].k - pre_insn_sp.k))) | |
1865 | after_last_frame_setup_insn = next_pc; | |
1866 | } | |
aeb43123 KB |
1867 | |
1868 | pc = next_pc; | |
1869 | } | |
1870 | ||
1871 | /* Is the frame size (offset, really) a known constant? */ | |
1872 | if (pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM)) | |
1873 | result->frame_size = reg[MEP_SP_REGNUM].k; | |
1874 | ||
1875 | /* Was the frame pointer initialized? */ | |
1876 | if (pv_is_register (reg[MEP_FP_REGNUM], MEP_SP_REGNUM)) | |
1877 | { | |
1878 | result->has_frame_ptr = 1; | |
1879 | result->frame_ptr_offset = reg[MEP_FP_REGNUM].k; | |
1880 | } | |
1881 | ||
1882 | /* Record where all the registers were saved. */ | |
f7b7ed97 | 1883 | stack.scan (check_for_saved, (void *) result); |
aeb43123 KB |
1884 | |
1885 | result->prologue_end = after_last_frame_setup_insn; | |
aeb43123 KB |
1886 | } |
1887 | ||
1888 | ||
1889 | static CORE_ADDR | |
6093d2eb | 1890 | mep_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
aeb43123 | 1891 | { |
2c02bd72 | 1892 | const char *name; |
aeb43123 KB |
1893 | CORE_ADDR func_addr, func_end; |
1894 | struct mep_prologue p; | |
1895 | ||
1896 | /* Try to find the extent of the function that contains PC. */ | |
1897 | if (! find_pc_partial_function (pc, &name, &func_addr, &func_end)) | |
1898 | return pc; | |
1899 | ||
9dacea90 | 1900 | mep_analyze_prologue (gdbarch, pc, func_end, &p); |
aeb43123 KB |
1901 | return p.prologue_end; |
1902 | } | |
1903 | ||
1904 | ||
1905 | \f | |
1906 | /* Breakpoints. */ | |
04180708 | 1907 | constexpr gdb_byte mep_break_insn[] = { 0x70, 0x32 }; |
aeb43123 | 1908 | |
04180708 | 1909 | typedef BP_MANIPULATION (mep_break_insn) mep_breakpoint; |
aeb43123 KB |
1910 | |
1911 | \f | |
1912 | /* Frames and frame unwinding. */ | |
1913 | ||
1914 | ||
1915 | static struct mep_prologue * | |
bd2b40ac | 1916 | mep_analyze_frame_prologue (frame_info_ptr this_frame, |
dda83cd7 | 1917 | void **this_prologue_cache) |
aeb43123 KB |
1918 | { |
1919 | if (! *this_prologue_cache) | |
1920 | { | |
1921 | CORE_ADDR func_start, stop_addr; | |
1922 | ||
1923 | *this_prologue_cache | |
dda83cd7 | 1924 | = FRAME_OBSTACK_ZALLOC (struct mep_prologue); |
aeb43123 | 1925 | |
94afd7a6 UW |
1926 | func_start = get_frame_func (this_frame); |
1927 | stop_addr = get_frame_pc (this_frame); | |
aeb43123 KB |
1928 | |
1929 | /* If we couldn't find any function containing the PC, then | |
dda83cd7 | 1930 | just initialize the prologue cache, but don't do anything. */ |
aeb43123 | 1931 | if (! func_start) |
dda83cd7 | 1932 | stop_addr = func_start; |
aeb43123 | 1933 | |
9dacea90 | 1934 | mep_analyze_prologue (get_frame_arch (this_frame), |
19ba03f4 SM |
1935 | func_start, stop_addr, |
1936 | (struct mep_prologue *) *this_prologue_cache); | |
aeb43123 KB |
1937 | } |
1938 | ||
19ba03f4 | 1939 | return (struct mep_prologue *) *this_prologue_cache; |
aeb43123 KB |
1940 | } |
1941 | ||
1942 | ||
1943 | /* Given the next frame and a prologue cache, return this frame's | |
1944 | base. */ | |
1945 | static CORE_ADDR | |
bd2b40ac | 1946 | mep_frame_base (frame_info_ptr this_frame, |
dda83cd7 | 1947 | void **this_prologue_cache) |
aeb43123 KB |
1948 | { |
1949 | struct mep_prologue *p | |
94afd7a6 | 1950 | = mep_analyze_frame_prologue (this_frame, this_prologue_cache); |
aeb43123 KB |
1951 | |
1952 | /* In functions that use alloca, the distance between the stack | |
1953 | pointer and the frame base varies dynamically, so we can't use | |
1954 | the SP plus static information like prologue analysis to find the | |
1955 | frame base. However, such functions must have a frame pointer, | |
1956 | to be able to restore the SP on exit. So whenever we do have a | |
1957 | frame pointer, use that to find the base. */ | |
1958 | if (p->has_frame_ptr) | |
1959 | { | |
1960 | CORE_ADDR fp | |
dda83cd7 | 1961 | = get_frame_register_unsigned (this_frame, MEP_FP_REGNUM); |
aeb43123 KB |
1962 | return fp - p->frame_ptr_offset; |
1963 | } | |
1964 | else | |
1965 | { | |
1966 | CORE_ADDR sp | |
dda83cd7 | 1967 | = get_frame_register_unsigned (this_frame, MEP_SP_REGNUM); |
aeb43123 KB |
1968 | return sp - p->frame_size; |
1969 | } | |
1970 | } | |
1971 | ||
1972 | ||
1973 | static void | |
bd2b40ac | 1974 | mep_frame_this_id (frame_info_ptr this_frame, |
dda83cd7 SM |
1975 | void **this_prologue_cache, |
1976 | struct frame_id *this_id) | |
aeb43123 | 1977 | { |
94afd7a6 | 1978 | *this_id = frame_id_build (mep_frame_base (this_frame, this_prologue_cache), |
dda83cd7 | 1979 | get_frame_func (this_frame)); |
aeb43123 KB |
1980 | } |
1981 | ||
1982 | ||
94afd7a6 | 1983 | static struct value * |
bd2b40ac | 1984 | mep_frame_prev_register (frame_info_ptr this_frame, |
dda83cd7 | 1985 | void **this_prologue_cache, int regnum) |
aeb43123 KB |
1986 | { |
1987 | struct mep_prologue *p | |
94afd7a6 | 1988 | = mep_analyze_frame_prologue (this_frame, this_prologue_cache); |
aeb43123 KB |
1989 | |
1990 | /* There are a number of complications in unwinding registers on the | |
1991 | MeP, having to do with core functions calling VLIW functions and | |
1992 | vice versa. | |
1993 | ||
1994 | The least significant bit of the link register, LP.LTOM, is the | |
1995 | VLIW mode toggle bit: it's set if a core function called a VLIW | |
1996 | function, or vice versa, and clear when the caller and callee | |
1997 | were both in the same mode. | |
1998 | ||
1999 | So, if we're asked to unwind the PC, then we really want to | |
2000 | unwind the LP and clear the least significant bit. (Real return | |
2001 | addresses are always even.) And if we want to unwind the program | |
2002 | status word (PSW), we need to toggle PSW.OM if LP.LTOM is set. | |
2003 | ||
2004 | Tweaking the register values we return in this way means that the | |
2005 | bits in BUFFERP[] are not the same as the bits you'd find at | |
2006 | ADDRP in the inferior, so we make sure lvalp is not_lval when we | |
2007 | do this. */ | |
2008 | if (regnum == MEP_PC_REGNUM) | |
2009 | { | |
94afd7a6 UW |
2010 | struct value *value; |
2011 | CORE_ADDR lp; | |
2012 | value = mep_frame_prev_register (this_frame, this_prologue_cache, | |
2013 | MEP_LP_REGNUM); | |
2014 | lp = value_as_long (value); | |
2015 | release_value (value); | |
94afd7a6 UW |
2016 | |
2017 | return frame_unwind_got_constant (this_frame, regnum, lp & ~1); | |
aeb43123 KB |
2018 | } |
2019 | else | |
2020 | { | |
94afd7a6 UW |
2021 | CORE_ADDR frame_base = mep_frame_base (this_frame, this_prologue_cache); |
2022 | struct value *value; | |
aeb43123 KB |
2023 | |
2024 | /* Our caller's SP is our frame base. */ | |
2025 | if (regnum == MEP_SP_REGNUM) | |
94afd7a6 | 2026 | return frame_unwind_got_constant (this_frame, regnum, frame_base); |
aeb43123 KB |
2027 | |
2028 | /* If prologue analysis says we saved this register somewhere, | |
dda83cd7 | 2029 | return a description of the stack slot holding it. */ |
94afd7a6 UW |
2030 | if (p->reg_offset[regnum] != 1) |
2031 | value = frame_unwind_got_memory (this_frame, regnum, | |
2032 | frame_base + p->reg_offset[regnum]); | |
aeb43123 KB |
2033 | |
2034 | /* Otherwise, presume we haven't changed the value of this | |
dda83cd7 | 2035 | register, and get it from the next frame. */ |
aeb43123 | 2036 | else |
94afd7a6 | 2037 | value = frame_unwind_got_register (this_frame, regnum, regnum); |
aeb43123 KB |
2038 | |
2039 | /* If we need to toggle the operating mode, do so. */ | |
2040 | if (regnum == MEP_PSW_REGNUM) | |
dda83cd7 | 2041 | { |
94afd7a6 UW |
2042 | CORE_ADDR psw, lp; |
2043 | ||
2044 | psw = value_as_long (value); | |
2045 | release_value (value); | |
aeb43123 | 2046 | |
dda83cd7 | 2047 | /* Get the LP's value, too. */ |
94afd7a6 UW |
2048 | value = get_frame_register_value (this_frame, MEP_LP_REGNUM); |
2049 | lp = value_as_long (value); | |
2050 | release_value (value); | |
aeb43123 | 2051 | |
dda83cd7 | 2052 | /* If LP.LTOM is set, then toggle PSW.OM. */ |
94afd7a6 UW |
2053 | if (lp & 0x1) |
2054 | psw ^= 0x1000; | |
2055 | ||
2056 | return frame_unwind_got_constant (this_frame, regnum, psw); | |
dda83cd7 | 2057 | } |
94afd7a6 UW |
2058 | |
2059 | return value; | |
aeb43123 KB |
2060 | } |
2061 | } | |
2062 | ||
2063 | ||
2064 | static const struct frame_unwind mep_frame_unwind = { | |
a154d838 | 2065 | "mep prologue", |
aeb43123 | 2066 | NORMAL_FRAME, |
8fbca658 | 2067 | default_frame_unwind_stop_reason, |
aeb43123 | 2068 | mep_frame_this_id, |
94afd7a6 UW |
2069 | mep_frame_prev_register, |
2070 | NULL, | |
2071 | default_frame_sniffer | |
aeb43123 KB |
2072 | }; |
2073 | ||
aeb43123 KB |
2074 | \f |
2075 | /* Return values. */ | |
2076 | ||
2077 | ||
2078 | static int | |
2079 | mep_use_struct_convention (struct type *type) | |
2080 | { | |
df86565b | 2081 | return (type->length () > MEP_GPR_SIZE); |
aeb43123 KB |
2082 | } |
2083 | ||
2084 | ||
2085 | static void | |
2086 | mep_extract_return_value (struct gdbarch *arch, | |
dda83cd7 SM |
2087 | struct type *type, |
2088 | struct regcache *regcache, | |
2089 | gdb_byte *valbuf) | |
aeb43123 KB |
2090 | { |
2091 | int byte_order = gdbarch_byte_order (arch); | |
2092 | ||
2093 | /* Values that don't occupy a full register appear at the less | |
2094 | significant end of the value. This is the offset to where the | |
2095 | value starts. */ | |
2096 | int offset; | |
2097 | ||
2098 | /* Return values > MEP_GPR_SIZE bytes are returned in memory, | |
2099 | pointed to by R0. */ | |
df86565b | 2100 | gdb_assert (type->length () <= MEP_GPR_SIZE); |
aeb43123 KB |
2101 | |
2102 | if (byte_order == BFD_ENDIAN_BIG) | |
df86565b | 2103 | offset = MEP_GPR_SIZE - type->length (); |
aeb43123 KB |
2104 | else |
2105 | offset = 0; | |
2106 | ||
025bb325 | 2107 | /* Return values that do fit in a single register are returned in R0. */ |
df86565b | 2108 | regcache->cooked_read_part (MEP_R0_REGNUM, offset, type->length (), |
73bb0000 | 2109 | valbuf); |
aeb43123 KB |
2110 | } |
2111 | ||
2112 | ||
2113 | static void | |
2114 | mep_store_return_value (struct gdbarch *arch, | |
dda83cd7 SM |
2115 | struct type *type, |
2116 | struct regcache *regcache, | |
2117 | const gdb_byte *valbuf) | |
aeb43123 KB |
2118 | { |
2119 | int byte_order = gdbarch_byte_order (arch); | |
2120 | ||
2121 | /* Values that fit in a single register go in R0. */ | |
df86565b | 2122 | if (type->length () <= MEP_GPR_SIZE) |
aeb43123 KB |
2123 | { |
2124 | /* Values that don't occupy a full register appear at the least | |
dda83cd7 SM |
2125 | significant end of the value. This is the offset to where the |
2126 | value starts. */ | |
aeb43123 KB |
2127 | int offset; |
2128 | ||
2129 | if (byte_order == BFD_ENDIAN_BIG) | |
df86565b | 2130 | offset = MEP_GPR_SIZE - type->length (); |
aeb43123 | 2131 | else |
dda83cd7 | 2132 | offset = 0; |
aeb43123 | 2133 | |
df86565b | 2134 | regcache->cooked_write_part (MEP_R0_REGNUM, offset, type->length (), |
e4c4a59b | 2135 | valbuf); |
aeb43123 KB |
2136 | } |
2137 | ||
2138 | /* Return values larger than a single register are returned in | |
2139 | memory, pointed to by R0. Unfortunately, we can't count on R0 | |
025bb325 | 2140 | pointing to the return buffer, so we raise an error here. */ |
aeb43123 | 2141 | else |
a73c6dcd MS |
2142 | error (_("\ |
2143 | GDB cannot set return values larger than four bytes; the Media Processor's\n\ | |
2144 | calling conventions do not provide enough information to do this.\n\ | |
2145 | Try using the 'return' command with no argument.")); | |
aeb43123 KB |
2146 | } |
2147 | ||
63807e1d | 2148 | static enum return_value_convention |
6a3a010b | 2149 | mep_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
2150 | struct type *type, struct regcache *regcache, |
2151 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
aeb43123 KB |
2152 | { |
2153 | if (mep_use_struct_convention (type)) | |
2154 | { | |
2155 | if (readbuf) | |
2156 | { | |
2157 | ULONGEST addr; | |
2158 | /* Although the address of the struct buffer gets passed in R1, it's | |
2159 | returned in R0. Fetch R0's value and then read the memory | |
2160 | at that address. */ | |
2161 | regcache_raw_read_unsigned (regcache, MEP_R0_REGNUM, &addr); | |
df86565b | 2162 | read_memory (addr, readbuf, type->length ()); |
aeb43123 KB |
2163 | } |
2164 | if (writebuf) | |
2165 | { | |
2166 | /* Return values larger than a single register are returned in | |
2167 | memory, pointed to by R0. Unfortunately, we can't count on R0 | |
025bb325 | 2168 | pointing to the return buffer, so we raise an error here. */ |
a73c6dcd MS |
2169 | error (_("\ |
2170 | GDB cannot set return values larger than four bytes; the Media Processor's\n\ | |
2171 | calling conventions do not provide enough information to do this.\n\ | |
2172 | Try using the 'return' command with no argument.")); | |
aeb43123 KB |
2173 | } |
2174 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
2175 | } | |
2176 | ||
2177 | if (readbuf) | |
2178 | mep_extract_return_value (gdbarch, type, regcache, readbuf); | |
2179 | if (writebuf) | |
2180 | mep_store_return_value (gdbarch, type, regcache, writebuf); | |
2181 | ||
2182 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2183 | } | |
2184 | ||
2185 | \f | |
2186 | /* Inferior calls. */ | |
2187 | ||
2188 | ||
2189 | static CORE_ADDR | |
2190 | mep_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2191 | { | |
2192 | /* Require word alignment. */ | |
2193 | return sp & -4; | |
2194 | } | |
2195 | ||
2196 | ||
2197 | /* From "lang_spec2.txt": | |
2198 | ||
2199 | 4.2 Calling conventions | |
2200 | ||
2201 | 4.2.1 Core register conventions | |
2202 | ||
2203 | - Parameters should be evaluated from left to right, and they | |
025bb325 MS |
2204 | should be held in $1,$2,$3,$4 in order. The fifth parameter or |
2205 | after should be held in the stack. If the size is larger than 4 | |
aeb43123 | 2206 | bytes in the first four parameters, the pointer should be held in |
025bb325 | 2207 | the registers instead. If the size is larger than 4 bytes in the |
aeb43123 KB |
2208 | fifth parameter or after, the pointer should be held in the stack. |
2209 | ||
025bb325 | 2210 | - Return value of a function should be held in register $0. If the |
aeb43123 | 2211 | size of return value is larger than 4 bytes, $1 should hold the |
025bb325 | 2212 | pointer pointing memory that would hold the return value. In this |
aeb43123 KB |
2213 | case, the first parameter should be held in $2, the second one in |
2214 | $3, and the third one in $4, and the forth parameter or after | |
2215 | should be held in the stack. | |
2216 | ||
2217 | [This doesn't say so, but arguments shorter than four bytes are | |
2218 | passed in the least significant end of a four-byte word when | |
2219 | they're passed on the stack.] */ | |
2220 | ||
2221 | ||
2222 | /* Traverse the list of ARGC arguments ARGV; for every ARGV[i] too | |
2223 | large to fit in a register, save it on the stack, and place its | |
2224 | address in COPY[i]. SP is the initial stack pointer; return the | |
2225 | new stack pointer. */ | |
2226 | static CORE_ADDR | |
2227 | push_large_arguments (CORE_ADDR sp, int argc, struct value **argv, | |
dda83cd7 | 2228 | CORE_ADDR copy[]) |
aeb43123 KB |
2229 | { |
2230 | int i; | |
2231 | ||
2232 | for (i = 0; i < argc; i++) | |
2233 | { | |
d0c97917 | 2234 | unsigned arg_len = argv[i]->type ()->length (); |
aeb43123 KB |
2235 | |
2236 | if (arg_len > MEP_GPR_SIZE) | |
dda83cd7 SM |
2237 | { |
2238 | /* Reserve space for the copy, and then round the SP down, to | |
2239 | make sure it's all aligned properly. */ | |
2240 | sp = (sp - arg_len) & -4; | |
efaf1ae0 | 2241 | write_memory (sp, argv[i]->contents ().data (), arg_len); |
dda83cd7 SM |
2242 | copy[i] = sp; |
2243 | } | |
aeb43123 KB |
2244 | } |
2245 | ||
2246 | return sp; | |
2247 | } | |
2248 | ||
2249 | ||
2250 | static CORE_ADDR | |
2251 | mep_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
dda83cd7 SM |
2252 | struct regcache *regcache, CORE_ADDR bp_addr, |
2253 | int argc, struct value **argv, CORE_ADDR sp, | |
cf84fa6b | 2254 | function_call_return_method return_method, |
dda83cd7 | 2255 | CORE_ADDR struct_addr) |
aeb43123 | 2256 | { |
e17a4113 | 2257 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
aeb43123 | 2258 | CORE_ADDR *copy = (CORE_ADDR *) alloca (argc * sizeof (copy[0])); |
aeb43123 KB |
2259 | int i; |
2260 | ||
2261 | /* The number of the next register available to hold an argument. */ | |
2262 | int arg_reg; | |
2263 | ||
2264 | /* The address of the next stack slot available to hold an argument. */ | |
2265 | CORE_ADDR arg_stack; | |
2266 | ||
2267 | /* The address of the end of the stack area for arguments. This is | |
2268 | just for error checking. */ | |
2269 | CORE_ADDR arg_stack_end; | |
2270 | ||
2271 | sp = push_large_arguments (sp, argc, argv, copy); | |
2272 | ||
2273 | /* Reserve space for the stack arguments, if any. */ | |
2274 | arg_stack_end = sp; | |
2275 | if (argc + (struct_addr ? 1 : 0) > 4) | |
2276 | sp -= ((argc + (struct_addr ? 1 : 0)) - 4) * MEP_GPR_SIZE; | |
2277 | ||
2278 | arg_reg = MEP_R1_REGNUM; | |
2279 | arg_stack = sp; | |
2280 | ||
2281 | /* If we're returning a structure by value, push the pointer to the | |
2282 | buffer as the first argument. */ | |
cf84fa6b | 2283 | if (return_method == return_method_struct) |
aeb43123 KB |
2284 | { |
2285 | regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr); | |
2286 | arg_reg++; | |
2287 | } | |
2288 | ||
2289 | for (i = 0; i < argc; i++) | |
2290 | { | |
aeb43123 KB |
2291 | ULONGEST value; |
2292 | ||
2293 | /* Arguments that fit in a GPR get expanded to fill the GPR. */ | |
d0c97917 | 2294 | if (argv[i]->type ()->length () <= MEP_GPR_SIZE) |
efaf1ae0 | 2295 | value = extract_unsigned_integer (argv[i]->contents ().data (), |
d0c97917 | 2296 | argv[i]->type ()->length (), |
e17a4113 | 2297 | byte_order); |
aeb43123 KB |
2298 | |
2299 | /* Arguments too large to fit in a GPR get copied to the stack, | |
dda83cd7 | 2300 | and we pass a pointer to the copy. */ |
aeb43123 | 2301 | else |
dda83cd7 | 2302 | value = copy[i]; |
aeb43123 KB |
2303 | |
2304 | /* We use $1 -- $4 for passing arguments, then use the stack. */ | |
2305 | if (arg_reg <= MEP_R4_REGNUM) | |
dda83cd7 SM |
2306 | { |
2307 | regcache_cooked_write_unsigned (regcache, arg_reg, value); | |
2308 | arg_reg++; | |
2309 | } | |
aeb43123 | 2310 | else |
dda83cd7 SM |
2311 | { |
2312 | gdb_byte buf[MEP_GPR_SIZE]; | |
2313 | store_unsigned_integer (buf, MEP_GPR_SIZE, byte_order, value); | |
2314 | write_memory (arg_stack, buf, MEP_GPR_SIZE); | |
2315 | arg_stack += MEP_GPR_SIZE; | |
2316 | } | |
aeb43123 KB |
2317 | } |
2318 | ||
2319 | gdb_assert (arg_stack <= arg_stack_end); | |
2320 | ||
2321 | /* Set the return address. */ | |
2322 | regcache_cooked_write_unsigned (regcache, MEP_LP_REGNUM, bp_addr); | |
2323 | ||
2324 | /* Update the stack pointer. */ | |
2325 | regcache_cooked_write_unsigned (regcache, MEP_SP_REGNUM, sp); | |
2326 | ||
2327 | return sp; | |
2328 | } | |
2329 | ||
aeb43123 KB |
2330 | \f |
2331 | /* Initialization. */ | |
2332 | ||
2333 | ||
2334 | static struct gdbarch * | |
2335 | mep_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
2336 | { | |
aeb43123 KB |
2337 | /* Which me_module are we building a gdbarch object for? */ |
2338 | CONFIG_ATTR me_module; | |
2339 | ||
2340 | /* If we have a BFD in hand, figure out which me_module it was built | |
2341 | for. Otherwise, use the no-particular-me_module code. */ | |
2342 | if (info.abfd) | |
2343 | { | |
2344 | /* The way to get the me_module code depends on the object file | |
dda83cd7 | 2345 | format. At the moment, we only know how to handle ELF. */ |
aeb43123 | 2346 | if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
f54b226f SM |
2347 | { |
2348 | int flag = elf_elfheader (info.abfd)->e_flags & EF_MEP_INDEX_MASK; | |
2349 | me_module = (CONFIG_ATTR) flag; | |
2350 | } | |
aeb43123 | 2351 | else |
dda83cd7 | 2352 | me_module = CONFIG_NONE; |
aeb43123 KB |
2353 | } |
2354 | else | |
2355 | me_module = CONFIG_NONE; | |
2356 | ||
2357 | /* If we're setting the architecture from a file, check the | |
2358 | endianness of the file against that of the me_module. */ | |
2359 | if (info.abfd) | |
2360 | { | |
2361 | /* The negations on either side make the comparison treat all | |
dda83cd7 | 2362 | non-zero (true) values as equal. */ |
aeb43123 | 2363 | if (! bfd_big_endian (info.abfd) != ! me_module_big_endian (me_module)) |
dda83cd7 SM |
2364 | { |
2365 | const char *module_name = me_module_name (me_module); | |
2366 | const char *module_endianness | |
2367 | = me_module_big_endian (me_module) ? "big" : "little"; | |
2368 | const char *file_name = bfd_get_filename (info.abfd); | |
2369 | const char *file_endianness | |
2370 | = bfd_big_endian (info.abfd) ? "big" : "little"; | |
2371 | ||
a11ac3b3 | 2372 | gdb_putc ('\n', gdb_stderr); |
dda83cd7 SM |
2373 | if (module_name) |
2374 | warning (_("the MeP module '%s' is %s-endian, but the executable\n" | |
a73c6dcd | 2375 | "%s is %s-endian."), |
dda83cd7 SM |
2376 | module_name, module_endianness, |
2377 | file_name, file_endianness); | |
2378 | else | |
2379 | warning (_("the selected MeP module is %s-endian, but the " | |
a73c6dcd MS |
2380 | "executable\n" |
2381 | "%s is %s-endian."), | |
dda83cd7 SM |
2382 | module_endianness, file_name, file_endianness); |
2383 | } | |
aeb43123 KB |
2384 | } |
2385 | ||
2386 | /* Find a candidate among the list of architectures we've created | |
2387 | already. info->bfd_arch_info needs to match, but we also want | |
2388 | the right me_module: the ELF header's e_flags field needs to | |
2389 | match as well. */ | |
2390 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
2391 | arches != NULL; | |
2392 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
345bd07c SM |
2393 | { |
2394 | mep_gdbarch_tdep *tdep | |
08106042 | 2395 | = gdbarch_tdep<mep_gdbarch_tdep> (arches->gdbarch); |
345bd07c SM |
2396 | |
2397 | if (tdep->me_module == me_module) | |
2398 | return arches->gdbarch; | |
2399 | } | |
aeb43123 | 2400 | |
2b16913c SM |
2401 | gdbarch *gdbarch |
2402 | = gdbarch_alloc (&info, gdbarch_tdep_up (new mep_gdbarch_tdep)); | |
2403 | mep_gdbarch_tdep *tdep = gdbarch_tdep<mep_gdbarch_tdep> (gdbarch); | |
aeb43123 KB |
2404 | |
2405 | /* Get a CGEN CPU descriptor for this architecture. */ | |
2406 | { | |
2407 | const char *mach_name = info.bfd_arch_info->printable_name; | |
2408 | enum cgen_endian endian = (info.byte_order == BFD_ENDIAN_BIG | |
dda83cd7 SM |
2409 | ? CGEN_ENDIAN_BIG |
2410 | : CGEN_ENDIAN_LITTLE); | |
aeb43123 KB |
2411 | |
2412 | tdep->cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, | |
dda83cd7 SM |
2413 | CGEN_CPU_OPEN_ENDIAN, endian, |
2414 | CGEN_CPU_OPEN_END); | |
aeb43123 KB |
2415 | } |
2416 | ||
2417 | tdep->me_module = me_module; | |
2418 | ||
2419 | /* Register set. */ | |
aeb43123 | 2420 | set_gdbarch_num_regs (gdbarch, MEP_NUM_RAW_REGS); |
54746424 | 2421 | set_gdbarch_pc_regnum (gdbarch, MEP_PC_REGNUM); |
aeb43123 KB |
2422 | set_gdbarch_sp_regnum (gdbarch, MEP_SP_REGNUM); |
2423 | set_gdbarch_register_name (gdbarch, mep_register_name); | |
2424 | set_gdbarch_register_type (gdbarch, mep_register_type); | |
2425 | set_gdbarch_num_pseudo_regs (gdbarch, MEP_NUM_PSEUDO_REGS); | |
2426 | set_gdbarch_pseudo_register_read (gdbarch, mep_pseudo_register_read); | |
2427 | set_gdbarch_pseudo_register_write (gdbarch, mep_pseudo_register_write); | |
2428 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum); | |
2429 | set_gdbarch_stab_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum); | |
2430 | ||
2431 | set_gdbarch_register_reggroup_p (gdbarch, mep_register_reggroup_p); | |
aeb43123 KB |
2432 | reggroup_add (gdbarch, mep_csr_reggroup); |
2433 | reggroup_add (gdbarch, mep_cr_reggroup); | |
2434 | reggroup_add (gdbarch, mep_ccr_reggroup); | |
2435 | ||
2436 | /* Disassembly. */ | |
2437 | set_gdbarch_print_insn (gdbarch, mep_gdb_print_insn); | |
2438 | ||
2439 | /* Breakpoints. */ | |
04180708 YQ |
2440 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, mep_breakpoint::kind_from_pc); |
2441 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, mep_breakpoint::bp_from_kind); | |
aeb43123 KB |
2442 | set_gdbarch_decr_pc_after_break (gdbarch, 0); |
2443 | set_gdbarch_skip_prologue (gdbarch, mep_skip_prologue); | |
2444 | ||
2445 | /* Frames and frame unwinding. */ | |
94afd7a6 | 2446 | frame_unwind_append_unwinder (gdbarch, &mep_frame_unwind); |
aeb43123 KB |
2447 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
2448 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
2449 | ||
2450 | /* Return values. */ | |
2451 | set_gdbarch_return_value (gdbarch, mep_return_value); | |
2452 | ||
2453 | /* Inferior function calls. */ | |
2454 | set_gdbarch_frame_align (gdbarch, mep_frame_align); | |
2455 | set_gdbarch_push_dummy_call (gdbarch, mep_push_dummy_call); | |
aeb43123 KB |
2456 | |
2457 | return gdbarch; | |
2458 | } | |
2459 | ||
6c265988 | 2460 | void _initialize_mep_tdep (); |
aeb43123 | 2461 | void |
6c265988 | 2462 | _initialize_mep_tdep () |
aeb43123 KB |
2463 | { |
2464 | mep_csr_reggroup = reggroup_new ("csr", USER_REGGROUP); | |
2465 | mep_cr_reggroup = reggroup_new ("cr", USER_REGGROUP); | |
2466 | mep_ccr_reggroup = reggroup_new ("ccr", USER_REGGROUP); | |
2467 | ||
ec29a63c | 2468 | gdbarch_register (bfd_arch_mep, mep_gdbarch_init); |
aeb43123 KB |
2469 | |
2470 | mep_init_pseudoregister_maps (); | |
2471 | } |