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75c9abc6 | 1 | /* Native-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
1d506c26 | 3 | Copyright (C) 2001-2024 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 | 19 | |
b9412953 DD |
20 | #include "command.h" |
21 | #include "gdbcmd.h" | |
d37eb719 | 22 | #include "inferior.h" |
6b753f60 | 23 | #include "mips-tdep.h" |
10d6c8cd | 24 | #include "target.h" |
28f5035f | 25 | #include "regcache.h" |
6798487f | 26 | #include "linux-nat-trad.h" |
d37eb719 | 27 | #include "mips-linux-tdep.h" |
822b6570 | 28 | #include "target-descriptions.h" |
2aa830e4 | 29 | |
dc60ece8 | 30 | #include "gdb_proc_service.h" |
3e00823e | 31 | #include "gregset.h" |
dc60ece8 | 32 | |
822b6570 | 33 | #include <sgidefs.h> |
5826e159 | 34 | #include "nat/gdb_ptrace.h" |
9be14b81 | 35 | #include <asm/ptrace.h> |
bcc0c096 | 36 | #include "inf-ptrace.h" |
d37eb719 | 37 | |
125f8a3d | 38 | #include "nat/mips-linux-watch.h" |
aaee2056 | 39 | |
dc60ece8 DJ |
40 | #ifndef PTRACE_GET_THREAD_AREA |
41 | #define PTRACE_GET_THREAD_AREA 25 | |
42 | #endif | |
43 | ||
f6ac5f3d PA |
44 | class mips_linux_nat_target final : public linux_nat_trad_target |
45 | { | |
46 | public: | |
47 | /* Add our register access methods. */ | |
48 | void fetch_registers (struct regcache *, int) override; | |
49 | void store_registers (struct regcache *, int) override; | |
50 | ||
51 | void close () override; | |
52 | ||
53 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
54 | ||
55 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
56 | struct expression *) override; | |
57 | ||
58 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
59 | struct expression *) override; | |
60 | ||
57810aa7 | 61 | bool stopped_by_watchpoint () override; |
f6ac5f3d | 62 | |
57810aa7 | 63 | bool stopped_data_address (CORE_ADDR *) override; |
d37eb719 | 64 | |
f6ac5f3d | 65 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; |
d37eb719 | 66 | |
f6ac5f3d | 67 | const struct target_desc *read_description () override; |
b9412953 | 68 | |
f6ac5f3d PA |
69 | protected: |
70 | /* Override linux_nat_trad_target methods. */ | |
71 | CORE_ADDR register_u_offset (struct gdbarch *gdbarch, | |
72 | int regno, int store_p) override; | |
73 | ||
135340af PA |
74 | /* Override linux_nat_target low methods. */ |
75 | void low_new_thread (struct lwp_info *lp) override; | |
76 | ||
f6ac5f3d PA |
77 | private: |
78 | /* Helpers. See definitions. */ | |
79 | void mips64_regsets_store_registers (struct regcache *regcache, | |
80 | int regno); | |
81 | void mips64_regsets_fetch_registers (struct regcache *regcache, | |
82 | int regno); | |
83 | }; | |
84 | ||
85 | static mips_linux_nat_target the_mips_linux_nat_target; | |
86 | ||
87 | /* Assume that we have PTRACE_GETREGS et al. support. If we do not, | |
88 | we'll clear this and use PTRACE_PEEKUSER instead. */ | |
89 | static int have_ptrace_regsets = 1; | |
d37eb719 | 90 | |
dda0c97e | 91 | /* Map gdb internal register number to ptrace ``address''. |
7714d83a UW |
92 | These ``addresses'' are normally defined in <asm/ptrace.h>. |
93 | ||
94 | ptrace does not provide a way to read (or set) MIPS_PS_REGNUM, | |
95 | and there's no point in reading or setting MIPS_ZERO_REGNUM. | |
96 | We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */ | |
dda0c97e UW |
97 | |
98 | static CORE_ADDR | |
7714d83a | 99 | mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 100 | { |
7714d83a | 101 | CORE_ADDR regaddr; |
dda0c97e | 102 | |
2eb4d78b | 103 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
104 | error (_("Bogon register number %d."), regno); |
105 | ||
7714d83a | 106 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 107 | regaddr = regno; |
7714d83a UW |
108 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
109 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
110 | regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); | |
111 | else if (regno == mips_regnum (gdbarch)->pc) | |
dda0c97e | 112 | regaddr = PC; |
7714d83a UW |
113 | else if (regno == mips_regnum (gdbarch)->cause) |
114 | regaddr = store? (CORE_ADDR) -1 : CAUSE; | |
115 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
116 | regaddr = store? (CORE_ADDR) -1 : BADVADDR; | |
117 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 118 | regaddr = MMLO; |
7714d83a | 119 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 120 | regaddr = MMHI; |
7714d83a | 121 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 122 | regaddr = FPC_CSR; |
7714d83a UW |
123 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
124 | regaddr = store? (CORE_ADDR) -1 : FPC_EIR; | |
1faeff08 MR |
125 | else if (mips_regnum (gdbarch)->dspacc != -1 |
126 | && regno >= mips_regnum (gdbarch)->dspacc | |
127 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
128 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
129 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
130 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
131 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
132 | regaddr = 0; | |
dda0c97e | 133 | else |
7714d83a | 134 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
135 | |
136 | return regaddr; | |
137 | } | |
138 | ||
139 | static CORE_ADDR | |
7714d83a | 140 | mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) |
dda0c97e | 141 | { |
7714d83a | 142 | CORE_ADDR regaddr; |
dda0c97e | 143 | |
2eb4d78b | 144 | if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda0c97e UW |
145 | error (_("Bogon register number %d."), regno); |
146 | ||
75d74cca MR |
147 | /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR |
148 | or PTRACE_POKEUSR. */ | |
149 | if (register_size (gdbarch, regno) > sizeof (PTRACE_TYPE_RET)) | |
150 | return (CORE_ADDR) -1; | |
151 | ||
7714d83a | 152 | if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) |
dda0c97e | 153 | regaddr = regno; |
7714d83a UW |
154 | else if ((regno >= mips_regnum (gdbarch)->fp0) |
155 | && (regno < mips_regnum (gdbarch)->fp0 + 32)) | |
2eb4d78b | 156 | regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch)); |
7714d83a | 157 | else if (regno == mips_regnum (gdbarch)->pc) |
dda0c97e | 158 | regaddr = MIPS64_PC; |
7714d83a UW |
159 | else if (regno == mips_regnum (gdbarch)->cause) |
160 | regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE; | |
161 | else if (regno == mips_regnum (gdbarch)->badvaddr) | |
162 | regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR; | |
163 | else if (regno == mips_regnum (gdbarch)->lo) | |
dda0c97e | 164 | regaddr = MIPS64_MMLO; |
7714d83a | 165 | else if (regno == mips_regnum (gdbarch)->hi) |
dda0c97e | 166 | regaddr = MIPS64_MMHI; |
7714d83a | 167 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
dda0c97e | 168 | regaddr = MIPS64_FPC_CSR; |
7714d83a UW |
169 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
170 | regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR; | |
1faeff08 MR |
171 | else if (mips_regnum (gdbarch)->dspacc != -1 |
172 | && regno >= mips_regnum (gdbarch)->dspacc | |
173 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
174 | regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc); | |
175 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
176 | regaddr = DSP_CONTROL; | |
822b6570 DJ |
177 | else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) |
178 | regaddr = 0; | |
dda0c97e | 179 | else |
7714d83a | 180 | regaddr = (CORE_ADDR) -1; |
dda0c97e UW |
181 | |
182 | return regaddr; | |
183 | } | |
184 | ||
dc60ece8 DJ |
185 | /* Fetch the thread-local storage pointer for libthread_db. */ |
186 | ||
187 | ps_err_e | |
754653a7 | 188 | ps_get_thread_area (struct ps_prochandle *ph, |
dda83cd7 | 189 | lwpid_t lwpid, int idx, void **base) |
dc60ece8 DJ |
190 | { |
191 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
192 | return PS_ERR; | |
193 | ||
194 | /* IDX is the bias from the thread pointer to the beginning of the | |
195 | thread descriptor. It has to be subtracted due to implementation | |
196 | quirks in libthread_db. */ | |
197 | *base = (void *) ((char *)*base - idx); | |
198 | ||
199 | return PS_OK; | |
200 | } | |
201 | ||
3e00823e UW |
202 | /* Wrapper functions. These are only used by libthread_db. */ |
203 | ||
204 | void | |
7f7fe91e | 205 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
3e00823e | 206 | { |
ac7936df | 207 | if (mips_isa_regsize (regcache->arch ()) == 4) |
7f7fe91e | 208 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp); |
3e00823e | 209 | else |
7f7fe91e | 210 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp); |
3e00823e UW |
211 | } |
212 | ||
213 | void | |
7f7fe91e UW |
214 | fill_gregset (const struct regcache *regcache, |
215 | gdb_gregset_t *gregsetp, int regno) | |
3e00823e | 216 | { |
ac7936df | 217 | if (mips_isa_regsize (regcache->arch ()) == 4) |
7f7fe91e | 218 | mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno); |
3e00823e | 219 | else |
7f7fe91e | 220 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno); |
3e00823e UW |
221 | } |
222 | ||
223 | void | |
7f7fe91e | 224 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
3e00823e | 225 | { |
d8dab6c3 | 226 | mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *) fpregsetp); |
3e00823e UW |
227 | } |
228 | ||
229 | void | |
7f7fe91e UW |
230 | fill_fpregset (const struct regcache *regcache, |
231 | gdb_fpregset_t *fpregsetp, int regno) | |
3e00823e | 232 | { |
d8dab6c3 | 233 | mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *) fpregsetp, regno); |
3e00823e UW |
234 | } |
235 | ||
236 | ||
d37eb719 DJ |
237 | /* Fetch REGNO (or all registers if REGNO == -1) from the target |
238 | using PTRACE_GETREGS et al. */ | |
239 | ||
f6ac5f3d PA |
240 | void |
241 | mips_linux_nat_target::mips64_regsets_fetch_registers | |
242 | (struct regcache *regcache, int regno) | |
d37eb719 | 243 | { |
ac7936df | 244 | struct gdbarch *gdbarch = regcache->arch (); |
1faeff08 MR |
245 | int is_fp, is_dsp; |
246 | int have_dsp; | |
247 | int regi; | |
d37eb719 DJ |
248 | int tid; |
249 | ||
2eb4d78b UW |
250 | if (regno >= mips_regnum (gdbarch)->fp0 |
251 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 252 | is_fp = 1; |
2eb4d78b | 253 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 254 | is_fp = 1; |
2eb4d78b | 255 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
256 | is_fp = 1; |
257 | else | |
258 | is_fp = 0; | |
259 | ||
1faeff08 MR |
260 | /* DSP registers are optional and not a part of any set. */ |
261 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
262 | if (!have_dsp) | |
263 | is_dsp = 0; | |
264 | else if (regno >= mips_regnum (gdbarch)->dspacc | |
265 | && regno < mips_regnum (gdbarch)->dspacc + 6) | |
266 | is_dsp = 1; | |
267 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
268 | is_dsp = 1; | |
269 | else | |
270 | is_dsp = 0; | |
271 | ||
222312d3 | 272 | tid = get_ptrace_pid (regcache->ptid ()); |
d37eb719 | 273 | |
1faeff08 | 274 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
275 | { |
276 | mips64_elf_gregset_t regs; | |
277 | ||
278 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
279 | { | |
280 | if (errno == EIO) | |
281 | { | |
282 | have_ptrace_regsets = 0; | |
283 | return; | |
284 | } | |
285 | perror_with_name (_("Couldn't get registers")); | |
286 | } | |
287 | ||
56be3814 | 288 | mips64_supply_gregset (regcache, |
28f5035f | 289 | (const mips64_elf_gregset_t *) ®s); |
d37eb719 DJ |
290 | } |
291 | ||
292 | if (regno == -1 || is_fp) | |
293 | { | |
294 | mips64_elf_fpregset_t fp_regs; | |
295 | ||
296 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
297 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
298 | { | |
299 | if (errno == EIO) | |
300 | { | |
301 | have_ptrace_regsets = 0; | |
302 | return; | |
303 | } | |
304 | perror_with_name (_("Couldn't get FP registers")); | |
305 | } | |
306 | ||
56be3814 | 307 | mips64_supply_fpregset (regcache, |
28f5035f | 308 | (const mips64_elf_fpregset_t *) &fp_regs); |
d37eb719 | 309 | } |
1faeff08 MR |
310 | |
311 | if (is_dsp) | |
f6ac5f3d | 312 | linux_nat_trad_target::fetch_registers (regcache, regno); |
1faeff08 MR |
313 | else if (regno == -1 && have_dsp) |
314 | { | |
315 | for (regi = mips_regnum (gdbarch)->dspacc; | |
316 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
317 | regi++) | |
f6ac5f3d PA |
318 | linux_nat_trad_target::fetch_registers (regcache, regi); |
319 | linux_nat_trad_target::fetch_registers (regcache, | |
320 | mips_regnum (gdbarch)->dspctl); | |
1faeff08 | 321 | } |
d37eb719 DJ |
322 | } |
323 | ||
324 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
325 | using PTRACE_SETREGS et al. */ | |
326 | ||
f6ac5f3d PA |
327 | void |
328 | mips_linux_nat_target::mips64_regsets_store_registers | |
329 | (struct regcache *regcache, int regno) | |
d37eb719 | 330 | { |
ac7936df | 331 | struct gdbarch *gdbarch = regcache->arch (); |
1faeff08 MR |
332 | int is_fp, is_dsp; |
333 | int have_dsp; | |
334 | int regi; | |
d37eb719 DJ |
335 | int tid; |
336 | ||
2eb4d78b UW |
337 | if (regno >= mips_regnum (gdbarch)->fp0 |
338 | && regno <= mips_regnum (gdbarch)->fp0 + 32) | |
d37eb719 | 339 | is_fp = 1; |
2eb4d78b | 340 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
d37eb719 | 341 | is_fp = 1; |
2eb4d78b | 342 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 DJ |
343 | is_fp = 1; |
344 | else | |
345 | is_fp = 0; | |
346 | ||
1faeff08 MR |
347 | /* DSP registers are optional and not a part of any set. */ |
348 | have_dsp = mips_regnum (gdbarch)->dspctl != -1; | |
349 | if (!have_dsp) | |
350 | is_dsp = 0; | |
6ce4c112 | 351 | else if (regno >= mips_regnum (gdbarch)->dspacc |
1faeff08 MR |
352 | && regno < mips_regnum (gdbarch)->dspacc + 6) |
353 | is_dsp = 1; | |
354 | else if (regno == mips_regnum (gdbarch)->dspctl) | |
355 | is_dsp = 1; | |
356 | else | |
357 | is_dsp = 0; | |
358 | ||
222312d3 | 359 | tid = get_ptrace_pid (regcache->ptid ()); |
d37eb719 | 360 | |
1faeff08 | 361 | if (regno == -1 || (!is_fp && !is_dsp)) |
d37eb719 DJ |
362 | { |
363 | mips64_elf_gregset_t regs; | |
364 | ||
365 | if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
366 | perror_with_name (_("Couldn't get registers")); | |
367 | ||
56be3814 | 368 | mips64_fill_gregset (regcache, ®s, regno); |
d37eb719 DJ |
369 | |
370 | if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) ®s) == -1) | |
371 | perror_with_name (_("Couldn't set registers")); | |
372 | } | |
373 | ||
374 | if (regno == -1 || is_fp) | |
375 | { | |
376 | mips64_elf_fpregset_t fp_regs; | |
377 | ||
378 | if (ptrace (PTRACE_GETFPREGS, tid, 0L, | |
379 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
380 | perror_with_name (_("Couldn't get FP registers")); | |
381 | ||
56be3814 | 382 | mips64_fill_fpregset (regcache, &fp_regs, regno); |
d37eb719 DJ |
383 | |
384 | if (ptrace (PTRACE_SETFPREGS, tid, 0L, | |
385 | (PTRACE_TYPE_ARG3) &fp_regs) == -1) | |
386 | perror_with_name (_("Couldn't set FP registers")); | |
387 | } | |
1faeff08 MR |
388 | |
389 | if (is_dsp) | |
f6ac5f3d | 390 | linux_nat_trad_target::store_registers (regcache, regno); |
1faeff08 MR |
391 | else if (regno == -1 && have_dsp) |
392 | { | |
393 | for (regi = mips_regnum (gdbarch)->dspacc; | |
394 | regi < mips_regnum (gdbarch)->dspacc + 6; | |
395 | regi++) | |
f6ac5f3d PA |
396 | linux_nat_trad_target::store_registers (regcache, regi); |
397 | linux_nat_trad_target::store_registers (regcache, | |
398 | mips_regnum (gdbarch)->dspctl); | |
1faeff08 | 399 | } |
d37eb719 DJ |
400 | } |
401 | ||
402 | /* Fetch REGNO (or all registers if REGNO == -1) from the target | |
403 | using any working method. */ | |
404 | ||
f6ac5f3d PA |
405 | void |
406 | mips_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) | |
d37eb719 DJ |
407 | { |
408 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
409 | if (have_ptrace_regsets) | |
f6ac5f3d | 410 | mips64_regsets_fetch_registers (regcache, regnum); |
d37eb719 DJ |
411 | |
412 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
413 | back to PTRACE_PEEKUSER. */ | |
414 | if (!have_ptrace_regsets) | |
4e6ff0e1 MR |
415 | { |
416 | linux_nat_trad_target::fetch_registers (regcache, regnum); | |
417 | ||
418 | /* Fill the inaccessible zero register with zero. */ | |
419 | if (regnum == MIPS_ZERO_REGNUM || regnum == -1) | |
420 | regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); | |
421 | } | |
d37eb719 DJ |
422 | } |
423 | ||
424 | /* Store REGNO (or all registers if REGNO == -1) to the target | |
425 | using any working method. */ | |
426 | ||
f6ac5f3d PA |
427 | void |
428 | mips_linux_nat_target::store_registers (struct regcache *regcache, int regnum) | |
d37eb719 DJ |
429 | { |
430 | /* Unless we already know that PTRACE_GETREGS does not work, try it. */ | |
431 | if (have_ptrace_regsets) | |
f6ac5f3d | 432 | mips64_regsets_store_registers (regcache, regnum); |
d37eb719 DJ |
433 | |
434 | /* If we know, or just found out, that PTRACE_GETREGS does not work, fall | |
435 | back to PTRACE_PEEKUSER. */ | |
436 | if (!have_ptrace_regsets) | |
f6ac5f3d | 437 | linux_nat_trad_target::store_registers (regcache, regnum); |
d37eb719 DJ |
438 | } |
439 | ||
910122bf UW |
440 | /* Return the address in the core dump or inferior of register |
441 | REGNO. */ | |
442 | ||
f6ac5f3d PA |
443 | CORE_ADDR |
444 | mips_linux_nat_target::register_u_offset (struct gdbarch *gdbarch, | |
445 | int regno, int store_p) | |
910122bf | 446 | { |
7714d83a UW |
447 | if (mips_abi_regsize (gdbarch) == 8) |
448 | return mips64_linux_register_addr (gdbarch, regno, store_p); | |
dda0c97e | 449 | else |
7714d83a | 450 | return mips_linux_register_addr (gdbarch, regno, store_p); |
910122bf UW |
451 | } |
452 | ||
f6ac5f3d PA |
453 | const struct target_desc * |
454 | mips_linux_nat_target::read_description () | |
822b6570 | 455 | { |
1faeff08 MR |
456 | static int have_dsp = -1; |
457 | ||
458 | if (have_dsp < 0) | |
459 | { | |
a4a688ff JB |
460 | /* Assume no DSP if there is no inferior to inspect with ptrace. */ |
461 | if (inferior_ptid == null_ptid) | |
462 | return _MIPS_SIM == _ABIO32 ? tdesc_mips_linux : tdesc_mips64_linux; | |
463 | ||
2d389915 | 464 | int tid = get_ptrace_pid (inferior_ptid); |
1faeff08 | 465 | |
ac740bc7 | 466 | errno = 0; |
1faeff08 MR |
467 | ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0); |
468 | switch (errno) | |
469 | { | |
470 | case 0: | |
471 | have_dsp = 1; | |
472 | break; | |
473 | case EIO: | |
474 | have_dsp = 0; | |
475 | break; | |
476 | default: | |
837a1b32 | 477 | perror_with_name (_("Couldn't check DSP support")); |
1faeff08 MR |
478 | break; |
479 | } | |
480 | } | |
481 | ||
81adfced DJ |
482 | /* Report that target registers are a size we know for sure |
483 | that we can get from ptrace. */ | |
484 | if (_MIPS_SIM == _ABIO32) | |
1faeff08 | 485 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; |
81adfced | 486 | else |
1faeff08 | 487 | return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux; |
822b6570 DJ |
488 | } |
489 | ||
b9412953 DD |
490 | /* -1 if the kernel and/or CPU do not support watch registers. |
491 | 1 if watch_readback is valid and we can read style, num_valid | |
492 | and the masks. | |
493 | 0 if we need to read the watch_readback. */ | |
494 | ||
495 | static int watch_readback_valid; | |
496 | ||
497 | /* Cached watch register read values. */ | |
498 | ||
499 | static struct pt_watch_regs watch_readback; | |
500 | ||
b9412953 DD |
501 | static struct mips_watchpoint *current_watches; |
502 | ||
503 | /* The current set of watch register values for writing the | |
504 | registers. */ | |
505 | ||
506 | static struct pt_watch_regs watch_mirror; | |
507 | ||
b9412953 DD |
508 | static void |
509 | mips_show_dr (const char *func, CORE_ADDR addr, | |
510 | int len, enum target_hw_bp_type type) | |
511 | { | |
512 | int i; | |
513 | ||
0426ad51 | 514 | gdb_puts (func, gdb_stdlog); |
b9412953 | 515 | if (addr || len) |
6cb06a8c TT |
516 | gdb_printf (gdb_stdlog, |
517 | " (addr=%s, len=%d, type=%s)", | |
99d9c3b9 | 518 | paddress (current_inferior ()->arch (), addr), len, |
6cb06a8c TT |
519 | type == hw_write ? "data-write" |
520 | : (type == hw_read ? "data-read" | |
521 | : (type == hw_access ? "data-read/write" | |
522 | : (type == hw_execute ? "instruction-execute" | |
523 | : "??unknown??")))); | |
0426ad51 | 524 | gdb_puts (":\n", gdb_stdlog); |
b9412953 DD |
525 | |
526 | for (i = 0; i < MAX_DEBUG_REGISTER; i++) | |
6cb06a8c | 527 | gdb_printf (gdb_stdlog, "\tDR%d: lo=%s, hi=%s\n", i, |
99d9c3b9 | 528 | paddress (current_inferior ()->arch (), |
6cb06a8c TT |
529 | mips_linux_watch_get_watchlo (&watch_mirror, |
530 | i)), | |
99d9c3b9 | 531 | paddress (current_inferior ()->arch (), |
6cb06a8c TT |
532 | mips_linux_watch_get_watchhi (&watch_mirror, |
533 | i))); | |
b9412953 DD |
534 | } |
535 | ||
b9412953 DD |
536 | /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can |
537 | handle the specified watch type. */ | |
538 | ||
f6ac5f3d PA |
539 | int |
540 | mips_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
541 | int cnt, int ot) | |
b9412953 DD |
542 | { |
543 | int i; | |
544 | uint32_t wanted_mask, irw_mask; | |
545 | ||
e38504b3 | 546 | if (!mips_linux_read_watch_registers (inferior_ptid.lwp (), |
b3436450 YQ |
547 | &watch_readback, |
548 | &watch_readback_valid, 0)) | |
b9412953 DD |
549 | return 0; |
550 | ||
551 | switch (type) | |
552 | { | |
553 | case bp_hardware_watchpoint: | |
554 | wanted_mask = W_MASK; | |
555 | break; | |
556 | case bp_read_watchpoint: | |
557 | wanted_mask = R_MASK; | |
558 | break; | |
559 | case bp_access_watchpoint: | |
560 | wanted_mask = R_MASK | W_MASK; | |
561 | break; | |
562 | default: | |
563 | return 0; | |
564 | } | |
565 | ||
b3436450 YQ |
566 | for (i = 0; |
567 | i < mips_linux_watch_get_num_valid (&watch_readback) && cnt; | |
568 | i++) | |
b9412953 | 569 | { |
b3436450 | 570 | irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i); |
b9412953 DD |
571 | if ((irw_mask & wanted_mask) == wanted_mask) |
572 | cnt--; | |
573 | } | |
574 | return (cnt == 0) ? 1 : 0; | |
575 | } | |
576 | ||
577 | /* Target to_stopped_by_watchpoint implementation. Return 1 if | |
578 | stopped by watchpoint. The watchhi R and W bits indicate the watch | |
025bb325 | 579 | register triggered. */ |
b9412953 | 580 | |
57810aa7 | 581 | bool |
f6ac5f3d | 582 | mips_linux_nat_target::stopped_by_watchpoint () |
b9412953 DD |
583 | { |
584 | int n; | |
585 | int num_valid; | |
586 | ||
e38504b3 | 587 | if (!mips_linux_read_watch_registers (inferior_ptid.lwp (), |
b3436450 YQ |
588 | &watch_readback, |
589 | &watch_readback_valid, 1)) | |
57810aa7 | 590 | return false; |
b9412953 | 591 | |
b3436450 | 592 | num_valid = mips_linux_watch_get_num_valid (&watch_readback); |
b9412953 DD |
593 | |
594 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
b3436450 | 595 | if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK)) |
57810aa7 | 596 | return true; |
b9412953 | 597 | |
57810aa7 | 598 | return false; |
b9412953 DD |
599 | } |
600 | ||
601 | /* Target to_stopped_data_address implementation. Set the address | |
602 | where the watch triggered (if known). Return 1 if the address was | |
603 | known. */ | |
604 | ||
57810aa7 | 605 | bool |
f6ac5f3d | 606 | mips_linux_nat_target::stopped_data_address (CORE_ADDR *paddr) |
b9412953 DD |
607 | { |
608 | /* On mips we don't know the low order 3 bits of the data address, | |
609 | so we must return false. */ | |
57810aa7 | 610 | return false; |
b9412953 DD |
611 | } |
612 | ||
b9412953 DD |
613 | /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if |
614 | the specified region can be covered by the watch registers. */ | |
615 | ||
f6ac5f3d PA |
616 | int |
617 | mips_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
b9412953 DD |
618 | { |
619 | struct pt_watch_regs dummy_regs; | |
620 | int i; | |
621 | ||
e38504b3 | 622 | if (!mips_linux_read_watch_registers (inferior_ptid.lwp (), |
b3436450 YQ |
623 | &watch_readback, |
624 | &watch_readback_valid, 0)) | |
b9412953 DD |
625 | return 0; |
626 | ||
627 | dummy_regs = watch_readback; | |
628 | /* Clear them out. */ | |
b3436450 YQ |
629 | for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++) |
630 | mips_linux_watch_set_watchlo (&dummy_regs, i, 0); | |
631 | return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0); | |
b9412953 DD |
632 | } |
633 | ||
b9412953 DD |
634 | /* Write the mirrored watch register values for each thread. */ |
635 | ||
636 | static int | |
637 | write_watchpoint_regs (void) | |
638 | { | |
901b9821 | 639 | for (const lwp_info *lp : all_lwps ()) |
b9412953 | 640 | { |
901b9821 | 641 | int tid = lp->ptid.lwp (); |
aa58a496 | 642 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) |
b9412953 DD |
643 | perror_with_name (_("Couldn't write debug register")); |
644 | } | |
645 | return 0; | |
646 | } | |
647 | ||
135340af PA |
648 | /* linux_nat_target::low_new_thread implementation. Write the |
649 | mirrored watch register values for the new thread. */ | |
b9412953 | 650 | |
135340af PA |
651 | void |
652 | mips_linux_nat_target::low_new_thread (struct lwp_info *lp) | |
b9412953 | 653 | { |
339053c2 | 654 | long tid = lp->ptid.lwp (); |
b9412953 | 655 | |
7974a605 | 656 | if (!mips_linux_read_watch_registers (tid, |
b3436450 YQ |
657 | &watch_readback, |
658 | &watch_readback_valid, 0)) | |
b9412953 DD |
659 | return; |
660 | ||
aa58a496 | 661 | if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1) |
b9412953 DD |
662 | perror_with_name (_("Couldn't write debug register")); |
663 | } | |
664 | ||
b9412953 DD |
665 | /* Target to_insert_watchpoint implementation. Try to insert a new |
666 | watch. Return zero on success. */ | |
667 | ||
f6ac5f3d PA |
668 | int |
669 | mips_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
670 | enum target_hw_bp_type type, | |
671 | struct expression *cond) | |
b9412953 DD |
672 | { |
673 | struct pt_watch_regs regs; | |
674 | struct mips_watchpoint *new_watch; | |
675 | struct mips_watchpoint **pw; | |
676 | ||
b9412953 DD |
677 | int retval; |
678 | ||
e38504b3 | 679 | if (!mips_linux_read_watch_registers (inferior_ptid.lwp (), |
b3436450 YQ |
680 | &watch_readback, |
681 | &watch_readback_valid, 0)) | |
b9412953 DD |
682 | return -1; |
683 | ||
684 | if (len <= 0) | |
685 | return -1; | |
686 | ||
687 | regs = watch_readback; | |
688 | /* Add the current watches. */ | |
b3436450 | 689 | mips_linux_watch_populate_regs (current_watches, ®s); |
b9412953 DD |
690 | |
691 | /* Now try to add the new watch. */ | |
b3436450 YQ |
692 | if (!mips_linux_watch_try_one_watch (®s, addr, len, |
693 | mips_linux_watch_type_to_irw (type))) | |
b9412953 DD |
694 | return -1; |
695 | ||
696 | /* It fit. Stick it on the end of the list. */ | |
8d749320 | 697 | new_watch = XNEW (struct mips_watchpoint); |
b9412953 DD |
698 | new_watch->addr = addr; |
699 | new_watch->len = len; | |
700 | new_watch->type = type; | |
701 | new_watch->next = NULL; | |
702 | ||
703 | pw = ¤t_watches; | |
704 | while (*pw != NULL) | |
705 | pw = &(*pw)->next; | |
706 | *pw = new_watch; | |
707 | ||
708 | watch_mirror = regs; | |
709 | retval = write_watchpoint_regs (); | |
710 | ||
c5e92cca | 711 | if (show_debug_regs) |
b9412953 DD |
712 | mips_show_dr ("insert_watchpoint", addr, len, type); |
713 | ||
714 | return retval; | |
715 | } | |
716 | ||
717 | /* Target to_remove_watchpoint implementation. Try to remove a watch. | |
718 | Return zero on success. */ | |
719 | ||
f6ac5f3d PA |
720 | int |
721 | mips_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
722 | enum target_hw_bp_type type, | |
723 | struct expression *cond) | |
b9412953 DD |
724 | { |
725 | int retval; | |
726 | int deleted_one; | |
727 | ||
728 | struct mips_watchpoint **pw; | |
729 | struct mips_watchpoint *w; | |
730 | ||
731 | /* Search for a known watch that matches. Then unlink and free | |
732 | it. */ | |
733 | deleted_one = 0; | |
734 | pw = ¤t_watches; | |
735 | while ((w = *pw)) | |
736 | { | |
737 | if (w->addr == addr && w->len == len && w->type == type) | |
738 | { | |
739 | *pw = w->next; | |
740 | xfree (w); | |
741 | deleted_one = 1; | |
742 | break; | |
743 | } | |
744 | pw = &(w->next); | |
745 | } | |
746 | ||
747 | if (!deleted_one) | |
748 | return -1; /* We don't know about it, fail doing nothing. */ | |
749 | ||
750 | /* At this point watch_readback is known to be valid because we | |
751 | could not have added the watch without reading it. */ | |
752 | gdb_assert (watch_readback_valid == 1); | |
753 | ||
754 | watch_mirror = watch_readback; | |
b3436450 | 755 | mips_linux_watch_populate_regs (current_watches, &watch_mirror); |
b9412953 DD |
756 | |
757 | retval = write_watchpoint_regs (); | |
758 | ||
c5e92cca | 759 | if (show_debug_regs) |
b9412953 DD |
760 | mips_show_dr ("remove_watchpoint", addr, len, type); |
761 | ||
762 | return retval; | |
763 | } | |
764 | ||
765 | /* Target to_close implementation. Free any watches and call the | |
766 | super implementation. */ | |
767 | ||
f6ac5f3d PA |
768 | void |
769 | mips_linux_nat_target::close () | |
b9412953 DD |
770 | { |
771 | struct mips_watchpoint *w; | |
772 | struct mips_watchpoint *nw; | |
773 | ||
774 | /* Clean out the current_watches list. */ | |
775 | w = current_watches; | |
776 | while (w) | |
777 | { | |
778 | nw = w->next; | |
779 | xfree (w); | |
780 | w = nw; | |
781 | } | |
782 | current_watches = NULL; | |
783 | ||
f6ac5f3d | 784 | linux_nat_trad_target::close (); |
b9412953 DD |
785 | } |
786 | ||
6c265988 | 787 | void _initialize_mips_linux_nat (); |
10d6c8cd | 788 | void |
6c265988 | 789 | _initialize_mips_linux_nat () |
10d6c8cd | 790 | { |
cbe54154 | 791 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, |
c5e92cca | 792 | &show_debug_regs, _("\ |
cbe54154 PA |
793 | Set whether to show variables that mirror the mips debug registers."), _("\ |
794 | Show whether to show variables that mirror the mips debug registers."), _("\ | |
b9412953 DD |
795 | Use \"on\" to enable, \"off\" to disable.\n\ |
796 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
797 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
798 | triggers a breakpoint or watchpoint."), | |
cbe54154 PA |
799 | NULL, |
800 | NULL, | |
801 | &maintenance_set_cmdlist, | |
802 | &maintenance_show_cmdlist); | |
b9412953 | 803 | |
f6ac5f3d | 804 | linux_target = &the_mips_linux_nat_target; |
d9f719f1 | 805 | add_inf_child_target (&the_mips_linux_nat_target); |
10d6c8cd | 806 | } |