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75c9abc6 1/* Native-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
e2882c85 3 Copyright (C) 2001-2018 Free Software Foundation, Inc.
2aa830e4
DJ
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
2aa830e4
DJ
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
2aa830e4
DJ
19
20#include "defs.h"
b9412953
DD
21#include "command.h"
22#include "gdbcmd.h"
d37eb719 23#include "inferior.h"
6b753f60 24#include "mips-tdep.h"
10d6c8cd 25#include "target.h"
28f5035f 26#include "regcache.h"
6798487f 27#include "linux-nat-trad.h"
d37eb719 28#include "mips-linux-tdep.h"
822b6570 29#include "target-descriptions.h"
2aa830e4 30
dc60ece8 31#include "gdb_proc_service.h"
3e00823e 32#include "gregset.h"
dc60ece8 33
822b6570 34#include <sgidefs.h>
5826e159 35#include "nat/gdb_ptrace.h"
9be14b81 36#include <asm/ptrace.h>
bcc0c096 37#include "inf-ptrace.h"
d37eb719 38
125f8a3d 39#include "nat/mips-linux-watch.h"
aaee2056 40
dc60ece8
DJ
41#ifndef PTRACE_GET_THREAD_AREA
42#define PTRACE_GET_THREAD_AREA 25
43#endif
44
f6ac5f3d
PA
45class mips_linux_nat_target final : public linux_nat_trad_target
46{
47public:
48 /* Add our register access methods. */
49 void fetch_registers (struct regcache *, int) override;
50 void store_registers (struct regcache *, int) override;
51
52 void close () override;
53
54 int can_use_hw_breakpoint (enum bptype, int, int) override;
55
56 int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
57 struct expression *) override;
58
59 int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
60 struct expression *) override;
61
57810aa7 62 bool stopped_by_watchpoint () override;
f6ac5f3d 63
57810aa7 64 bool stopped_data_address (CORE_ADDR *) override;
d37eb719 65
f6ac5f3d 66 int region_ok_for_hw_watchpoint (CORE_ADDR, int) override;
d37eb719 67
f6ac5f3d 68 const struct target_desc *read_description () override;
b9412953 69
f6ac5f3d
PA
70protected:
71 /* Override linux_nat_trad_target methods. */
72 CORE_ADDR register_u_offset (struct gdbarch *gdbarch,
73 int regno, int store_p) override;
74
135340af
PA
75 /* Override linux_nat_target low methods. */
76 void low_new_thread (struct lwp_info *lp) override;
77
f6ac5f3d
PA
78private:
79 /* Helpers. See definitions. */
80 void mips64_regsets_store_registers (struct regcache *regcache,
81 int regno);
82 void mips64_regsets_fetch_registers (struct regcache *regcache,
83 int regno);
84};
85
86static mips_linux_nat_target the_mips_linux_nat_target;
87
88/* Assume that we have PTRACE_GETREGS et al. support. If we do not,
89 we'll clear this and use PTRACE_PEEKUSER instead. */
90static int have_ptrace_regsets = 1;
d37eb719 91
dda0c97e 92/* Map gdb internal register number to ptrace ``address''.
7714d83a
UW
93 These ``addresses'' are normally defined in <asm/ptrace.h>.
94
95 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
96 and there's no point in reading or setting MIPS_ZERO_REGNUM.
97 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
dda0c97e
UW
98
99static CORE_ADDR
7714d83a 100mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
dda0c97e 101{
7714d83a 102 CORE_ADDR regaddr;
dda0c97e 103
2eb4d78b 104 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
dda0c97e
UW
105 error (_("Bogon register number %d."), regno);
106
7714d83a 107 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
dda0c97e 108 regaddr = regno;
7714d83a
UW
109 else if ((regno >= mips_regnum (gdbarch)->fp0)
110 && (regno < mips_regnum (gdbarch)->fp0 + 32))
111 regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
112 else if (regno == mips_regnum (gdbarch)->pc)
dda0c97e 113 regaddr = PC;
7714d83a
UW
114 else if (regno == mips_regnum (gdbarch)->cause)
115 regaddr = store? (CORE_ADDR) -1 : CAUSE;
116 else if (regno == mips_regnum (gdbarch)->badvaddr)
117 regaddr = store? (CORE_ADDR) -1 : BADVADDR;
118 else if (regno == mips_regnum (gdbarch)->lo)
dda0c97e 119 regaddr = MMLO;
7714d83a 120 else if (regno == mips_regnum (gdbarch)->hi)
dda0c97e 121 regaddr = MMHI;
7714d83a 122 else if (regno == mips_regnum (gdbarch)->fp_control_status)
dda0c97e 123 regaddr = FPC_CSR;
7714d83a
UW
124 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
125 regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
1faeff08
MR
126 else if (mips_regnum (gdbarch)->dspacc != -1
127 && regno >= mips_regnum (gdbarch)->dspacc
128 && regno < mips_regnum (gdbarch)->dspacc + 6)
129 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
130 else if (regno == mips_regnum (gdbarch)->dspctl)
131 regaddr = DSP_CONTROL;
822b6570
DJ
132 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
133 regaddr = 0;
dda0c97e 134 else
7714d83a 135 regaddr = (CORE_ADDR) -1;
dda0c97e
UW
136
137 return regaddr;
138}
139
140static CORE_ADDR
7714d83a 141mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
dda0c97e 142{
7714d83a 143 CORE_ADDR regaddr;
dda0c97e 144
2eb4d78b 145 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
dda0c97e
UW
146 error (_("Bogon register number %d."), regno);
147
75d74cca
MR
148 /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR
149 or PTRACE_POKEUSR. */
150 if (register_size (gdbarch, regno) > sizeof (PTRACE_TYPE_RET))
151 return (CORE_ADDR) -1;
152
7714d83a 153 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
dda0c97e 154 regaddr = regno;
7714d83a
UW
155 else if ((regno >= mips_regnum (gdbarch)->fp0)
156 && (regno < mips_regnum (gdbarch)->fp0 + 32))
2eb4d78b 157 regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
7714d83a 158 else if (regno == mips_regnum (gdbarch)->pc)
dda0c97e 159 regaddr = MIPS64_PC;
7714d83a
UW
160 else if (regno == mips_regnum (gdbarch)->cause)
161 regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
162 else if (regno == mips_regnum (gdbarch)->badvaddr)
163 regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
164 else if (regno == mips_regnum (gdbarch)->lo)
dda0c97e 165 regaddr = MIPS64_MMLO;
7714d83a 166 else if (regno == mips_regnum (gdbarch)->hi)
dda0c97e 167 regaddr = MIPS64_MMHI;
7714d83a 168 else if (regno == mips_regnum (gdbarch)->fp_control_status)
dda0c97e 169 regaddr = MIPS64_FPC_CSR;
7714d83a
UW
170 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
171 regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
1faeff08
MR
172 else if (mips_regnum (gdbarch)->dspacc != -1
173 && regno >= mips_regnum (gdbarch)->dspacc
174 && regno < mips_regnum (gdbarch)->dspacc + 6)
175 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
176 else if (regno == mips_regnum (gdbarch)->dspctl)
177 regaddr = DSP_CONTROL;
822b6570
DJ
178 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
179 regaddr = 0;
dda0c97e 180 else
7714d83a 181 regaddr = (CORE_ADDR) -1;
dda0c97e
UW
182
183 return regaddr;
184}
185
dc60ece8
DJ
186/* Fetch the thread-local storage pointer for libthread_db. */
187
188ps_err_e
754653a7 189ps_get_thread_area (struct ps_prochandle *ph,
dc60ece8
DJ
190 lwpid_t lwpid, int idx, void **base)
191{
192 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
193 return PS_ERR;
194
195 /* IDX is the bias from the thread pointer to the beginning of the
196 thread descriptor. It has to be subtracted due to implementation
197 quirks in libthread_db. */
198 *base = (void *) ((char *)*base - idx);
199
200 return PS_OK;
201}
202
3e00823e
UW
203/* Wrapper functions. These are only used by libthread_db. */
204
205void
7f7fe91e 206supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
3e00823e 207{
ac7936df 208 if (mips_isa_regsize (regcache->arch ()) == 4)
7f7fe91e 209 mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
3e00823e 210 else
7f7fe91e 211 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp);
3e00823e
UW
212}
213
214void
7f7fe91e
UW
215fill_gregset (const struct regcache *regcache,
216 gdb_gregset_t *gregsetp, int regno)
3e00823e 217{
ac7936df 218 if (mips_isa_regsize (regcache->arch ()) == 4)
7f7fe91e 219 mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
3e00823e 220 else
7f7fe91e 221 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno);
3e00823e
UW
222}
223
224void
7f7fe91e 225supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
3e00823e 226{
d8dab6c3 227 mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *) fpregsetp);
3e00823e
UW
228}
229
230void
7f7fe91e
UW
231fill_fpregset (const struct regcache *regcache,
232 gdb_fpregset_t *fpregsetp, int regno)
3e00823e 233{
d8dab6c3 234 mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *) fpregsetp, regno);
3e00823e
UW
235}
236
237
d37eb719
DJ
238/* Fetch REGNO (or all registers if REGNO == -1) from the target
239 using PTRACE_GETREGS et al. */
240
f6ac5f3d
PA
241void
242mips_linux_nat_target::mips64_regsets_fetch_registers
243 (struct regcache *regcache, int regno)
d37eb719 244{
ac7936df 245 struct gdbarch *gdbarch = regcache->arch ();
1faeff08
MR
246 int is_fp, is_dsp;
247 int have_dsp;
248 int regi;
d37eb719
DJ
249 int tid;
250
2eb4d78b
UW
251 if (regno >= mips_regnum (gdbarch)->fp0
252 && regno <= mips_regnum (gdbarch)->fp0 + 32)
d37eb719 253 is_fp = 1;
2eb4d78b 254 else if (regno == mips_regnum (gdbarch)->fp_control_status)
d37eb719 255 is_fp = 1;
2eb4d78b 256 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719
DJ
257 is_fp = 1;
258 else
259 is_fp = 0;
260
1faeff08
MR
261 /* DSP registers are optional and not a part of any set. */
262 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
263 if (!have_dsp)
264 is_dsp = 0;
265 else if (regno >= mips_regnum (gdbarch)->dspacc
266 && regno < mips_regnum (gdbarch)->dspacc + 6)
267 is_dsp = 1;
268 else if (regno == mips_regnum (gdbarch)->dspctl)
269 is_dsp = 1;
270 else
271 is_dsp = 0;
272
222312d3 273 tid = get_ptrace_pid (regcache->ptid ());
d37eb719 274
1faeff08 275 if (regno == -1 || (!is_fp && !is_dsp))
d37eb719
DJ
276 {
277 mips64_elf_gregset_t regs;
278
279 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
280 {
281 if (errno == EIO)
282 {
283 have_ptrace_regsets = 0;
284 return;
285 }
286 perror_with_name (_("Couldn't get registers"));
287 }
288
56be3814 289 mips64_supply_gregset (regcache,
28f5035f 290 (const mips64_elf_gregset_t *) &regs);
d37eb719
DJ
291 }
292
293 if (regno == -1 || is_fp)
294 {
295 mips64_elf_fpregset_t fp_regs;
296
297 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
298 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
299 {
300 if (errno == EIO)
301 {
302 have_ptrace_regsets = 0;
303 return;
304 }
305 perror_with_name (_("Couldn't get FP registers"));
306 }
307
56be3814 308 mips64_supply_fpregset (regcache,
28f5035f 309 (const mips64_elf_fpregset_t *) &fp_regs);
d37eb719 310 }
1faeff08
MR
311
312 if (is_dsp)
f6ac5f3d 313 linux_nat_trad_target::fetch_registers (regcache, regno);
1faeff08
MR
314 else if (regno == -1 && have_dsp)
315 {
316 for (regi = mips_regnum (gdbarch)->dspacc;
317 regi < mips_regnum (gdbarch)->dspacc + 6;
318 regi++)
f6ac5f3d
PA
319 linux_nat_trad_target::fetch_registers (regcache, regi);
320 linux_nat_trad_target::fetch_registers (regcache,
321 mips_regnum (gdbarch)->dspctl);
1faeff08 322 }
d37eb719
DJ
323}
324
325/* Store REGNO (or all registers if REGNO == -1) to the target
326 using PTRACE_SETREGS et al. */
327
f6ac5f3d
PA
328void
329mips_linux_nat_target::mips64_regsets_store_registers
330 (struct regcache *regcache, int regno)
d37eb719 331{
ac7936df 332 struct gdbarch *gdbarch = regcache->arch ();
1faeff08
MR
333 int is_fp, is_dsp;
334 int have_dsp;
335 int regi;
d37eb719
DJ
336 int tid;
337
2eb4d78b
UW
338 if (regno >= mips_regnum (gdbarch)->fp0
339 && regno <= mips_regnum (gdbarch)->fp0 + 32)
d37eb719 340 is_fp = 1;
2eb4d78b 341 else if (regno == mips_regnum (gdbarch)->fp_control_status)
d37eb719 342 is_fp = 1;
2eb4d78b 343 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
d37eb719
DJ
344 is_fp = 1;
345 else
346 is_fp = 0;
347
1faeff08
MR
348 /* DSP registers are optional and not a part of any set. */
349 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
350 if (!have_dsp)
351 is_dsp = 0;
6ce4c112 352 else if (regno >= mips_regnum (gdbarch)->dspacc
1faeff08
MR
353 && regno < mips_regnum (gdbarch)->dspacc + 6)
354 is_dsp = 1;
355 else if (regno == mips_regnum (gdbarch)->dspctl)
356 is_dsp = 1;
357 else
358 is_dsp = 0;
359
222312d3 360 tid = get_ptrace_pid (regcache->ptid ());
d37eb719 361
1faeff08 362 if (regno == -1 || (!is_fp && !is_dsp))
d37eb719
DJ
363 {
364 mips64_elf_gregset_t regs;
365
366 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
367 perror_with_name (_("Couldn't get registers"));
368
56be3814 369 mips64_fill_gregset (regcache, &regs, regno);
d37eb719
DJ
370
371 if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
372 perror_with_name (_("Couldn't set registers"));
373 }
374
375 if (regno == -1 || is_fp)
376 {
377 mips64_elf_fpregset_t fp_regs;
378
379 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
380 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
381 perror_with_name (_("Couldn't get FP registers"));
382
56be3814 383 mips64_fill_fpregset (regcache, &fp_regs, regno);
d37eb719
DJ
384
385 if (ptrace (PTRACE_SETFPREGS, tid, 0L,
386 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
387 perror_with_name (_("Couldn't set FP registers"));
388 }
1faeff08
MR
389
390 if (is_dsp)
f6ac5f3d 391 linux_nat_trad_target::store_registers (regcache, regno);
1faeff08
MR
392 else if (regno == -1 && have_dsp)
393 {
394 for (regi = mips_regnum (gdbarch)->dspacc;
395 regi < mips_regnum (gdbarch)->dspacc + 6;
396 regi++)
f6ac5f3d
PA
397 linux_nat_trad_target::store_registers (regcache, regi);
398 linux_nat_trad_target::store_registers (regcache,
399 mips_regnum (gdbarch)->dspctl);
1faeff08 400 }
d37eb719
DJ
401}
402
403/* Fetch REGNO (or all registers if REGNO == -1) from the target
404 using any working method. */
405
f6ac5f3d
PA
406void
407mips_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
d37eb719
DJ
408{
409 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
410 if (have_ptrace_regsets)
f6ac5f3d 411 mips64_regsets_fetch_registers (regcache, regnum);
d37eb719
DJ
412
413 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
414 back to PTRACE_PEEKUSER. */
415 if (!have_ptrace_regsets)
4e6ff0e1
MR
416 {
417 linux_nat_trad_target::fetch_registers (regcache, regnum);
418
419 /* Fill the inaccessible zero register with zero. */
420 if (regnum == MIPS_ZERO_REGNUM || regnum == -1)
421 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM);
422 }
d37eb719
DJ
423}
424
425/* Store REGNO (or all registers if REGNO == -1) to the target
426 using any working method. */
427
f6ac5f3d
PA
428void
429mips_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
d37eb719
DJ
430{
431 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
432 if (have_ptrace_regsets)
f6ac5f3d 433 mips64_regsets_store_registers (regcache, regnum);
d37eb719
DJ
434
435 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
436 back to PTRACE_PEEKUSER. */
437 if (!have_ptrace_regsets)
f6ac5f3d 438 linux_nat_trad_target::store_registers (regcache, regnum);
d37eb719
DJ
439}
440
910122bf
UW
441/* Return the address in the core dump or inferior of register
442 REGNO. */
443
f6ac5f3d
PA
444CORE_ADDR
445mips_linux_nat_target::register_u_offset (struct gdbarch *gdbarch,
446 int regno, int store_p)
910122bf 447{
7714d83a
UW
448 if (mips_abi_regsize (gdbarch) == 8)
449 return mips64_linux_register_addr (gdbarch, regno, store_p);
dda0c97e 450 else
7714d83a 451 return mips_linux_register_addr (gdbarch, regno, store_p);
910122bf
UW
452}
453
f6ac5f3d
PA
454const struct target_desc *
455mips_linux_nat_target::read_description ()
822b6570 456{
1faeff08
MR
457 static int have_dsp = -1;
458
459 if (have_dsp < 0)
460 {
461 int tid;
462
463 tid = ptid_get_lwp (inferior_ptid);
464 if (tid == 0)
e99b03dc 465 tid = inferior_ptid.pid ();
1faeff08 466
ac740bc7 467 errno = 0;
1faeff08
MR
468 ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0);
469 switch (errno)
470 {
471 case 0:
472 have_dsp = 1;
473 break;
474 case EIO:
475 have_dsp = 0;
476 break;
477 default:
837a1b32 478 perror_with_name (_("Couldn't check DSP support"));
1faeff08
MR
479 break;
480 }
481 }
482
81adfced
DJ
483 /* Report that target registers are a size we know for sure
484 that we can get from ptrace. */
485 if (_MIPS_SIM == _ABIO32)
1faeff08 486 return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
81adfced 487 else
1faeff08 488 return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
822b6570
DJ
489}
490
b9412953
DD
491/* -1 if the kernel and/or CPU do not support watch registers.
492 1 if watch_readback is valid and we can read style, num_valid
493 and the masks.
494 0 if we need to read the watch_readback. */
495
496static int watch_readback_valid;
497
498/* Cached watch register read values. */
499
500static struct pt_watch_regs watch_readback;
501
b9412953
DD
502static struct mips_watchpoint *current_watches;
503
504/* The current set of watch register values for writing the
505 registers. */
506
507static struct pt_watch_regs watch_mirror;
508
b9412953
DD
509static void
510mips_show_dr (const char *func, CORE_ADDR addr,
511 int len, enum target_hw_bp_type type)
512{
513 int i;
514
515 puts_unfiltered (func);
516 if (addr || len)
5af949e3 517 printf_unfiltered (" (addr=%s, len=%d, type=%s)",
f5656ead 518 paddress (target_gdbarch (), addr), len,
b9412953
DD
519 type == hw_write ? "data-write"
520 : (type == hw_read ? "data-read"
521 : (type == hw_access ? "data-read/write"
522 : (type == hw_execute ? "instruction-execute"
523 : "??unknown??"))));
524 puts_unfiltered (":\n");
525
526 for (i = 0; i < MAX_DEBUG_REGISTER; i++)
5af949e3 527 printf_unfiltered ("\tDR%d: lo=%s, hi=%s\n", i,
f5656ead 528 paddress (target_gdbarch (),
b3436450
YQ
529 mips_linux_watch_get_watchlo (&watch_mirror,
530 i)),
f5656ead 531 paddress (target_gdbarch (),
b3436450
YQ
532 mips_linux_watch_get_watchhi (&watch_mirror,
533 i)));
b9412953
DD
534}
535
b9412953
DD
536/* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
537 handle the specified watch type. */
538
f6ac5f3d
PA
539int
540mips_linux_nat_target::can_use_hw_breakpoint (enum bptype type,
541 int cnt, int ot)
b9412953
DD
542{
543 int i;
544 uint32_t wanted_mask, irw_mask;
545
b3436450
YQ
546 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
547 &watch_readback,
548 &watch_readback_valid, 0))
b9412953
DD
549 return 0;
550
551 switch (type)
552 {
553 case bp_hardware_watchpoint:
554 wanted_mask = W_MASK;
555 break;
556 case bp_read_watchpoint:
557 wanted_mask = R_MASK;
558 break;
559 case bp_access_watchpoint:
560 wanted_mask = R_MASK | W_MASK;
561 break;
562 default:
563 return 0;
564 }
565
b3436450
YQ
566 for (i = 0;
567 i < mips_linux_watch_get_num_valid (&watch_readback) && cnt;
568 i++)
b9412953 569 {
b3436450 570 irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i);
b9412953
DD
571 if ((irw_mask & wanted_mask) == wanted_mask)
572 cnt--;
573 }
574 return (cnt == 0) ? 1 : 0;
575}
576
577/* Target to_stopped_by_watchpoint implementation. Return 1 if
578 stopped by watchpoint. The watchhi R and W bits indicate the watch
025bb325 579 register triggered. */
b9412953 580
57810aa7 581bool
f6ac5f3d 582mips_linux_nat_target::stopped_by_watchpoint ()
b9412953
DD
583{
584 int n;
585 int num_valid;
586
b3436450
YQ
587 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
588 &watch_readback,
589 &watch_readback_valid, 1))
57810aa7 590 return false;
b9412953 591
b3436450 592 num_valid = mips_linux_watch_get_num_valid (&watch_readback);
b9412953
DD
593
594 for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
b3436450 595 if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
57810aa7 596 return true;
b9412953 597
57810aa7 598 return false;
b9412953
DD
599}
600
601/* Target to_stopped_data_address implementation. Set the address
602 where the watch triggered (if known). Return 1 if the address was
603 known. */
604
57810aa7 605bool
f6ac5f3d 606mips_linux_nat_target::stopped_data_address (CORE_ADDR *paddr)
b9412953
DD
607{
608 /* On mips we don't know the low order 3 bits of the data address,
609 so we must return false. */
57810aa7 610 return false;
b9412953
DD
611}
612
b9412953
DD
613/* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
614 the specified region can be covered by the watch registers. */
615
f6ac5f3d
PA
616int
617mips_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
b9412953
DD
618{
619 struct pt_watch_regs dummy_regs;
620 int i;
621
b3436450
YQ
622 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
623 &watch_readback,
624 &watch_readback_valid, 0))
b9412953
DD
625 return 0;
626
627 dummy_regs = watch_readback;
628 /* Clear them out. */
b3436450
YQ
629 for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++)
630 mips_linux_watch_set_watchlo (&dummy_regs, i, 0);
631 return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0);
b9412953
DD
632}
633
b9412953
DD
634/* Write the mirrored watch register values for each thread. */
635
636static int
637write_watchpoint_regs (void)
638{
639 struct lwp_info *lp;
b9412953
DD
640 int tid;
641
4c38200f 642 ALL_LWPS (lp)
b9412953 643 {
4c38200f 644 tid = ptid_get_lwp (lp->ptid);
aa58a496 645 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
b9412953
DD
646 perror_with_name (_("Couldn't write debug register"));
647 }
648 return 0;
649}
650
135340af
PA
651/* linux_nat_target::low_new_thread implementation. Write the
652 mirrored watch register values for the new thread. */
b9412953 653
135340af
PA
654void
655mips_linux_nat_target::low_new_thread (struct lwp_info *lp)
b9412953 656{
339053c2 657 long tid = lp->ptid.lwp ();
b9412953 658
7974a605 659 if (!mips_linux_read_watch_registers (tid,
b3436450
YQ
660 &watch_readback,
661 &watch_readback_valid, 0))
b9412953
DD
662 return;
663
aa58a496 664 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
b9412953
DD
665 perror_with_name (_("Couldn't write debug register"));
666}
667
b9412953
DD
668/* Target to_insert_watchpoint implementation. Try to insert a new
669 watch. Return zero on success. */
670
f6ac5f3d
PA
671int
672mips_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
673 enum target_hw_bp_type type,
674 struct expression *cond)
b9412953
DD
675{
676 struct pt_watch_regs regs;
677 struct mips_watchpoint *new_watch;
678 struct mips_watchpoint **pw;
679
680 int i;
681 int retval;
682
b3436450
YQ
683 if (!mips_linux_read_watch_registers (ptid_get_lwp (inferior_ptid),
684 &watch_readback,
685 &watch_readback_valid, 0))
b9412953
DD
686 return -1;
687
688 if (len <= 0)
689 return -1;
690
691 regs = watch_readback;
692 /* Add the current watches. */
b3436450 693 mips_linux_watch_populate_regs (current_watches, &regs);
b9412953
DD
694
695 /* Now try to add the new watch. */
b3436450
YQ
696 if (!mips_linux_watch_try_one_watch (&regs, addr, len,
697 mips_linux_watch_type_to_irw (type)))
b9412953
DD
698 return -1;
699
700 /* It fit. Stick it on the end of the list. */
8d749320 701 new_watch = XNEW (struct mips_watchpoint);
b9412953
DD
702 new_watch->addr = addr;
703 new_watch->len = len;
704 new_watch->type = type;
705 new_watch->next = NULL;
706
707 pw = &current_watches;
708 while (*pw != NULL)
709 pw = &(*pw)->next;
710 *pw = new_watch;
711
712 watch_mirror = regs;
713 retval = write_watchpoint_regs ();
714
c5e92cca 715 if (show_debug_regs)
b9412953
DD
716 mips_show_dr ("insert_watchpoint", addr, len, type);
717
718 return retval;
719}
720
721/* Target to_remove_watchpoint implementation. Try to remove a watch.
722 Return zero on success. */
723
f6ac5f3d
PA
724int
725mips_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
726 enum target_hw_bp_type type,
727 struct expression *cond)
b9412953
DD
728{
729 int retval;
730 int deleted_one;
731
732 struct mips_watchpoint **pw;
733 struct mips_watchpoint *w;
734
735 /* Search for a known watch that matches. Then unlink and free
736 it. */
737 deleted_one = 0;
738 pw = &current_watches;
739 while ((w = *pw))
740 {
741 if (w->addr == addr && w->len == len && w->type == type)
742 {
743 *pw = w->next;
744 xfree (w);
745 deleted_one = 1;
746 break;
747 }
748 pw = &(w->next);
749 }
750
751 if (!deleted_one)
752 return -1; /* We don't know about it, fail doing nothing. */
753
754 /* At this point watch_readback is known to be valid because we
755 could not have added the watch without reading it. */
756 gdb_assert (watch_readback_valid == 1);
757
758 watch_mirror = watch_readback;
b3436450 759 mips_linux_watch_populate_regs (current_watches, &watch_mirror);
b9412953
DD
760
761 retval = write_watchpoint_regs ();
762
c5e92cca 763 if (show_debug_regs)
b9412953
DD
764 mips_show_dr ("remove_watchpoint", addr, len, type);
765
766 return retval;
767}
768
769/* Target to_close implementation. Free any watches and call the
770 super implementation. */
771
f6ac5f3d
PA
772void
773mips_linux_nat_target::close ()
b9412953
DD
774{
775 struct mips_watchpoint *w;
776 struct mips_watchpoint *nw;
777
778 /* Clean out the current_watches list. */
779 w = current_watches;
780 while (w)
781 {
782 nw = w->next;
783 xfree (w);
784 w = nw;
785 }
786 current_watches = NULL;
787
f6ac5f3d 788 linux_nat_trad_target::close ();
b9412953
DD
789}
790
10d6c8cd
DJ
791void
792_initialize_mips_linux_nat (void)
793{
cbe54154 794 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
c5e92cca 795 &show_debug_regs, _("\
cbe54154
PA
796Set whether to show variables that mirror the mips debug registers."), _("\
797Show whether to show variables that mirror the mips debug registers."), _("\
b9412953
DD
798Use \"on\" to enable, \"off\" to disable.\n\
799If enabled, the debug registers values are shown when GDB inserts\n\
800or removes a hardware breakpoint or watchpoint, and when the inferior\n\
801triggers a breakpoint or watchpoint."),
cbe54154
PA
802 NULL,
803 NULL,
804 &maintenance_set_cmdlist,
805 &maintenance_show_cmdlist);
b9412953 806
f6ac5f3d 807 linux_target = &the_mips_linux_nat_target;
d9f719f1 808 add_inf_child_target (&the_mips_linux_nat_target);
10d6c8cd 809}