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[thirdparty/binutils-gdb.git] / gdb / mips-linux-tdep.c
CommitLineData
75c9abc6 1/* Target-dependent code for GNU/Linux on MIPS processors.
a094c6fb 2
6aba47ca 3 Copyright (C) 2001, 2002, 2004, 2005, 2006, 2007
76a9d10f 4 Free Software Foundation, Inc.
2aa830e4
DJ		 5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ		 20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
2aa830e4
DJ		 22
23#include "defs.h"
24#include "gdbcore.h"
25#include "target.h"
26#include "solib-svr4.h"
19ed69dd 27#include "osabi.h"
96f026fc 28#include "mips-tdep.h"
19ed69dd 29#include "gdb_string.h"
96f026fc 30#include "gdb_assert.h"
6de918a6 31#include "frame.h"
2fdf551c 32#include "regcache.h"
5792a79b
DJ		 33#include "trad-frame.h"
34#include "tramp-frame.h"
d05f6826 35#include "floatformat.h"
5ea03926 36#include "solib.h"
982e9687 37#include "symtab.h"
d37eb719 38#include "mips-linux-tdep.h"
2aa830e4
DJ		 39
40/* Figure out where the longjmp will land.
295093a4
MS		 41 We expect the first arg to be a pointer to the jmp_buf structure
42 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
43 at. The pc is copied into PC. This routine returns 1 on
44 success. */
2aa830e4 45
19ed69dd
KB		 46#define MIPS_LINUX_JB_ELEMENT_SIZE 4
47#define MIPS_LINUX_JB_PC 0
48
49static int
2aa830e4
DJ		 50mips_linux_get_longjmp_target (CORE_ADDR *pc)
51{
52 CORE_ADDR jb_addr;
53 char buf[TARGET_PTR_BIT / TARGET_CHAR_BIT];
54
613e114f 55 jb_addr = read_register (MIPS_A0_REGNUM);
2aa830e4 56
bf072999
DJ		 57 if (target_read_memory (jb_addr
58 + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE,
59 buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
2aa830e4
DJ		 60 return 0;
61
7c0b4a20 62 *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
2aa830e4
DJ		 63
64 return 1;
65}
66
4246e332 67/* Transform the bits comprising a 32-bit register to the right size
23a6d369
AC		 68 for regcache_raw_supply(). This is needed when mips_isa_regsize()
69 is 8. */
96f026fc
KB		 70
71static void
72supply_32bit_reg (int regnum, const void *addr)
73{
d37eb719 74 gdb_byte buf[MAX_REGISTER_SIZE];
3acba339 75 store_signed_integer (buf, register_size (current_gdbarch, regnum),
96f026fc 76 extract_signed_integer (addr, 4));
23a6d369 77 regcache_raw_supply (current_regcache, regnum, buf);
96f026fc
KB		 78}
79
2aa830e4
DJ		 80/* Unpack an elf_gregset_t into GDB's register cache. */
81
d37eb719
DJ		 82void
83mips_supply_gregset (mips_elf_gregset_t *gregsetp)
2aa830e4
DJ		 84{
85 int regi;
d37eb719 86 mips_elf_greg_t *regp = *gregsetp;
d9d9c31f 87 char zerobuf[MAX_REGISTER_SIZE];
bf072999 88
d9d9c31f 89 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4
DJ		 90
91 for (regi = EF_REG0; regi <= EF_REG31; regi++)
96f026fc 92 supply_32bit_reg ((regi - EF_REG0), (char *)(regp + regi));
2aa830e4 93
56cea623
AC		 94 supply_32bit_reg (mips_regnum (current_gdbarch)->lo,
95 (char *)(regp + EF_LO));
96 supply_32bit_reg (mips_regnum (current_gdbarch)->hi,
97 (char *)(regp + EF_HI));
98
99 supply_32bit_reg (mips_regnum (current_gdbarch)->pc,
100 (char *)(regp + EF_CP0_EPC));
101 supply_32bit_reg (mips_regnum (current_gdbarch)->badvaddr,
102 (char *)(regp + EF_CP0_BADVADDR));
24e05951 103 supply_32bit_reg (MIPS_PS_REGNUM, (char *)(regp + EF_CP0_STATUS));
56cea623
AC		 104 supply_32bit_reg (mips_regnum (current_gdbarch)->cause,
105 (char *)(regp + EF_CP0_CAUSE));
2aa830e4
DJ		 106
107 /* Fill inaccessible registers with zero. */
613e114f 108 regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
295093a4
MS		 109 for (regi = MIPS_FIRST_EMBED_REGNUM;
110 regi < MIPS_LAST_EMBED_REGNUM;
111 regi++)
23a6d369 112 regcache_raw_supply (current_regcache, regi, zerobuf);
2aa830e4
DJ		 113}
114
115/* Pack our registers (or one register) into an elf_gregset_t. */
116
d37eb719
DJ		 117void
118mips_fill_gregset (mips_elf_gregset_t *gregsetp, int regno)
2aa830e4
DJ		 119{
120 int regaddr, regi;
d37eb719 121 mips_elf_greg_t *regp = *gregsetp;
96f026fc 122 void *dst;
2aa830e4
DJ		 123
124 if (regno == -1)
125 {
d37eb719 126 memset (regp, 0, sizeof (mips_elf_gregset_t));
2aa830e4 127 for (regi = 0; regi < 32; regi++)
9f62d0e2
DJ		 128 mips_fill_gregset (gregsetp, regi);
129 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
130 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
131 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
132 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->badvaddr);
133 mips_fill_gregset (gregsetp, MIPS_PS_REGNUM);
134 mips_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->cause);
2aa830e4
DJ		 135
136 return;
137 }
138
139 if (regno < 32)
140 {
2aa830e4 141 dst = regp + regno + EF_REG0;
822c9732 142 regcache_raw_collect (current_regcache, regno, dst);
2aa830e4
DJ		 143 return;
144 }
145
56cea623
AC		 146 if (regno == mips_regnum (current_gdbarch)->lo)
147 regaddr = EF_LO;
148 else if (regno == mips_regnum (current_gdbarch)->hi)
149 regaddr = EF_HI;
150 else if (regno == mips_regnum (current_gdbarch)->pc)
151 regaddr = EF_CP0_EPC;
152 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
153 regaddr = EF_CP0_BADVADDR;
24e05951 154 else if (regno == MIPS_PS_REGNUM)
56cea623
AC		 155 regaddr = EF_CP0_STATUS;
156 else if (regno == mips_regnum (current_gdbarch)->cause)
157 regaddr = EF_CP0_CAUSE;
158 else
159 regaddr = -1;
2aa830e4
DJ		 160
161 if (regaddr != -1)
162 {
2aa830e4 163 dst = regp + regaddr;
822c9732 164 regcache_raw_collect (current_regcache, regno, dst);
2aa830e4
DJ		 165 }
166}
167
168/* Likewise, unpack an elf_fpregset_t. */
169
d37eb719
DJ		 170void
171mips_supply_fpregset (mips_elf_fpregset_t *fpregsetp)
2aa830e4 172{
52f0bd74 173 int regi;
d9d9c31f 174 char zerobuf[MAX_REGISTER_SIZE];
bf072999 175
d9d9c31f 176 memset (zerobuf, 0, MAX_REGISTER_SIZE);
2aa830e4
DJ		 177
178 for (regi = 0; regi < 32; regi++)
23a6d369
AC		 179 regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
180 (char *)(*fpregsetp + regi));
2aa830e4 181
23a6d369
AC		 182 regcache_raw_supply (current_regcache,
183 mips_regnum (current_gdbarch)->fp_control_status,
184 (char *)(*fpregsetp + 32));
2aa830e4 185
295093a4 186 /* FIXME: how can we supply FCRIR? The ABI doesn't tell us. */
23a6d369
AC		 187 regcache_raw_supply (current_regcache,
188 mips_regnum (current_gdbarch)->fp_implementation_revision,
189 zerobuf);
2aa830e4
DJ		 190}
191
192/* Likewise, pack one or all floating point registers into an
193 elf_fpregset_t. */
194
d37eb719
DJ		 195void
196mips_fill_fpregset (mips_elf_fpregset_t *fpregsetp, int regno)
2aa830e4
DJ		 197{
198 char *from, *to;
199
200 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
201 {
2aa830e4 202 to = (char *) (*fpregsetp + regno - FP0_REGNUM);
2fdf551c 203 regcache_raw_collect (current_regcache, regno, to);
2aa830e4 204 }
56cea623 205 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
2aa830e4 206 {
2aa830e4 207 to = (char *) (*fpregsetp + 32);
2fdf551c 208 regcache_raw_collect (current_regcache, regno, to);
2aa830e4
DJ		 209 }
210 else if (regno == -1)
211 {
212 int regi;
213
214 for (regi = 0; regi < 32; regi++)
9f62d0e2
DJ		 215 mips_fill_fpregset (fpregsetp, FP0_REGNUM + regi);
216 mips_fill_fpregset (fpregsetp,
217 mips_regnum (current_gdbarch)->fp_control_status);
2aa830e4
DJ		 218 }
219}
220
221/* Map gdb internal register number to ptrace ``address''.
222 These ``addresses'' are normally defined in <asm/ptrace.h>. */
223
96f026fc
KB		 224static CORE_ADDR
225mips_linux_register_addr (int regno, CORE_ADDR blockend)
2aa830e4
DJ		 226{
227 int regaddr;
228
229 if (regno < 0 || regno >= NUM_REGS)
8a3fe4f8 230 error (_("Bogon register number %d."), regno);
2aa830e4
DJ		 231
232 if (regno < 32)
233 regaddr = regno;
56cea623
AC		 234 else if ((regno >= mips_regnum (current_gdbarch)->fp0)
235 && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
236 regaddr = FPR_BASE + (regno - mips_regnum (current_gdbarch)->fp0);
237 else if (regno == mips_regnum (current_gdbarch)->pc)
2aa830e4 238 regaddr = PC;
56cea623 239 else if (regno == mips_regnum (current_gdbarch)->cause)
2aa830e4 240 regaddr = CAUSE;
56cea623 241 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
2aa830e4 242 regaddr = BADVADDR;
56cea623 243 else if (regno == mips_regnum (current_gdbarch)->lo)
2aa830e4 244 regaddr = MMLO;
56cea623 245 else if (regno == mips_regnum (current_gdbarch)->hi)
2aa830e4 246 regaddr = MMHI;
56cea623 247 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
2aa830e4 248 regaddr = FPC_CSR;
56cea623 249 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
2aa830e4
DJ		 250 regaddr = FPC_EIR;
251 else
8a3fe4f8 252 error (_("Unknowable register number %d."), regno);
2aa830e4
DJ		 253
254 return regaddr;
255}
256
96f026fc
KB		 257/* Support for 64-bit ABIs. */
258
96f026fc 259/* Figure out where the longjmp will land.
295093a4
MS		 260 We expect the first arg to be a pointer to the jmp_buf structure
261 from which we extract the pc (MIPS_LINUX_JB_PC) that we will land
262 at. The pc is copied into PC. This routine returns 1 on
263 success. */
96f026fc
KB		 264
265/* Details about jmp_buf. */
266
267#define MIPS64_LINUX_JB_PC 0
268
269static int
270mips64_linux_get_longjmp_target (CORE_ADDR *pc)
271{
272 CORE_ADDR jb_addr;
273 void *buf = alloca (TARGET_PTR_BIT / TARGET_CHAR_BIT);
274 int element_size = TARGET_PTR_BIT == 32 ? 4 : 8;
275
613e114f 276 jb_addr = read_register (MIPS_A0_REGNUM);
96f026fc
KB		 277
278 if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size,
279 buf, TARGET_PTR_BIT / TARGET_CHAR_BIT))
280 return 0;
281
7c0b4a20 282 *pc = extract_unsigned_integer (buf, TARGET_PTR_BIT / TARGET_CHAR_BIT);
96f026fc
KB		 283
284 return 1;
285}
286
d37eb719
DJ		 287/* Register set support functions. These operate on standard 64-bit
288 regsets, but work whether the target is 32-bit or 64-bit. A 32-bit
289 target will still use the 64-bit format for PTRACE_GETREGS. */
290
291/* Supply a 64-bit register. */
96f026fc 292
d37eb719
DJ		 293void
294supply_64bit_reg (int regnum, const gdb_byte *buf)
295{
296 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG
297 && register_size (current_gdbarch, regnum) == 4)
298 regcache_raw_supply (current_regcache, regnum, buf + 4);
299 else
300 regcache_raw_supply (current_regcache, regnum, buf);
301}
302
303/* Unpack a 64-bit elf_gregset_t into GDB's register cache. */
304
305void
96f026fc
KB		 306mips64_supply_gregset (mips64_elf_gregset_t *gregsetp)
307{
308 int regi;
309 mips64_elf_greg_t *regp = *gregsetp;
d37eb719 310 gdb_byte zerobuf[MAX_REGISTER_SIZE];
96f026fc 311
d9d9c31f 312 memset (zerobuf, 0, MAX_REGISTER_SIZE);
96f026fc
KB		 313
314 for (regi = MIPS64_EF_REG0; regi <= MIPS64_EF_REG31; regi++)
d37eb719
DJ		 315 supply_64bit_reg (regi - MIPS64_EF_REG0, (gdb_byte *)(regp + regi));
316
317 supply_64bit_reg (mips_regnum (current_gdbarch)->lo,
318 (gdb_byte *) (regp + MIPS64_EF_LO));
319 supply_64bit_reg (mips_regnum (current_gdbarch)->hi,
320 (gdb_byte *) (regp + MIPS64_EF_HI));
321
322 supply_64bit_reg (mips_regnum (current_gdbarch)->pc,
323 (gdb_byte *) (regp + MIPS64_EF_CP0_EPC));
324 supply_64bit_reg (mips_regnum (current_gdbarch)->badvaddr,
325 (gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR));
326 supply_64bit_reg (MIPS_PS_REGNUM,
327 (gdb_byte *) (regp + MIPS64_EF_CP0_STATUS));
328 supply_64bit_reg (mips_regnum (current_gdbarch)->cause,
329 (gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE));
96f026fc
KB		 330
331 /* Fill inaccessible registers with zero. */
613e114f 332 regcache_raw_supply (current_regcache, MIPS_UNUSED_REGNUM, zerobuf);
295093a4
MS		 333 for (regi = MIPS_FIRST_EMBED_REGNUM;
334 regi < MIPS_LAST_EMBED_REGNUM;
335 regi++)
23a6d369 336 regcache_raw_supply (current_regcache, regi, zerobuf);
96f026fc
KB		 337}
338
d37eb719 339/* Pack our registers (or one register) into a 64-bit elf_gregset_t. */
96f026fc 340
d37eb719 341void
96f026fc
KB		 342mips64_fill_gregset (mips64_elf_gregset_t *gregsetp, int regno)
343{
344 int regaddr, regi;
345 mips64_elf_greg_t *regp = *gregsetp;
346 void *src, *dst;
347
348 if (regno == -1)
349 {
350 memset (regp, 0, sizeof (mips64_elf_gregset_t));
351 for (regi = 0; regi < 32; regi++)
352 mips64_fill_gregset (gregsetp, regi);
56cea623
AC		 353 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->lo);
354 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->hi);
355 mips64_fill_gregset (gregsetp, mips_regnum (current_gdbarch)->pc);
295093a4
MS		 356 mips64_fill_gregset (gregsetp,
357 mips_regnum (current_gdbarch)->badvaddr);
24e05951 358 mips64_fill_gregset (gregsetp, MIPS_PS_REGNUM);
295093a4
MS		 359 mips64_fill_gregset (gregsetp,
360 mips_regnum (current_gdbarch)->cause);
96f026fc
KB		 361
362 return;
363 }
364
365 if (regno < 32)
d37eb719
DJ		 366 regaddr = regno + MIPS64_EF_REG0;
367 else if (regno == mips_regnum (current_gdbarch)->lo)
56cea623
AC		 368 regaddr = MIPS64_EF_LO;
369 else if (regno == mips_regnum (current_gdbarch)->hi)
370 regaddr = MIPS64_EF_HI;
371 else if (regno == mips_regnum (current_gdbarch)->pc)
372 regaddr = MIPS64_EF_CP0_EPC;
373 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
374 regaddr = MIPS64_EF_CP0_BADVADDR;
24e05951 375 else if (regno == MIPS_PS_REGNUM)
56cea623
AC		 376 regaddr = MIPS64_EF_CP0_STATUS;
377 else if (regno == mips_regnum (current_gdbarch)->cause)
378 regaddr = MIPS64_EF_CP0_CAUSE;
379 else
380 regaddr = -1;
96f026fc
KB		 381
382 if (regaddr != -1)
383 {
d37eb719
DJ		 384 gdb_byte buf[MAX_REGISTER_SIZE];
385 LONGEST val;
386
387 regcache_raw_collect (current_regcache, regno, buf);
388 val = extract_signed_integer (buf,
389 register_size (current_gdbarch, regno));
96f026fc 390 dst = regp + regaddr;
d37eb719 391 store_signed_integer (dst, 8, val);
96f026fc
KB		 392 }
393}
394
395/* Likewise, unpack an elf_fpregset_t. */
396
d37eb719 397void
96f026fc
KB		 398mips64_supply_fpregset (mips64_elf_fpregset_t *fpregsetp)
399{
52f0bd74 400 int regi;
96f026fc 401
d37eb719
DJ		 402 /* See mips_linux_o32_sigframe_init for a description of the
403 peculiar FP register layout. */
404 if (register_size (current_gdbarch, FP0_REGNUM) == 4)
405 for (regi = 0; regi < 32; regi++)
406 {
407 gdb_byte *reg_ptr = (gdb_byte *) (*fpregsetp + (regi & ~1));
408 if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (regi & 1))
409 reg_ptr += 4;
410 regcache_raw_supply (current_regcache, FP0_REGNUM + regi, reg_ptr);
411 }
412 else
413 for (regi = 0; regi < 32; regi++)
414 regcache_raw_supply (current_regcache, FP0_REGNUM + regi,
415 (char *)(*fpregsetp + regi));
416
417 supply_32bit_reg (mips_regnum (current_gdbarch)->fp_control_status,
418 (gdb_byte *)(*fpregsetp + 32));
419
420 /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't
421 include it - but the result of PTRACE_GETFPREGS does. The best we
422 can do is to assume that its value is present. */
423 supply_32bit_reg (mips_regnum (current_gdbarch)->fp_implementation_revision,
424 (gdb_byte *)(*fpregsetp + 32) + 4);
96f026fc
KB		 425}
426
427/* Likewise, pack one or all floating point registers into an
428 elf_fpregset_t. */
429
d37eb719 430void
96f026fc
KB		 431mips64_fill_fpregset (mips64_elf_fpregset_t *fpregsetp, int regno)
432{
d37eb719 433 gdb_byte *to;
96f026fc
KB		 434
435 if ((regno >= FP0_REGNUM) && (regno < FP0_REGNUM + 32))
436 {
d37eb719
DJ		 437 /* See mips_linux_o32_sigframe_init for a description of the
438 peculiar FP register layout. */
439 if (register_size (current_gdbarch, regno) == 4)
440 {
441 int regi = regno - FP0_REGNUM;
442
443 to = (gdb_byte *) (*fpregsetp + (regi & ~1));
444 if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (regi & 1))
445 to += 4;
446 regcache_raw_collect (current_regcache, regno, to);
447 }
448 else
449 {
450 to = (gdb_byte *) (*fpregsetp + regno - FP0_REGNUM);
451 regcache_raw_collect (current_regcache, regno, to);
452 }
96f026fc 453 }
56cea623 454 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
96f026fc 455 {
d37eb719
DJ		 456 gdb_byte buf[MAX_REGISTER_SIZE];
457 LONGEST val;
458
459 regcache_raw_collect (current_regcache, regno, buf);
460 val = extract_signed_integer (buf,
461 register_size (current_gdbarch, regno));
462 to = (gdb_byte *) (*fpregsetp + 32);
463 store_signed_integer (to, 4, val);
464 }
465 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
466 {
467 gdb_byte buf[MAX_REGISTER_SIZE];
468 LONGEST val;
469
470 regcache_raw_collect (current_regcache, regno, buf);
471 val = extract_signed_integer (buf,
472 register_size (current_gdbarch, regno));
473 to = (gdb_byte *) (*fpregsetp + 32) + 4;
474 store_signed_integer (to, 4, val);
96f026fc
KB		 475 }
476 else if (regno == -1)
477 {
478 int regi;
479
480 for (regi = 0; regi < 32; regi++)
481 mips64_fill_fpregset (fpregsetp, FP0_REGNUM + regi);
d37eb719
DJ		 482 mips64_fill_fpregset (fpregsetp,
483 mips_regnum (current_gdbarch)->fp_control_status);
484 mips64_fill_fpregset (fpregsetp, (mips_regnum (current_gdbarch)
485 ->fp_implementation_revision));
96f026fc
KB		 486 }
487}
488
489
490/* Map gdb internal register number to ptrace ``address''.
491 These ``addresses'' are normally defined in <asm/ptrace.h>. */
492
493static CORE_ADDR
494mips64_linux_register_addr (int regno, CORE_ADDR blockend)
495{
496 int regaddr;
497
498 if (regno < 0 || regno >= NUM_REGS)
8a3fe4f8 499 error (_("Bogon register number %d."), regno);
96f026fc
KB		 500
501 if (regno < 32)
502 regaddr = regno;
56cea623
AC		 503 else if ((regno >= mips_regnum (current_gdbarch)->fp0)
504 && (regno < mips_regnum (current_gdbarch)->fp0 + 32))
96f026fc 505 regaddr = MIPS64_FPR_BASE + (regno - FP0_REGNUM);
56cea623 506 else if (regno == mips_regnum (current_gdbarch)->pc)
96f026fc 507 regaddr = MIPS64_PC;
56cea623 508 else if (regno == mips_regnum (current_gdbarch)->cause)
96f026fc 509 regaddr = MIPS64_CAUSE;
56cea623 510 else if (regno == mips_regnum (current_gdbarch)->badvaddr)
96f026fc 511 regaddr = MIPS64_BADVADDR;
56cea623 512 else if (regno == mips_regnum (current_gdbarch)->lo)
96f026fc 513 regaddr = MIPS64_MMLO;
56cea623 514 else if (regno == mips_regnum (current_gdbarch)->hi)
96f026fc 515 regaddr = MIPS64_MMHI;
56cea623 516 else if (regno == mips_regnum (current_gdbarch)->fp_control_status)
96f026fc 517 regaddr = MIPS64_FPC_CSR;
56cea623 518 else if (regno == mips_regnum (current_gdbarch)->fp_implementation_revision)
96f026fc
KB		 519 regaddr = MIPS64_FPC_EIR;
520 else
8a3fe4f8 521 error (_("Unknowable register number %d."), regno);
96f026fc
KB		 522
523 return regaddr;
524}
525
2aa830e4
DJ		 526/* Use a local version of this function to get the correct types for
527 regsets, until multi-arch core support is ready. */
528
529static void
530fetch_core_registers (char *core_reg_sect, unsigned core_reg_size,
531 int which, CORE_ADDR reg_addr)
532{
d37eb719
DJ		 533 mips_elf_gregset_t gregset;
534 mips_elf_fpregset_t fpregset;
96f026fc
KB		 535 mips64_elf_gregset_t gregset64;
536 mips64_elf_fpregset_t fpregset64;
2aa830e4
DJ		 537
538 if (which == 0)
539 {
96f026fc 540 if (core_reg_size == sizeof (gregset))
2aa830e4 541 {
96f026fc 542 memcpy ((char *) &gregset, core_reg_sect, sizeof (gregset));
9f62d0e2 543 mips_supply_gregset (&gregset);
96f026fc
KB		 544 }
545 else if (core_reg_size == sizeof (gregset64))
546 {
547 memcpy ((char *) &gregset64, core_reg_sect, sizeof (gregset64));
548 mips64_supply_gregset (&gregset64);
2aa830e4
DJ		 549 }
550 else
551 {
8a3fe4f8 552 warning (_("wrong size gregset struct in core file"));
2aa830e4
DJ		 553 }
554 }
555 else if (which == 2)
556 {
96f026fc 557 if (core_reg_size == sizeof (fpregset))
2aa830e4 558 {
96f026fc 559 memcpy ((char *) &fpregset, core_reg_sect, sizeof (fpregset));
9f62d0e2 560 mips_supply_fpregset (&fpregset);
96f026fc
KB		 561 }
562 else if (core_reg_size == sizeof (fpregset64))
563 {
295093a4
MS		 564 memcpy ((char *) &fpregset64, core_reg_sect,
565 sizeof (fpregset64));
96f026fc 566 mips64_supply_fpregset (&fpregset64);
2aa830e4
DJ		 567 }
568 else
569 {
8a3fe4f8 570 warning (_("wrong size fpregset struct in core file"));
2aa830e4
DJ		 571 }
572 }
573}
574
575/* Register that we are able to handle ELF file formats using standard
576 procfs "regset" structures. */
577
578static struct core_fns regset_core_fns =
579{
580 bfd_target_elf_flavour, /* core_flavour */
581 default_check_format, /* check_format */
582 default_core_sniffer, /* core_sniffer */
583 fetch_core_registers, /* core_read_registers */
584 NULL /* next */
585};
586
295093a4
MS		 587/* Handle for obtaining pointer to the current register_addr()
588 function for a given architecture. */
96f026fc
KB		 589static struct gdbarch_data *register_addr_data;
590
591CORE_ADDR
592register_addr (int regno, CORE_ADDR blockend)
593{
594 CORE_ADDR (*register_addr_ptr) (int, CORE_ADDR) =
595 gdbarch_data (current_gdbarch, register_addr_data);
596
597 gdb_assert (register_addr_ptr != 0);
598
599 return register_addr_ptr (regno, blockend);
600}
601
602static void
603set_mips_linux_register_addr (struct gdbarch *gdbarch,
295093a4
MS		 604 CORE_ADDR (*register_addr_ptr) (int,
605 CORE_ADDR))
96f026fc 606{
295093a4
MS		 607 deprecated_set_gdbarch_data (gdbarch, register_addr_data,
608 register_addr_ptr);
96f026fc
KB		 609}
610
611static void *
612init_register_addr_data (struct gdbarch *gdbarch)
613{
614 return 0;
615}
616
295093a4
MS		 617/* Check the code at PC for a dynamic linker lazy resolution stub.
618 Because they aren't in the .plt section, we pattern-match on the
619 code generated by GNU ld. They look like this:
6de918a6
DJ		 620
621 lw t9,0x8010(gp)
622 addu t7,ra
623 jalr t9,ra
624 addiu t8,zero,INDEX
625
295093a4
MS		 626 (with the appropriate doubleword instructions for N64). Also
627 return the dynamic symbol index used in the last instruction. */
6de918a6
DJ		 628
629static int
630mips_linux_in_dynsym_stub (CORE_ADDR pc, char *name)
631{
632 unsigned char buf[28], *p;
633 ULONGEST insn, insn1;
634 int n64 = (mips_abi (current_gdbarch) == MIPS_ABI_N64);
635
636 read_memory (pc - 12, buf, 28);
637
638 if (n64)
639 {
640 /* ld t9,0x8010(gp) */
641 insn1 = 0xdf998010;
642 }
643 else
644 {
645 /* lw t9,0x8010(gp) */
646 insn1 = 0x8f998010;
647 }
648
649 p = buf + 12;
650 while (p >= buf)
651 {
652 insn = extract_unsigned_integer (p, 4);
653 if (insn == insn1)
654 break;
655 p -= 4;
656 }
657 if (p < buf)
658 return 0;
659
660 insn = extract_unsigned_integer (p + 4, 4);
661 if (n64)
662 {
663 /* daddu t7,ra */
664 if (insn != 0x03e0782d)
665 return 0;
666 }
667 else
668 {
669 /* addu t7,ra */
670 if (insn != 0x03e07821)
671 return 0;
672 }
295093a4 673
6de918a6
DJ		 674 insn = extract_unsigned_integer (p + 8, 4);
675 /* jalr t9,ra */
676 if (insn != 0x0320f809)
677 return 0;
678
679 insn = extract_unsigned_integer (p + 12, 4);
680 if (n64)
681 {
682 /* daddiu t8,zero,0 */
683 if ((insn & 0xffff0000) != 0x64180000)
684 return 0;
685 }
686 else
687 {
688 /* addiu t8,zero,0 */
689 if ((insn & 0xffff0000) != 0x24180000)
690 return 0;
691 }
692
693 return (insn & 0xffff);
694}
695
295093a4
MS		 696/* Return non-zero iff PC belongs to the dynamic linker resolution
697 code or to a stub. */
6de918a6
DJ		 698
699int
700mips_linux_in_dynsym_resolve_code (CORE_ADDR pc)
701{
295093a4
MS		 702 /* Check whether PC is in the dynamic linker. This also checks
703 whether it is in the .plt section, which MIPS does not use. */
6de918a6
DJ		 704 if (in_solib_dynsym_resolve_code (pc))
705 return 1;
706
295093a4
MS		 707 /* Pattern match for the stub. It would be nice if there were a
708 more efficient way to avoid this check. */
6de918a6
DJ		 709 if (mips_linux_in_dynsym_stub (pc, NULL))
710 return 1;
711
712 return 0;
713}
714
715/* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c,
716 and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc
717 implementation of this triggers at "fixup" from the same objfile as
c4c5b7ba
AC		 718 "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at
719 "__dl_runtime_resolve" directly. An unresolved PLT entry will
720 point to _dl_runtime_resolve, which will first call
721 __dl_runtime_resolve, and then pass control to the resolved
722 function. */
6de918a6
DJ		 723
724static CORE_ADDR
725mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc)
726{
727 struct minimal_symbol *resolver;
728
729 resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL);
730
731 if (resolver && SYMBOL_VALUE_ADDRESS (resolver) == pc)
295093a4 732 return frame_pc_unwind (get_current_frame ());
6de918a6
DJ		 733
734 return 0;
295093a4 735}
6de918a6 736
5792a79b
DJ		 737/* Signal trampoline support. There are four supported layouts for a
738 signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and
739 n64 rt_sigframe. We handle them all independently; not the most
740 efficient way, but simplest. First, declare all the unwinders. */
741
742static void mips_linux_o32_sigframe_init (const struct tramp_frame *self,
743 struct frame_info *next_frame,
744 struct trad_frame_cache *this_cache,
745 CORE_ADDR func);
746
747static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
748 struct frame_info *next_frame,
749 struct trad_frame_cache *this_cache,
750 CORE_ADDR func);
751
752#define MIPS_NR_LINUX 4000
753#define MIPS_NR_N64_LINUX 5000
754#define MIPS_NR_N32_LINUX 6000
755
756#define MIPS_NR_sigreturn MIPS_NR_LINUX + 119
757#define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193
758#define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211
759#define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211
760
761#define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn
762#define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn
763#define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn
764#define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn
765#define MIPS_INST_SYSCALL 0x0000000c
766
2cd8546d
AC		 767static const struct tramp_frame mips_linux_o32_sigframe = {
768 SIGTRAMP_FRAME,
5792a79b 769 4,
2cd8546d
AC		 770 {
771 { MIPS_INST_LI_V0_SIGRETURN, -1 },
772 { MIPS_INST_SYSCALL, -1 },
773 { TRAMP_SENTINEL_INSN, -1 }
774 },
5792a79b
DJ		 775 mips_linux_o32_sigframe_init
776};
777
2cd8546d
AC		 778static const struct tramp_frame mips_linux_o32_rt_sigframe = {
779 SIGTRAMP_FRAME,
5792a79b 780 4,
2cd8546d
AC		 781 {
782 { MIPS_INST_LI_V0_RT_SIGRETURN, -1 },
783 { MIPS_INST_SYSCALL, -1 },
784 { TRAMP_SENTINEL_INSN, -1 } },
5792a79b
DJ		 785 mips_linux_o32_sigframe_init
786};
787
2cd8546d
AC		 788static const struct tramp_frame mips_linux_n32_rt_sigframe = {
789 SIGTRAMP_FRAME,
5792a79b 790 4,
2cd8546d
AC		 791 {
792 { MIPS_INST_LI_V0_N32_RT_SIGRETURN, -1 },
793 { MIPS_INST_SYSCALL, -1 },
794 { TRAMP_SENTINEL_INSN, -1 }
795 },
5792a79b
DJ		 796 mips_linux_n32n64_sigframe_init
797};
798
2cd8546d
AC		 799static const struct tramp_frame mips_linux_n64_rt_sigframe = {
800 SIGTRAMP_FRAME,
5792a79b 801 4,
295093a4
MS		 802 { MIPS_INST_LI_V0_N64_RT_SIGRETURN,
803 MIPS_INST_SYSCALL,
804 TRAMP_SENTINEL_INSN },
5792a79b
DJ		 805 mips_linux_n32n64_sigframe_init
806};
807
808/* *INDENT-OFF* */
809/* The unwinder for o32 signal frames. The legacy structures look
810 like this:
811
812 struct sigframe {
813 u32 sf_ass[4]; [argument save space for o32]
814 u32 sf_code[2]; [signal trampoline]
815 struct sigcontext sf_sc;
816 sigset_t sf_mask;
817 };
818
819 struct sigcontext {
820 unsigned int sc_regmask; [Unused]
821 unsigned int sc_status;
822 unsigned long long sc_pc;
823 unsigned long long sc_regs[32];
824 unsigned long long sc_fpregs[32];
825 unsigned int sc_ownedfp;
826 unsigned int sc_fpc_csr;
827 unsigned int sc_fpc_eir; [Unused]
828 unsigned int sc_used_math;
829 unsigned int sc_ssflags; [Unused]
830 [Alignment hole of four bytes]
831 unsigned long long sc_mdhi;
832 unsigned long long sc_mdlo;
833
834 unsigned int sc_cause; [Unused]
835 unsigned int sc_badvaddr; [Unused]
836
837 unsigned long sc_sigset[4]; [kernel's sigset_t]
838 };
839
840 The RT signal frames look like this:
841
842 struct rt_sigframe {
843 u32 rs_ass[4]; [argument save space for o32]
844 u32 rs_code[2] [signal trampoline]
845 struct siginfo rs_info;
846 struct ucontext rs_uc;
847 };
848
849 struct ucontext {
850 unsigned long uc_flags;
851 struct ucontext *uc_link;
852 stack_t uc_stack;
853 [Alignment hole of four bytes]
854 struct sigcontext uc_mcontext;
855 sigset_t uc_sigmask;
856 }; */
857/* *INDENT-ON* */
858
859#define SIGFRAME_CODE_OFFSET (4 * 4)
860#define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4)
861
862#define RTSIGFRAME_SIGINFO_SIZE 128
863#define STACK_T_SIZE (3 * 4)
864#define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4)
865#define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
866 + RTSIGFRAME_SIGINFO_SIZE \
867 + UCONTEXT_SIGCONTEXT_OFFSET)
868
869#define SIGCONTEXT_PC (1 * 8)
870#define SIGCONTEXT_REGS (2 * 8)
871#define SIGCONTEXT_FPREGS (34 * 8)
872#define SIGCONTEXT_FPCSR (66 * 8 + 4)
873#define SIGCONTEXT_HI (69 * 8)
874#define SIGCONTEXT_LO (70 * 8)
875#define SIGCONTEXT_CAUSE (71 * 8 + 0)
876#define SIGCONTEXT_BADVADDR (71 * 8 + 4)
877
878#define SIGCONTEXT_REG_SIZE 8
879
880static void
881mips_linux_o32_sigframe_init (const struct tramp_frame *self,
882 struct frame_info *next_frame,
883 struct trad_frame_cache *this_cache,
884 CORE_ADDR func)
885{
886 int ireg, reg_position;
887 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
888 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
37c4d197 889 CORE_ADDR regs_base;
5792a79b
DJ		 890
891 if (self == &mips_linux_o32_sigframe)
892 sigcontext_base += SIGFRAME_SIGCONTEXT_OFFSET;
893 else
894 sigcontext_base += RTSIGFRAME_SIGCONTEXT_OFFSET;
295093a4
MS		 895
896 /* I'm not proud of this hack. Eventually we will have the
897 infrastructure to indicate the size of saved registers on a
898 per-frame basis, but right now we don't; the kernel saves eight
37c4d197
DJ		 899 bytes but we only want four. Use regs_base to access any
900 64-bit fields. */
5792a79b 901 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
37c4d197
DJ		 902 regs_base = sigcontext_base + 4;
903 else
904 regs_base = sigcontext_base;
5792a79b
DJ		 905
906#if 0
907 trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
37c4d197 908 regs_base + SIGCONTEXT_REGS);
5792a79b
DJ		 909#endif
910
911 for (ireg = 1; ireg < 32; ireg++)
295093a4
MS		 912 trad_frame_set_reg_addr (this_cache,
913 ireg + MIPS_ZERO_REGNUM + NUM_REGS,
37c4d197 914 regs_base + SIGCONTEXT_REGS
5792a79b
DJ		 915 + ireg * SIGCONTEXT_REG_SIZE);
916
37c4d197
DJ		 917 /* The way that floating point registers are saved, unfortunately,
918 depends on the architecture the kernel is built for. For the r3000 and
919 tx39, four bytes of each register are at the beginning of each of the
920 32 eight byte slots. For everything else, the registers are saved
921 using double precision; only the even-numbered slots are initialized,
922 and the high bits are the odd-numbered register. Assume the latter
923 layout, since we can't tell, and it's much more common. Which bits are
924 the "high" bits depends on endianness. */
5792a79b 925 for (ireg = 0; ireg < 32; ireg++)
37c4d197
DJ		 926 if ((TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) != (ireg & 1))
927 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
928 sigcontext_base + SIGCONTEXT_FPREGS + 4
929 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
930 else
931 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
932 sigcontext_base + SIGCONTEXT_FPREGS
933 + (ireg & ~1) * SIGCONTEXT_REG_SIZE);
5792a79b
DJ		 934
935 trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
37c4d197 936 regs_base + SIGCONTEXT_PC);
5792a79b 937
295093a4
MS		 938 trad_frame_set_reg_addr (this_cache,
939 regs->fp_control_status + NUM_REGS,
5792a79b
DJ		 940 sigcontext_base + SIGCONTEXT_FPCSR);
941 trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
37c4d197 942 regs_base + SIGCONTEXT_HI);
5792a79b 943 trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
37c4d197 944 regs_base + SIGCONTEXT_LO);
5792a79b
DJ		 945 trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
946 sigcontext_base + SIGCONTEXT_CAUSE);
947 trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
948 sigcontext_base + SIGCONTEXT_BADVADDR);
949
950 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
951 trad_frame_set_id (this_cache,
295093a4
MS		 952 frame_id_build (func - SIGFRAME_CODE_OFFSET,
953 func));
5792a79b
DJ		 954}
955
956/* *INDENT-OFF* */
957/* For N32/N64 things look different. There is no non-rt signal frame.
958
959 struct rt_sigframe_n32 {
960 u32 rs_ass[4]; [ argument save space for o32 ]
961 u32 rs_code[2]; [ signal trampoline ]
962 struct siginfo rs_info;
963 struct ucontextn32 rs_uc;
964 };
965
966 struct ucontextn32 {
967 u32 uc_flags;
968 s32 uc_link;
969 stack32_t uc_stack;
970 struct sigcontext uc_mcontext;
971 sigset_t uc_sigmask; [ mask last for extensibility ]
972 };
295093a4 973
5792a79b
DJ		 974 struct rt_sigframe_n32 {
975 u32 rs_ass[4]; [ argument save space for o32 ]
976 u32 rs_code[2]; [ signal trampoline ]
977 struct siginfo rs_info;
978 struct ucontext rs_uc;
979 };
980
981 struct ucontext {
982 unsigned long uc_flags;
983 struct ucontext *uc_link;
984 stack_t uc_stack;
985 struct sigcontext uc_mcontext;
986 sigset_t uc_sigmask; [ mask last for extensibility ]
987 };
988
989 And the sigcontext is different (this is for both n32 and n64):
990
991 struct sigcontext {
992 unsigned long long sc_regs[32];
993 unsigned long long sc_fpregs[32];
994 unsigned long long sc_mdhi;
995 unsigned long long sc_mdlo;
996 unsigned long long sc_pc;
997 unsigned int sc_status;
998 unsigned int sc_fpc_csr;
999 unsigned int sc_fpc_eir;
1000 unsigned int sc_used_math;
1001 unsigned int sc_cause;
1002 unsigned int sc_badvaddr;
1003 }; */
1004/* *INDENT-ON* */
1005
1006#define N32_STACK_T_SIZE STACK_T_SIZE
1007#define N64_STACK_T_SIZE (2 * 8 + 4)
1008#define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4)
1009#define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4)
1010#define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1011 + RTSIGFRAME_SIGINFO_SIZE \
1012 + N32_UCONTEXT_SIGCONTEXT_OFFSET)
1013#define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \
1014 + RTSIGFRAME_SIGINFO_SIZE \
1015 + N64_UCONTEXT_SIGCONTEXT_OFFSET)
1016
1017#define N64_SIGCONTEXT_REGS (0 * 8)
1018#define N64_SIGCONTEXT_FPREGS (32 * 8)
1019#define N64_SIGCONTEXT_HI (64 * 8)
1020#define N64_SIGCONTEXT_LO (65 * 8)
1021#define N64_SIGCONTEXT_PC (66 * 8)
1022#define N64_SIGCONTEXT_FPCSR (67 * 8 + 1 * 4)
1023#define N64_SIGCONTEXT_FIR (67 * 8 + 2 * 4)
1024#define N64_SIGCONTEXT_CAUSE (67 * 8 + 4 * 4)
1025#define N64_SIGCONTEXT_BADVADDR (67 * 8 + 5 * 4)
1026
1027#define N64_SIGCONTEXT_REG_SIZE 8
295093a4 1028
5792a79b
DJ		 1029static void
1030mips_linux_n32n64_sigframe_init (const struct tramp_frame *self,
1031 struct frame_info *next_frame,
1032 struct trad_frame_cache *this_cache,
1033 CORE_ADDR func)
1034{
1035 int ireg, reg_position;
1036 CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET;
1037 const struct mips_regnum *regs = mips_regnum (current_gdbarch);
1038
1039 if (self == &mips_linux_n32_rt_sigframe)
1040 sigcontext_base += N32_SIGFRAME_SIGCONTEXT_OFFSET;
1041 else
1042 sigcontext_base += N64_SIGFRAME_SIGCONTEXT_OFFSET;
295093a4 1043
5792a79b
DJ		 1044#if 0
1045 trad_frame_set_reg_addr (this_cache, ORIG_ZERO_REGNUM + NUM_REGS,
1046 sigcontext_base + N64_SIGCONTEXT_REGS);
1047#endif
1048
1049 for (ireg = 1; ireg < 32; ireg++)
295093a4
MS		 1050 trad_frame_set_reg_addr (this_cache,
1051 ireg + MIPS_ZERO_REGNUM + NUM_REGS,
5792a79b
DJ		 1052 sigcontext_base + N64_SIGCONTEXT_REGS
1053 + ireg * N64_SIGCONTEXT_REG_SIZE);
1054
1055 for (ireg = 0; ireg < 32; ireg++)
1056 trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + NUM_REGS,
1057 sigcontext_base + N64_SIGCONTEXT_FPREGS
1058 + ireg * N64_SIGCONTEXT_REG_SIZE);
1059
1060 trad_frame_set_reg_addr (this_cache, regs->pc + NUM_REGS,
1061 sigcontext_base + N64_SIGCONTEXT_PC);
1062
295093a4
MS		 1063 trad_frame_set_reg_addr (this_cache,
1064 regs->fp_control_status + NUM_REGS,
5792a79b
DJ		 1065 sigcontext_base + N64_SIGCONTEXT_FPCSR);
1066 trad_frame_set_reg_addr (this_cache, regs->hi + NUM_REGS,
1067 sigcontext_base + N64_SIGCONTEXT_HI);
1068 trad_frame_set_reg_addr (this_cache, regs->lo + NUM_REGS,
1069 sigcontext_base + N64_SIGCONTEXT_LO);
1070 trad_frame_set_reg_addr (this_cache, regs->cause + NUM_REGS,
1071 sigcontext_base + N64_SIGCONTEXT_CAUSE);
1072 trad_frame_set_reg_addr (this_cache, regs->badvaddr + NUM_REGS,
1073 sigcontext_base + N64_SIGCONTEXT_BADVADDR);
1074
1075 /* Choice of the bottom of the sigframe is somewhat arbitrary. */
1076 trad_frame_set_id (this_cache,
295093a4
MS		 1077 frame_id_build (func - SIGFRAME_CODE_OFFSET,
1078 func));
5792a79b
DJ		 1079}
1080
9f62d0e2
DJ		 1081/* Wrapper functions. These are only used by libthread_db. */
1082
1083void
d37eb719 1084supply_gregset (mips_elf_gregset_t *gregsetp)
9f62d0e2
DJ		 1085{
1086 if (mips_isa_regsize (current_gdbarch) == 4)
1087 mips_supply_gregset (gregsetp);
1088 else
1089 mips64_supply_gregset ((void *) gregsetp);
1090}
1091
1092void
d37eb719 1093fill_gregset (mips_elf_gregset_t *gregsetp, int regno)
9f62d0e2
DJ		 1094{
1095 if (mips_isa_regsize (current_gdbarch) == 4)
1096 mips_fill_gregset (gregsetp, regno);
1097 else
1098 mips64_fill_gregset ((void *) gregsetp, regno);
1099}
1100
1101/* Likewise, unpack an elf_fpregset_t. */
1102
1103void
d37eb719 1104supply_fpregset (mips_elf_fpregset_t *fpregsetp)
9f62d0e2
DJ		 1105{
1106 if (mips_isa_regsize (current_gdbarch) == 4)
1107 mips_supply_fpregset (fpregsetp);
1108 else
1109 mips64_supply_fpregset ((void *) fpregsetp);
1110}
1111
1112/* Likewise, pack one or all floating point registers into an
1113 elf_fpregset_t. */
1114
1115void
d37eb719 1116fill_fpregset (mips_elf_fpregset_t *fpregsetp, int regno)
9f62d0e2
DJ		 1117{
1118 if (mips_isa_regsize (current_gdbarch) == 4)
1119 mips_fill_fpregset (fpregsetp, regno);
1120 else
1121 mips64_fill_fpregset ((void *) fpregsetp, regno);
1122}
1123
5792a79b
DJ		 1124/* Initialize one of the GNU/Linux OS ABIs. */
1125
19ed69dd 1126static void
295093a4
MS		 1127mips_linux_init_abi (struct gdbarch_info info,
1128 struct gdbarch *gdbarch)
19ed69dd 1129{
96f026fc
KB		 1130 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1131 enum mips_abi abi = mips_abi (gdbarch);
1132
1133 switch (abi)
1134 {
1135 case MIPS_ABI_O32:
1136 set_gdbarch_get_longjmp_target (gdbarch,
1137 mips_linux_get_longjmp_target);
1138 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1139 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
96f026fc 1140 set_mips_linux_register_addr (gdbarch, mips_linux_register_addr);
fb2be677
AC		 1141 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe);
1142 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe);
96f026fc
KB		 1143 break;
1144 case MIPS_ABI_N32:
1145 set_gdbarch_get_longjmp_target (gdbarch,
1146 mips_linux_get_longjmp_target);
1147 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1148 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
96f026fc 1149 set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
d05f6826
DJ		 1150 set_gdbarch_long_double_bit (gdbarch, 128);
1151 /* These floatformats should probably be renamed. MIPS uses
1152 the same 128-bit IEEE floating point format that IA-64 uses,
1153 except that the quiet/signalling NaN bit is reversed (GDB
1154 does not distinguish between quiet and signalling NaNs). */
1155 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1156 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_big);
1157 else
1158 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_little);
fb2be677 1159 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe);
96f026fc
KB		 1160 break;
1161 case MIPS_ABI_N64:
1162 set_gdbarch_get_longjmp_target (gdbarch,
1163 mips64_linux_get_longjmp_target);
1164 set_solib_svr4_fetch_link_map_offsets
76a9d10f 1165 (gdbarch, svr4_lp64_fetch_link_map_offsets);
96f026fc 1166 set_mips_linux_register_addr (gdbarch, mips64_linux_register_addr);
d05f6826
DJ		 1167 set_gdbarch_long_double_bit (gdbarch, 128);
1168 /* These floatformats should probably be renamed. MIPS uses
1169 the same 128-bit IEEE floating point format that IA-64 uses,
1170 except that the quiet/signalling NaN bit is reversed (GDB
1171 does not distinguish between quiet and signalling NaNs). */
1172 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1173 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_big);
1174 else
1175 set_gdbarch_long_double_format (gdbarch, &floatformat_ia64_quad_little);
fb2be677 1176 tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe);
96f026fc
KB		 1177 break;
1178 default:
e2e0b3e5 1179 internal_error (__FILE__, __LINE__, _("can't handle ABI"));
96f026fc
KB		 1180 break;
1181 }
6de918a6 1182
982e9687 1183 set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
6de918a6
DJ		 1184 set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver);
1185
0d0266c6 1186 set_gdbarch_software_single_step (gdbarch, mips_software_single_step);
b2756930
KB		 1187
1188 /* Enable TLS support. */
1189 set_gdbarch_fetch_tls_load_module_address (gdbarch,
1190 svr4_fetch_objfile_link_map);
19ed69dd
KB		 1191}
1192
2aa830e4 1193void
d1bacddc 1194_initialize_mips_linux_tdep (void)
2aa830e4 1195{
96f026fc
KB		 1196 const struct bfd_arch_info *arch_info;
1197
1198 register_addr_data =
030f20e1 1199 gdbarch_data_register_post_init (init_register_addr_data);
96f026fc
KB		 1200
1201 for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0);
1202 arch_info != NULL;
1203 arch_info = arch_info->next)
1204 {
295093a4
MS		 1205 gdbarch_register_osabi (bfd_arch_mips, arch_info->mach,
1206 GDB_OSABI_LINUX,
96f026fc
KB		 1207 mips_linux_init_abi);
1208 }
1209
00e32a35 1210 deprecated_add_core_fns (&regset_core_fns);
2aa830e4 1211}
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