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75c9abc6 | 1 | /* Target-dependent code for GNU/Linux on MIPS processors. |
a094c6fb | 2 | |
1d506c26 | 3 | Copyright (C) 2001-2024 Free Software Foundation, Inc. |
2aa830e4 DJ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
2aa830e4 DJ |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
2aa830e4 DJ |
19 | |
20 | #include "defs.h" | |
21 | #include "gdbcore.h" | |
22 | #include "target.h" | |
23 | #include "solib-svr4.h" | |
19ed69dd | 24 | #include "osabi.h" |
96f026fc | 25 | #include "mips-tdep.h" |
6de918a6 | 26 | #include "frame.h" |
2fdf551c | 27 | #include "regcache.h" |
5792a79b DJ |
28 | #include "trad-frame.h" |
29 | #include "tramp-frame.h" | |
e6bb342a | 30 | #include "gdbtypes.h" |
3e5d3a5a | 31 | #include "objfiles.h" |
5ea03926 | 32 | #include "solib.h" |
7d522c90 | 33 | #include "solist.h" |
982e9687 | 34 | #include "symtab.h" |
822b6570 | 35 | #include "target-descriptions.h" |
50e8a0d5 | 36 | #include "regset.h" |
d37eb719 | 37 | #include "mips-linux-tdep.h" |
db5f024e | 38 | #include "glibc-tdep.h" |
a5ee0f0c | 39 | #include "linux-tdep.h" |
385203ed | 40 | #include "xml-syscall.h" |
268a13a5 | 41 | #include "gdbsupport/gdb_signals.h" |
99d9c3b9 | 42 | #include "inferior.h" |
2aa830e4 | 43 | |
032bb6ea YQ |
44 | #include "features/mips-linux.c" |
45 | #include "features/mips-dsp-linux.c" | |
46 | #include "features/mips64-linux.c" | |
47 | #include "features/mips64-dsp-linux.c" | |
48 | ||
6cedf3bc | 49 | static solib_ops mips_svr4_so_ops; |
7d522c90 | 50 | |
eb14d406 SDJ |
51 | /* This enum represents the signals' numbers on the MIPS |
52 | architecture. It just contains the signal definitions which are | |
53 | different from the generic implementation. | |
54 | ||
55 | It is derived from the file <arch/mips/include/uapi/asm/signal.h>, | |
56 | from the Linux kernel tree. */ | |
57 | ||
58 | enum | |
59 | { | |
60 | MIPS_LINUX_SIGEMT = 7, | |
61 | MIPS_LINUX_SIGBUS = 10, | |
62 | MIPS_LINUX_SIGSYS = 12, | |
63 | MIPS_LINUX_SIGUSR1 = 16, | |
64 | MIPS_LINUX_SIGUSR2 = 17, | |
65 | MIPS_LINUX_SIGCHLD = 18, | |
66 | MIPS_LINUX_SIGCLD = MIPS_LINUX_SIGCHLD, | |
67 | MIPS_LINUX_SIGPWR = 19, | |
68 | MIPS_LINUX_SIGWINCH = 20, | |
69 | MIPS_LINUX_SIGURG = 21, | |
70 | MIPS_LINUX_SIGIO = 22, | |
71 | MIPS_LINUX_SIGPOLL = MIPS_LINUX_SIGIO, | |
72 | MIPS_LINUX_SIGSTOP = 23, | |
73 | MIPS_LINUX_SIGTSTP = 24, | |
74 | MIPS_LINUX_SIGCONT = 25, | |
75 | MIPS_LINUX_SIGTTIN = 26, | |
76 | MIPS_LINUX_SIGTTOU = 27, | |
77 | MIPS_LINUX_SIGVTALRM = 28, | |
78 | MIPS_LINUX_SIGPROF = 29, | |
79 | MIPS_LINUX_SIGXCPU = 30, | |
80 | MIPS_LINUX_SIGXFSZ = 31, | |
81 | ||
82 | MIPS_LINUX_SIGRTMIN = 32, | |
83 | MIPS_LINUX_SIGRT64 = 64, | |
84 | MIPS_LINUX_SIGRTMAX = 127, | |
85 | }; | |
86 | ||
2aa830e4 | 87 | /* Figure out where the longjmp will land. |
295093a4 MS |
88 | We expect the first arg to be a pointer to the jmp_buf structure |
89 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
90 | at. The pc is copied into PC. This routine returns 1 on | |
91 | success. */ | |
2aa830e4 | 92 | |
19ed69dd KB |
93 | #define MIPS_LINUX_JB_ELEMENT_SIZE 4 |
94 | #define MIPS_LINUX_JB_PC 0 | |
95 | ||
96 | static int | |
bd2b40ac | 97 | mips_linux_get_longjmp_target (frame_info_ptr frame, CORE_ADDR *pc) |
2aa830e4 DJ |
98 | { |
99 | CORE_ADDR jb_addr; | |
2eb4d78b | 100 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 101 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
e362b510 | 102 | gdb_byte buf[gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT]; |
2aa830e4 | 103 | |
60ade65d | 104 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
2aa830e4 | 105 | |
7d266584 MR |
106 | if (target_read_memory ((jb_addr |
107 | + MIPS_LINUX_JB_PC * MIPS_LINUX_JB_ELEMENT_SIZE), | |
2eb4d78b | 108 | buf, gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
2aa830e4 DJ |
109 | return 0; |
110 | ||
819844ad | 111 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
112 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
113 | byte_order); | |
2aa830e4 DJ |
114 | |
115 | return 1; | |
116 | } | |
117 | ||
4246e332 | 118 | /* Transform the bits comprising a 32-bit register to the right size |
23a6d369 AC |
119 | for regcache_raw_supply(). This is needed when mips_isa_regsize() |
120 | is 8. */ | |
96f026fc KB |
121 | |
122 | static void | |
28f5035f | 123 | supply_32bit_reg (struct regcache *regcache, int regnum, const void *addr) |
96f026fc | 124 | { |
b057297a | 125 | regcache->raw_supply_integer (regnum, (const gdb_byte *) addr, 4, true); |
96f026fc KB |
126 | } |
127 | ||
2aa830e4 DJ |
128 | /* Unpack an elf_gregset_t into GDB's register cache. */ |
129 | ||
d37eb719 | 130 | void |
28f5035f UW |
131 | mips_supply_gregset (struct regcache *regcache, |
132 | const mips_elf_gregset_t *gregsetp) | |
2aa830e4 DJ |
133 | { |
134 | int regi; | |
28f5035f | 135 | const mips_elf_greg_t *regp = *gregsetp; |
ac7936df | 136 | struct gdbarch *gdbarch = regcache->arch (); |
bf072999 | 137 | |
822b6570 | 138 | for (regi = EF_REG0 + 1; regi <= EF_REG31; regi++) |
28f5035f | 139 | supply_32bit_reg (regcache, regi - EF_REG0, regp + regi); |
2aa830e4 | 140 | |
2eb4d78b | 141 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
142 | supply_32bit_reg (regcache, MIPS_RESTART_REGNUM, regp + EF_REG0); |
143 | ||
2eb4d78b UW |
144 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->lo, regp + EF_LO); |
145 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->hi, regp + EF_HI); | |
56cea623 | 146 | |
2eb4d78b | 147 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 148 | regp + EF_CP0_EPC); |
2eb4d78b | 149 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
150 | regp + EF_CP0_BADVADDR); |
151 | supply_32bit_reg (regcache, MIPS_PS_REGNUM, regp + EF_CP0_STATUS); | |
2eb4d78b | 152 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 153 | regp + EF_CP0_CAUSE); |
2aa830e4 | 154 | |
1faeff08 | 155 | /* Fill the inaccessible zero register with zero. */ |
27bfc1d1 | 156 | regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); |
2aa830e4 DJ |
157 | } |
158 | ||
50e8a0d5 HZ |
159 | static void |
160 | mips_supply_gregset_wrapper (const struct regset *regset, | |
7d266584 MR |
161 | struct regcache *regcache, |
162 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 | 163 | { |
1528345d | 164 | gdb_assert (len >= sizeof (mips_elf_gregset_t)); |
50e8a0d5 HZ |
165 | |
166 | mips_supply_gregset (regcache, (const mips_elf_gregset_t *)gregs); | |
167 | } | |
168 | ||
2aa830e4 DJ |
169 | /* Pack our registers (or one register) into an elf_gregset_t. */ |
170 | ||
d37eb719 | 171 | void |
28f5035f UW |
172 | mips_fill_gregset (const struct regcache *regcache, |
173 | mips_elf_gregset_t *gregsetp, int regno) | |
2aa830e4 | 174 | { |
ac7936df | 175 | struct gdbarch *gdbarch = regcache->arch (); |
2aa830e4 | 176 | int regaddr, regi; |
d37eb719 | 177 | mips_elf_greg_t *regp = *gregsetp; |
96f026fc | 178 | void *dst; |
2aa830e4 DJ |
179 | |
180 | if (regno == -1) | |
181 | { | |
d37eb719 | 182 | memset (regp, 0, sizeof (mips_elf_gregset_t)); |
822b6570 | 183 | for (regi = 1; regi < 32; regi++) |
28f5035f | 184 | mips_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
185 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
186 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
187 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
188 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 189 | mips_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 190 | mips_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 191 | mips_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
2aa830e4 DJ |
192 | return; |
193 | } | |
194 | ||
822b6570 | 195 | if (regno > 0 && regno < 32) |
2aa830e4 | 196 | { |
2aa830e4 | 197 | dst = regp + regno + EF_REG0; |
34a79281 | 198 | regcache->raw_collect (regno, dst); |
2aa830e4 DJ |
199 | return; |
200 | } | |
201 | ||
2eb4d78b UW |
202 | if (regno == mips_regnum (gdbarch)->lo) |
203 | regaddr = EF_LO; | |
204 | else if (regno == mips_regnum (gdbarch)->hi) | |
56cea623 | 205 | regaddr = EF_HI; |
2eb4d78b | 206 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 207 | regaddr = EF_CP0_EPC; |
2eb4d78b | 208 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 209 | regaddr = EF_CP0_BADVADDR; |
24e05951 | 210 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 211 | regaddr = EF_CP0_STATUS; |
2eb4d78b | 212 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 213 | regaddr = EF_CP0_CAUSE; |
2eb4d78b | 214 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
215 | && regno == MIPS_RESTART_REGNUM) |
216 | regaddr = EF_REG0; | |
56cea623 AC |
217 | else |
218 | regaddr = -1; | |
2aa830e4 DJ |
219 | |
220 | if (regaddr != -1) | |
221 | { | |
2aa830e4 | 222 | dst = regp + regaddr; |
34a79281 | 223 | regcache->raw_collect (regno, dst); |
2aa830e4 DJ |
224 | } |
225 | } | |
226 | ||
50e8a0d5 HZ |
227 | static void |
228 | mips_fill_gregset_wrapper (const struct regset *regset, | |
229 | const struct regcache *regcache, | |
230 | int regnum, void *gregs, size_t len) | |
231 | { | |
1528345d | 232 | gdb_assert (len >= sizeof (mips_elf_gregset_t)); |
50e8a0d5 HZ |
233 | |
234 | mips_fill_gregset (regcache, (mips_elf_gregset_t *)gregs, regnum); | |
235 | } | |
236 | ||
96f026fc KB |
237 | /* Support for 64-bit ABIs. */ |
238 | ||
96f026fc | 239 | /* Figure out where the longjmp will land. |
295093a4 MS |
240 | We expect the first arg to be a pointer to the jmp_buf structure |
241 | from which we extract the pc (MIPS_LINUX_JB_PC) that we will land | |
242 | at. The pc is copied into PC. This routine returns 1 on | |
243 | success. */ | |
96f026fc KB |
244 | |
245 | /* Details about jmp_buf. */ | |
246 | ||
247 | #define MIPS64_LINUX_JB_PC 0 | |
248 | ||
249 | static int | |
bd2b40ac | 250 | mips64_linux_get_longjmp_target (frame_info_ptr frame, CORE_ADDR *pc) |
96f026fc KB |
251 | { |
252 | CORE_ADDR jb_addr; | |
2eb4d78b | 253 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 254 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
709476c3 SM |
255 | gdb_byte *buf |
256 | = (gdb_byte *) alloca (gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT); | |
2eb4d78b | 257 | int element_size = gdbarch_ptr_bit (gdbarch) == 32 ? 4 : 8; |
96f026fc | 258 | |
60ade65d | 259 | jb_addr = get_frame_register_unsigned (frame, MIPS_A0_REGNUM); |
96f026fc KB |
260 | |
261 | if (target_read_memory (jb_addr + MIPS64_LINUX_JB_PC * element_size, | |
819844ad | 262 | buf, |
2eb4d78b | 263 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT)) |
96f026fc KB |
264 | return 0; |
265 | ||
819844ad | 266 | *pc = extract_unsigned_integer (buf, |
e17a4113 UW |
267 | gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT, |
268 | byte_order); | |
96f026fc KB |
269 | |
270 | return 1; | |
271 | } | |
272 | ||
d37eb719 DJ |
273 | /* Register set support functions. These operate on standard 64-bit |
274 | regsets, but work whether the target is 32-bit or 64-bit. A 32-bit | |
275 | target will still use the 64-bit format for PTRACE_GETREGS. */ | |
276 | ||
277 | /* Supply a 64-bit register. */ | |
96f026fc | 278 | |
63807e1d | 279 | static void |
28f5035f UW |
280 | supply_64bit_reg (struct regcache *regcache, int regnum, |
281 | const gdb_byte *buf) | |
d37eb719 | 282 | { |
ac7936df | 283 | struct gdbarch *gdbarch = regcache->arch (); |
2eb4d78b UW |
284 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
285 | && register_size (gdbarch, regnum) == 4) | |
73e1c03f | 286 | regcache->raw_supply (regnum, buf + 4); |
d37eb719 | 287 | else |
73e1c03f | 288 | regcache->raw_supply (regnum, buf); |
d37eb719 DJ |
289 | } |
290 | ||
291 | /* Unpack a 64-bit elf_gregset_t into GDB's register cache. */ | |
292 | ||
293 | void | |
28f5035f UW |
294 | mips64_supply_gregset (struct regcache *regcache, |
295 | const mips64_elf_gregset_t *gregsetp) | |
96f026fc KB |
296 | { |
297 | int regi; | |
28f5035f | 298 | const mips64_elf_greg_t *regp = *gregsetp; |
ac7936df | 299 | struct gdbarch *gdbarch = regcache->arch (); |
96f026fc | 300 | |
822b6570 | 301 | for (regi = MIPS64_EF_REG0 + 1; regi <= MIPS64_EF_REG31; regi++) |
28f5035f | 302 | supply_64bit_reg (regcache, regi - MIPS64_EF_REG0, |
7d266584 | 303 | (const gdb_byte *) (regp + regi)); |
28f5035f | 304 | |
2eb4d78b | 305 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 | 306 | supply_64bit_reg (regcache, MIPS_RESTART_REGNUM, |
7d266584 | 307 | (const gdb_byte *) (regp + MIPS64_EF_REG0)); |
822b6570 | 308 | |
2eb4d78b | 309 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->lo, |
28f5035f | 310 | (const gdb_byte *) (regp + MIPS64_EF_LO)); |
2eb4d78b | 311 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->hi, |
28f5035f UW |
312 | (const gdb_byte *) (regp + MIPS64_EF_HI)); |
313 | ||
2eb4d78b | 314 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->pc, |
28f5035f | 315 | (const gdb_byte *) (regp + MIPS64_EF_CP0_EPC)); |
2eb4d78b | 316 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->badvaddr, |
28f5035f UW |
317 | (const gdb_byte *) (regp + MIPS64_EF_CP0_BADVADDR)); |
318 | supply_64bit_reg (regcache, MIPS_PS_REGNUM, | |
319 | (const gdb_byte *) (regp + MIPS64_EF_CP0_STATUS)); | |
2eb4d78b | 320 | supply_64bit_reg (regcache, mips_regnum (gdbarch)->cause, |
28f5035f | 321 | (const gdb_byte *) (regp + MIPS64_EF_CP0_CAUSE)); |
96f026fc | 322 | |
1faeff08 | 323 | /* Fill the inaccessible zero register with zero. */ |
27bfc1d1 | 324 | regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM); |
96f026fc KB |
325 | } |
326 | ||
50e8a0d5 HZ |
327 | static void |
328 | mips64_supply_gregset_wrapper (const struct regset *regset, | |
7d266584 MR |
329 | struct regcache *regcache, |
330 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 | 331 | { |
1528345d | 332 | gdb_assert (len >= sizeof (mips64_elf_gregset_t)); |
50e8a0d5 HZ |
333 | |
334 | mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *)gregs); | |
335 | } | |
336 | ||
d37eb719 | 337 | /* Pack our registers (or one register) into a 64-bit elf_gregset_t. */ |
96f026fc | 338 | |
d37eb719 | 339 | void |
28f5035f UW |
340 | mips64_fill_gregset (const struct regcache *regcache, |
341 | mips64_elf_gregset_t *gregsetp, int regno) | |
96f026fc | 342 | { |
ac7936df | 343 | struct gdbarch *gdbarch = regcache->arch (); |
96f026fc KB |
344 | int regaddr, regi; |
345 | mips64_elf_greg_t *regp = *gregsetp; | |
2ba93934 | 346 | void *dst; |
96f026fc KB |
347 | |
348 | if (regno == -1) | |
349 | { | |
350 | memset (regp, 0, sizeof (mips64_elf_gregset_t)); | |
822b6570 | 351 | for (regi = 1; regi < 32; regi++) |
7d266584 | 352 | mips64_fill_gregset (regcache, gregsetp, regi); |
2eb4d78b UW |
353 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->lo); |
354 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->hi); | |
355 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->pc); | |
025bb325 MS |
356 | mips64_fill_gregset (regcache, gregsetp, |
357 | mips_regnum (gdbarch)->badvaddr); | |
28f5035f | 358 | mips64_fill_gregset (regcache, gregsetp, MIPS_PS_REGNUM); |
2eb4d78b | 359 | mips64_fill_gregset (regcache, gregsetp, mips_regnum (gdbarch)->cause); |
822b6570 | 360 | mips64_fill_gregset (regcache, gregsetp, MIPS_RESTART_REGNUM); |
96f026fc KB |
361 | return; |
362 | } | |
363 | ||
822b6570 | 364 | if (regno > 0 && regno < 32) |
d37eb719 | 365 | regaddr = regno + MIPS64_EF_REG0; |
2eb4d78b | 366 | else if (regno == mips_regnum (gdbarch)->lo) |
56cea623 | 367 | regaddr = MIPS64_EF_LO; |
2eb4d78b | 368 | else if (regno == mips_regnum (gdbarch)->hi) |
56cea623 | 369 | regaddr = MIPS64_EF_HI; |
2eb4d78b | 370 | else if (regno == mips_regnum (gdbarch)->pc) |
56cea623 | 371 | regaddr = MIPS64_EF_CP0_EPC; |
2eb4d78b | 372 | else if (regno == mips_regnum (gdbarch)->badvaddr) |
56cea623 | 373 | regaddr = MIPS64_EF_CP0_BADVADDR; |
24e05951 | 374 | else if (regno == MIPS_PS_REGNUM) |
56cea623 | 375 | regaddr = MIPS64_EF_CP0_STATUS; |
2eb4d78b | 376 | else if (regno == mips_regnum (gdbarch)->cause) |
56cea623 | 377 | regaddr = MIPS64_EF_CP0_CAUSE; |
2eb4d78b | 378 | else if (mips_linux_restart_reg_p (gdbarch) |
822b6570 DJ |
379 | && regno == MIPS_RESTART_REGNUM) |
380 | regaddr = MIPS64_EF_REG0; | |
56cea623 AC |
381 | else |
382 | regaddr = -1; | |
96f026fc KB |
383 | |
384 | if (regaddr != -1) | |
385 | { | |
386 | dst = regp + regaddr; | |
b057297a | 387 | regcache->raw_collect_integer (regno, (gdb_byte *) dst, 8, true); |
96f026fc KB |
388 | } |
389 | } | |
390 | ||
50e8a0d5 HZ |
391 | static void |
392 | mips64_fill_gregset_wrapper (const struct regset *regset, | |
393 | const struct regcache *regcache, | |
394 | int regnum, void *gregs, size_t len) | |
395 | { | |
1528345d | 396 | gdb_assert (len >= sizeof (mips64_elf_gregset_t)); |
50e8a0d5 HZ |
397 | |
398 | mips64_fill_gregset (regcache, (mips64_elf_gregset_t *)gregs, regnum); | |
399 | } | |
400 | ||
d8dab6c3 MR |
401 | /* Likewise, unpack an elf_fpregset_t. Linux only uses even-numbered |
402 | FPR slots in the Status.FR=0 mode, storing even-odd FPR pairs as the | |
403 | SDC1 instruction would. When run on MIPS I architecture processors | |
404 | all FPR slots used to be used, unusually, holding the respective FPRs | |
405 | in the first 4 bytes, but that was corrected for consistency, with | |
406 | `linux-mips.org' (LMO) commit 42533948caac ("Major pile of FP emulator | |
407 | changes."), the fix corrected with LMO commit 849fa7a50dff ("R3k FPU | |
408 | ptrace() handling fixes."), and then broken and fixed over and over | |
409 | again, until last time fixed with commit 80cbfad79096 ("MIPS: Correct | |
410 | MIPS I FP context layout"). */ | |
96f026fc | 411 | |
d37eb719 | 412 | void |
28f5035f UW |
413 | mips64_supply_fpregset (struct regcache *regcache, |
414 | const mips64_elf_fpregset_t *fpregsetp) | |
96f026fc | 415 | { |
ac7936df | 416 | struct gdbarch *gdbarch = regcache->arch (); |
52f0bd74 | 417 | int regi; |
96f026fc | 418 | |
2eb4d78b | 419 | if (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)) == 4) |
d37eb719 DJ |
420 | for (regi = 0; regi < 32; regi++) |
421 | { | |
7d266584 MR |
422 | const gdb_byte *reg_ptr |
423 | = (const gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 424 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 425 | reg_ptr += 4; |
73e1c03f | 426 | regcache->raw_supply (gdbarch_fp0_regnum (gdbarch) + regi, reg_ptr); |
d37eb719 DJ |
427 | } |
428 | else | |
429 | for (regi = 0; regi < 32; regi++) | |
73e1c03f SM |
430 | regcache->raw_supply (gdbarch_fp0_regnum (gdbarch) + regi, |
431 | (const char *) (*fpregsetp + regi)); | |
d37eb719 | 432 | |
2eb4d78b | 433 | supply_32bit_reg (regcache, mips_regnum (gdbarch)->fp_control_status, |
7d266584 | 434 | (const gdb_byte *) (*fpregsetp + 32)); |
d37eb719 DJ |
435 | |
436 | /* The ABI doesn't tell us how to supply FCRIR, and core dumps don't | |
437 | include it - but the result of PTRACE_GETFPREGS does. The best we | |
438 | can do is to assume that its value is present. */ | |
28f5035f | 439 | supply_32bit_reg (regcache, |
2eb4d78b | 440 | mips_regnum (gdbarch)->fp_implementation_revision, |
7d266584 | 441 | (const gdb_byte *) (*fpregsetp + 32) + 4); |
96f026fc KB |
442 | } |
443 | ||
50e8a0d5 HZ |
444 | static void |
445 | mips64_supply_fpregset_wrapper (const struct regset *regset, | |
7d266584 MR |
446 | struct regcache *regcache, |
447 | int regnum, const void *gregs, size_t len) | |
50e8a0d5 | 448 | { |
1528345d | 449 | gdb_assert (len >= sizeof (mips64_elf_fpregset_t)); |
50e8a0d5 HZ |
450 | |
451 | mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *)gregs); | |
452 | } | |
453 | ||
96f026fc | 454 | /* Likewise, pack one or all floating point registers into an |
d8dab6c3 MR |
455 | elf_fpregset_t. See `mips_supply_fpregset' for an explanation |
456 | of the layout. */ | |
96f026fc | 457 | |
d37eb719 | 458 | void |
28f5035f UW |
459 | mips64_fill_fpregset (const struct regcache *regcache, |
460 | mips64_elf_fpregset_t *fpregsetp, int regno) | |
96f026fc | 461 | { |
ac7936df | 462 | struct gdbarch *gdbarch = regcache->arch (); |
d37eb719 | 463 | gdb_byte *to; |
96f026fc | 464 | |
2eb4d78b UW |
465 | if ((regno >= gdbarch_fp0_regnum (gdbarch)) |
466 | && (regno < gdbarch_fp0_regnum (gdbarch) + 32)) | |
96f026fc | 467 | { |
2eb4d78b | 468 | if (register_size (gdbarch, regno) == 4) |
d37eb719 | 469 | { |
2eb4d78b | 470 | int regi = regno - gdbarch_fp0_regnum (gdbarch); |
d37eb719 DJ |
471 | |
472 | to = (gdb_byte *) (*fpregsetp + (regi & ~1)); | |
2eb4d78b | 473 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (regi & 1)) |
d37eb719 | 474 | to += 4; |
34a79281 | 475 | regcache->raw_collect (regno, to); |
d37eb719 DJ |
476 | } |
477 | else | |
478 | { | |
025bb325 MS |
479 | to = (gdb_byte *) (*fpregsetp + regno |
480 | - gdbarch_fp0_regnum (gdbarch)); | |
34a79281 | 481 | regcache->raw_collect (regno, to); |
d37eb719 | 482 | } |
96f026fc | 483 | } |
2eb4d78b | 484 | else if (regno == mips_regnum (gdbarch)->fp_control_status) |
96f026fc | 485 | { |
d37eb719 | 486 | to = (gdb_byte *) (*fpregsetp + 32); |
b057297a | 487 | regcache->raw_collect_integer (regno, to, 4, true); |
d37eb719 | 488 | } |
2eb4d78b | 489 | else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) |
d37eb719 | 490 | { |
d37eb719 | 491 | to = (gdb_byte *) (*fpregsetp + 32) + 4; |
b057297a | 492 | regcache->raw_collect_integer (regno, to, 4, true); |
96f026fc KB |
493 | } |
494 | else if (regno == -1) | |
495 | { | |
496 | int regi; | |
497 | ||
498 | for (regi = 0; regi < 32; regi++) | |
3e8c568d | 499 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 500 | gdbarch_fp0_regnum (gdbarch) + regi); |
28f5035f | 501 | mips64_fill_fpregset (regcache, fpregsetp, |
2eb4d78b | 502 | mips_regnum (gdbarch)->fp_control_status); |
28f5035f | 503 | mips64_fill_fpregset (regcache, fpregsetp, |
7d266584 | 504 | mips_regnum (gdbarch)->fp_implementation_revision); |
96f026fc KB |
505 | } |
506 | } | |
507 | ||
50e8a0d5 HZ |
508 | static void |
509 | mips64_fill_fpregset_wrapper (const struct regset *regset, | |
510 | const struct regcache *regcache, | |
511 | int regnum, void *gregs, size_t len) | |
512 | { | |
1528345d | 513 | gdb_assert (len >= sizeof (mips64_elf_fpregset_t)); |
96f026fc | 514 | |
50e8a0d5 HZ |
515 | mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *)gregs, regnum); |
516 | } | |
2aa830e4 | 517 | |
b7195f27 AA |
518 | static const struct regset mips_linux_gregset = |
519 | { | |
520 | NULL, mips_supply_gregset_wrapper, mips_fill_gregset_wrapper | |
521 | }; | |
522 | ||
523 | static const struct regset mips64_linux_gregset = | |
524 | { | |
525 | NULL, mips64_supply_gregset_wrapper, mips64_fill_gregset_wrapper | |
526 | }; | |
527 | ||
b7195f27 AA |
528 | static const struct regset mips64_linux_fpregset = |
529 | { | |
530 | NULL, mips64_supply_fpregset_wrapper, mips64_fill_fpregset_wrapper | |
531 | }; | |
532 | ||
d4036235 AA |
533 | static void |
534 | mips_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
535 | iterate_over_regset_sections_cb *cb, | |
536 | void *cb_data, | |
537 | const struct regcache *regcache) | |
2aa830e4 | 538 | { |
d4036235 | 539 | if (register_size (gdbarch, MIPS_ZERO_REGNUM) == 4) |
2aa830e4 | 540 | { |
a616bb94 AH |
541 | cb (".reg", sizeof (mips_elf_gregset_t), sizeof (mips_elf_gregset_t), |
542 | &mips_linux_gregset, NULL, cb_data); | |
543 | cb (".reg2", sizeof (mips64_elf_fpregset_t), | |
544 | sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset, | |
d4036235 | 545 | NULL, cb_data); |
2aa830e4 | 546 | } |
d4036235 | 547 | else |
2aa830e4 | 548 | { |
a616bb94 AH |
549 | cb (".reg", sizeof (mips64_elf_gregset_t), sizeof (mips64_elf_gregset_t), |
550 | &mips64_linux_gregset, NULL, cb_data); | |
551 | cb (".reg2", sizeof (mips64_elf_fpregset_t), | |
552 | sizeof (mips64_elf_fpregset_t), &mips64_linux_fpregset, | |
d4036235 | 553 | NULL, cb_data); |
2aa830e4 | 554 | } |
50e8a0d5 | 555 | } |
2aa830e4 | 556 | |
4eb0ad19 DJ |
557 | static const struct target_desc * |
558 | mips_linux_core_read_description (struct gdbarch *gdbarch, | |
559 | struct target_ops *target, | |
560 | bfd *abfd) | |
561 | { | |
562 | asection *section = bfd_get_section_by_name (abfd, ".reg"); | |
563 | if (! section) | |
564 | return NULL; | |
565 | ||
fd361982 | 566 | switch (bfd_section_size (section)) |
4eb0ad19 DJ |
567 | { |
568 | case sizeof (mips_elf_gregset_t): | |
569 | return mips_tdesc_gp32; | |
570 | ||
571 | case sizeof (mips64_elf_gregset_t): | |
572 | return mips_tdesc_gp64; | |
573 | ||
574 | default: | |
575 | return NULL; | |
576 | } | |
577 | } | |
578 | ||
96f026fc | 579 | |
295093a4 | 580 | /* Check the code at PC for a dynamic linker lazy resolution stub. |
3e5d3a5a MR |
581 | GNU ld for MIPS has put lazy resolution stubs into a ".MIPS.stubs" |
582 | section uniformly since version 2.15. If the pc is in that section, | |
583 | then we are in such a stub. Before that ".stub" was used in 32-bit | |
584 | ELF binaries, however we do not bother checking for that since we | |
585 | have never had and that case should be extremely rare these days. | |
586 | Instead we pattern-match on the code generated by GNU ld. They look | |
587 | like this: | |
6de918a6 DJ |
588 | |
589 | lw t9,0x8010(gp) | |
590 | addu t7,ra | |
591 | jalr t9,ra | |
592 | addiu t8,zero,INDEX | |
593 | ||
3e5d3a5a MR |
594 | (with the appropriate doubleword instructions for N64). As any lazy |
595 | resolution stubs in microMIPS binaries will always be in a | |
596 | ".MIPS.stubs" section we only ever verify standard MIPS patterns. */ | |
6de918a6 DJ |
597 | |
598 | static int | |
3e5d3a5a | 599 | mips_linux_in_dynsym_stub (CORE_ADDR pc) |
6de918a6 | 600 | { |
e362b510 | 601 | gdb_byte buf[28], *p; |
6de918a6 | 602 | ULONGEST insn, insn1; |
99d9c3b9 SM |
603 | int n64 = (mips_abi (current_inferior ()->arch ()) == MIPS_ABI_N64); |
604 | bfd_endian byte_order = gdbarch_byte_order (current_inferior ()->arch ()); | |
6de918a6 | 605 | |
3e5d3a5a MR |
606 | if (in_mips_stubs_section (pc)) |
607 | return 1; | |
608 | ||
6de918a6 DJ |
609 | read_memory (pc - 12, buf, 28); |
610 | ||
611 | if (n64) | |
612 | { | |
613 | /* ld t9,0x8010(gp) */ | |
614 | insn1 = 0xdf998010; | |
615 | } | |
616 | else | |
617 | { | |
618 | /* lw t9,0x8010(gp) */ | |
619 | insn1 = 0x8f998010; | |
620 | } | |
621 | ||
622 | p = buf + 12; | |
623 | while (p >= buf) | |
624 | { | |
e17a4113 | 625 | insn = extract_unsigned_integer (p, 4, byte_order); |
6de918a6 DJ |
626 | if (insn == insn1) |
627 | break; | |
628 | p -= 4; | |
629 | } | |
630 | if (p < buf) | |
631 | return 0; | |
632 | ||
e17a4113 | 633 | insn = extract_unsigned_integer (p + 4, 4, byte_order); |
6de918a6 DJ |
634 | if (n64) |
635 | { | |
93084fcd | 636 | /* 'daddu t7,ra' or 'or t7, ra, zero'*/ |
59f7bd8d | 637 | if (insn != 0x03e0782d && insn != 0x03e07825) |
6de918a6 DJ |
638 | return 0; |
639 | } | |
640 | else | |
641 | { | |
93084fcd | 642 | /* 'addu t7,ra' or 'or t7, ra, zero'*/ |
59f7bd8d | 643 | if (insn != 0x03e07821 && insn != 0x03e07825) |
6de918a6 DJ |
644 | return 0; |
645 | } | |
295093a4 | 646 | |
e17a4113 | 647 | insn = extract_unsigned_integer (p + 8, 4, byte_order); |
6de918a6 DJ |
648 | /* jalr t9,ra */ |
649 | if (insn != 0x0320f809) | |
650 | return 0; | |
651 | ||
e17a4113 | 652 | insn = extract_unsigned_integer (p + 12, 4, byte_order); |
6de918a6 DJ |
653 | if (n64) |
654 | { | |
655 | /* daddiu t8,zero,0 */ | |
656 | if ((insn & 0xffff0000) != 0x64180000) | |
657 | return 0; | |
658 | } | |
659 | else | |
660 | { | |
661 | /* addiu t8,zero,0 */ | |
662 | if ((insn & 0xffff0000) != 0x24180000) | |
663 | return 0; | |
664 | } | |
665 | ||
3e5d3a5a | 666 | return 1; |
6de918a6 DJ |
667 | } |
668 | ||
295093a4 | 669 | /* Return non-zero iff PC belongs to the dynamic linker resolution |
db5f024e | 670 | code, a PLT entry, or a lazy binding stub. */ |
6de918a6 | 671 | |
7d522c90 | 672 | static int |
6de918a6 DJ |
673 | mips_linux_in_dynsym_resolve_code (CORE_ADDR pc) |
674 | { | |
295093a4 | 675 | /* Check whether PC is in the dynamic linker. This also checks |
db5f024e | 676 | whether it is in the .plt section, used by non-PIC executables. */ |
7d522c90 | 677 | if (svr4_in_dynsym_resolve_code (pc)) |
6de918a6 DJ |
678 | return 1; |
679 | ||
3e5d3a5a MR |
680 | /* Likewise for the stubs. They live in the .MIPS.stubs section these |
681 | days, so we check if the PC is within, than fall back to a pattern | |
682 | match. */ | |
683 | if (mips_linux_in_dynsym_stub (pc)) | |
6de918a6 DJ |
684 | return 1; |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
689 | /* See the comments for SKIP_SOLIB_RESOLVER at the top of infrun.c, | |
690 | and glibc_skip_solib_resolver in glibc-tdep.c. The normal glibc | |
691 | implementation of this triggers at "fixup" from the same objfile as | |
c4c5b7ba | 692 | "_dl_runtime_resolve"; MIPS GNU/Linux can trigger at |
db5f024e DJ |
693 | "__dl_runtime_resolve" directly. An unresolved lazy binding |
694 | stub will point to _dl_runtime_resolve, which will first call | |
c4c5b7ba AC |
695 | __dl_runtime_resolve, and then pass control to the resolved |
696 | function. */ | |
6de918a6 DJ |
697 | |
698 | static CORE_ADDR | |
699 | mips_linux_skip_resolver (struct gdbarch *gdbarch, CORE_ADDR pc) | |
700 | { | |
3b7344d5 | 701 | struct bound_minimal_symbol resolver; |
6de918a6 DJ |
702 | |
703 | resolver = lookup_minimal_symbol ("__dl_runtime_resolve", NULL, NULL); | |
704 | ||
4aeddc50 | 705 | if (resolver.minsym && resolver.value_address () == pc) |
c7ce8faa | 706 | return frame_unwind_caller_pc (get_current_frame ()); |
6de918a6 | 707 | |
db5f024e | 708 | return glibc_skip_solib_resolver (gdbarch, pc); |
295093a4 | 709 | } |
6de918a6 | 710 | |
5792a79b DJ |
711 | /* Signal trampoline support. There are four supported layouts for a |
712 | signal frame: o32 sigframe, o32 rt_sigframe, n32 rt_sigframe, and | |
713 | n64 rt_sigframe. We handle them all independently; not the most | |
714 | efficient way, but simplest. First, declare all the unwinders. */ | |
715 | ||
716 | static void mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
bd2b40ac | 717 | frame_info_ptr this_frame, |
5792a79b DJ |
718 | struct trad_frame_cache *this_cache, |
719 | CORE_ADDR func); | |
720 | ||
721 | static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
bd2b40ac | 722 | frame_info_ptr this_frame, |
5792a79b DJ |
723 | struct trad_frame_cache *this_cache, |
724 | CORE_ADDR func); | |
725 | ||
858339f2 | 726 | static int mips_linux_sigframe_validate (const struct tramp_frame *self, |
bd2b40ac | 727 | frame_info_ptr this_frame, |
858339f2 MR |
728 | CORE_ADDR *pc); |
729 | ||
730 | static int micromips_linux_sigframe_validate (const struct tramp_frame *self, | |
bd2b40ac | 731 | frame_info_ptr this_frame, |
858339f2 MR |
732 | CORE_ADDR *pc); |
733 | ||
5792a79b DJ |
734 | #define MIPS_NR_LINUX 4000 |
735 | #define MIPS_NR_N64_LINUX 5000 | |
736 | #define MIPS_NR_N32_LINUX 6000 | |
737 | ||
738 | #define MIPS_NR_sigreturn MIPS_NR_LINUX + 119 | |
739 | #define MIPS_NR_rt_sigreturn MIPS_NR_LINUX + 193 | |
740 | #define MIPS_NR_N64_rt_sigreturn MIPS_NR_N64_LINUX + 211 | |
741 | #define MIPS_NR_N32_rt_sigreturn MIPS_NR_N32_LINUX + 211 | |
742 | ||
743 | #define MIPS_INST_LI_V0_SIGRETURN 0x24020000 + MIPS_NR_sigreturn | |
744 | #define MIPS_INST_LI_V0_RT_SIGRETURN 0x24020000 + MIPS_NR_rt_sigreturn | |
745 | #define MIPS_INST_LI_V0_N64_RT_SIGRETURN 0x24020000 + MIPS_NR_N64_rt_sigreturn | |
746 | #define MIPS_INST_LI_V0_N32_RT_SIGRETURN 0x24020000 + MIPS_NR_N32_rt_sigreturn | |
747 | #define MIPS_INST_SYSCALL 0x0000000c | |
748 | ||
858339f2 MR |
749 | #define MICROMIPS_INST_LI_V0 0x3040 |
750 | #define MICROMIPS_INST_POOL32A 0x0000 | |
751 | #define MICROMIPS_INST_SYSCALL 0x8b7c | |
752 | ||
2cd8546d AC |
753 | static const struct tramp_frame mips_linux_o32_sigframe = { |
754 | SIGTRAMP_FRAME, | |
5792a79b | 755 | 4, |
2cd8546d | 756 | { |
7bc02706 TT |
757 | { MIPS_INST_LI_V0_SIGRETURN, ULONGEST_MAX }, |
758 | { MIPS_INST_SYSCALL, ULONGEST_MAX }, | |
759 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
2cd8546d | 760 | }, |
858339f2 MR |
761 | mips_linux_o32_sigframe_init, |
762 | mips_linux_sigframe_validate | |
5792a79b DJ |
763 | }; |
764 | ||
2cd8546d AC |
765 | static const struct tramp_frame mips_linux_o32_rt_sigframe = { |
766 | SIGTRAMP_FRAME, | |
5792a79b | 767 | 4, |
2cd8546d | 768 | { |
7bc02706 TT |
769 | { MIPS_INST_LI_V0_RT_SIGRETURN, ULONGEST_MAX }, |
770 | { MIPS_INST_SYSCALL, ULONGEST_MAX }, | |
771 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } }, | |
858339f2 MR |
772 | mips_linux_o32_sigframe_init, |
773 | mips_linux_sigframe_validate | |
5792a79b DJ |
774 | }; |
775 | ||
2cd8546d AC |
776 | static const struct tramp_frame mips_linux_n32_rt_sigframe = { |
777 | SIGTRAMP_FRAME, | |
5792a79b | 778 | 4, |
2cd8546d | 779 | { |
7bc02706 TT |
780 | { MIPS_INST_LI_V0_N32_RT_SIGRETURN, ULONGEST_MAX }, |
781 | { MIPS_INST_SYSCALL, ULONGEST_MAX }, | |
782 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
2cd8546d | 783 | }, |
858339f2 MR |
784 | mips_linux_n32n64_sigframe_init, |
785 | mips_linux_sigframe_validate | |
5792a79b DJ |
786 | }; |
787 | ||
2cd8546d AC |
788 | static const struct tramp_frame mips_linux_n64_rt_sigframe = { |
789 | SIGTRAMP_FRAME, | |
5792a79b | 790 | 4, |
fcbd8a5c | 791 | { |
7bc02706 TT |
792 | { MIPS_INST_LI_V0_N64_RT_SIGRETURN, ULONGEST_MAX }, |
793 | { MIPS_INST_SYSCALL, ULONGEST_MAX }, | |
794 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
fcbd8a5c | 795 | }, |
858339f2 MR |
796 | mips_linux_n32n64_sigframe_init, |
797 | mips_linux_sigframe_validate | |
798 | }; | |
799 | ||
800 | static const struct tramp_frame micromips_linux_o32_sigframe = { | |
801 | SIGTRAMP_FRAME, | |
802 | 2, | |
803 | { | |
7bc02706 TT |
804 | { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, |
805 | { MIPS_NR_sigreturn, ULONGEST_MAX }, | |
806 | { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, | |
807 | { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, | |
808 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
858339f2 MR |
809 | }, |
810 | mips_linux_o32_sigframe_init, | |
811 | micromips_linux_sigframe_validate | |
812 | }; | |
813 | ||
814 | static const struct tramp_frame micromips_linux_o32_rt_sigframe = { | |
815 | SIGTRAMP_FRAME, | |
816 | 2, | |
817 | { | |
7bc02706 TT |
818 | { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, |
819 | { MIPS_NR_rt_sigreturn, ULONGEST_MAX }, | |
820 | { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, | |
821 | { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, | |
822 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
858339f2 MR |
823 | }, |
824 | mips_linux_o32_sigframe_init, | |
825 | micromips_linux_sigframe_validate | |
826 | }; | |
827 | ||
828 | static const struct tramp_frame micromips_linux_n32_rt_sigframe = { | |
829 | SIGTRAMP_FRAME, | |
830 | 2, | |
831 | { | |
7bc02706 TT |
832 | { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, |
833 | { MIPS_NR_N32_rt_sigreturn, ULONGEST_MAX }, | |
834 | { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, | |
835 | { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, | |
836 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
858339f2 MR |
837 | }, |
838 | mips_linux_n32n64_sigframe_init, | |
839 | micromips_linux_sigframe_validate | |
840 | }; | |
841 | ||
842 | static const struct tramp_frame micromips_linux_n64_rt_sigframe = { | |
843 | SIGTRAMP_FRAME, | |
844 | 2, | |
845 | { | |
7bc02706 TT |
846 | { MICROMIPS_INST_LI_V0, ULONGEST_MAX }, |
847 | { MIPS_NR_N64_rt_sigreturn, ULONGEST_MAX }, | |
848 | { MICROMIPS_INST_POOL32A, ULONGEST_MAX }, | |
849 | { MICROMIPS_INST_SYSCALL, ULONGEST_MAX }, | |
850 | { TRAMP_SENTINEL_INSN, ULONGEST_MAX } | |
858339f2 MR |
851 | }, |
852 | mips_linux_n32n64_sigframe_init, | |
853 | micromips_linux_sigframe_validate | |
5792a79b DJ |
854 | }; |
855 | ||
5792a79b DJ |
856 | /* The unwinder for o32 signal frames. The legacy structures look |
857 | like this: | |
858 | ||
859 | struct sigframe { | |
860 | u32 sf_ass[4]; [argument save space for o32] | |
eb195664 | 861 | u32 sf_code[2]; [signal trampoline or fill] |
5792a79b DJ |
862 | struct sigcontext sf_sc; |
863 | sigset_t sf_mask; | |
864 | }; | |
865 | ||
d0e64392 MR |
866 | Pre-2.6.12 sigcontext: |
867 | ||
5792a79b | 868 | struct sigcontext { |
dda83cd7 SM |
869 | unsigned int sc_regmask; [Unused] |
870 | unsigned int sc_status; | |
871 | unsigned long long sc_pc; | |
872 | unsigned long long sc_regs[32]; | |
873 | unsigned long long sc_fpregs[32]; | |
874 | unsigned int sc_ownedfp; | |
875 | unsigned int sc_fpc_csr; | |
876 | unsigned int sc_fpc_eir; [Unused] | |
877 | unsigned int sc_used_math; | |
878 | unsigned int sc_ssflags; [Unused] | |
5792a79b | 879 | [Alignment hole of four bytes] |
dda83cd7 SM |
880 | unsigned long long sc_mdhi; |
881 | unsigned long long sc_mdlo; | |
5792a79b | 882 | |
dda83cd7 SM |
883 | unsigned int sc_cause; [Unused] |
884 | unsigned int sc_badvaddr; [Unused] | |
5792a79b | 885 | |
dda83cd7 | 886 | unsigned long sc_sigset[4]; [kernel's sigset_t] |
5792a79b DJ |
887 | }; |
888 | ||
d0e64392 MR |
889 | Post-2.6.12 sigcontext (SmartMIPS/DSP support added): |
890 | ||
891 | struct sigcontext { | |
dda83cd7 SM |
892 | unsigned int sc_regmask; [Unused] |
893 | unsigned int sc_status; [Unused] | |
894 | unsigned long long sc_pc; | |
895 | unsigned long long sc_regs[32]; | |
896 | unsigned long long sc_fpregs[32]; | |
897 | unsigned int sc_acx; | |
898 | unsigned int sc_fpc_csr; | |
899 | unsigned int sc_fpc_eir; [Unused] | |
900 | unsigned int sc_used_math; | |
901 | unsigned int sc_dsp; | |
d0e64392 | 902 | [Alignment hole of four bytes] |
dda83cd7 SM |
903 | unsigned long long sc_mdhi; |
904 | unsigned long long sc_mdlo; | |
905 | unsigned long sc_hi1; | |
906 | unsigned long sc_lo1; | |
907 | unsigned long sc_hi2; | |
908 | unsigned long sc_lo2; | |
909 | unsigned long sc_hi3; | |
910 | unsigned long sc_lo3; | |
d0e64392 MR |
911 | }; |
912 | ||
5792a79b DJ |
913 | The RT signal frames look like this: |
914 | ||
915 | struct rt_sigframe { | |
916 | u32 rs_ass[4]; [argument save space for o32] | |
eb195664 | 917 | u32 rs_code[2] [signal trampoline or fill] |
5792a79b DJ |
918 | struct siginfo rs_info; |
919 | struct ucontext rs_uc; | |
920 | }; | |
921 | ||
922 | struct ucontext { | |
923 | unsigned long uc_flags; | |
924 | struct ucontext *uc_link; | |
925 | stack_t uc_stack; | |
926 | [Alignment hole of four bytes] | |
927 | struct sigcontext uc_mcontext; | |
928 | sigset_t uc_sigmask; | |
929 | }; */ | |
5792a79b | 930 | |
5792a79b DJ |
931 | #define SIGFRAME_SIGCONTEXT_OFFSET (6 * 4) |
932 | ||
933 | #define RTSIGFRAME_SIGINFO_SIZE 128 | |
934 | #define STACK_T_SIZE (3 * 4) | |
935 | #define UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + STACK_T_SIZE + 4) | |
936 | #define RTSIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
937 | + RTSIGFRAME_SIGINFO_SIZE \ | |
938 | + UCONTEXT_SIGCONTEXT_OFFSET) | |
939 | ||
940 | #define SIGCONTEXT_PC (1 * 8) | |
941 | #define SIGCONTEXT_REGS (2 * 8) | |
942 | #define SIGCONTEXT_FPREGS (34 * 8) | |
943 | #define SIGCONTEXT_FPCSR (66 * 8 + 4) | |
d0e64392 | 944 | #define SIGCONTEXT_DSPCTL (68 * 8 + 0) |
5792a79b DJ |
945 | #define SIGCONTEXT_HI (69 * 8) |
946 | #define SIGCONTEXT_LO (70 * 8) | |
947 | #define SIGCONTEXT_CAUSE (71 * 8 + 0) | |
948 | #define SIGCONTEXT_BADVADDR (71 * 8 + 4) | |
d0e64392 MR |
949 | #define SIGCONTEXT_HI1 (71 * 8 + 0) |
950 | #define SIGCONTEXT_LO1 (71 * 8 + 4) | |
951 | #define SIGCONTEXT_HI2 (72 * 8 + 0) | |
952 | #define SIGCONTEXT_LO2 (72 * 8 + 4) | |
953 | #define SIGCONTEXT_HI3 (73 * 8 + 0) | |
954 | #define SIGCONTEXT_LO3 (73 * 8 + 4) | |
5792a79b DJ |
955 | |
956 | #define SIGCONTEXT_REG_SIZE 8 | |
957 | ||
958 | static void | |
959 | mips_linux_o32_sigframe_init (const struct tramp_frame *self, | |
bd2b40ac | 960 | frame_info_ptr this_frame, |
5792a79b DJ |
961 | struct trad_frame_cache *this_cache, |
962 | CORE_ADDR func) | |
963 | { | |
b8a22b94 | 964 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 965 | int ireg; |
eb195664 DD |
966 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
967 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 968 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
37c4d197 | 969 | CORE_ADDR regs_base; |
5792a79b | 970 | |
858339f2 MR |
971 | if (self == &mips_linux_o32_sigframe |
972 | || self == µmips_linux_o32_sigframe) | |
eb195664 | 973 | sigcontext_base = frame_sp + SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 974 | else |
eb195664 | 975 | sigcontext_base = frame_sp + RTSIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 MS |
976 | |
977 | /* I'm not proud of this hack. Eventually we will have the | |
978 | infrastructure to indicate the size of saved registers on a | |
979 | per-frame basis, but right now we don't; the kernel saves eight | |
37c4d197 DJ |
980 | bytes but we only want four. Use regs_base to access any |
981 | 64-bit fields. */ | |
2eb4d78b | 982 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
37c4d197 DJ |
983 | regs_base = sigcontext_base + 4; |
984 | else | |
985 | regs_base = sigcontext_base; | |
5792a79b | 986 | |
2eb4d78b | 987 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
988 | trad_frame_set_reg_addr (this_cache, |
989 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 990 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 991 | regs_base + SIGCONTEXT_REGS); |
5792a79b DJ |
992 | |
993 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 994 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
995 | (ireg + MIPS_ZERO_REGNUM |
996 | + gdbarch_num_regs (gdbarch)), | |
997 | (regs_base + SIGCONTEXT_REGS | |
998 | + ireg * SIGCONTEXT_REG_SIZE)); | |
5792a79b DJ |
999 | |
1000 | for (ireg = 0; ireg < 32; ireg++) | |
2eb4d78b | 1001 | if ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) != (ireg & 1)) |
f57d151a | 1002 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1003 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1004 | (sigcontext_base + SIGCONTEXT_FPREGS + 4 | |
1005 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); | |
37c4d197 | 1006 | else |
f57d151a | 1007 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1008 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1009 | (sigcontext_base + SIGCONTEXT_FPREGS | |
1010 | + (ireg & ~1) * SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1011 | |
f57d151a | 1012 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1013 | regs->pc + gdbarch_num_regs (gdbarch), |
37c4d197 | 1014 | regs_base + SIGCONTEXT_PC); |
5792a79b | 1015 | |
295093a4 | 1016 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1017 | (regs->fp_control_status |
1018 | + gdbarch_num_regs (gdbarch)), | |
5792a79b | 1019 | sigcontext_base + SIGCONTEXT_FPCSR); |
d0e64392 MR |
1020 | |
1021 | if (regs->dspctl != -1) | |
1022 | trad_frame_set_reg_addr (this_cache, | |
1023 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1024 | sigcontext_base + SIGCONTEXT_DSPCTL); | |
1025 | ||
f57d151a | 1026 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1027 | regs->hi + gdbarch_num_regs (gdbarch), |
37c4d197 | 1028 | regs_base + SIGCONTEXT_HI); |
f57d151a | 1029 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1030 | regs->lo + gdbarch_num_regs (gdbarch), |
37c4d197 | 1031 | regs_base + SIGCONTEXT_LO); |
d0e64392 MR |
1032 | |
1033 | if (regs->dspacc != -1) | |
1034 | { | |
1035 | trad_frame_set_reg_addr (this_cache, | |
1036 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1037 | sigcontext_base + SIGCONTEXT_HI1); | |
1038 | trad_frame_set_reg_addr (this_cache, | |
1039 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1040 | sigcontext_base + SIGCONTEXT_LO1); | |
1041 | trad_frame_set_reg_addr (this_cache, | |
1042 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1043 | sigcontext_base + SIGCONTEXT_HI2); | |
1044 | trad_frame_set_reg_addr (this_cache, | |
1045 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1046 | sigcontext_base + SIGCONTEXT_LO2); | |
1047 | trad_frame_set_reg_addr (this_cache, | |
1048 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1049 | sigcontext_base + SIGCONTEXT_HI3); | |
1050 | trad_frame_set_reg_addr (this_cache, | |
1051 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1052 | sigcontext_base + SIGCONTEXT_LO3); | |
1053 | } | |
1054 | else | |
1055 | { | |
1056 | trad_frame_set_reg_addr (this_cache, | |
1057 | regs->cause + gdbarch_num_regs (gdbarch), | |
1058 | sigcontext_base + SIGCONTEXT_CAUSE); | |
1059 | trad_frame_set_reg_addr (this_cache, | |
1060 | regs->badvaddr + gdbarch_num_regs (gdbarch), | |
1061 | sigcontext_base + SIGCONTEXT_BADVADDR); | |
1062 | } | |
5792a79b DJ |
1063 | |
1064 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ | |
eb195664 | 1065 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1066 | } |
1067 | ||
5792a79b DJ |
1068 | /* For N32/N64 things look different. There is no non-rt signal frame. |
1069 | ||
1070 | struct rt_sigframe_n32 { | |
1071 | u32 rs_ass[4]; [ argument save space for o32 ] | |
eb195664 | 1072 | u32 rs_code[2]; [ signal trampoline or fill ] |
5792a79b DJ |
1073 | struct siginfo rs_info; |
1074 | struct ucontextn32 rs_uc; | |
1075 | }; | |
1076 | ||
1077 | struct ucontextn32 { | |
1078 | u32 uc_flags; | |
1079 | s32 uc_link; | |
1080 | stack32_t uc_stack; | |
1081 | struct sigcontext uc_mcontext; | |
1082 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1083 | }; | |
295093a4 | 1084 | |
e741f4d4 | 1085 | struct rt_sigframe { |
5792a79b DJ |
1086 | u32 rs_ass[4]; [ argument save space for o32 ] |
1087 | u32 rs_code[2]; [ signal trampoline ] | |
1088 | struct siginfo rs_info; | |
1089 | struct ucontext rs_uc; | |
1090 | }; | |
1091 | ||
1092 | struct ucontext { | |
1093 | unsigned long uc_flags; | |
1094 | struct ucontext *uc_link; | |
1095 | stack_t uc_stack; | |
1096 | struct sigcontext uc_mcontext; | |
1097 | sigset_t uc_sigmask; [ mask last for extensibility ] | |
1098 | }; | |
1099 | ||
1100 | And the sigcontext is different (this is for both n32 and n64): | |
1101 | ||
1102 | struct sigcontext { | |
1103 | unsigned long long sc_regs[32]; | |
1104 | unsigned long long sc_fpregs[32]; | |
1105 | unsigned long long sc_mdhi; | |
e741f4d4 DJ |
1106 | unsigned long long sc_hi1; |
1107 | unsigned long long sc_hi2; | |
1108 | unsigned long long sc_hi3; | |
5792a79b | 1109 | unsigned long long sc_mdlo; |
e741f4d4 DJ |
1110 | unsigned long long sc_lo1; |
1111 | unsigned long long sc_lo2; | |
1112 | unsigned long long sc_lo3; | |
5792a79b | 1113 | unsigned long long sc_pc; |
5792a79b | 1114 | unsigned int sc_fpc_csr; |
5792a79b | 1115 | unsigned int sc_used_math; |
e741f4d4 DJ |
1116 | unsigned int sc_dsp; |
1117 | unsigned int sc_reserved; | |
1118 | }; | |
1119 | ||
1120 | That is the post-2.6.12 definition of the 64-bit sigcontext; before | |
1121 | then, there were no hi1-hi3 or lo1-lo3. Cause and badvaddr were | |
1122 | included too. */ | |
5792a79b DJ |
1123 | |
1124 | #define N32_STACK_T_SIZE STACK_T_SIZE | |
1125 | #define N64_STACK_T_SIZE (2 * 8 + 4) | |
1126 | #define N32_UCONTEXT_SIGCONTEXT_OFFSET (2 * 4 + N32_STACK_T_SIZE + 4) | |
1127 | #define N64_UCONTEXT_SIGCONTEXT_OFFSET (2 * 8 + N64_STACK_T_SIZE + 4) | |
1128 | #define N32_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1129 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1130 | + N32_UCONTEXT_SIGCONTEXT_OFFSET) | |
1131 | #define N64_SIGFRAME_SIGCONTEXT_OFFSET (SIGFRAME_SIGCONTEXT_OFFSET \ | |
1132 | + RTSIGFRAME_SIGINFO_SIZE \ | |
1133 | + N64_UCONTEXT_SIGCONTEXT_OFFSET) | |
1134 | ||
1135 | #define N64_SIGCONTEXT_REGS (0 * 8) | |
1136 | #define N64_SIGCONTEXT_FPREGS (32 * 8) | |
1137 | #define N64_SIGCONTEXT_HI (64 * 8) | |
d0e64392 MR |
1138 | #define N64_SIGCONTEXT_HI1 (65 * 8) |
1139 | #define N64_SIGCONTEXT_HI2 (66 * 8) | |
1140 | #define N64_SIGCONTEXT_HI3 (67 * 8) | |
e741f4d4 | 1141 | #define N64_SIGCONTEXT_LO (68 * 8) |
d0e64392 MR |
1142 | #define N64_SIGCONTEXT_LO1 (69 * 8) |
1143 | #define N64_SIGCONTEXT_LO2 (70 * 8) | |
1144 | #define N64_SIGCONTEXT_LO3 (71 * 8) | |
e741f4d4 | 1145 | #define N64_SIGCONTEXT_PC (72 * 8) |
d0e64392 MR |
1146 | #define N64_SIGCONTEXT_FPCSR (73 * 8 + 0) |
1147 | #define N64_SIGCONTEXT_DSPCTL (74 * 8 + 0) | |
5792a79b DJ |
1148 | |
1149 | #define N64_SIGCONTEXT_REG_SIZE 8 | |
295093a4 | 1150 | |
5792a79b DJ |
1151 | static void |
1152 | mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, | |
bd2b40ac | 1153 | frame_info_ptr this_frame, |
5792a79b DJ |
1154 | struct trad_frame_cache *this_cache, |
1155 | CORE_ADDR func) | |
1156 | { | |
b8a22b94 | 1157 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
22e048c9 | 1158 | int ireg; |
eb195664 DD |
1159 | CORE_ADDR frame_sp = get_frame_sp (this_frame); |
1160 | CORE_ADDR sigcontext_base; | |
2eb4d78b | 1161 | const struct mips_regnum *regs = mips_regnum (gdbarch); |
5792a79b | 1162 | |
858339f2 MR |
1163 | if (self == &mips_linux_n32_rt_sigframe |
1164 | || self == µmips_linux_n32_rt_sigframe) | |
eb195664 | 1165 | sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET; |
5792a79b | 1166 | else |
eb195664 | 1167 | sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET; |
295093a4 | 1168 | |
2eb4d78b | 1169 | if (mips_linux_restart_reg_p (gdbarch)) |
822b6570 DJ |
1170 | trad_frame_set_reg_addr (this_cache, |
1171 | (MIPS_RESTART_REGNUM | |
2eb4d78b | 1172 | + gdbarch_num_regs (gdbarch)), |
822b6570 | 1173 | sigcontext_base + N64_SIGCONTEXT_REGS); |
5792a79b DJ |
1174 | |
1175 | for (ireg = 1; ireg < 32; ireg++) | |
295093a4 | 1176 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1177 | (ireg + MIPS_ZERO_REGNUM |
1178 | + gdbarch_num_regs (gdbarch)), | |
1179 | (sigcontext_base + N64_SIGCONTEXT_REGS | |
1180 | + ireg * N64_SIGCONTEXT_REG_SIZE)); | |
5792a79b DJ |
1181 | |
1182 | for (ireg = 0; ireg < 32; ireg++) | |
f57d151a | 1183 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1184 | ireg + regs->fp0 + gdbarch_num_regs (gdbarch), |
1185 | (sigcontext_base + N64_SIGCONTEXT_FPREGS | |
1186 | + ireg * N64_SIGCONTEXT_REG_SIZE)); | |
5792a79b | 1187 | |
f57d151a | 1188 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1189 | regs->pc + gdbarch_num_regs (gdbarch), |
5792a79b DJ |
1190 | sigcontext_base + N64_SIGCONTEXT_PC); |
1191 | ||
295093a4 | 1192 | trad_frame_set_reg_addr (this_cache, |
7d266584 MR |
1193 | (regs->fp_control_status |
1194 | + gdbarch_num_regs (gdbarch)), | |
5792a79b | 1195 | sigcontext_base + N64_SIGCONTEXT_FPCSR); |
d0e64392 | 1196 | |
f57d151a | 1197 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1198 | regs->hi + gdbarch_num_regs (gdbarch), |
5792a79b | 1199 | sigcontext_base + N64_SIGCONTEXT_HI); |
f57d151a | 1200 | trad_frame_set_reg_addr (this_cache, |
2eb4d78b | 1201 | regs->lo + gdbarch_num_regs (gdbarch), |
5792a79b | 1202 | sigcontext_base + N64_SIGCONTEXT_LO); |
5792a79b | 1203 | |
d0e64392 MR |
1204 | if (regs->dspacc != -1) |
1205 | { | |
1206 | trad_frame_set_reg_addr (this_cache, | |
1207 | regs->dspacc + 0 + gdbarch_num_regs (gdbarch), | |
1208 | sigcontext_base + N64_SIGCONTEXT_HI1); | |
1209 | trad_frame_set_reg_addr (this_cache, | |
1210 | regs->dspacc + 1 + gdbarch_num_regs (gdbarch), | |
1211 | sigcontext_base + N64_SIGCONTEXT_LO1); | |
1212 | trad_frame_set_reg_addr (this_cache, | |
1213 | regs->dspacc + 2 + gdbarch_num_regs (gdbarch), | |
1214 | sigcontext_base + N64_SIGCONTEXT_HI2); | |
1215 | trad_frame_set_reg_addr (this_cache, | |
1216 | regs->dspacc + 3 + gdbarch_num_regs (gdbarch), | |
1217 | sigcontext_base + N64_SIGCONTEXT_LO2); | |
1218 | trad_frame_set_reg_addr (this_cache, | |
1219 | regs->dspacc + 4 + gdbarch_num_regs (gdbarch), | |
1220 | sigcontext_base + N64_SIGCONTEXT_HI3); | |
1221 | trad_frame_set_reg_addr (this_cache, | |
1222 | regs->dspacc + 5 + gdbarch_num_regs (gdbarch), | |
1223 | sigcontext_base + N64_SIGCONTEXT_LO3); | |
1224 | } | |
1225 | if (regs->dspctl != -1) | |
1226 | trad_frame_set_reg_addr (this_cache, | |
1227 | regs->dspctl + gdbarch_num_regs (gdbarch), | |
1228 | sigcontext_base + N64_SIGCONTEXT_DSPCTL); | |
1229 | ||
5792a79b | 1230 | /* Choice of the bottom of the sigframe is somewhat arbitrary. */ |
eb195664 | 1231 | trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); |
5792a79b DJ |
1232 | } |
1233 | ||
858339f2 MR |
1234 | /* Implement struct tramp_frame's "validate" method for standard MIPS code. */ |
1235 | ||
1236 | static int | |
1237 | mips_linux_sigframe_validate (const struct tramp_frame *self, | |
bd2b40ac | 1238 | frame_info_ptr this_frame, |
858339f2 MR |
1239 | CORE_ADDR *pc) |
1240 | { | |
1241 | return mips_pc_is_mips (*pc); | |
1242 | } | |
1243 | ||
1244 | /* Implement struct tramp_frame's "validate" method for microMIPS code. */ | |
1245 | ||
1246 | static int | |
1247 | micromips_linux_sigframe_validate (const struct tramp_frame *self, | |
bd2b40ac | 1248 | frame_info_ptr this_frame, |
858339f2 MR |
1249 | CORE_ADDR *pc) |
1250 | { | |
3e29f34a MR |
1251 | if (mips_pc_is_micromips (get_frame_arch (this_frame), *pc)) |
1252 | { | |
1253 | *pc = mips_unmake_compact_addr (*pc); | |
1254 | return 1; | |
1255 | } | |
1256 | else | |
1257 | return 0; | |
858339f2 MR |
1258 | } |
1259 | ||
5a439849 MR |
1260 | /* Implement the "write_pc" gdbarch method. */ |
1261 | ||
822b6570 | 1262 | static void |
61a1198a | 1263 | mips_linux_write_pc (struct regcache *regcache, CORE_ADDR pc) |
822b6570 | 1264 | { |
ac7936df | 1265 | struct gdbarch *gdbarch = regcache->arch (); |
5a439849 MR |
1266 | |
1267 | mips_write_pc (regcache, pc); | |
822b6570 DJ |
1268 | |
1269 | /* Clear the syscall restart flag. */ | |
2eb4d78b | 1270 | if (mips_linux_restart_reg_p (gdbarch)) |
61a1198a | 1271 | regcache_cooked_write_unsigned (regcache, MIPS_RESTART_REGNUM, 0); |
822b6570 DJ |
1272 | } |
1273 | ||
1274 | /* Return 1 if MIPS_RESTART_REGNUM is usable. */ | |
1275 | ||
1276 | int | |
1277 | mips_linux_restart_reg_p (struct gdbarch *gdbarch) | |
1278 | { | |
1279 | /* If we do not have a target description with registers, then | |
1280 | MIPS_RESTART_REGNUM will not be included in the register set. */ | |
1281 | if (!tdesc_has_registers (gdbarch_target_desc (gdbarch))) | |
1282 | return 0; | |
1283 | ||
1284 | /* If we do, then MIPS_RESTART_REGNUM is safe to check; it will | |
1285 | either be GPR-sized or missing. */ | |
1286 | return register_size (gdbarch, MIPS_RESTART_REGNUM) > 0; | |
1287 | } | |
9f62d0e2 | 1288 | |
e38d4e1a DJ |
1289 | /* When FRAME is at a syscall instruction, return the PC of the next |
1290 | instruction to be executed. */ | |
1291 | ||
63807e1d | 1292 | static CORE_ADDR |
bd2b40ac | 1293 | mips_linux_syscall_next_pc (frame_info_ptr frame) |
e38d4e1a DJ |
1294 | { |
1295 | CORE_ADDR pc = get_frame_pc (frame); | |
1296 | ULONGEST v0 = get_frame_register_unsigned (frame, MIPS_V0_REGNUM); | |
1297 | ||
1298 | /* If we are about to make a sigreturn syscall, use the unwinder to | |
1299 | decode the signal frame. */ | |
1300 | if (v0 == MIPS_NR_sigreturn | |
1301 | || v0 == MIPS_NR_rt_sigreturn | |
1302 | || v0 == MIPS_NR_N64_rt_sigreturn | |
1303 | || v0 == MIPS_NR_N32_rt_sigreturn) | |
c7ce8faa | 1304 | return frame_unwind_caller_pc (get_current_frame ()); |
e38d4e1a DJ |
1305 | |
1306 | return pc + 4; | |
1307 | } | |
1308 | ||
385203ed DD |
1309 | /* Return the current system call's number present in the |
1310 | v0 register. When the function fails, it returns -1. */ | |
1311 | ||
1312 | static LONGEST | |
1313 | mips_linux_get_syscall_number (struct gdbarch *gdbarch, | |
00431a78 | 1314 | thread_info *thread) |
385203ed | 1315 | { |
00431a78 | 1316 | struct regcache *regcache = get_thread_regcache (thread); |
08106042 | 1317 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
385203ed DD |
1318 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1319 | int regsize = register_size (gdbarch, MIPS_V0_REGNUM); | |
1320 | /* The content of a register */ | |
1321 | gdb_byte buf[8]; | |
1322 | /* The result */ | |
1323 | LONGEST ret; | |
1324 | ||
1325 | /* Make sure we're in a known ABI */ | |
1326 | gdb_assert (tdep->mips_abi == MIPS_ABI_O32 | |
1327 | || tdep->mips_abi == MIPS_ABI_N32 | |
1328 | || tdep->mips_abi == MIPS_ABI_N64); | |
1329 | ||
1330 | gdb_assert (regsize <= sizeof (buf)); | |
1331 | ||
1332 | /* Getting the system call number from the register. | |
1333 | syscall number is in v0 or $2. */ | |
dca08e1f | 1334 | regcache->cooked_read (MIPS_V0_REGNUM, buf); |
385203ed DD |
1335 | |
1336 | ret = extract_signed_integer (buf, regsize, byte_order); | |
1337 | ||
1338 | return ret; | |
1339 | } | |
1340 | ||
eb14d406 SDJ |
1341 | /* Implementation of `gdbarch_gdb_signal_to_target', as defined in |
1342 | gdbarch.h. */ | |
1343 | ||
1344 | static int | |
1345 | mips_gdb_signal_to_target (struct gdbarch *gdbarch, | |
1346 | enum gdb_signal signal) | |
1347 | { | |
1348 | switch (signal) | |
1349 | { | |
1350 | case GDB_SIGNAL_EMT: | |
1351 | return MIPS_LINUX_SIGEMT; | |
1352 | ||
1353 | case GDB_SIGNAL_BUS: | |
1354 | return MIPS_LINUX_SIGBUS; | |
1355 | ||
1356 | case GDB_SIGNAL_SYS: | |
1357 | return MIPS_LINUX_SIGSYS; | |
1358 | ||
1359 | case GDB_SIGNAL_USR1: | |
1360 | return MIPS_LINUX_SIGUSR1; | |
1361 | ||
1362 | case GDB_SIGNAL_USR2: | |
1363 | return MIPS_LINUX_SIGUSR2; | |
1364 | ||
1365 | case GDB_SIGNAL_CHLD: | |
1366 | return MIPS_LINUX_SIGCHLD; | |
1367 | ||
1368 | case GDB_SIGNAL_PWR: | |
1369 | return MIPS_LINUX_SIGPWR; | |
1370 | ||
1371 | case GDB_SIGNAL_WINCH: | |
1372 | return MIPS_LINUX_SIGWINCH; | |
1373 | ||
1374 | case GDB_SIGNAL_URG: | |
1375 | return MIPS_LINUX_SIGURG; | |
1376 | ||
1377 | case GDB_SIGNAL_IO: | |
1378 | return MIPS_LINUX_SIGIO; | |
1379 | ||
1380 | case GDB_SIGNAL_POLL: | |
1381 | return MIPS_LINUX_SIGPOLL; | |
1382 | ||
1383 | case GDB_SIGNAL_STOP: | |
1384 | return MIPS_LINUX_SIGSTOP; | |
1385 | ||
1386 | case GDB_SIGNAL_TSTP: | |
1387 | return MIPS_LINUX_SIGTSTP; | |
1388 | ||
1389 | case GDB_SIGNAL_CONT: | |
1390 | return MIPS_LINUX_SIGCONT; | |
1391 | ||
1392 | case GDB_SIGNAL_TTIN: | |
1393 | return MIPS_LINUX_SIGTTIN; | |
1394 | ||
1395 | case GDB_SIGNAL_TTOU: | |
1396 | return MIPS_LINUX_SIGTTOU; | |
1397 | ||
1398 | case GDB_SIGNAL_VTALRM: | |
1399 | return MIPS_LINUX_SIGVTALRM; | |
1400 | ||
1401 | case GDB_SIGNAL_PROF: | |
1402 | return MIPS_LINUX_SIGPROF; | |
1403 | ||
1404 | case GDB_SIGNAL_XCPU: | |
1405 | return MIPS_LINUX_SIGXCPU; | |
1406 | ||
1407 | case GDB_SIGNAL_XFSZ: | |
1408 | return MIPS_LINUX_SIGXFSZ; | |
1409 | ||
1410 | /* GDB_SIGNAL_REALTIME_32 is not continuous in <gdb/signals.def>, | |
1411 | therefore we have to handle it here. */ | |
1412 | case GDB_SIGNAL_REALTIME_32: | |
1413 | return MIPS_LINUX_SIGRTMIN; | |
1414 | } | |
1415 | ||
1416 | if (signal >= GDB_SIGNAL_REALTIME_33 | |
1417 | && signal <= GDB_SIGNAL_REALTIME_63) | |
1418 | { | |
1419 | int offset = signal - GDB_SIGNAL_REALTIME_33; | |
1420 | ||
1421 | return MIPS_LINUX_SIGRTMIN + 1 + offset; | |
1422 | } | |
1423 | else if (signal >= GDB_SIGNAL_REALTIME_64 | |
1424 | && signal <= GDB_SIGNAL_REALTIME_127) | |
1425 | { | |
1426 | int offset = signal - GDB_SIGNAL_REALTIME_64; | |
1427 | ||
1428 | return MIPS_LINUX_SIGRT64 + offset; | |
1429 | } | |
1430 | ||
1431 | return linux_gdb_signal_to_target (gdbarch, signal); | |
1432 | } | |
1433 | ||
7d266584 | 1434 | /* Translate signals based on MIPS signal values. |
268a13a5 | 1435 | Adapted from gdb/gdbsupport/signals.c. */ |
232b8704 ME |
1436 | |
1437 | static enum gdb_signal | |
eb14d406 | 1438 | mips_gdb_signal_from_target (struct gdbarch *gdbarch, int signal) |
232b8704 | 1439 | { |
eb14d406 | 1440 | switch (signal) |
232b8704 | 1441 | { |
eb14d406 | 1442 | case MIPS_LINUX_SIGEMT: |
232b8704 | 1443 | return GDB_SIGNAL_EMT; |
eb14d406 SDJ |
1444 | |
1445 | case MIPS_LINUX_SIGBUS: | |
232b8704 | 1446 | return GDB_SIGNAL_BUS; |
eb14d406 SDJ |
1447 | |
1448 | case MIPS_LINUX_SIGSYS: | |
232b8704 | 1449 | return GDB_SIGNAL_SYS; |
eb14d406 SDJ |
1450 | |
1451 | case MIPS_LINUX_SIGUSR1: | |
232b8704 | 1452 | return GDB_SIGNAL_USR1; |
eb14d406 SDJ |
1453 | |
1454 | case MIPS_LINUX_SIGUSR2: | |
232b8704 | 1455 | return GDB_SIGNAL_USR2; |
eb14d406 SDJ |
1456 | |
1457 | case MIPS_LINUX_SIGCHLD: | |
232b8704 | 1458 | return GDB_SIGNAL_CHLD; |
eb14d406 SDJ |
1459 | |
1460 | case MIPS_LINUX_SIGPWR: | |
232b8704 | 1461 | return GDB_SIGNAL_PWR; |
eb14d406 SDJ |
1462 | |
1463 | case MIPS_LINUX_SIGWINCH: | |
232b8704 | 1464 | return GDB_SIGNAL_WINCH; |
eb14d406 SDJ |
1465 | |
1466 | case MIPS_LINUX_SIGURG: | |
232b8704 | 1467 | return GDB_SIGNAL_URG; |
eb14d406 SDJ |
1468 | |
1469 | /* No way to differentiate between SIGIO and SIGPOLL. | |
1470 | Therefore, we just handle the first one. */ | |
1471 | case MIPS_LINUX_SIGIO: | |
1472 | return GDB_SIGNAL_IO; | |
1473 | ||
1474 | case MIPS_LINUX_SIGSTOP: | |
232b8704 | 1475 | return GDB_SIGNAL_STOP; |
eb14d406 SDJ |
1476 | |
1477 | case MIPS_LINUX_SIGTSTP: | |
232b8704 | 1478 | return GDB_SIGNAL_TSTP; |
eb14d406 SDJ |
1479 | |
1480 | case MIPS_LINUX_SIGCONT: | |
232b8704 | 1481 | return GDB_SIGNAL_CONT; |
eb14d406 SDJ |
1482 | |
1483 | case MIPS_LINUX_SIGTTIN: | |
232b8704 | 1484 | return GDB_SIGNAL_TTIN; |
eb14d406 SDJ |
1485 | |
1486 | case MIPS_LINUX_SIGTTOU: | |
232b8704 | 1487 | return GDB_SIGNAL_TTOU; |
eb14d406 SDJ |
1488 | |
1489 | case MIPS_LINUX_SIGVTALRM: | |
232b8704 | 1490 | return GDB_SIGNAL_VTALRM; |
eb14d406 SDJ |
1491 | |
1492 | case MIPS_LINUX_SIGPROF: | |
232b8704 | 1493 | return GDB_SIGNAL_PROF; |
eb14d406 SDJ |
1494 | |
1495 | case MIPS_LINUX_SIGXCPU: | |
232b8704 | 1496 | return GDB_SIGNAL_XCPU; |
eb14d406 SDJ |
1497 | |
1498 | case MIPS_LINUX_SIGXFSZ: | |
232b8704 | 1499 | return GDB_SIGNAL_XFSZ; |
eb14d406 | 1500 | } |
232b8704 | 1501 | |
eb14d406 | 1502 | if (signal >= MIPS_LINUX_SIGRTMIN && signal <= MIPS_LINUX_SIGRTMAX) |
232b8704 ME |
1503 | { |
1504 | /* GDB_SIGNAL_REALTIME values are not contiguous, map parts of | |
dda83cd7 | 1505 | the MIPS block to the respective GDB_SIGNAL_REALTIME blocks. */ |
eb14d406 SDJ |
1506 | int offset = signal - MIPS_LINUX_SIGRTMIN; |
1507 | ||
1508 | if (offset == 0) | |
232b8704 | 1509 | return GDB_SIGNAL_REALTIME_32; |
eb14d406 SDJ |
1510 | else if (offset < 32) |
1511 | return (enum gdb_signal) (offset - 1 | |
1512 | + (int) GDB_SIGNAL_REALTIME_33); | |
232b8704 | 1513 | else |
eb14d406 SDJ |
1514 | return (enum gdb_signal) (offset - 32 |
1515 | + (int) GDB_SIGNAL_REALTIME_64); | |
232b8704 ME |
1516 | } |
1517 | ||
eb14d406 | 1518 | return linux_gdb_signal_from_target (gdbarch, signal); |
232b8704 ME |
1519 | } |
1520 | ||
5792a79b DJ |
1521 | /* Initialize one of the GNU/Linux OS ABIs. */ |
1522 | ||
19ed69dd | 1523 | static void |
295093a4 MS |
1524 | mips_linux_init_abi (struct gdbarch_info info, |
1525 | struct gdbarch *gdbarch) | |
19ed69dd | 1526 | { |
08106042 | 1527 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
96f026fc | 1528 | enum mips_abi abi = mips_abi (gdbarch); |
0dba2a6c | 1529 | struct tdesc_arch_data *tdesc_data = info.tdesc_data; |
96f026fc | 1530 | |
480af54c | 1531 | linux_init_abi (info, gdbarch, 0); |
a5ee0f0c | 1532 | |
385203ed DD |
1533 | /* Get the syscall number from the arch's register. */ |
1534 | set_gdbarch_get_syscall_number (gdbarch, mips_linux_get_syscall_number); | |
1535 | ||
96f026fc KB |
1536 | switch (abi) |
1537 | { | |
1538 | case MIPS_ABI_O32: | |
1539 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1540 | mips_linux_get_longjmp_target); |
96f026fc | 1541 | set_solib_svr4_fetch_link_map_offsets |
c0154a4a | 1542 | (gdbarch, linux_ilp32_fetch_link_map_offsets); |
858339f2 MR |
1543 | tramp_frame_prepend_unwinder (gdbarch, µmips_linux_o32_sigframe); |
1544 | tramp_frame_prepend_unwinder (gdbarch, | |
1545 | µmips_linux_o32_rt_sigframe); | |
fb2be677 AC |
1546 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_sigframe); |
1547 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_o32_rt_sigframe); | |
458c8db8 | 1548 | set_xml_syscall_file_name (gdbarch, "syscalls/mips-o32-linux.xml"); |
96f026fc KB |
1549 | break; |
1550 | case MIPS_ABI_N32: | |
1551 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1552 | mips_linux_get_longjmp_target); |
96f026fc | 1553 | set_solib_svr4_fetch_link_map_offsets |
c0154a4a | 1554 | (gdbarch, linux_ilp32_fetch_link_map_offsets); |
d05f6826 | 1555 | set_gdbarch_long_double_bit (gdbarch, 128); |
552f1157 | 1556 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_quad); |
858339f2 MR |
1557 | tramp_frame_prepend_unwinder (gdbarch, |
1558 | µmips_linux_n32_rt_sigframe); | |
fb2be677 | 1559 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n32_rt_sigframe); |
458c8db8 | 1560 | set_xml_syscall_file_name (gdbarch, "syscalls/mips-n32-linux.xml"); |
96f026fc KB |
1561 | break; |
1562 | case MIPS_ABI_N64: | |
1563 | set_gdbarch_get_longjmp_target (gdbarch, | |
7d266584 | 1564 | mips64_linux_get_longjmp_target); |
96f026fc | 1565 | set_solib_svr4_fetch_link_map_offsets |
c0154a4a | 1566 | (gdbarch, linux_lp64_fetch_link_map_offsets); |
d05f6826 | 1567 | set_gdbarch_long_double_bit (gdbarch, 128); |
552f1157 | 1568 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_quad); |
858339f2 MR |
1569 | tramp_frame_prepend_unwinder (gdbarch, |
1570 | µmips_linux_n64_rt_sigframe); | |
fb2be677 | 1571 | tramp_frame_prepend_unwinder (gdbarch, &mips_linux_n64_rt_sigframe); |
458c8db8 | 1572 | set_xml_syscall_file_name (gdbarch, "syscalls/mips-n64-linux.xml"); |
96f026fc KB |
1573 | break; |
1574 | default: | |
96f026fc KB |
1575 | break; |
1576 | } | |
6de918a6 DJ |
1577 | |
1578 | set_gdbarch_skip_solib_resolver (gdbarch, mips_linux_skip_resolver); | |
1579 | ||
0d0266c6 | 1580 | set_gdbarch_software_single_step (gdbarch, mips_software_single_step); |
b2756930 KB |
1581 | |
1582 | /* Enable TLS support. */ | |
1583 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
7d266584 | 1584 | svr4_fetch_objfile_link_map); |
7d522c90 DJ |
1585 | |
1586 | /* Initialize this lazily, to avoid an initialization order | |
1587 | dependency on solib-svr4.c's _initialize routine. */ | |
1588 | if (mips_svr4_so_ops.in_dynsym_resolve_code == NULL) | |
1589 | { | |
1590 | mips_svr4_so_ops = svr4_so_ops; | |
1591 | mips_svr4_so_ops.in_dynsym_resolve_code | |
1592 | = mips_linux_in_dynsym_resolve_code; | |
1593 | } | |
9e468e95 | 1594 | set_gdbarch_so_ops (gdbarch, &mips_svr4_so_ops); |
822b6570 DJ |
1595 | |
1596 | set_gdbarch_write_pc (gdbarch, mips_linux_write_pc); | |
1597 | ||
4eb0ad19 DJ |
1598 | set_gdbarch_core_read_description (gdbarch, |
1599 | mips_linux_core_read_description); | |
1600 | ||
d4036235 AA |
1601 | set_gdbarch_iterate_over_regset_sections |
1602 | (gdbarch, mips_linux_iterate_over_regset_sections); | |
50e8a0d5 | 1603 | |
232b8704 ME |
1604 | set_gdbarch_gdb_signal_from_target (gdbarch, |
1605 | mips_gdb_signal_from_target); | |
1606 | ||
eb14d406 SDJ |
1607 | set_gdbarch_gdb_signal_to_target (gdbarch, |
1608 | mips_gdb_signal_to_target); | |
1609 | ||
e38d4e1a DJ |
1610 | tdep->syscall_next_pc = mips_linux_syscall_next_pc; |
1611 | ||
822b6570 DJ |
1612 | if (tdesc_data) |
1613 | { | |
1614 | const struct tdesc_feature *feature; | |
1615 | ||
1616 | /* If we have target-described registers, then we can safely | |
1617 | reserve a number for MIPS_RESTART_REGNUM (whether it is | |
1618 | described or not). */ | |
1619 | gdb_assert (gdbarch_num_regs (gdbarch) <= MIPS_RESTART_REGNUM); | |
1620 | set_gdbarch_num_regs (gdbarch, MIPS_RESTART_REGNUM + 1); | |
cf233303 | 1621 | set_gdbarch_num_pseudo_regs (gdbarch, MIPS_RESTART_REGNUM + 1); |
822b6570 DJ |
1622 | |
1623 | /* If it's present, then assign it to the reserved number. */ | |
1624 | feature = tdesc_find_feature (info.target_desc, | |
1625 | "org.gnu.gdb.mips.linux"); | |
1626 | if (feature != NULL) | |
1627 | tdesc_numbered_register (feature, tdesc_data, MIPS_RESTART_REGNUM, | |
1628 | "restart"); | |
1629 | } | |
19ed69dd KB |
1630 | } |
1631 | ||
6c265988 | 1632 | void _initialize_mips_linux_tdep (); |
2aa830e4 | 1633 | void |
6c265988 | 1634 | _initialize_mips_linux_tdep () |
2aa830e4 | 1635 | { |
96f026fc KB |
1636 | const struct bfd_arch_info *arch_info; |
1637 | ||
96f026fc KB |
1638 | for (arch_info = bfd_lookup_arch (bfd_arch_mips, 0); |
1639 | arch_info != NULL; | |
1640 | arch_info = arch_info->next) | |
1641 | { | |
295093a4 MS |
1642 | gdbarch_register_osabi (bfd_arch_mips, arch_info->mach, |
1643 | GDB_OSABI_LINUX, | |
96f026fc KB |
1644 | mips_linux_init_abi); |
1645 | } | |
032bb6ea YQ |
1646 | |
1647 | /* Initialize the standard target descriptions. */ | |
1648 | initialize_tdesc_mips_linux (); | |
1649 | initialize_tdesc_mips_dsp_linux (); | |
1650 | initialize_tdesc_mips64_linux (); | |
1651 | initialize_tdesc_mips64_dsp_linux (); | |
2aa830e4 | 1652 | } |