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c906108c | 1 | /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
bf64bfd6 | 2 | |
213516ef | 3 | Copyright (C) 1988-2023 Free Software Foundation, Inc. |
bf64bfd6 | 4 | |
c906108c SS |
5 | Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 | and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | |
7 | ||
c5aa993b | 8 | This file is part of GDB. |
c906108c | 9 | |
c5aa993b JM |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 12 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 13 | (at your option) any later version. |
c906108c | 14 | |
c5aa993b JM |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
c906108c | 19 | |
c5aa993b | 20 | You should have received a copy of the GNU General Public License |
a9762ec7 | 21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
22 | |
23 | #include "defs.h" | |
c906108c SS |
24 | #include "frame.h" |
25 | #include "inferior.h" | |
26 | #include "symtab.h" | |
27 | #include "value.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "language.h" | |
30 | #include "gdbcore.h" | |
31 | #include "symfile.h" | |
32 | #include "objfiles.h" | |
33 | #include "gdbtypes.h" | |
34 | #include "target.h" | |
28d069e6 | 35 | #include "arch-utils.h" |
4e052eda | 36 | #include "regcache.h" |
70f80edf | 37 | #include "osabi.h" |
d1973055 | 38 | #include "mips-tdep.h" |
fe898f56 | 39 | #include "block.h" |
a4b8ebc8 | 40 | #include "reggroups.h" |
c906108c | 41 | #include "opcode/mips.h" |
c2d11a7d JM |
42 | #include "elf/mips.h" |
43 | #include "elf-bfd.h" | |
2475bac3 | 44 | #include "symcat.h" |
a4b8ebc8 | 45 | #include "sim-regno.h" |
a89aa300 | 46 | #include "dis-asm.h" |
e47ad6c0 | 47 | #include "disasm.h" |
edfae063 AC |
48 | #include "frame-unwind.h" |
49 | #include "frame-base.h" | |
50 | #include "trad-frame.h" | |
7d9b040b | 51 | #include "infcall.h" |
29709017 DJ |
52 | #include "remote.h" |
53 | #include "target-descriptions.h" | |
82ca8957 | 54 | #include "dwarf2/frame.h" |
f8b73d13 | 55 | #include "user-regs.h" |
79a45b7d | 56 | #include "valprint.h" |
175ff332 | 57 | #include "ax.h" |
f69fdf9b | 58 | #include "target-float.h" |
325fac50 | 59 | #include <algorithm> |
c906108c | 60 | |
5bbcb741 | 61 | static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
e0f7ec59 | 62 | |
ab50adb6 MR |
63 | static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, |
64 | ULONGEST inst); | |
65 | static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32); | |
66 | static int mips16_instruction_has_delay_slot (unsigned short inst, | |
67 | int mustbe32); | |
68 | ||
69 | static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
70 | CORE_ADDR addr); | |
71 | static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
72 | CORE_ADDR addr, int mustbe32); | |
73 | static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
74 | CORE_ADDR addr, int mustbe32); | |
4cc0665f | 75 | |
1bab7383 | 76 | static void mips_print_float_info (struct gdbarch *, struct ui_file *, |
9efe17a3 | 77 | frame_info_ptr, const char *); |
1bab7383 | 78 | |
24e05951 | 79 | /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
dd824b04 DJ |
80 | /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
81 | #define ST0_FR (1 << 26) | |
82 | ||
b0069a17 AC |
83 | /* The sizes of floating point registers. */ |
84 | ||
85 | enum | |
86 | { | |
87 | MIPS_FPU_SINGLE_REGSIZE = 4, | |
88 | MIPS_FPU_DOUBLE_REGSIZE = 8 | |
89 | }; | |
90 | ||
1a69e1e4 DJ |
91 | enum |
92 | { | |
93 | MIPS32_REGSIZE = 4, | |
94 | MIPS64_REGSIZE = 8 | |
95 | }; | |
0dadbba0 | 96 | |
2e4ebe70 DJ |
97 | static const char *mips_abi_string; |
98 | ||
40478521 | 99 | static const char *const mips_abi_strings[] = { |
2e4ebe70 DJ |
100 | "auto", |
101 | "n32", | |
102 | "o32", | |
28d169de | 103 | "n64", |
2e4ebe70 DJ |
104 | "o64", |
105 | "eabi32", | |
106 | "eabi64", | |
107 | NULL | |
108 | }; | |
109 | ||
44f1c4d7 YQ |
110 | /* Enum describing the different kinds of breakpoints. */ |
111 | ||
112 | enum mips_breakpoint_kind | |
113 | { | |
114 | /* 16-bit MIPS16 mode breakpoint. */ | |
115 | MIPS_BP_KIND_MIPS16 = 2, | |
116 | ||
117 | /* 16-bit microMIPS mode breakpoint. */ | |
118 | MIPS_BP_KIND_MICROMIPS16 = 3, | |
119 | ||
120 | /* 32-bit standard MIPS mode breakpoint. */ | |
121 | MIPS_BP_KIND_MIPS32 = 4, | |
122 | ||
123 | /* 32-bit microMIPS mode breakpoint. */ | |
124 | MIPS_BP_KIND_MICROMIPS32 = 5, | |
125 | }; | |
126 | ||
4cc0665f MR |
127 | /* For backwards compatibility we default to MIPS16. This flag is |
128 | overridden as soon as unambiguous ELF file flags tell us the | |
129 | compressed ISA encoding used. */ | |
130 | static const char mips_compression_mips16[] = "mips16"; | |
131 | static const char mips_compression_micromips[] = "micromips"; | |
132 | static const char *const mips_compression_strings[] = | |
133 | { | |
134 | mips_compression_mips16, | |
135 | mips_compression_micromips, | |
136 | NULL | |
137 | }; | |
138 | ||
139 | static const char *mips_compression_string = mips_compression_mips16; | |
140 | ||
f8b73d13 DJ |
141 | /* The standard register names, and all the valid aliases for them. */ |
142 | struct register_alias | |
143 | { | |
144 | const char *name; | |
145 | int regnum; | |
146 | }; | |
147 | ||
148 | /* Aliases for o32 and most other ABIs. */ | |
149 | const struct register_alias mips_o32_aliases[] = { | |
150 | { "ta0", 12 }, | |
151 | { "ta1", 13 }, | |
152 | { "ta2", 14 }, | |
153 | { "ta3", 15 } | |
154 | }; | |
155 | ||
156 | /* Aliases for n32 and n64. */ | |
157 | const struct register_alias mips_n32_n64_aliases[] = { | |
158 | { "ta0", 8 }, | |
159 | { "ta1", 9 }, | |
160 | { "ta2", 10 }, | |
161 | { "ta3", 11 } | |
162 | }; | |
163 | ||
164 | /* Aliases for ABI-independent registers. */ | |
165 | const struct register_alias mips_register_aliases[] = { | |
166 | /* The architecture manuals specify these ABI-independent names for | |
167 | the GPRs. */ | |
168 | #define R(n) { "r" #n, n } | |
169 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
170 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
171 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
172 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
173 | #undef R | |
174 | ||
175 | /* k0 and k1 are sometimes called these instead (for "kernel | |
176 | temp"). */ | |
177 | { "kt0", 26 }, | |
178 | { "kt1", 27 }, | |
179 | ||
180 | /* This is the traditional GDB name for the CP0 status register. */ | |
181 | { "sr", MIPS_PS_REGNUM }, | |
182 | ||
183 | /* This is the traditional GDB name for the CP0 BadVAddr register. */ | |
184 | { "bad", MIPS_EMBED_BADVADDR_REGNUM }, | |
185 | ||
186 | /* This is the traditional GDB name for the FCSR. */ | |
187 | { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } | |
188 | }; | |
189 | ||
865093a3 AR |
190 | const struct register_alias mips_numeric_register_aliases[] = { |
191 | #define R(n) { #n, n } | |
192 | R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), | |
193 | R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), | |
194 | R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), | |
195 | R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), | |
196 | #undef R | |
197 | }; | |
198 | ||
c906108c SS |
199 | #ifndef MIPS_DEFAULT_FPU_TYPE |
200 | #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE | |
201 | #endif | |
202 | static int mips_fpu_type_auto = 1; | |
203 | static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; | |
7a292a7a | 204 | |
ccce17b0 | 205 | static unsigned int mips_debug = 0; |
7a292a7a | 206 | |
29709017 DJ |
207 | /* Properties (for struct target_desc) describing the g/G packet |
208 | layout. */ | |
209 | #define PROPERTY_GP32 "internal: transfers-32bit-registers" | |
210 | #define PROPERTY_GP64 "internal: transfers-64bit-registers" | |
211 | ||
4eb0ad19 DJ |
212 | struct target_desc *mips_tdesc_gp32; |
213 | struct target_desc *mips_tdesc_gp64; | |
214 | ||
471b9d15 MR |
215 | /* The current set of options to be passed to the disassembler. */ |
216 | static char *mips_disassembler_options; | |
217 | ||
218 | /* Implicit disassembler options for individual ABIs. These tell | |
219 | libopcodes to use general-purpose register names corresponding | |
220 | to the ABI we have selected, perhaps via a `set mips abi ...' | |
221 | override, rather than ones inferred from the ABI set in the ELF | |
222 | headers of the binary file selected for debugging. */ | |
223 | static const char mips_disassembler_options_o32[] = "gpr-names=32"; | |
224 | static const char mips_disassembler_options_n32[] = "gpr-names=n32"; | |
225 | static const char mips_disassembler_options_n64[] = "gpr-names=64"; | |
226 | ||
56cea623 AC |
227 | const struct mips_regnum * |
228 | mips_regnum (struct gdbarch *gdbarch) | |
229 | { | |
08106042 | 230 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c | 231 | return tdep->regnum; |
56cea623 AC |
232 | } |
233 | ||
234 | static int | |
235 | mips_fpa0_regnum (struct gdbarch *gdbarch) | |
236 | { | |
237 | return mips_regnum (gdbarch)->fp0 + 12; | |
238 | } | |
239 | ||
004159a2 MR |
240 | /* Return 1 if REGNUM refers to a floating-point general register, raw |
241 | or cooked. Otherwise return 0. */ | |
242 | ||
243 | static int | |
244 | mips_float_register_p (struct gdbarch *gdbarch, int regnum) | |
245 | { | |
246 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
247 | ||
248 | return (rawnum >= mips_regnum (gdbarch)->fp0 | |
249 | && rawnum < mips_regnum (gdbarch)->fp0 + 32); | |
250 | } | |
251 | ||
345bd07c SM |
252 | static bool |
253 | mips_eabi (gdbarch *arch) | |
254 | { | |
08106042 | 255 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); |
345bd07c SM |
256 | return (tdep->mips_abi == MIPS_ABI_EABI32 \ |
257 | || tdep->mips_abi == MIPS_ABI_EABI64); | |
258 | } | |
c2d11a7d | 259 | |
345bd07c SM |
260 | static int |
261 | mips_last_fp_arg_regnum (gdbarch *arch) | |
262 | { | |
08106042 | 263 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); |
345bd07c SM |
264 | return tdep->mips_last_fp_arg_regnum; |
265 | } | |
c2d11a7d | 266 | |
345bd07c SM |
267 | static int |
268 | mips_last_arg_regnum (gdbarch *arch) | |
269 | { | |
08106042 | 270 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); |
345bd07c SM |
271 | return tdep->mips_last_arg_regnum; |
272 | } | |
c2d11a7d | 273 | |
345bd07c SM |
274 | static enum mips_fpu_type |
275 | mips_get_fpu_type (gdbarch *arch) | |
276 | { | |
08106042 | 277 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); |
345bd07c SM |
278 | return tdep->mips_fpu_type; |
279 | } | |
c2d11a7d | 280 | |
d1973055 KB |
281 | /* Return the MIPS ABI associated with GDBARCH. */ |
282 | enum mips_abi | |
283 | mips_abi (struct gdbarch *gdbarch) | |
284 | { | |
08106042 | 285 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c | 286 | return tdep->mips_abi; |
d1973055 KB |
287 | } |
288 | ||
4246e332 | 289 | int |
1b13c4f6 | 290 | mips_isa_regsize (struct gdbarch *gdbarch) |
4246e332 | 291 | { |
08106042 | 292 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
29709017 DJ |
293 | |
294 | /* If we know how big the registers are, use that size. */ | |
295 | if (tdep->register_size_valid_p) | |
296 | return tdep->register_size; | |
297 | ||
298 | /* Fall back to the previous behavior. */ | |
4246e332 AC |
299 | return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word |
300 | / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); | |
301 | } | |
302 | ||
b3464d03 PA |
303 | /* Max saved register size. */ |
304 | #define MAX_MIPS_ABI_REGSIZE 8 | |
305 | ||
025bb325 | 306 | /* Return the currently configured (or set) saved register size. */ |
480d3dd2 | 307 | |
e6bc2e8a | 308 | unsigned int |
13326b4e | 309 | mips_abi_regsize (struct gdbarch *gdbarch) |
d929b26f | 310 | { |
1a69e1e4 DJ |
311 | switch (mips_abi (gdbarch)) |
312 | { | |
313 | case MIPS_ABI_EABI32: | |
314 | case MIPS_ABI_O32: | |
315 | return 4; | |
316 | case MIPS_ABI_N32: | |
317 | case MIPS_ABI_N64: | |
318 | case MIPS_ABI_O64: | |
319 | case MIPS_ABI_EABI64: | |
320 | return 8; | |
321 | case MIPS_ABI_UNKNOWN: | |
322 | case MIPS_ABI_LAST: | |
323 | default: | |
f34652de | 324 | internal_error (_("bad switch")); |
1a69e1e4 | 325 | } |
d929b26f AC |
326 | } |
327 | ||
4cc0665f MR |
328 | /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
329 | are some functions to handle addresses associated with compressed | |
330 | code including but not limited to testing, setting, or clearing | |
331 | bit 0 of such addresses. */ | |
742c84f6 | 332 | |
4cc0665f MR |
333 | /* Return one iff compressed code is the MIPS16 instruction set. */ |
334 | ||
335 | static int | |
336 | is_mips16_isa (struct gdbarch *gdbarch) | |
337 | { | |
08106042 | 338 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c | 339 | return tdep->mips_isa == ISA_MIPS16; |
4cc0665f MR |
340 | } |
341 | ||
342 | /* Return one iff compressed code is the microMIPS instruction set. */ | |
343 | ||
344 | static int | |
345 | is_micromips_isa (struct gdbarch *gdbarch) | |
346 | { | |
08106042 | 347 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c | 348 | return tdep->mips_isa == ISA_MICROMIPS; |
4cc0665f MR |
349 | } |
350 | ||
351 | /* Return one iff ADDR denotes compressed code. */ | |
352 | ||
353 | static int | |
354 | is_compact_addr (CORE_ADDR addr) | |
742c84f6 MR |
355 | { |
356 | return ((addr) & 1); | |
357 | } | |
358 | ||
4cc0665f MR |
359 | /* Return one iff ADDR denotes standard ISA code. */ |
360 | ||
361 | static int | |
362 | is_mips_addr (CORE_ADDR addr) | |
363 | { | |
364 | return !is_compact_addr (addr); | |
365 | } | |
366 | ||
367 | /* Return one iff ADDR denotes MIPS16 code. */ | |
368 | ||
369 | static int | |
370 | is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
371 | { | |
372 | return is_compact_addr (addr) && is_mips16_isa (gdbarch); | |
373 | } | |
374 | ||
375 | /* Return one iff ADDR denotes microMIPS code. */ | |
376 | ||
377 | static int | |
378 | is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) | |
379 | { | |
380 | return is_compact_addr (addr) && is_micromips_isa (gdbarch); | |
381 | } | |
382 | ||
383 | /* Strip the ISA (compression) bit off from ADDR. */ | |
384 | ||
742c84f6 | 385 | static CORE_ADDR |
4cc0665f | 386 | unmake_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
387 | { |
388 | return ((addr) & ~(CORE_ADDR) 1); | |
389 | } | |
390 | ||
4cc0665f MR |
391 | /* Add the ISA (compression) bit to ADDR. */ |
392 | ||
742c84f6 | 393 | static CORE_ADDR |
4cc0665f | 394 | make_compact_addr (CORE_ADDR addr) |
742c84f6 MR |
395 | { |
396 | return ((addr) | (CORE_ADDR) 1); | |
397 | } | |
398 | ||
3e29f34a MR |
399 | /* Extern version of unmake_compact_addr; we use a separate function |
400 | so that unmake_compact_addr can be inlined throughout this file. */ | |
401 | ||
402 | CORE_ADDR | |
403 | mips_unmake_compact_addr (CORE_ADDR addr) | |
404 | { | |
405 | return unmake_compact_addr (addr); | |
406 | } | |
407 | ||
71b8ef93 | 408 | /* Functions for setting and testing a bit in a minimal symbol that |
4cc0665f MR |
409 | marks it as MIPS16 or microMIPS function. The MSB of the minimal |
410 | symbol's "info" field is used for this purpose. | |
5a89d8aa | 411 | |
4cc0665f MR |
412 | gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
413 | "special", i.e. refers to a MIPS16 or microMIPS function, and sets | |
414 | one of the "special" bits in a minimal symbol to mark it accordingly. | |
415 | The test checks an ELF-private flag that is valid for true function | |
1bbce132 MR |
416 | symbols only; for synthetic symbols such as for PLT stubs that have |
417 | no ELF-private part at all the MIPS BFD backend arranges for this | |
418 | information to be carried in the asymbol's udata field instead. | |
5a89d8aa | 419 | |
4cc0665f MR |
420 | msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
421 | in a minimal symbol. */ | |
5a89d8aa | 422 | |
5a89d8aa | 423 | static void |
6d82d43b AC |
424 | mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
425 | { | |
4cc0665f | 426 | elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
1bbce132 | 427 | unsigned char st_other; |
4cc0665f | 428 | |
1bbce132 MR |
429 | if ((sym->flags & BSF_SYNTHETIC) == 0) |
430 | st_other = elfsym->internal_elf_sym.st_other; | |
431 | else if ((sym->flags & BSF_FUNCTION) != 0) | |
432 | st_other = sym->udata.i; | |
433 | else | |
4cc0665f MR |
434 | return; |
435 | ||
1bbce132 | 436 | if (ELF_ST_IS_MICROMIPS (st_other)) |
3e29f34a | 437 | { |
e165fcef | 438 | SET_MSYMBOL_TARGET_FLAG_MICROMIPS (msym); |
93d50cd8 | 439 | CORE_ADDR fixed = CORE_ADDR (msym->unrelocated_address ()) | 1; |
9675da25 | 440 | msym->set_unrelocated_address (unrelocated_addr (fixed)); |
3e29f34a | 441 | } |
1bbce132 | 442 | else if (ELF_ST_IS_MIPS16 (st_other)) |
3e29f34a | 443 | { |
e165fcef | 444 | SET_MSYMBOL_TARGET_FLAG_MIPS16 (msym); |
93d50cd8 | 445 | CORE_ADDR fixed = CORE_ADDR (msym->unrelocated_address ()) | 1; |
9675da25 | 446 | msym->set_unrelocated_address (unrelocated_addr (fixed)); |
3e29f34a | 447 | } |
4cc0665f MR |
448 | } |
449 | ||
450 | /* Return one iff MSYM refers to standard ISA code. */ | |
451 | ||
452 | static int | |
453 | msymbol_is_mips (struct minimal_symbol *msym) | |
454 | { | |
f161c171 | 455 | return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym) |
febb368c | 456 | || MSYMBOL_TARGET_FLAG_MICROMIPS (msym)); |
5a89d8aa MS |
457 | } |
458 | ||
4cc0665f MR |
459 | /* Return one iff MSYM refers to MIPS16 code. */ |
460 | ||
71b8ef93 | 461 | static int |
4cc0665f | 462 | msymbol_is_mips16 (struct minimal_symbol *msym) |
71b8ef93 | 463 | { |
f161c171 | 464 | return MSYMBOL_TARGET_FLAG_MIPS16 (msym); |
71b8ef93 MS |
465 | } |
466 | ||
4cc0665f MR |
467 | /* Return one iff MSYM refers to microMIPS code. */ |
468 | ||
469 | static int | |
470 | msymbol_is_micromips (struct minimal_symbol *msym) | |
471 | { | |
f161c171 | 472 | return MSYMBOL_TARGET_FLAG_MICROMIPS (msym); |
4cc0665f MR |
473 | } |
474 | ||
3e29f34a MR |
475 | /* Set the ISA bit in the main symbol too, complementing the corresponding |
476 | minimal symbol setting and reflecting the run-time value of the symbol. | |
477 | The need for comes from the ISA bit having been cleared as code in | |
478 | `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's | |
479 | `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values | |
480 | of symbols referring to compressed code different in GDB to the values | |
481 | used by actual code. That in turn makes them evaluate incorrectly in | |
482 | expressions, producing results different to what the same expressions | |
483 | yield when compiled into the program being debugged. */ | |
484 | ||
485 | static void | |
486 | mips_make_symbol_special (struct symbol *sym, struct objfile *objfile) | |
487 | { | |
66d7f48f | 488 | if (sym->aclass () == LOC_BLOCK) |
3e29f34a MR |
489 | { |
490 | /* We are in symbol reading so it is OK to cast away constness. */ | |
4aeddc50 | 491 | struct block *block = (struct block *) sym->value_block (); |
3e29f34a MR |
492 | CORE_ADDR compact_block_start; |
493 | struct bound_minimal_symbol msym; | |
494 | ||
4b8791e1 | 495 | compact_block_start = block->start () | 1; |
3e29f34a MR |
496 | msym = lookup_minimal_symbol_by_pc (compact_block_start); |
497 | if (msym.minsym && !msymbol_is_mips (msym.minsym)) | |
498 | { | |
4b8791e1 | 499 | block->set_start (compact_block_start); |
3e29f34a MR |
500 | } |
501 | } | |
502 | } | |
503 | ||
88658117 AC |
504 | /* XFER a value from the big/little/left end of the register. |
505 | Depending on the size of the value it might occupy the entire | |
506 | register or just part of it. Make an allowance for this, aligning | |
507 | things accordingly. */ | |
508 | ||
509 | static void | |
ba32f989 DJ |
510 | mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
511 | int reg_num, int length, | |
870cd05e MK |
512 | enum bfd_endian endian, gdb_byte *in, |
513 | const gdb_byte *out, int buf_offset) | |
88658117 | 514 | { |
88658117 | 515 | int reg_offset = 0; |
72a155b4 UW |
516 | |
517 | gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); | |
cb1d2653 AC |
518 | /* Need to transfer the left or right part of the register, based on |
519 | the targets byte order. */ | |
88658117 AC |
520 | switch (endian) |
521 | { | |
522 | case BFD_ENDIAN_BIG: | |
72a155b4 | 523 | reg_offset = register_size (gdbarch, reg_num) - length; |
88658117 AC |
524 | break; |
525 | case BFD_ENDIAN_LITTLE: | |
526 | reg_offset = 0; | |
527 | break; | |
6d82d43b | 528 | case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ |
88658117 AC |
529 | reg_offset = 0; |
530 | break; | |
531 | default: | |
f34652de | 532 | internal_error (_("bad switch")); |
88658117 AC |
533 | } |
534 | if (mips_debug) | |
6cb06a8c TT |
535 | gdb_printf (gdb_stderr, |
536 | "xfer $%d, reg offset %d, buf offset %d, length %d, ", | |
537 | reg_num, reg_offset, buf_offset, length); | |
88658117 AC |
538 | if (mips_debug && out != NULL) |
539 | { | |
540 | int i; | |
6cb06a8c | 541 | gdb_printf (gdb_stdlog, "out "); |
88658117 | 542 | for (i = 0; i < length; i++) |
6cb06a8c | 543 | gdb_printf (gdb_stdlog, "%02x", out[buf_offset + i]); |
88658117 AC |
544 | } |
545 | if (in != NULL) | |
73bb0000 | 546 | regcache->cooked_read_part (reg_num, reg_offset, length, in + buf_offset); |
88658117 | 547 | if (out != NULL) |
e4c4a59b | 548 | regcache->cooked_write_part (reg_num, reg_offset, length, out + buf_offset); |
88658117 AC |
549 | if (mips_debug && in != NULL) |
550 | { | |
551 | int i; | |
6cb06a8c | 552 | gdb_printf (gdb_stdlog, "in "); |
88658117 | 553 | for (i = 0; i < length; i++) |
6cb06a8c | 554 | gdb_printf (gdb_stdlog, "%02x", in[buf_offset + i]); |
88658117 AC |
555 | } |
556 | if (mips_debug) | |
6cb06a8c | 557 | gdb_printf (gdb_stdlog, "\n"); |
88658117 AC |
558 | } |
559 | ||
dd824b04 DJ |
560 | /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU |
561 | compatiblity mode. A return value of 1 means that we have | |
562 | physical 64-bit registers, but should treat them as 32-bit registers. */ | |
563 | ||
564 | static int | |
bd2b40ac | 565 | mips2_fp_compat (frame_info_ptr frame) |
dd824b04 | 566 | { |
72a155b4 | 567 | struct gdbarch *gdbarch = get_frame_arch (frame); |
dd824b04 DJ |
568 | /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not |
569 | meaningful. */ | |
72a155b4 | 570 | if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) |
dd824b04 DJ |
571 | return 0; |
572 | ||
573 | #if 0 | |
574 | /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, | |
575 | in all the places we deal with FP registers. PR gdb/413. */ | |
576 | /* Otherwise check the FR bit in the status register - it controls | |
577 | the FP compatiblity mode. If it is clear we are in compatibility | |
578 | mode. */ | |
9c9acae0 | 579 | if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) |
dd824b04 DJ |
580 | return 1; |
581 | #endif | |
361d1df0 | 582 | |
dd824b04 DJ |
583 | return 0; |
584 | } | |
585 | ||
7a292a7a | 586 | #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 |
c906108c | 587 | |
74ed0bb4 | 588 | static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); |
c906108c | 589 | |
025bb325 | 590 | /* The list of available "set mips " and "show mips " commands. */ |
acdb74a0 AC |
591 | |
592 | static struct cmd_list_element *setmipscmdlist = NULL; | |
593 | static struct cmd_list_element *showmipscmdlist = NULL; | |
594 | ||
5e2e9765 KB |
595 | /* Integer registers 0 thru 31 are handled explicitly by |
596 | mips_register_name(). Processor specific registers 32 and above | |
8a9fc081 | 597 | are listed in the following tables. */ |
691c0433 | 598 | |
6d82d43b AC |
599 | enum |
600 | { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | |
691c0433 AC |
601 | |
602 | /* Generic MIPS. */ | |
603 | ||
27087b7f | 604 | static const char * const mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
6d82d43b AC |
605 | "sr", "lo", "hi", "bad", "cause", "pc", |
606 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
607 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
608 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
609 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
1faeff08 | 610 | "fsr", "fir", |
691c0433 AC |
611 | }; |
612 | ||
691c0433 AC |
613 | /* Names of tx39 registers. */ |
614 | ||
27087b7f | 615 | static const char * const mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
6d82d43b AC |
616 | "sr", "lo", "hi", "bad", "cause", "pc", |
617 | "", "", "", "", "", "", "", "", | |
618 | "", "", "", "", "", "", "", "", | |
619 | "", "", "", "", "", "", "", "", | |
620 | "", "", "", "", "", "", "", "", | |
621 | "", "", "", "", | |
622 | "", "", "", "", "", "", "", "", | |
1faeff08 | 623 | "", "", "config", "cache", "debug", "depc", "epc", |
691c0433 AC |
624 | }; |
625 | ||
44099a67 | 626 | /* Names of registers with Linux kernels. */ |
27087b7f | 627 | static const char * const mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
1faeff08 MR |
628 | "sr", "lo", "hi", "bad", "cause", "pc", |
629 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
630 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
631 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
632 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
633 | "fsr", "fir" | |
634 | }; | |
635 | ||
cce74817 | 636 | |
5e2e9765 | 637 | /* Return the name of the register corresponding to REGNO. */ |
5a89d8aa | 638 | static const char * |
d93859e2 | 639 | mips_register_name (struct gdbarch *gdbarch, int regno) |
cce74817 | 640 | { |
08106042 | 641 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
5e2e9765 | 642 | /* GPR names for all ABIs other than n32/n64. */ |
a121b7c1 | 643 | static const char *mips_gpr_names[] = { |
6d82d43b AC |
644 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
645 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
646 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
647 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", | |
5e2e9765 KB |
648 | }; |
649 | ||
650 | /* GPR names for n32 and n64 ABIs. */ | |
a121b7c1 | 651 | static const char *mips_n32_n64_gpr_names[] = { |
6d82d43b AC |
652 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
653 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
654 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
655 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
5e2e9765 KB |
656 | }; |
657 | ||
d93859e2 | 658 | enum mips_abi abi = mips_abi (gdbarch); |
5e2e9765 | 659 | |
f57d151a | 660 | /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, |
6229fbea HZ |
661 | but then don't make the raw register names visible. This (upper) |
662 | range of user visible register numbers are the pseudo-registers. | |
663 | ||
664 | This approach was adopted accommodate the following scenario: | |
665 | It is possible to debug a 64-bit device using a 32-bit | |
666 | programming model. In such instances, the raw registers are | |
667 | configured to be 64-bits wide, while the pseudo registers are | |
668 | configured to be 32-bits wide. The registers that the user | |
669 | sees - the pseudo registers - match the users expectations | |
670 | given the programming model being used. */ | |
d93859e2 UW |
671 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
672 | if (regno < gdbarch_num_regs (gdbarch)) | |
a4b8ebc8 AC |
673 | return ""; |
674 | ||
5e2e9765 KB |
675 | /* The MIPS integer registers are always mapped from 0 to 31. The |
676 | names of the registers (which reflects the conventions regarding | |
677 | register use) vary depending on the ABI. */ | |
a4b8ebc8 | 678 | if (0 <= rawnum && rawnum < 32) |
5e2e9765 KB |
679 | { |
680 | if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | |
a4b8ebc8 | 681 | return mips_n32_n64_gpr_names[rawnum]; |
5e2e9765 | 682 | else |
a4b8ebc8 | 683 | return mips_gpr_names[rawnum]; |
5e2e9765 | 684 | } |
d93859e2 UW |
685 | else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
686 | return tdesc_register_name (gdbarch, rawnum); | |
687 | else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | |
691c0433 AC |
688 | { |
689 | gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | |
1faeff08 MR |
690 | if (tdep->mips_processor_reg_names[rawnum - 32]) |
691 | return tdep->mips_processor_reg_names[rawnum - 32]; | |
692 | return ""; | |
691c0433 | 693 | } |
5e2e9765 | 694 | else |
f34652de | 695 | internal_error (_("mips_register_name: bad register number %d"), rawnum); |
cce74817 | 696 | } |
5e2e9765 | 697 | |
a4b8ebc8 | 698 | /* Return the groups that a MIPS register can be categorised into. */ |
c5aa993b | 699 | |
a4b8ebc8 AC |
700 | static int |
701 | mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 702 | const struct reggroup *reggroup) |
a4b8ebc8 AC |
703 | { |
704 | int vector_p; | |
705 | int float_p; | |
706 | int raw_p; | |
72a155b4 UW |
707 | int rawnum = regnum % gdbarch_num_regs (gdbarch); |
708 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
a4b8ebc8 AC |
709 | if (reggroup == all_reggroup) |
710 | return pseudo; | |
bd63c870 | 711 | vector_p = register_type (gdbarch, regnum)->is_vector (); |
78134374 | 712 | float_p = register_type (gdbarch, regnum)->code () == TYPE_CODE_FLT; |
a4b8ebc8 AC |
713 | /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs |
714 | (gdbarch), as not all architectures are multi-arch. */ | |
72a155b4 | 715 | raw_p = rawnum < gdbarch_num_regs (gdbarch); |
637b2f86 | 716 | if (gdbarch_register_name (gdbarch, regnum)[0] == '\0') |
a4b8ebc8 AC |
717 | return 0; |
718 | if (reggroup == float_reggroup) | |
719 | return float_p && pseudo; | |
720 | if (reggroup == vector_reggroup) | |
721 | return vector_p && pseudo; | |
722 | if (reggroup == general_reggroup) | |
723 | return (!vector_p && !float_p) && pseudo; | |
724 | /* Save the pseudo registers. Need to make certain that any code | |
725 | extracting register values from a saved register cache also uses | |
726 | pseudo registers. */ | |
727 | if (reggroup == save_reggroup) | |
728 | return raw_p && pseudo; | |
729 | /* Restore the same pseudo register. */ | |
730 | if (reggroup == restore_reggroup) | |
731 | return raw_p && pseudo; | |
6d82d43b | 732 | return 0; |
a4b8ebc8 AC |
733 | } |
734 | ||
f8b73d13 DJ |
735 | /* Return the groups that a MIPS register can be categorised into. |
736 | This version is only used if we have a target description which | |
737 | describes real registers (and their groups). */ | |
738 | ||
739 | static int | |
740 | mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 741 | const struct reggroup *reggroup) |
f8b73d13 DJ |
742 | { |
743 | int rawnum = regnum % gdbarch_num_regs (gdbarch); | |
744 | int pseudo = regnum / gdbarch_num_regs (gdbarch); | |
745 | int ret; | |
746 | ||
747 | /* Only save, restore, and display the pseudo registers. Need to | |
748 | make certain that any code extracting register values from a | |
749 | saved register cache also uses pseudo registers. | |
750 | ||
751 | Note: saving and restoring the pseudo registers is slightly | |
752 | strange; if we have 64 bits, we should save and restore all | |
753 | 64 bits. But this is hard and has little benefit. */ | |
754 | if (!pseudo) | |
755 | return 0; | |
756 | ||
757 | ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); | |
758 | if (ret != -1) | |
759 | return ret; | |
760 | ||
761 | return mips_register_reggroup_p (gdbarch, regnum, reggroup); | |
762 | } | |
763 | ||
a4b8ebc8 | 764 | /* Map the symbol table registers which live in the range [1 * |
f57d151a | 765 | gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw |
47ebcfbe | 766 | registers. Take care of alignment and size problems. */ |
c5aa993b | 767 | |
05d1431c | 768 | static enum register_status |
849d0ba8 | 769 | mips_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, |
47a35522 | 770 | int cookednum, gdb_byte *buf) |
a4b8ebc8 | 771 | { |
72a155b4 UW |
772 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
773 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
774 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 775 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
03f50fc8 | 776 | return regcache->raw_read (rawnum, buf); |
6d82d43b AC |
777 | else if (register_size (gdbarch, rawnum) > |
778 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 779 | { |
08106042 | 780 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c SM |
781 | |
782 | if (tdep->mips64_transfers_32bit_regs_p) | |
03f50fc8 | 783 | return regcache->raw_read_part (rawnum, 0, 4, buf); |
47ebcfbe | 784 | else |
8bdf35dc KB |
785 | { |
786 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
787 | LONGEST regval; | |
05d1431c PA |
788 | enum register_status status; |
789 | ||
03f50fc8 | 790 | status = regcache->raw_read (rawnum, ®val); |
05d1431c PA |
791 | if (status == REG_VALID) |
792 | store_signed_integer (buf, 4, byte_order, regval); | |
793 | return status; | |
8bdf35dc | 794 | } |
47ebcfbe AC |
795 | } |
796 | else | |
f34652de | 797 | internal_error (_("bad register size")); |
a4b8ebc8 AC |
798 | } |
799 | ||
800 | static void | |
6d82d43b AC |
801 | mips_pseudo_register_write (struct gdbarch *gdbarch, |
802 | struct regcache *regcache, int cookednum, | |
47a35522 | 803 | const gdb_byte *buf) |
a4b8ebc8 | 804 | { |
72a155b4 UW |
805 | int rawnum = cookednum % gdbarch_num_regs (gdbarch); |
806 | gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) | |
807 | && cookednum < 2 * gdbarch_num_regs (gdbarch)); | |
47ebcfbe | 808 | if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) |
10eaee5f | 809 | regcache->raw_write (rawnum, buf); |
6d82d43b AC |
810 | else if (register_size (gdbarch, rawnum) > |
811 | register_size (gdbarch, cookednum)) | |
47ebcfbe | 812 | { |
08106042 | 813 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c SM |
814 | |
815 | if (tdep->mips64_transfers_32bit_regs_p) | |
4f0420fd | 816 | regcache->raw_write_part (rawnum, 0, 4, buf); |
47ebcfbe | 817 | else |
8bdf35dc KB |
818 | { |
819 | /* Sign extend the shortened version of the register prior | |
820 | to placing it in the raw register. This is required for | |
821 | some mips64 parts in order to avoid unpredictable behavior. */ | |
822 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
823 | LONGEST regval = extract_signed_integer (buf, 4, byte_order); | |
824 | regcache_raw_write_signed (regcache, rawnum, regval); | |
825 | } | |
47ebcfbe AC |
826 | } |
827 | else | |
f34652de | 828 | internal_error (_("bad register size")); |
a4b8ebc8 | 829 | } |
c5aa993b | 830 | |
175ff332 HZ |
831 | static int |
832 | mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
833 | struct agent_expr *ax, int reg) | |
834 | { | |
835 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
836 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
837 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
838 | ||
839 | ax_reg_mask (ax, rawnum); | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
844 | static int | |
845 | mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, | |
846 | struct agent_expr *ax, int reg) | |
847 | { | |
848 | int rawnum = reg % gdbarch_num_regs (gdbarch); | |
849 | gdb_assert (reg >= gdbarch_num_regs (gdbarch) | |
850 | && reg < 2 * gdbarch_num_regs (gdbarch)); | |
851 | if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) | |
852 | { | |
853 | ax_reg (ax, rawnum); | |
854 | ||
855 | if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) | |
dda83cd7 | 856 | { |
345bd07c | 857 | mips_gdbarch_tdep *tdep |
08106042 | 858 | = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
345bd07c SM |
859 | |
860 | if (!tdep->mips64_transfers_32bit_regs_p | |
175ff332 HZ |
861 | || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) |
862 | { | |
863 | ax_const_l (ax, 32); | |
864 | ax_simple (ax, aop_lsh); | |
865 | } | |
866 | ax_const_l (ax, 32); | |
867 | ax_simple (ax, aop_rsh_signed); | |
868 | } | |
869 | } | |
870 | else | |
f34652de | 871 | internal_error (_("bad register size")); |
175ff332 HZ |
872 | |
873 | return 0; | |
874 | } | |
875 | ||
4cc0665f | 876 | /* Table to translate 3-bit register field to actual register number. */ |
d467df4e | 877 | static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
c906108c SS |
878 | |
879 | /* Heuristic_proc_start may hunt through the text section for a long | |
880 | time across a 2400 baud serial line. Allows the user to limit this | |
881 | search. */ | |
882 | ||
44096aee | 883 | static int heuristic_fence_post = 0; |
c906108c | 884 | |
46cd78fb | 885 | /* Number of bytes of storage in the actual machine representation for |
719ec221 AC |
886 | register N. NOTE: This defines the pseudo register type so need to |
887 | rebuild the architecture vector. */ | |
43e526b9 | 888 | |
491144b5 | 889 | static bool mips64_transfers_32bit_regs_p = false; |
43e526b9 | 890 | |
719ec221 | 891 | static void |
eb4c3f4a | 892 | set_mips64_transfers_32bit_regs (const char *args, int from_tty, |
719ec221 | 893 | struct cmd_list_element *c) |
43e526b9 | 894 | { |
719ec221 | 895 | struct gdbarch_info info; |
719ec221 AC |
896 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
897 | instead of relying on globals. Doing that would let generic code | |
898 | handle the search for this specific architecture. */ | |
899 | if (!gdbarch_update_p (info)) | |
a4b8ebc8 | 900 | { |
719ec221 | 901 | mips64_transfers_32bit_regs_p = 0; |
8a3fe4f8 | 902 | error (_("32-bit compatibility mode not supported")); |
a4b8ebc8 | 903 | } |
a4b8ebc8 AC |
904 | } |
905 | ||
47ebcfbe | 906 | /* Convert to/from a register and the corresponding memory value. */ |
43e526b9 | 907 | |
ee51a8c7 KB |
908 | /* This predicate tests for the case of an 8 byte floating point |
909 | value that is being transferred to or from a pair of floating point | |
910 | registers each of which are (or are considered to be) only 4 bytes | |
911 | wide. */ | |
ff2e87ac | 912 | static int |
ee51a8c7 KB |
913 | mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
914 | struct type *type) | |
ff2e87ac | 915 | { |
0abe36f5 MD |
916 | return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
917 | && register_size (gdbarch, regnum) == 4 | |
004159a2 | 918 | && mips_float_register_p (gdbarch, regnum) |
df86565b | 919 | && type->code () == TYPE_CODE_FLT && type->length () == 8); |
ff2e87ac AC |
920 | } |
921 | ||
ee51a8c7 KB |
922 | /* This predicate tests for the case of a value of less than 8 |
923 | bytes in width that is being transfered to or from an 8 byte | |
924 | general purpose register. */ | |
925 | static int | |
926 | mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | |
927 | struct type *type) | |
928 | { | |
929 | int num_regs = gdbarch_num_regs (gdbarch); | |
930 | ||
931 | return (register_size (gdbarch, regnum) == 8 | |
dda83cd7 | 932 | && regnum % num_regs > 0 && regnum % num_regs < 32 |
df86565b | 933 | && type->length () < 8); |
ee51a8c7 KB |
934 | } |
935 | ||
936 | static int | |
025bb325 MS |
937 | mips_convert_register_p (struct gdbarch *gdbarch, |
938 | int regnum, struct type *type) | |
ee51a8c7 | 939 | { |
eaa05d59 MR |
940 | return (mips_convert_register_float_case_p (gdbarch, regnum, type) |
941 | || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); | |
ee51a8c7 KB |
942 | } |
943 | ||
8dccd430 | 944 | static int |
bd2b40ac | 945 | mips_register_to_value (frame_info_ptr frame, int regnum, |
8dccd430 PA |
946 | struct type *type, gdb_byte *to, |
947 | int *optimizedp, int *unavailablep) | |
102182a9 | 948 | { |
ee51a8c7 KB |
949 | struct gdbarch *gdbarch = get_frame_arch (frame); |
950 | ||
951 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
952 | { | |
953 | get_frame_register (frame, regnum + 0, to + 4); | |
954 | get_frame_register (frame, regnum + 1, to + 0); | |
8dccd430 | 955 | |
bdec2917 | 956 | if (!get_frame_register_bytes (frame, regnum + 0, 0, {to + 4, 4}, |
8dccd430 PA |
957 | optimizedp, unavailablep)) |
958 | return 0; | |
959 | ||
bdec2917 | 960 | if (!get_frame_register_bytes (frame, regnum + 1, 0, {to + 0, 4}, |
8dccd430 PA |
961 | optimizedp, unavailablep)) |
962 | return 0; | |
963 | *optimizedp = *unavailablep = 0; | |
964 | return 1; | |
ee51a8c7 KB |
965 | } |
966 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
967 | { | |
df86565b | 968 | size_t len = type->length (); |
8dccd430 PA |
969 | CORE_ADDR offset; |
970 | ||
971 | offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; | |
bdec2917 | 972 | if (!get_frame_register_bytes (frame, regnum, offset, {to, len}, |
8dccd430 PA |
973 | optimizedp, unavailablep)) |
974 | return 0; | |
975 | ||
976 | *optimizedp = *unavailablep = 0; | |
977 | return 1; | |
ee51a8c7 KB |
978 | } |
979 | else | |
980 | { | |
f34652de | 981 | internal_error (_("mips_register_to_value: unrecognized case")); |
ee51a8c7 | 982 | } |
102182a9 MS |
983 | } |
984 | ||
42c466d7 | 985 | static void |
bd2b40ac | 986 | mips_value_to_register (frame_info_ptr frame, int regnum, |
47a35522 | 987 | struct type *type, const gdb_byte *from) |
102182a9 | 988 | { |
ee51a8c7 KB |
989 | struct gdbarch *gdbarch = get_frame_arch (frame); |
990 | ||
991 | if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | |
992 | { | |
993 | put_frame_register (frame, regnum + 0, from + 4); | |
994 | put_frame_register (frame, regnum + 1, from + 0); | |
995 | } | |
996 | else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) | |
997 | { | |
998 | gdb_byte fill[8]; | |
df86565b | 999 | size_t len = type->length (); |
ee51a8c7 KB |
1000 | |
1001 | /* Sign extend values, irrespective of type, that are stored to | |
dda83cd7 | 1002 | a 64-bit general purpose register. (32-bit unsigned values |
ee51a8c7 KB |
1003 | are stored as signed quantities within a 64-bit register. |
1004 | When performing an operation, in compiled code, that combines | |
1005 | a 32-bit unsigned value with a signed 64-bit value, a type | |
1006 | conversion is first performed that zeroes out the high 32 bits.) */ | |
1007 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | |
1008 | { | |
1009 | if (from[0] & 0x80) | |
1010 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); | |
1011 | else | |
1012 | store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); | |
bdec2917 LM |
1013 | put_frame_register_bytes (frame, regnum, 0, {fill, 8 - len}); |
1014 | put_frame_register_bytes (frame, regnum, 8 - len, {from, len}); | |
ee51a8c7 KB |
1015 | } |
1016 | else | |
1017 | { | |
1018 | if (from[len-1] & 0x80) | |
1019 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); | |
1020 | else | |
1021 | store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); | |
bdec2917 LM |
1022 | put_frame_register_bytes (frame, regnum, 0, {from, len}); |
1023 | put_frame_register_bytes (frame, regnum, len, {fill, 8 - len}); | |
ee51a8c7 KB |
1024 | } |
1025 | } | |
1026 | else | |
1027 | { | |
f34652de | 1028 | internal_error (_("mips_value_to_register: unrecognized case")); |
ee51a8c7 | 1029 | } |
102182a9 MS |
1030 | } |
1031 | ||
a4b8ebc8 AC |
1032 | /* Return the GDB type object for the "standard" data type of data in |
1033 | register REG. */ | |
78fde5f8 KB |
1034 | |
1035 | static struct type * | |
a4b8ebc8 AC |
1036 | mips_register_type (struct gdbarch *gdbarch, int regnum) |
1037 | { | |
72a155b4 | 1038 | gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
004159a2 | 1039 | if (mips_float_register_p (gdbarch, regnum)) |
a6425924 | 1040 | { |
5ef80fb0 | 1041 | /* The floating-point registers raw, or cooked, always match |
dda83cd7 | 1042 | mips_isa_regsize(), and also map 1:1, byte for byte. */ |
8da61cc4 | 1043 | if (mips_isa_regsize (gdbarch) == 4) |
27067745 | 1044 | return builtin_type (gdbarch)->builtin_float; |
8da61cc4 | 1045 | else |
27067745 | 1046 | return builtin_type (gdbarch)->builtin_double; |
a6425924 | 1047 | } |
72a155b4 | 1048 | else if (regnum < gdbarch_num_regs (gdbarch)) |
d5ac5a39 AC |
1049 | { |
1050 | /* The raw or ISA registers. These are all sized according to | |
1051 | the ISA regsize. */ | |
1052 | if (mips_isa_regsize (gdbarch) == 4) | |
df4df182 | 1053 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 | 1054 | else |
df4df182 | 1055 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1056 | } |
78fde5f8 | 1057 | else |
d5ac5a39 | 1058 | { |
1faeff08 | 1059 | int rawnum = regnum - gdbarch_num_regs (gdbarch); |
08106042 | 1060 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
1faeff08 | 1061 | |
d5ac5a39 AC |
1062 | /* The cooked or ABI registers. These are sized according to |
1063 | the ABI (with a few complications). */ | |
1faeff08 MR |
1064 | if (rawnum == mips_regnum (gdbarch)->fp_control_status |
1065 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1066 | return builtin_type (gdbarch)->builtin_int32; | |
de4bfa86 | 1067 | else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
1faeff08 MR |
1068 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1069 | && rawnum <= MIPS_LAST_EMBED_REGNUM) | |
d5ac5a39 AC |
1070 | /* The pseudo/cooked view of the embedded registers is always |
1071 | 32-bit. The raw view is handled below. */ | |
df4df182 | 1072 | return builtin_type (gdbarch)->builtin_int32; |
345bd07c | 1073 | else if (tdep->mips64_transfers_32bit_regs_p) |
d5ac5a39 AC |
1074 | /* The target, while possibly using a 64-bit register buffer, |
1075 | is only transfering 32-bits of each integer register. | |
1076 | Reflect this in the cooked/pseudo (ABI) register value. */ | |
df4df182 | 1077 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1078 | else if (mips_abi_regsize (gdbarch) == 4) |
1079 | /* The ABI is restricted to 32-bit registers (the ISA could be | |
1080 | 32- or 64-bit). */ | |
df4df182 | 1081 | return builtin_type (gdbarch)->builtin_int32; |
d5ac5a39 AC |
1082 | else |
1083 | /* 64-bit ABI. */ | |
df4df182 | 1084 | return builtin_type (gdbarch)->builtin_int64; |
d5ac5a39 | 1085 | } |
78fde5f8 KB |
1086 | } |
1087 | ||
f8b73d13 DJ |
1088 | /* Return the GDB type for the pseudo register REGNUM, which is the |
1089 | ABI-level view. This function is only called if there is a target | |
1090 | description which includes registers, so we know precisely the | |
1091 | types of hardware registers. */ | |
1092 | ||
1093 | static struct type * | |
1094 | mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
1095 | { | |
1096 | const int num_regs = gdbarch_num_regs (gdbarch); | |
f8b73d13 DJ |
1097 | int rawnum = regnum % num_regs; |
1098 | struct type *rawtype; | |
1099 | ||
1100 | gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | |
1101 | ||
1102 | /* Absent registers are still absent. */ | |
1103 | rawtype = gdbarch_register_type (gdbarch, rawnum); | |
df86565b | 1104 | if (rawtype->length () == 0) |
f8b73d13 DJ |
1105 | return rawtype; |
1106 | ||
a6912260 MR |
1107 | /* Present the floating point registers however the hardware did; |
1108 | do not try to convert between FPU layouts. */ | |
de13fcf2 | 1109 | if (mips_float_register_p (gdbarch, rawnum)) |
f8b73d13 DJ |
1110 | return rawtype; |
1111 | ||
78b86327 MR |
1112 | /* Floating-point control registers are always 32-bit even though for |
1113 | backwards compatibility reasons 64-bit targets will transfer them | |
1114 | as 64-bit quantities even if using XML descriptions. */ | |
1115 | if (rawnum == mips_regnum (gdbarch)->fp_control_status | |
1116 | || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) | |
1117 | return builtin_type (gdbarch)->builtin_int32; | |
1118 | ||
f8b73d13 DJ |
1119 | /* Use pointer types for registers if we can. For n32 we can not, |
1120 | since we do not have a 64-bit pointer type. */ | |
0dfff4cb | 1121 | if (mips_abi_regsize (gdbarch) |
df86565b | 1122 | == builtin_type (gdbarch)->builtin_data_ptr->length()) |
f8b73d13 | 1123 | { |
1faeff08 MR |
1124 | if (rawnum == MIPS_SP_REGNUM |
1125 | || rawnum == mips_regnum (gdbarch)->badvaddr) | |
0dfff4cb | 1126 | return builtin_type (gdbarch)->builtin_data_ptr; |
1faeff08 | 1127 | else if (rawnum == mips_regnum (gdbarch)->pc) |
0dfff4cb | 1128 | return builtin_type (gdbarch)->builtin_func_ptr; |
f8b73d13 DJ |
1129 | } |
1130 | ||
df86565b | 1131 | if (mips_abi_regsize (gdbarch) == 4 && rawtype->length () == 8 |
1faeff08 MR |
1132 | && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
1133 | || rawnum == mips_regnum (gdbarch)->lo | |
1134 | || rawnum == mips_regnum (gdbarch)->hi | |
1135 | || rawnum == mips_regnum (gdbarch)->badvaddr | |
1136 | || rawnum == mips_regnum (gdbarch)->cause | |
1137 | || rawnum == mips_regnum (gdbarch)->pc | |
1138 | || (mips_regnum (gdbarch)->dspacc != -1 | |
1139 | && rawnum >= mips_regnum (gdbarch)->dspacc | |
1140 | && rawnum < mips_regnum (gdbarch)->dspacc + 6))) | |
df4df182 | 1141 | return builtin_type (gdbarch)->builtin_int32; |
f8b73d13 | 1142 | |
a6912260 MR |
1143 | /* The pseudo/cooked view of embedded registers is always |
1144 | 32-bit, even if the target transfers 64-bit values for them. | |
1145 | New targets relying on XML descriptions should only transfer | |
1146 | the necessary 32 bits, but older versions of GDB expected 64, | |
1147 | so allow the target to provide 64 bits without interfering | |
1148 | with the displayed type. */ | |
de4bfa86 | 1149 | if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
78b86327 | 1150 | && rawnum >= MIPS_FIRST_EMBED_REGNUM |
1faeff08 | 1151 | && rawnum <= MIPS_LAST_EMBED_REGNUM) |
a6912260 | 1152 | return builtin_type (gdbarch)->builtin_int32; |
1faeff08 | 1153 | |
f8b73d13 DJ |
1154 | /* For all other registers, pass through the hardware type. */ |
1155 | return rawtype; | |
1156 | } | |
bcb0cc15 | 1157 | |
025bb325 | 1158 | /* Should the upper word of 64-bit addresses be zeroed? */ |
ea33cd92 | 1159 | static enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
4014092b AC |
1160 | |
1161 | static int | |
345bd07c | 1162 | mips_mask_address_p (mips_gdbarch_tdep *tdep) |
4014092b AC |
1163 | { |
1164 | switch (mask_address_var) | |
1165 | { | |
7f19b9a2 | 1166 | case AUTO_BOOLEAN_TRUE: |
4014092b | 1167 | return 1; |
7f19b9a2 | 1168 | case AUTO_BOOLEAN_FALSE: |
4014092b AC |
1169 | return 0; |
1170 | break; | |
7f19b9a2 | 1171 | case AUTO_BOOLEAN_AUTO: |
480d3dd2 | 1172 | return tdep->default_mask_address_p; |
4014092b | 1173 | default: |
f34652de | 1174 | internal_error (_("mips_mask_address_p: bad switch")); |
4014092b | 1175 | return -1; |
361d1df0 | 1176 | } |
4014092b AC |
1177 | } |
1178 | ||
1179 | static void | |
08546159 AC |
1180 | show_mask_address (struct ui_file *file, int from_tty, |
1181 | struct cmd_list_element *c, const char *value) | |
4014092b | 1182 | { |
52abb4de AB |
1183 | const char *additional_text = ""; |
1184 | if (mask_address_var == AUTO_BOOLEAN_AUTO) | |
4014092b | 1185 | { |
52abb4de AB |
1186 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
1187 | additional_text = _(" (current architecture is not MIPS)"); | |
1188 | else | |
1189 | { | |
1190 | mips_gdbarch_tdep *tdep | |
08106042 | 1191 | = gdbarch_tdep<mips_gdbarch_tdep> (target_gdbarch ()); |
52abb4de AB |
1192 | |
1193 | if (mips_mask_address_p (tdep)) | |
1194 | additional_text = _(" (currently \"on\")"); | |
1195 | else | |
1196 | additional_text = _(" (currently \"off\")"); | |
1197 | } | |
361d1df0 | 1198 | } |
52abb4de AB |
1199 | |
1200 | gdb_printf (file, _("Zeroing of upper 32 bits of 64-bit addresses is \"%s\"%s.\n"), | |
1201 | value, additional_text); | |
4014092b | 1202 | } |
c906108c | 1203 | |
4cc0665f MR |
1204 | /* Tell if the program counter value in MEMADDR is in a standard ISA |
1205 | function. */ | |
1206 | ||
1207 | int | |
1208 | mips_pc_is_mips (CORE_ADDR memaddr) | |
1209 | { | |
7cbd4a93 | 1210 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1211 | |
1212 | /* Flags indicating that this is a MIPS16 or microMIPS function is | |
1213 | stored by elfread.c in the high bit of the info field. Use this | |
1214 | to decide if the function is standard MIPS. Otherwise if bit 0 | |
1215 | of the address is clear, then this is a standard MIPS function. */ | |
3e29f34a | 1216 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1217 | if (sym.minsym) |
1218 | return msymbol_is_mips (sym.minsym); | |
4cc0665f MR |
1219 | else |
1220 | return is_mips_addr (memaddr); | |
1221 | } | |
1222 | ||
c906108c SS |
1223 | /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
1224 | ||
0fe7e7c8 | 1225 | int |
4cc0665f | 1226 | mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
c906108c | 1227 | { |
7cbd4a93 | 1228 | struct bound_minimal_symbol sym; |
c906108c | 1229 | |
91912e4d MR |
1230 | /* A flag indicating that this is a MIPS16 function is stored by |
1231 | elfread.c in the high bit of the info field. Use this to decide | |
4cc0665f MR |
1232 | if the function is MIPS16. Otherwise if bit 0 of the address is |
1233 | set, then ELF file flags will tell if this is a MIPS16 function. */ | |
3e29f34a | 1234 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1235 | if (sym.minsym) |
1236 | return msymbol_is_mips16 (sym.minsym); | |
4cc0665f MR |
1237 | else |
1238 | return is_mips16_addr (gdbarch, memaddr); | |
1239 | } | |
1240 | ||
1241 | /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ | |
1242 | ||
1243 | int | |
1244 | mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1245 | { | |
7cbd4a93 | 1246 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1247 | |
1248 | /* A flag indicating that this is a microMIPS function is stored by | |
1249 | elfread.c in the high bit of the info field. Use this to decide | |
1250 | if the function is microMIPS. Otherwise if bit 0 of the address | |
1251 | is set, then ELF file flags will tell if this is a microMIPS | |
1252 | function. */ | |
3e29f34a | 1253 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 TT |
1254 | if (sym.minsym) |
1255 | return msymbol_is_micromips (sym.minsym); | |
4cc0665f MR |
1256 | else |
1257 | return is_micromips_addr (gdbarch, memaddr); | |
1258 | } | |
1259 | ||
1260 | /* Tell the ISA type of the function the program counter value in MEMADDR | |
1261 | is in. */ | |
1262 | ||
1263 | static enum mips_isa | |
1264 | mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) | |
1265 | { | |
7cbd4a93 | 1266 | struct bound_minimal_symbol sym; |
4cc0665f MR |
1267 | |
1268 | /* A flag indicating that this is a MIPS16 or a microMIPS function | |
1269 | is stored by elfread.c in the high bit of the info field. Use | |
1270 | this to decide if the function is MIPS16 or microMIPS or normal | |
1271 | MIPS. Otherwise if bit 0 of the address is set, then ELF file | |
1272 | flags will tell if this is a MIPS16 or a microMIPS function. */ | |
3e29f34a | 1273 | sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); |
7cbd4a93 | 1274 | if (sym.minsym) |
4cc0665f | 1275 | { |
7cbd4a93 | 1276 | if (msymbol_is_micromips (sym.minsym)) |
4cc0665f | 1277 | return ISA_MICROMIPS; |
7cbd4a93 | 1278 | else if (msymbol_is_mips16 (sym.minsym)) |
4cc0665f MR |
1279 | return ISA_MIPS16; |
1280 | else | |
1281 | return ISA_MIPS; | |
1282 | } | |
c906108c | 1283 | else |
4cc0665f MR |
1284 | { |
1285 | if (is_mips_addr (memaddr)) | |
1286 | return ISA_MIPS; | |
1287 | else if (is_micromips_addr (gdbarch, memaddr)) | |
1288 | return ISA_MICROMIPS; | |
1289 | else | |
1290 | return ISA_MIPS16; | |
1291 | } | |
c906108c SS |
1292 | } |
1293 | ||
3e29f34a MR |
1294 | /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery. |
1295 | The need for comes from the ISA bit having been cleared, making | |
1296 | addresses in FDE, range records, etc. referring to compressed code | |
1297 | different to those in line information, the symbol table and finally | |
1298 | the PC register. That in turn confuses many operations. */ | |
1299 | ||
1300 | static CORE_ADDR | |
1301 | mips_adjust_dwarf2_addr (CORE_ADDR pc) | |
1302 | { | |
1303 | pc = unmake_compact_addr (pc); | |
1304 | return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc); | |
1305 | } | |
1306 | ||
1307 | /* Recalculate the line record requested so that the resulting PC has | |
1308 | the ISA bit set correctly, used by DWARF-2 machinery. The need for | |
1309 | this adjustment comes from some records associated with compressed | |
1310 | code having the ISA bit cleared, most notably at function prologue | |
1311 | ends. The ISA bit is in this context retrieved from the minimal | |
1312 | symbol covering the address requested, which in turn has been | |
1313 | constructed from the binary's symbol table rather than DWARF-2 | |
1314 | information. The correct setting of the ISA bit is required for | |
1315 | breakpoint addresses to correctly match against the stop PC. | |
1316 | ||
1317 | As line entries can specify relative address adjustments we need to | |
1318 | keep track of the absolute value of the last line address recorded | |
1319 | in line information, so that we can calculate the actual address to | |
1320 | apply the ISA bit adjustment to. We use PC for this tracking and | |
1321 | keep the original address there. | |
1322 | ||
1323 | As such relative address adjustments can be odd within compressed | |
1324 | code we need to keep track of the last line address with the ISA | |
1325 | bit adjustment applied too, as the original address may or may not | |
1326 | have had the ISA bit set. We use ADJ_PC for this tracking and keep | |
1327 | the adjusted address there. | |
1328 | ||
1329 | For relative address adjustments we then use these variables to | |
1330 | calculate the address intended by line information, which will be | |
1331 | PC-relative, and return an updated adjustment carrying ISA bit | |
1332 | information, which will be ADJ_PC-relative. For absolute address | |
1333 | adjustments we just return the same address that we store in ADJ_PC | |
1334 | too. | |
1335 | ||
1336 | As the first line entry can be relative to an implied address value | |
1337 | of 0 we need to have the initial address set up that we store in PC | |
1338 | and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1' | |
1339 | that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */ | |
1340 | ||
1341 | static CORE_ADDR | |
1342 | mips_adjust_dwarf2_line (CORE_ADDR addr, int rel) | |
1343 | { | |
1344 | static CORE_ADDR adj_pc; | |
1345 | static CORE_ADDR pc; | |
1346 | CORE_ADDR isa_pc; | |
1347 | ||
1348 | pc = rel ? pc + addr : addr; | |
1349 | isa_pc = mips_adjust_dwarf2_addr (pc); | |
1350 | addr = rel ? isa_pc - adj_pc : isa_pc; | |
1351 | adj_pc = isa_pc; | |
1352 | return addr; | |
1353 | } | |
1354 | ||
14132e89 MR |
1355 | /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
1356 | ||
1357 | static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; | |
1358 | static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; | |
1359 | static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; | |
1360 | static const char mips_str_call_stub[] = "__call_stub_"; | |
1361 | static const char mips_str_fn_stub[] = "__fn_stub_"; | |
1362 | ||
1363 | /* This is used as a PIC thunk prefix. */ | |
1364 | ||
1365 | static const char mips_str_pic[] = ".pic."; | |
1366 | ||
1367 | /* Return non-zero if the PC is inside a call thunk (aka stub or | |
1368 | trampoline) that should be treated as a temporary frame. */ | |
1369 | ||
1370 | static int | |
1371 | mips_in_frame_stub (CORE_ADDR pc) | |
1372 | { | |
1373 | CORE_ADDR start_addr; | |
1374 | const char *name; | |
1375 | ||
1376 | /* Find the starting address of the function containing the PC. */ | |
1377 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1378 | return 0; | |
1379 | ||
1380 | /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ | |
61012eef | 1381 | if (startswith (name, mips_str_mips16_call_stub)) |
14132e89 MR |
1382 | return 1; |
1383 | /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ | |
61012eef | 1384 | if (startswith (name, mips_str_call_stub)) |
14132e89 MR |
1385 | return 1; |
1386 | /* If the PC is in __fn_stub_*, this is a call stub. */ | |
61012eef | 1387 | if (startswith (name, mips_str_fn_stub)) |
14132e89 MR |
1388 | return 1; |
1389 | ||
1390 | return 0; /* Not a stub. */ | |
1391 | } | |
1392 | ||
b2fa5097 | 1393 | /* MIPS believes that the PC has a sign extended value. Perhaps the |
025bb325 | 1394 | all registers should be sign extended for simplicity? */ |
6c997a34 AC |
1395 | |
1396 | static CORE_ADDR | |
c113ed0c | 1397 | mips_read_pc (readable_regcache *regcache) |
6c997a34 | 1398 | { |
ac7936df | 1399 | int regnum = gdbarch_pc_regnum (regcache->arch ()); |
70242eb1 | 1400 | LONGEST pc; |
8376de04 | 1401 | |
c113ed0c | 1402 | regcache->cooked_read (regnum, &pc); |
61a1198a | 1403 | return pc; |
b6cb9035 AC |
1404 | } |
1405 | ||
58dfe9ff | 1406 | static CORE_ADDR |
bd2b40ac | 1407 | mips_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame) |
58dfe9ff | 1408 | { |
14132e89 | 1409 | CORE_ADDR pc; |
930bd0e0 | 1410 | |
8376de04 | 1411 | pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
14132e89 MR |
1412 | /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
1413 | intermediate frames. In this case we can get the caller's address | |
1414 | from $ra, or if $ra contains an address within a thunk as well, then | |
1415 | it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} | |
1416 | and thus the caller's address is in $s2. */ | |
1417 | if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) | |
1418 | { | |
1419 | pc = frame_unwind_register_signed | |
1420 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
14132e89 | 1421 | if (mips_in_frame_stub (pc)) |
3e29f34a MR |
1422 | pc = frame_unwind_register_signed |
1423 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
14132e89 | 1424 | } |
930bd0e0 | 1425 | return pc; |
edfae063 AC |
1426 | } |
1427 | ||
30244cd8 | 1428 | static CORE_ADDR |
bd2b40ac | 1429 | mips_unwind_sp (struct gdbarch *gdbarch, frame_info_ptr next_frame) |
30244cd8 | 1430 | { |
72a155b4 UW |
1431 | return frame_unwind_register_signed |
1432 | (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | |
30244cd8 UW |
1433 | } |
1434 | ||
b8a22b94 | 1435 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
edfae063 AC |
1436 | dummy frame. The frame ID's base needs to match the TOS value |
1437 | saved by save_dummy_frame_tos(), and the PC match the dummy frame's | |
1438 | breakpoint. */ | |
1439 | ||
1440 | static struct frame_id | |
bd2b40ac | 1441 | mips_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) |
edfae063 | 1442 | { |
f57d151a | 1443 | return frame_id_build |
b8a22b94 DJ |
1444 | (get_frame_register_signed (this_frame, |
1445 | gdbarch_num_regs (gdbarch) | |
1446 | + MIPS_SP_REGNUM), | |
1447 | get_frame_pc (this_frame)); | |
58dfe9ff AC |
1448 | } |
1449 | ||
5a439849 MR |
1450 | /* Implement the "write_pc" gdbarch method. */ |
1451 | ||
1452 | void | |
61a1198a | 1453 | mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
b6cb9035 | 1454 | { |
ac7936df | 1455 | int regnum = gdbarch_pc_regnum (regcache->arch ()); |
8376de04 | 1456 | |
3e29f34a | 1457 | regcache_cooked_write_unsigned (regcache, regnum, pc); |
6c997a34 | 1458 | } |
c906108c | 1459 | |
4cc0665f MR |
1460 | /* Fetch and return instruction from the specified location. Handle |
1461 | MIPS16/microMIPS as appropriate. */ | |
c906108c | 1462 | |
d37cca3d | 1463 | static ULONGEST |
4cc0665f | 1464 | mips_fetch_instruction (struct gdbarch *gdbarch, |
d09f2c3f | 1465 | enum mips_isa isa, CORE_ADDR addr, int *errp) |
c906108c | 1466 | { |
e17a4113 | 1467 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 1468 | gdb_byte buf[MIPS_INSN32_SIZE]; |
c906108c | 1469 | int instlen; |
d09f2c3f | 1470 | int err; |
c906108c | 1471 | |
4cc0665f | 1472 | switch (isa) |
c906108c | 1473 | { |
4cc0665f MR |
1474 | case ISA_MICROMIPS: |
1475 | case ISA_MIPS16: | |
95ac2dcf | 1476 | instlen = MIPS_INSN16_SIZE; |
4cc0665f MR |
1477 | addr = unmake_compact_addr (addr); |
1478 | break; | |
1479 | case ISA_MIPS: | |
1480 | instlen = MIPS_INSN32_SIZE; | |
1481 | break; | |
1482 | default: | |
f34652de | 1483 | internal_error (_("invalid ISA")); |
4cc0665f | 1484 | break; |
c906108c | 1485 | } |
d09f2c3f PA |
1486 | err = target_read_memory (addr, buf, instlen); |
1487 | if (errp != NULL) | |
1488 | *errp = err; | |
1489 | if (err != 0) | |
4cc0665f | 1490 | { |
d09f2c3f PA |
1491 | if (errp == NULL) |
1492 | memory_error (TARGET_XFER_E_IO, addr); | |
4cc0665f MR |
1493 | return 0; |
1494 | } | |
e17a4113 | 1495 | return extract_unsigned_integer (buf, instlen, byte_order); |
c906108c SS |
1496 | } |
1497 | ||
025bb325 | 1498 | /* These are the fields of 32 bit mips instructions. */ |
e135b889 DJ |
1499 | #define mips32_op(x) (x >> 26) |
1500 | #define itype_op(x) (x >> 26) | |
1501 | #define itype_rs(x) ((x >> 21) & 0x1f) | |
c906108c | 1502 | #define itype_rt(x) ((x >> 16) & 0x1f) |
e135b889 | 1503 | #define itype_immediate(x) (x & 0xffff) |
c906108c | 1504 | |
e135b889 DJ |
1505 | #define jtype_op(x) (x >> 26) |
1506 | #define jtype_target(x) (x & 0x03ffffff) | |
c906108c | 1507 | |
e135b889 DJ |
1508 | #define rtype_op(x) (x >> 26) |
1509 | #define rtype_rs(x) ((x >> 21) & 0x1f) | |
1510 | #define rtype_rt(x) ((x >> 16) & 0x1f) | |
1511 | #define rtype_rd(x) ((x >> 11) & 0x1f) | |
1512 | #define rtype_shamt(x) ((x >> 6) & 0x1f) | |
1513 | #define rtype_funct(x) (x & 0x3f) | |
c906108c | 1514 | |
4cc0665f MR |
1515 | /* MicroMIPS instruction fields. */ |
1516 | #define micromips_op(x) ((x) >> 10) | |
1517 | ||
1518 | /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest | |
1519 | bit and the size respectively of the field extracted. */ | |
1520 | #define b0s4_imm(x) ((x) & 0xf) | |
1521 | #define b0s5_imm(x) ((x) & 0x1f) | |
1522 | #define b0s5_reg(x) ((x) & 0x1f) | |
1523 | #define b0s7_imm(x) ((x) & 0x7f) | |
1524 | #define b0s10_imm(x) ((x) & 0x3ff) | |
1525 | #define b1s4_imm(x) (((x) >> 1) & 0xf) | |
1526 | #define b1s9_imm(x) (((x) >> 1) & 0x1ff) | |
1527 | #define b2s3_cc(x) (((x) >> 2) & 0x7) | |
1528 | #define b4s2_regl(x) (((x) >> 4) & 0x3) | |
1529 | #define b5s5_op(x) (((x) >> 5) & 0x1f) | |
1530 | #define b5s5_reg(x) (((x) >> 5) & 0x1f) | |
1531 | #define b6s4_op(x) (((x) >> 6) & 0xf) | |
1532 | #define b7s3_reg(x) (((x) >> 7) & 0x7) | |
1533 | ||
1534 | /* 32-bit instruction formats, B and S refer to the lowest bit and the size | |
1535 | respectively of the field extracted. */ | |
1536 | #define b0s6_op(x) ((x) & 0x3f) | |
1537 | #define b0s11_op(x) ((x) & 0x7ff) | |
1538 | #define b0s12_imm(x) ((x) & 0xfff) | |
1539 | #define b0s16_imm(x) ((x) & 0xffff) | |
1540 | #define b0s26_imm(x) ((x) & 0x3ffffff) | |
1541 | #define b6s10_ext(x) (((x) >> 6) & 0x3ff) | |
1542 | #define b11s5_reg(x) (((x) >> 11) & 0x1f) | |
1543 | #define b12s4_op(x) (((x) >> 12) & 0xf) | |
1544 | ||
1545 | /* Return the size in bytes of the instruction INSN encoded in the ISA | |
1546 | instruction set. */ | |
1547 | ||
1548 | static int | |
1549 | mips_insn_size (enum mips_isa isa, ULONGEST insn) | |
1550 | { | |
1551 | switch (isa) | |
1552 | { | |
1553 | case ISA_MICROMIPS: | |
100b4f2e MR |
1554 | if ((micromips_op (insn) & 0x4) == 0x4 |
1555 | || (micromips_op (insn) & 0x7) == 0x0) | |
dda83cd7 | 1556 | return 2 * MIPS_INSN16_SIZE; |
4cc0665f | 1557 | else |
dda83cd7 | 1558 | return MIPS_INSN16_SIZE; |
4cc0665f MR |
1559 | case ISA_MIPS16: |
1560 | if ((insn & 0xf800) == 0xf000) | |
1561 | return 2 * MIPS_INSN16_SIZE; | |
1562 | else | |
1563 | return MIPS_INSN16_SIZE; | |
1564 | case ISA_MIPS: | |
1565 | return MIPS_INSN32_SIZE; | |
1566 | } | |
f34652de | 1567 | internal_error (_("invalid ISA")); |
4cc0665f MR |
1568 | } |
1569 | ||
06987e64 MK |
1570 | static LONGEST |
1571 | mips32_relative_offset (ULONGEST inst) | |
c5aa993b | 1572 | { |
06987e64 | 1573 | return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
c906108c SS |
1574 | } |
1575 | ||
a385295e MR |
1576 | /* Determine the address of the next instruction executed after the INST |
1577 | floating condition branch instruction at PC. COUNT specifies the | |
1578 | number of the floating condition bits tested by the branch. */ | |
1579 | ||
1580 | static CORE_ADDR | |
7113a196 | 1581 | mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
a385295e MR |
1582 | ULONGEST inst, CORE_ADDR pc, int count) |
1583 | { | |
1584 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1585 | int cnum = (itype_rt (inst) >> 2) & (count - 1); | |
1586 | int tf = itype_rt (inst) & 1; | |
1587 | int mask = (1 << count) - 1; | |
1588 | ULONGEST fcs; | |
1589 | int cond; | |
1590 | ||
1591 | if (fcsr == -1) | |
1592 | /* No way to handle; it'll most likely trap anyway. */ | |
1593 | return pc; | |
1594 | ||
7113a196 | 1595 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
a385295e MR |
1596 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1597 | ||
1598 | if (((cond >> cnum) & mask) != mask * !tf) | |
1599 | pc += mips32_relative_offset (inst); | |
1600 | else | |
1601 | pc += 4; | |
1602 | ||
1603 | return pc; | |
1604 | } | |
1605 | ||
f94363d7 AP |
1606 | /* Return nonzero if the gdbarch is an Octeon series. */ |
1607 | ||
1608 | static int | |
1609 | is_octeon (struct gdbarch *gdbarch) | |
1610 | { | |
1611 | const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); | |
1612 | ||
1613 | return (info->mach == bfd_mach_mips_octeon | |
dda83cd7 SM |
1614 | || info->mach == bfd_mach_mips_octeonp |
1615 | || info->mach == bfd_mach_mips_octeon2); | |
f94363d7 AP |
1616 | } |
1617 | ||
1618 | /* Return true if the OP represents the Octeon's BBIT instruction. */ | |
1619 | ||
1620 | static int | |
1621 | is_octeon_bbit_op (int op, struct gdbarch *gdbarch) | |
1622 | { | |
1623 | if (!is_octeon (gdbarch)) | |
1624 | return 0; | |
1625 | /* BBIT0 is encoded as LWC2: 110 010. */ | |
1626 | /* BBIT032 is encoded as LDC2: 110 110. */ | |
1627 | /* BBIT1 is encoded as SWC2: 111 010. */ | |
1628 | /* BBIT132 is encoded as SDC2: 111 110. */ | |
1629 | if (op == 50 || op == 54 || op == 58 || op == 62) | |
1630 | return 1; | |
1631 | return 0; | |
1632 | } | |
1633 | ||
1634 | ||
f49e4e6d MS |
1635 | /* Determine where to set a single step breakpoint while considering |
1636 | branch prediction. */ | |
78a59c2f | 1637 | |
5a89d8aa | 1638 | static CORE_ADDR |
7113a196 | 1639 | mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c5aa993b | 1640 | { |
ac7936df | 1641 | struct gdbarch *gdbarch = regcache->arch (); |
c5aa993b JM |
1642 | unsigned long inst; |
1643 | int op; | |
4cc0665f | 1644 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
4f5bcb50 | 1645 | op = itype_op (inst); |
025bb325 MS |
1646 | if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1647 | instruction. */ | |
c5aa993b | 1648 | { |
4f5bcb50 | 1649 | if (op >> 2 == 5) |
6d82d43b | 1650 | /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
c5aa993b | 1651 | { |
4f5bcb50 | 1652 | switch (op & 0x03) |
c906108c | 1653 | { |
e135b889 DJ |
1654 | case 0: /* BEQL */ |
1655 | goto equal_branch; | |
1656 | case 1: /* BNEL */ | |
1657 | goto neq_branch; | |
1658 | case 2: /* BLEZL */ | |
1659 | goto less_branch; | |
313628cc | 1660 | case 3: /* BGTZL */ |
e135b889 | 1661 | goto greater_branch; |
c5aa993b JM |
1662 | default: |
1663 | pc += 4; | |
c906108c SS |
1664 | } |
1665 | } | |
4f5bcb50 | 1666 | else if (op == 17 && itype_rs (inst) == 8) |
6d82d43b | 1667 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
7113a196 | 1668 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); |
4f5bcb50 | 1669 | else if (op == 17 && itype_rs (inst) == 9 |
a385295e MR |
1670 | && (itype_rt (inst) & 2) == 0) |
1671 | /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ | |
7113a196 | 1672 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); |
4f5bcb50 | 1673 | else if (op == 17 && itype_rs (inst) == 10 |
a385295e MR |
1674 | && (itype_rt (inst) & 2) == 0) |
1675 | /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ | |
7113a196 | 1676 | pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); |
4f5bcb50 | 1677 | else if (op == 29) |
9e8da49c MR |
1678 | /* JALX: 011101 */ |
1679 | /* The new PC will be alternate mode. */ | |
1680 | { | |
1681 | unsigned long reg; | |
1682 | ||
1683 | reg = jtype_target (inst) << 2; | |
1684 | /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ | |
1685 | pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; | |
1686 | } | |
f94363d7 AP |
1687 | else if (is_octeon_bbit_op (op, gdbarch)) |
1688 | { | |
1689 | int bit, branch_if; | |
1690 | ||
1691 | branch_if = op == 58 || op == 62; | |
1692 | bit = itype_rt (inst); | |
1693 | ||
1694 | /* Take into account the *32 instructions. */ | |
1695 | if (op == 54 || op == 62) | |
1696 | bit += 32; | |
1697 | ||
7113a196 YQ |
1698 | if (((regcache_raw_get_signed (regcache, |
1699 | itype_rs (inst)) >> bit) & 1) | |
dda83cd7 | 1700 | == branch_if) |
f94363d7 | 1701 | pc += mips32_relative_offset (inst) + 4; |
dda83cd7 | 1702 | else |
f94363d7 AP |
1703 | pc += 8; /* After the delay slot. */ |
1704 | } | |
1705 | ||
c5aa993b | 1706 | else |
025bb325 | 1707 | pc += 4; /* Not a branch, next instruction is easy. */ |
c906108c SS |
1708 | } |
1709 | else | |
025bb325 | 1710 | { /* This gets way messy. */ |
c5aa993b | 1711 | |
025bb325 | 1712 | /* Further subdivide into SPECIAL, REGIMM and other. */ |
4f5bcb50 | 1713 | switch (op & 0x07) /* Extract bits 28,27,26. */ |
c906108c | 1714 | { |
c5aa993b JM |
1715 | case 0: /* SPECIAL */ |
1716 | op = rtype_funct (inst); | |
1717 | switch (op) | |
1718 | { | |
1719 | case 8: /* JR */ | |
1720 | case 9: /* JALR */ | |
025bb325 | 1721 | /* Set PC to that address. */ |
7113a196 | 1722 | pc = regcache_raw_get_signed (regcache, rtype_rs (inst)); |
c5aa993b | 1723 | break; |
e38d4e1a DJ |
1724 | case 12: /* SYSCALL */ |
1725 | { | |
345bd07c | 1726 | mips_gdbarch_tdep *tdep |
08106042 | 1727 | = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
e38d4e1a | 1728 | |
e38d4e1a | 1729 | if (tdep->syscall_next_pc != NULL) |
7113a196 | 1730 | pc = tdep->syscall_next_pc (get_current_frame ()); |
e38d4e1a DJ |
1731 | else |
1732 | pc += 4; | |
1733 | } | |
1734 | break; | |
c5aa993b JM |
1735 | default: |
1736 | pc += 4; | |
1737 | } | |
1738 | ||
6d82d43b | 1739 | break; /* end SPECIAL */ |
025bb325 | 1740 | case 1: /* REGIMM */ |
c906108c | 1741 | { |
e135b889 DJ |
1742 | op = itype_rt (inst); /* branch condition */ |
1743 | switch (op) | |
c906108c | 1744 | { |
c5aa993b | 1745 | case 0: /* BLTZ */ |
e135b889 DJ |
1746 | case 2: /* BLTZL */ |
1747 | case 16: /* BLTZAL */ | |
c5aa993b | 1748 | case 18: /* BLTZALL */ |
c906108c | 1749 | less_branch: |
7113a196 | 1750 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0) |
c5aa993b JM |
1751 | pc += mips32_relative_offset (inst) + 4; |
1752 | else | |
1753 | pc += 8; /* after the delay slot */ | |
1754 | break; | |
e135b889 | 1755 | case 1: /* BGEZ */ |
c5aa993b JM |
1756 | case 3: /* BGEZL */ |
1757 | case 17: /* BGEZAL */ | |
1758 | case 19: /* BGEZALL */ | |
7113a196 | 1759 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0) |
c5aa993b JM |
1760 | pc += mips32_relative_offset (inst) + 4; |
1761 | else | |
1762 | pc += 8; /* after the delay slot */ | |
1763 | break; | |
a385295e MR |
1764 | case 0x1c: /* BPOSGE32 */ |
1765 | case 0x1e: /* BPOSGE64 */ | |
1766 | pc += 4; | |
1767 | if (itype_rs (inst) == 0) | |
1768 | { | |
1769 | unsigned int pos = (op & 2) ? 64 : 32; | |
1770 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
1771 | ||
1772 | if (dspctl == -1) | |
1773 | /* No way to handle; it'll most likely trap anyway. */ | |
1774 | break; | |
1775 | ||
7113a196 YQ |
1776 | if ((regcache_raw_get_unsigned (regcache, |
1777 | dspctl) & 0x7f) >= pos) | |
a385295e MR |
1778 | pc += mips32_relative_offset (inst); |
1779 | else | |
1780 | pc += 4; | |
1781 | } | |
1782 | break; | |
e135b889 | 1783 | /* All of the other instructions in the REGIMM category */ |
c5aa993b JM |
1784 | default: |
1785 | pc += 4; | |
c906108c SS |
1786 | } |
1787 | } | |
6d82d43b | 1788 | break; /* end REGIMM */ |
c5aa993b JM |
1789 | case 2: /* J */ |
1790 | case 3: /* JAL */ | |
1791 | { | |
1792 | unsigned long reg; | |
1793 | reg = jtype_target (inst) << 2; | |
025bb325 | 1794 | /* Upper four bits get never changed... */ |
5b652102 | 1795 | pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
c906108c | 1796 | } |
c5aa993b | 1797 | break; |
e135b889 | 1798 | case 4: /* BEQ, BEQL */ |
c5aa993b | 1799 | equal_branch: |
7113a196 YQ |
1800 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) == |
1801 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1802 | pc += mips32_relative_offset (inst) + 4; |
1803 | else | |
1804 | pc += 8; | |
1805 | break; | |
e135b889 | 1806 | case 5: /* BNE, BNEL */ |
c5aa993b | 1807 | neq_branch: |
7113a196 YQ |
1808 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) != |
1809 | regcache_raw_get_signed (regcache, itype_rt (inst))) | |
c5aa993b JM |
1810 | pc += mips32_relative_offset (inst) + 4; |
1811 | else | |
1812 | pc += 8; | |
1813 | break; | |
e135b889 | 1814 | case 6: /* BLEZ, BLEZL */ |
7113a196 | 1815 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0) |
c5aa993b JM |
1816 | pc += mips32_relative_offset (inst) + 4; |
1817 | else | |
1818 | pc += 8; | |
1819 | break; | |
1820 | case 7: | |
e135b889 DJ |
1821 | default: |
1822 | greater_branch: /* BGTZ, BGTZL */ | |
7113a196 | 1823 | if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) |
c5aa993b JM |
1824 | pc += mips32_relative_offset (inst) + 4; |
1825 | else | |
1826 | pc += 8; | |
1827 | break; | |
c5aa993b JM |
1828 | } /* switch */ |
1829 | } /* else */ | |
1830 | return pc; | |
1831 | } /* mips32_next_pc */ | |
c906108c | 1832 | |
4cc0665f MR |
1833 | /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
1834 | INSN. */ | |
1835 | ||
1836 | static LONGEST | |
1837 | micromips_relative_offset7 (ULONGEST insn) | |
1838 | { | |
1839 | return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; | |
1840 | } | |
1841 | ||
1842 | /* Extract the 10-bit signed immediate offset from the microMIPS instruction | |
1843 | INSN. */ | |
1844 | ||
1845 | static LONGEST | |
1846 | micromips_relative_offset10 (ULONGEST insn) | |
1847 | { | |
1848 | return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; | |
1849 | } | |
1850 | ||
1851 | /* Extract the 16-bit signed immediate offset from the microMIPS instruction | |
1852 | INSN. */ | |
1853 | ||
1854 | static LONGEST | |
1855 | micromips_relative_offset16 (ULONGEST insn) | |
1856 | { | |
1857 | return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; | |
1858 | } | |
1859 | ||
1860 | /* Return the size in bytes of the microMIPS instruction at the address PC. */ | |
1861 | ||
1862 | static int | |
1863 | micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1864 | { | |
1865 | ULONGEST insn; | |
1866 | ||
1867 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1868 | return mips_insn_size (ISA_MICROMIPS, insn); | |
1869 | } | |
1870 | ||
1871 | /* Calculate the address of the next microMIPS instruction to execute | |
1872 | after the INSN coprocessor 1 conditional branch instruction at the | |
1873 | address PC. COUNT denotes the number of coprocessor condition bits | |
1874 | examined by the branch. */ | |
1875 | ||
1876 | static CORE_ADDR | |
7113a196 | 1877 | micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, |
4cc0665f MR |
1878 | ULONGEST insn, CORE_ADDR pc, int count) |
1879 | { | |
1880 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
1881 | int cnum = b2s3_cc (insn >> 16) & (count - 1); | |
1882 | int tf = b5s5_op (insn >> 16) & 1; | |
1883 | int mask = (1 << count) - 1; | |
1884 | ULONGEST fcs; | |
1885 | int cond; | |
1886 | ||
1887 | if (fcsr == -1) | |
1888 | /* No way to handle; it'll most likely trap anyway. */ | |
1889 | return pc; | |
1890 | ||
7113a196 | 1891 | fcs = regcache_raw_get_unsigned (regcache, fcsr); |
4cc0665f MR |
1892 | cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
1893 | ||
1894 | if (((cond >> cnum) & mask) != mask * !tf) | |
1895 | pc += micromips_relative_offset16 (insn); | |
1896 | else | |
1897 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1898 | ||
1899 | return pc; | |
1900 | } | |
1901 | ||
1902 | /* Calculate the address of the next microMIPS instruction to execute | |
1903 | after the instruction at the address PC. */ | |
1904 | ||
1905 | static CORE_ADDR | |
7113a196 | 1906 | micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
4cc0665f | 1907 | { |
ac7936df | 1908 | struct gdbarch *gdbarch = regcache->arch (); |
4cc0665f MR |
1909 | ULONGEST insn; |
1910 | ||
1911 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1912 | pc += MIPS_INSN16_SIZE; | |
1913 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
1914 | { | |
4cc0665f MR |
1915 | /* 32-bit instructions. */ |
1916 | case 2 * MIPS_INSN16_SIZE: | |
1917 | insn <<= 16; | |
1918 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
1919 | pc += MIPS_INSN16_SIZE; | |
1920 | switch (micromips_op (insn >> 16)) | |
1921 | { | |
1922 | case 0x00: /* POOL32A: bits 000000 */ | |
6592ceed MR |
1923 | switch (b0s6_op (insn)) |
1924 | { | |
1925 | case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */ | |
1926 | switch (b6s10_ext (insn)) | |
1927 | { | |
1928 | case 0x3c: /* JALR: 000000 0000111100 111100 */ | |
1929 | case 0x7c: /* JALR.HB: 000000 0001111100 111100 */ | |
1930 | case 0x13c: /* JALRS: 000000 0100111100 111100 */ | |
1931 | case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */ | |
1932 | pc = regcache_raw_get_signed (regcache, | |
1933 | b0s5_reg (insn >> 16)); | |
1934 | break; | |
1935 | case 0x22d: /* SYSCALL: 000000 1000101101 111100 */ | |
1936 | { | |
345bd07c | 1937 | mips_gdbarch_tdep *tdep |
08106042 | 1938 | = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
6592ceed | 1939 | |
6592ceed MR |
1940 | if (tdep->syscall_next_pc != NULL) |
1941 | pc = tdep->syscall_next_pc (get_current_frame ()); | |
1942 | } | |
1943 | break; | |
1944 | } | |
1945 | break; | |
1946 | } | |
4cc0665f MR |
1947 | break; |
1948 | ||
1949 | case 0x10: /* POOL32I: bits 010000 */ | |
1950 | switch (b5s5_op (insn >> 16)) | |
1951 | { | |
1952 | case 0x00: /* BLTZ: bits 010000 00000 */ | |
1953 | case 0x01: /* BLTZAL: bits 010000 00001 */ | |
1954 | case 0x11: /* BLTZALS: bits 010000 10001 */ | |
7113a196 YQ |
1955 | if (regcache_raw_get_signed (regcache, |
1956 | b0s5_reg (insn >> 16)) < 0) | |
4cc0665f MR |
1957 | pc += micromips_relative_offset16 (insn); |
1958 | else | |
1959 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1960 | break; | |
1961 | ||
1962 | case 0x02: /* BGEZ: bits 010000 00010 */ | |
1963 | case 0x03: /* BGEZAL: bits 010000 00011 */ | |
1964 | case 0x13: /* BGEZALS: bits 010000 10011 */ | |
7113a196 YQ |
1965 | if (regcache_raw_get_signed (regcache, |
1966 | b0s5_reg (insn >> 16)) >= 0) | |
4cc0665f MR |
1967 | pc += micromips_relative_offset16 (insn); |
1968 | else | |
1969 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1970 | break; | |
1971 | ||
1972 | case 0x04: /* BLEZ: bits 010000 00100 */ | |
7113a196 YQ |
1973 | if (regcache_raw_get_signed (regcache, |
1974 | b0s5_reg (insn >> 16)) <= 0) | |
4cc0665f MR |
1975 | pc += micromips_relative_offset16 (insn); |
1976 | else | |
1977 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1978 | break; | |
1979 | ||
1980 | case 0x05: /* BNEZC: bits 010000 00101 */ | |
7113a196 YQ |
1981 | if (regcache_raw_get_signed (regcache, |
1982 | b0s5_reg (insn >> 16)) != 0) | |
4cc0665f MR |
1983 | pc += micromips_relative_offset16 (insn); |
1984 | break; | |
1985 | ||
1986 | case 0x06: /* BGTZ: bits 010000 00110 */ | |
7113a196 YQ |
1987 | if (regcache_raw_get_signed (regcache, |
1988 | b0s5_reg (insn >> 16)) > 0) | |
4cc0665f MR |
1989 | pc += micromips_relative_offset16 (insn); |
1990 | else | |
1991 | pc += micromips_pc_insn_size (gdbarch, pc); | |
1992 | break; | |
1993 | ||
1994 | case 0x07: /* BEQZC: bits 010000 00111 */ | |
7113a196 YQ |
1995 | if (regcache_raw_get_signed (regcache, |
1996 | b0s5_reg (insn >> 16)) == 0) | |
4cc0665f MR |
1997 | pc += micromips_relative_offset16 (insn); |
1998 | break; | |
1999 | ||
2000 | case 0x14: /* BC2F: bits 010000 10100 xxx00 */ | |
2001 | case 0x15: /* BC2T: bits 010000 10101 xxx00 */ | |
2002 | if (((insn >> 16) & 0x3) == 0x0) | |
2003 | /* BC2F, BC2T: don't know how to handle these. */ | |
2004 | break; | |
2005 | break; | |
2006 | ||
2007 | case 0x1a: /* BPOSGE64: bits 010000 11010 */ | |
2008 | case 0x1b: /* BPOSGE32: bits 010000 11011 */ | |
2009 | { | |
2010 | unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; | |
2011 | int dspctl = mips_regnum (gdbarch)->dspctl; | |
2012 | ||
2013 | if (dspctl == -1) | |
2014 | /* No way to handle; it'll most likely trap anyway. */ | |
2015 | break; | |
2016 | ||
7113a196 YQ |
2017 | if ((regcache_raw_get_unsigned (regcache, |
2018 | dspctl) & 0x7f) >= pos) | |
4cc0665f MR |
2019 | pc += micromips_relative_offset16 (insn); |
2020 | else | |
2021 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2022 | } | |
2023 | break; | |
2024 | ||
2025 | case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ | |
2026 | /* BC1ANY2F: bits 010000 11100 xxx01 */ | |
2027 | case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ | |
2028 | /* BC1ANY2T: bits 010000 11101 xxx01 */ | |
2029 | if (((insn >> 16) & 0x2) == 0x0) | |
7113a196 | 2030 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, |
4cc0665f MR |
2031 | ((insn >> 16) & 0x1) + 1); |
2032 | break; | |
2033 | ||
2034 | case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ | |
2035 | case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ | |
2036 | if (((insn >> 16) & 0x3) == 0x1) | |
7113a196 | 2037 | pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 4); |
4cc0665f MR |
2038 | break; |
2039 | } | |
2040 | break; | |
2041 | ||
2042 | case 0x1d: /* JALS: bits 011101 */ | |
2043 | case 0x35: /* J: bits 110101 */ | |
2044 | case 0x3d: /* JAL: bits 111101 */ | |
2045 | pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); | |
2046 | break; | |
2047 | ||
2048 | case 0x25: /* BEQ: bits 100101 */ | |
7113a196 YQ |
2049 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
2050 | == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f MR |
2051 | pc += micromips_relative_offset16 (insn); |
2052 | else | |
2053 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2054 | break; | |
2055 | ||
2056 | case 0x2d: /* BNE: bits 101101 */ | |
7113a196 YQ |
2057 | if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) |
2058 | != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) | |
4cc0665f | 2059 | pc += micromips_relative_offset16 (insn); |
492325c4 | 2060 | else |
4cc0665f MR |
2061 | pc += micromips_pc_insn_size (gdbarch, pc); |
2062 | break; | |
2063 | ||
2064 | case 0x3c: /* JALX: bits 111100 */ | |
2065 | pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); | |
2066 | break; | |
2067 | } | |
2068 | break; | |
2069 | ||
2070 | /* 16-bit instructions. */ | |
2071 | case MIPS_INSN16_SIZE: | |
2072 | switch (micromips_op (insn)) | |
2073 | { | |
2074 | case 0x11: /* POOL16C: bits 010001 */ | |
2075 | if ((b5s5_op (insn) & 0x1c) == 0xc) | |
2076 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
7113a196 | 2077 | pc = regcache_raw_get_signed (regcache, b0s5_reg (insn)); |
4cc0665f MR |
2078 | else if (b5s5_op (insn) == 0x18) |
2079 | /* JRADDIUSP: bits 010001 11000 */ | |
7113a196 | 2080 | pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM); |
4cc0665f MR |
2081 | break; |
2082 | ||
2083 | case 0x23: /* BEQZ16: bits 100011 */ | |
2084 | { | |
2085 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2086 | ||
7113a196 | 2087 | if (regcache_raw_get_signed (regcache, rs) == 0) |
4cc0665f MR |
2088 | pc += micromips_relative_offset7 (insn); |
2089 | else | |
2090 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2091 | } | |
2092 | break; | |
2093 | ||
2094 | case 0x2b: /* BNEZ16: bits 101011 */ | |
2095 | { | |
2096 | int rs = mips_reg3_to_reg[b7s3_reg (insn)]; | |
2097 | ||
7113a196 | 2098 | if (regcache_raw_get_signed (regcache, rs) != 0) |
4cc0665f MR |
2099 | pc += micromips_relative_offset7 (insn); |
2100 | else | |
2101 | pc += micromips_pc_insn_size (gdbarch, pc); | |
2102 | } | |
2103 | break; | |
2104 | ||
2105 | case 0x33: /* B16: bits 110011 */ | |
2106 | pc += micromips_relative_offset10 (insn); | |
2107 | break; | |
2108 | } | |
2109 | break; | |
2110 | } | |
2111 | ||
2112 | return pc; | |
2113 | } | |
2114 | ||
c906108c | 2115 | /* Decoding the next place to set a breakpoint is irregular for the |
025bb325 MS |
2116 | mips 16 variant, but fortunately, there fewer instructions. We have |
2117 | to cope ith extensions for 16 bit instructions and a pair of actual | |
2118 | 32 bit instructions. We dont want to set a single step instruction | |
2119 | on the extend instruction either. */ | |
c906108c SS |
2120 | |
2121 | /* Lots of mips16 instruction formats */ | |
2122 | /* Predicting jumps requires itype,ritype,i8type | |
025bb325 | 2123 | and their extensions extItype,extritype,extI8type. */ |
c906108c SS |
2124 | enum mips16_inst_fmts |
2125 | { | |
c5aa993b JM |
2126 | itype, /* 0 immediate 5,10 */ |
2127 | ritype, /* 1 5,3,8 */ | |
2128 | rrtype, /* 2 5,3,3,5 */ | |
2129 | rritype, /* 3 5,3,3,5 */ | |
2130 | rrrtype, /* 4 5,3,3,3,2 */ | |
2131 | rriatype, /* 5 5,3,3,1,4 */ | |
2132 | shifttype, /* 6 5,3,3,3,2 */ | |
2133 | i8type, /* 7 5,3,8 */ | |
2134 | i8movtype, /* 8 5,3,3,5 */ | |
2135 | i8mov32rtype, /* 9 5,3,5,3 */ | |
2136 | i64type, /* 10 5,3,8 */ | |
2137 | ri64type, /* 11 5,3,3,5 */ | |
2138 | jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ | |
2139 | exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ | |
2140 | extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ | |
2141 | extRRItype, /* 15 5,5,5,5,3,3,5 */ | |
2142 | extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ | |
2143 | EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ | |
2144 | extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ | |
2145 | extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ | |
2146 | extRi64type, /* 20 5,6,5,5,3,3,5 */ | |
2147 | extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ | |
2148 | }; | |
12f02c2a | 2149 | /* I am heaping all the fields of the formats into one structure and |
025bb325 | 2150 | then, only the fields which are involved in instruction extension. */ |
c906108c | 2151 | struct upk_mips16 |
6d82d43b AC |
2152 | { |
2153 | CORE_ADDR offset; | |
025bb325 | 2154 | unsigned int regx; /* Function in i8 type. */ |
6d82d43b AC |
2155 | unsigned int regy; |
2156 | }; | |
c906108c SS |
2157 | |
2158 | ||
12f02c2a | 2159 | /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format |
c68cf8ad | 2160 | for the bits which make up the immediate extension. */ |
c906108c | 2161 | |
12f02c2a AC |
2162 | static CORE_ADDR |
2163 | extended_offset (unsigned int extension) | |
c906108c | 2164 | { |
12f02c2a | 2165 | CORE_ADDR value; |
130854df | 2166 | |
4c2051c6 | 2167 | value = (extension >> 16) & 0x1f; /* Extract 15:11. */ |
c5aa993b | 2168 | value = value << 6; |
4c2051c6 | 2169 | value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ |
c5aa993b | 2170 | value = value << 5; |
130854df MR |
2171 | value |= extension & 0x1f; /* Extract 4:0. */ |
2172 | ||
c5aa993b | 2173 | return value; |
c906108c SS |
2174 | } |
2175 | ||
2176 | /* Only call this function if you know that this is an extendable | |
bcf1ea1e MR |
2177 | instruction. It won't malfunction, but why make excess remote memory |
2178 | references? If the immediate operands get sign extended or something, | |
2179 | do it after the extension is performed. */ | |
c906108c | 2180 | /* FIXME: Every one of these cases needs to worry about sign extension |
bcf1ea1e | 2181 | when the offset is to be used in relative addressing. */ |
c906108c | 2182 | |
12f02c2a | 2183 | static unsigned int |
e17a4113 | 2184 | fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) |
c906108c | 2185 | { |
e17a4113 | 2186 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
47a35522 | 2187 | gdb_byte buf[8]; |
a2fb2cee MR |
2188 | |
2189 | pc = unmake_compact_addr (pc); /* Clear the low order bit. */ | |
c5aa993b | 2190 | target_read_memory (pc, buf, 2); |
e17a4113 | 2191 | return extract_unsigned_integer (buf, 2, byte_order); |
c906108c SS |
2192 | } |
2193 | ||
2194 | static void | |
e17a4113 | 2195 | unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, |
12f02c2a AC |
2196 | unsigned int extension, |
2197 | unsigned int inst, | |
6d82d43b | 2198 | enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) |
c906108c | 2199 | { |
12f02c2a AC |
2200 | CORE_ADDR offset; |
2201 | int regx; | |
2202 | int regy; | |
2203 | switch (insn_format) | |
c906108c | 2204 | { |
c5aa993b | 2205 | case itype: |
c906108c | 2206 | { |
12f02c2a AC |
2207 | CORE_ADDR value; |
2208 | if (extension) | |
c5aa993b | 2209 | { |
4c2051c6 MR |
2210 | value = extended_offset ((extension << 16) | inst); |
2211 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c SS |
2212 | } |
2213 | else | |
c5aa993b | 2214 | { |
12f02c2a | 2215 | value = inst & 0x7ff; |
4c2051c6 | 2216 | value = (value ^ 0x400) - 0x400; /* Sign-extend. */ |
c906108c | 2217 | } |
12f02c2a AC |
2218 | offset = value; |
2219 | regx = -1; | |
2220 | regy = -1; | |
c906108c | 2221 | } |
c5aa993b JM |
2222 | break; |
2223 | case ritype: | |
2224 | case i8type: | |
025bb325 | 2225 | { /* A register identifier and an offset. */ |
c906108c | 2226 | /* Most of the fields are the same as I type but the |
025bb325 | 2227 | immediate value is of a different length. */ |
12f02c2a AC |
2228 | CORE_ADDR value; |
2229 | if (extension) | |
c906108c | 2230 | { |
4c2051c6 MR |
2231 | value = extended_offset ((extension << 16) | inst); |
2232 | value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ | |
c906108c | 2233 | } |
c5aa993b JM |
2234 | else |
2235 | { | |
4c2051c6 MR |
2236 | value = inst & 0xff; /* 8 bits */ |
2237 | value = (value ^ 0x80) - 0x80; /* Sign-extend. */ | |
c5aa993b | 2238 | } |
12f02c2a | 2239 | offset = value; |
4c2051c6 | 2240 | regx = (inst >> 8) & 0x07; /* i8 funct */ |
12f02c2a | 2241 | regy = -1; |
c5aa993b | 2242 | break; |
c906108c | 2243 | } |
c5aa993b | 2244 | case jalxtype: |
c906108c | 2245 | { |
c5aa993b | 2246 | unsigned long value; |
12f02c2a AC |
2247 | unsigned int nexthalf; |
2248 | value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | |
c5aa993b | 2249 | value = value << 16; |
4cc0665f MR |
2250 | nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
2251 | /* Low bit still set. */ | |
c5aa993b | 2252 | value |= nexthalf; |
12f02c2a AC |
2253 | offset = value; |
2254 | regx = -1; | |
2255 | regy = -1; | |
c5aa993b | 2256 | break; |
c906108c SS |
2257 | } |
2258 | default: | |
f34652de | 2259 | internal_error (_("bad switch")); |
c906108c | 2260 | } |
12f02c2a AC |
2261 | upk->offset = offset; |
2262 | upk->regx = regx; | |
2263 | upk->regy = regy; | |
c906108c SS |
2264 | } |
2265 | ||
2266 | ||
484933d1 MR |
2267 | /* Calculate the destination of a branch whose 16-bit opcode word is at PC, |
2268 | and having a signed 16-bit OFFSET. */ | |
2269 | ||
c5aa993b JM |
2270 | static CORE_ADDR |
2271 | add_offset_16 (CORE_ADDR pc, int offset) | |
c906108c | 2272 | { |
484933d1 | 2273 | return pc + (offset << 1) + 2; |
c906108c SS |
2274 | } |
2275 | ||
12f02c2a | 2276 | static CORE_ADDR |
7113a196 | 2277 | extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, |
6d82d43b | 2278 | unsigned int extension, unsigned int insn) |
c906108c | 2279 | { |
ac7936df | 2280 | struct gdbarch *gdbarch = regcache->arch (); |
12f02c2a AC |
2281 | int op = (insn >> 11); |
2282 | switch (op) | |
c906108c | 2283 | { |
6d82d43b | 2284 | case 2: /* Branch */ |
12f02c2a | 2285 | { |
12f02c2a | 2286 | struct upk_mips16 upk; |
e17a4113 | 2287 | unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
484933d1 | 2288 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2289 | break; |
2290 | } | |
025bb325 MS |
2291 | case 3: /* JAL , JALX - Watch out, these are 32 bit |
2292 | instructions. */ | |
12f02c2a AC |
2293 | { |
2294 | struct upk_mips16 upk; | |
e17a4113 | 2295 | unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
484933d1 | 2296 | pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); |
12f02c2a | 2297 | if ((insn >> 10) & 0x01) /* Exchange mode */ |
025bb325 | 2298 | pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
12f02c2a AC |
2299 | else |
2300 | pc |= 0x01; | |
2301 | break; | |
2302 | } | |
6d82d43b | 2303 | case 4: /* beqz */ |
12f02c2a AC |
2304 | { |
2305 | struct upk_mips16 upk; | |
2306 | int reg; | |
e17a4113 | 2307 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2308 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2309 | if (reg == 0) |
484933d1 | 2310 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2311 | else |
2312 | pc += 2; | |
2313 | break; | |
2314 | } | |
6d82d43b | 2315 | case 5: /* bnez */ |
12f02c2a AC |
2316 | { |
2317 | struct upk_mips16 upk; | |
2318 | int reg; | |
e17a4113 | 2319 | unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
7113a196 | 2320 | reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); |
12f02c2a | 2321 | if (reg != 0) |
484933d1 | 2322 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2323 | else |
2324 | pc += 2; | |
2325 | break; | |
2326 | } | |
6d82d43b | 2327 | case 12: /* I8 Formats btez btnez */ |
12f02c2a AC |
2328 | { |
2329 | struct upk_mips16 upk; | |
2330 | int reg; | |
e17a4113 | 2331 | unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); |
12f02c2a | 2332 | /* upk.regx contains the opcode */ |
7113a196 YQ |
2333 | /* Test register is 24 */ |
2334 | reg = regcache_raw_get_signed (regcache, 24); | |
12f02c2a AC |
2335 | if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ |
2336 | || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ | |
484933d1 | 2337 | pc = add_offset_16 (pc, upk.offset); |
12f02c2a AC |
2338 | else |
2339 | pc += 2; | |
2340 | break; | |
2341 | } | |
6d82d43b | 2342 | case 29: /* RR Formats JR, JALR, JALR-RA */ |
12f02c2a AC |
2343 | { |
2344 | struct upk_mips16 upk; | |
2345 | /* upk.fmt = rrtype; */ | |
2346 | op = insn & 0x1f; | |
2347 | if (op == 0) | |
c5aa993b | 2348 | { |
12f02c2a AC |
2349 | int reg; |
2350 | upk.regx = (insn >> 8) & 0x07; | |
2351 | upk.regy = (insn >> 5) & 0x07; | |
4c2051c6 | 2352 | if ((upk.regy & 1) == 0) |
4cc0665f | 2353 | reg = mips_reg3_to_reg[upk.regx]; |
4c2051c6 MR |
2354 | else |
2355 | reg = 31; /* Function return instruction. */ | |
7113a196 | 2356 | pc = regcache_raw_get_signed (regcache, reg); |
c906108c | 2357 | } |
12f02c2a | 2358 | else |
c5aa993b | 2359 | pc += 2; |
12f02c2a AC |
2360 | break; |
2361 | } | |
2362 | case 30: | |
2363 | /* This is an instruction extension. Fetch the real instruction | |
dda83cd7 SM |
2364 | (which follows the extension) and decode things based on |
2365 | that. */ | |
12f02c2a AC |
2366 | { |
2367 | pc += 2; | |
7113a196 | 2368 | pc = extended_mips16_next_pc (regcache, pc, insn, |
e17a4113 | 2369 | fetch_mips_16 (gdbarch, pc)); |
12f02c2a AC |
2370 | break; |
2371 | } | |
2372 | default: | |
2373 | { | |
2374 | pc += 2; | |
2375 | break; | |
2376 | } | |
c906108c | 2377 | } |
c5aa993b | 2378 | return pc; |
12f02c2a | 2379 | } |
c906108c | 2380 | |
5a89d8aa | 2381 | static CORE_ADDR |
7113a196 | 2382 | mips16_next_pc (struct regcache *regcache, CORE_ADDR pc) |
12f02c2a | 2383 | { |
ac7936df | 2384 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 2385 | unsigned int insn = fetch_mips_16 (gdbarch, pc); |
7113a196 | 2386 | return extended_mips16_next_pc (regcache, pc, 0, insn); |
12f02c2a AC |
2387 | } |
2388 | ||
2389 | /* The mips_next_pc function supports single_step when the remote | |
7e73cedf | 2390 | target monitor or stub is not developed enough to do a single_step. |
12f02c2a | 2391 | It works by decoding the current instruction and predicting where a |
1aee363c | 2392 | branch will go. This isn't hard because all the data is available. |
4cc0665f | 2393 | The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
ad527d2e | 2394 | static CORE_ADDR |
7113a196 | 2395 | mips_next_pc (struct regcache *regcache, CORE_ADDR pc) |
c906108c | 2396 | { |
ac7936df | 2397 | struct gdbarch *gdbarch = regcache->arch (); |
4cc0665f MR |
2398 | |
2399 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
7113a196 | 2400 | return mips16_next_pc (regcache, pc); |
4cc0665f | 2401 | else if (mips_pc_is_micromips (gdbarch, pc)) |
7113a196 | 2402 | return micromips_next_pc (regcache, pc); |
c5aa993b | 2403 | else |
7113a196 | 2404 | return mips32_next_pc (regcache, pc); |
12f02c2a | 2405 | } |
c906108c | 2406 | |
ab50adb6 MR |
2407 | /* Return non-zero if the MIPS16 instruction INSN is a compact branch |
2408 | or jump. */ | |
2409 | ||
2410 | static int | |
2411 | mips16_instruction_is_compact_branch (unsigned short insn) | |
2412 | { | |
2413 | switch (insn & 0xf800) | |
2414 | { | |
2415 | case 0xe800: | |
2416 | return (insn & 0x009f) == 0x80; /* JALRC/JRC */ | |
2417 | case 0x6000: | |
2418 | return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ | |
2419 | case 0x2800: /* BNEZ */ | |
2420 | case 0x2000: /* BEQZ */ | |
2421 | case 0x1000: /* B */ | |
2422 | return 1; | |
2423 | default: | |
2424 | return 0; | |
2425 | } | |
2426 | } | |
2427 | ||
2428 | /* Return non-zero if the microMIPS instruction INSN is a compact branch | |
2429 | or jump. */ | |
2430 | ||
2431 | static int | |
2432 | micromips_instruction_is_compact_branch (unsigned short insn) | |
2433 | { | |
2434 | switch (micromips_op (insn)) | |
2435 | { | |
2436 | case 0x11: /* POOL16C: bits 010001 */ | |
2437 | return (b5s5_op (insn) == 0x18 | |
2438 | /* JRADDIUSP: bits 010001 11000 */ | |
2439 | || b5s5_op (insn) == 0xd); | |
2440 | /* JRC: bits 010011 01101 */ | |
2441 | case 0x10: /* POOL32I: bits 010000 */ | |
2442 | return (b5s5_op (insn) & 0x1d) == 0x5; | |
2443 | /* BEQZC/BNEZC: bits 010000 001x1 */ | |
2444 | default: | |
2445 | return 0; | |
2446 | } | |
2447 | } | |
2448 | ||
edfae063 AC |
2449 | struct mips_frame_cache |
2450 | { | |
2451 | CORE_ADDR base; | |
098caef4 | 2452 | trad_frame_saved_reg *saved_regs; |
edfae063 AC |
2453 | }; |
2454 | ||
29639122 JB |
2455 | /* Set a register's saved stack address in temp_saved_regs. If an |
2456 | address has already been set for this register, do nothing; this | |
2457 | way we will only recognize the first save of a given register in a | |
2458 | function prologue. | |
eec63939 | 2459 | |
f57d151a UW |
2460 | For simplicity, save the address in both [0 .. gdbarch_num_regs) and |
2461 | [gdbarch_num_regs .. 2*gdbarch_num_regs). | |
2462 | Strictly speaking, only the second range is used as it is only second | |
2463 | range (the ABI instead of ISA registers) that comes into play when finding | |
2464 | saved registers in a frame. */ | |
eec63939 AC |
2465 | |
2466 | static void | |
74ed0bb4 MD |
2467 | set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, |
2468 | int regnum, CORE_ADDR offset) | |
eec63939 | 2469 | { |
29639122 | 2470 | if (this_cache != NULL |
a9a87d35 LM |
2471 | && this_cache->saved_regs[regnum].is_realreg () |
2472 | && this_cache->saved_regs[regnum].realreg () == regnum) | |
29639122 | 2473 | { |
098caef4 LM |
2474 | this_cache->saved_regs[regnum + 0 |
2475 | * gdbarch_num_regs (gdbarch)].set_addr (offset); | |
2476 | this_cache->saved_regs[regnum + 1 | |
2477 | * gdbarch_num_regs (gdbarch)].set_addr (offset); | |
29639122 | 2478 | } |
eec63939 AC |
2479 | } |
2480 | ||
eec63939 | 2481 | |
29639122 JB |
2482 | /* Fetch the immediate value from a MIPS16 instruction. |
2483 | If the previous instruction was an EXTEND, use it to extend | |
2484 | the upper bits of the immediate value. This is a helper function | |
2485 | for mips16_scan_prologue. */ | |
eec63939 | 2486 | |
29639122 JB |
2487 | static int |
2488 | mips16_get_imm (unsigned short prev_inst, /* previous instruction */ | |
2489 | unsigned short inst, /* current instruction */ | |
2490 | int nbits, /* number of bits in imm field */ | |
2491 | int scale, /* scale factor to be applied to imm */ | |
025bb325 | 2492 | int is_signed) /* is the imm field signed? */ |
eec63939 | 2493 | { |
29639122 | 2494 | int offset; |
eec63939 | 2495 | |
29639122 JB |
2496 | if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ |
2497 | { | |
2498 | offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); | |
2499 | if (offset & 0x8000) /* check for negative extend */ | |
2500 | offset = 0 - (0x10000 - (offset & 0xffff)); | |
2501 | return offset | (inst & 0x1f); | |
2502 | } | |
eec63939 | 2503 | else |
29639122 JB |
2504 | { |
2505 | int max_imm = 1 << nbits; | |
2506 | int mask = max_imm - 1; | |
2507 | int sign_bit = max_imm >> 1; | |
45c9dd44 | 2508 | |
29639122 JB |
2509 | offset = inst & mask; |
2510 | if (is_signed && (offset & sign_bit)) | |
2511 | offset = 0 - (max_imm - offset); | |
2512 | return offset * scale; | |
2513 | } | |
2514 | } | |
eec63939 | 2515 | |
65596487 | 2516 | |
29639122 JB |
2517 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
2518 | the associated FRAME_CACHE if not null. | |
2519 | Return the address of the first instruction past the prologue. */ | |
eec63939 | 2520 | |
29639122 | 2521 | static CORE_ADDR |
e17a4113 UW |
2522 | mips16_scan_prologue (struct gdbarch *gdbarch, |
2523 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
bd2b40ac | 2524 | frame_info_ptr this_frame, |
dda83cd7 | 2525 | struct mips_frame_cache *this_cache) |
29639122 | 2526 | { |
ab50adb6 MR |
2527 | int prev_non_prologue_insn = 0; |
2528 | int this_non_prologue_insn; | |
2529 | int non_prologue_insns = 0; | |
2530 | CORE_ADDR prev_pc; | |
29639122 | 2531 | CORE_ADDR cur_pc; |
025bb325 | 2532 | CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ |
29639122 JB |
2533 | CORE_ADDR sp; |
2534 | long frame_offset = 0; /* Size of stack frame. */ | |
2535 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
2536 | int frame_reg = MIPS_SP_REGNUM; | |
025bb325 | 2537 | unsigned short prev_inst = 0; /* saved copy of previous instruction. */ |
29639122 JB |
2538 | unsigned inst = 0; /* current instruction */ |
2539 | unsigned entry_inst = 0; /* the entry instruction */ | |
2207132d | 2540 | unsigned save_inst = 0; /* the save instruction */ |
ab50adb6 MR |
2541 | int prev_delay_slot = 0; |
2542 | int in_delay_slot; | |
29639122 | 2543 | int reg, offset; |
a343eb3c | 2544 | |
29639122 | 2545 | int extend_bytes = 0; |
ab50adb6 MR |
2546 | int prev_extend_bytes = 0; |
2547 | CORE_ADDR end_prologue_addr; | |
a343eb3c | 2548 | |
29639122 | 2549 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
2550 | THIS_FRAME. */ |
2551 | if (this_frame != NULL) | |
2552 | sp = get_frame_register_signed (this_frame, | |
2553 | gdbarch_num_regs (gdbarch) | |
2554 | + MIPS_SP_REGNUM); | |
29639122 JB |
2555 | else |
2556 | sp = 0; | |
eec63939 | 2557 | |
29639122 JB |
2558 | if (limit_pc > start_pc + 200) |
2559 | limit_pc = start_pc + 200; | |
ab50adb6 | 2560 | prev_pc = start_pc; |
eec63939 | 2561 | |
ab50adb6 MR |
2562 | /* Permit at most one non-prologue non-control-transfer instruction |
2563 | in the middle which may have been reordered by the compiler for | |
2564 | optimisation. */ | |
95ac2dcf | 2565 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
29639122 | 2566 | { |
ab50adb6 MR |
2567 | this_non_prologue_insn = 0; |
2568 | in_delay_slot = 0; | |
2569 | ||
29639122 | 2570 | /* Save the previous instruction. If it's an EXTEND, we'll extract |
dda83cd7 | 2571 | the immediate offset extension from it in mips16_get_imm. */ |
29639122 | 2572 | prev_inst = inst; |
eec63939 | 2573 | |
025bb325 | 2574 | /* Fetch and decode the instruction. */ |
4cc0665f MR |
2575 | inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
2576 | cur_pc, NULL); | |
eec63939 | 2577 | |
29639122 | 2578 | /* Normally we ignore extend instructions. However, if it is |
dda83cd7 SM |
2579 | not followed by a valid prologue instruction, then this |
2580 | instruction is not part of the prologue either. We must | |
2581 | remember in this case to adjust the end_prologue_addr back | |
2582 | over the extend. */ | |
29639122 | 2583 | if ((inst & 0xf800) == 0xf000) /* extend */ |
dda83cd7 SM |
2584 | { |
2585 | extend_bytes = MIPS_INSN16_SIZE; | |
2586 | continue; | |
2587 | } | |
eec63939 | 2588 | |
29639122 JB |
2589 | prev_extend_bytes = extend_bytes; |
2590 | extend_bytes = 0; | |
eec63939 | 2591 | |
29639122 JB |
2592 | if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2593 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
2594 | { | |
2595 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); | |
025bb325 | 2596 | if (offset < 0) /* Negative stack adjustment? */ |
29639122 JB |
2597 | frame_offset -= offset; |
2598 | else | |
2599 | /* Exit loop if a positive stack adjustment is found, which | |
2600 | usually means that the stack cleanup code in the function | |
2601 | epilogue is reached. */ | |
2602 | break; | |
2603 | } | |
2604 | else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | |
2605 | { | |
2606 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
4cc0665f | 2607 | reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
74ed0bb4 | 2608 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2609 | } |
2610 | else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | |
2611 | { | |
2612 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2613 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2614 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
2615 | } |
2616 | else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | |
2617 | { | |
2618 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
74ed0bb4 | 2619 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2620 | } |
2621 | else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | |
2622 | { | |
2623 | offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | |
74ed0bb4 | 2624 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
29639122 JB |
2625 | } |
2626 | else if (inst == 0x673d) /* move $s1, $sp */ | |
2627 | { | |
2628 | frame_addr = sp; | |
2629 | frame_reg = 17; | |
2630 | } | |
2631 | else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | |
2632 | { | |
2633 | offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | |
2634 | frame_addr = sp + offset; | |
2635 | frame_reg = 17; | |
2636 | frame_adjust = offset; | |
2637 | } | |
2638 | else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | |
2639 | { | |
2640 | offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | |
4cc0665f | 2641 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2642 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2643 | } |
2644 | else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | |
2645 | { | |
2646 | offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | |
4cc0665f | 2647 | reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
74ed0bb4 | 2648 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
2649 | } |
2650 | else if ((inst & 0xf81f) == 0xe809 | |
dda83cd7 | 2651 | && (inst & 0x700) != 0x700) /* entry */ |
025bb325 | 2652 | entry_inst = inst; /* Save for later processing. */ |
2207132d MR |
2653 | else if ((inst & 0xff80) == 0x6480) /* save */ |
2654 | { | |
025bb325 | 2655 | save_inst = inst; /* Save for later processing. */ |
2207132d MR |
2656 | if (prev_extend_bytes) /* extend */ |
2657 | save_inst |= prev_inst << 16; | |
2658 | } | |
29639122 | 2659 | else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ |
dda83cd7 SM |
2660 | { |
2661 | /* This instruction is part of the prologue, but we don't | |
2662 | need to do anything special to handle it. */ | |
2663 | } | |
ab50adb6 MR |
2664 | else if (mips16_instruction_has_delay_slot (inst, 0)) |
2665 | /* JAL/JALR/JALX/JR */ | |
2666 | { | |
2667 | /* The instruction in the delay slot can be a part | |
2668 | of the prologue, so move forward once more. */ | |
2669 | in_delay_slot = 1; | |
2670 | if (mips16_instruction_has_delay_slot (inst, 1)) | |
2671 | /* JAL/JALX */ | |
2672 | { | |
2673 | prev_extend_bytes = MIPS_INSN16_SIZE; | |
2674 | cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ | |
2675 | } | |
2676 | } | |
29639122 | 2677 | else |
dda83cd7 | 2678 | { |
ab50adb6 | 2679 | this_non_prologue_insn = 1; |
dda83cd7 | 2680 | } |
ab50adb6 MR |
2681 | |
2682 | non_prologue_insns += this_non_prologue_insn; | |
2683 | ||
2684 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
dda83cd7 | 2685 | then we must have reached the end of the prologue by now. */ |
ab50adb6 MR |
2686 | if (prev_delay_slot || non_prologue_insns > 1 |
2687 | || mips16_instruction_is_compact_branch (inst)) | |
2688 | break; | |
2689 | ||
2690 | prev_non_prologue_insn = this_non_prologue_insn; | |
2691 | prev_delay_slot = in_delay_slot; | |
2692 | prev_pc = cur_pc - prev_extend_bytes; | |
29639122 | 2693 | } |
eec63939 | 2694 | |
29639122 JB |
2695 | /* The entry instruction is typically the first instruction in a function, |
2696 | and it stores registers at offsets relative to the value of the old SP | |
2697 | (before the prologue). But the value of the sp parameter to this | |
2698 | function is the new SP (after the prologue has been executed). So we | |
2699 | can't calculate those offsets until we've seen the entire prologue, | |
025bb325 | 2700 | and can calculate what the old SP must have been. */ |
29639122 JB |
2701 | if (entry_inst != 0) |
2702 | { | |
2703 | int areg_count = (entry_inst >> 8) & 7; | |
2704 | int sreg_count = (entry_inst >> 6) & 3; | |
eec63939 | 2705 | |
29639122 JB |
2706 | /* The entry instruction always subtracts 32 from the SP. */ |
2707 | frame_offset += 32; | |
2708 | ||
2709 | /* Now we can calculate what the SP must have been at the | |
dda83cd7 | 2710 | start of the function prologue. */ |
29639122 JB |
2711 | sp += frame_offset; |
2712 | ||
2713 | /* Check if a0-a3 were saved in the caller's argument save area. */ | |
2714 | for (reg = 4, offset = 0; reg < areg_count + 4; reg++) | |
2715 | { | |
74ed0bb4 | 2716 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2717 | offset += mips_abi_regsize (gdbarch); |
29639122 JB |
2718 | } |
2719 | ||
2720 | /* Check if the ra register was pushed on the stack. */ | |
2721 | offset = -4; | |
2722 | if (entry_inst & 0x20) | |
2723 | { | |
74ed0bb4 | 2724 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
72a155b4 | 2725 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2726 | } |
2727 | ||
2728 | /* Check if the s0 and s1 registers were pushed on the stack. */ | |
2729 | for (reg = 16; reg < sreg_count + 16; reg++) | |
2730 | { | |
74ed0bb4 | 2731 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
72a155b4 | 2732 | offset -= mips_abi_regsize (gdbarch); |
29639122 JB |
2733 | } |
2734 | } | |
2735 | ||
2207132d MR |
2736 | /* The SAVE instruction is similar to ENTRY, except that defined by the |
2737 | MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the | |
2738 | size of the frame is specified as an immediate field of instruction | |
2739 | and an extended variation exists which lets additional registers and | |
2740 | frame space to be specified. The instruction always treats registers | |
2741 | as 32-bit so its usefulness for 64-bit ABIs is questionable. */ | |
2742 | if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) | |
2743 | { | |
2744 | static int args_table[16] = { | |
2745 | 0, 0, 0, 0, 1, 1, 1, 1, | |
2746 | 2, 2, 2, 0, 3, 3, 4, -1, | |
2747 | }; | |
2748 | static int astatic_table[16] = { | |
2749 | 0, 1, 2, 3, 0, 1, 2, 3, | |
2750 | 0, 1, 2, 4, 0, 1, 0, -1, | |
2751 | }; | |
2752 | int aregs = (save_inst >> 16) & 0xf; | |
2753 | int xsregs = (save_inst >> 24) & 0x7; | |
2754 | int args = args_table[aregs]; | |
2755 | int astatic = astatic_table[aregs]; | |
2756 | long frame_size; | |
2757 | ||
2758 | if (args < 0) | |
2759 | { | |
2760 | warning (_("Invalid number of argument registers encoded in SAVE.")); | |
2761 | args = 0; | |
2762 | } | |
2763 | if (astatic < 0) | |
2764 | { | |
2765 | warning (_("Invalid number of static registers encoded in SAVE.")); | |
2766 | astatic = 0; | |
2767 | } | |
2768 | ||
2769 | /* For standard SAVE the frame size of 0 means 128. */ | |
2770 | frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); | |
2771 | if (frame_size == 0 && (save_inst >> 16) == 0) | |
2772 | frame_size = 16; | |
2773 | frame_size *= 8; | |
2774 | frame_offset += frame_size; | |
2775 | ||
2776 | /* Now we can calculate what the SP must have been at the | |
dda83cd7 | 2777 | start of the function prologue. */ |
2207132d MR |
2778 | sp += frame_offset; |
2779 | ||
2780 | /* Check if A0-A3 were saved in the caller's argument save area. */ | |
2781 | for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) | |
2782 | { | |
74ed0bb4 | 2783 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2784 | offset += mips_abi_regsize (gdbarch); |
2785 | } | |
2786 | ||
2787 | offset = -4; | |
2788 | ||
2789 | /* Check if the RA register was pushed on the stack. */ | |
2790 | if (save_inst & 0x40) | |
2791 | { | |
74ed0bb4 | 2792 | set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
2207132d MR |
2793 | offset -= mips_abi_regsize (gdbarch); |
2794 | } | |
2795 | ||
2796 | /* Check if the S8 register was pushed on the stack. */ | |
2797 | if (xsregs > 6) | |
2798 | { | |
74ed0bb4 | 2799 | set_reg_offset (gdbarch, this_cache, 30, sp + offset); |
2207132d MR |
2800 | offset -= mips_abi_regsize (gdbarch); |
2801 | xsregs--; | |
2802 | } | |
2803 | /* Check if S2-S7 were pushed on the stack. */ | |
2804 | for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) | |
2805 | { | |
74ed0bb4 | 2806 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
2207132d MR |
2807 | offset -= mips_abi_regsize (gdbarch); |
2808 | } | |
2809 | ||
2810 | /* Check if the S1 register was pushed on the stack. */ | |
2811 | if (save_inst & 0x10) | |
2812 | { | |
74ed0bb4 | 2813 | set_reg_offset (gdbarch, this_cache, 17, sp + offset); |
2207132d MR |
2814 | offset -= mips_abi_regsize (gdbarch); |
2815 | } | |
2816 | /* Check if the S0 register was pushed on the stack. */ | |
2817 | if (save_inst & 0x20) | |
2818 | { | |
74ed0bb4 | 2819 | set_reg_offset (gdbarch, this_cache, 16, sp + offset); |
2207132d MR |
2820 | offset -= mips_abi_regsize (gdbarch); |
2821 | } | |
2822 | ||
4cc0665f MR |
2823 | /* Check if A0-A3 were pushed on the stack. */ |
2824 | for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) | |
2825 | { | |
2826 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); | |
2827 | offset -= mips_abi_regsize (gdbarch); | |
2828 | } | |
2829 | } | |
2830 | ||
2831 | if (this_cache != NULL) | |
2832 | { | |
2833 | this_cache->base = | |
dda83cd7 | 2834 | (get_frame_register_signed (this_frame, |
4cc0665f | 2835 | gdbarch_num_regs (gdbarch) + frame_reg) |
dda83cd7 | 2836 | + frame_offset - frame_adjust); |
4cc0665f | 2837 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
dda83cd7 SM |
2838 | be able to get rid of the assignment below, evetually. But it's |
2839 | still needed for now. */ | |
4cc0665f MR |
2840 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
2841 | + mips_regnum (gdbarch)->pc] | |
dda83cd7 | 2842 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
4cc0665f MR |
2843 | } |
2844 | ||
ab50adb6 MR |
2845 | /* Set end_prologue_addr to the address of the instruction immediately |
2846 | after the last one we scanned. Unless the last one looked like a | |
2847 | non-prologue instruction (and we looked ahead), in which case use | |
2848 | its address instead. */ | |
2849 | end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot | |
2850 | ? prev_pc : cur_pc - prev_extend_bytes); | |
4cc0665f MR |
2851 | |
2852 | return end_prologue_addr; | |
2853 | } | |
2854 | ||
2855 | /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). | |
2856 | Procedures that use the 32-bit instruction set are handled by the | |
2857 | mips_insn32 unwinder. */ | |
2858 | ||
2859 | static struct mips_frame_cache * | |
bd2b40ac | 2860 | mips_insn16_frame_cache (frame_info_ptr this_frame, void **this_cache) |
4cc0665f MR |
2861 | { |
2862 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2863 | struct mips_frame_cache *cache; | |
2864 | ||
2865 | if ((*this_cache) != NULL) | |
19ba03f4 | 2866 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2867 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
2868 | (*this_cache) = cache; | |
2869 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
2870 | ||
2871 | /* Analyze the function prologue. */ | |
2872 | { | |
2873 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); | |
2874 | CORE_ADDR start_addr; | |
2875 | ||
2876 | find_pc_partial_function (pc, NULL, &start_addr, NULL); | |
2877 | if (start_addr == 0) | |
2878 | start_addr = heuristic_proc_start (gdbarch, pc); | |
2879 | /* We can't analyze the prologue if we couldn't find the begining | |
2880 | of the function. */ | |
2881 | if (start_addr == 0) | |
2882 | return cache; | |
2883 | ||
19ba03f4 SM |
2884 | mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, |
2885 | (struct mips_frame_cache *) *this_cache); | |
4cc0665f MR |
2886 | } |
2887 | ||
2888 | /* gdbarch_sp_regnum contains the value and not the address. */ | |
a9a87d35 LM |
2889 | cache->saved_regs[gdbarch_num_regs (gdbarch) |
2890 | + MIPS_SP_REGNUM].set_value (cache->base); | |
4cc0665f | 2891 | |
19ba03f4 | 2892 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f MR |
2893 | } |
2894 | ||
2895 | static void | |
bd2b40ac | 2896 | mips_insn16_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
4cc0665f MR |
2897 | struct frame_id *this_id) |
2898 | { | |
2899 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2900 | this_cache); | |
2901 | /* This marks the outermost frame. */ | |
2902 | if (info->base == 0) | |
2903 | return; | |
2904 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); | |
2905 | } | |
2906 | ||
2907 | static struct value * | |
bd2b40ac | 2908 | mips_insn16_frame_prev_register (frame_info_ptr this_frame, |
4cc0665f MR |
2909 | void **this_cache, int regnum) |
2910 | { | |
2911 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2912 | this_cache); | |
2913 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2914 | } | |
2915 | ||
2916 | static int | |
2917 | mips_insn16_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 2918 | frame_info_ptr this_frame, void **this_cache) |
4cc0665f MR |
2919 | { |
2920 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2921 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2922 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2923 | return 1; | |
2924 | return 0; | |
2925 | } | |
2926 | ||
2927 | static const struct frame_unwind mips_insn16_frame_unwind = | |
2928 | { | |
a154d838 | 2929 | "mips insn16 prologue", |
4cc0665f MR |
2930 | NORMAL_FRAME, |
2931 | default_frame_unwind_stop_reason, | |
2932 | mips_insn16_frame_this_id, | |
2933 | mips_insn16_frame_prev_register, | |
2934 | NULL, | |
2935 | mips_insn16_frame_sniffer | |
2936 | }; | |
2937 | ||
2938 | static CORE_ADDR | |
bd2b40ac | 2939 | mips_insn16_frame_base_address (frame_info_ptr this_frame, |
4cc0665f MR |
2940 | void **this_cache) |
2941 | { | |
2942 | struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | |
2943 | this_cache); | |
2944 | return info->base; | |
2945 | } | |
2946 | ||
2947 | static const struct frame_base mips_insn16_frame_base = | |
2948 | { | |
2949 | &mips_insn16_frame_unwind, | |
2950 | mips_insn16_frame_base_address, | |
2951 | mips_insn16_frame_base_address, | |
2952 | mips_insn16_frame_base_address | |
2953 | }; | |
2954 | ||
2955 | static const struct frame_base * | |
bd2b40ac | 2956 | mips_insn16_frame_base_sniffer (frame_info_ptr this_frame) |
4cc0665f MR |
2957 | { |
2958 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
2959 | CORE_ADDR pc = get_frame_pc (this_frame); | |
2960 | if (mips_pc_is_mips16 (gdbarch, pc)) | |
2961 | return &mips_insn16_frame_base; | |
2962 | else | |
2963 | return NULL; | |
2964 | } | |
2965 | ||
2966 | /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped | |
2967 | to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are | |
2968 | interpreted directly, and then multiplied by 4. */ | |
2969 | ||
2970 | static int | |
2971 | micromips_decode_imm9 (int imm) | |
2972 | { | |
2973 | imm = (imm ^ 0x100) - 0x100; | |
2974 | if (imm > -3 && imm < 2) | |
2975 | imm ^= 0x100; | |
2976 | return imm << 2; | |
2977 | } | |
2978 | ||
2979 | /* Analyze the function prologue from START_PC to LIMIT_PC. Return | |
2980 | the address of the first instruction past the prologue. */ | |
2981 | ||
2982 | static CORE_ADDR | |
2983 | micromips_scan_prologue (struct gdbarch *gdbarch, | |
2984 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
bd2b40ac | 2985 | frame_info_ptr this_frame, |
4cc0665f MR |
2986 | struct mips_frame_cache *this_cache) |
2987 | { | |
ab50adb6 | 2988 | CORE_ADDR end_prologue_addr; |
4cc0665f MR |
2989 | int prev_non_prologue_insn = 0; |
2990 | int frame_reg = MIPS_SP_REGNUM; | |
2991 | int this_non_prologue_insn; | |
2992 | int non_prologue_insns = 0; | |
2993 | long frame_offset = 0; /* Size of stack frame. */ | |
2994 | long frame_adjust = 0; /* Offset of FP from SP. */ | |
ab50adb6 MR |
2995 | int prev_delay_slot = 0; |
2996 | int in_delay_slot; | |
4cc0665f MR |
2997 | CORE_ADDR prev_pc; |
2998 | CORE_ADDR cur_pc; | |
2999 | ULONGEST insn; /* current instruction */ | |
3000 | CORE_ADDR sp; | |
3001 | long offset; | |
3002 | long sp_adj; | |
3003 | long v1_off = 0; /* The assumption is LUI will replace it. */ | |
3004 | int reglist; | |
3005 | int breg; | |
3006 | int dreg; | |
3007 | int sreg; | |
3008 | int treg; | |
3009 | int loc; | |
3010 | int op; | |
3011 | int s; | |
3012 | int i; | |
3013 | ||
3014 | /* Can be called when there's no process, and hence when there's no | |
3015 | THIS_FRAME. */ | |
3016 | if (this_frame != NULL) | |
3017 | sp = get_frame_register_signed (this_frame, | |
3018 | gdbarch_num_regs (gdbarch) | |
3019 | + MIPS_SP_REGNUM); | |
3020 | else | |
3021 | sp = 0; | |
3022 | ||
3023 | if (limit_pc > start_pc + 200) | |
3024 | limit_pc = start_pc + 200; | |
3025 | prev_pc = start_pc; | |
3026 | ||
3027 | /* Permit at most one non-prologue non-control-transfer instruction | |
3028 | in the middle which may have been reordered by the compiler for | |
3029 | optimisation. */ | |
3030 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) | |
3031 | { | |
3032 | this_non_prologue_insn = 0; | |
ab50adb6 | 3033 | in_delay_slot = 0; |
4cc0665f MR |
3034 | sp_adj = 0; |
3035 | loc = 0; | |
3036 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); | |
3037 | loc += MIPS_INSN16_SIZE; | |
3038 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
3039 | { | |
4cc0665f MR |
3040 | /* 32-bit instructions. */ |
3041 | case 2 * MIPS_INSN16_SIZE: | |
3042 | insn <<= 16; | |
3043 | insn |= mips_fetch_instruction (gdbarch, | |
3044 | ISA_MICROMIPS, cur_pc + loc, NULL); | |
3045 | loc += MIPS_INSN16_SIZE; | |
3046 | switch (micromips_op (insn >> 16)) | |
3047 | { | |
3048 | /* Record $sp/$fp adjustment. */ | |
3049 | /* Discard (D)ADDU $gp,$jp used for PIC code. */ | |
3050 | case 0x0: /* POOL32A: bits 000000 */ | |
3051 | case 0x16: /* POOL32S: bits 010110 */ | |
3052 | op = b0s11_op (insn); | |
3053 | sreg = b0s5_reg (insn >> 16); | |
3054 | treg = b5s5_reg (insn >> 16); | |
3055 | dreg = b11s5_reg (insn); | |
3056 | if (op == 0x1d0 | |
3057 | /* SUBU: bits 000000 00111010000 */ | |
3058 | /* DSUBU: bits 010110 00111010000 */ | |
3059 | && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM | |
3060 | && treg == 3) | |
3061 | /* (D)SUBU $sp, $v1 */ | |
3062 | sp_adj = v1_off; | |
3063 | else if (op != 0x150 | |
3064 | /* ADDU: bits 000000 00101010000 */ | |
3065 | /* DADDU: bits 010110 00101010000 */ | |
3066 | || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) | |
3067 | this_non_prologue_insn = 1; | |
3068 | break; | |
3069 | ||
3070 | case 0x8: /* POOL32B: bits 001000 */ | |
3071 | op = b12s4_op (insn); | |
3072 | breg = b0s5_reg (insn >> 16); | |
3073 | reglist = sreg = b5s5_reg (insn >> 16); | |
3074 | offset = (b0s12_imm (insn) ^ 0x800) - 0x800; | |
3075 | if ((op == 0x9 || op == 0xc) | |
3076 | /* SWP: bits 001000 1001 */ | |
3077 | /* SDP: bits 001000 1100 */ | |
3078 | && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) | |
3079 | /* S[DW]P reg,offset($sp) */ | |
3080 | { | |
3081 | s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); | |
3082 | set_reg_offset (gdbarch, this_cache, | |
3083 | sreg, sp + offset); | |
3084 | set_reg_offset (gdbarch, this_cache, | |
3085 | sreg + 1, sp + offset + s); | |
3086 | } | |
3087 | else if ((op == 0xd || op == 0xf) | |
3088 | /* SWM: bits 001000 1101 */ | |
3089 | /* SDM: bits 001000 1111 */ | |
3090 | && breg == MIPS_SP_REGNUM | |
3091 | /* SWM reglist,offset($sp) */ | |
3092 | && ((reglist >= 1 && reglist <= 9) | |
3093 | || (reglist >= 16 && reglist <= 25))) | |
3094 | { | |
325fac50 | 3095 | int sreglist = std::min(reglist & 0xf, 8); |
4cc0665f MR |
3096 | |
3097 | s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); | |
3098 | for (i = 0; i < sreglist; i++) | |
3099 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); | |
3100 | if ((reglist & 0xf) > 8) | |
3101 | set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); | |
3102 | if ((reglist & 0x10) == 0x10) | |
3103 | set_reg_offset (gdbarch, this_cache, | |
3104 | MIPS_RA_REGNUM, sp + s * i++); | |
3105 | } | |
3106 | else | |
3107 | this_non_prologue_insn = 1; | |
3108 | break; | |
3109 | ||
3110 | /* Record $sp/$fp adjustment. */ | |
3111 | /* Discard (D)ADDIU $gp used for PIC code. */ | |
3112 | case 0xc: /* ADDIU: bits 001100 */ | |
3113 | case 0x17: /* DADDIU: bits 010111 */ | |
3114 | sreg = b0s5_reg (insn >> 16); | |
3115 | dreg = b5s5_reg (insn >> 16); | |
3116 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3117 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) | |
3118 | /* (D)ADDIU $sp, imm */ | |
3119 | sp_adj = offset; | |
3120 | else if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3121 | /* (D)ADDIU $fp, $sp, imm */ | |
3122 | { | |
4cc0665f MR |
3123 | frame_adjust = offset; |
3124 | frame_reg = 30; | |
3125 | } | |
3126 | else if (sreg != 28 || dreg != 28) | |
3127 | /* (D)ADDIU $gp, imm */ | |
3128 | this_non_prologue_insn = 1; | |
3129 | break; | |
3130 | ||
3131 | /* LUI $v1 is used for larger $sp adjustments. */ | |
3356937a | 3132 | /* Discard LUI $gp used for PIC code. */ |
4cc0665f MR |
3133 | case 0x10: /* POOL32I: bits 010000 */ |
3134 | if (b5s5_op (insn >> 16) == 0xd | |
3135 | /* LUI: bits 010000 001101 */ | |
3136 | && b0s5_reg (insn >> 16) == 3) | |
3137 | /* LUI $v1, imm */ | |
3138 | v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; | |
3139 | else if (b5s5_op (insn >> 16) != 0xd | |
3140 | /* LUI: bits 010000 001101 */ | |
3141 | || b0s5_reg (insn >> 16) != 28) | |
3142 | /* LUI $gp, imm */ | |
3143 | this_non_prologue_insn = 1; | |
3144 | break; | |
3145 | ||
3146 | /* ORI $v1 is used for larger $sp adjustments. */ | |
3147 | case 0x14: /* ORI: bits 010100 */ | |
3148 | sreg = b0s5_reg (insn >> 16); | |
3149 | dreg = b5s5_reg (insn >> 16); | |
3150 | if (sreg == 3 && dreg == 3) | |
3151 | /* ORI $v1, imm */ | |
3152 | v1_off |= b0s16_imm (insn); | |
3153 | else | |
3154 | this_non_prologue_insn = 1; | |
3155 | break; | |
3156 | ||
3157 | case 0x26: /* SWC1: bits 100110 */ | |
3158 | case 0x2e: /* SDC1: bits 101110 */ | |
3159 | breg = b0s5_reg (insn >> 16); | |
3160 | if (breg != MIPS_SP_REGNUM) | |
3161 | /* S[DW]C1 reg,offset($sp) */ | |
3162 | this_non_prologue_insn = 1; | |
3163 | break; | |
3164 | ||
3165 | case 0x36: /* SD: bits 110110 */ | |
3166 | case 0x3e: /* SW: bits 111110 */ | |
3167 | breg = b0s5_reg (insn >> 16); | |
3168 | sreg = b5s5_reg (insn >> 16); | |
3169 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
3170 | if (breg == MIPS_SP_REGNUM) | |
3171 | /* S[DW] reg,offset($sp) */ | |
3172 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3173 | else | |
3174 | this_non_prologue_insn = 1; | |
3175 | break; | |
3176 | ||
3177 | default: | |
ab50adb6 | 3178 | /* The instruction in the delay slot can be a part |
dda83cd7 | 3179 | of the prologue, so move forward once more. */ |
ab50adb6 MR |
3180 | if (micromips_instruction_has_delay_slot (insn, 0)) |
3181 | in_delay_slot = 1; | |
3182 | else | |
3183 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3184 | break; |
3185 | } | |
ab50adb6 | 3186 | insn >>= 16; |
4cc0665f MR |
3187 | break; |
3188 | ||
3189 | /* 16-bit instructions. */ | |
3190 | case MIPS_INSN16_SIZE: | |
3191 | switch (micromips_op (insn)) | |
3192 | { | |
3193 | case 0x3: /* MOVE: bits 000011 */ | |
3194 | sreg = b0s5_reg (insn); | |
3195 | dreg = b5s5_reg (insn); | |
3196 | if (sreg == MIPS_SP_REGNUM && dreg == 30) | |
3197 | /* MOVE $fp, $sp */ | |
78cc6c2d | 3198 | frame_reg = 30; |
4cc0665f MR |
3199 | else if ((sreg & 0x1c) != 0x4) |
3200 | /* MOVE reg, $a0-$a3 */ | |
3201 | this_non_prologue_insn = 1; | |
3202 | break; | |
3203 | ||
3204 | case 0x11: /* POOL16C: bits 010001 */ | |
3205 | if (b6s4_op (insn) == 0x5) | |
3206 | /* SWM: bits 010001 0101 */ | |
3207 | { | |
3208 | offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; | |
3209 | reglist = b4s2_regl (insn); | |
3210 | for (i = 0; i <= reglist; i++) | |
3211 | set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); | |
3212 | set_reg_offset (gdbarch, this_cache, | |
3213 | MIPS_RA_REGNUM, sp + 4 * i++); | |
3214 | } | |
3215 | else | |
3216 | this_non_prologue_insn = 1; | |
3217 | break; | |
3218 | ||
3219 | case 0x13: /* POOL16D: bits 010011 */ | |
3220 | if ((insn & 0x1) == 0x1) | |
3221 | /* ADDIUSP: bits 010011 1 */ | |
3222 | sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); | |
3223 | else if (b5s5_reg (insn) == MIPS_SP_REGNUM) | |
3224 | /* ADDIUS5: bits 010011 0 */ | |
3225 | /* ADDIUS5 $sp, imm */ | |
3226 | sp_adj = (b1s4_imm (insn) ^ 8) - 8; | |
3227 | else | |
3228 | this_non_prologue_insn = 1; | |
3229 | break; | |
3230 | ||
3231 | case 0x32: /* SWSP: bits 110010 */ | |
3232 | offset = b0s5_imm (insn) << 2; | |
3233 | sreg = b5s5_reg (insn); | |
3234 | set_reg_offset (gdbarch, this_cache, sreg, sp + offset); | |
3235 | break; | |
3236 | ||
3237 | default: | |
ab50adb6 | 3238 | /* The instruction in the delay slot can be a part |
dda83cd7 | 3239 | of the prologue, so move forward once more. */ |
ab50adb6 MR |
3240 | if (micromips_instruction_has_delay_slot (insn << 16, 0)) |
3241 | in_delay_slot = 1; | |
3242 | else | |
3243 | this_non_prologue_insn = 1; | |
4cc0665f MR |
3244 | break; |
3245 | } | |
3246 | break; | |
3247 | } | |
3248 | if (sp_adj < 0) | |
3249 | frame_offset -= sp_adj; | |
3250 | ||
3251 | non_prologue_insns += this_non_prologue_insn; | |
ab50adb6 MR |
3252 | |
3253 | /* A jump or branch, enough non-prologue insns seen or positive | |
dda83cd7 SM |
3254 | stack adjustment? If so, then we must have reached the end |
3255 | of the prologue by now. */ | |
ab50adb6 MR |
3256 | if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0 |
3257 | || micromips_instruction_is_compact_branch (insn)) | |
3258 | break; | |
3259 | ||
4cc0665f | 3260 | prev_non_prologue_insn = this_non_prologue_insn; |
ab50adb6 | 3261 | prev_delay_slot = in_delay_slot; |
4cc0665f | 3262 | prev_pc = cur_pc; |
2207132d MR |
3263 | } |
3264 | ||
29639122 JB |
3265 | if (this_cache != NULL) |
3266 | { | |
3267 | this_cache->base = | |
4cc0665f | 3268 | (get_frame_register_signed (this_frame, |
b8a22b94 | 3269 | gdbarch_num_regs (gdbarch) + frame_reg) |
4cc0665f | 3270 | + frame_offset - frame_adjust); |
29639122 | 3271 | /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
4cc0665f MR |
3272 | be able to get rid of the assignment below, evetually. But it's |
3273 | still needed for now. */ | |
72a155b4 UW |
3274 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3275 | + mips_regnum (gdbarch)->pc] | |
4cc0665f | 3276 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
29639122 JB |
3277 | } |
3278 | ||
ab50adb6 MR |
3279 | /* Set end_prologue_addr to the address of the instruction immediately |
3280 | after the last one we scanned. Unless the last one looked like a | |
3281 | non-prologue instruction (and we looked ahead), in which case use | |
3282 | its address instead. */ | |
3283 | end_prologue_addr | |
3284 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3285 | |
3286 | return end_prologue_addr; | |
eec63939 AC |
3287 | } |
3288 | ||
4cc0665f | 3289 | /* Heuristic unwinder for procedures using microMIPS instructions. |
29639122 | 3290 | Procedures that use the 32-bit instruction set are handled by the |
4cc0665f | 3291 | mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
29639122 JB |
3292 | |
3293 | static struct mips_frame_cache * | |
bd2b40ac | 3294 | mips_micro_frame_cache (frame_info_ptr this_frame, void **this_cache) |
eec63939 | 3295 | { |
e17a4113 | 3296 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3297 | struct mips_frame_cache *cache; |
eec63939 AC |
3298 | |
3299 | if ((*this_cache) != NULL) | |
19ba03f4 | 3300 | return (struct mips_frame_cache *) (*this_cache); |
4cc0665f | 3301 | |
29639122 JB |
3302 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3303 | (*this_cache) = cache; | |
b8a22b94 | 3304 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
eec63939 | 3305 | |
29639122 JB |
3306 | /* Analyze the function prologue. */ |
3307 | { | |
b8a22b94 | 3308 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3309 | CORE_ADDR start_addr; |
eec63939 | 3310 | |
29639122 JB |
3311 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3312 | if (start_addr == 0) | |
4cc0665f | 3313 | start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
29639122 JB |
3314 | /* We can't analyze the prologue if we couldn't find the begining |
3315 | of the function. */ | |
3316 | if (start_addr == 0) | |
3317 | return cache; | |
eec63939 | 3318 | |
19ba03f4 SM |
3319 | micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3320 | (struct mips_frame_cache *) *this_cache); | |
29639122 | 3321 | } |
4cc0665f | 3322 | |
3e8c568d | 3323 | /* gdbarch_sp_regnum contains the value and not the address. */ |
a9a87d35 LM |
3324 | cache->saved_regs[gdbarch_num_regs (gdbarch) |
3325 | + MIPS_SP_REGNUM].set_value (cache->base); | |
eec63939 | 3326 | |
19ba03f4 | 3327 | return (struct mips_frame_cache *) (*this_cache); |
eec63939 AC |
3328 | } |
3329 | ||
3330 | static void | |
bd2b40ac | 3331 | mips_micro_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
4cc0665f | 3332 | struct frame_id *this_id) |
eec63939 | 3333 | { |
4cc0665f MR |
3334 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3335 | this_cache); | |
21327321 DJ |
3336 | /* This marks the outermost frame. */ |
3337 | if (info->base == 0) | |
3338 | return; | |
b8a22b94 | 3339 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
eec63939 AC |
3340 | } |
3341 | ||
b8a22b94 | 3342 | static struct value * |
bd2b40ac | 3343 | mips_micro_frame_prev_register (frame_info_ptr this_frame, |
4cc0665f | 3344 | void **this_cache, int regnum) |
eec63939 | 3345 | { |
4cc0665f MR |
3346 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3347 | this_cache); | |
b8a22b94 DJ |
3348 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3349 | } | |
3350 | ||
3351 | static int | |
4cc0665f | 3352 | mips_micro_frame_sniffer (const struct frame_unwind *self, |
bd2b40ac | 3353 | frame_info_ptr this_frame, void **this_cache) |
b8a22b94 | 3354 | { |
4cc0665f | 3355 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3356 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3357 | |
3358 | if (mips_pc_is_micromips (gdbarch, pc)) | |
b8a22b94 DJ |
3359 | return 1; |
3360 | return 0; | |
eec63939 AC |
3361 | } |
3362 | ||
4cc0665f | 3363 | static const struct frame_unwind mips_micro_frame_unwind = |
eec63939 | 3364 | { |
a154d838 | 3365 | "mips micro prologue", |
eec63939 | 3366 | NORMAL_FRAME, |
8fbca658 | 3367 | default_frame_unwind_stop_reason, |
4cc0665f MR |
3368 | mips_micro_frame_this_id, |
3369 | mips_micro_frame_prev_register, | |
b8a22b94 | 3370 | NULL, |
4cc0665f | 3371 | mips_micro_frame_sniffer |
eec63939 AC |
3372 | }; |
3373 | ||
eec63939 | 3374 | static CORE_ADDR |
bd2b40ac | 3375 | mips_micro_frame_base_address (frame_info_ptr this_frame, |
4cc0665f | 3376 | void **this_cache) |
eec63939 | 3377 | { |
4cc0665f MR |
3378 | struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
3379 | this_cache); | |
29639122 | 3380 | return info->base; |
eec63939 AC |
3381 | } |
3382 | ||
4cc0665f | 3383 | static const struct frame_base mips_micro_frame_base = |
eec63939 | 3384 | { |
4cc0665f MR |
3385 | &mips_micro_frame_unwind, |
3386 | mips_micro_frame_base_address, | |
3387 | mips_micro_frame_base_address, | |
3388 | mips_micro_frame_base_address | |
eec63939 AC |
3389 | }; |
3390 | ||
3391 | static const struct frame_base * | |
bd2b40ac | 3392 | mips_micro_frame_base_sniffer (frame_info_ptr this_frame) |
eec63939 | 3393 | { |
4cc0665f | 3394 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
b8a22b94 | 3395 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f MR |
3396 | |
3397 | if (mips_pc_is_micromips (gdbarch, pc)) | |
3398 | return &mips_micro_frame_base; | |
eec63939 AC |
3399 | else |
3400 | return NULL; | |
edfae063 AC |
3401 | } |
3402 | ||
29639122 JB |
3403 | /* Mark all the registers as unset in the saved_regs array |
3404 | of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | |
3405 | ||
74ed0bb4 MD |
3406 | static void |
3407 | reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | |
c906108c | 3408 | { |
29639122 JB |
3409 | if (this_cache == NULL || this_cache->saved_regs == NULL) |
3410 | return; | |
3411 | ||
3412 | { | |
74ed0bb4 | 3413 | const int num_regs = gdbarch_num_regs (gdbarch); |
29639122 | 3414 | int i; |
64159455 | 3415 | |
a9a87d35 LM |
3416 | /* Reset the register values to their default state. Register i's value |
3417 | is in register i. */ | |
29639122 | 3418 | for (i = 0; i < num_regs; i++) |
a9a87d35 | 3419 | this_cache->saved_regs[i].set_realreg (i); |
29639122 | 3420 | } |
c906108c SS |
3421 | } |
3422 | ||
025bb325 | 3423 | /* Analyze the function prologue from START_PC to LIMIT_PC. Builds |
29639122 JB |
3424 | the associated FRAME_CACHE if not null. |
3425 | Return the address of the first instruction past the prologue. */ | |
c906108c | 3426 | |
875e1767 | 3427 | static CORE_ADDR |
e17a4113 UW |
3428 | mips32_scan_prologue (struct gdbarch *gdbarch, |
3429 | CORE_ADDR start_pc, CORE_ADDR limit_pc, | |
bd2b40ac | 3430 | frame_info_ptr this_frame, |
dda83cd7 | 3431 | struct mips_frame_cache *this_cache) |
c906108c | 3432 | { |
ab50adb6 MR |
3433 | int prev_non_prologue_insn; |
3434 | int this_non_prologue_insn; | |
3435 | int non_prologue_insns; | |
025bb325 MS |
3436 | CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for |
3437 | frame-pointer. */ | |
ab50adb6 MR |
3438 | int prev_delay_slot; |
3439 | CORE_ADDR prev_pc; | |
3440 | CORE_ADDR cur_pc; | |
29639122 JB |
3441 | CORE_ADDR sp; |
3442 | long frame_offset; | |
3443 | int frame_reg = MIPS_SP_REGNUM; | |
8fa9cfa1 | 3444 | |
ab50adb6 | 3445 | CORE_ADDR end_prologue_addr; |
29639122 JB |
3446 | int seen_sp_adjust = 0; |
3447 | int load_immediate_bytes = 0; | |
ab50adb6 | 3448 | int in_delay_slot; |
7d1e6fb8 | 3449 | int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); |
8fa9cfa1 | 3450 | |
29639122 | 3451 | /* Can be called when there's no process, and hence when there's no |
b8a22b94 DJ |
3452 | THIS_FRAME. */ |
3453 | if (this_frame != NULL) | |
3454 | sp = get_frame_register_signed (this_frame, | |
3455 | gdbarch_num_regs (gdbarch) | |
3456 | + MIPS_SP_REGNUM); | |
8fa9cfa1 | 3457 | else |
29639122 | 3458 | sp = 0; |
9022177c | 3459 | |
29639122 JB |
3460 | if (limit_pc > start_pc + 200) |
3461 | limit_pc = start_pc + 200; | |
9022177c | 3462 | |
29639122 | 3463 | restart: |
ab50adb6 MR |
3464 | prev_non_prologue_insn = 0; |
3465 | non_prologue_insns = 0; | |
3466 | prev_delay_slot = 0; | |
3467 | prev_pc = start_pc; | |
9022177c | 3468 | |
ab50adb6 MR |
3469 | /* Permit at most one non-prologue non-control-transfer instruction |
3470 | in the middle which may have been reordered by the compiler for | |
3471 | optimisation. */ | |
29639122 | 3472 | frame_offset = 0; |
95ac2dcf | 3473 | for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
9022177c | 3474 | { |
eaa6a9a4 MR |
3475 | unsigned long inst, high_word; |
3476 | long offset; | |
29639122 | 3477 | int reg; |
9022177c | 3478 | |
ab50adb6 MR |
3479 | this_non_prologue_insn = 0; |
3480 | in_delay_slot = 0; | |
3481 | ||
025bb325 | 3482 | /* Fetch the instruction. */ |
4cc0665f MR |
3483 | inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
3484 | cur_pc, NULL); | |
9022177c | 3485 | |
29639122 JB |
3486 | /* Save some code by pre-extracting some useful fields. */ |
3487 | high_word = (inst >> 16) & 0xffff; | |
eaa6a9a4 | 3488 | offset = ((inst & 0xffff) ^ 0x8000) - 0x8000; |
29639122 | 3489 | reg = high_word & 0x1f; |
fe29b929 | 3490 | |
025bb325 | 3491 | if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
29639122 JB |
3492 | || high_word == 0x23bd /* addi $sp,$sp,-i */ |
3493 | || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | |
3494 | { | |
eaa6a9a4 | 3495 | if (offset < 0) /* Negative stack adjustment? */ |
dda83cd7 | 3496 | frame_offset -= offset; |
29639122 JB |
3497 | else |
3498 | /* Exit loop if a positive stack adjustment is found, which | |
3499 | usually means that the stack cleanup code in the function | |
3500 | epilogue is reached. */ | |
3501 | break; | |
dda83cd7 | 3502 | seen_sp_adjust = 1; |
29639122 | 3503 | } |
7d1e6fb8 | 3504 | else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ |
dda83cd7 | 3505 | && !regsize_is_64_bits) |
29639122 | 3506 | { |
eaa6a9a4 | 3507 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 | 3508 | } |
7d1e6fb8 | 3509 | else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ |
dda83cd7 | 3510 | && regsize_is_64_bits) |
29639122 JB |
3511 | { |
3512 | /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ | |
eaa6a9a4 | 3513 | set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
29639122 JB |
3514 | } |
3515 | else if (high_word == 0x27be) /* addiu $30,$sp,size */ | |
3516 | { | |
3517 | /* Old gcc frame, r30 is virtual frame pointer. */ | |
eaa6a9a4 MR |
3518 | if (offset != frame_offset) |
3519 | frame_addr = sp + offset; | |
b8a22b94 | 3520 | else if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3521 | { |
3522 | unsigned alloca_adjust; | |
a4b8ebc8 | 3523 | |
29639122 | 3524 | frame_reg = 30; |
b8a22b94 DJ |
3525 | frame_addr = get_frame_register_signed |
3526 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
ca9c94ef | 3527 | frame_offset = 0; |
d2ca4222 | 3528 | |
eaa6a9a4 | 3529 | alloca_adjust = (unsigned) (frame_addr - (sp + offset)); |
29639122 JB |
3530 | if (alloca_adjust > 0) |
3531 | { | |
dda83cd7 SM |
3532 | /* FP > SP + frame_size. This may be because of |
3533 | an alloca or somethings similar. Fix sp to | |
3534 | "pre-alloca" value, and try again. */ | |
29639122 | 3535 | sp += alloca_adjust; |
dda83cd7 SM |
3536 | /* Need to reset the status of all registers. Otherwise, |
3537 | we will hit a guard that prevents the new address | |
3538 | for each register to be recomputed during the second | |
3539 | pass. */ | |
3540 | reset_saved_regs (gdbarch, this_cache); | |
29639122 JB |
3541 | goto restart; |
3542 | } | |
3543 | } | |
3544 | } | |
3545 | /* move $30,$sp. With different versions of gas this will be either | |
dda83cd7 SM |
3546 | `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. |
3547 | Accept any one of these. */ | |
29639122 JB |
3548 | else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) |
3549 | { | |
3550 | /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ | |
b8a22b94 | 3551 | if (this_frame && frame_reg == MIPS_SP_REGNUM) |
29639122 JB |
3552 | { |
3553 | unsigned alloca_adjust; | |
c906108c | 3554 | |
29639122 | 3555 | frame_reg = 30; |
b8a22b94 DJ |
3556 | frame_addr = get_frame_register_signed |
3557 | (this_frame, gdbarch_num_regs (gdbarch) + 30); | |
d2ca4222 | 3558 | |
29639122 JB |
3559 | alloca_adjust = (unsigned) (frame_addr - sp); |
3560 | if (alloca_adjust > 0) | |
dda83cd7 SM |
3561 | { |
3562 | /* FP > SP + frame_size. This may be because of | |
3563 | an alloca or somethings similar. Fix sp to | |
3564 | "pre-alloca" value, and try again. */ | |
3565 | sp = frame_addr; | |
3566 | /* Need to reset the status of all registers. Otherwise, | |
3567 | we will hit a guard that prevents the new address | |
3568 | for each register to be recomputed during the second | |
3569 | pass. */ | |
3570 | reset_saved_regs (gdbarch, this_cache); | |
3571 | goto restart; | |
3572 | } | |
29639122 JB |
3573 | } |
3574 | } | |
7d1e6fb8 | 3575 | else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ |
dda83cd7 | 3576 | && !regsize_is_64_bits) |
29639122 | 3577 | { |
eaa6a9a4 | 3578 | set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
29639122 JB |
3579 | } |
3580 | else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | |
dda83cd7 SM |
3581 | || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ |
3582 | || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | |
3583 | || high_word == 0x3c1c /* lui $gp,n */ | |
3584 | || high_word == 0x279c /* addiu $gp,$gp,n */ | |
f8b786e2 | 3585 | || high_word == 0x679c /* daddiu $gp,$gp,n */ |
dda83cd7 SM |
3586 | || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ |
3587 | || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | |
f8b786e2 YT |
3588 | || inst == 0x0399e02d /* daddu $gp,$gp,$t9 */ |
3589 | || inst == 0x033ce02d /* daddu $gp,$t9,$gp */ | |
dda83cd7 | 3590 | ) |
19080931 MR |
3591 | { |
3592 | /* These instructions are part of the prologue, but we don't | |
3593 | need to do anything special to handle them. */ | |
3594 | } | |
29639122 | 3595 | /* The instructions below load $at or $t0 with an immediate |
dda83cd7 SM |
3596 | value in preparation for a stack adjustment via |
3597 | subu $sp,$sp,[$at,$t0]. These instructions could also | |
3598 | initialize a local variable, so we accept them only before | |
3599 | a stack adjustment instruction was seen. */ | |
29639122 | 3600 | else if (!seen_sp_adjust |
ab50adb6 | 3601 | && !prev_delay_slot |
19080931 MR |
3602 | && (high_word == 0x3c01 /* lui $at,n */ |
3603 | || high_word == 0x3c08 /* lui $t0,n */ | |
3604 | || high_word == 0x3421 /* ori $at,$at,n */ | |
3605 | || high_word == 0x3508 /* ori $t0,$t0,n */ | |
3606 | || high_word == 0x3401 /* ori $at,$zero,n */ | |
3607 | || high_word == 0x3408 /* ori $t0,$zero,n */ | |
3608 | )) | |
3609 | { | |
ab50adb6 | 3610 | load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ |
19080931 | 3611 | } |
ab50adb6 | 3612 | /* Check for branches and jumps. The instruction in the delay |
dda83cd7 | 3613 | slot can be a part of the prologue, so move forward once more. */ |
ab50adb6 MR |
3614 | else if (mips32_instruction_has_delay_slot (gdbarch, inst)) |
3615 | { | |
3616 | in_delay_slot = 1; | |
3617 | } | |
3618 | /* This instruction is not an instruction typically found | |
dda83cd7 SM |
3619 | in a prologue, so we must have reached the end of the |
3620 | prologue. */ | |
29639122 | 3621 | else |
19080931 | 3622 | { |
ab50adb6 | 3623 | this_non_prologue_insn = 1; |
19080931 | 3624 | } |
db5f024e | 3625 | |
ab50adb6 MR |
3626 | non_prologue_insns += this_non_prologue_insn; |
3627 | ||
3628 | /* A jump or branch, or enough non-prologue insns seen? If so, | |
dda83cd7 | 3629 | then we must have reached the end of the prologue by now. */ |
ab50adb6 | 3630 | if (prev_delay_slot || non_prologue_insns > 1) |
db5f024e | 3631 | break; |
ab50adb6 MR |
3632 | |
3633 | prev_non_prologue_insn = this_non_prologue_insn; | |
3634 | prev_delay_slot = in_delay_slot; | |
3635 | prev_pc = cur_pc; | |
a4b8ebc8 | 3636 | } |
c906108c | 3637 | |
29639122 JB |
3638 | if (this_cache != NULL) |
3639 | { | |
3640 | this_cache->base = | |
dda83cd7 | 3641 | (get_frame_register_signed (this_frame, |
b8a22b94 | 3642 | gdbarch_num_regs (gdbarch) + frame_reg) |
dda83cd7 | 3643 | + frame_offset); |
29639122 | 3644 | /* FIXME: brobecker/2004-09-15: We should be able to get rid of |
dda83cd7 SM |
3645 | this assignment below, eventually. But it's still needed |
3646 | for now. */ | |
72a155b4 UW |
3647 | this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
3648 | + mips_regnum (gdbarch)->pc] | |
dda83cd7 | 3649 | = this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
f57d151a | 3650 | + MIPS_RA_REGNUM]; |
29639122 | 3651 | } |
c906108c | 3652 | |
ab50adb6 MR |
3653 | /* Set end_prologue_addr to the address of the instruction immediately |
3654 | after the last one we scanned. Unless the last one looked like a | |
3655 | non-prologue instruction (and we looked ahead), in which case use | |
3656 | its address instead. */ | |
3657 | end_prologue_addr | |
3658 | = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; | |
29639122 JB |
3659 | |
3660 | /* In a frameless function, we might have incorrectly | |
025bb325 | 3661 | skipped some load immediate instructions. Undo the skipping |
29639122 JB |
3662 | if the load immediate was not followed by a stack adjustment. */ |
3663 | if (load_immediate_bytes && !seen_sp_adjust) | |
3664 | end_prologue_addr -= load_immediate_bytes; | |
c906108c | 3665 | |
29639122 | 3666 | return end_prologue_addr; |
c906108c SS |
3667 | } |
3668 | ||
29639122 JB |
3669 | /* Heuristic unwinder for procedures using 32-bit instructions (covers |
3670 | both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | |
3671 | instructions (a.k.a. MIPS16) are handled by the mips_insn16 | |
4cc0665f | 3672 | unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
c906108c | 3673 | |
29639122 | 3674 | static struct mips_frame_cache * |
bd2b40ac | 3675 | mips_insn32_frame_cache (frame_info_ptr this_frame, void **this_cache) |
c906108c | 3676 | { |
e17a4113 | 3677 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
29639122 | 3678 | struct mips_frame_cache *cache; |
c906108c | 3679 | |
29639122 | 3680 | if ((*this_cache) != NULL) |
19ba03f4 | 3681 | return (struct mips_frame_cache *) (*this_cache); |
c5aa993b | 3682 | |
29639122 JB |
3683 | cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
3684 | (*this_cache) = cache; | |
b8a22b94 | 3685 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
c5aa993b | 3686 | |
29639122 JB |
3687 | /* Analyze the function prologue. */ |
3688 | { | |
b8a22b94 | 3689 | const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
29639122 | 3690 | CORE_ADDR start_addr; |
c906108c | 3691 | |
29639122 JB |
3692 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
3693 | if (start_addr == 0) | |
e17a4113 | 3694 | start_addr = heuristic_proc_start (gdbarch, pc); |
29639122 JB |
3695 | /* We can't analyze the prologue if we couldn't find the begining |
3696 | of the function. */ | |
3697 | if (start_addr == 0) | |
3698 | return cache; | |
c5aa993b | 3699 | |
19ba03f4 SM |
3700 | mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, |
3701 | (struct mips_frame_cache *) *this_cache); | |
29639122 JB |
3702 | } |
3703 | ||
3e8c568d | 3704 | /* gdbarch_sp_regnum contains the value and not the address. */ |
a9a87d35 LM |
3705 | cache->saved_regs[gdbarch_num_regs (gdbarch) |
3706 | + MIPS_SP_REGNUM].set_value (cache->base); | |
c5aa993b | 3707 | |
19ba03f4 | 3708 | return (struct mips_frame_cache *) (*this_cache); |
c906108c SS |
3709 | } |
3710 | ||
29639122 | 3711 | static void |
bd2b40ac | 3712 | mips_insn32_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
29639122 | 3713 | struct frame_id *this_id) |
c906108c | 3714 | { |
b8a22b94 | 3715 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3716 | this_cache); |
21327321 DJ |
3717 | /* This marks the outermost frame. */ |
3718 | if (info->base == 0) | |
3719 | return; | |
b8a22b94 | 3720 | (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
29639122 | 3721 | } |
c906108c | 3722 | |
b8a22b94 | 3723 | static struct value * |
bd2b40ac | 3724 | mips_insn32_frame_prev_register (frame_info_ptr this_frame, |
b8a22b94 | 3725 | void **this_cache, int regnum) |
29639122 | 3726 | { |
b8a22b94 | 3727 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 | 3728 | this_cache); |
b8a22b94 DJ |
3729 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
3730 | } | |
3731 | ||
3732 | static int | |
3733 | mips_insn32_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3734 | frame_info_ptr this_frame, void **this_cache) |
b8a22b94 DJ |
3735 | { |
3736 | CORE_ADDR pc = get_frame_pc (this_frame); | |
4cc0665f | 3737 | if (mips_pc_is_mips (pc)) |
b8a22b94 DJ |
3738 | return 1; |
3739 | return 0; | |
c906108c SS |
3740 | } |
3741 | ||
29639122 JB |
3742 | static const struct frame_unwind mips_insn32_frame_unwind = |
3743 | { | |
a154d838 | 3744 | "mips insn32 prologue", |
29639122 | 3745 | NORMAL_FRAME, |
8fbca658 | 3746 | default_frame_unwind_stop_reason, |
29639122 | 3747 | mips_insn32_frame_this_id, |
b8a22b94 DJ |
3748 | mips_insn32_frame_prev_register, |
3749 | NULL, | |
3750 | mips_insn32_frame_sniffer | |
29639122 | 3751 | }; |
c906108c | 3752 | |
1c645fec | 3753 | static CORE_ADDR |
bd2b40ac | 3754 | mips_insn32_frame_base_address (frame_info_ptr this_frame, |
29639122 | 3755 | void **this_cache) |
c906108c | 3756 | { |
b8a22b94 | 3757 | struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
29639122 JB |
3758 | this_cache); |
3759 | return info->base; | |
3760 | } | |
c906108c | 3761 | |
29639122 JB |
3762 | static const struct frame_base mips_insn32_frame_base = |
3763 | { | |
3764 | &mips_insn32_frame_unwind, | |
3765 | mips_insn32_frame_base_address, | |
3766 | mips_insn32_frame_base_address, | |
3767 | mips_insn32_frame_base_address | |
3768 | }; | |
1c645fec | 3769 | |
29639122 | 3770 | static const struct frame_base * |
bd2b40ac | 3771 | mips_insn32_frame_base_sniffer (frame_info_ptr this_frame) |
29639122 | 3772 | { |
b8a22b94 | 3773 | CORE_ADDR pc = get_frame_pc (this_frame); |
4cc0665f | 3774 | if (mips_pc_is_mips (pc)) |
29639122 | 3775 | return &mips_insn32_frame_base; |
a65bbe44 | 3776 | else |
29639122 JB |
3777 | return NULL; |
3778 | } | |
a65bbe44 | 3779 | |
29639122 | 3780 | static struct trad_frame_cache * |
bd2b40ac | 3781 | mips_stub_frame_cache (frame_info_ptr this_frame, void **this_cache) |
29639122 JB |
3782 | { |
3783 | CORE_ADDR pc; | |
3784 | CORE_ADDR start_addr; | |
3785 | CORE_ADDR stack_addr; | |
3786 | struct trad_frame_cache *this_trad_cache; | |
b8a22b94 DJ |
3787 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
3788 | int num_regs = gdbarch_num_regs (gdbarch); | |
c906108c | 3789 | |
29639122 | 3790 | if ((*this_cache) != NULL) |
19ba03f4 | 3791 | return (struct trad_frame_cache *) (*this_cache); |
b8a22b94 | 3792 | this_trad_cache = trad_frame_cache_zalloc (this_frame); |
29639122 | 3793 | (*this_cache) = this_trad_cache; |
1c645fec | 3794 | |
29639122 | 3795 | /* The return address is in the link register. */ |
3e8c568d | 3796 | trad_frame_set_reg_realreg (this_trad_cache, |
72a155b4 | 3797 | gdbarch_pc_regnum (gdbarch), |
b8a22b94 | 3798 | num_regs + MIPS_RA_REGNUM); |
1c645fec | 3799 | |
29639122 JB |
3800 | /* Frame ID, since it's a frameless / stackless function, no stack |
3801 | space is allocated and SP on entry is the current SP. */ | |
b8a22b94 | 3802 | pc = get_frame_pc (this_frame); |
29639122 | 3803 | find_pc_partial_function (pc, NULL, &start_addr, NULL); |
b8a22b94 DJ |
3804 | stack_addr = get_frame_register_signed (this_frame, |
3805 | num_regs + MIPS_SP_REGNUM); | |
aa6c981f | 3806 | trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); |
1c645fec | 3807 | |
29639122 JB |
3808 | /* Assume that the frame's base is the same as the |
3809 | stack-pointer. */ | |
3810 | trad_frame_set_this_base (this_trad_cache, stack_addr); | |
c906108c | 3811 | |
29639122 JB |
3812 | return this_trad_cache; |
3813 | } | |
c906108c | 3814 | |
29639122 | 3815 | static void |
bd2b40ac | 3816 | mips_stub_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
29639122 JB |
3817 | struct frame_id *this_id) |
3818 | { | |
3819 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3820 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3821 | trad_frame_get_id (this_trad_cache, this_id); |
3822 | } | |
c906108c | 3823 | |
b8a22b94 | 3824 | static struct value * |
bd2b40ac | 3825 | mips_stub_frame_prev_register (frame_info_ptr this_frame, |
b8a22b94 | 3826 | void **this_cache, int regnum) |
29639122 JB |
3827 | { |
3828 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 DJ |
3829 | = mips_stub_frame_cache (this_frame, this_cache); |
3830 | return trad_frame_get_register (this_trad_cache, this_frame, regnum); | |
29639122 | 3831 | } |
c906108c | 3832 | |
b8a22b94 DJ |
3833 | static int |
3834 | mips_stub_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 3835 | frame_info_ptr this_frame, void **this_cache) |
29639122 | 3836 | { |
aa6c981f | 3837 | gdb_byte dummy[4]; |
b8a22b94 | 3838 | CORE_ADDR pc = get_frame_address_in_block (this_frame); |
7cbd4a93 | 3839 | struct bound_minimal_symbol msym; |
979b38e0 | 3840 | |
aa6c981f | 3841 | /* Use the stub unwinder for unreadable code. */ |
b8a22b94 DJ |
3842 | if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) |
3843 | return 1; | |
aa6c981f | 3844 | |
3e5d3a5a | 3845 | if (in_plt_section (pc) || in_mips_stubs_section (pc)) |
b8a22b94 | 3846 | return 1; |
979b38e0 | 3847 | |
db5f024e DJ |
3848 | /* Calling a PIC function from a non-PIC function passes through a |
3849 | stub. The stub for foo is named ".pic.foo". */ | |
3850 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 3851 | if (msym.minsym != NULL |
c9d95fa3 CB |
3852 | && msym.minsym->linkage_name () != NULL |
3853 | && startswith (msym.minsym->linkage_name (), ".pic.")) | |
db5f024e DJ |
3854 | return 1; |
3855 | ||
b8a22b94 | 3856 | return 0; |
29639122 | 3857 | } |
c906108c | 3858 | |
b8a22b94 DJ |
3859 | static const struct frame_unwind mips_stub_frame_unwind = |
3860 | { | |
a154d838 | 3861 | "mips stub", |
b8a22b94 | 3862 | NORMAL_FRAME, |
8fbca658 | 3863 | default_frame_unwind_stop_reason, |
b8a22b94 DJ |
3864 | mips_stub_frame_this_id, |
3865 | mips_stub_frame_prev_register, | |
3866 | NULL, | |
3867 | mips_stub_frame_sniffer | |
3868 | }; | |
3869 | ||
29639122 | 3870 | static CORE_ADDR |
bd2b40ac | 3871 | mips_stub_frame_base_address (frame_info_ptr this_frame, |
29639122 JB |
3872 | void **this_cache) |
3873 | { | |
3874 | struct trad_frame_cache *this_trad_cache | |
b8a22b94 | 3875 | = mips_stub_frame_cache (this_frame, this_cache); |
29639122 JB |
3876 | return trad_frame_get_this_base (this_trad_cache); |
3877 | } | |
0fce0821 | 3878 | |
29639122 JB |
3879 | static const struct frame_base mips_stub_frame_base = |
3880 | { | |
3881 | &mips_stub_frame_unwind, | |
3882 | mips_stub_frame_base_address, | |
3883 | mips_stub_frame_base_address, | |
3884 | mips_stub_frame_base_address | |
3885 | }; | |
3886 | ||
3887 | static const struct frame_base * | |
bd2b40ac | 3888 | mips_stub_frame_base_sniffer (frame_info_ptr this_frame) |
29639122 | 3889 | { |
b8a22b94 | 3890 | if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) |
29639122 JB |
3891 | return &mips_stub_frame_base; |
3892 | else | |
3893 | return NULL; | |
3894 | } | |
3895 | ||
29639122 | 3896 | /* mips_addr_bits_remove - remove useless address bits */ |
65596487 | 3897 | |
29639122 | 3898 | static CORE_ADDR |
24568a2c | 3899 | mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
65596487 | 3900 | { |
08106042 | 3901 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
930bd0e0 | 3902 | |
29639122 JB |
3903 | if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
3904 | /* This hack is a work-around for existing boards using PMON, the | |
3905 | simulator, and any other 64-bit targets that doesn't have true | |
3906 | 64-bit addressing. On these targets, the upper 32 bits of | |
3907 | addresses are ignored by the hardware. Thus, the PC or SP are | |
3908 | likely to have been sign extended to all 1s by instruction | |
3909 | sequences that load 32-bit addresses. For example, a typical | |
3910 | piece of code that loads an address is this: | |
65596487 | 3911 | |
29639122 JB |
3912 | lui $r2, <upper 16 bits> |
3913 | ori $r2, <lower 16 bits> | |
65596487 | 3914 | |
29639122 JB |
3915 | But the lui sign-extends the value such that the upper 32 bits |
3916 | may be all 1s. The workaround is simply to mask off these | |
3917 | bits. In the future, gcc may be changed to support true 64-bit | |
3918 | addressing, and this masking will have to be disabled. */ | |
3919 | return addr &= 0xffffffffUL; | |
3920 | else | |
3921 | return addr; | |
65596487 JB |
3922 | } |
3923 | ||
3d5f6d12 DJ |
3924 | |
3925 | /* Checks for an atomic sequence of instructions beginning with a LL/LLD | |
3926 | instruction and ending with a SC/SCD instruction. If such a sequence | |
3927 | is found, attempt to step through it. A breakpoint is placed at the end of | |
3928 | the sequence. */ | |
3929 | ||
4cc0665f MR |
3930 | /* Instructions used during single-stepping of atomic sequences, standard |
3931 | ISA version. */ | |
3932 | #define LL_OPCODE 0x30 | |
3933 | #define LLD_OPCODE 0x34 | |
3934 | #define SC_OPCODE 0x38 | |
3935 | #define SCD_OPCODE 0x3c | |
3936 | ||
a0ff9e1a | 3937 | static std::vector<CORE_ADDR> |
93f9a11f | 3938 | mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
3d5f6d12 | 3939 | { |
70ab8ccd | 3940 | CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; |
3d5f6d12 DJ |
3941 | CORE_ADDR loc = pc; |
3942 | CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | |
4cc0665f | 3943 | ULONGEST insn; |
3d5f6d12 DJ |
3944 | int insn_count; |
3945 | int index; | |
3946 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
3947 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
3948 | ||
4cc0665f | 3949 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3950 | /* Assume all atomic sequences start with a ll/lld instruction. */ |
3951 | if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | |
a0ff9e1a | 3952 | return {}; |
3d5f6d12 DJ |
3953 | |
3954 | /* Assume that no atomic sequence is longer than "atomic_sequence_length" | |
3955 | instructions. */ | |
3956 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3957 | { | |
3958 | int is_branch = 0; | |
3959 | loc += MIPS_INSN32_SIZE; | |
4cc0665f | 3960 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
3d5f6d12 DJ |
3961 | |
3962 | /* Assume that there is at most one branch in the atomic | |
3963 | sequence. If a branch is found, put a breakpoint in its | |
3964 | destination address. */ | |
3965 | switch (itype_op (insn)) | |
3966 | { | |
3967 | case 0: /* SPECIAL */ | |
3968 | if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | |
a0ff9e1a | 3969 | return {}; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3970 | break; |
3971 | case 1: /* REGIMM */ | |
a385295e MR |
3972 | is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
3973 | || ((itype_rt (insn) & 0x1e) == 0 | |
3974 | && itype_rs (insn) == 0)); /* BPOSGE* */ | |
3d5f6d12 DJ |
3975 | break; |
3976 | case 2: /* J */ | |
3977 | case 3: /* JAL */ | |
a0ff9e1a | 3978 | return {}; /* fallback to the standard single-step code. */ |
3d5f6d12 DJ |
3979 | case 4: /* BEQ */ |
3980 | case 5: /* BNE */ | |
3981 | case 6: /* BLEZ */ | |
3982 | case 7: /* BGTZ */ | |
3983 | case 20: /* BEQL */ | |
3984 | case 21: /* BNEL */ | |
3985 | case 22: /* BLEZL */ | |
3986 | case 23: /* BGTTL */ | |
3987 | is_branch = 1; | |
3988 | break; | |
3989 | case 17: /* COP1 */ | |
a385295e MR |
3990 | is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
3991 | && (itype_rt (insn) & 0x2) == 0); | |
3992 | if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ | |
3993 | break; | |
3994 | /* Fall through. */ | |
3d5f6d12 DJ |
3995 | case 18: /* COP2 */ |
3996 | case 19: /* COP3 */ | |
3997 | is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | |
3998 | break; | |
3999 | } | |
4000 | if (is_branch) | |
4001 | { | |
4002 | branch_bp = loc + mips32_relative_offset (insn) + 4; | |
4003 | if (last_breakpoint >= 1) | |
a0ff9e1a SM |
4004 | return {}; /* More than one branch found, fallback to the |
4005 | standard single-step code. */ | |
3d5f6d12 DJ |
4006 | breaks[1] = branch_bp; |
4007 | last_breakpoint++; | |
4008 | } | |
4009 | ||
4010 | if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) | |
4011 | break; | |
4012 | } | |
4013 | ||
4014 | /* Assume that the atomic sequence ends with a sc/scd instruction. */ | |
4015 | if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) | |
a0ff9e1a | 4016 | return {}; |
3d5f6d12 DJ |
4017 | |
4018 | loc += MIPS_INSN32_SIZE; | |
4019 | ||
4020 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
4021 | breaks[0] = loc; | |
4022 | ||
4023 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
025bb325 | 4024 | placed (branch instruction's destination) in the atomic sequence. */ |
3d5f6d12 DJ |
4025 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
4026 | last_breakpoint = 0; | |
4027 | ||
a0ff9e1a SM |
4028 | std::vector<CORE_ADDR> next_pcs; |
4029 | ||
3d5f6d12 DJ |
4030 | /* Effectively inserts the breakpoints. */ |
4031 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 4032 | next_pcs.push_back (breaks[index]); |
3d5f6d12 | 4033 | |
93f9a11f | 4034 | return next_pcs; |
3d5f6d12 DJ |
4035 | } |
4036 | ||
a0ff9e1a | 4037 | static std::vector<CORE_ADDR> |
4cc0665f | 4038 | micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
4cc0665f MR |
4039 | CORE_ADDR pc) |
4040 | { | |
4041 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
4042 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
70ab8ccd | 4043 | CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; |
4b844a38 AT |
4044 | CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's |
4045 | destination. */ | |
4cc0665f MR |
4046 | CORE_ADDR loc = pc; |
4047 | int sc_found = 0; | |
4048 | ULONGEST insn; | |
4049 | int insn_count; | |
4050 | int index; | |
4051 | ||
4052 | /* Assume all atomic sequences start with a ll/lld instruction. */ | |
4053 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4054 | if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ | |
a0ff9e1a | 4055 | return {}; |
4cc0665f MR |
4056 | loc += MIPS_INSN16_SIZE; |
4057 | insn <<= 16; | |
4058 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4059 | if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ | |
a0ff9e1a | 4060 | return {}; |
4cc0665f MR |
4061 | loc += MIPS_INSN16_SIZE; |
4062 | ||
4063 | /* Assume all atomic sequences end with an sc/scd instruction. Assume | |
4064 | that no atomic sequence is longer than "atomic_sequence_length" | |
4065 | instructions. */ | |
4066 | for (insn_count = 0; | |
4067 | !sc_found && insn_count < atomic_sequence_length; | |
4068 | ++insn_count) | |
4069 | { | |
4070 | int is_branch = 0; | |
4071 | ||
4072 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); | |
4073 | loc += MIPS_INSN16_SIZE; | |
4074 | ||
4075 | /* Assume that there is at most one conditional branch in the | |
dda83cd7 SM |
4076 | atomic sequence. If a branch is found, put a breakpoint in |
4077 | its destination address. */ | |
4cc0665f MR |
4078 | switch (mips_insn_size (ISA_MICROMIPS, insn)) |
4079 | { | |
4cc0665f MR |
4080 | /* 32-bit instructions. */ |
4081 | case 2 * MIPS_INSN16_SIZE: | |
4082 | switch (micromips_op (insn)) | |
4083 | { | |
4084 | case 0x10: /* POOL32I: bits 010000 */ | |
4085 | if ((b5s5_op (insn) & 0x18) != 0x0 | |
4086 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ | |
4087 | /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ | |
4088 | && (b5s5_op (insn) & 0x1d) != 0x11 | |
4089 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ | |
4090 | && ((b5s5_op (insn) & 0x1e) != 0x14 | |
4091 | || (insn & 0x3) != 0x0) | |
4092 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ | |
4093 | && (b5s5_op (insn) & 0x1e) != 0x1a | |
4094 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ | |
4095 | && ((b5s5_op (insn) & 0x1e) != 0x1c | |
4096 | || (insn & 0x3) != 0x0) | |
4097 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ | |
4098 | && ((b5s5_op (insn) & 0x1c) != 0x1c | |
4099 | || (insn & 0x3) != 0x1)) | |
4100 | /* BC1ANY*: bits 010000 111xx xxx01 */ | |
4101 | break; | |
4102 | /* Fall through. */ | |
4103 | ||
4104 | case 0x25: /* BEQ: bits 100101 */ | |
4105 | case 0x2d: /* BNE: bits 101101 */ | |
4106 | insn <<= 16; | |
4107 | insn |= mips_fetch_instruction (gdbarch, | |
4108 | ISA_MICROMIPS, loc, NULL); | |
4109 | branch_bp = (loc + MIPS_INSN16_SIZE | |
4110 | + micromips_relative_offset16 (insn)); | |
4111 | is_branch = 1; | |
4112 | break; | |
4113 | ||
4114 | case 0x00: /* POOL32A: bits 000000 */ | |
4115 | insn <<= 16; | |
4116 | insn |= mips_fetch_instruction (gdbarch, | |
4117 | ISA_MICROMIPS, loc, NULL); | |
4118 | if (b0s6_op (insn) != 0x3c | |
4119 | /* POOL32Axf: bits 000000 ... 111100 */ | |
4120 | || (b6s10_ext (insn) & 0x2bf) != 0x3c) | |
4121 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
4122 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
4123 | break; | |
4124 | /* Fall through. */ | |
4125 | ||
4126 | case 0x1d: /* JALS: bits 011101 */ | |
4127 | case 0x35: /* J: bits 110101 */ | |
4128 | case 0x3d: /* JAL: bits 111101 */ | |
4129 | case 0x3c: /* JALX: bits 111100 */ | |
a0ff9e1a | 4130 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4131 | |
4132 | case 0x18: /* POOL32C: bits 011000 */ | |
4133 | if ((b12s4_op (insn) & 0xb) == 0xb) | |
4134 | /* SC, SCD: bits 011000 1x11 */ | |
4135 | sc_found = 1; | |
4136 | break; | |
4137 | } | |
4138 | loc += MIPS_INSN16_SIZE; | |
4139 | break; | |
4140 | ||
4141 | /* 16-bit instructions. */ | |
4142 | case MIPS_INSN16_SIZE: | |
4143 | switch (micromips_op (insn)) | |
4144 | { | |
4145 | case 0x23: /* BEQZ16: bits 100011 */ | |
4146 | case 0x2b: /* BNEZ16: bits 101011 */ | |
4147 | branch_bp = loc + micromips_relative_offset7 (insn); | |
4148 | is_branch = 1; | |
4149 | break; | |
4150 | ||
4151 | case 0x11: /* POOL16C: bits 010001 */ | |
4152 | if ((b5s5_op (insn) & 0x1c) != 0xc | |
4153 | /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ | |
dda83cd7 | 4154 | && b5s5_op (insn) != 0x18) |
4cc0665f | 4155 | /* JRADDIUSP: bits 010001 11000 */ |
dda83cd7 | 4156 | break; |
a0ff9e1a | 4157 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4158 | |
4159 | case 0x33: /* B16: bits 110011 */ | |
a0ff9e1a | 4160 | return {}; /* Fall back to the standard single-step code. */ |
4cc0665f MR |
4161 | } |
4162 | break; | |
4163 | } | |
4164 | if (is_branch) | |
4165 | { | |
4166 | if (last_breakpoint >= 1) | |
a0ff9e1a SM |
4167 | return {}; /* More than one branch found, fallback to the |
4168 | standard single-step code. */ | |
4cc0665f MR |
4169 | breaks[1] = branch_bp; |
4170 | last_breakpoint++; | |
4171 | } | |
4172 | } | |
4173 | if (!sc_found) | |
a0ff9e1a | 4174 | return {}; |
4cc0665f MR |
4175 | |
4176 | /* Insert a breakpoint right after the end of the atomic sequence. */ | |
4177 | breaks[0] = loc; | |
4178 | ||
4179 | /* Check for duplicated breakpoints. Check also for a breakpoint | |
4180 | placed (branch instruction's destination) in the atomic sequence */ | |
4181 | if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | |
4182 | last_breakpoint = 0; | |
4183 | ||
a0ff9e1a SM |
4184 | std::vector<CORE_ADDR> next_pcs; |
4185 | ||
4cc0665f MR |
4186 | /* Effectively inserts the breakpoints. */ |
4187 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 4188 | next_pcs.push_back (breaks[index]); |
4cc0665f | 4189 | |
93f9a11f | 4190 | return next_pcs; |
4cc0665f MR |
4191 | } |
4192 | ||
a0ff9e1a | 4193 | static std::vector<CORE_ADDR> |
93f9a11f | 4194 | deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) |
4cc0665f MR |
4195 | { |
4196 | if (mips_pc_is_mips (pc)) | |
93f9a11f | 4197 | return mips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4198 | else if (mips_pc_is_micromips (gdbarch, pc)) |
93f9a11f | 4199 | return micromips_deal_with_atomic_sequence (gdbarch, pc); |
4cc0665f | 4200 | else |
a0ff9e1a | 4201 | return {}; |
4cc0665f MR |
4202 | } |
4203 | ||
29639122 JB |
4204 | /* mips_software_single_step() is called just before we want to resume |
4205 | the inferior, if we want to single-step it but there is no hardware | |
4206 | or kernel single-step support (MIPS on GNU/Linux for example). We find | |
e0cd558a | 4207 | the target of the coming instruction and breakpoint it. */ |
29639122 | 4208 | |
a0ff9e1a | 4209 | std::vector<CORE_ADDR> |
f5ea389a | 4210 | mips_software_single_step (struct regcache *regcache) |
c906108c | 4211 | { |
ac7936df | 4212 | struct gdbarch *gdbarch = regcache->arch (); |
8181d85f | 4213 | CORE_ADDR pc, next_pc; |
65596487 | 4214 | |
7113a196 | 4215 | pc = regcache_read_pc (regcache); |
a0ff9e1a SM |
4216 | std::vector<CORE_ADDR> next_pcs = deal_with_atomic_sequence (gdbarch, pc); |
4217 | ||
4218 | if (!next_pcs.empty ()) | |
93f9a11f | 4219 | return next_pcs; |
3d5f6d12 | 4220 | |
7113a196 | 4221 | next_pc = mips_next_pc (regcache, pc); |
e6590a1b | 4222 | |
a0ff9e1a | 4223 | return {next_pc}; |
29639122 | 4224 | } |
a65bbe44 | 4225 | |
29639122 | 4226 | /* Test whether the PC points to the return instruction at the |
025bb325 | 4227 | end of a function. */ |
65596487 | 4228 | |
29639122 | 4229 | static int |
e17a4113 | 4230 | mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 | 4231 | { |
6321c22a MR |
4232 | ULONGEST insn; |
4233 | ULONGEST hint; | |
4234 | ||
4235 | /* This used to check for MIPS16, but this piece of code is never | |
4cc0665f MR |
4236 | called for MIPS16 functions. And likewise microMIPS ones. */ |
4237 | gdb_assert (mips_pc_is_mips (pc)); | |
6321c22a | 4238 | |
4cc0665f | 4239 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
6321c22a MR |
4240 | hint = 0x7c0; |
4241 | return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ | |
29639122 | 4242 | } |
c906108c | 4243 | |
c906108c | 4244 | |
29639122 JB |
4245 | /* This fencepost looks highly suspicious to me. Removing it also |
4246 | seems suspicious as it could affect remote debugging across serial | |
4247 | lines. */ | |
c906108c | 4248 | |
29639122 | 4249 | static CORE_ADDR |
74ed0bb4 | 4250 | heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
29639122 JB |
4251 | { |
4252 | CORE_ADDR start_pc; | |
4253 | CORE_ADDR fence; | |
4254 | int instlen; | |
4255 | int seen_adjsp = 0; | |
d6b48e9c | 4256 | struct inferior *inf; |
65596487 | 4257 | |
74ed0bb4 | 4258 | pc = gdbarch_addr_bits_remove (gdbarch, pc); |
29639122 JB |
4259 | start_pc = pc; |
4260 | fence = start_pc - heuristic_fence_post; | |
4261 | if (start_pc == 0) | |
4262 | return 0; | |
65596487 | 4263 | |
44096aee | 4264 | if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) |
29639122 | 4265 | fence = VM_MIN_ADDRESS; |
65596487 | 4266 | |
4cc0665f | 4267 | instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
98b4dd94 | 4268 | |
d6b48e9c PA |
4269 | inf = current_inferior (); |
4270 | ||
025bb325 | 4271 | /* Search back for previous return. */ |
29639122 JB |
4272 | for (start_pc -= instlen;; start_pc -= instlen) |
4273 | if (start_pc < fence) | |
4274 | { | |
4275 | /* It's not clear to me why we reach this point when | |
4276 | stop_soon, but with this test, at least we | |
4277 | don't print out warnings for every child forked (eg, on | |
4278 | decstation). 22apr93 rich@cygnus.com. */ | |
16c381f0 | 4279 | if (inf->control.stop_soon == NO_STOP_QUIETLY) |
29639122 JB |
4280 | { |
4281 | static int blurb_printed = 0; | |
98b4dd94 | 4282 | |
5af949e3 UW |
4283 | warning (_("GDB can't find the start of the function at %s."), |
4284 | paddress (gdbarch, pc)); | |
29639122 JB |
4285 | |
4286 | if (!blurb_printed) | |
4287 | { | |
4288 | /* This actually happens frequently in embedded | |
4289 | development, when you first connect to a board | |
4290 | and your stack pointer and pc are nowhere in | |
4291 | particular. This message needs to give people | |
4292 | in that situation enough information to | |
4293 | determine that it's no big deal. */ | |
6cb06a8c | 4294 | gdb_printf ("\n\ |
5af949e3 | 4295 | GDB is unable to find the start of the function at %s\n\ |
29639122 JB |
4296 | and thus can't determine the size of that function's stack frame.\n\ |
4297 | This means that GDB may be unable to access that stack frame, or\n\ | |
4298 | the frames below it.\n\ | |
4299 | This problem is most likely caused by an invalid program counter or\n\ | |
4300 | stack pointer.\n\ | |
4301 | However, if you think GDB should simply search farther back\n\ | |
5af949e3 | 4302 | from %s for code which looks like the beginning of a\n\ |
29639122 | 4303 | function, you can increase the range of the search using the `set\n\ |
5af949e3 | 4304 | heuristic-fence-post' command.\n", |
6cb06a8c | 4305 | paddress (gdbarch, pc), paddress (gdbarch, pc)); |
29639122 JB |
4306 | blurb_printed = 1; |
4307 | } | |
4308 | } | |
4309 | ||
4310 | return 0; | |
4311 | } | |
4cc0665f | 4312 | else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
29639122 JB |
4313 | { |
4314 | unsigned short inst; | |
4315 | ||
4316 | /* On MIPS16, any one of the following is likely to be the | |
4317 | start of a function: | |
24b21115 | 4318 | extend save |
193774b3 | 4319 | save |
29639122 JB |
4320 | entry |
4321 | addiu sp,-n | |
4322 | daddiu sp,-n | |
025bb325 | 4323 | extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
4cc0665f | 4324 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
193774b3 MR |
4325 | if ((inst & 0xff80) == 0x6480) /* save */ |
4326 | { | |
4327 | if (start_pc - instlen >= fence) | |
4328 | { | |
4cc0665f MR |
4329 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
4330 | start_pc - instlen, NULL); | |
193774b3 MR |
4331 | if ((inst & 0xf800) == 0xf000) /* extend */ |
4332 | start_pc -= instlen; | |
4333 | } | |
4334 | break; | |
4335 | } | |
4336 | else if (((inst & 0xf81f) == 0xe809 | |
4337 | && (inst & 0x700) != 0x700) /* entry */ | |
4338 | || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | |
4339 | || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | |
4340 | || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | |
29639122 JB |
4341 | break; |
4342 | else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | |
4343 | || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | |
4344 | seen_adjsp = 1; | |
4345 | else | |
4346 | seen_adjsp = 0; | |
4347 | } | |
4cc0665f MR |
4348 | else if (mips_pc_is_micromips (gdbarch, start_pc)) |
4349 | { | |
4350 | ULONGEST insn; | |
4351 | int stop = 0; | |
4352 | long offset; | |
4353 | int dreg; | |
4354 | int sreg; | |
4355 | ||
4356 | /* On microMIPS, any one of the following is likely to be the | |
4357 | start of a function: | |
4358 | ADDIUSP -imm | |
4359 | (D)ADDIU $sp, -imm | |
4360 | LUI $gp, imm */ | |
4361 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
4362 | switch (micromips_op (insn)) | |
4363 | { | |
4364 | case 0xc: /* ADDIU: bits 001100 */ | |
4365 | case 0x17: /* DADDIU: bits 010111 */ | |
4366 | sreg = b0s5_reg (insn); | |
4367 | dreg = b5s5_reg (insn); | |
4368 | insn <<= 16; | |
4369 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, | |
4370 | pc + MIPS_INSN16_SIZE, NULL); | |
4371 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
4372 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
4373 | /* (D)ADDIU $sp, imm */ | |
4374 | && offset < 0) | |
4375 | stop = 1; | |
4376 | break; | |
4377 | ||
4378 | case 0x10: /* POOL32I: bits 010000 */ | |
4379 | if (b5s5_op (insn) == 0xd | |
4380 | /* LUI: bits 010000 001101 */ | |
4381 | && b0s5_reg (insn >> 16) == 28) | |
4382 | /* LUI $gp, imm */ | |
4383 | stop = 1; | |
4384 | break; | |
4385 | ||
4386 | case 0x13: /* POOL16D: bits 010011 */ | |
4387 | if ((insn & 0x1) == 0x1) | |
4388 | /* ADDIUSP: bits 010011 1 */ | |
4389 | { | |
4390 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
4391 | if (offset < 0) | |
4392 | /* ADDIUSP -imm */ | |
4393 | stop = 1; | |
4394 | } | |
4395 | else | |
4396 | /* ADDIUS5: bits 010011 0 */ | |
4397 | { | |
4398 | dreg = b5s5_reg (insn); | |
4399 | offset = (b1s4_imm (insn) ^ 8) - 8; | |
4400 | if (dreg == MIPS_SP_REGNUM && offset < 0) | |
4401 | /* ADDIUS5 $sp, -imm */ | |
4402 | stop = 1; | |
4403 | } | |
4404 | break; | |
4405 | } | |
4406 | if (stop) | |
4407 | break; | |
4408 | } | |
e17a4113 | 4409 | else if (mips_about_to_return (gdbarch, start_pc)) |
29639122 | 4410 | { |
4c7d22cb | 4411 | /* Skip return and its delay slot. */ |
95ac2dcf | 4412 | start_pc += 2 * MIPS_INSN32_SIZE; |
29639122 JB |
4413 | break; |
4414 | } | |
4415 | ||
4416 | return start_pc; | |
c906108c SS |
4417 | } |
4418 | ||
6c0d6680 DJ |
4419 | struct mips_objfile_private |
4420 | { | |
4421 | bfd_size_type size; | |
4422 | char *contents; | |
4423 | }; | |
4424 | ||
f09ded24 AC |
4425 | /* According to the current ABI, should the type be passed in a |
4426 | floating-point register (assuming that there is space)? When there | |
a1f5b845 | 4427 | is no FPU, FP are not even considered as possible candidates for |
f09ded24 | 4428 | FP registers and, consequently this returns false - forces FP |
025bb325 | 4429 | arguments into integer registers. */ |
f09ded24 AC |
4430 | |
4431 | static int | |
74ed0bb4 MD |
4432 | fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, |
4433 | struct type *arg_type) | |
f09ded24 AC |
4434 | { |
4435 | return ((typecode == TYPE_CODE_FLT | |
345bd07c | 4436 | || (mips_eabi (gdbarch) |
6d82d43b AC |
4437 | && (typecode == TYPE_CODE_STRUCT |
4438 | || typecode == TYPE_CODE_UNION) | |
1f704f76 | 4439 | && arg_type->num_fields () == 1 |
940da03e | 4440 | && check_typedef (arg_type->field (0).type ())->code () |
b2d6f210 | 4441 | == TYPE_CODE_FLT)) |
345bd07c | 4442 | && mips_get_fpu_type (gdbarch) != MIPS_FPU_NONE); |
f09ded24 AC |
4443 | } |
4444 | ||
49e790b0 | 4445 | /* On o32, argument passing in GPRs depends on the alignment of the type being |
025bb325 | 4446 | passed. Return 1 if this type must be aligned to a doubleword boundary. */ |
49e790b0 DJ |
4447 | |
4448 | static int | |
4449 | mips_type_needs_double_align (struct type *type) | |
4450 | { | |
78134374 | 4451 | enum type_code typecode = type->code (); |
361d1df0 | 4452 | |
df86565b | 4453 | if (typecode == TYPE_CODE_FLT && type->length () == 8) |
49e790b0 DJ |
4454 | return 1; |
4455 | else if (typecode == TYPE_CODE_STRUCT) | |
4456 | { | |
1f704f76 | 4457 | if (type->num_fields () < 1) |
49e790b0 | 4458 | return 0; |
940da03e | 4459 | return mips_type_needs_double_align (type->field (0).type ()); |
49e790b0 DJ |
4460 | } |
4461 | else if (typecode == TYPE_CODE_UNION) | |
4462 | { | |
361d1df0 | 4463 | int i, n; |
49e790b0 | 4464 | |
1f704f76 | 4465 | n = type->num_fields (); |
49e790b0 | 4466 | for (i = 0; i < n; i++) |
940da03e | 4467 | if (mips_type_needs_double_align (type->field (i).type ())) |
49e790b0 DJ |
4468 | return 1; |
4469 | return 0; | |
4470 | } | |
4471 | return 0; | |
4472 | } | |
4473 | ||
dc604539 AC |
4474 | /* Adjust the address downward (direction of stack growth) so that it |
4475 | is correctly aligned for a new stack frame. */ | |
4476 | static CORE_ADDR | |
4477 | mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
4478 | { | |
5b03f266 | 4479 | return align_down (addr, 16); |
dc604539 AC |
4480 | } |
4481 | ||
8ae38c14 | 4482 | /* Implement the "push_dummy_code" gdbarch method. */ |
2c76a0c7 JB |
4483 | |
4484 | static CORE_ADDR | |
4485 | mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
4486 | CORE_ADDR funaddr, struct value **args, | |
4487 | int nargs, struct type *value_type, | |
4488 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
4489 | struct regcache *regcache) | |
4490 | { | |
2c76a0c7 | 4491 | static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; |
2e81047f MR |
4492 | CORE_ADDR nop_addr; |
4493 | CORE_ADDR bp_slot; | |
2c76a0c7 JB |
4494 | |
4495 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
2e81047f MR |
4496 | bp_slot = sp - sizeof (nop_insn); |
4497 | ||
4498 | /* Return to microMIPS mode if calling microMIPS code to avoid | |
4499 | triggering an address error exception on processors that only | |
4500 | support microMIPS execution. */ | |
4501 | *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) | |
4502 | ? make_compact_addr (bp_slot) : bp_slot); | |
2c76a0c7 JB |
4503 | |
4504 | /* The breakpoint layer automatically adjusts the address of | |
4505 | breakpoints inserted in a branch delay slot. With enough | |
4506 | bad luck, the 4 bytes located just before our breakpoint | |
4507 | instruction could look like a branch instruction, and thus | |
4508 | trigger the adjustement, and break the function call entirely. | |
4509 | So, we reserve those 4 bytes and write a nop instruction | |
4510 | to prevent that from happening. */ | |
2e81047f | 4511 | nop_addr = bp_slot - sizeof (nop_insn); |
2c76a0c7 JB |
4512 | write_memory (nop_addr, nop_insn, sizeof (nop_insn)); |
4513 | sp = mips_frame_align (gdbarch, nop_addr); | |
4514 | ||
4515 | /* Inferior resumes at the function entry point. */ | |
4516 | *real_pc = funaddr; | |
4517 | ||
4518 | return sp; | |
4519 | } | |
4520 | ||
f7ab6ec6 | 4521 | static CORE_ADDR |
7d9b040b | 4522 | mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4523 | struct regcache *regcache, CORE_ADDR bp_addr, |
4524 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
4525 | function_call_return_method return_method, |
4526 | CORE_ADDR struct_addr) | |
c906108c SS |
4527 | { |
4528 | int argreg; | |
4529 | int float_argreg; | |
4530 | int argnum; | |
b926417a | 4531 | int arg_space = 0; |
c906108c | 4532 | int stack_offset = 0; |
e17a4113 | 4533 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4534 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
b3464d03 | 4535 | int abi_regsize = mips_abi_regsize (gdbarch); |
c906108c | 4536 | |
25ab4790 AC |
4537 | /* For shared libraries, "t9" needs to point at the function |
4538 | address. */ | |
4c7d22cb | 4539 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4540 | |
4541 | /* Set the return address register to point to the entry point of | |
4542 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4543 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4544 | |
c906108c | 4545 | /* First ensure that the stack and structure return address (if any) |
cb3d25d1 MS |
4546 | are properly aligned. The stack has to be at least 64-bit |
4547 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4548 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4549 | aligned, so we round to this widest known alignment. */ | |
4550 | ||
5b03f266 AC |
4551 | sp = align_down (sp, 16); |
4552 | struct_addr = align_down (struct_addr, 16); | |
c5aa993b | 4553 | |
46e0f506 | 4554 | /* Now make space on the stack for the args. We allocate more |
c906108c | 4555 | than necessary for EABI, because the first few arguments are |
46e0f506 | 4556 | passed in registers, but that's OK. */ |
c906108c | 4557 | for (argnum = 0; argnum < nargs; argnum++) |
d0c97917 | 4558 | arg_space += align_up (args[argnum]->type ()->length (), |
df86565b | 4559 | abi_regsize); |
b926417a | 4560 | sp -= align_up (arg_space, 16); |
c906108c | 4561 | |
9ace0497 | 4562 | if (mips_debug) |
6cb06a8c TT |
4563 | gdb_printf (gdb_stdlog, |
4564 | "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", | |
4565 | paddress (gdbarch, sp), | |
4566 | (long) align_up (arg_space, 16)); | |
9ace0497 | 4567 | |
c906108c | 4568 | /* Initialize the integer and float register pointers. */ |
4c7d22cb | 4569 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4570 | float_argreg = mips_fpa0_regnum (gdbarch); |
c906108c | 4571 | |
46e0f506 | 4572 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cf84fa6b | 4573 | if (return_method == return_method_struct) |
9ace0497 AC |
4574 | { |
4575 | if (mips_debug) | |
6cb06a8c TT |
4576 | gdb_printf (gdb_stdlog, |
4577 | "mips_eabi_push_dummy_call: " | |
4578 | "struct_return reg=%d %s\n", | |
4579 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 4580 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
9ace0497 | 4581 | } |
c906108c SS |
4582 | |
4583 | /* Now load as many as possible of the first arguments into | |
4584 | registers, and push the rest onto the stack. Loop thru args | |
4585 | from first to last. */ | |
4586 | for (argnum = 0; argnum < nargs; argnum++) | |
4587 | { | |
47a35522 | 4588 | const gdb_byte *val; |
b3464d03 PA |
4589 | /* This holds the address of structures that are passed by |
4590 | reference. */ | |
4591 | gdb_byte ref_valbuf[MAX_MIPS_ABI_REGSIZE]; | |
ea7c478f | 4592 | struct value *arg = args[argnum]; |
d0c97917 | 4593 | struct type *arg_type = check_typedef (arg->type ()); |
df86565b | 4594 | int len = arg_type->length (); |
78134374 | 4595 | enum type_code typecode = arg_type->code (); |
c906108c | 4596 | |
9ace0497 | 4597 | if (mips_debug) |
6cb06a8c TT |
4598 | gdb_printf (gdb_stdlog, |
4599 | "mips_eabi_push_dummy_call: %d len=%d type=%d", | |
4600 | argnum + 1, len, (int) typecode); | |
9ace0497 | 4601 | |
c906108c | 4602 | /* The EABI passes structures that do not fit in a register by |
dda83cd7 | 4603 | reference. */ |
b3464d03 | 4604 | if (len > abi_regsize |
9ace0497 | 4605 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
c906108c | 4606 | { |
b3464d03 PA |
4607 | gdb_assert (abi_regsize <= ARRAY_SIZE (ref_valbuf)); |
4608 | store_unsigned_integer (ref_valbuf, abi_regsize, byte_order, | |
9feb2d07 | 4609 | arg->address ()); |
c906108c | 4610 | typecode = TYPE_CODE_PTR; |
b3464d03 PA |
4611 | len = abi_regsize; |
4612 | val = ref_valbuf; | |
9ace0497 | 4613 | if (mips_debug) |
6cb06a8c | 4614 | gdb_printf (gdb_stdlog, " push"); |
c906108c SS |
4615 | } |
4616 | else | |
efaf1ae0 | 4617 | val = arg->contents ().data (); |
c906108c SS |
4618 | |
4619 | /* 32-bit ABIs always start floating point arguments in an | |
dda83cd7 SM |
4620 | even-numbered floating point register. Round the FP register |
4621 | up before the check to see if there are any FP registers | |
4622 | left. Non MIPS_EABI targets also pass the FP in the integer | |
4623 | registers so also round up normal registers. */ | |
b3464d03 | 4624 | if (abi_regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) |
acdb74a0 AC |
4625 | { |
4626 | if ((float_argreg & 1)) | |
4627 | float_argreg++; | |
4628 | } | |
c906108c SS |
4629 | |
4630 | /* Floating point arguments passed in registers have to be | |
dda83cd7 SM |
4631 | treated specially. On 32-bit architectures, doubles |
4632 | are passed in register pairs; the even register gets | |
4633 | the low word, and the odd register gets the high word. | |
4634 | On non-EABI processors, the first two floating point arguments are | |
4635 | also copied to general registers, because MIPS16 functions | |
4636 | don't use float registers for arguments. This duplication of | |
4637 | arguments in general registers can't hurt non-MIPS16 functions | |
4638 | because those registers are normally skipped. */ | |
1012bd0e | 4639 | /* MIPS_EABI squeezes a struct that contains a single floating |
dda83cd7 SM |
4640 | point value into an FP register instead of pushing it onto the |
4641 | stack. */ | |
74ed0bb4 | 4642 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
345bd07c | 4643 | && float_argreg <= mips_last_fp_arg_regnum (gdbarch)) |
c906108c | 4644 | { |
6da397e0 KB |
4645 | /* EABI32 will pass doubles in consecutive registers, even on |
4646 | 64-bit cores. At one time, we used to check the size of | |
4647 | `float_argreg' to determine whether or not to pass doubles | |
4648 | in consecutive registers, but this is not sufficient for | |
4649 | making the ABI determination. */ | |
4650 | if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) | |
c906108c | 4651 | { |
72a155b4 | 4652 | int low_offset = gdbarch_byte_order (gdbarch) |
4c6b5505 | 4653 | == BFD_ENDIAN_BIG ? 4 : 0; |
a8852dc5 | 4654 | long regval; |
c906108c SS |
4655 | |
4656 | /* Write the low word of the double to the even register(s). */ | |
a8852dc5 KB |
4657 | regval = extract_signed_integer (val + low_offset, |
4658 | 4, byte_order); | |
9ace0497 | 4659 | if (mips_debug) |
6cb06a8c TT |
4660 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
4661 | float_argreg, phex (regval, 4)); | |
a8852dc5 | 4662 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4663 | |
4664 | /* Write the high word of the double to the odd register(s). */ | |
a8852dc5 KB |
4665 | regval = extract_signed_integer (val + 4 - low_offset, |
4666 | 4, byte_order); | |
9ace0497 | 4667 | if (mips_debug) |
6cb06a8c TT |
4668 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
4669 | float_argreg, phex (regval, 4)); | |
a8852dc5 | 4670 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4671 | } |
4672 | else | |
4673 | { | |
4674 | /* This is a floating point value that fits entirely | |
dda83cd7 | 4675 | in a single register. */ |
53a5351d | 4676 | /* On 32 bit ABI's the float_argreg is further adjusted |
dda83cd7 | 4677 | above to ensure that it is even register aligned. */ |
a8852dc5 | 4678 | LONGEST regval = extract_signed_integer (val, len, byte_order); |
9ace0497 | 4679 | if (mips_debug) |
6cb06a8c TT |
4680 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
4681 | float_argreg, phex (regval, len)); | |
a8852dc5 | 4682 | regcache_cooked_write_signed (regcache, float_argreg++, regval); |
c906108c SS |
4683 | } |
4684 | } | |
4685 | else | |
4686 | { | |
4687 | /* Copy the argument to general registers or the stack in | |
4688 | register-sized pieces. Large arguments are split between | |
4689 | registers and stack. */ | |
b3464d03 | 4690 | /* Note: structs whose size is not a multiple of abi_regsize |
1a69e1e4 | 4691 | are treated specially: Irix cc passes |
d5ac5a39 AC |
4692 | them in registers where gcc sometimes puts them on the |
4693 | stack. For maximum compatibility, we will put them in | |
4694 | both places. */ | |
b3464d03 | 4695 | int odd_sized_struct = (len > abi_regsize && len % abi_regsize != 0); |
46e0f506 | 4696 | |
f09ded24 | 4697 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 4698 | register are only written to memory. */ |
c906108c SS |
4699 | while (len > 0) |
4700 | { | |
ebafbe83 | 4701 | /* Remember if the argument was written to the stack. */ |
566f0f7a | 4702 | int stack_used_p = 0; |
b3464d03 | 4703 | int partial_len = (len < abi_regsize ? len : abi_regsize); |
c906108c | 4704 | |
acdb74a0 | 4705 | if (mips_debug) |
6cb06a8c TT |
4706 | gdb_printf (gdb_stdlog, " -- partial=%d", |
4707 | partial_len); | |
acdb74a0 | 4708 | |
566f0f7a | 4709 | /* Write this portion of the argument to the stack. */ |
345bd07c | 4710 | if (argreg > mips_last_arg_regnum (gdbarch) |
f09ded24 | 4711 | || odd_sized_struct |
74ed0bb4 | 4712 | || fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4713 | { |
c906108c | 4714 | /* Should shorter than int integer values be |
025bb325 | 4715 | promoted to int before being stored? */ |
c906108c | 4716 | int longword_offset = 0; |
9ace0497 | 4717 | CORE_ADDR addr; |
566f0f7a | 4718 | stack_used_p = 1; |
72a155b4 | 4719 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
7a292a7a | 4720 | { |
b3464d03 | 4721 | if (abi_regsize == 8 |
480d3dd2 AC |
4722 | && (typecode == TYPE_CODE_INT |
4723 | || typecode == TYPE_CODE_PTR | |
6d82d43b | 4724 | || typecode == TYPE_CODE_FLT) && len <= 4) |
b3464d03 | 4725 | longword_offset = abi_regsize - len; |
480d3dd2 AC |
4726 | else if ((typecode == TYPE_CODE_STRUCT |
4727 | || typecode == TYPE_CODE_UNION) | |
df86565b | 4728 | && arg_type->length () < abi_regsize) |
b3464d03 | 4729 | longword_offset = abi_regsize - len; |
7a292a7a | 4730 | } |
c5aa993b | 4731 | |
9ace0497 AC |
4732 | if (mips_debug) |
4733 | { | |
6cb06a8c TT |
4734 | gdb_printf (gdb_stdlog, " - stack_offset=%s", |
4735 | paddress (gdbarch, stack_offset)); | |
4736 | gdb_printf (gdb_stdlog, " longword_offset=%s", | |
4737 | paddress (gdbarch, longword_offset)); | |
9ace0497 | 4738 | } |
361d1df0 | 4739 | |
9ace0497 AC |
4740 | addr = sp + stack_offset + longword_offset; |
4741 | ||
4742 | if (mips_debug) | |
4743 | { | |
4744 | int i; | |
6cb06a8c TT |
4745 | gdb_printf (gdb_stdlog, " @%s ", |
4746 | paddress (gdbarch, addr)); | |
9ace0497 AC |
4747 | for (i = 0; i < partial_len; i++) |
4748 | { | |
6cb06a8c TT |
4749 | gdb_printf (gdb_stdlog, "%02x", |
4750 | val[i] & 0xff); | |
9ace0497 AC |
4751 | } |
4752 | } | |
4753 | write_memory (addr, val, partial_len); | |
c906108c SS |
4754 | } |
4755 | ||
f09ded24 | 4756 | /* Note!!! This is NOT an else clause. Odd sized |
dda83cd7 SM |
4757 | structs may go thru BOTH paths. Floating point |
4758 | arguments will not. */ | |
566f0f7a | 4759 | /* Write this portion of the argument to a general |
dda83cd7 | 4760 | purpose register. */ |
345bd07c | 4761 | if (argreg <= mips_last_arg_regnum (gdbarch) |
74ed0bb4 | 4762 | && !fp_register_arg_p (gdbarch, typecode, arg_type)) |
c906108c | 4763 | { |
6d82d43b | 4764 | LONGEST regval = |
a8852dc5 | 4765 | extract_signed_integer (val, partial_len, byte_order); |
c906108c | 4766 | |
9ace0497 | 4767 | if (mips_debug) |
6cb06a8c TT |
4768 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
4769 | argreg, | |
4770 | phex (regval, abi_regsize)); | |
a8852dc5 | 4771 | regcache_cooked_write_signed (regcache, argreg, regval); |
c906108c | 4772 | argreg++; |
c906108c | 4773 | } |
c5aa993b | 4774 | |
c906108c SS |
4775 | len -= partial_len; |
4776 | val += partial_len; | |
4777 | ||
b021a221 | 4778 | /* Compute the offset into the stack at which we will |
dda83cd7 | 4779 | copy the next parameter. |
566f0f7a | 4780 | |
dda83cd7 SM |
4781 | In the new EABI (and the NABI32), the stack_offset |
4782 | only needs to be adjusted when it has been used. */ | |
c906108c | 4783 | |
46e0f506 | 4784 | if (stack_used_p) |
b3464d03 | 4785 | stack_offset += align_up (partial_len, abi_regsize); |
c906108c SS |
4786 | } |
4787 | } | |
9ace0497 | 4788 | if (mips_debug) |
6cb06a8c | 4789 | gdb_printf (gdb_stdlog, "\n"); |
c906108c SS |
4790 | } |
4791 | ||
f10683bb | 4792 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 4793 | |
0f71a2f6 JM |
4794 | /* Return adjusted stack pointer. */ |
4795 | return sp; | |
4796 | } | |
4797 | ||
a1f5b845 | 4798 | /* Determine the return value convention being used. */ |
6d82d43b | 4799 | |
9c8fdbfa | 4800 | static enum return_value_convention |
6a3a010b | 4801 | mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 4802 | struct type *type, struct regcache *regcache, |
47a35522 | 4803 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 4804 | { |
08106042 | 4805 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
609ba780 JM |
4806 | int fp_return_type = 0; |
4807 | int offset, regnum, xfer; | |
4808 | ||
df86565b | 4809 | if (type->length () > 2 * mips_abi_regsize (gdbarch)) |
9c8fdbfa | 4810 | return RETURN_VALUE_STRUCT_CONVENTION; |
609ba780 JM |
4811 | |
4812 | /* Floating point type? */ | |
4813 | if (tdep->mips_fpu_type != MIPS_FPU_NONE) | |
4814 | { | |
78134374 | 4815 | if (type->code () == TYPE_CODE_FLT) |
609ba780 JM |
4816 | fp_return_type = 1; |
4817 | /* Structs with a single field of float type | |
4818 | are returned in a floating point register. */ | |
78134374 SM |
4819 | if ((type->code () == TYPE_CODE_STRUCT |
4820 | || type->code () == TYPE_CODE_UNION) | |
1f704f76 | 4821 | && type->num_fields () == 1) |
609ba780 | 4822 | { |
940da03e | 4823 | struct type *fieldtype = type->field (0).type (); |
609ba780 | 4824 | |
78134374 | 4825 | if (check_typedef (fieldtype)->code () == TYPE_CODE_FLT) |
609ba780 JM |
4826 | fp_return_type = 1; |
4827 | } | |
4828 | } | |
4829 | ||
4830 | if (fp_return_type) | |
4831 | { | |
4832 | /* A floating-point value belongs in the least significant part | |
4833 | of FP0/FP1. */ | |
4834 | if (mips_debug) | |
6cb06a8c | 4835 | gdb_printf (gdb_stderr, "Return float in $fp0\n"); |
609ba780 JM |
4836 | regnum = mips_regnum (gdbarch)->fp0; |
4837 | } | |
4838 | else | |
4839 | { | |
4840 | /* An integer value goes in V0/V1. */ | |
4841 | if (mips_debug) | |
6cb06a8c | 4842 | gdb_printf (gdb_stderr, "Return scalar in $v0\n"); |
609ba780 JM |
4843 | regnum = MIPS_V0_REGNUM; |
4844 | } | |
4845 | for (offset = 0; | |
df86565b | 4846 | offset < type->length (); |
609ba780 JM |
4847 | offset += mips_abi_regsize (gdbarch), regnum++) |
4848 | { | |
4849 | xfer = mips_abi_regsize (gdbarch); | |
df86565b SM |
4850 | if (offset + xfer > type->length ()) |
4851 | xfer = type->length () - offset; | |
609ba780 JM |
4852 | mips_xfer_register (gdbarch, regcache, |
4853 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
4854 | gdbarch_byte_order (gdbarch), readbuf, writebuf, | |
4855 | offset); | |
4856 | } | |
4857 | ||
9c8fdbfa | 4858 | return RETURN_VALUE_REGISTER_CONVENTION; |
6d82d43b AC |
4859 | } |
4860 | ||
6d82d43b AC |
4861 | |
4862 | /* N32/N64 ABI stuff. */ | |
ebafbe83 | 4863 | |
8d26208a DJ |
4864 | /* Search for a naturally aligned double at OFFSET inside a struct |
4865 | ARG_TYPE. The N32 / N64 ABIs pass these in floating point | |
4866 | registers. */ | |
4867 | ||
4868 | static int | |
74ed0bb4 MD |
4869 | mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, |
4870 | int offset) | |
8d26208a DJ |
4871 | { |
4872 | int i; | |
4873 | ||
78134374 | 4874 | if (arg_type->code () != TYPE_CODE_STRUCT) |
8d26208a DJ |
4875 | return 0; |
4876 | ||
345bd07c | 4877 | if (mips_get_fpu_type (gdbarch) != MIPS_FPU_DOUBLE) |
8d26208a DJ |
4878 | return 0; |
4879 | ||
df86565b | 4880 | if (arg_type->length () < offset + MIPS64_REGSIZE) |
8d26208a DJ |
4881 | return 0; |
4882 | ||
1f704f76 | 4883 | for (i = 0; i < arg_type->num_fields (); i++) |
8d26208a DJ |
4884 | { |
4885 | int pos; | |
4886 | struct type *field_type; | |
4887 | ||
4888 | /* We're only looking at normal fields. */ | |
c819a338 | 4889 | if (arg_type->field (i).is_static () |
b610c045 | 4890 | || (arg_type->field (i).loc_bitpos () % 8) != 0) |
8d26208a DJ |
4891 | continue; |
4892 | ||
4893 | /* If we have gone past the offset, there is no double to pass. */ | |
b610c045 | 4894 | pos = arg_type->field (i).loc_bitpos () / 8; |
8d26208a DJ |
4895 | if (pos > offset) |
4896 | return 0; | |
4897 | ||
940da03e | 4898 | field_type = check_typedef (arg_type->field (i).type ()); |
8d26208a DJ |
4899 | |
4900 | /* If this field is entirely before the requested offset, go | |
4901 | on to the next one. */ | |
df86565b | 4902 | if (pos + field_type->length () <= offset) |
8d26208a DJ |
4903 | continue; |
4904 | ||
4905 | /* If this is our special aligned double, we can stop. */ | |
78134374 | 4906 | if (field_type->code () == TYPE_CODE_FLT |
df86565b | 4907 | && field_type->length () == MIPS64_REGSIZE) |
8d26208a DJ |
4908 | return 1; |
4909 | ||
4910 | /* This field starts at or before the requested offset, and | |
4911 | overlaps it. If it is a structure, recurse inwards. */ | |
74ed0bb4 | 4912 | return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); |
8d26208a DJ |
4913 | } |
4914 | ||
4915 | return 0; | |
4916 | } | |
4917 | ||
f7ab6ec6 | 4918 | static CORE_ADDR |
7d9b040b | 4919 | mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
4920 | struct regcache *regcache, CORE_ADDR bp_addr, |
4921 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
4922 | function_call_return_method return_method, |
4923 | CORE_ADDR struct_addr) | |
cb3d25d1 MS |
4924 | { |
4925 | int argreg; | |
4926 | int float_argreg; | |
4927 | int argnum; | |
b926417a | 4928 | int arg_space = 0; |
cb3d25d1 | 4929 | int stack_offset = 0; |
e17a4113 | 4930 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 4931 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
cb3d25d1 | 4932 | |
25ab4790 AC |
4933 | /* For shared libraries, "t9" needs to point at the function |
4934 | address. */ | |
4c7d22cb | 4935 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
4936 | |
4937 | /* Set the return address register to point to the entry point of | |
4938 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 4939 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 4940 | |
cb3d25d1 MS |
4941 | /* First ensure that the stack and structure return address (if any) |
4942 | are properly aligned. The stack has to be at least 64-bit | |
4943 | aligned even on 32-bit machines, because doubles must be 64-bit | |
4944 | aligned. For n32 and n64, stack frames need to be 128-bit | |
4945 | aligned, so we round to this widest known alignment. */ | |
4946 | ||
5b03f266 AC |
4947 | sp = align_down (sp, 16); |
4948 | struct_addr = align_down (struct_addr, 16); | |
cb3d25d1 MS |
4949 | |
4950 | /* Now make space on the stack for the args. */ | |
4951 | for (argnum = 0; argnum < nargs; argnum++) | |
d0c97917 | 4952 | arg_space += align_up (args[argnum]->type ()->length (), |
df86565b | 4953 | MIPS64_REGSIZE); |
b926417a | 4954 | sp -= align_up (arg_space, 16); |
cb3d25d1 MS |
4955 | |
4956 | if (mips_debug) | |
6cb06a8c TT |
4957 | gdb_printf (gdb_stdlog, |
4958 | "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", | |
4959 | paddress (gdbarch, sp), | |
4960 | (long) align_up (arg_space, 16)); | |
cb3d25d1 MS |
4961 | |
4962 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 4963 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 4964 | float_argreg = mips_fpa0_regnum (gdbarch); |
cb3d25d1 | 4965 | |
46e0f506 | 4966 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cf84fa6b | 4967 | if (return_method == return_method_struct) |
cb3d25d1 MS |
4968 | { |
4969 | if (mips_debug) | |
6cb06a8c TT |
4970 | gdb_printf (gdb_stdlog, |
4971 | "mips_n32n64_push_dummy_call: " | |
4972 | "struct_return reg=%d %s\n", | |
4973 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 4974 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
cb3d25d1 MS |
4975 | } |
4976 | ||
4977 | /* Now load as many as possible of the first arguments into | |
4978 | registers, and push the rest onto the stack. Loop thru args | |
4979 | from first to last. */ | |
4980 | for (argnum = 0; argnum < nargs; argnum++) | |
4981 | { | |
47a35522 | 4982 | const gdb_byte *val; |
cb3d25d1 | 4983 | struct value *arg = args[argnum]; |
d0c97917 | 4984 | struct type *arg_type = check_typedef (arg->type ()); |
df86565b | 4985 | int len = arg_type->length (); |
78134374 | 4986 | enum type_code typecode = arg_type->code (); |
cb3d25d1 MS |
4987 | |
4988 | if (mips_debug) | |
6cb06a8c TT |
4989 | gdb_printf (gdb_stdlog, |
4990 | "mips_n32n64_push_dummy_call: %d len=%d type=%d", | |
4991 | argnum + 1, len, (int) typecode); | |
cb3d25d1 | 4992 | |
efaf1ae0 | 4993 | val = arg->contents ().data (); |
cb3d25d1 | 4994 | |
5b68030f JM |
4995 | /* A 128-bit long double value requires an even-odd pair of |
4996 | floating-point registers. */ | |
4997 | if (len == 16 | |
4998 | && fp_register_arg_p (gdbarch, typecode, arg_type) | |
4999 | && (float_argreg & 1)) | |
5000 | { | |
5001 | float_argreg++; | |
5002 | argreg++; | |
5003 | } | |
5004 | ||
74ed0bb4 | 5005 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
345bd07c | 5006 | && argreg <= mips_last_arg_regnum (gdbarch)) |
cb3d25d1 MS |
5007 | { |
5008 | /* This is a floating point value that fits entirely | |
5b68030f JM |
5009 | in a single register or a pair of registers. */ |
5010 | int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); | |
e17a4113 | 5011 | LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); |
cb3d25d1 | 5012 | if (mips_debug) |
6cb06a8c TT |
5013 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5014 | float_argreg, phex (regval, reglen)); | |
8d26208a | 5015 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
cb3d25d1 MS |
5016 | |
5017 | if (mips_debug) | |
6cb06a8c TT |
5018 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5019 | argreg, phex (regval, reglen)); | |
9c9acae0 | 5020 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a DJ |
5021 | float_argreg++; |
5022 | argreg++; | |
5b68030f JM |
5023 | if (len == 16) |
5024 | { | |
e17a4113 UW |
5025 | regval = extract_unsigned_integer (val + reglen, |
5026 | reglen, byte_order); | |
5b68030f | 5027 | if (mips_debug) |
6cb06a8c TT |
5028 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5029 | float_argreg, phex (regval, reglen)); | |
5b68030f JM |
5030 | regcache_cooked_write_unsigned (regcache, float_argreg, regval); |
5031 | ||
5032 | if (mips_debug) | |
6cb06a8c TT |
5033 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5034 | argreg, phex (regval, reglen)); | |
5b68030f JM |
5035 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
5036 | float_argreg++; | |
5037 | argreg++; | |
5038 | } | |
cb3d25d1 MS |
5039 | } |
5040 | else | |
5041 | { | |
5042 | /* Copy the argument to general registers or the stack in | |
5043 | register-sized pieces. Large arguments are split between | |
5044 | registers and stack. */ | |
ab2e1992 MR |
5045 | /* For N32/N64, structs, unions, or other composite types are |
5046 | treated as a sequence of doublewords, and are passed in integer | |
5047 | or floating point registers as though they were simple scalar | |
5048 | parameters to the extent that they fit, with any excess on the | |
5049 | stack packed according to the normal memory layout of the | |
5050 | object. | |
5051 | The caller does not reserve space for the register arguments; | |
5052 | the callee is responsible for reserving it if required. */ | |
cb3d25d1 | 5053 | /* Note: Floating-point values that didn't fit into an FP |
6d82d43b | 5054 | register are only written to memory. */ |
cb3d25d1 MS |
5055 | while (len > 0) |
5056 | { | |
ad018eee | 5057 | /* Remember if the argument was written to the stack. */ |
cb3d25d1 | 5058 | int stack_used_p = 0; |
1a69e1e4 | 5059 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
cb3d25d1 MS |
5060 | |
5061 | if (mips_debug) | |
6cb06a8c TT |
5062 | gdb_printf (gdb_stdlog, " -- partial=%d", |
5063 | partial_len); | |
cb3d25d1 | 5064 | |
74ed0bb4 | 5065 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
345bd07c | 5066 | gdb_assert (argreg > mips_last_arg_regnum (gdbarch)); |
8d26208a | 5067 | |
cb3d25d1 | 5068 | /* Write this portion of the argument to the stack. */ |
345bd07c | 5069 | if (argreg > mips_last_arg_regnum (gdbarch)) |
cb3d25d1 MS |
5070 | { |
5071 | /* Should shorter than int integer values be | |
025bb325 | 5072 | promoted to int before being stored? */ |
cb3d25d1 MS |
5073 | int longword_offset = 0; |
5074 | CORE_ADDR addr; | |
5075 | stack_used_p = 1; | |
72a155b4 | 5076 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
cb3d25d1 | 5077 | { |
1a69e1e4 | 5078 | if ((typecode == TYPE_CODE_INT |
5b68030f | 5079 | || typecode == TYPE_CODE_PTR) |
1a69e1e4 DJ |
5080 | && len <= 4) |
5081 | longword_offset = MIPS64_REGSIZE - len; | |
cb3d25d1 MS |
5082 | } |
5083 | ||
5084 | if (mips_debug) | |
5085 | { | |
6cb06a8c TT |
5086 | gdb_printf (gdb_stdlog, " - stack_offset=%s", |
5087 | paddress (gdbarch, stack_offset)); | |
5088 | gdb_printf (gdb_stdlog, " longword_offset=%s", | |
5089 | paddress (gdbarch, longword_offset)); | |
cb3d25d1 MS |
5090 | } |
5091 | ||
5092 | addr = sp + stack_offset + longword_offset; | |
5093 | ||
5094 | if (mips_debug) | |
5095 | { | |
5096 | int i; | |
6cb06a8c TT |
5097 | gdb_printf (gdb_stdlog, " @%s ", |
5098 | paddress (gdbarch, addr)); | |
cb3d25d1 MS |
5099 | for (i = 0; i < partial_len; i++) |
5100 | { | |
6cb06a8c TT |
5101 | gdb_printf (gdb_stdlog, "%02x", |
5102 | val[i] & 0xff); | |
cb3d25d1 MS |
5103 | } |
5104 | } | |
5105 | write_memory (addr, val, partial_len); | |
5106 | } | |
5107 | ||
5108 | /* Note!!! This is NOT an else clause. Odd sized | |
dda83cd7 | 5109 | structs may go thru BOTH paths. */ |
cb3d25d1 | 5110 | /* Write this portion of the argument to a general |
dda83cd7 | 5111 | purpose register. */ |
345bd07c | 5112 | if (argreg <= mips_last_arg_regnum (gdbarch)) |
cb3d25d1 | 5113 | { |
5863b5d5 MR |
5114 | LONGEST regval; |
5115 | ||
5116 | /* Sign extend pointers, 32-bit integers and signed | |
5117 | 16-bit and 8-bit integers; everything else is taken | |
5118 | as is. */ | |
5119 | ||
5120 | if ((partial_len == 4 | |
5121 | && (typecode == TYPE_CODE_PTR | |
5122 | || typecode == TYPE_CODE_INT)) | |
5123 | || (partial_len < 4 | |
5124 | && typecode == TYPE_CODE_INT | |
c6d940a9 | 5125 | && !arg_type->is_unsigned ())) |
e17a4113 UW |
5126 | regval = extract_signed_integer (val, partial_len, |
5127 | byte_order); | |
5863b5d5 | 5128 | else |
e17a4113 UW |
5129 | regval = extract_unsigned_integer (val, partial_len, |
5130 | byte_order); | |
cb3d25d1 MS |
5131 | |
5132 | /* A non-floating-point argument being passed in a | |
5133 | general register. If a struct or union, and if | |
5134 | the remaining length is smaller than the register | |
5135 | size, we have to adjust the register value on | |
5136 | big endian targets. | |
5137 | ||
5138 | It does not seem to be necessary to do the | |
1a69e1e4 | 5139 | same for integral types. */ |
cb3d25d1 | 5140 | |
72a155b4 | 5141 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5142 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
5143 | && (typecode == TYPE_CODE_STRUCT |
5144 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5145 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 5146 | * TARGET_CHAR_BIT); |
cb3d25d1 MS |
5147 | |
5148 | if (mips_debug) | |
6cb06a8c TT |
5149 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5150 | argreg, | |
5151 | phex (regval, MIPS64_REGSIZE)); | |
9c9acae0 | 5152 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
8d26208a | 5153 | |
74ed0bb4 | 5154 | if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, |
df86565b | 5155 | arg_type->length () - len)) |
8d26208a DJ |
5156 | { |
5157 | if (mips_debug) | |
6cb06a8c TT |
5158 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5159 | float_argreg, | |
5160 | phex (regval, MIPS64_REGSIZE)); | |
8d26208a DJ |
5161 | regcache_cooked_write_unsigned (regcache, float_argreg, |
5162 | regval); | |
5163 | } | |
5164 | ||
5165 | float_argreg++; | |
cb3d25d1 MS |
5166 | argreg++; |
5167 | } | |
5168 | ||
5169 | len -= partial_len; | |
5170 | val += partial_len; | |
5171 | ||
b021a221 | 5172 | /* Compute the offset into the stack at which we will |
dda83cd7 | 5173 | copy the next parameter. |
cb3d25d1 | 5174 | |
dda83cd7 SM |
5175 | In N32 (N64?), the stack_offset only needs to be |
5176 | adjusted when it has been used. */ | |
cb3d25d1 MS |
5177 | |
5178 | if (stack_used_p) | |
1a69e1e4 | 5179 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
cb3d25d1 MS |
5180 | } |
5181 | } | |
5182 | if (mips_debug) | |
6cb06a8c | 5183 | gdb_printf (gdb_stdlog, "\n"); |
cb3d25d1 MS |
5184 | } |
5185 | ||
f10683bb | 5186 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5187 | |
cb3d25d1 MS |
5188 | /* Return adjusted stack pointer. */ |
5189 | return sp; | |
5190 | } | |
5191 | ||
6d82d43b | 5192 | static enum return_value_convention |
6a3a010b | 5193 | mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
6d82d43b | 5194 | struct type *type, struct regcache *regcache, |
47a35522 | 5195 | gdb_byte *readbuf, const gdb_byte *writebuf) |
ebafbe83 | 5196 | { |
08106042 | 5197 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
b18bb924 MR |
5198 | |
5199 | /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | |
5200 | ||
5201 | Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | |
5202 | if needed), as appropriate for the type. Composite results (struct, | |
5203 | union, or array) are returned in $2/$f0 and $3/$f2 according to the | |
5204 | following rules: | |
5205 | ||
5206 | * A struct with only one or two floating point fields is returned in $f0 | |
5207 | (and $f2 if necessary). This is a generalization of the Fortran COMPLEX | |
5208 | case. | |
5209 | ||
f08877ba | 5210 | * Any other composite results of at most 128 bits are returned in |
b18bb924 MR |
5211 | $2 (first 64 bits) and $3 (remainder, if necessary). |
5212 | ||
5213 | * Larger composite results are handled by converting the function to a | |
5214 | procedure with an implicit first parameter, which is a pointer to an area | |
5215 | reserved by the caller to receive the result. [The o32-bit ABI requires | |
5216 | that all composite results be handled by conversion to implicit first | |
5217 | parameters. The MIPS/SGI Fortran implementation has always made a | |
5218 | specific exception to return COMPLEX results in the floating point | |
089169c0 YT |
5219 | registers.] |
5220 | ||
5221 | From MIPSpro Assembly Language Programmer's Guide, Document Number: | |
5222 | 007-2418-004 | |
5223 | ||
287de656 | 5224 | Software |
089169c0 YT |
5225 | Register Name(from |
5226 | Name fgregdef.h) Use and Linkage | |
5227 | ----------------------------------------------------------------- | |
5228 | $f0, $f2 fv0, fv1 Hold results of floating-point type function | |
287de656 SM |
5229 | ($f0) and complex type function ($f0 has the |
5230 | real part, $f2 has the imaginary part.) */ | |
b18bb924 | 5231 | |
df86565b | 5232 | if (type->length () > 2 * MIPS64_REGSIZE) |
6d82d43b | 5233 | return RETURN_VALUE_STRUCT_CONVENTION; |
089169c0 | 5234 | else if ((type->code () == TYPE_CODE_COMPLEX |
df86565b | 5235 | || (type->code () == TYPE_CODE_FLT && type->length () == 16)) |
d05f6826 DJ |
5236 | && tdep->mips_fpu_type != MIPS_FPU_NONE) |
5237 | { | |
089169c0 YT |
5238 | /* A complex value of up to 128 bits in width as well as a 128-bit |
5239 | floating-point value goes in both $f0 and $f2. A single complex | |
5240 | value is held in the lower halves only of the respective registers. | |
5241 | The two registers are used in the same as memory order, so the | |
5242 | bytes with the lower memory address are in $f0. */ | |
d05f6826 | 5243 | if (mips_debug) |
6cb06a8c | 5244 | gdb_printf (gdb_stderr, "Return float in $f0 and $f2\n"); |
ba32f989 | 5245 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5246 | (gdbarch_num_regs (gdbarch) |
5247 | + mips_regnum (gdbarch)->fp0), | |
df86565b | 5248 | type->length () / 2, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5249 | readbuf, writebuf, 0); |
ba32f989 | 5250 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5251 | (gdbarch_num_regs (gdbarch) |
5252 | + mips_regnum (gdbarch)->fp0 + 2), | |
df86565b SM |
5253 | type->length () / 2, gdbarch_byte_order (gdbarch), |
5254 | readbuf ? readbuf + type->length () / 2 : readbuf, | |
089169c0 | 5255 | (writebuf |
df86565b | 5256 | ? writebuf + type->length () / 2 : writebuf), 0); |
d05f6826 DJ |
5257 | return RETURN_VALUE_REGISTER_CONVENTION; |
5258 | } | |
78134374 | 5259 | else if (type->code () == TYPE_CODE_FLT |
6d82d43b AC |
5260 | && tdep->mips_fpu_type != MIPS_FPU_NONE) |
5261 | { | |
59aa1faa | 5262 | /* A single or double floating-point value that fits in FP0. */ |
6d82d43b | 5263 | if (mips_debug) |
6cb06a8c | 5264 | gdb_printf (gdb_stderr, "Return float in $fp0\n"); |
ba32f989 | 5265 | mips_xfer_register (gdbarch, regcache, |
dca9aa3a MR |
5266 | (gdbarch_num_regs (gdbarch) |
5267 | + mips_regnum (gdbarch)->fp0), | |
df86565b | 5268 | type->length (), |
72a155b4 | 5269 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5270 | readbuf, writebuf, 0); |
6d82d43b AC |
5271 | return RETURN_VALUE_REGISTER_CONVENTION; |
5272 | } | |
78134374 | 5273 | else if (type->code () == TYPE_CODE_STRUCT |
1f704f76 SM |
5274 | && type->num_fields () <= 2 |
5275 | && type->num_fields () >= 1 | |
5276 | && ((type->num_fields () == 1 | |
940da03e | 5277 | && (check_typedef (type->field (0).type ())->code () |
6d82d43b | 5278 | == TYPE_CODE_FLT)) |
1f704f76 | 5279 | || (type->num_fields () == 2 |
940da03e | 5280 | && (check_typedef (type->field (0).type ())->code () |
6d82d43b | 5281 | == TYPE_CODE_FLT) |
940da03e | 5282 | && (check_typedef (type->field (1).type ())->code () |
5b68030f | 5283 | == TYPE_CODE_FLT)))) |
6d82d43b AC |
5284 | { |
5285 | /* A struct that contains one or two floats. Each value is part | |
dda83cd7 SM |
5286 | in the least significant part of their floating point |
5287 | register (or GPR, for soft float). */ | |
6d82d43b AC |
5288 | int regnum; |
5289 | int field; | |
5b68030f JM |
5290 | for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE |
5291 | ? mips_regnum (gdbarch)->fp0 | |
5292 | : MIPS_V0_REGNUM); | |
1f704f76 | 5293 | field < type->num_fields (); field++, regnum += 2) |
6d82d43b | 5294 | { |
3a543e21 | 5295 | int offset = type->field (field).loc_bitpos () / TARGET_CHAR_BIT; |
6d82d43b | 5296 | if (mips_debug) |
6cb06a8c TT |
5297 | gdb_printf (gdb_stderr, "Return float struct+%d\n", |
5298 | offset); | |
df86565b | 5299 | if (type->field (field).type ()->length () == 16) |
5b68030f JM |
5300 | { |
5301 | /* A 16-byte long double field goes in two consecutive | |
5302 | registers. */ | |
5303 | mips_xfer_register (gdbarch, regcache, | |
5304 | gdbarch_num_regs (gdbarch) + regnum, | |
5305 | 8, | |
5306 | gdbarch_byte_order (gdbarch), | |
5307 | readbuf, writebuf, offset); | |
5308 | mips_xfer_register (gdbarch, regcache, | |
5309 | gdbarch_num_regs (gdbarch) + regnum + 1, | |
5310 | 8, | |
5311 | gdbarch_byte_order (gdbarch), | |
5312 | readbuf, writebuf, offset + 8); | |
5313 | } | |
5314 | else | |
5315 | mips_xfer_register (gdbarch, regcache, | |
5316 | gdbarch_num_regs (gdbarch) + regnum, | |
df86565b | 5317 | type->field (field).type ()->length (), |
5b68030f JM |
5318 | gdbarch_byte_order (gdbarch), |
5319 | readbuf, writebuf, offset); | |
6d82d43b AC |
5320 | } |
5321 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5322 | } | |
78134374 SM |
5323 | else if (type->code () == TYPE_CODE_STRUCT |
5324 | || type->code () == TYPE_CODE_UNION | |
5325 | || type->code () == TYPE_CODE_ARRAY) | |
6d82d43b | 5326 | { |
f08877ba | 5327 | /* A composite type. Extract the left justified value, |
dda83cd7 SM |
5328 | regardless of the byte order. I.e. DO NOT USE |
5329 | mips_xfer_lower. */ | |
6d82d43b AC |
5330 | int offset; |
5331 | int regnum; | |
4c7d22cb | 5332 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
df86565b | 5333 | offset < type->length (); |
72a155b4 | 5334 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5335 | { |
72a155b4 | 5336 | int xfer = register_size (gdbarch, regnum); |
df86565b SM |
5337 | if (offset + xfer > type->length ()) |
5338 | xfer = type->length () - offset; | |
6d82d43b | 5339 | if (mips_debug) |
6cb06a8c TT |
5340 | gdb_printf (gdb_stderr, "Return struct+%d:%d in $%d\n", |
5341 | offset, xfer, regnum); | |
ba32f989 DJ |
5342 | mips_xfer_register (gdbarch, regcache, |
5343 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 UW |
5344 | xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, |
5345 | offset); | |
6d82d43b AC |
5346 | } |
5347 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5348 | } | |
5349 | else | |
5350 | { | |
5351 | /* A scalar extract each part but least-significant-byte | |
dda83cd7 | 5352 | justified. */ |
6d82d43b AC |
5353 | int offset; |
5354 | int regnum; | |
4c7d22cb | 5355 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
df86565b | 5356 | offset < type->length (); |
72a155b4 | 5357 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5358 | { |
72a155b4 | 5359 | int xfer = register_size (gdbarch, regnum); |
df86565b SM |
5360 | if (offset + xfer > type->length ()) |
5361 | xfer = type->length () - offset; | |
6d82d43b | 5362 | if (mips_debug) |
6cb06a8c TT |
5363 | gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
5364 | offset, xfer, regnum); | |
ba32f989 DJ |
5365 | mips_xfer_register (gdbarch, regcache, |
5366 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 5367 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5368 | readbuf, writebuf, offset); |
6d82d43b AC |
5369 | } |
5370 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5371 | } | |
5372 | } | |
5373 | ||
6a3a010b MR |
5374 | /* Which registers to use for passing floating-point values between |
5375 | function calls, one of floating-point, general and both kinds of | |
5376 | registers. O32 and O64 use different register kinds for standard | |
5377 | MIPS and MIPS16 code; to make the handling of cases where we may | |
5378 | not know what kind of code is being used (e.g. no debug information) | |
5379 | easier we sometimes use both kinds. */ | |
5380 | ||
5381 | enum mips_fval_reg | |
5382 | { | |
5383 | mips_fval_fpr, | |
5384 | mips_fval_gpr, | |
5385 | mips_fval_both | |
5386 | }; | |
5387 | ||
6d82d43b AC |
5388 | /* O32 ABI stuff. */ |
5389 | ||
5390 | static CORE_ADDR | |
7d9b040b | 5391 | mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5392 | struct regcache *regcache, CORE_ADDR bp_addr, |
5393 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
5394 | function_call_return_method return_method, |
5395 | CORE_ADDR struct_addr) | |
6d82d43b AC |
5396 | { |
5397 | int argreg; | |
5398 | int float_argreg; | |
5399 | int argnum; | |
b926417a | 5400 | int arg_space = 0; |
6d82d43b | 5401 | int stack_offset = 0; |
e17a4113 | 5402 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5403 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
6d82d43b AC |
5404 | |
5405 | /* For shared libraries, "t9" needs to point at the function | |
5406 | address. */ | |
4c7d22cb | 5407 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
6d82d43b AC |
5408 | |
5409 | /* Set the return address register to point to the entry point of | |
5410 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5411 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
6d82d43b AC |
5412 | |
5413 | /* First ensure that the stack and structure return address (if any) | |
5414 | are properly aligned. The stack has to be at least 64-bit | |
5415 | aligned even on 32-bit machines, because doubles must be 64-bit | |
ebafbe83 MS |
5416 | aligned. For n32 and n64, stack frames need to be 128-bit |
5417 | aligned, so we round to this widest known alignment. */ | |
5418 | ||
5b03f266 AC |
5419 | sp = align_down (sp, 16); |
5420 | struct_addr = align_down (struct_addr, 16); | |
ebafbe83 MS |
5421 | |
5422 | /* Now make space on the stack for the args. */ | |
5423 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 | 5424 | { |
d0c97917 | 5425 | struct type *arg_type = check_typedef (args[argnum]->type ()); |
968b5391 MR |
5426 | |
5427 | /* Align to double-word if necessary. */ | |
2afd3f0a | 5428 | if (mips_type_needs_double_align (arg_type)) |
b926417a | 5429 | arg_space = align_up (arg_space, MIPS32_REGSIZE * 2); |
968b5391 | 5430 | /* Allocate space on the stack. */ |
df86565b | 5431 | arg_space += align_up (arg_type->length (), MIPS32_REGSIZE); |
968b5391 | 5432 | } |
b926417a | 5433 | sp -= align_up (arg_space, 16); |
ebafbe83 MS |
5434 | |
5435 | if (mips_debug) | |
6cb06a8c TT |
5436 | gdb_printf (gdb_stdlog, |
5437 | "mips_o32_push_dummy_call: sp=%s allocated %ld\n", | |
5438 | paddress (gdbarch, sp), | |
5439 | (long) align_up (arg_space, 16)); | |
ebafbe83 MS |
5440 | |
5441 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5442 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5443 | float_argreg = mips_fpa0_regnum (gdbarch); |
ebafbe83 | 5444 | |
bcb0cc15 | 5445 | /* The struct_return pointer occupies the first parameter-passing reg. */ |
cf84fa6b | 5446 | if (return_method == return_method_struct) |
ebafbe83 MS |
5447 | { |
5448 | if (mips_debug) | |
6cb06a8c TT |
5449 | gdb_printf (gdb_stdlog, |
5450 | "mips_o32_push_dummy_call: " | |
5451 | "struct_return reg=%d %s\n", | |
5452 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 5453 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5454 | stack_offset += MIPS32_REGSIZE; |
ebafbe83 MS |
5455 | } |
5456 | ||
5457 | /* Now load as many as possible of the first arguments into | |
5458 | registers, and push the rest onto the stack. Loop thru args | |
5459 | from first to last. */ | |
5460 | for (argnum = 0; argnum < nargs; argnum++) | |
5461 | { | |
47a35522 | 5462 | const gdb_byte *val; |
ebafbe83 | 5463 | struct value *arg = args[argnum]; |
d0c97917 | 5464 | struct type *arg_type = check_typedef (arg->type ()); |
df86565b | 5465 | int len = arg_type->length (); |
78134374 | 5466 | enum type_code typecode = arg_type->code (); |
ebafbe83 MS |
5467 | |
5468 | if (mips_debug) | |
6cb06a8c TT |
5469 | gdb_printf (gdb_stdlog, |
5470 | "mips_o32_push_dummy_call: %d len=%d type=%d", | |
5471 | argnum + 1, len, (int) typecode); | |
46cac009 | 5472 | |
efaf1ae0 | 5473 | val = arg->contents ().data (); |
46cac009 AC |
5474 | |
5475 | /* 32-bit ABIs always start floating point arguments in an | |
dda83cd7 SM |
5476 | even-numbered floating point register. Round the FP register |
5477 | up before the check to see if there are any FP registers | |
5478 | left. O32 targets also pass the FP in the integer registers | |
5479 | so also round up normal registers. */ | |
74ed0bb4 | 5480 | if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
46cac009 AC |
5481 | { |
5482 | if ((float_argreg & 1)) | |
5483 | float_argreg++; | |
5484 | } | |
5485 | ||
5486 | /* Floating point arguments passed in registers have to be | |
dda83cd7 SM |
5487 | treated specially. On 32-bit architectures, doubles are |
5488 | passed in register pairs; the even FP register gets the | |
5489 | low word, and the odd FP register gets the high word. | |
5490 | On O32, the first two floating point arguments are also | |
5491 | copied to general registers, following their memory order, | |
5492 | because MIPS16 functions don't use float registers for | |
5493 | arguments. This duplication of arguments in general | |
5494 | registers can't hurt non-MIPS16 functions, because those | |
5495 | registers are normally skipped. */ | |
46cac009 | 5496 | |
74ed0bb4 | 5497 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
345bd07c | 5498 | && float_argreg <= mips_last_fp_arg_regnum (gdbarch)) |
46cac009 | 5499 | { |
8b07f6d8 | 5500 | if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
46cac009 | 5501 | { |
6a3a010b MR |
5502 | int freg_offset = gdbarch_byte_order (gdbarch) |
5503 | == BFD_ENDIAN_BIG ? 1 : 0; | |
46cac009 AC |
5504 | unsigned long regval; |
5505 | ||
6a3a010b MR |
5506 | /* First word. */ |
5507 | regval = extract_unsigned_integer (val, 4, byte_order); | |
46cac009 | 5508 | if (mips_debug) |
6cb06a8c TT |
5509 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5510 | float_argreg + freg_offset, | |
5511 | phex (regval, 4)); | |
025bb325 | 5512 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5513 | float_argreg++ + freg_offset, |
5514 | regval); | |
46cac009 | 5515 | if (mips_debug) |
6cb06a8c TT |
5516 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5517 | argreg, phex (regval, 4)); | |
9c9acae0 | 5518 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 | 5519 | |
6a3a010b MR |
5520 | /* Second word. */ |
5521 | regval = extract_unsigned_integer (val + 4, 4, byte_order); | |
46cac009 | 5522 | if (mips_debug) |
6cb06a8c TT |
5523 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5524 | float_argreg - freg_offset, | |
5525 | phex (regval, 4)); | |
025bb325 | 5526 | regcache_cooked_write_unsigned (regcache, |
6a3a010b MR |
5527 | float_argreg++ - freg_offset, |
5528 | regval); | |
46cac009 | 5529 | if (mips_debug) |
6cb06a8c TT |
5530 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5531 | argreg, phex (regval, 4)); | |
9c9acae0 | 5532 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5533 | } |
5534 | else | |
5535 | { | |
5536 | /* This is a floating point value that fits entirely | |
dda83cd7 | 5537 | in a single register. */ |
46cac009 | 5538 | /* On 32 bit ABI's the float_argreg is further adjusted |
dda83cd7 | 5539 | above to ensure that it is even register aligned. */ |
e17a4113 | 5540 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
46cac009 | 5541 | if (mips_debug) |
6cb06a8c TT |
5542 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
5543 | float_argreg, phex (regval, len)); | |
025bb325 MS |
5544 | regcache_cooked_write_unsigned (regcache, |
5545 | float_argreg++, regval); | |
5b68030f JM |
5546 | /* Although two FP registers are reserved for each |
5547 | argument, only one corresponding integer register is | |
5548 | reserved. */ | |
46cac009 | 5549 | if (mips_debug) |
6cb06a8c TT |
5550 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5551 | argreg, phex (regval, len)); | |
5b68030f | 5552 | regcache_cooked_write_unsigned (regcache, argreg++, regval); |
46cac009 AC |
5553 | } |
5554 | /* Reserve space for the FP register. */ | |
1a69e1e4 | 5555 | stack_offset += align_up (len, MIPS32_REGSIZE); |
46cac009 AC |
5556 | } |
5557 | else | |
5558 | { | |
5559 | /* Copy the argument to general registers or the stack in | |
5560 | register-sized pieces. Large arguments are split between | |
5561 | registers and stack. */ | |
1a69e1e4 DJ |
5562 | /* Note: structs whose size is not a multiple of MIPS32_REGSIZE |
5563 | are treated specially: Irix cc passes | |
d5ac5a39 AC |
5564 | them in registers where gcc sometimes puts them on the |
5565 | stack. For maximum compatibility, we will put them in | |
5566 | both places. */ | |
1a69e1e4 DJ |
5567 | int odd_sized_struct = (len > MIPS32_REGSIZE |
5568 | && len % MIPS32_REGSIZE != 0); | |
46cac009 AC |
5569 | /* Structures should be aligned to eight bytes (even arg registers) |
5570 | on MIPS_ABI_O32, if their first member has double precision. */ | |
2afd3f0a | 5571 | if (mips_type_needs_double_align (arg_type)) |
46cac009 AC |
5572 | { |
5573 | if ((argreg & 1)) | |
968b5391 MR |
5574 | { |
5575 | argreg++; | |
1a69e1e4 | 5576 | stack_offset += MIPS32_REGSIZE; |
968b5391 | 5577 | } |
46cac009 | 5578 | } |
46cac009 AC |
5579 | while (len > 0) |
5580 | { | |
1a69e1e4 | 5581 | int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); |
46cac009 AC |
5582 | |
5583 | if (mips_debug) | |
6cb06a8c TT |
5584 | gdb_printf (gdb_stdlog, " -- partial=%d", |
5585 | partial_len); | |
46cac009 AC |
5586 | |
5587 | /* Write this portion of the argument to the stack. */ | |
345bd07c | 5588 | if (argreg > mips_last_arg_regnum (gdbarch) |
968b5391 | 5589 | || odd_sized_struct) |
46cac009 AC |
5590 | { |
5591 | /* Should shorter than int integer values be | |
025bb325 | 5592 | promoted to int before being stored? */ |
46cac009 AC |
5593 | int longword_offset = 0; |
5594 | CORE_ADDR addr; | |
46cac009 AC |
5595 | |
5596 | if (mips_debug) | |
5597 | { | |
6cb06a8c TT |
5598 | gdb_printf (gdb_stdlog, " - stack_offset=%s", |
5599 | paddress (gdbarch, stack_offset)); | |
5600 | gdb_printf (gdb_stdlog, " longword_offset=%s", | |
5601 | paddress (gdbarch, longword_offset)); | |
46cac009 AC |
5602 | } |
5603 | ||
5604 | addr = sp + stack_offset + longword_offset; | |
5605 | ||
5606 | if (mips_debug) | |
5607 | { | |
5608 | int i; | |
6cb06a8c TT |
5609 | gdb_printf (gdb_stdlog, " @%s ", |
5610 | paddress (gdbarch, addr)); | |
46cac009 AC |
5611 | for (i = 0; i < partial_len; i++) |
5612 | { | |
6cb06a8c TT |
5613 | gdb_printf (gdb_stdlog, "%02x", |
5614 | val[i] & 0xff); | |
46cac009 AC |
5615 | } |
5616 | } | |
5617 | write_memory (addr, val, partial_len); | |
5618 | } | |
5619 | ||
5620 | /* Note!!! This is NOT an else clause. Odd sized | |
dda83cd7 | 5621 | structs may go thru BOTH paths. */ |
46cac009 | 5622 | /* Write this portion of the argument to a general |
dda83cd7 | 5623 | purpose register. */ |
345bd07c | 5624 | if (argreg <= mips_last_arg_regnum (gdbarch)) |
46cac009 | 5625 | { |
e17a4113 UW |
5626 | LONGEST regval = extract_signed_integer (val, partial_len, |
5627 | byte_order); | |
4246e332 | 5628 | /* Value may need to be sign extended, because |
1b13c4f6 | 5629 | mips_isa_regsize() != mips_abi_regsize(). */ |
46cac009 AC |
5630 | |
5631 | /* A non-floating-point argument being passed in a | |
5632 | general register. If a struct or union, and if | |
5633 | the remaining length is smaller than the register | |
5634 | size, we have to adjust the register value on | |
5635 | big endian targets. | |
5636 | ||
5637 | It does not seem to be necessary to do the | |
5638 | same for integral types. | |
5639 | ||
5640 | Also don't do this adjustment on O64 binaries. | |
5641 | ||
5642 | cagney/2001-07-23: gdb/179: Also, GCC, when | |
5643 | outputting LE O32 with sizeof (struct) < | |
e914cb17 MR |
5644 | mips_abi_regsize(), generates a left shift |
5645 | as part of storing the argument in a register | |
5646 | (the left shift isn't generated when | |
1b13c4f6 | 5647 | sizeof (struct) >= mips_abi_regsize()). Since |
480d3dd2 AC |
5648 | it is quite possible that this is GCC |
5649 | contradicting the LE/O32 ABI, GDB has not been | |
5650 | adjusted to accommodate this. Either someone | |
5651 | needs to demonstrate that the LE/O32 ABI | |
5652 | specifies such a left shift OR this new ABI gets | |
5653 | identified as such and GDB gets tweaked | |
5654 | accordingly. */ | |
5655 | ||
72a155b4 | 5656 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 5657 | && partial_len < MIPS32_REGSIZE |
06f9a1af MR |
5658 | && (typecode == TYPE_CODE_STRUCT |
5659 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 5660 | regval <<= ((MIPS32_REGSIZE - partial_len) |
9ecf7166 | 5661 | * TARGET_CHAR_BIT); |
46cac009 AC |
5662 | |
5663 | if (mips_debug) | |
6cb06a8c TT |
5664 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
5665 | argreg, | |
5666 | phex (regval, MIPS32_REGSIZE)); | |
9c9acae0 | 5667 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
46cac009 AC |
5668 | argreg++; |
5669 | ||
5670 | /* Prevent subsequent floating point arguments from | |
5671 | being passed in floating point registers. */ | |
345bd07c | 5672 | float_argreg = mips_last_fp_arg_regnum (gdbarch) + 1; |
46cac009 AC |
5673 | } |
5674 | ||
5675 | len -= partial_len; | |
5676 | val += partial_len; | |
5677 | ||
b021a221 | 5678 | /* Compute the offset into the stack at which we will |
dda83cd7 | 5679 | copy the next parameter. |
46cac009 | 5680 | |
dda83cd7 SM |
5681 | In older ABIs, the caller reserved space for |
5682 | registers that contained arguments. This was loosely | |
33b5899f | 5683 | referred to as their "home". Consequently, space is |
dda83cd7 | 5684 | always allocated. */ |
46cac009 | 5685 | |
1a69e1e4 | 5686 | stack_offset += align_up (partial_len, MIPS32_REGSIZE); |
46cac009 AC |
5687 | } |
5688 | } | |
5689 | if (mips_debug) | |
6cb06a8c | 5690 | gdb_printf (gdb_stdlog, "\n"); |
46cac009 AC |
5691 | } |
5692 | ||
f10683bb | 5693 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 5694 | |
46cac009 AC |
5695 | /* Return adjusted stack pointer. */ |
5696 | return sp; | |
5697 | } | |
5698 | ||
6d82d43b | 5699 | static enum return_value_convention |
6a3a010b | 5700 | mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 5701 | struct type *type, struct regcache *regcache, |
47a35522 | 5702 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 5703 | { |
6a3a010b | 5704 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 5705 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
08106042 | 5706 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
6a3a010b | 5707 | enum mips_fval_reg fval_reg; |
6d82d43b | 5708 | |
6a3a010b | 5709 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
78134374 SM |
5710 | if (type->code () == TYPE_CODE_STRUCT |
5711 | || type->code () == TYPE_CODE_UNION | |
5712 | || type->code () == TYPE_CODE_ARRAY) | |
6d82d43b | 5713 | return RETURN_VALUE_STRUCT_CONVENTION; |
78134374 | 5714 | else if (type->code () == TYPE_CODE_FLT |
df86565b | 5715 | && type->length () == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
6d82d43b | 5716 | { |
6a3a010b | 5717 | /* A single-precision floating-point value. If reading in or copying, |
dda83cd7 SM |
5718 | then we get it from/put it to FP0 for standard MIPS code or GPR2 |
5719 | for MIPS16 code. If writing out only, then we put it to both FP0 | |
5720 | and GPR2. We do not support reading in with no function known, if | |
5721 | this safety check ever triggers, then we'll have to try harder. */ | |
6a3a010b | 5722 | gdb_assert (function || !readbuf); |
6d82d43b | 5723 | if (mips_debug) |
6a3a010b MR |
5724 | switch (fval_reg) |
5725 | { | |
5726 | case mips_fval_fpr: | |
6cb06a8c | 5727 | gdb_printf (gdb_stderr, "Return float in $fp0\n"); |
6a3a010b MR |
5728 | break; |
5729 | case mips_fval_gpr: | |
6cb06a8c | 5730 | gdb_printf (gdb_stderr, "Return float in $2\n"); |
6a3a010b MR |
5731 | break; |
5732 | case mips_fval_both: | |
6cb06a8c | 5733 | gdb_printf (gdb_stderr, "Return float in $fp0 and $2\n"); |
6a3a010b MR |
5734 | break; |
5735 | } | |
5736 | if (fval_reg != mips_fval_gpr) | |
5737 | mips_xfer_register (gdbarch, regcache, | |
5738 | (gdbarch_num_regs (gdbarch) | |
5739 | + mips_regnum (gdbarch)->fp0), | |
df86565b | 5740 | type->length (), |
6a3a010b MR |
5741 | gdbarch_byte_order (gdbarch), |
5742 | readbuf, writebuf, 0); | |
5743 | if (fval_reg != mips_fval_fpr) | |
5744 | mips_xfer_register (gdbarch, regcache, | |
5745 | gdbarch_num_regs (gdbarch) + 2, | |
df86565b | 5746 | type->length (), |
6a3a010b MR |
5747 | gdbarch_byte_order (gdbarch), |
5748 | readbuf, writebuf, 0); | |
6d82d43b AC |
5749 | return RETURN_VALUE_REGISTER_CONVENTION; |
5750 | } | |
78134374 | 5751 | else if (type->code () == TYPE_CODE_FLT |
df86565b | 5752 | && type->length () == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
6d82d43b | 5753 | { |
6a3a010b | 5754 | /* A double-precision floating-point value. If reading in or copying, |
dda83cd7 SM |
5755 | then we get it from/put it to FP1 and FP0 for standard MIPS code or |
5756 | GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it | |
5757 | to both FP1/FP0 and GPR2/GPR3. We do not support reading in with | |
5758 | no function known, if this safety check ever triggers, then we'll | |
5759 | have to try harder. */ | |
6a3a010b | 5760 | gdb_assert (function || !readbuf); |
6d82d43b | 5761 | if (mips_debug) |
6a3a010b MR |
5762 | switch (fval_reg) |
5763 | { | |
5764 | case mips_fval_fpr: | |
6cb06a8c | 5765 | gdb_printf (gdb_stderr, "Return float in $fp1/$fp0\n"); |
6a3a010b MR |
5766 | break; |
5767 | case mips_fval_gpr: | |
6cb06a8c | 5768 | gdb_printf (gdb_stderr, "Return float in $2/$3\n"); |
6a3a010b MR |
5769 | break; |
5770 | case mips_fval_both: | |
6cb06a8c TT |
5771 | gdb_printf (gdb_stderr, |
5772 | "Return float in $fp1/$fp0 and $2/$3\n"); | |
6a3a010b MR |
5773 | break; |
5774 | } | |
5775 | if (fval_reg != mips_fval_gpr) | |
6d82d43b | 5776 | { |
6a3a010b MR |
5777 | /* The most significant part goes in FP1, and the least significant |
5778 | in FP0. */ | |
5779 | switch (gdbarch_byte_order (gdbarch)) | |
5780 | { | |
5781 | case BFD_ENDIAN_LITTLE: | |
5782 | mips_xfer_register (gdbarch, regcache, | |
5783 | (gdbarch_num_regs (gdbarch) | |
5784 | + mips_regnum (gdbarch)->fp0 + 0), | |
5785 | 4, gdbarch_byte_order (gdbarch), | |
5786 | readbuf, writebuf, 0); | |
5787 | mips_xfer_register (gdbarch, regcache, | |
5788 | (gdbarch_num_regs (gdbarch) | |
5789 | + mips_regnum (gdbarch)->fp0 + 1), | |
5790 | 4, gdbarch_byte_order (gdbarch), | |
5791 | readbuf, writebuf, 4); | |
5792 | break; | |
5793 | case BFD_ENDIAN_BIG: | |
5794 | mips_xfer_register (gdbarch, regcache, | |
5795 | (gdbarch_num_regs (gdbarch) | |
5796 | + mips_regnum (gdbarch)->fp0 + 1), | |
5797 | 4, gdbarch_byte_order (gdbarch), | |
5798 | readbuf, writebuf, 0); | |
5799 | mips_xfer_register (gdbarch, regcache, | |
5800 | (gdbarch_num_regs (gdbarch) | |
5801 | + mips_regnum (gdbarch)->fp0 + 0), | |
5802 | 4, gdbarch_byte_order (gdbarch), | |
5803 | readbuf, writebuf, 4); | |
5804 | break; | |
5805 | default: | |
f34652de | 5806 | internal_error (_("bad switch")); |
6a3a010b MR |
5807 | } |
5808 | } | |
5809 | if (fval_reg != mips_fval_fpr) | |
5810 | { | |
5811 | /* The two 32-bit parts are always placed in GPR2 and GPR3 | |
5812 | following these registers' memory order. */ | |
ba32f989 | 5813 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5814 | gdbarch_num_regs (gdbarch) + 2, |
72a155b4 | 5815 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5816 | readbuf, writebuf, 0); |
ba32f989 | 5817 | mips_xfer_register (gdbarch, regcache, |
6a3a010b | 5818 | gdbarch_num_regs (gdbarch) + 3, |
72a155b4 | 5819 | 4, gdbarch_byte_order (gdbarch), |
4c6b5505 | 5820 | readbuf, writebuf, 4); |
6d82d43b AC |
5821 | } |
5822 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5823 | } | |
5824 | #if 0 | |
78134374 | 5825 | else if (type->code () == TYPE_CODE_STRUCT |
1f704f76 SM |
5826 | && type->num_fields () <= 2 |
5827 | && type->num_fields () >= 1 | |
5828 | && ((type->num_fields () == 1 | |
940da03e | 5829 | && (TYPE_CODE (type->field (0).type ()) |
6d82d43b | 5830 | == TYPE_CODE_FLT)) |
1f704f76 | 5831 | || (type->num_fields () == 2 |
940da03e | 5832 | && (TYPE_CODE (type->field (0).type ()) |
6d82d43b | 5833 | == TYPE_CODE_FLT) |
940da03e | 5834 | && (TYPE_CODE (type->field (1).type ()) |
6d82d43b AC |
5835 | == TYPE_CODE_FLT))) |
5836 | && tdep->mips_fpu_type != MIPS_FPU_NONE) | |
5837 | { | |
5838 | /* A struct that contains one or two floats. Each value is part | |
dda83cd7 SM |
5839 | in the least significant part of their floating point |
5840 | register.. */ | |
6d82d43b AC |
5841 | int regnum; |
5842 | int field; | |
72a155b4 | 5843 | for (field = 0, regnum = mips_regnum (gdbarch)->fp0; |
1f704f76 | 5844 | field < type->num_fields (); field++, regnum += 2) |
6d82d43b | 5845 | { |
3a543e21 | 5846 | int offset = (type->fields ()[field].loc_bitpos () / TARGET_CHAR_BIT); |
6d82d43b | 5847 | if (mips_debug) |
6cb06a8c TT |
5848 | gdb_printf (gdb_stderr, "Return float struct+%d\n", |
5849 | offset); | |
ba32f989 DJ |
5850 | mips_xfer_register (gdbarch, regcache, |
5851 | gdbarch_num_regs (gdbarch) + regnum, | |
940da03e | 5852 | TYPE_LENGTH (type->field (field).type ()), |
72a155b4 | 5853 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5854 | readbuf, writebuf, offset); |
6d82d43b AC |
5855 | } |
5856 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5857 | } | |
5858 | #endif | |
5859 | #if 0 | |
78134374 SM |
5860 | else if (type->code () == TYPE_CODE_STRUCT |
5861 | || type->code () == TYPE_CODE_UNION) | |
6d82d43b AC |
5862 | { |
5863 | /* A structure or union. Extract the left justified value, | |
dda83cd7 SM |
5864 | regardless of the byte order. I.e. DO NOT USE |
5865 | mips_xfer_lower. */ | |
6d82d43b AC |
5866 | int offset; |
5867 | int regnum; | |
4c7d22cb | 5868 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
df86565b | 5869 | offset < type->length (); |
72a155b4 | 5870 | offset += register_size (gdbarch, regnum), regnum++) |
6d82d43b | 5871 | { |
72a155b4 | 5872 | int xfer = register_size (gdbarch, regnum); |
df86565b SM |
5873 | if (offset + xfer > type->length ()) |
5874 | xfer = type->length () - offset; | |
6d82d43b | 5875 | if (mips_debug) |
6cb06a8c TT |
5876 | gdb_printf (gdb_stderr, "Return struct+%d:%d in $%d\n", |
5877 | offset, xfer, regnum); | |
ba32f989 DJ |
5878 | mips_xfer_register (gdbarch, regcache, |
5879 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
6d82d43b AC |
5880 | BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); |
5881 | } | |
5882 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5883 | } | |
5884 | #endif | |
5885 | else | |
5886 | { | |
5887 | /* A scalar extract each part but least-significant-byte | |
dda83cd7 SM |
5888 | justified. o32 thinks registers are 4 byte, regardless of |
5889 | the ISA. */ | |
6d82d43b AC |
5890 | int offset; |
5891 | int regnum; | |
4c7d22cb | 5892 | for (offset = 0, regnum = MIPS_V0_REGNUM; |
df86565b | 5893 | offset < type->length (); |
1a69e1e4 | 5894 | offset += MIPS32_REGSIZE, regnum++) |
6d82d43b | 5895 | { |
1a69e1e4 | 5896 | int xfer = MIPS32_REGSIZE; |
df86565b SM |
5897 | if (offset + xfer > type->length ()) |
5898 | xfer = type->length () - offset; | |
6d82d43b | 5899 | if (mips_debug) |
6cb06a8c TT |
5900 | gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
5901 | offset, xfer, regnum); | |
ba32f989 DJ |
5902 | mips_xfer_register (gdbarch, regcache, |
5903 | gdbarch_num_regs (gdbarch) + regnum, xfer, | |
72a155b4 | 5904 | gdbarch_byte_order (gdbarch), |
4c6b5505 | 5905 | readbuf, writebuf, offset); |
6d82d43b AC |
5906 | } |
5907 | return RETURN_VALUE_REGISTER_CONVENTION; | |
5908 | } | |
5909 | } | |
5910 | ||
5911 | /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 | |
5912 | ABI. */ | |
46cac009 AC |
5913 | |
5914 | static CORE_ADDR | |
7d9b040b | 5915 | mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
6d82d43b AC |
5916 | struct regcache *regcache, CORE_ADDR bp_addr, |
5917 | int nargs, | |
5918 | struct value **args, CORE_ADDR sp, | |
cf84fa6b | 5919 | function_call_return_method return_method, CORE_ADDR struct_addr) |
46cac009 AC |
5920 | { |
5921 | int argreg; | |
5922 | int float_argreg; | |
5923 | int argnum; | |
b926417a | 5924 | int arg_space = 0; |
46cac009 | 5925 | int stack_offset = 0; |
e17a4113 | 5926 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7d9b040b | 5927 | CORE_ADDR func_addr = find_function_addr (function, NULL); |
46cac009 | 5928 | |
25ab4790 AC |
5929 | /* For shared libraries, "t9" needs to point at the function |
5930 | address. */ | |
4c7d22cb | 5931 | regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
25ab4790 AC |
5932 | |
5933 | /* Set the return address register to point to the entry point of | |
5934 | the program, where a breakpoint lies in wait. */ | |
4c7d22cb | 5935 | regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
25ab4790 | 5936 | |
46cac009 AC |
5937 | /* First ensure that the stack and structure return address (if any) |
5938 | are properly aligned. The stack has to be at least 64-bit | |
5939 | aligned even on 32-bit machines, because doubles must be 64-bit | |
5940 | aligned. For n32 and n64, stack frames need to be 128-bit | |
5941 | aligned, so we round to this widest known alignment. */ | |
5942 | ||
5b03f266 AC |
5943 | sp = align_down (sp, 16); |
5944 | struct_addr = align_down (struct_addr, 16); | |
46cac009 AC |
5945 | |
5946 | /* Now make space on the stack for the args. */ | |
5947 | for (argnum = 0; argnum < nargs; argnum++) | |
968b5391 | 5948 | { |
d0c97917 | 5949 | struct type *arg_type = check_typedef (args[argnum]->type ()); |
968b5391 | 5950 | |
968b5391 | 5951 | /* Allocate space on the stack. */ |
df86565b | 5952 | arg_space += align_up (arg_type->length (), MIPS64_REGSIZE); |
968b5391 | 5953 | } |
b926417a | 5954 | sp -= align_up (arg_space, 16); |
46cac009 AC |
5955 | |
5956 | if (mips_debug) | |
6cb06a8c TT |
5957 | gdb_printf (gdb_stdlog, |
5958 | "mips_o64_push_dummy_call: sp=%s allocated %ld\n", | |
5959 | paddress (gdbarch, sp), | |
5960 | (long) align_up (arg_space, 16)); | |
46cac009 AC |
5961 | |
5962 | /* Initialize the integer and float register pointers. */ | |
4c7d22cb | 5963 | argreg = MIPS_A0_REGNUM; |
72a155b4 | 5964 | float_argreg = mips_fpa0_regnum (gdbarch); |
46cac009 AC |
5965 | |
5966 | /* The struct_return pointer occupies the first parameter-passing reg. */ | |
cf84fa6b | 5967 | if (return_method == return_method_struct) |
46cac009 AC |
5968 | { |
5969 | if (mips_debug) | |
6cb06a8c TT |
5970 | gdb_printf (gdb_stdlog, |
5971 | "mips_o64_push_dummy_call: " | |
5972 | "struct_return reg=%d %s\n", | |
5973 | argreg, paddress (gdbarch, struct_addr)); | |
9c9acae0 | 5974 | regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); |
1a69e1e4 | 5975 | stack_offset += MIPS64_REGSIZE; |
46cac009 AC |
5976 | } |
5977 | ||
5978 | /* Now load as many as possible of the first arguments into | |
5979 | registers, and push the rest onto the stack. Loop thru args | |
5980 | from first to last. */ | |
5981 | for (argnum = 0; argnum < nargs; argnum++) | |
5982 | { | |
47a35522 | 5983 | const gdb_byte *val; |
46cac009 | 5984 | struct value *arg = args[argnum]; |
d0c97917 | 5985 | struct type *arg_type = check_typedef (arg->type ()); |
df86565b | 5986 | int len = arg_type->length (); |
78134374 | 5987 | enum type_code typecode = arg_type->code (); |
46cac009 AC |
5988 | |
5989 | if (mips_debug) | |
6cb06a8c TT |
5990 | gdb_printf (gdb_stdlog, |
5991 | "mips_o64_push_dummy_call: %d len=%d type=%d", | |
5992 | argnum + 1, len, (int) typecode); | |
ebafbe83 | 5993 | |
efaf1ae0 | 5994 | val = arg->contents ().data (); |
ebafbe83 | 5995 | |
ebafbe83 | 5996 | /* Floating point arguments passed in registers have to be |
dda83cd7 SM |
5997 | treated specially. On 32-bit architectures, doubles are |
5998 | passed in register pairs; the even FP register gets the | |
5999 | low word, and the odd FP register gets the high word. | |
6000 | On O64, the first two floating point arguments are also | |
6001 | copied to general registers, because MIPS16 functions | |
6002 | don't use float registers for arguments. This duplication | |
6003 | of arguments in general registers can't hurt non-MIPS16 | |
6004 | functions because those registers are normally skipped. */ | |
ebafbe83 | 6005 | |
74ed0bb4 | 6006 | if (fp_register_arg_p (gdbarch, typecode, arg_type) |
345bd07c | 6007 | && float_argreg <= mips_last_fp_arg_regnum (gdbarch)) |
ebafbe83 | 6008 | { |
e17a4113 | 6009 | LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
2afd3f0a | 6010 | if (mips_debug) |
6cb06a8c TT |
6011 | gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", |
6012 | float_argreg, phex (regval, len)); | |
9c9acae0 | 6013 | regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
2afd3f0a | 6014 | if (mips_debug) |
6cb06a8c TT |
6015 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
6016 | argreg, phex (regval, len)); | |
9c9acae0 | 6017 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
2afd3f0a | 6018 | argreg++; |
ebafbe83 | 6019 | /* Reserve space for the FP register. */ |
1a69e1e4 | 6020 | stack_offset += align_up (len, MIPS64_REGSIZE); |
ebafbe83 MS |
6021 | } |
6022 | else | |
6023 | { | |
6024 | /* Copy the argument to general registers or the stack in | |
6025 | register-sized pieces. Large arguments are split between | |
6026 | registers and stack. */ | |
1a69e1e4 | 6027 | /* Note: structs whose size is not a multiple of MIPS64_REGSIZE |
436aafc4 MR |
6028 | are treated specially: Irix cc passes them in registers |
6029 | where gcc sometimes puts them on the stack. For maximum | |
6030 | compatibility, we will put them in both places. */ | |
1a69e1e4 DJ |
6031 | int odd_sized_struct = (len > MIPS64_REGSIZE |
6032 | && len % MIPS64_REGSIZE != 0); | |
ebafbe83 MS |
6033 | while (len > 0) |
6034 | { | |
1a69e1e4 | 6035 | int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); |
ebafbe83 MS |
6036 | |
6037 | if (mips_debug) | |
6cb06a8c TT |
6038 | gdb_printf (gdb_stdlog, " -- partial=%d", |
6039 | partial_len); | |
ebafbe83 MS |
6040 | |
6041 | /* Write this portion of the argument to the stack. */ | |
345bd07c | 6042 | if (argreg > mips_last_arg_regnum (gdbarch) |
968b5391 | 6043 | || odd_sized_struct) |
ebafbe83 MS |
6044 | { |
6045 | /* Should shorter than int integer values be | |
025bb325 | 6046 | promoted to int before being stored? */ |
ebafbe83 MS |
6047 | int longword_offset = 0; |
6048 | CORE_ADDR addr; | |
72a155b4 | 6049 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
ebafbe83 | 6050 | { |
1a69e1e4 DJ |
6051 | if ((typecode == TYPE_CODE_INT |
6052 | || typecode == TYPE_CODE_PTR | |
6053 | || typecode == TYPE_CODE_FLT) | |
6054 | && len <= 4) | |
6055 | longword_offset = MIPS64_REGSIZE - len; | |
ebafbe83 MS |
6056 | } |
6057 | ||
6058 | if (mips_debug) | |
6059 | { | |
6cb06a8c TT |
6060 | gdb_printf (gdb_stdlog, " - stack_offset=%s", |
6061 | paddress (gdbarch, stack_offset)); | |
6062 | gdb_printf (gdb_stdlog, " longword_offset=%s", | |
6063 | paddress (gdbarch, longword_offset)); | |
ebafbe83 MS |
6064 | } |
6065 | ||
6066 | addr = sp + stack_offset + longword_offset; | |
6067 | ||
6068 | if (mips_debug) | |
6069 | { | |
6070 | int i; | |
6cb06a8c TT |
6071 | gdb_printf (gdb_stdlog, " @%s ", |
6072 | paddress (gdbarch, addr)); | |
ebafbe83 MS |
6073 | for (i = 0; i < partial_len; i++) |
6074 | { | |
6cb06a8c TT |
6075 | gdb_printf (gdb_stdlog, "%02x", |
6076 | val[i] & 0xff); | |
ebafbe83 MS |
6077 | } |
6078 | } | |
6079 | write_memory (addr, val, partial_len); | |
6080 | } | |
6081 | ||
6082 | /* Note!!! This is NOT an else clause. Odd sized | |
dda83cd7 | 6083 | structs may go thru BOTH paths. */ |
ebafbe83 | 6084 | /* Write this portion of the argument to a general |
dda83cd7 | 6085 | purpose register. */ |
345bd07c | 6086 | if (argreg <= mips_last_arg_regnum (gdbarch)) |
ebafbe83 | 6087 | { |
e17a4113 UW |
6088 | LONGEST regval = extract_signed_integer (val, partial_len, |
6089 | byte_order); | |
4246e332 | 6090 | /* Value may need to be sign extended, because |
1b13c4f6 | 6091 | mips_isa_regsize() != mips_abi_regsize(). */ |
ebafbe83 MS |
6092 | |
6093 | /* A non-floating-point argument being passed in a | |
6094 | general register. If a struct or union, and if | |
6095 | the remaining length is smaller than the register | |
6096 | size, we have to adjust the register value on | |
6097 | big endian targets. | |
6098 | ||
6099 | It does not seem to be necessary to do the | |
025bb325 | 6100 | same for integral types. */ |
480d3dd2 | 6101 | |
72a155b4 | 6102 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
1a69e1e4 | 6103 | && partial_len < MIPS64_REGSIZE |
06f9a1af MR |
6104 | && (typecode == TYPE_CODE_STRUCT |
6105 | || typecode == TYPE_CODE_UNION)) | |
1a69e1e4 | 6106 | regval <<= ((MIPS64_REGSIZE - partial_len) |
9ecf7166 | 6107 | * TARGET_CHAR_BIT); |
ebafbe83 MS |
6108 | |
6109 | if (mips_debug) | |
6cb06a8c TT |
6110 | gdb_printf (gdb_stdlog, " - reg=%d val=%s", |
6111 | argreg, | |
6112 | phex (regval, MIPS64_REGSIZE)); | |
9c9acae0 | 6113 | regcache_cooked_write_unsigned (regcache, argreg, regval); |
ebafbe83 MS |
6114 | argreg++; |
6115 | ||
6116 | /* Prevent subsequent floating point arguments from | |
6117 | being passed in floating point registers. */ | |
345bd07c | 6118 | float_argreg = mips_last_fp_arg_regnum (gdbarch) + 1; |
ebafbe83 MS |
6119 | } |
6120 | ||
6121 | len -= partial_len; | |
6122 | val += partial_len; | |
6123 | ||
b021a221 | 6124 | /* Compute the offset into the stack at which we will |
dda83cd7 | 6125 | copy the next parameter. |
ebafbe83 | 6126 | |
dda83cd7 SM |
6127 | In older ABIs, the caller reserved space for |
6128 | registers that contained arguments. This was loosely | |
33b5899f | 6129 | referred to as their "home". Consequently, space is |
dda83cd7 | 6130 | always allocated. */ |
ebafbe83 | 6131 | |
1a69e1e4 | 6132 | stack_offset += align_up (partial_len, MIPS64_REGSIZE); |
ebafbe83 MS |
6133 | } |
6134 | } | |
6135 | if (mips_debug) | |
6cb06a8c | 6136 | gdb_printf (gdb_stdlog, "\n"); |
ebafbe83 MS |
6137 | } |
6138 | ||
f10683bb | 6139 | regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
310e9b6a | 6140 | |
ebafbe83 MS |
6141 | /* Return adjusted stack pointer. */ |
6142 | return sp; | |
6143 | } | |
6144 | ||
9c8fdbfa | 6145 | static enum return_value_convention |
6a3a010b | 6146 | mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
9c8fdbfa | 6147 | struct type *type, struct regcache *regcache, |
47a35522 | 6148 | gdb_byte *readbuf, const gdb_byte *writebuf) |
6d82d43b | 6149 | { |
6a3a010b | 6150 | CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
4cc0665f | 6151 | int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
6a3a010b | 6152 | enum mips_fval_reg fval_reg; |
7a076fd2 | 6153 | |
6a3a010b | 6154 | fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
78134374 SM |
6155 | if (type->code () == TYPE_CODE_STRUCT |
6156 | || type->code () == TYPE_CODE_UNION | |
6157 | || type->code () == TYPE_CODE_ARRAY) | |
7a076fd2 | 6158 | return RETURN_VALUE_STRUCT_CONVENTION; |
78134374 | 6159 | else if (fp_register_arg_p (gdbarch, type->code (), type)) |
7a076fd2 | 6160 | { |
6a3a010b | 6161 | /* A floating-point value. If reading in or copying, then we get it |
dda83cd7 SM |
6162 | from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. |
6163 | If writing out only, then we put it to both FP0 and GPR2. We do | |
6164 | not support reading in with no function known, if this safety | |
6165 | check ever triggers, then we'll have to try harder. */ | |
6a3a010b | 6166 | gdb_assert (function || !readbuf); |
7a076fd2 | 6167 | if (mips_debug) |
6a3a010b MR |
6168 | switch (fval_reg) |
6169 | { | |
6170 | case mips_fval_fpr: | |
6cb06a8c | 6171 | gdb_printf (gdb_stderr, "Return float in $fp0\n"); |
6a3a010b MR |
6172 | break; |
6173 | case mips_fval_gpr: | |
6cb06a8c | 6174 | gdb_printf (gdb_stderr, "Return float in $2\n"); |
6a3a010b MR |
6175 | break; |
6176 | case mips_fval_both: | |
6cb06a8c | 6177 | gdb_printf (gdb_stderr, "Return float in $fp0 and $2\n"); |
6a3a010b MR |
6178 | break; |
6179 | } | |
6180 | if (fval_reg != mips_fval_gpr) | |
6181 | mips_xfer_register (gdbarch, regcache, | |
6182 | (gdbarch_num_regs (gdbarch) | |
6183 | + mips_regnum (gdbarch)->fp0), | |
df86565b | 6184 | type->length (), |
6a3a010b MR |
6185 | gdbarch_byte_order (gdbarch), |
6186 | readbuf, writebuf, 0); | |
6187 | if (fval_reg != mips_fval_fpr) | |
6188 | mips_xfer_register (gdbarch, regcache, | |
6189 | gdbarch_num_regs (gdbarch) + 2, | |
df86565b | 6190 | type->length (), |
6a3a010b MR |
6191 | gdbarch_byte_order (gdbarch), |
6192 | readbuf, writebuf, 0); | |
7a076fd2 FF |
6193 | return RETURN_VALUE_REGISTER_CONVENTION; |
6194 | } | |
6195 | else | |
6196 | { | |
6197 | /* A scalar extract each part but least-significant-byte | |
dda83cd7 | 6198 | justified. */ |
7a076fd2 FF |
6199 | int offset; |
6200 | int regnum; | |
6201 | for (offset = 0, regnum = MIPS_V0_REGNUM; | |
df86565b | 6202 | offset < type->length (); |
1a69e1e4 | 6203 | offset += MIPS64_REGSIZE, regnum++) |
7a076fd2 | 6204 | { |
1a69e1e4 | 6205 | int xfer = MIPS64_REGSIZE; |
df86565b SM |
6206 | if (offset + xfer > type->length ()) |
6207 | xfer = type->length () - offset; | |
7a076fd2 | 6208 | if (mips_debug) |
6cb06a8c TT |
6209 | gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", |
6210 | offset, xfer, regnum); | |
ba32f989 DJ |
6211 | mips_xfer_register (gdbarch, regcache, |
6212 | gdbarch_num_regs (gdbarch) + regnum, | |
72a155b4 | 6213 | xfer, gdbarch_byte_order (gdbarch), |
4c6b5505 | 6214 | readbuf, writebuf, offset); |
7a076fd2 FF |
6215 | } |
6216 | return RETURN_VALUE_REGISTER_CONVENTION; | |
6217 | } | |
6d82d43b AC |
6218 | } |
6219 | ||
dd824b04 DJ |
6220 | /* Floating point register management. |
6221 | ||
6222 | Background: MIPS1 & 2 fp registers are 32 bits wide. To support | |
6223 | 64bit operations, these early MIPS cpus treat fp register pairs | |
6224 | (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp | |
6225 | registers and offer a compatibility mode that emulates the MIPS2 fp | |
6226 | model. When operating in MIPS2 fp compat mode, later cpu's split | |
6227 | double precision floats into two 32-bit chunks and store them in | |
6228 | consecutive fp regs. To display 64-bit floats stored in this | |
6229 | fashion, we have to combine 32 bits from f0 and 32 bits from f1. | |
6230 | Throw in user-configurable endianness and you have a real mess. | |
6231 | ||
6232 | The way this works is: | |
6233 | - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit | |
6234 | double-precision value will be split across two logical registers. | |
6235 | The lower-numbered logical register will hold the low-order bits, | |
6236 | regardless of the processor's endianness. | |
6237 | - If we are on a 64-bit processor, and we are looking for a | |
6238 | single-precision value, it will be in the low ordered bits | |
6239 | of a 64-bit GPR (after mfc1, for example) or a 64-bit register | |
6240 | save slot in memory. | |
6241 | - If we are in 64-bit mode, everything is straightforward. | |
6242 | ||
6243 | Note that this code only deals with "live" registers at the top of the | |
6244 | stack. We will attempt to deal with saved registers later, when | |
025bb325 | 6245 | the raw/cooked register interface is in place. (We need a general |
dd824b04 DJ |
6246 | interface that can deal with dynamic saved register sizes -- fp |
6247 | regs could be 32 bits wide in one frame and 64 on the frame above | |
6248 | and below). */ | |
6249 | ||
6250 | /* Copy a 32-bit single-precision value from the current frame | |
6251 | into rare_buffer. */ | |
6252 | ||
6253 | static void | |
bd2b40ac | 6254 | mips_read_fp_register_single (frame_info_ptr frame, int regno, |
47a35522 | 6255 | gdb_byte *rare_buffer) |
dd824b04 | 6256 | { |
72a155b4 UW |
6257 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6258 | int raw_size = register_size (gdbarch, regno); | |
224c3ddb | 6259 | gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size); |
dd824b04 | 6260 | |
ca9d61b9 | 6261 | if (!deprecated_frame_register_read (frame, regno, raw_buffer)) |
c9f4d572 | 6262 | error (_("can't read register %d (%s)"), |
72a155b4 | 6263 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6264 | if (raw_size == 8) |
6265 | { | |
6266 | /* We have a 64-bit value for this register. Find the low-order | |
dda83cd7 | 6267 | 32 bits. */ |
dd824b04 DJ |
6268 | int offset; |
6269 | ||
72a155b4 | 6270 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 DJ |
6271 | offset = 4; |
6272 | else | |
6273 | offset = 0; | |
6274 | ||
6275 | memcpy (rare_buffer, raw_buffer + offset, 4); | |
6276 | } | |
6277 | else | |
6278 | { | |
6279 | memcpy (rare_buffer, raw_buffer, 4); | |
6280 | } | |
6281 | } | |
6282 | ||
6283 | /* Copy a 64-bit double-precision value from the current frame into | |
6284 | rare_buffer. This may include getting half of it from the next | |
6285 | register. */ | |
6286 | ||
6287 | static void | |
bd2b40ac | 6288 | mips_read_fp_register_double (frame_info_ptr frame, int regno, |
47a35522 | 6289 | gdb_byte *rare_buffer) |
dd824b04 | 6290 | { |
72a155b4 UW |
6291 | struct gdbarch *gdbarch = get_frame_arch (frame); |
6292 | int raw_size = register_size (gdbarch, regno); | |
dd824b04 | 6293 | |
9c9acae0 | 6294 | if (raw_size == 8 && !mips2_fp_compat (frame)) |
dd824b04 DJ |
6295 | { |
6296 | /* We have a 64-bit value for this register, and we should use | |
dda83cd7 | 6297 | all 64 bits. */ |
ca9d61b9 | 6298 | if (!deprecated_frame_register_read (frame, regno, rare_buffer)) |
c9f4d572 | 6299 | error (_("can't read register %d (%s)"), |
72a155b4 | 6300 | regno, gdbarch_register_name (gdbarch, regno)); |
dd824b04 DJ |
6301 | } |
6302 | else | |
6303 | { | |
72a155b4 | 6304 | int rawnum = regno % gdbarch_num_regs (gdbarch); |
82e91389 | 6305 | |
72a155b4 | 6306 | if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) |
f34652de | 6307 | internal_error (_("mips_read_fp_register_double: bad access to " |
e2e0b3e5 | 6308 | "odd-numbered FP register")); |
dd824b04 DJ |
6309 | |
6310 | /* mips_read_fp_register_single will find the correct 32 bits from | |
dda83cd7 | 6311 | each register. */ |
72a155b4 | 6312 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
dd824b04 | 6313 | { |
e11c53d2 AC |
6314 | mips_read_fp_register_single (frame, regno, rare_buffer + 4); |
6315 | mips_read_fp_register_single (frame, regno + 1, rare_buffer); | |
dd824b04 | 6316 | } |
361d1df0 | 6317 | else |
dd824b04 | 6318 | { |
e11c53d2 AC |
6319 | mips_read_fp_register_single (frame, regno, rare_buffer); |
6320 | mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); | |
dd824b04 DJ |
6321 | } |
6322 | } | |
6323 | } | |
6324 | ||
c906108c | 6325 | static void |
bd2b40ac | 6326 | mips_print_fp_register (struct ui_file *file, frame_info_ptr frame, |
e11c53d2 | 6327 | int regnum) |
025bb325 | 6328 | { /* Do values for FP (float) regs. */ |
72a155b4 | 6329 | struct gdbarch *gdbarch = get_frame_arch (frame); |
47a35522 | 6330 | gdb_byte *raw_buffer; |
8ba0dd51 UW |
6331 | std::string flt_str, dbl_str; |
6332 | ||
f69fdf9b UW |
6333 | const struct type *flt_type = builtin_type (gdbarch)->builtin_float; |
6334 | const struct type *dbl_type = builtin_type (gdbarch)->builtin_double; | |
c5aa993b | 6335 | |
224c3ddb SM |
6336 | raw_buffer |
6337 | = ((gdb_byte *) | |
6338 | alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); | |
c906108c | 6339 | |
6cb06a8c TT |
6340 | gdb_printf (file, "%s:", gdbarch_register_name (gdbarch, regnum)); |
6341 | gdb_printf (file, "%*s", | |
6342 | 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), | |
6343 | ""); | |
f0ef6b29 | 6344 | |
72a155b4 | 6345 | if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) |
c906108c | 6346 | { |
79a45b7d TT |
6347 | struct value_print_options opts; |
6348 | ||
f0ef6b29 | 6349 | /* 4-byte registers: Print hex and floating. Also print even |
dda83cd7 | 6350 | numbered registers as doubles. */ |
e11c53d2 | 6351 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
f69fdf9b | 6352 | flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); |
c5aa993b | 6353 | |
79a45b7d | 6354 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6355 | print_scalar_formatted (raw_buffer, |
6356 | builtin_type (gdbarch)->builtin_uint32, | |
6357 | &opts, 'w', file); | |
dd824b04 | 6358 | |
6cb06a8c | 6359 | gdb_printf (file, " flt: %s", flt_str.c_str ()); |
1adad886 | 6360 | |
72a155b4 | 6361 | if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) |
f0ef6b29 | 6362 | { |
e11c53d2 | 6363 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f69fdf9b | 6364 | dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); |
1adad886 | 6365 | |
6cb06a8c | 6366 | gdb_printf (file, " dbl: %s", dbl_str.c_str ()); |
f0ef6b29 | 6367 | } |
c906108c SS |
6368 | } |
6369 | else | |
dd824b04 | 6370 | { |
79a45b7d TT |
6371 | struct value_print_options opts; |
6372 | ||
f0ef6b29 | 6373 | /* Eight byte registers: print each one as hex, float and double. */ |
e11c53d2 | 6374 | mips_read_fp_register_single (frame, regnum, raw_buffer); |
f69fdf9b | 6375 | flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); |
c906108c | 6376 | |
e11c53d2 | 6377 | mips_read_fp_register_double (frame, regnum, raw_buffer); |
f69fdf9b | 6378 | dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); |
f0ef6b29 | 6379 | |
79a45b7d | 6380 | get_formatted_print_options (&opts, 'x'); |
df4df182 UW |
6381 | print_scalar_formatted (raw_buffer, |
6382 | builtin_type (gdbarch)->builtin_uint64, | |
6383 | &opts, 'g', file); | |
f0ef6b29 | 6384 | |
6cb06a8c TT |
6385 | gdb_printf (file, " flt: %s", flt_str.c_str ()); |
6386 | gdb_printf (file, " dbl: %s", dbl_str.c_str ()); | |
f0ef6b29 KB |
6387 | } |
6388 | } | |
6389 | ||
6390 | static void | |
bd2b40ac | 6391 | mips_print_register (struct ui_file *file, frame_info_ptr frame, |
0cc93a06 | 6392 | int regnum) |
f0ef6b29 | 6393 | { |
a4b8ebc8 | 6394 | struct gdbarch *gdbarch = get_frame_arch (frame); |
79a45b7d | 6395 | struct value_print_options opts; |
de15c4ab | 6396 | struct value *val; |
1adad886 | 6397 | |
004159a2 | 6398 | if (mips_float_register_p (gdbarch, regnum)) |
f0ef6b29 | 6399 | { |
e11c53d2 | 6400 | mips_print_fp_register (file, frame, regnum); |
f0ef6b29 KB |
6401 | return; |
6402 | } | |
6403 | ||
de15c4ab | 6404 | val = get_frame_register_value (frame, regnum); |
f0ef6b29 | 6405 | |
0426ad51 | 6406 | gdb_puts (gdbarch_register_name (gdbarch, regnum), file); |
f0ef6b29 KB |
6407 | |
6408 | /* The problem with printing numeric register names (r26, etc.) is that | |
6409 | the user can't use them on input. Probably the best solution is to | |
6410 | fix it so that either the numeric or the funky (a2, etc.) names | |
6411 | are accepted on input. */ | |
6412 | if (regnum < MIPS_NUMREGS) | |
6cb06a8c | 6413 | gdb_printf (file, "(r%d): ", regnum); |
f0ef6b29 | 6414 | else |
6cb06a8c | 6415 | gdb_printf (file, ": "); |
f0ef6b29 | 6416 | |
79a45b7d | 6417 | get_formatted_print_options (&opts, 'x'); |
4dba70ee | 6418 | value_print_scalar_formatted (val, &opts, 0, file); |
c906108c SS |
6419 | } |
6420 | ||
1bab7383 YQ |
6421 | /* Print IEEE exception condition bits in FLAGS. */ |
6422 | ||
6423 | static void | |
6424 | print_fpu_flags (struct ui_file *file, int flags) | |
6425 | { | |
6426 | if (flags & (1 << 0)) | |
0426ad51 | 6427 | gdb_puts (" inexact", file); |
1bab7383 | 6428 | if (flags & (1 << 1)) |
0426ad51 | 6429 | gdb_puts (" uflow", file); |
1bab7383 | 6430 | if (flags & (1 << 2)) |
0426ad51 | 6431 | gdb_puts (" oflow", file); |
1bab7383 | 6432 | if (flags & (1 << 3)) |
0426ad51 | 6433 | gdb_puts (" div0", file); |
1bab7383 | 6434 | if (flags & (1 << 4)) |
0426ad51 | 6435 | gdb_puts (" inval", file); |
1bab7383 | 6436 | if (flags & (1 << 5)) |
0426ad51 | 6437 | gdb_puts (" unimp", file); |
a11ac3b3 | 6438 | gdb_putc ('\n', file); |
1bab7383 YQ |
6439 | } |
6440 | ||
6441 | /* Print interesting information about the floating point processor | |
6442 | (if present) or emulator. */ | |
6443 | ||
6444 | static void | |
6445 | mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, | |
bd2b40ac | 6446 | frame_info_ptr frame, const char *args) |
1bab7383 YQ |
6447 | { |
6448 | int fcsr = mips_regnum (gdbarch)->fp_control_status; | |
345bd07c | 6449 | enum mips_fpu_type type = mips_get_fpu_type (gdbarch); |
1bab7383 YQ |
6450 | ULONGEST fcs = 0; |
6451 | int i; | |
6452 | ||
6453 | if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs)) | |
6454 | type = MIPS_FPU_NONE; | |
6455 | ||
6cb06a8c TT |
6456 | gdb_printf (file, "fpu type: %s\n", |
6457 | type == MIPS_FPU_DOUBLE ? "double-precision" | |
6458 | : type == MIPS_FPU_SINGLE ? "single-precision" | |
6459 | : "none / unused"); | |
1bab7383 YQ |
6460 | |
6461 | if (type == MIPS_FPU_NONE) | |
6462 | return; | |
6463 | ||
6cb06a8c TT |
6464 | gdb_printf (file, "reg size: %d bits\n", |
6465 | register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8); | |
1bab7383 | 6466 | |
0426ad51 | 6467 | gdb_puts ("cond :", file); |
1bab7383 | 6468 | if (fcs & (1 << 23)) |
0426ad51 | 6469 | gdb_puts (" 0", file); |
1bab7383 YQ |
6470 | for (i = 1; i <= 7; i++) |
6471 | if (fcs & (1 << (24 + i))) | |
6cb06a8c | 6472 | gdb_printf (file, " %d", i); |
a11ac3b3 | 6473 | gdb_putc ('\n', file); |
1bab7383 | 6474 | |
0426ad51 | 6475 | gdb_puts ("cause :", file); |
1bab7383 YQ |
6476 | print_fpu_flags (file, (fcs >> 12) & 0x3f); |
6477 | fputs ("mask :", stdout); | |
6478 | print_fpu_flags (file, (fcs >> 7) & 0x1f); | |
6479 | fputs ("flags :", stdout); | |
6480 | print_fpu_flags (file, (fcs >> 2) & 0x1f); | |
6481 | ||
0426ad51 | 6482 | gdb_puts ("rounding: ", file); |
1bab7383 YQ |
6483 | switch (fcs & 3) |
6484 | { | |
0426ad51 TT |
6485 | case 0: gdb_puts ("nearest\n", file); break; |
6486 | case 1: gdb_puts ("zero\n", file); break; | |
6487 | case 2: gdb_puts ("+inf\n", file); break; | |
6488 | case 3: gdb_puts ("-inf\n", file); break; | |
1bab7383 YQ |
6489 | } |
6490 | ||
0426ad51 | 6491 | gdb_puts ("flush :", file); |
1bab7383 | 6492 | if (fcs & (1 << 21)) |
0426ad51 | 6493 | gdb_puts (" nearest", file); |
1bab7383 | 6494 | if (fcs & (1 << 22)) |
0426ad51 | 6495 | gdb_puts (" override", file); |
1bab7383 | 6496 | if (fcs & (1 << 24)) |
0426ad51 | 6497 | gdb_puts (" zero", file); |
1bab7383 | 6498 | if ((fcs & (0xb << 21)) == 0) |
0426ad51 | 6499 | gdb_puts (" no", file); |
a11ac3b3 | 6500 | gdb_putc ('\n', file); |
1bab7383 | 6501 | |
6cb06a8c TT |
6502 | gdb_printf (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no"); |
6503 | gdb_printf (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no"); | |
a11ac3b3 | 6504 | gdb_putc ('\n', file); |
1bab7383 YQ |
6505 | |
6506 | default_print_float_info (gdbarch, file, frame, args); | |
6507 | } | |
6508 | ||
f0ef6b29 KB |
6509 | /* Replacement for generic do_registers_info. |
6510 | Print regs in pretty columns. */ | |
6511 | ||
6512 | static int | |
bd2b40ac | 6513 | print_fp_register_row (struct ui_file *file, frame_info_ptr frame, |
e11c53d2 | 6514 | int regnum) |
f0ef6b29 | 6515 | { |
6cb06a8c | 6516 | gdb_printf (file, " "); |
e11c53d2 | 6517 | mips_print_fp_register (file, frame, regnum); |
6cb06a8c | 6518 | gdb_printf (file, "\n"); |
f0ef6b29 KB |
6519 | return regnum + 1; |
6520 | } | |
6521 | ||
6522 | ||
025bb325 | 6523 | /* Print a row's worth of GP (int) registers, with name labels above. */ |
c906108c SS |
6524 | |
6525 | static int | |
bd2b40ac | 6526 | print_gp_register_row (struct ui_file *file, frame_info_ptr frame, |
a4b8ebc8 | 6527 | int start_regnum) |
c906108c | 6528 | { |
a4b8ebc8 | 6529 | struct gdbarch *gdbarch = get_frame_arch (frame); |
025bb325 | 6530 | /* Do values for GP (int) regs. */ |
313c5961 AH |
6531 | const gdb_byte *raw_buffer; |
6532 | struct value *value; | |
025bb325 MS |
6533 | int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols |
6534 | per row. */ | |
c906108c | 6535 | int col, byte; |
a4b8ebc8 | 6536 | int regnum; |
c906108c | 6537 | |
025bb325 | 6538 | /* For GP registers, we print a separate row of names above the vals. */ |
a4b8ebc8 | 6539 | for (col = 0, regnum = start_regnum; |
f6efe3f8 | 6540 | col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); |
f57d151a | 6541 | regnum++) |
c906108c | 6542 | { |
72a155b4 | 6543 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6544 | continue; /* unused register */ |
004159a2 | 6545 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6546 | break; /* End the row: reached FP register. */ |
0cc93a06 | 6547 | /* Large registers are handled separately. */ |
72a155b4 | 6548 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6549 | { |
6550 | if (col > 0) | |
6551 | break; /* End the row before this register. */ | |
6552 | ||
6553 | /* Print this register on a row by itself. */ | |
6554 | mips_print_register (file, frame, regnum); | |
6cb06a8c | 6555 | gdb_printf (file, "\n"); |
0cc93a06 DJ |
6556 | return regnum + 1; |
6557 | } | |
d05f6826 | 6558 | if (col == 0) |
6cb06a8c TT |
6559 | gdb_printf (file, " "); |
6560 | gdb_printf (file, | |
6561 | mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", | |
6562 | gdbarch_register_name (gdbarch, regnum)); | |
c906108c SS |
6563 | col++; |
6564 | } | |
d05f6826 DJ |
6565 | |
6566 | if (col == 0) | |
6567 | return regnum; | |
6568 | ||
025bb325 | 6569 | /* Print the R0 to R31 names. */ |
72a155b4 | 6570 | if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) |
6cb06a8c TT |
6571 | gdb_printf (file, "\n R%-4d", |
6572 | start_regnum % gdbarch_num_regs (gdbarch)); | |
20e6603c | 6573 | else |
6cb06a8c | 6574 | gdb_printf (file, "\n "); |
c906108c | 6575 | |
025bb325 | 6576 | /* Now print the values in hex, 4 or 8 to the row. */ |
a4b8ebc8 | 6577 | for (col = 0, regnum = start_regnum; |
f6efe3f8 | 6578 | col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); |
f57d151a | 6579 | regnum++) |
c906108c | 6580 | { |
72a155b4 | 6581 | if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
c5aa993b | 6582 | continue; /* unused register */ |
004159a2 | 6583 | if (mips_float_register_p (gdbarch, regnum)) |
025bb325 | 6584 | break; /* End row: reached FP register. */ |
72a155b4 | 6585 | if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
0cc93a06 DJ |
6586 | break; /* End row: large register. */ |
6587 | ||
c906108c | 6588 | /* OK: get the data in raw format. */ |
313c5961 | 6589 | value = get_frame_register_value (frame, regnum); |
d00664db TT |
6590 | if (value->optimized_out () |
6591 | || !value->entirely_available ()) | |
325c9fd4 | 6592 | { |
6cb06a8c TT |
6593 | gdb_printf (file, "%*s ", |
6594 | (int) mips_abi_regsize (gdbarch) * 2, | |
6595 | (mips_abi_regsize (gdbarch) == 4 ? "<unavl>" | |
6596 | : "<unavailable>")); | |
325c9fd4 JB |
6597 | col++; |
6598 | continue; | |
6599 | } | |
efaf1ae0 | 6600 | raw_buffer = value->contents_all ().data (); |
c906108c | 6601 | /* pad small registers */ |
4246e332 | 6602 | for (byte = 0; |
72a155b4 UW |
6603 | byte < (mips_abi_regsize (gdbarch) |
6604 | - register_size (gdbarch, regnum)); byte++) | |
6cb06a8c | 6605 | gdb_printf (file, " "); |
025bb325 | 6606 | /* Now print the register value in hex, endian order. */ |
72a155b4 | 6607 | if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
6d82d43b | 6608 | for (byte = |
72a155b4 UW |
6609 | register_size (gdbarch, regnum) - register_size (gdbarch, regnum); |
6610 | byte < register_size (gdbarch, regnum); byte++) | |
6cb06a8c | 6611 | gdb_printf (file, "%02x", raw_buffer[byte]); |
c906108c | 6612 | else |
72a155b4 | 6613 | for (byte = register_size (gdbarch, regnum) - 1; |
6d82d43b | 6614 | byte >= 0; byte--) |
6cb06a8c TT |
6615 | gdb_printf (file, "%02x", raw_buffer[byte]); |
6616 | gdb_printf (file, " "); | |
c906108c SS |
6617 | col++; |
6618 | } | |
025bb325 | 6619 | if (col > 0) /* ie. if we actually printed anything... */ |
6cb06a8c | 6620 | gdb_printf (file, "\n"); |
c906108c SS |
6621 | |
6622 | return regnum; | |
6623 | } | |
6624 | ||
025bb325 | 6625 | /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ |
c906108c | 6626 | |
bf1f5b4c | 6627 | static void |
e11c53d2 | 6628 | mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, |
bd2b40ac | 6629 | frame_info_ptr frame, int regnum, int all) |
c906108c | 6630 | { |
025bb325 | 6631 | if (regnum != -1) /* Do one specified register. */ |
c906108c | 6632 | { |
72a155b4 UW |
6633 | gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); |
6634 | if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') | |
8a3fe4f8 | 6635 | error (_("Not a valid register for the current processor type")); |
c906108c | 6636 | |
0cc93a06 | 6637 | mips_print_register (file, frame, regnum); |
6cb06a8c | 6638 | gdb_printf (file, "\n"); |
c906108c | 6639 | } |
c5aa993b | 6640 | else |
025bb325 | 6641 | /* Do all (or most) registers. */ |
c906108c | 6642 | { |
72a155b4 | 6643 | regnum = gdbarch_num_regs (gdbarch); |
f6efe3f8 | 6644 | while (regnum < gdbarch_num_cooked_regs (gdbarch)) |
c906108c | 6645 | { |
004159a2 | 6646 | if (mips_float_register_p (gdbarch, regnum)) |
e11c53d2 | 6647 | { |
025bb325 | 6648 | if (all) /* True for "INFO ALL-REGISTERS" command. */ |
e11c53d2 AC |
6649 | regnum = print_fp_register_row (file, frame, regnum); |
6650 | else | |
025bb325 | 6651 | regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
e11c53d2 | 6652 | } |
c906108c | 6653 | else |
e11c53d2 | 6654 | regnum = print_gp_register_row (file, frame, regnum); |
c906108c SS |
6655 | } |
6656 | } | |
6657 | } | |
6658 | ||
63807e1d | 6659 | static int |
3352ef37 | 6660 | mips_single_step_through_delay (struct gdbarch *gdbarch, |
bd2b40ac | 6661 | frame_info_ptr frame) |
c906108c | 6662 | { |
3352ef37 | 6663 | CORE_ADDR pc = get_frame_pc (frame); |
4cc0665f MR |
6664 | enum mips_isa isa; |
6665 | ULONGEST insn; | |
4cc0665f MR |
6666 | int size; |
6667 | ||
6668 | if ((mips_pc_is_mips (pc) | |
ab50adb6 | 6669 | && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) |
4cc0665f | 6670 | || (mips_pc_is_micromips (gdbarch, pc) |
ab50adb6 | 6671 | && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) |
4cc0665f | 6672 | || (mips_pc_is_mips16 (gdbarch, pc) |
ab50adb6 | 6673 | && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0))) |
06648491 MK |
6674 | return 0; |
6675 | ||
4cc0665f MR |
6676 | isa = mips_pc_isa (gdbarch, pc); |
6677 | /* _has_delay_slot above will have validated the read. */ | |
6678 | insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); | |
6679 | size = mips_insn_size (isa, insn); | |
8b86c959 YQ |
6680 | |
6681 | const address_space *aspace = get_frame_address_space (frame); | |
6682 | ||
4cc0665f | 6683 | return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; |
c906108c SS |
6684 | } |
6685 | ||
6d82d43b AC |
6686 | /* To skip prologues, I use this predicate. Returns either PC itself |
6687 | if the code at PC does not look like a function prologue; otherwise | |
6688 | returns an address that (if we're lucky) follows the prologue. If | |
6689 | LENIENT, then we must skip everything which is involved in setting | |
6690 | up the frame (it's OK to skip more, just so long as we don't skip | |
6691 | anything which might clobber the registers which are being saved. | |
6692 | We must skip more in the case where part of the prologue is in the | |
6693 | delay slot of a non-prologue instruction). */ | |
6694 | ||
6695 | static CORE_ADDR | |
6093d2eb | 6696 | mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
6d82d43b | 6697 | { |
8b622e6a AC |
6698 | CORE_ADDR limit_pc; |
6699 | CORE_ADDR func_addr; | |
6700 | ||
6d82d43b AC |
6701 | /* See if we can determine the end of the prologue via the symbol table. |
6702 | If so, then return either PC, or the PC after the prologue, whichever | |
6703 | is greater. */ | |
8b622e6a AC |
6704 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) |
6705 | { | |
d80b854b UW |
6706 | CORE_ADDR post_prologue_pc |
6707 | = skip_prologue_using_sal (gdbarch, func_addr); | |
8b622e6a | 6708 | if (post_prologue_pc != 0) |
325fac50 | 6709 | return std::max (pc, post_prologue_pc); |
8b622e6a | 6710 | } |
6d82d43b AC |
6711 | |
6712 | /* Can't determine prologue from the symbol table, need to examine | |
6713 | instructions. */ | |
6714 | ||
98b4dd94 JB |
6715 | /* Find an upper limit on the function prologue using the debug |
6716 | information. If the debug information could not be used to provide | |
6717 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 6718 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
98b4dd94 JB |
6719 | if (limit_pc == 0) |
6720 | limit_pc = pc + 100; /* Magic. */ | |
6721 | ||
4cc0665f | 6722 | if (mips_pc_is_mips16 (gdbarch, pc)) |
e17a4113 | 6723 | return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4cc0665f MR |
6724 | else if (mips_pc_is_micromips (gdbarch, pc)) |
6725 | return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | |
6d82d43b | 6726 | else |
e17a4113 | 6727 | return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
88658117 AC |
6728 | } |
6729 | ||
c9cf6e20 MG |
6730 | /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version). |
6731 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6732 | ||
97ab0fdd | 6733 | static int |
c9cf6e20 | 6734 | mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6735 | { |
6736 | CORE_ADDR func_addr = 0, func_end = 0; | |
6737 | ||
6738 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6739 | { | |
6740 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6741 | CORE_ADDR addr = func_end - 12; | |
6742 | ||
6743 | if (addr < func_addr + 4) | |
dda83cd7 | 6744 | addr = func_addr + 4; |
97ab0fdd | 6745 | if (pc < addr) |
dda83cd7 | 6746 | return 0; |
97ab0fdd MR |
6747 | |
6748 | for (; pc < func_end; pc += MIPS_INSN32_SIZE) | |
6749 | { | |
6750 | unsigned long high_word; | |
6751 | unsigned long inst; | |
6752 | ||
4cc0665f | 6753 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
97ab0fdd MR |
6754 | high_word = (inst >> 16) & 0xffff; |
6755 | ||
6756 | if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | |
6757 | && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | |
6758 | && inst != 0x03e00008 /* jr $ra */ | |
6759 | && inst != 0x00000000) /* nop */ | |
6760 | return 0; | |
6761 | } | |
6762 | ||
6763 | return 1; | |
6764 | } | |
6765 | ||
6766 | return 0; | |
6767 | } | |
6768 | ||
c9cf6e20 MG |
6769 | /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version). |
6770 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
4cc0665f MR |
6771 | |
6772 | static int | |
c9cf6e20 | 6773 | micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4cc0665f MR |
6774 | { |
6775 | CORE_ADDR func_addr = 0; | |
6776 | CORE_ADDR func_end = 0; | |
6777 | CORE_ADDR addr; | |
6778 | ULONGEST insn; | |
6779 | long offset; | |
6780 | int dreg; | |
6781 | int sreg; | |
6782 | int loc; | |
6783 | ||
6784 | if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6785 | return 0; | |
6786 | ||
6787 | /* The microMIPS epilogue is max. 12 bytes long. */ | |
6788 | addr = func_end - 12; | |
6789 | ||
6790 | if (addr < func_addr + 2) | |
6791 | addr = func_addr + 2; | |
6792 | if (pc < addr) | |
6793 | return 0; | |
6794 | ||
6795 | for (; pc < func_end; pc += loc) | |
6796 | { | |
6797 | loc = 0; | |
6798 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); | |
6799 | loc += MIPS_INSN16_SIZE; | |
6800 | switch (mips_insn_size (ISA_MICROMIPS, insn)) | |
6801 | { | |
4cc0665f MR |
6802 | /* 32-bit instructions. */ |
6803 | case 2 * MIPS_INSN16_SIZE: | |
6804 | insn <<= 16; | |
6805 | insn |= mips_fetch_instruction (gdbarch, | |
6806 | ISA_MICROMIPS, pc + loc, NULL); | |
6807 | loc += MIPS_INSN16_SIZE; | |
6808 | switch (micromips_op (insn >> 16)) | |
6809 | { | |
6810 | case 0xc: /* ADDIU: bits 001100 */ | |
6811 | case 0x17: /* DADDIU: bits 010111 */ | |
6812 | sreg = b0s5_reg (insn >> 16); | |
6813 | dreg = b5s5_reg (insn >> 16); | |
6814 | offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; | |
6815 | if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM | |
6816 | /* (D)ADDIU $sp, imm */ | |
6817 | && offset >= 0) | |
6818 | break; | |
6819 | return 0; | |
6820 | ||
6821 | default: | |
6822 | return 0; | |
6823 | } | |
6824 | break; | |
6825 | ||
6826 | /* 16-bit instructions. */ | |
6827 | case MIPS_INSN16_SIZE: | |
6828 | switch (micromips_op (insn)) | |
6829 | { | |
6830 | case 0x3: /* MOVE: bits 000011 */ | |
6831 | sreg = b0s5_reg (insn); | |
6832 | dreg = b5s5_reg (insn); | |
6833 | if (sreg == 0 && dreg == 0) | |
6834 | /* MOVE $zero, $zero aka NOP */ | |
6835 | break; | |
6836 | return 0; | |
6837 | ||
6838 | case 0x11: /* POOL16C: bits 010001 */ | |
6839 | if (b5s5_op (insn) == 0x18 | |
6840 | /* JRADDIUSP: bits 010011 11000 */ | |
6841 | || (b5s5_op (insn) == 0xd | |
6842 | /* JRC: bits 010011 01101 */ | |
6843 | && b0s5_reg (insn) == MIPS_RA_REGNUM)) | |
6844 | /* JRC $ra */ | |
6845 | break; | |
6846 | return 0; | |
6847 | ||
6848 | case 0x13: /* POOL16D: bits 010011 */ | |
6849 | offset = micromips_decode_imm9 (b1s9_imm (insn)); | |
6850 | if ((insn & 0x1) == 0x1 | |
6851 | /* ADDIUSP: bits 010011 1 */ | |
6852 | && offset > 0) | |
6853 | break; | |
6854 | return 0; | |
6855 | ||
6856 | default: | |
6857 | return 0; | |
6858 | } | |
6859 | } | |
6860 | } | |
6861 | ||
6862 | return 1; | |
6863 | } | |
6864 | ||
c9cf6e20 MG |
6865 | /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version). |
6866 | This is a helper function for mips_stack_frame_destroyed_p. */ | |
6867 | ||
97ab0fdd | 6868 | static int |
c9cf6e20 | 6869 | mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd MR |
6870 | { |
6871 | CORE_ADDR func_addr = 0, func_end = 0; | |
6872 | ||
6873 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
6874 | { | |
6875 | /* The MIPS epilogue is max. 12 bytes long. */ | |
6876 | CORE_ADDR addr = func_end - 12; | |
6877 | ||
6878 | if (addr < func_addr + 4) | |
dda83cd7 | 6879 | addr = func_addr + 4; |
97ab0fdd | 6880 | if (pc < addr) |
dda83cd7 | 6881 | return 0; |
97ab0fdd MR |
6882 | |
6883 | for (; pc < func_end; pc += MIPS_INSN16_SIZE) | |
6884 | { | |
6885 | unsigned short inst; | |
6886 | ||
4cc0665f | 6887 | inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
97ab0fdd MR |
6888 | |
6889 | if ((inst & 0xf800) == 0xf000) /* extend */ | |
6890 | continue; | |
6891 | ||
6892 | if (inst != 0x6300 /* addiu $sp,offset */ | |
6893 | && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | |
6894 | && inst != 0xe820 /* jr $ra */ | |
6895 | && inst != 0xe8a0 /* jrc $ra */ | |
6896 | && inst != 0x6500) /* nop */ | |
6897 | return 0; | |
6898 | } | |
6899 | ||
6900 | return 1; | |
6901 | } | |
6902 | ||
6903 | return 0; | |
6904 | } | |
6905 | ||
c9cf6e20 MG |
6906 | /* Implement the stack_frame_destroyed_p gdbarch method. |
6907 | ||
6908 | The epilogue is defined here as the area at the end of a function, | |
97ab0fdd | 6909 | after an instruction which destroys the function's stack frame. */ |
c9cf6e20 | 6910 | |
97ab0fdd | 6911 | static int |
c9cf6e20 | 6912 | mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
97ab0fdd | 6913 | { |
4cc0665f | 6914 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c9cf6e20 | 6915 | return mips16_stack_frame_destroyed_p (gdbarch, pc); |
4cc0665f | 6916 | else if (mips_pc_is_micromips (gdbarch, pc)) |
c9cf6e20 | 6917 | return micromips_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd | 6918 | else |
c9cf6e20 | 6919 | return mips32_stack_frame_destroyed_p (gdbarch, pc); |
97ab0fdd MR |
6920 | } |
6921 | ||
c906108c SS |
6922 | /* Commands to show/set the MIPS FPU type. */ |
6923 | ||
c906108c | 6924 | static void |
bd4c9dfe | 6925 | show_mipsfpu_command (const char *args, int from_tty) |
c906108c | 6926 | { |
a121b7c1 | 6927 | const char *fpu; |
6ca0852e | 6928 | |
f5656ead | 6929 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
6ca0852e | 6930 | { |
6cb06a8c | 6931 | gdb_printf |
6ca0852e UW |
6932 | ("The MIPS floating-point coprocessor is unknown " |
6933 | "because the current architecture is not MIPS.\n"); | |
6934 | return; | |
6935 | } | |
6936 | ||
345bd07c | 6937 | switch (mips_get_fpu_type (target_gdbarch ())) |
c906108c SS |
6938 | { |
6939 | case MIPS_FPU_SINGLE: | |
6940 | fpu = "single-precision"; | |
6941 | break; | |
6942 | case MIPS_FPU_DOUBLE: | |
6943 | fpu = "double-precision"; | |
6944 | break; | |
6945 | case MIPS_FPU_NONE: | |
6946 | fpu = "absent (none)"; | |
6947 | break; | |
93d56215 | 6948 | default: |
f34652de | 6949 | internal_error (_("bad switch")); |
c906108c SS |
6950 | } |
6951 | if (mips_fpu_type_auto) | |
6cb06a8c TT |
6952 | gdb_printf ("The MIPS floating-point coprocessor " |
6953 | "is set automatically (currently %s)\n", | |
6954 | fpu); | |
c906108c | 6955 | else |
6cb06a8c | 6956 | gdb_printf |
6d82d43b | 6957 | ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); |
c906108c SS |
6958 | } |
6959 | ||
6960 | ||
c906108c | 6961 | static void |
bd4c9dfe | 6962 | set_mipsfpu_single_command (const char *args, int from_tty) |
c906108c | 6963 | { |
8d5838b5 | 6964 | struct gdbarch_info info; |
c906108c SS |
6965 | mips_fpu_type = MIPS_FPU_SINGLE; |
6966 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6967 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6968 | instead of relying on globals. Doing that would let generic code | |
6969 | handle the search for this specific architecture. */ | |
6970 | if (!gdbarch_update_p (info)) | |
f34652de | 6971 | internal_error (_("set mipsfpu failed")); |
c906108c SS |
6972 | } |
6973 | ||
c906108c | 6974 | static void |
bd4c9dfe | 6975 | set_mipsfpu_double_command (const char *args, int from_tty) |
c906108c | 6976 | { |
8d5838b5 | 6977 | struct gdbarch_info info; |
c906108c SS |
6978 | mips_fpu_type = MIPS_FPU_DOUBLE; |
6979 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6980 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6981 | instead of relying on globals. Doing that would let generic code | |
6982 | handle the search for this specific architecture. */ | |
6983 | if (!gdbarch_update_p (info)) | |
f34652de | 6984 | internal_error (_("set mipsfpu failed")); |
c906108c SS |
6985 | } |
6986 | ||
c906108c | 6987 | static void |
bd4c9dfe | 6988 | set_mipsfpu_none_command (const char *args, int from_tty) |
c906108c | 6989 | { |
8d5838b5 | 6990 | struct gdbarch_info info; |
c906108c SS |
6991 | mips_fpu_type = MIPS_FPU_NONE; |
6992 | mips_fpu_type_auto = 0; | |
8d5838b5 AC |
6993 | /* FIXME: cagney/2003-11-15: Should be setting a field in "info" |
6994 | instead of relying on globals. Doing that would let generic code | |
6995 | handle the search for this specific architecture. */ | |
6996 | if (!gdbarch_update_p (info)) | |
f34652de | 6997 | internal_error (_("set mipsfpu failed")); |
c906108c SS |
6998 | } |
6999 | ||
c906108c | 7000 | static void |
bd4c9dfe | 7001 | set_mipsfpu_auto_command (const char *args, int from_tty) |
c906108c SS |
7002 | { |
7003 | mips_fpu_type_auto = 1; | |
7004 | } | |
7005 | ||
c906108c SS |
7006 | /* Just like reinit_frame_cache, but with the right arguments to be |
7007 | callable as an sfunc. */ | |
7008 | ||
7009 | static void | |
eb4c3f4a | 7010 | reinit_frame_cache_sfunc (const char *args, int from_tty, |
acdb74a0 | 7011 | struct cmd_list_element *c) |
c906108c SS |
7012 | { |
7013 | reinit_frame_cache (); | |
7014 | } | |
7015 | ||
a89aa300 AC |
7016 | static int |
7017 | gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | |
c906108c | 7018 | { |
f0c2e3e0 AB |
7019 | gdb_disassemble_info *di |
7020 | = static_cast<gdb_disassemble_info *> (info->application_data); | |
e47ad6c0 | 7021 | struct gdbarch *gdbarch = di->arch (); |
4cc0665f | 7022 | |
d31431ed AC |
7023 | /* FIXME: cagney/2003-06-26: Is this even necessary? The |
7024 | disassembler needs to be able to locally determine the ISA, and | |
7025 | not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | |
7026 | work. */ | |
4cc0665f | 7027 | if (mips_pc_is_mips16 (gdbarch, memaddr)) |
ec4045ea | 7028 | info->mach = bfd_mach_mips16; |
4cc0665f MR |
7029 | else if (mips_pc_is_micromips (gdbarch, memaddr)) |
7030 | info->mach = bfd_mach_mips_micromips; | |
c906108c SS |
7031 | |
7032 | /* Round down the instruction address to the appropriate boundary. */ | |
4cc0665f MR |
7033 | memaddr &= (info->mach == bfd_mach_mips16 |
7034 | || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; | |
c5aa993b | 7035 | |
6394c606 | 7036 | return default_print_insn (memaddr, info); |
c906108c SS |
7037 | } |
7038 | ||
cd6c3b4f YQ |
7039 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
7040 | ||
d19280ad YQ |
7041 | static int |
7042 | mips_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
c906108c | 7043 | { |
4cc0665f MR |
7044 | CORE_ADDR pc = *pcptr; |
7045 | ||
d19280ad | 7046 | if (mips_pc_is_mips16 (gdbarch, pc)) |
c906108c | 7047 | { |
d19280ad YQ |
7048 | *pcptr = unmake_compact_addr (pc); |
7049 | return MIPS_BP_KIND_MIPS16; | |
7050 | } | |
7051 | else if (mips_pc_is_micromips (gdbarch, pc)) | |
7052 | { | |
7053 | ULONGEST insn; | |
7054 | int status; | |
c906108c | 7055 | |
d19280ad YQ |
7056 | *pcptr = unmake_compact_addr (pc); |
7057 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); | |
7058 | if (status || (mips_insn_size (ISA_MICROMIPS, insn) == 2)) | |
7059 | return MIPS_BP_KIND_MICROMIPS16; | |
7060 | else | |
7061 | return MIPS_BP_KIND_MICROMIPS32; | |
c906108c SS |
7062 | } |
7063 | else | |
d19280ad YQ |
7064 | return MIPS_BP_KIND_MIPS32; |
7065 | } | |
7066 | ||
cd6c3b4f YQ |
7067 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
7068 | ||
d19280ad YQ |
7069 | static const gdb_byte * |
7070 | mips_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
7071 | { | |
7072 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
7073 | ||
7074 | switch (kind) | |
c906108c | 7075 | { |
d19280ad YQ |
7076 | case MIPS_BP_KIND_MIPS16: |
7077 | { | |
7078 | static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; | |
7079 | static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; | |
7080 | ||
7081 | *size = 2; | |
7082 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7083 | return mips16_big_breakpoint; | |
7084 | else | |
c906108c | 7085 | return mips16_little_breakpoint; |
d19280ad YQ |
7086 | } |
7087 | case MIPS_BP_KIND_MICROMIPS16: | |
7088 | { | |
7089 | static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; | |
7090 | static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; | |
7091 | ||
7092 | *size = 2; | |
7093 | ||
7094 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7095 | return micromips16_big_breakpoint; | |
7096 | else | |
7097 | return micromips16_little_breakpoint; | |
7098 | } | |
7099 | case MIPS_BP_KIND_MICROMIPS32: | |
7100 | { | |
7101 | static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; | |
7102 | static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; | |
7103 | ||
7104 | *size = 4; | |
7105 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7106 | return micromips32_big_breakpoint; | |
7107 | else | |
7108 | return micromips32_little_breakpoint; | |
7109 | } | |
7110 | case MIPS_BP_KIND_MIPS32: | |
7111 | { | |
7112 | static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; | |
7113 | static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; | |
c906108c | 7114 | |
d19280ad YQ |
7115 | *size = 4; |
7116 | if (byte_order_for_code == BFD_ENDIAN_BIG) | |
7117 | return big_breakpoint; | |
7118 | else | |
7e3d947d | 7119 | return little_breakpoint; |
d19280ad YQ |
7120 | } |
7121 | default: | |
7122 | gdb_assert_not_reached ("unexpected mips breakpoint kind"); | |
7123 | }; | |
c906108c SS |
7124 | } |
7125 | ||
ab50adb6 MR |
7126 | /* Return non-zero if the standard MIPS instruction INST has a branch |
7127 | delay slot (i.e. it is a jump or branch instruction). This function | |
7128 | is based on mips32_next_pc. */ | |
c8cef75f MR |
7129 | |
7130 | static int | |
ab50adb6 | 7131 | mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) |
c8cef75f | 7132 | { |
c8cef75f | 7133 | int op; |
a385295e MR |
7134 | int rs; |
7135 | int rt; | |
c8cef75f | 7136 | |
c8cef75f MR |
7137 | op = itype_op (inst); |
7138 | if ((inst & 0xe0000000) != 0) | |
a385295e MR |
7139 | { |
7140 | rs = itype_rs (inst); | |
7141 | rt = itype_rt (inst); | |
f94363d7 AP |
7142 | return (is_octeon_bbit_op (op, gdbarch) |
7143 | || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | |
a385295e MR |
7144 | || op == 29 /* JALX: bits 011101 */ |
7145 | || (op == 17 | |
7146 | && (rs == 8 | |
c8cef75f | 7147 | /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
a385295e MR |
7148 | || (rs == 9 && (rt & 0x2) == 0) |
7149 | /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ | |
7150 | || (rs == 10 && (rt & 0x2) == 0)))); | |
7151 | /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ | |
7152 | } | |
c8cef75f MR |
7153 | else |
7154 | switch (op & 0x07) /* extract bits 28,27,26 */ | |
7155 | { | |
7156 | case 0: /* SPECIAL */ | |
7157 | op = rtype_funct (inst); | |
7158 | return (op == 8 /* JR */ | |
7159 | || op == 9); /* JALR */ | |
7160 | break; /* end SPECIAL */ | |
7161 | case 1: /* REGIMM */ | |
a385295e MR |
7162 | rs = itype_rs (inst); |
7163 | rt = itype_rt (inst); /* branch condition */ | |
7164 | return ((rt & 0xc) == 0 | |
c8cef75f MR |
7165 | /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
7166 | /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ | |
a385295e MR |
7167 | || ((rt & 0x1e) == 0x1c && rs == 0)); |
7168 | /* BPOSGE32, BPOSGE64: bits 1110x */ | |
c8cef75f MR |
7169 | break; /* end REGIMM */ |
7170 | default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ | |
7171 | return 1; | |
7172 | break; | |
7173 | } | |
7174 | } | |
7175 | ||
ab50adb6 MR |
7176 | /* Return non-zero if a standard MIPS instruction at ADDR has a branch |
7177 | delay slot (i.e. it is a jump or branch instruction). */ | |
c8cef75f | 7178 | |
4cc0665f | 7179 | static int |
ab50adb6 | 7180 | mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) |
4cc0665f MR |
7181 | { |
7182 | ULONGEST insn; | |
7183 | int status; | |
7184 | ||
ab50adb6 | 7185 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
4cc0665f MR |
7186 | if (status) |
7187 | return 0; | |
7188 | ||
ab50adb6 MR |
7189 | return mips32_instruction_has_delay_slot (gdbarch, insn); |
7190 | } | |
4cc0665f | 7191 | |
ab50adb6 MR |
7192 | /* Return non-zero if the microMIPS instruction INSN, comprising the |
7193 | 16-bit major opcode word in the high 16 bits and any second word | |
7194 | in the low 16 bits, has a branch delay slot (i.e. it is a non-compact | |
7195 | jump or branch instruction). The instruction must be 32-bit if | |
7196 | MUSTBE32 is set or can be any instruction otherwise. */ | |
7197 | ||
7198 | static int | |
7199 | micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) | |
7200 | { | |
7201 | ULONGEST major = insn >> 16; | |
4cc0665f | 7202 | |
ab50adb6 MR |
7203 | switch (micromips_op (major)) |
7204 | { | |
7205 | /* 16-bit instructions. */ | |
7206 | case 0x33: /* B16: bits 110011 */ | |
7207 | case 0x2b: /* BNEZ16: bits 101011 */ | |
7208 | case 0x23: /* BEQZ16: bits 100011 */ | |
7209 | return !mustbe32; | |
7210 | case 0x11: /* POOL16C: bits 010001 */ | |
7211 | return (!mustbe32 | |
7212 | && ((b5s5_op (major) == 0xc | |
7213 | /* JR16: bits 010001 01100 */ | |
7214 | || (b5s5_op (major) & 0x1e) == 0xe))); | |
7215 | /* JALR16, JALRS16: bits 010001 0111x */ | |
7216 | /* 32-bit instructions. */ | |
7217 | case 0x3d: /* JAL: bits 111101 */ | |
7218 | case 0x3c: /* JALX: bits 111100 */ | |
7219 | case 0x35: /* J: bits 110101 */ | |
7220 | case 0x2d: /* BNE: bits 101101 */ | |
7221 | case 0x25: /* BEQ: bits 100101 */ | |
7222 | case 0x1d: /* JALS: bits 011101 */ | |
7223 | return 1; | |
7224 | case 0x10: /* POOL32I: bits 010000 */ | |
7225 | return ((b5s5_op (major) & 0x1c) == 0x0 | |
4cc0665f | 7226 | /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ |
ab50adb6 | 7227 | || (b5s5_op (major) & 0x1d) == 0x4 |
4cc0665f | 7228 | /* BLEZ, BGTZ: bits 010000 001x0 */ |
ab50adb6 | 7229 | || (b5s5_op (major) & 0x1d) == 0x11 |
4cc0665f | 7230 | /* BLTZALS, BGEZALS: bits 010000 100x1 */ |
ab50adb6 MR |
7231 | || ((b5s5_op (major) & 0x1e) == 0x14 |
7232 | && (major & 0x3) == 0x0) | |
4cc0665f | 7233 | /* BC2F, BC2T: bits 010000 1010x xxx00 */ |
ab50adb6 | 7234 | || (b5s5_op (major) & 0x1e) == 0x1a |
4cc0665f | 7235 | /* BPOSGE64, BPOSGE32: bits 010000 1101x */ |
ab50adb6 MR |
7236 | || ((b5s5_op (major) & 0x1e) == 0x1c |
7237 | && (major & 0x3) == 0x0) | |
4cc0665f | 7238 | /* BC1F, BC1T: bits 010000 1110x xxx00 */ |
ab50adb6 MR |
7239 | || ((b5s5_op (major) & 0x1c) == 0x1c |
7240 | && (major & 0x3) == 0x1)); | |
4cc0665f | 7241 | /* BC1ANY*: bits 010000 111xx xxx01 */ |
ab50adb6 MR |
7242 | case 0x0: /* POOL32A: bits 000000 */ |
7243 | return (b0s6_op (insn) == 0x3c | |
7244 | /* POOL32Axf: bits 000000 ... 111100 */ | |
7245 | && (b6s10_ext (insn) & 0x2bf) == 0x3c); | |
7246 | /* JALR, JALR.HB: 000000 000x111100 111100 */ | |
7247 | /* JALRS, JALRS.HB: 000000 010x111100 111100 */ | |
7248 | default: | |
7249 | return 0; | |
7250 | } | |
4cc0665f MR |
7251 | } |
7252 | ||
ab50adb6 | 7253 | /* Return non-zero if a microMIPS instruction at ADDR has a branch delay |
ae790652 MR |
7254 | slot (i.e. it is a non-compact jump instruction). The instruction |
7255 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7256 | ||
c8cef75f | 7257 | static int |
ab50adb6 MR |
7258 | micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, |
7259 | CORE_ADDR addr, int mustbe32) | |
c8cef75f | 7260 | { |
ab50adb6 | 7261 | ULONGEST insn; |
c8cef75f | 7262 | int status; |
3f7f3650 | 7263 | int size; |
c8cef75f | 7264 | |
ab50adb6 | 7265 | insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); |
c8cef75f MR |
7266 | if (status) |
7267 | return 0; | |
3f7f3650 | 7268 | size = mips_insn_size (ISA_MICROMIPS, insn); |
ab50adb6 | 7269 | insn <<= 16; |
3f7f3650 | 7270 | if (size == 2 * MIPS_INSN16_SIZE) |
ab50adb6 MR |
7271 | { |
7272 | insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); | |
7273 | if (status) | |
7274 | return 0; | |
7275 | } | |
7276 | ||
7277 | return micromips_instruction_has_delay_slot (insn, mustbe32); | |
7278 | } | |
c8cef75f | 7279 | |
ab50adb6 MR |
7280 | /* Return non-zero if the MIPS16 instruction INST, which must be |
7281 | a 32-bit instruction if MUSTBE32 is set or can be any instruction | |
7282 | otherwise, has a branch delay slot (i.e. it is a non-compact jump | |
7283 | instruction). This function is based on mips16_next_pc. */ | |
7284 | ||
7285 | static int | |
7286 | mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) | |
7287 | { | |
ae790652 MR |
7288 | if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ |
7289 | return !mustbe32; | |
c8cef75f MR |
7290 | return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ |
7291 | } | |
7292 | ||
ab50adb6 MR |
7293 | /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay |
7294 | slot (i.e. it is a non-compact jump instruction). The instruction | |
7295 | must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ | |
7296 | ||
7297 | static int | |
7298 | mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, | |
7299 | CORE_ADDR addr, int mustbe32) | |
7300 | { | |
7301 | unsigned short insn; | |
7302 | int status; | |
7303 | ||
7304 | insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); | |
7305 | if (status) | |
7306 | return 0; | |
7307 | ||
7308 | return mips16_instruction_has_delay_slot (insn, mustbe32); | |
7309 | } | |
7310 | ||
c8cef75f MR |
7311 | /* Calculate the starting address of the MIPS memory segment BPADDR is in. |
7312 | This assumes KSSEG exists. */ | |
7313 | ||
7314 | static CORE_ADDR | |
7315 | mips_segment_boundary (CORE_ADDR bpaddr) | |
7316 | { | |
7317 | CORE_ADDR mask = CORE_ADDR_MAX; | |
7318 | int segsize; | |
7319 | ||
7320 | if (sizeof (CORE_ADDR) == 8) | |
7321 | /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid | |
7322 | a compiler warning produced where CORE_ADDR is a 32-bit type even | |
7323 | though in that case this is dead code). */ | |
7324 | switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) | |
7325 | { | |
7326 | case 3: | |
7327 | if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) | |
7328 | segsize = 29; /* 32-bit compatibility segment */ | |
7329 | else | |
7330 | segsize = 62; /* xkseg */ | |
7331 | break; | |
7332 | case 2: /* xkphys */ | |
7333 | segsize = 59; | |
7334 | break; | |
7335 | default: /* xksseg (1), xkuseg/kuseg (0) */ | |
7336 | segsize = 62; | |
7337 | break; | |
7338 | } | |
7339 | else if (bpaddr & 0x80000000) /* kernel segment */ | |
7340 | segsize = 29; | |
7341 | else | |
7342 | segsize = 31; /* user segment */ | |
7343 | mask <<= segsize; | |
7344 | return bpaddr & mask; | |
7345 | } | |
7346 | ||
7347 | /* Move the breakpoint at BPADDR out of any branch delay slot by shifting | |
7348 | it backwards if necessary. Return the address of the new location. */ | |
7349 | ||
7350 | static CORE_ADDR | |
7351 | mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) | |
7352 | { | |
22e048c9 | 7353 | CORE_ADDR prev_addr; |
c8cef75f MR |
7354 | CORE_ADDR boundary; |
7355 | CORE_ADDR func_addr; | |
7356 | ||
7357 | /* If a breakpoint is set on the instruction in a branch delay slot, | |
7358 | GDB gets confused. When the breakpoint is hit, the PC isn't on | |
7359 | the instruction in the branch delay slot, the PC will point to | |
7360 | the branch instruction. Since the PC doesn't match any known | |
7361 | breakpoints, GDB reports a trap exception. | |
7362 | ||
7363 | There are two possible fixes for this problem. | |
7364 | ||
7365 | 1) When the breakpoint gets hit, see if the BD bit is set in the | |
7366 | Cause register (which indicates the last exception occurred in a | |
7367 | branch delay slot). If the BD bit is set, fix the PC to point to | |
7368 | the instruction in the branch delay slot. | |
7369 | ||
7370 | 2) When the user sets the breakpoint, don't allow him to set the | |
7371 | breakpoint on the instruction in the branch delay slot. Instead | |
7372 | move the breakpoint to the branch instruction (which will have | |
7373 | the same result). | |
7374 | ||
7375 | The problem with the first solution is that if the user then | |
7376 | single-steps the processor, the branch instruction will get | |
7377 | skipped (since GDB thinks the PC is on the instruction in the | |
7378 | branch delay slot). | |
7379 | ||
7380 | So, we'll use the second solution. To do this we need to know if | |
7381 | the instruction we're trying to set the breakpoint on is in the | |
7382 | branch delay slot. */ | |
7383 | ||
7384 | boundary = mips_segment_boundary (bpaddr); | |
7385 | ||
7386 | /* Make sure we don't scan back before the beginning of the current | |
7387 | function, since we may fetch constant data or insns that look like | |
7388 | a jump. Of course we might do that anyway if the compiler has | |
7389 | moved constants inline. :-( */ | |
7390 | if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) | |
7391 | && func_addr > boundary && func_addr <= bpaddr) | |
7392 | boundary = func_addr; | |
7393 | ||
4cc0665f | 7394 | if (mips_pc_is_mips (bpaddr)) |
c8cef75f MR |
7395 | { |
7396 | if (bpaddr == boundary) | |
7397 | return bpaddr; | |
7398 | ||
7399 | /* If the previous instruction has a branch delay slot, we have | |
dda83cd7 | 7400 | to move the breakpoint to the branch instruction. */ |
c8cef75f | 7401 | prev_addr = bpaddr - 4; |
ab50adb6 | 7402 | if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) |
c8cef75f MR |
7403 | bpaddr = prev_addr; |
7404 | } | |
7405 | else | |
7406 | { | |
ab50adb6 | 7407 | int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
c8cef75f MR |
7408 | CORE_ADDR addr, jmpaddr; |
7409 | int i; | |
7410 | ||
4cc0665f | 7411 | boundary = unmake_compact_addr (boundary); |
c8cef75f MR |
7412 | |
7413 | /* The only MIPS16 instructions with delay slots are JAL, JALX, | |
dda83cd7 SM |
7414 | JALR and JR. An absolute JAL/JALX is always 4 bytes long, |
7415 | so try for that first, then try the 2 byte JALR/JR. | |
7416 | The microMIPS ASE has a whole range of jumps and branches | |
7417 | with delay slots, some of which take 4 bytes and some take | |
7418 | 2 bytes, so the idea is the same. | |
7419 | FIXME: We have to assume that bpaddr is not the second half | |
7420 | of an extended instruction. */ | |
ab50adb6 MR |
7421 | insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
7422 | ? micromips_insn_at_pc_has_delay_slot | |
7423 | : mips16_insn_at_pc_has_delay_slot); | |
c8cef75f MR |
7424 | |
7425 | jmpaddr = 0; | |
7426 | addr = bpaddr; | |
7427 | for (i = 1; i < 4; i++) | |
7428 | { | |
4cc0665f | 7429 | if (unmake_compact_addr (addr) == boundary) |
c8cef75f | 7430 | break; |
4cc0665f | 7431 | addr -= MIPS_INSN16_SIZE; |
ab50adb6 | 7432 | if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) |
c8cef75f MR |
7433 | /* Looks like a JR/JALR at [target-1], but it could be |
7434 | the second word of a previous JAL/JALX, so record it | |
7435 | and check back one more. */ | |
7436 | jmpaddr = addr; | |
ab50adb6 | 7437 | else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) |
c8cef75f MR |
7438 | { |
7439 | if (i == 2) | |
7440 | /* Looks like a JAL/JALX at [target-2], but it could also | |
7441 | be the second word of a previous JAL/JALX, record it, | |
7442 | and check back one more. */ | |
7443 | jmpaddr = addr; | |
7444 | else | |
7445 | /* Looks like a JAL/JALX at [target-3], so any previously | |
7446 | recorded JAL/JALX or JR/JALR must be wrong, because: | |
7447 | ||
7448 | >-3: JAL | |
7449 | -2: JAL-ext (can't be JAL/JALX) | |
7450 | -1: bdslot (can't be JR/JALR) | |
7451 | 0: target insn | |
7452 | ||
7453 | Of course it could be another JAL-ext which looks | |
7454 | like a JAL, but in that case we'd have broken out | |
7455 | of this loop at [target-2]: | |
7456 | ||
7457 | -4: JAL | |
7458 | >-3: JAL-ext | |
7459 | -2: bdslot (can't be jmp) | |
7460 | -1: JR/JALR | |
7461 | 0: target insn */ | |
7462 | jmpaddr = 0; | |
7463 | } | |
7464 | else | |
7465 | { | |
7466 | /* Not a jump instruction: if we're at [target-1] this | |
dda83cd7 SM |
7467 | could be the second word of a JAL/JALX, so continue; |
7468 | otherwise we're done. */ | |
c8cef75f MR |
7469 | if (i > 1) |
7470 | break; | |
7471 | } | |
7472 | } | |
7473 | ||
7474 | if (jmpaddr) | |
7475 | bpaddr = jmpaddr; | |
7476 | } | |
7477 | ||
7478 | return bpaddr; | |
7479 | } | |
7480 | ||
14132e89 MR |
7481 | /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
7482 | call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ | |
7483 | ||
7484 | static int | |
7485 | mips_is_stub_suffix (const char *suffix, int zero) | |
7486 | { | |
7487 | switch (suffix[0]) | |
7488 | { | |
7489 | case '0': | |
7490 | return zero && suffix[1] == '\0'; | |
7491 | case '1': | |
7492 | return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); | |
7493 | case '2': | |
7494 | case '5': | |
7495 | case '6': | |
7496 | case '9': | |
7497 | return suffix[1] == '\0'; | |
7498 | default: | |
7499 | return 0; | |
7500 | } | |
7501 | } | |
7502 | ||
7503 | /* Return non-zero if MODE is one of the mode infixes used for MIPS16 | |
7504 | call stubs, one of sf, df, sc, or dc. */ | |
7505 | ||
7506 | static int | |
7507 | mips_is_stub_mode (const char *mode) | |
7508 | { | |
7509 | return ((mode[0] == 's' || mode[0] == 'd') | |
7510 | && (mode[1] == 'f' || mode[1] == 'c')); | |
7511 | } | |
7512 | ||
7513 | /* Code at PC is a compiler-generated stub. Such a stub for a function | |
7514 | bar might have a name like __fn_stub_bar, and might look like this: | |
7515 | ||
7516 | mfc1 $4, $f13 | |
7517 | mfc1 $5, $f12 | |
7518 | mfc1 $6, $f15 | |
7519 | mfc1 $7, $f14 | |
7520 | ||
7521 | followed by (or interspersed with): | |
7522 | ||
7523 | j bar | |
7524 | ||
7525 | or: | |
7526 | ||
7527 | lui $25, %hi(bar) | |
7528 | addiu $25, $25, %lo(bar) | |
7529 | jr $25 | |
7530 | ||
7531 | ($1 may be used in old code; for robustness we accept any register) | |
7532 | or, in PIC code: | |
7533 | ||
7534 | lui $28, %hi(_gp_disp) | |
7535 | addiu $28, $28, %lo(_gp_disp) | |
7536 | addu $28, $28, $25 | |
7537 | lw $25, %got(bar) | |
7538 | addiu $25, $25, %lo(bar) | |
7539 | jr $25 | |
7540 | ||
7541 | In the case of a __call_stub_bar stub, the sequence to set up | |
7542 | arguments might look like this: | |
7543 | ||
7544 | mtc1 $4, $f13 | |
7545 | mtc1 $5, $f12 | |
7546 | mtc1 $6, $f15 | |
7547 | mtc1 $7, $f14 | |
7548 | ||
7549 | followed by (or interspersed with) one of the jump sequences above. | |
7550 | ||
7551 | In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead | |
7552 | of J or JR, respectively, followed by: | |
7553 | ||
7554 | mfc1 $2, $f0 | |
7555 | mfc1 $3, $f1 | |
7556 | jr $18 | |
7557 | ||
7558 | We are at the beginning of the stub here, and scan down and extract | |
7559 | the target address from the jump immediate instruction or, if a jump | |
7560 | register instruction is used, from the register referred. Return | |
7561 | the value of PC calculated or 0 if inconclusive. | |
7562 | ||
7563 | The limit on the search is arbitrarily set to 20 instructions. FIXME. */ | |
7564 | ||
7565 | static CORE_ADDR | |
bd2b40ac | 7566 | mips_get_mips16_fn_stub_pc (frame_info_ptr frame, CORE_ADDR pc) |
14132e89 MR |
7567 | { |
7568 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
7569 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7570 | int addrreg = MIPS_ZERO_REGNUM; | |
7571 | CORE_ADDR start_pc = pc; | |
7572 | CORE_ADDR target_pc = 0; | |
7573 | CORE_ADDR addr = 0; | |
7574 | CORE_ADDR gp = 0; | |
7575 | int status = 0; | |
7576 | int i; | |
7577 | ||
7578 | for (i = 0; | |
7579 | status == 0 && target_pc == 0 && i < 20; | |
7580 | i++, pc += MIPS_INSN32_SIZE) | |
7581 | { | |
4cc0665f | 7582 | ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
14132e89 MR |
7583 | CORE_ADDR imm; |
7584 | int rt; | |
7585 | int rs; | |
7586 | int rd; | |
7587 | ||
7588 | switch (itype_op (inst)) | |
7589 | { | |
7590 | case 0: /* SPECIAL */ | |
7591 | switch (rtype_funct (inst)) | |
7592 | { | |
7593 | case 8: /* JR */ | |
7594 | case 9: /* JALR */ | |
7595 | rs = rtype_rs (inst); | |
7596 | if (rs == MIPS_GP_REGNUM) | |
7597 | target_pc = gp; /* Hmm... */ | |
7598 | else if (rs == addrreg) | |
7599 | target_pc = addr; | |
7600 | break; | |
7601 | ||
7602 | case 0x21: /* ADDU */ | |
7603 | rt = rtype_rt (inst); | |
7604 | rs = rtype_rs (inst); | |
7605 | rd = rtype_rd (inst); | |
7606 | if (rd == MIPS_GP_REGNUM | |
7607 | && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) | |
7608 | || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) | |
7609 | gp += start_pc; | |
7610 | break; | |
7611 | } | |
7612 | break; | |
7613 | ||
7614 | case 2: /* J */ | |
7615 | case 3: /* JAL */ | |
7616 | target_pc = jtype_target (inst) << 2; | |
7617 | target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | |
7618 | break; | |
7619 | ||
7620 | case 9: /* ADDIU */ | |
7621 | rt = itype_rt (inst); | |
7622 | rs = itype_rs (inst); | |
7623 | if (rt == rs) | |
7624 | { | |
7625 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7626 | if (rt == MIPS_GP_REGNUM) | |
7627 | gp += imm; | |
7628 | else if (rt == addrreg) | |
7629 | addr += imm; | |
7630 | } | |
7631 | break; | |
7632 | ||
7633 | case 0xf: /* LUI */ | |
7634 | rt = itype_rt (inst); | |
7635 | imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; | |
7636 | if (rt == MIPS_GP_REGNUM) | |
7637 | gp = imm; | |
7638 | else if (rt != MIPS_ZERO_REGNUM) | |
7639 | { | |
7640 | addrreg = rt; | |
7641 | addr = imm; | |
7642 | } | |
7643 | break; | |
7644 | ||
7645 | case 0x23: /* LW */ | |
7646 | rt = itype_rt (inst); | |
7647 | rs = itype_rs (inst); | |
7648 | imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; | |
7649 | if (gp != 0 && rs == MIPS_GP_REGNUM) | |
7650 | { | |
7651 | gdb_byte buf[4]; | |
7652 | ||
7653 | memset (buf, 0, sizeof (buf)); | |
7654 | status = target_read_memory (gp + imm, buf, sizeof (buf)); | |
7655 | addrreg = rt; | |
7656 | addr = extract_signed_integer (buf, sizeof (buf), byte_order); | |
7657 | } | |
7658 | break; | |
7659 | } | |
7660 | } | |
7661 | ||
7662 | return target_pc; | |
7663 | } | |
7664 | ||
7665 | /* If PC is in a MIPS16 call or return stub, return the address of the | |
7666 | target PC, which is either the callee or the caller. There are several | |
c906108c SS |
7667 | cases which must be handled: |
7668 | ||
14132e89 MR |
7669 | * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7670 | and the target PC is in $31 ($ra). | |
c906108c | 7671 | * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
14132e89 MR |
7672 | and the target PC is in $2. |
7673 | * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, | |
7674 | i.e. before the JALR instruction, this is effectively a call stub | |
7675 | and the target PC is in $2. Otherwise this is effectively | |
7676 | a return stub and the target PC is in $18. | |
7677 | * If the PC is at the start of __call_stub_fp_*, i.e. before the | |
7678 | JAL or JALR instruction, this is effectively a call stub and the | |
7679 | target PC is buried in the instruction stream. Otherwise this | |
7680 | is effectively a return stub and the target PC is in $18. | |
7681 | * If the PC is in __call_stub_* or in __fn_stub_*, this is a call | |
7682 | stub and the target PC is buried in the instruction stream. | |
7683 | ||
7684 | See the source code for the stubs in gcc/config/mips/mips16.S, or the | |
7685 | stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the | |
e7d6a6d2 | 7686 | gory details. */ |
c906108c | 7687 | |
757a7cc6 | 7688 | static CORE_ADDR |
bd2b40ac | 7689 | mips_skip_mips16_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) |
c906108c | 7690 | { |
e17a4113 | 7691 | struct gdbarch *gdbarch = get_frame_arch (frame); |
c906108c | 7692 | CORE_ADDR start_addr; |
14132e89 MR |
7693 | const char *name; |
7694 | size_t prefixlen; | |
c906108c SS |
7695 | |
7696 | /* Find the starting address and name of the function containing the PC. */ | |
7697 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
7698 | return 0; | |
7699 | ||
14132e89 MR |
7700 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
7701 | and the target PC is in $31 ($ra). */ | |
7702 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7703 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7704 | && mips_is_stub_mode (name + prefixlen) | |
7705 | && name[prefixlen + 2] == '\0') | |
7706 | return get_frame_register_signed | |
7707 | (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); | |
7708 | ||
7709 | /* If the PC is in __mips16_call_stub_*, this is one of the call | |
7710 | call/return stubs. */ | |
7711 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7712 | if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) | |
c906108c SS |
7713 | { |
7714 | /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | |
dda83cd7 | 7715 | and the target PC is in $2. */ |
14132e89 MR |
7716 | if (mips_is_stub_suffix (name + prefixlen, 0)) |
7717 | return get_frame_register_signed | |
7718 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c | 7719 | |
14132e89 | 7720 | /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
dda83cd7 SM |
7721 | i.e. before the JALR instruction, this is effectively a call stub |
7722 | and the target PC is in $2. Otherwise this is effectively | |
7723 | a return stub and the target PC is in $18. */ | |
14132e89 MR |
7724 | else if (mips_is_stub_mode (name + prefixlen) |
7725 | && name[prefixlen + 2] == '_' | |
7726 | && mips_is_stub_suffix (name + prefixlen + 3, 0)) | |
c906108c SS |
7727 | { |
7728 | if (pc == start_addr) | |
14132e89 MR |
7729 | /* This is the 'call' part of a call stub. The return |
7730 | address is in $2. */ | |
7731 | return get_frame_register_signed | |
7732 | (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); | |
c906108c SS |
7733 | else |
7734 | /* This is the 'return' part of a call stub. The return | |
14132e89 MR |
7735 | address is in $18. */ |
7736 | return get_frame_register_signed | |
7737 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7738 | } |
14132e89 MR |
7739 | else |
7740 | return 0; /* Not a stub. */ | |
7741 | } | |
7742 | ||
7743 | /* If the PC is in __call_stub_* or __fn_stub*, this is one of the | |
7744 | compiler-generated call or call/return stubs. */ | |
61012eef GB |
7745 | if (startswith (name, mips_str_fn_stub) |
7746 | || startswith (name, mips_str_call_stub)) | |
14132e89 MR |
7747 | { |
7748 | if (pc == start_addr) | |
7749 | /* This is the 'call' part of a call stub. Call this helper | |
7750 | to scan through this code for interesting instructions | |
7751 | and determine the final PC. */ | |
7752 | return mips_get_mips16_fn_stub_pc (frame, pc); | |
7753 | else | |
7754 | /* This is the 'return' part of a call stub. The return address | |
7755 | is in $18. */ | |
7756 | return get_frame_register_signed | |
7757 | (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); | |
c906108c | 7758 | } |
14132e89 MR |
7759 | |
7760 | return 0; /* Not a stub. */ | |
7761 | } | |
7762 | ||
7763 | /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). | |
7764 | This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ | |
7765 | ||
7766 | static int | |
7767 | mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) | |
7768 | { | |
7769 | CORE_ADDR start_addr; | |
7770 | size_t prefixlen; | |
7771 | ||
7772 | /* Find the starting address of the function containing the PC. */ | |
7773 | if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) | |
7774 | return 0; | |
7775 | ||
7776 | /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at | |
7777 | the start, i.e. after the JALR instruction, this is effectively | |
7778 | a return stub. */ | |
7779 | prefixlen = strlen (mips_str_mips16_call_stub); | |
7780 | if (pc != start_addr | |
7781 | && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 | |
7782 | && mips_is_stub_mode (name + prefixlen) | |
7783 | && name[prefixlen + 2] == '_' | |
7784 | && mips_is_stub_suffix (name + prefixlen + 3, 1)) | |
7785 | return 1; | |
7786 | ||
7787 | /* If the PC is in __call_stub_fp_* but not at the start, i.e. after | |
7788 | the JAL or JALR instruction, this is effectively a return stub. */ | |
7789 | prefixlen = strlen (mips_str_call_fp_stub); | |
7790 | if (pc != start_addr | |
7791 | && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) | |
7792 | return 1; | |
7793 | ||
7794 | /* Consume the .pic. prefix of any PIC stub, this function must return | |
7795 | true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub | |
7796 | or the call stub path will trigger in handle_inferior_event causing | |
7797 | it to go astray. */ | |
7798 | prefixlen = strlen (mips_str_pic); | |
7799 | if (strncmp (name, mips_str_pic, prefixlen) == 0) | |
7800 | name += prefixlen; | |
7801 | ||
7802 | /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ | |
7803 | prefixlen = strlen (mips_str_mips16_ret_stub); | |
7804 | if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 | |
7805 | && mips_is_stub_mode (name + prefixlen) | |
7806 | && name[prefixlen + 2] == '\0') | |
7807 | return 1; | |
7808 | ||
7809 | return 0; /* Not a stub. */ | |
c906108c SS |
7810 | } |
7811 | ||
db5f024e DJ |
7812 | /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
7813 | PC of the stub target. The stub just loads $t9 and jumps to it, | |
7814 | so that $t9 has the correct value at function entry. */ | |
7815 | ||
7816 | static CORE_ADDR | |
bd2b40ac | 7817 | mips_skip_pic_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) |
db5f024e | 7818 | { |
e17a4113 UW |
7819 | struct gdbarch *gdbarch = get_frame_arch (frame); |
7820 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
7cbd4a93 | 7821 | struct bound_minimal_symbol msym; |
db5f024e DJ |
7822 | int i; |
7823 | gdb_byte stub_code[16]; | |
7824 | int32_t stub_words[4]; | |
7825 | ||
7826 | /* The stub for foo is named ".pic.foo", and is either two | |
7827 | instructions inserted before foo or a three instruction sequence | |
7828 | which jumps to foo. */ | |
7829 | msym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 7830 | if (msym.minsym == NULL |
4aeddc50 | 7831 | || msym.value_address () != pc |
c9d95fa3 CB |
7832 | || msym.minsym->linkage_name () == NULL |
7833 | || !startswith (msym.minsym->linkage_name (), ".pic.")) | |
db5f024e DJ |
7834 | return 0; |
7835 | ||
7836 | /* A two-instruction header. */ | |
5bbfd12d | 7837 | if (msym.minsym->size () == 8) |
db5f024e DJ |
7838 | return pc + 8; |
7839 | ||
7840 | /* A three-instruction (plus delay slot) trampoline. */ | |
5bbfd12d | 7841 | if (msym.minsym->size () == 16) |
db5f024e DJ |
7842 | { |
7843 | if (target_read_memory (pc, stub_code, 16) != 0) | |
7844 | return 0; | |
7845 | for (i = 0; i < 4; i++) | |
e17a4113 UW |
7846 | stub_words[i] = extract_unsigned_integer (stub_code + i * 4, |
7847 | 4, byte_order); | |
db5f024e DJ |
7848 | |
7849 | /* A stub contains these instructions: | |
7850 | lui t9, %hi(target) | |
7851 | j target | |
7852 | addiu t9, t9, %lo(target) | |
7853 | nop | |
7854 | ||
7855 | This works even for N64, since stubs are only generated with | |
7856 | -msym32. */ | |
7857 | if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | |
7858 | && (stub_words[1] & 0xfc000000U) == 0x08000000 | |
7859 | && (stub_words[2] & 0xffff0000U) == 0x27390000 | |
7860 | && stub_words[3] == 0x00000000) | |
34b192ce MR |
7861 | return ((((stub_words[0] & 0x0000ffff) << 16) |
7862 | + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; | |
db5f024e DJ |
7863 | } |
7864 | ||
7865 | /* Not a recognized stub. */ | |
7866 | return 0; | |
7867 | } | |
7868 | ||
7869 | static CORE_ADDR | |
bd2b40ac | 7870 | mips_skip_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) |
db5f024e | 7871 | { |
14132e89 | 7872 | CORE_ADDR requested_pc = pc; |
db5f024e | 7873 | CORE_ADDR target_pc; |
14132e89 MR |
7874 | CORE_ADDR new_pc; |
7875 | ||
7876 | do | |
7877 | { | |
7878 | target_pc = pc; | |
db5f024e | 7879 | |
14132e89 MR |
7880 | new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
7881 | if (new_pc) | |
3e29f34a | 7882 | pc = new_pc; |
db5f024e | 7883 | |
14132e89 MR |
7884 | new_pc = find_solib_trampoline_target (frame, pc); |
7885 | if (new_pc) | |
3e29f34a | 7886 | pc = new_pc; |
db5f024e | 7887 | |
14132e89 MR |
7888 | new_pc = mips_skip_pic_trampoline_code (frame, pc); |
7889 | if (new_pc) | |
3e29f34a | 7890 | pc = new_pc; |
14132e89 MR |
7891 | } |
7892 | while (pc != target_pc); | |
db5f024e | 7893 | |
14132e89 | 7894 | return pc != requested_pc ? pc : 0; |
db5f024e DJ |
7895 | } |
7896 | ||
a4b8ebc8 | 7897 | /* Convert a dbx stab register number (from `r' declaration) to a GDB |
f57d151a | 7898 | [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7899 | |
7900 | static int | |
d3f73121 | 7901 | mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7902 | { |
a4b8ebc8 | 7903 | int regnum; |
2f38ef89 | 7904 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7905 | regnum = num; |
2f38ef89 | 7906 | else if (num >= 38 && num < 70) |
d3f73121 | 7907 | regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
040b99fd | 7908 | else if (num == 70) |
d3f73121 | 7909 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7910 | else if (num == 71) |
d3f73121 | 7911 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7912 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
7913 | regnum = num + mips_regnum (gdbarch)->dspacc - 72; | |
2f38ef89 | 7914 | else |
0fde2c53 | 7915 | return -1; |
d3f73121 | 7916 | return gdbarch_num_regs (gdbarch) + regnum; |
88c72b7d AC |
7917 | } |
7918 | ||
2f38ef89 | 7919 | |
a4b8ebc8 | 7920 | /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
f57d151a | 7921 | gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
88c72b7d AC |
7922 | |
7923 | static int | |
d3f73121 | 7924 | mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
88c72b7d | 7925 | { |
a4b8ebc8 | 7926 | int regnum; |
2f38ef89 | 7927 | if (num >= 0 && num < 32) |
a4b8ebc8 | 7928 | regnum = num; |
2f38ef89 | 7929 | else if (num >= 32 && num < 64) |
d3f73121 | 7930 | regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
040b99fd | 7931 | else if (num == 64) |
d3f73121 | 7932 | regnum = mips_regnum (gdbarch)->hi; |
040b99fd | 7933 | else if (num == 65) |
d3f73121 | 7934 | regnum = mips_regnum (gdbarch)->lo; |
1faeff08 MR |
7935 | else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
7936 | regnum = num + mips_regnum (gdbarch)->dspacc - 66; | |
2f38ef89 | 7937 | else |
0fde2c53 | 7938 | return -1; |
d3f73121 | 7939 | return gdbarch_num_regs (gdbarch) + regnum; |
a4b8ebc8 AC |
7940 | } |
7941 | ||
7942 | static int | |
e7faf938 | 7943 | mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
a4b8ebc8 AC |
7944 | { |
7945 | /* Only makes sense to supply raw registers. */ | |
e7faf938 | 7946 | gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); |
a4b8ebc8 AC |
7947 | /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to |
7948 | decide if it is valid. Should instead define a standard sim/gdb | |
7949 | register numbering scheme. */ | |
e7faf938 | 7950 | if (gdbarch_register_name (gdbarch, |
637b2f86 | 7951 | gdbarch_num_regs (gdbarch) + regnum)[0] != '\0') |
a4b8ebc8 AC |
7952 | return regnum; |
7953 | else | |
6d82d43b | 7954 | return LEGACY_SIM_REGNO_IGNORE; |
88c72b7d AC |
7955 | } |
7956 | ||
2f38ef89 | 7957 | |
4844f454 CV |
7958 | /* Convert an integer into an address. Extracting the value signed |
7959 | guarantees a correctly sign extended address. */ | |
fc0c74b1 AC |
7960 | |
7961 | static CORE_ADDR | |
79dd2d24 | 7962 | mips_integer_to_address (struct gdbarch *gdbarch, |
870cd05e | 7963 | struct type *type, const gdb_byte *buf) |
fc0c74b1 | 7964 | { |
e17a4113 | 7965 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
df86565b | 7966 | return extract_signed_integer (buf, type->length (), byte_order); |
fc0c74b1 AC |
7967 | } |
7968 | ||
82e91389 DJ |
7969 | /* Dummy virtual frame pointer method. This is no more or less accurate |
7970 | than most other architectures; we just need to be explicit about it, | |
7971 | because the pseudo-register gdbarch_sp_regnum will otherwise lead to | |
7972 | an assertion failure. */ | |
7973 | ||
7974 | static void | |
a54fba4c MD |
7975 | mips_virtual_frame_pointer (struct gdbarch *gdbarch, |
7976 | CORE_ADDR pc, int *reg, LONGEST *offset) | |
82e91389 DJ |
7977 | { |
7978 | *reg = MIPS_SP_REGNUM; | |
7979 | *offset = 0; | |
7980 | } | |
7981 | ||
caaa3122 DJ |
7982 | static void |
7983 | mips_find_abi_section (bfd *abfd, asection *sect, void *obj) | |
7984 | { | |
7985 | enum mips_abi *abip = (enum mips_abi *) obj; | |
fd361982 | 7986 | const char *name = bfd_section_name (sect); |
caaa3122 DJ |
7987 | |
7988 | if (*abip != MIPS_ABI_UNKNOWN) | |
7989 | return; | |
7990 | ||
61012eef | 7991 | if (!startswith (name, ".mdebug.")) |
caaa3122 DJ |
7992 | return; |
7993 | ||
7994 | if (strcmp (name, ".mdebug.abi32") == 0) | |
7995 | *abip = MIPS_ABI_O32; | |
7996 | else if (strcmp (name, ".mdebug.abiN32") == 0) | |
7997 | *abip = MIPS_ABI_N32; | |
62a49b2c | 7998 | else if (strcmp (name, ".mdebug.abi64") == 0) |
e3bddbfa | 7999 | *abip = MIPS_ABI_N64; |
caaa3122 DJ |
8000 | else if (strcmp (name, ".mdebug.abiO64") == 0) |
8001 | *abip = MIPS_ABI_O64; | |
8002 | else if (strcmp (name, ".mdebug.eabi32") == 0) | |
8003 | *abip = MIPS_ABI_EABI32; | |
8004 | else if (strcmp (name, ".mdebug.eabi64") == 0) | |
8005 | *abip = MIPS_ABI_EABI64; | |
8006 | else | |
8a3fe4f8 | 8007 | warning (_("unsupported ABI %s."), name + 8); |
caaa3122 DJ |
8008 | } |
8009 | ||
22e47e37 FF |
8010 | static void |
8011 | mips_find_long_section (bfd *abfd, asection *sect, void *obj) | |
8012 | { | |
8013 | int *lbp = (int *) obj; | |
fd361982 | 8014 | const char *name = bfd_section_name (sect); |
22e47e37 | 8015 | |
61012eef | 8016 | if (startswith (name, ".gcc_compiled_long32")) |
22e47e37 | 8017 | *lbp = 32; |
61012eef | 8018 | else if (startswith (name, ".gcc_compiled_long64")) |
22e47e37 | 8019 | *lbp = 64; |
61012eef | 8020 | else if (startswith (name, ".gcc_compiled_long")) |
22e47e37 FF |
8021 | warning (_("unrecognized .gcc_compiled_longXX")); |
8022 | } | |
8023 | ||
2e4ebe70 DJ |
8024 | static enum mips_abi |
8025 | global_mips_abi (void) | |
8026 | { | |
8027 | int i; | |
8028 | ||
8029 | for (i = 0; mips_abi_strings[i] != NULL; i++) | |
8030 | if (mips_abi_strings[i] == mips_abi_string) | |
8031 | return (enum mips_abi) i; | |
8032 | ||
f34652de | 8033 | internal_error (_("unknown ABI string")); |
2e4ebe70 DJ |
8034 | } |
8035 | ||
4cc0665f MR |
8036 | /* Return the default compressed instruction set, either of MIPS16 |
8037 | or microMIPS, selected when none could have been determined from | |
8038 | the ELF header of the binary being executed (or no binary has been | |
8039 | selected. */ | |
8040 | ||
8041 | static enum mips_isa | |
8042 | global_mips_compression (void) | |
8043 | { | |
8044 | int i; | |
8045 | ||
8046 | for (i = 0; mips_compression_strings[i] != NULL; i++) | |
8047 | if (mips_compression_strings[i] == mips_compression_string) | |
8048 | return (enum mips_isa) i; | |
8049 | ||
f34652de | 8050 | internal_error (_("unknown compressed ISA string")); |
4cc0665f MR |
8051 | } |
8052 | ||
29709017 DJ |
8053 | static void |
8054 | mips_register_g_packet_guesses (struct gdbarch *gdbarch) | |
8055 | { | |
29709017 DJ |
8056 | /* If the size matches the set of 32-bit or 64-bit integer registers, |
8057 | assume that's what we've got. */ | |
4eb0ad19 DJ |
8058 | register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
8059 | register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8060 | |
8061 | /* If the size matches the full set of registers GDB traditionally | |
8062 | knows about, including floating point, for either 32-bit or | |
8063 | 64-bit, assume that's what we've got. */ | |
4eb0ad19 DJ |
8064 | register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); |
8065 | register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); | |
29709017 DJ |
8066 | |
8067 | /* Otherwise we don't have a useful guess. */ | |
8068 | } | |
8069 | ||
f8b73d13 | 8070 | static struct value * |
bd2b40ac | 8071 | value_of_mips_user_reg (frame_info_ptr frame, const void *baton) |
f8b73d13 | 8072 | { |
19ba03f4 | 8073 | const int *reg_p = (const int *) baton; |
f8b73d13 DJ |
8074 | return value_of_register (*reg_p, frame); |
8075 | } | |
8076 | ||
c2d11a7d | 8077 | static struct gdbarch * |
6d82d43b | 8078 | mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
c2d11a7d | 8079 | { |
c2d11a7d | 8080 | int elf_flags; |
2e4ebe70 | 8081 | enum mips_abi mips_abi, found_abi, wanted_abi; |
f8b73d13 | 8082 | int i, num_regs; |
8d5838b5 | 8083 | enum mips_fpu_type fpu_type; |
c1e1314d | 8084 | tdesc_arch_data_up tdesc_data; |
d929bc19 | 8085 | int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; |
27087b7f | 8086 | const char * const *reg_names; |
1faeff08 | 8087 | struct mips_regnum mips_regnum, *regnum; |
4cc0665f | 8088 | enum mips_isa mips_isa; |
1faeff08 MR |
8089 | int dspacc; |
8090 | int dspctl; | |
8091 | ||
ec03c1ac AC |
8092 | /* First of all, extract the elf_flags, if available. */ |
8093 | if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8094 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
6214a8a1 | 8095 | else if (arches != NULL) |
345bd07c SM |
8096 | { |
8097 | mips_gdbarch_tdep *tdep | |
08106042 | 8098 | = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch); |
345bd07c SM |
8099 | elf_flags = tdep->elf_flags; |
8100 | } | |
ec03c1ac AC |
8101 | else |
8102 | elf_flags = 0; | |
8103 | if (gdbarch_debug) | |
6cb06a8c TT |
8104 | gdb_printf (gdb_stdlog, |
8105 | "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); | |
c2d11a7d | 8106 | |
102182a9 | 8107 | /* Check ELF_FLAGS to see if it specifies the ABI being used. */ |
0dadbba0 AC |
8108 | switch ((elf_flags & EF_MIPS_ABI)) |
8109 | { | |
8110 | case E_MIPS_ABI_O32: | |
ec03c1ac | 8111 | found_abi = MIPS_ABI_O32; |
0dadbba0 AC |
8112 | break; |
8113 | case E_MIPS_ABI_O64: | |
ec03c1ac | 8114 | found_abi = MIPS_ABI_O64; |
0dadbba0 AC |
8115 | break; |
8116 | case E_MIPS_ABI_EABI32: | |
ec03c1ac | 8117 | found_abi = MIPS_ABI_EABI32; |
0dadbba0 AC |
8118 | break; |
8119 | case E_MIPS_ABI_EABI64: | |
ec03c1ac | 8120 | found_abi = MIPS_ABI_EABI64; |
0dadbba0 AC |
8121 | break; |
8122 | default: | |
acdb74a0 | 8123 | if ((elf_flags & EF_MIPS_ABI2)) |
ec03c1ac | 8124 | found_abi = MIPS_ABI_N32; |
acdb74a0 | 8125 | else |
ec03c1ac | 8126 | found_abi = MIPS_ABI_UNKNOWN; |
0dadbba0 AC |
8127 | break; |
8128 | } | |
acdb74a0 | 8129 | |
caaa3122 | 8130 | /* GCC creates a pseudo-section whose name describes the ABI. */ |
ec03c1ac AC |
8131 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) |
8132 | bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); | |
caaa3122 | 8133 | |
dc305454 | 8134 | /* If we have no useful BFD information, use the ABI from the last |
ec03c1ac AC |
8135 | MIPS architecture (if there is one). */ |
8136 | if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) | |
345bd07c SM |
8137 | { |
8138 | mips_gdbarch_tdep *tdep | |
08106042 | 8139 | = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch); |
345bd07c SM |
8140 | found_abi = tdep->found_abi; |
8141 | } | |
2e4ebe70 | 8142 | |
32a6503c | 8143 | /* Try the architecture for any hint of the correct ABI. */ |
ec03c1ac | 8144 | if (found_abi == MIPS_ABI_UNKNOWN |
bf64bfd6 AC |
8145 | && info.bfd_arch_info != NULL |
8146 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8147 | { | |
8148 | switch (info.bfd_arch_info->mach) | |
8149 | { | |
8150 | case bfd_mach_mips3900: | |
ec03c1ac | 8151 | found_abi = MIPS_ABI_EABI32; |
bf64bfd6 AC |
8152 | break; |
8153 | case bfd_mach_mips4100: | |
8154 | case bfd_mach_mips5000: | |
ec03c1ac | 8155 | found_abi = MIPS_ABI_EABI64; |
bf64bfd6 | 8156 | break; |
1d06468c EZ |
8157 | case bfd_mach_mips8000: |
8158 | case bfd_mach_mips10000: | |
32a6503c KB |
8159 | /* On Irix, ELF64 executables use the N64 ABI. The |
8160 | pseudo-sections which describe the ABI aren't present | |
8161 | on IRIX. (Even for executables created by gcc.) */ | |
e6c2f47b PA |
8162 | if (info.abfd != NULL |
8163 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
28d169de | 8164 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) |
ec03c1ac | 8165 | found_abi = MIPS_ABI_N64; |
28d169de | 8166 | else |
ec03c1ac | 8167 | found_abi = MIPS_ABI_N32; |
1d06468c | 8168 | break; |
bf64bfd6 AC |
8169 | } |
8170 | } | |
2e4ebe70 | 8171 | |
26c53e50 DJ |
8172 | /* Default 64-bit objects to N64 instead of O32. */ |
8173 | if (found_abi == MIPS_ABI_UNKNOWN | |
8174 | && info.abfd != NULL | |
8175 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour | |
8176 | && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) | |
8177 | found_abi = MIPS_ABI_N64; | |
8178 | ||
ec03c1ac | 8179 | if (gdbarch_debug) |
6cb06a8c TT |
8180 | gdb_printf (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", |
8181 | found_abi); | |
ec03c1ac AC |
8182 | |
8183 | /* What has the user specified from the command line? */ | |
8184 | wanted_abi = global_mips_abi (); | |
8185 | if (gdbarch_debug) | |
6cb06a8c TT |
8186 | gdb_printf (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", |
8187 | wanted_abi); | |
2e4ebe70 DJ |
8188 | |
8189 | /* Now that we have found what the ABI for this binary would be, | |
8190 | check whether the user is overriding it. */ | |
2e4ebe70 DJ |
8191 | if (wanted_abi != MIPS_ABI_UNKNOWN) |
8192 | mips_abi = wanted_abi; | |
ec03c1ac AC |
8193 | else if (found_abi != MIPS_ABI_UNKNOWN) |
8194 | mips_abi = found_abi; | |
8195 | else | |
8196 | mips_abi = MIPS_ABI_O32; | |
8197 | if (gdbarch_debug) | |
6cb06a8c TT |
8198 | gdb_printf (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", |
8199 | mips_abi); | |
2e4ebe70 | 8200 | |
c5196c92 MR |
8201 | /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */ |
8202 | if (mips_abi != MIPS_ABI_EABI32 | |
8203 | && mips_abi != MIPS_ABI_O32 | |
8204 | && info.bfd_arch_info != NULL | |
8205 | && info.bfd_arch_info->arch == bfd_arch_mips | |
8206 | && info.bfd_arch_info->bits_per_word < 64) | |
8207 | info.bfd_arch_info = bfd_lookup_arch (bfd_arch_mips, bfd_mach_mips4000); | |
8208 | ||
4cc0665f MR |
8209 | /* Determine the default compressed ISA. */ |
8210 | if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 | |
8211 | && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) | |
8212 | mips_isa = ISA_MICROMIPS; | |
8213 | else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 | |
8214 | && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) | |
8215 | mips_isa = ISA_MIPS16; | |
8216 | else | |
8217 | mips_isa = global_mips_compression (); | |
8218 | mips_compression_string = mips_compression_strings[mips_isa]; | |
8219 | ||
ec03c1ac | 8220 | /* Also used when doing an architecture lookup. */ |
4b9b3959 | 8221 | if (gdbarch_debug) |
6cb06a8c TT |
8222 | gdb_printf (gdb_stdlog, |
8223 | "mips_gdbarch_init: " | |
8224 | "mips64_transfers_32bit_regs_p = %d\n", | |
8225 | mips64_transfers_32bit_regs_p); | |
0dadbba0 | 8226 | |
8d5838b5 | 8227 | /* Determine the MIPS FPU type. */ |
609ca2b9 DJ |
8228 | #ifdef HAVE_ELF |
8229 | if (info.abfd | |
8230 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
8231 | elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, | |
8232 | Tag_GNU_MIPS_ABI_FP); | |
8233 | #endif /* HAVE_ELF */ | |
8234 | ||
8d5838b5 AC |
8235 | if (!mips_fpu_type_auto) |
8236 | fpu_type = mips_fpu_type; | |
d929bc19 | 8237 | else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) |
609ca2b9 DJ |
8238 | { |
8239 | switch (elf_fpu_type) | |
8240 | { | |
d929bc19 | 8241 | case Val_GNU_MIPS_ABI_FP_DOUBLE: |
609ca2b9 DJ |
8242 | fpu_type = MIPS_FPU_DOUBLE; |
8243 | break; | |
d929bc19 | 8244 | case Val_GNU_MIPS_ABI_FP_SINGLE: |
609ca2b9 DJ |
8245 | fpu_type = MIPS_FPU_SINGLE; |
8246 | break; | |
d929bc19 | 8247 | case Val_GNU_MIPS_ABI_FP_SOFT: |
609ca2b9 DJ |
8248 | default: |
8249 | /* Soft float or unknown. */ | |
8250 | fpu_type = MIPS_FPU_NONE; | |
8251 | break; | |
8252 | } | |
8253 | } | |
8d5838b5 AC |
8254 | else if (info.bfd_arch_info != NULL |
8255 | && info.bfd_arch_info->arch == bfd_arch_mips) | |
8256 | switch (info.bfd_arch_info->mach) | |
8257 | { | |
8258 | case bfd_mach_mips3900: | |
8259 | case bfd_mach_mips4100: | |
8260 | case bfd_mach_mips4111: | |
a9d61c86 | 8261 | case bfd_mach_mips4120: |
8d5838b5 AC |
8262 | fpu_type = MIPS_FPU_NONE; |
8263 | break; | |
8264 | case bfd_mach_mips4650: | |
8265 | fpu_type = MIPS_FPU_SINGLE; | |
8266 | break; | |
8267 | default: | |
8268 | fpu_type = MIPS_FPU_DOUBLE; | |
8269 | break; | |
8270 | } | |
8271 | else if (arches != NULL) | |
345bd07c | 8272 | fpu_type = mips_get_fpu_type (arches->gdbarch); |
8d5838b5 AC |
8273 | else |
8274 | fpu_type = MIPS_FPU_DOUBLE; | |
8275 | if (gdbarch_debug) | |
6cb06a8c TT |
8276 | gdb_printf (gdb_stdlog, |
8277 | "mips_gdbarch_init: fpu_type = %d\n", fpu_type); | |
8d5838b5 | 8278 | |
29709017 DJ |
8279 | /* Check for blatant incompatibilities. */ |
8280 | ||
8281 | /* If we have only 32-bit registers, then we can't debug a 64-bit | |
8282 | ABI. */ | |
8283 | if (info.target_desc | |
8284 | && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL | |
8285 | && mips_abi != MIPS_ABI_EABI32 | |
8286 | && mips_abi != MIPS_ABI_O32) | |
37c33887 MR |
8287 | return NULL; |
8288 | ||
8289 | /* Fill in the OS dependent register numbers and names. */ | |
8290 | if (info.osabi == GDB_OSABI_LINUX) | |
f8b73d13 | 8291 | { |
37c33887 MR |
8292 | mips_regnum.fp0 = 38; |
8293 | mips_regnum.pc = 37; | |
8294 | mips_regnum.cause = 36; | |
8295 | mips_regnum.badvaddr = 35; | |
8296 | mips_regnum.hi = 34; | |
8297 | mips_regnum.lo = 33; | |
8298 | mips_regnum.fp_control_status = 70; | |
8299 | mips_regnum.fp_implementation_revision = 71; | |
8300 | mips_regnum.dspacc = -1; | |
8301 | mips_regnum.dspctl = -1; | |
8302 | dspacc = 72; | |
8303 | dspctl = 78; | |
8304 | num_regs = 90; | |
8305 | reg_names = mips_linux_reg_names; | |
8306 | } | |
8307 | else | |
8308 | { | |
8309 | mips_regnum.lo = MIPS_EMBED_LO_REGNUM; | |
8310 | mips_regnum.hi = MIPS_EMBED_HI_REGNUM; | |
8311 | mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
8312 | mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; | |
8313 | mips_regnum.pc = MIPS_EMBED_PC_REGNUM; | |
8314 | mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; | |
8315 | mips_regnum.fp_control_status = 70; | |
8316 | mips_regnum.fp_implementation_revision = 71; | |
8317 | mips_regnum.dspacc = dspacc = -1; | |
8318 | mips_regnum.dspctl = dspctl = -1; | |
8319 | num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
8320 | if (info.bfd_arch_info != NULL | |
dda83cd7 SM |
8321 | && info.bfd_arch_info->mach == bfd_mach_mips3900) |
8322 | reg_names = mips_tx39_reg_names; | |
37c33887 | 8323 | else |
dda83cd7 | 8324 | reg_names = mips_generic_reg_names; |
37c33887 MR |
8325 | } |
8326 | ||
8327 | /* Check any target description for validity. */ | |
8328 | if (tdesc_has_registers (info.target_desc)) | |
8329 | { | |
8330 | static const char *const mips_gprs[] = { | |
8331 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
8332 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
8333 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
8334 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | |
8335 | }; | |
8336 | static const char *const mips_fprs[] = { | |
8337 | "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | |
8338 | "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | |
8339 | "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | |
8340 | "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | |
8341 | }; | |
8342 | ||
8343 | const struct tdesc_feature *feature; | |
8344 | int valid_p; | |
8345 | ||
8346 | feature = tdesc_find_feature (info.target_desc, | |
8347 | "org.gnu.gdb.mips.cpu"); | |
8348 | if (feature == NULL) | |
8349 | return NULL; | |
8350 | ||
8351 | tdesc_data = tdesc_data_alloc (); | |
8352 | ||
8353 | valid_p = 1; | |
8354 | for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | |
c1e1314d | 8355 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
37c33887 MR |
8356 | mips_gprs[i]); |
8357 | ||
8358 | ||
c1e1314d | 8359 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8360 | mips_regnum.lo, "lo"); |
c1e1314d | 8361 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8362 | mips_regnum.hi, "hi"); |
c1e1314d | 8363 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8364 | mips_regnum.pc, "pc"); |
8365 | ||
8366 | if (!valid_p) | |
c1e1314d | 8367 | return NULL; |
37c33887 MR |
8368 | |
8369 | feature = tdesc_find_feature (info.target_desc, | |
8370 | "org.gnu.gdb.mips.cp0"); | |
8371 | if (feature == NULL) | |
c1e1314d | 8372 | return NULL; |
37c33887 MR |
8373 | |
8374 | valid_p = 1; | |
c1e1314d | 8375 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8376 | mips_regnum.badvaddr, "badvaddr"); |
c1e1314d | 8377 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8378 | MIPS_PS_REGNUM, "status"); |
c1e1314d | 8379 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8380 | mips_regnum.cause, "cause"); |
8381 | ||
8382 | if (!valid_p) | |
c1e1314d | 8383 | return NULL; |
37c33887 MR |
8384 | |
8385 | /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | |
8386 | backend is not prepared for that, though. */ | |
8387 | feature = tdesc_find_feature (info.target_desc, | |
8388 | "org.gnu.gdb.mips.fpu"); | |
8389 | if (feature == NULL) | |
c1e1314d | 8390 | return NULL; |
37c33887 MR |
8391 | |
8392 | valid_p = 1; | |
8393 | for (i = 0; i < 32; i++) | |
c1e1314d | 8394 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8395 | i + mips_regnum.fp0, mips_fprs[i]); |
8396 | ||
c1e1314d | 8397 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8398 | mips_regnum.fp_control_status, |
8399 | "fcsr"); | |
8400 | valid_p | |
c1e1314d | 8401 | &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8402 | mips_regnum.fp_implementation_revision, |
8403 | "fir"); | |
8404 | ||
8405 | if (!valid_p) | |
c1e1314d | 8406 | return NULL; |
37c33887 MR |
8407 | |
8408 | num_regs = mips_regnum.fp_implementation_revision + 1; | |
8409 | ||
8410 | if (dspacc >= 0) | |
8411 | { | |
8412 | feature = tdesc_find_feature (info.target_desc, | |
8413 | "org.gnu.gdb.mips.dsp"); | |
8414 | /* The DSP registers are optional; it's OK if they are absent. */ | |
8415 | if (feature != NULL) | |
8416 | { | |
8417 | i = 0; | |
8418 | valid_p = 1; | |
c1e1314d | 8419 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8420 | dspacc + i++, "hi1"); |
c1e1314d | 8421 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8422 | dspacc + i++, "lo1"); |
c1e1314d | 8423 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8424 | dspacc + i++, "hi2"); |
c1e1314d | 8425 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8426 | dspacc + i++, "lo2"); |
c1e1314d | 8427 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 | 8428 | dspacc + i++, "hi3"); |
c1e1314d | 8429 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8430 | dspacc + i++, "lo3"); |
8431 | ||
c1e1314d | 8432 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
37c33887 MR |
8433 | dspctl, "dspctl"); |
8434 | ||
8435 | if (!valid_p) | |
c1e1314d | 8436 | return NULL; |
37c33887 MR |
8437 | |
8438 | mips_regnum.dspacc = dspacc; | |
8439 | mips_regnum.dspctl = dspctl; | |
8440 | ||
8441 | num_regs = mips_regnum.dspctl + 1; | |
8442 | } | |
8443 | } | |
8444 | ||
8445 | /* It would be nice to detect an attempt to use a 64-bit ABI | |
8446 | when only 32-bit registers are provided. */ | |
8447 | reg_names = NULL; | |
f8b73d13 | 8448 | } |
29709017 | 8449 | |
025bb325 | 8450 | /* Try to find a pre-existing architecture. */ |
c2d11a7d JM |
8451 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
8452 | arches != NULL; | |
8453 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
8454 | { | |
345bd07c | 8455 | mips_gdbarch_tdep *tdep |
08106042 | 8456 | = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch); |
345bd07c | 8457 | |
d54398a7 | 8458 | /* MIPS needs to be pedantic about which ABI and the compressed |
dda83cd7 | 8459 | ISA variation the object is using. */ |
345bd07c | 8460 | if (tdep->elf_flags != elf_flags) |
c2d11a7d | 8461 | continue; |
345bd07c | 8462 | if (tdep->mips_abi != mips_abi) |
0dadbba0 | 8463 | continue; |
345bd07c | 8464 | if (tdep->mips_isa != mips_isa) |
d54398a7 | 8465 | continue; |
719ec221 | 8466 | /* Need to be pedantic about which register virtual size is |
dda83cd7 | 8467 | used. */ |
345bd07c | 8468 | if (tdep->mips64_transfers_32bit_regs_p |
719ec221 AC |
8469 | != mips64_transfers_32bit_regs_p) |
8470 | continue; | |
8d5838b5 | 8471 | /* Be pedantic about which FPU is selected. */ |
345bd07c | 8472 | if (mips_get_fpu_type (arches->gdbarch) != fpu_type) |
8d5838b5 | 8473 | continue; |
f8b73d13 | 8474 | |
4be87837 | 8475 | return arches->gdbarch; |
c2d11a7d JM |
8476 | } |
8477 | ||
102182a9 | 8478 | /* Need a new architecture. Fill in a target specific vector. */ |
2b16913c SM |
8479 | gdbarch *gdbarch |
8480 | = gdbarch_alloc (&info, gdbarch_tdep_up (new mips_gdbarch_tdep)); | |
8481 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); | |
8482 | ||
c2d11a7d | 8483 | tdep->elf_flags = elf_flags; |
719ec221 | 8484 | tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
ec03c1ac AC |
8485 | tdep->found_abi = found_abi; |
8486 | tdep->mips_abi = mips_abi; | |
4cc0665f | 8487 | tdep->mips_isa = mips_isa; |
8d5838b5 | 8488 | tdep->mips_fpu_type = fpu_type; |
29709017 DJ |
8489 | tdep->register_size_valid_p = 0; |
8490 | tdep->register_size = 0; | |
8491 | ||
8492 | if (info.target_desc) | |
8493 | { | |
8494 | /* Some useful properties can be inferred from the target. */ | |
8495 | if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) | |
8496 | { | |
8497 | tdep->register_size_valid_p = 1; | |
8498 | tdep->register_size = 4; | |
8499 | } | |
8500 | else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) | |
8501 | { | |
8502 | tdep->register_size_valid_p = 1; | |
8503 | tdep->register_size = 8; | |
8504 | } | |
8505 | } | |
c2d11a7d | 8506 | |
102182a9 | 8507 | /* Initially set everything according to the default ABI/ISA. */ |
c2d11a7d JM |
8508 | set_gdbarch_short_bit (gdbarch, 16); |
8509 | set_gdbarch_int_bit (gdbarch, 32); | |
8510 | set_gdbarch_float_bit (gdbarch, 32); | |
8511 | set_gdbarch_double_bit (gdbarch, 64); | |
8512 | set_gdbarch_long_double_bit (gdbarch, 64); | |
a4b8ebc8 AC |
8513 | set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); |
8514 | set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); | |
8515 | set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | |
1d06468c | 8516 | |
175ff332 HZ |
8517 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8518 | mips_ax_pseudo_register_collect); | |
8519 | set_gdbarch_ax_pseudo_register_push_stack | |
8520 | (gdbarch, mips_ax_pseudo_register_push_stack); | |
8521 | ||
6d82d43b | 8522 | set_gdbarch_elf_make_msymbol_special (gdbarch, |
f7ab6ec6 | 8523 | mips_elf_make_msymbol_special); |
3e29f34a MR |
8524 | set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special); |
8525 | set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr); | |
8526 | set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line); | |
f7ab6ec6 | 8527 | |
1faeff08 MR |
8528 | regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
8529 | *regnum = mips_regnum; | |
1faeff08 MR |
8530 | set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
8531 | set_gdbarch_num_regs (gdbarch, num_regs); | |
8532 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8533 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
8534 | set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
8535 | tdep->mips_processor_reg_names = reg_names; | |
8536 | tdep->regnum = regnum; | |
fe29b929 | 8537 | |
0dadbba0 | 8538 | switch (mips_abi) |
c2d11a7d | 8539 | { |
0dadbba0 | 8540 | case MIPS_ABI_O32: |
25ab4790 | 8541 | set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
29dfb2ac | 8542 | set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
4c7d22cb | 8543 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8544 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
4014092b | 8545 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8546 | set_gdbarch_long_bit (gdbarch, 32); |
8547 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8548 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8549 | break; | |
0dadbba0 | 8550 | case MIPS_ABI_O64: |
25ab4790 | 8551 | set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); |
9c8fdbfa | 8552 | set_gdbarch_return_value (gdbarch, mips_o64_return_value); |
4c7d22cb | 8553 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
56cea623 | 8554 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
361d1df0 | 8555 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8556 | set_gdbarch_long_bit (gdbarch, 32); |
8557 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8558 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8559 | break; | |
0dadbba0 | 8560 | case MIPS_ABI_EABI32: |
25ab4790 | 8561 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8562 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8563 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8564 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8565 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8566 | set_gdbarch_long_bit (gdbarch, 32); |
8567 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8568 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8569 | break; | |
0dadbba0 | 8570 | case MIPS_ABI_EABI64: |
25ab4790 | 8571 | set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); |
9c8fdbfa | 8572 | set_gdbarch_return_value (gdbarch, mips_eabi_return_value); |
4c7d22cb | 8573 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8574 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8575 | tdep->default_mask_address_p = 0; |
c2d11a7d JM |
8576 | set_gdbarch_long_bit (gdbarch, 64); |
8577 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8578 | set_gdbarch_long_long_bit (gdbarch, 64); | |
8579 | break; | |
0dadbba0 | 8580 | case MIPS_ABI_N32: |
25ab4790 | 8581 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8582 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8583 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8584 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
4014092b | 8585 | tdep->default_mask_address_p = 0; |
0dadbba0 AC |
8586 | set_gdbarch_long_bit (gdbarch, 32); |
8587 | set_gdbarch_ptr_bit (gdbarch, 32); | |
8588 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8589 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8590 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
28d169de KB |
8591 | break; |
8592 | case MIPS_ABI_N64: | |
25ab4790 | 8593 | set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); |
29dfb2ac | 8594 | set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); |
4c7d22cb | 8595 | tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; |
56cea623 | 8596 | tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; |
28d169de KB |
8597 | tdep->default_mask_address_p = 0; |
8598 | set_gdbarch_long_bit (gdbarch, 64); | |
8599 | set_gdbarch_ptr_bit (gdbarch, 64); | |
8600 | set_gdbarch_long_long_bit (gdbarch, 64); | |
fed7ba43 | 8601 | set_gdbarch_long_double_bit (gdbarch, 128); |
b14d30e1 | 8602 | set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); |
0dadbba0 | 8603 | break; |
c2d11a7d | 8604 | default: |
f34652de | 8605 | internal_error (_("unknown ABI in switch")); |
c2d11a7d JM |
8606 | } |
8607 | ||
22e47e37 FF |
8608 | /* GCC creates a pseudo-section whose name specifies the size of |
8609 | longs, since -mlong32 or -mlong64 may be used independent of | |
8610 | other options. How those options affect pointer sizes is ABI and | |
8611 | architecture dependent, so use them to override the default sizes | |
8612 | set by the ABI. This table shows the relationship between ABI, | |
8613 | -mlongXX, and size of pointers: | |
8614 | ||
8615 | ABI -mlongXX ptr bits | |
8616 | --- -------- -------- | |
8617 | o32 32 32 | |
8618 | o32 64 32 | |
8619 | n32 32 32 | |
8620 | n32 64 64 | |
8621 | o64 32 32 | |
8622 | o64 64 64 | |
8623 | n64 32 32 | |
8624 | n64 64 64 | |
8625 | eabi32 32 32 | |
8626 | eabi32 64 32 | |
8627 | eabi64 32 32 | |
8628 | eabi64 64 64 | |
8629 | ||
8630 | Note that for o32 and eabi32, pointers are always 32 bits | |
8631 | regardless of any -mlongXX option. For all others, pointers and | |
025bb325 | 8632 | longs are the same, as set by -mlongXX or set by defaults. */ |
22e47e37 FF |
8633 | |
8634 | if (info.abfd != NULL) | |
8635 | { | |
8636 | int long_bit = 0; | |
8637 | ||
8638 | bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); | |
8639 | if (long_bit) | |
8640 | { | |
8641 | set_gdbarch_long_bit (gdbarch, long_bit); | |
8642 | switch (mips_abi) | |
8643 | { | |
8644 | case MIPS_ABI_O32: | |
8645 | case MIPS_ABI_EABI32: | |
8646 | break; | |
8647 | case MIPS_ABI_N32: | |
8648 | case MIPS_ABI_O64: | |
8649 | case MIPS_ABI_N64: | |
8650 | case MIPS_ABI_EABI64: | |
8651 | set_gdbarch_ptr_bit (gdbarch, long_bit); | |
8652 | break; | |
8653 | default: | |
f34652de | 8654 | internal_error (_("unknown ABI in switch")); |
22e47e37 FF |
8655 | } |
8656 | } | |
8657 | } | |
8658 | ||
a5ea2558 AC |
8659 | /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE |
8660 | that could indicate -gp32 BUT gas/config/tc-mips.c contains the | |
8661 | comment: | |
8662 | ||
8663 | ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE | |
8664 | flag in object files because to do so would make it impossible to | |
102182a9 | 8665 | link with libraries compiled without "-gp32". This is |
a5ea2558 | 8666 | unnecessarily restrictive. |
361d1df0 | 8667 | |
a5ea2558 AC |
8668 | We could solve this problem by adding "-gp32" multilibs to gcc, |
8669 | but to set this flag before gcc is built with such multilibs will | |
8670 | break too many systems.'' | |
8671 | ||
8672 | But even more unhelpfully, the default linker output target for | |
8673 | mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even | |
8674 | for 64-bit programs - you need to change the ABI to change this, | |
102182a9 | 8675 | and not all gcc targets support that currently. Therefore using |
a5ea2558 AC |
8676 | this flag to detect 32-bit mode would do the wrong thing given |
8677 | the current gcc - it would make GDB treat these 64-bit programs | |
102182a9 | 8678 | as 32-bit programs by default. */ |
a5ea2558 | 8679 | |
6c997a34 | 8680 | set_gdbarch_read_pc (gdbarch, mips_read_pc); |
b6cb9035 | 8681 | set_gdbarch_write_pc (gdbarch, mips_write_pc); |
c2d11a7d | 8682 | |
102182a9 MS |
8683 | /* Add/remove bits from an address. The MIPS needs be careful to |
8684 | ensure that all 32 bit addresses are sign extended to 64 bits. */ | |
875e1767 AC |
8685 | set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); |
8686 | ||
58dfe9ff AC |
8687 | /* Unwind the frame. */ |
8688 | set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); | |
30244cd8 | 8689 | set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); |
b8a22b94 | 8690 | set_gdbarch_dummy_id (gdbarch, mips_dummy_id); |
10312cc4 | 8691 | |
102182a9 | 8692 | /* Map debug register numbers onto internal register numbers. */ |
88c72b7d | 8693 | set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6d82d43b AC |
8694 | set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
8695 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
6d82d43b AC |
8696 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
8697 | mips_dwarf_dwarf2_ecoff_reg_to_regnum); | |
a4b8ebc8 | 8698 | set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
88c72b7d | 8699 | |
025bb325 | 8700 | /* MIPS version of CALL_DUMMY. */ |
c2d11a7d | 8701 | |
2c76a0c7 JB |
8702 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8703 | set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); | |
dc604539 | 8704 | set_gdbarch_frame_align (gdbarch, mips_frame_align); |
d05285fa | 8705 | |
1bab7383 YQ |
8706 | set_gdbarch_print_float_info (gdbarch, mips_print_float_info); |
8707 | ||
87783b8b AC |
8708 | set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
8709 | set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | |
8710 | set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | |
8711 | ||
f7b9e9fc | 8712 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
04180708 YQ |
8713 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, mips_breakpoint_kind_from_pc); |
8714 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, mips_sw_breakpoint_from_kind); | |
c8cef75f MR |
8715 | set_gdbarch_adjust_breakpoint_address (gdbarch, |
8716 | mips_adjust_breakpoint_address); | |
f7b9e9fc AC |
8717 | |
8718 | set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | |
f7b9e9fc | 8719 | |
c9cf6e20 | 8720 | set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p); |
97ab0fdd | 8721 | |
fc0c74b1 AC |
8722 | set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
8723 | set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | |
8724 | set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | |
70f80edf | 8725 | |
a4b8ebc8 | 8726 | set_gdbarch_register_type (gdbarch, mips_register_type); |
78fde5f8 | 8727 | |
e11c53d2 | 8728 | set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); |
bf1f5b4c | 8729 | |
471b9d15 MR |
8730 | set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); |
8731 | if (mips_abi == MIPS_ABI_N64) | |
8732 | set_gdbarch_disassembler_options_implicit | |
8733 | (gdbarch, (const char *) mips_disassembler_options_n64); | |
8734 | else if (mips_abi == MIPS_ABI_N32) | |
8735 | set_gdbarch_disassembler_options_implicit | |
8736 | (gdbarch, (const char *) mips_disassembler_options_n32); | |
9dae60cc | 8737 | else |
471b9d15 MR |
8738 | set_gdbarch_disassembler_options_implicit |
8739 | (gdbarch, (const char *) mips_disassembler_options_o32); | |
8740 | set_gdbarch_disassembler_options (gdbarch, &mips_disassembler_options); | |
8741 | set_gdbarch_valid_disassembler_options (gdbarch, | |
8742 | disassembler_options_mips ()); | |
e5ab0dce | 8743 | |
d92524f1 PM |
8744 | /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
8745 | HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | |
3a3bc038 | 8746 | need to all be folded into the target vector. Since they are |
d92524f1 PM |
8747 | being used as guards for target_stopped_by_watchpoint, why not have |
8748 | target_stopped_by_watchpoint return the type of watchpoint that the code | |
3a3bc038 AC |
8749 | is sitting on? */ |
8750 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
8751 | ||
e7d6a6d2 | 8752 | set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
757a7cc6 | 8753 | |
14132e89 MR |
8754 | /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
8755 | to support MIPS16. This is a bad thing. Make sure not to do it | |
8756 | if we have an OS ABI that actually supports shared libraries, since | |
8757 | shared library support is more important. If we have an OS someday | |
8758 | that supports both shared libraries and MIPS16, we'll have to find | |
8759 | a better place for these. | |
8760 | macro/2012-04-25: But that applies to return trampolines only and | |
8761 | currently no MIPS OS ABI uses shared libraries that have them. */ | |
8762 | set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); | |
8763 | ||
025bb325 MS |
8764 | set_gdbarch_single_step_through_delay (gdbarch, |
8765 | mips_single_step_through_delay); | |
3352ef37 | 8766 | |
0d5de010 DJ |
8767 | /* Virtual tables. */ |
8768 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
8769 | ||
29709017 DJ |
8770 | mips_register_g_packet_guesses (gdbarch); |
8771 | ||
6de918a6 | 8772 | /* Hook in OS ABI-specific overrides, if they have been registered. */ |
c1e1314d | 8773 | info.tdesc_data = tdesc_data.get (); |
6de918a6 | 8774 | gdbarch_init_osabi (info, gdbarch); |
757a7cc6 | 8775 | |
9aac7884 MR |
8776 | /* The hook may have adjusted num_regs, fetch the final value and |
8777 | set pc_regnum and sp_regnum now that it has been fixed. */ | |
9aac7884 MR |
8778 | num_regs = gdbarch_num_regs (gdbarch); |
8779 | set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
8780 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8781 | ||
5792a79b | 8782 | /* Unwind the frame. */ |
b8a22b94 DJ |
8783 | dwarf2_append_unwinders (gdbarch); |
8784 | frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | |
8785 | frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | |
4cc0665f | 8786 | frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
b8a22b94 | 8787 | frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
2bd0c3d7 | 8788 | frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
eec63939 | 8789 | frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
45c9dd44 | 8790 | frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
4cc0665f | 8791 | frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
45c9dd44 | 8792 | frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
5792a79b | 8793 | |
c1e1314d | 8794 | if (tdesc_data != nullptr) |
f8b73d13 DJ |
8795 | { |
8796 | set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | |
c1e1314d | 8797 | tdesc_use_registers (gdbarch, info.target_desc, std::move (tdesc_data)); |
f8b73d13 DJ |
8798 | |
8799 | /* Override the normal target description methods to handle our | |
8800 | dual real and pseudo registers. */ | |
8801 | set_gdbarch_register_name (gdbarch, mips_register_name); | |
025bb325 MS |
8802 | set_gdbarch_register_reggroup_p (gdbarch, |
8803 | mips_tdesc_register_reggroup_p); | |
f8b73d13 DJ |
8804 | |
8805 | num_regs = gdbarch_num_regs (gdbarch); | |
8806 | set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
8807 | set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); | |
8808 | set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
8809 | } | |
8810 | ||
8811 | /* Add ABI-specific aliases for the registers. */ | |
8812 | if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) | |
8813 | for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) | |
8814 | user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, | |
8815 | value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); | |
8816 | else | |
8817 | for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) | |
8818 | user_reg_add (gdbarch, mips_o32_aliases[i].name, | |
8819 | value_of_mips_user_reg, &mips_o32_aliases[i].regnum); | |
8820 | ||
8821 | /* Add some other standard aliases. */ | |
8822 | for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) | |
8823 | user_reg_add (gdbarch, mips_register_aliases[i].name, | |
8824 | value_of_mips_user_reg, &mips_register_aliases[i].regnum); | |
8825 | ||
865093a3 AR |
8826 | for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) |
8827 | user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, | |
8828 | value_of_mips_user_reg, | |
8829 | &mips_numeric_register_aliases[i].regnum); | |
8830 | ||
4b9b3959 AC |
8831 | return gdbarch; |
8832 | } | |
8833 | ||
2e4ebe70 | 8834 | static void |
eb4c3f4a TT |
8835 | mips_abi_update (const char *ignore_args, |
8836 | int from_tty, struct cmd_list_element *c) | |
2e4ebe70 DJ |
8837 | { |
8838 | struct gdbarch_info info; | |
8839 | ||
8840 | /* Force the architecture to update, and (if it's a MIPS architecture) | |
8841 | mips_gdbarch_init will take care of the rest. */ | |
2e4ebe70 DJ |
8842 | gdbarch_update_p (info); |
8843 | } | |
8844 | ||
ad188201 KB |
8845 | /* Print out which MIPS ABI is in use. */ |
8846 | ||
8847 | static void | |
1f8ca57c JB |
8848 | show_mips_abi (struct ui_file *file, |
8849 | int from_tty, | |
8850 | struct cmd_list_element *ignored_cmd, | |
8851 | const char *ignored_value) | |
ad188201 | 8852 | { |
f5656ead | 8853 | if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) |
6cb06a8c | 8854 | gdb_printf |
1f8ca57c JB |
8855 | (file, |
8856 | "The MIPS ABI is unknown because the current architecture " | |
8857 | "is not MIPS.\n"); | |
ad188201 KB |
8858 | else |
8859 | { | |
8860 | enum mips_abi global_abi = global_mips_abi (); | |
f5656ead | 8861 | enum mips_abi actual_abi = mips_abi (target_gdbarch ()); |
ad188201 KB |
8862 | const char *actual_abi_str = mips_abi_strings[actual_abi]; |
8863 | ||
8864 | if (global_abi == MIPS_ABI_UNKNOWN) | |
6cb06a8c | 8865 | gdb_printf |
1f8ca57c JB |
8866 | (file, |
8867 | "The MIPS ABI is set automatically (currently \"%s\").\n", | |
6d82d43b | 8868 | actual_abi_str); |
ad188201 | 8869 | else if (global_abi == actual_abi) |
6cb06a8c | 8870 | gdb_printf |
1f8ca57c JB |
8871 | (file, |
8872 | "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", | |
6d82d43b | 8873 | actual_abi_str); |
ad188201 KB |
8874 | else |
8875 | { | |
8876 | /* Probably shouldn't happen... */ | |
6cb06a8c TT |
8877 | gdb_printf (file, |
8878 | "The (auto detected) MIPS ABI \"%s\" is in use " | |
8879 | "even though the user setting was \"%s\".\n", | |
8880 | actual_abi_str, mips_abi_strings[global_abi]); | |
ad188201 KB |
8881 | } |
8882 | } | |
8883 | } | |
8884 | ||
4cc0665f MR |
8885 | /* Print out which MIPS compressed ISA encoding is used. */ |
8886 | ||
8887 | static void | |
8888 | show_mips_compression (struct ui_file *file, int from_tty, | |
8889 | struct cmd_list_element *c, const char *value) | |
8890 | { | |
6cb06a8c TT |
8891 | gdb_printf (file, _("The compressed ISA encoding used is %s.\n"), |
8892 | value); | |
4cc0665f MR |
8893 | } |
8894 | ||
a4f320fd MR |
8895 | /* Return a textual name for MIPS FPU type FPU_TYPE. */ |
8896 | ||
8897 | static const char * | |
8898 | mips_fpu_type_str (enum mips_fpu_type fpu_type) | |
8899 | { | |
8900 | switch (fpu_type) | |
8901 | { | |
8902 | case MIPS_FPU_NONE: | |
8903 | return "none"; | |
8904 | case MIPS_FPU_SINGLE: | |
8905 | return "single"; | |
8906 | case MIPS_FPU_DOUBLE: | |
8907 | return "double"; | |
8908 | default: | |
8909 | return "???"; | |
8910 | } | |
8911 | } | |
8912 | ||
4b9b3959 | 8913 | static void |
72a155b4 | 8914 | mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
4b9b3959 | 8915 | { |
08106042 | 8916 | mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); |
4b9b3959 | 8917 | if (tdep != NULL) |
c2d11a7d | 8918 | { |
acdb74a0 AC |
8919 | int ef_mips_arch; |
8920 | int ef_mips_32bitmode; | |
f49e4e6d | 8921 | /* Determine the ISA. */ |
acdb74a0 AC |
8922 | switch (tdep->elf_flags & EF_MIPS_ARCH) |
8923 | { | |
8924 | case E_MIPS_ARCH_1: | |
8925 | ef_mips_arch = 1; | |
8926 | break; | |
8927 | case E_MIPS_ARCH_2: | |
8928 | ef_mips_arch = 2; | |
8929 | break; | |
8930 | case E_MIPS_ARCH_3: | |
8931 | ef_mips_arch = 3; | |
8932 | break; | |
8933 | case E_MIPS_ARCH_4: | |
93d56215 | 8934 | ef_mips_arch = 4; |
acdb74a0 AC |
8935 | break; |
8936 | default: | |
93d56215 | 8937 | ef_mips_arch = 0; |
acdb74a0 AC |
8938 | break; |
8939 | } | |
f49e4e6d | 8940 | /* Determine the size of a pointer. */ |
acdb74a0 | 8941 | ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); |
6cb06a8c TT |
8942 | gdb_printf (file, |
8943 | "mips_dump_tdep: tdep->elf_flags = 0x%x\n", | |
8944 | tdep->elf_flags); | |
8945 | gdb_printf (file, | |
8946 | "mips_dump_tdep: ef_mips_32bitmode = %d\n", | |
8947 | ef_mips_32bitmode); | |
8948 | gdb_printf (file, | |
8949 | "mips_dump_tdep: ef_mips_arch = %d\n", | |
8950 | ef_mips_arch); | |
8951 | gdb_printf (file, | |
8952 | "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", | |
8953 | tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); | |
8954 | gdb_printf (file, | |
8955 | "mips_dump_tdep: " | |
8956 | "mips_mask_address_p() %d (default %d)\n", | |
8957 | mips_mask_address_p (tdep), | |
8958 | tdep->default_mask_address_p); | |
c2d11a7d | 8959 | } |
6cb06a8c TT |
8960 | gdb_printf (file, |
8961 | "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", | |
8962 | MIPS_DEFAULT_FPU_TYPE, | |
8963 | mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE)); | |
8964 | gdb_printf (file, "mips_dump_tdep: MIPS_EABI = %d\n", | |
8965 | mips_eabi (gdbarch)); | |
8966 | gdb_printf (file, | |
8967 | "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", | |
8968 | mips_get_fpu_type (gdbarch), | |
8969 | mips_fpu_type_str (mips_get_fpu_type (gdbarch))); | |
c2d11a7d JM |
8970 | } |
8971 | ||
6c265988 | 8972 | void _initialize_mips_tdep (); |
c906108c | 8973 | void |
6c265988 | 8974 | _initialize_mips_tdep () |
c906108c SS |
8975 | { |
8976 | static struct cmd_list_element *mipsfpulist = NULL; | |
c906108c | 8977 | |
6d82d43b | 8978 | mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; |
2e4ebe70 DJ |
8979 | if (MIPS_ABI_LAST + 1 |
8980 | != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) | |
f34652de | 8981 | internal_error (_("mips_abi_strings out of sync")); |
2e4ebe70 | 8982 | |
4b9b3959 | 8983 | gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); |
c906108c | 8984 | |
4eb0ad19 DJ |
8985 | /* Create feature sets with the appropriate properties. The values |
8986 | are not important. */ | |
51a948fd | 8987 | mips_tdesc_gp32 = allocate_target_description ().release (); |
4eb0ad19 DJ |
8988 | set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); |
8989 | ||
51a948fd | 8990 | mips_tdesc_gp64 = allocate_target_description ().release (); |
4eb0ad19 DJ |
8991 | set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); |
8992 | ||
025bb325 | 8993 | /* Add root prefix command for all "set mips"/"show mips" commands. */ |
f54bdb6d SM |
8994 | add_setshow_prefix_cmd ("mips", no_class, |
8995 | _("Various MIPS specific commands."), | |
8996 | _("Various MIPS specific commands."), | |
8997 | &setmipscmdlist, &showmipscmdlist, | |
8998 | &setlist, &showlist); | |
a5ea2558 | 8999 | |
025bb325 | 9000 | /* Allow the user to override the ABI. */ |
7ab04401 AC |
9001 | add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, |
9002 | &mips_abi_string, _("\ | |
9003 | Set the MIPS ABI used by this program."), _("\ | |
9004 | Show the MIPS ABI used by this program."), _("\ | |
9005 | This option can be set to one of:\n\ | |
9006 | auto - the default ABI associated with the current binary\n\ | |
9007 | o32\n\ | |
9008 | o64\n\ | |
9009 | n32\n\ | |
9010 | n64\n\ | |
9011 | eabi32\n\ | |
9012 | eabi64"), | |
9013 | mips_abi_update, | |
9014 | show_mips_abi, | |
9015 | &setmipscmdlist, &showmipscmdlist); | |
2e4ebe70 | 9016 | |
4cc0665f MR |
9017 | /* Allow the user to set the ISA to assume for compressed code if ELF |
9018 | file flags don't tell or there is no program file selected. This | |
9019 | setting is updated whenever unambiguous ELF file flags are interpreted, | |
9020 | and carried over to subsequent sessions. */ | |
9021 | add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, | |
9022 | &mips_compression_string, _("\ | |
9023 | Set the compressed ISA encoding used by MIPS code."), _("\ | |
9024 | Show the compressed ISA encoding used by MIPS code."), _("\ | |
9025 | Select the compressed ISA encoding used in functions that have no symbol\n\ | |
9026 | information available. The encoding can be set to either of:\n\ | |
9027 | mips16\n\ | |
9028 | micromips\n\ | |
9029 | and is updated automatically from ELF file flags if available."), | |
9030 | mips_abi_update, | |
9031 | show_mips_compression, | |
9032 | &setmipscmdlist, &showmipscmdlist); | |
9033 | ||
c906108c SS |
9034 | /* Let the user turn off floating point and set the fence post for |
9035 | heuristic_proc_start. */ | |
9036 | ||
3b6acaee TT |
9037 | add_basic_prefix_cmd ("mipsfpu", class_support, |
9038 | _("Set use of MIPS floating-point coprocessor."), | |
2f822da5 | 9039 | &mipsfpulist, 0, &setlist); |
c906108c | 9040 | add_cmd ("single", class_support, set_mipsfpu_single_command, |
1a966eab | 9041 | _("Select single-precision MIPS floating-point coprocessor."), |
c906108c | 9042 | &mipsfpulist); |
5e84b7ee SM |
9043 | cmd_list_element *set_mipsfpu_double_cmd |
9044 | = add_cmd ("double", class_support, set_mipsfpu_double_command, | |
9045 | _("Select double-precision MIPS floating-point coprocessor."), | |
9046 | &mipsfpulist); | |
9047 | add_alias_cmd ("on", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); | |
9048 | add_alias_cmd ("yes", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); | |
9049 | add_alias_cmd ("1", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); | |
9050 | ||
9051 | cmd_list_element *set_mipsfpu_none_cmd | |
9052 | = add_cmd ("none", class_support, set_mipsfpu_none_command, | |
9053 | _("Select no MIPS floating-point coprocessor."), &mipsfpulist); | |
9054 | add_alias_cmd ("off", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); | |
9055 | add_alias_cmd ("no", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); | |
9056 | add_alias_cmd ("0", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); | |
c906108c | 9057 | add_cmd ("auto", class_support, set_mipsfpu_auto_command, |
1a966eab | 9058 | _("Select MIPS floating-point coprocessor automatically."), |
c906108c SS |
9059 | &mipsfpulist); |
9060 | add_cmd ("mipsfpu", class_support, show_mipsfpu_command, | |
1a966eab | 9061 | _("Show current use of MIPS floating-point coprocessor target."), |
c906108c SS |
9062 | &showlist); |
9063 | ||
c906108c SS |
9064 | /* We really would like to have both "0" and "unlimited" work, but |
9065 | command.c doesn't deal with that. So make it a var_zinteger | |
9066 | because the user can always use "999999" or some such for unlimited. */ | |
6bcadd06 | 9067 | add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, |
7915a72c AC |
9068 | &heuristic_fence_post, _("\ |
9069 | Set the distance searched for the start of a function."), _("\ | |
9070 | Show the distance searched for the start of a function."), _("\ | |
c906108c SS |
9071 | If you are debugging a stripped executable, GDB needs to search through the\n\ |
9072 | program for the start of a function. This command sets the distance of the\n\ | |
7915a72c | 9073 | search. The only need to set it is when debugging a stripped executable."), |
2c5b56ce | 9074 | reinit_frame_cache_sfunc, |
025bb325 MS |
9075 | NULL, /* FIXME: i18n: The distance searched for |
9076 | the start of a function is %s. */ | |
6bcadd06 | 9077 | &setlist, &showlist); |
c906108c SS |
9078 | |
9079 | /* Allow the user to control whether the upper bits of 64-bit | |
9080 | addresses should be zeroed. */ | |
7915a72c AC |
9081 | add_setshow_auto_boolean_cmd ("mask-address", no_class, |
9082 | &mask_address_var, _("\ | |
9083 | Set zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
9084 | Show zeroing of upper 32 bits of 64-bit addresses."), _("\ | |
cce7e648 | 9085 | Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ |
7915a72c | 9086 | allow GDB to determine the correct value."), |
08546159 AC |
9087 | NULL, show_mask_address, |
9088 | &setmipscmdlist, &showmipscmdlist); | |
43e526b9 JM |
9089 | |
9090 | /* Allow the user to control the size of 32 bit registers within the | |
9091 | raw remote packet. */ | |
b3f42336 | 9092 | add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, |
7915a72c AC |
9093 | &mips64_transfers_32bit_regs_p, _("\ |
9094 | Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9095 | _("\ | |
9096 | Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), | |
9097 | _("\ | |
719ec221 AC |
9098 | Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ |
9099 | that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ | |
7915a72c | 9100 | 64 bits for others. Use \"off\" to disable compatibility mode"), |
2c5b56ce | 9101 | set_mips64_transfers_32bit_regs, |
025bb325 MS |
9102 | NULL, /* FIXME: i18n: Compatibility with 64-bit |
9103 | MIPS target that transfers 32-bit | |
9104 | quantities is %s. */ | |
7915a72c | 9105 | &setlist, &showlist); |
9ace0497 | 9106 | |
025bb325 | 9107 | /* Debug this files internals. */ |
ccce17b0 YQ |
9108 | add_setshow_zuinteger_cmd ("mips", class_maintenance, |
9109 | &mips_debug, _("\ | |
7915a72c AC |
9110 | Set mips debugging."), _("\ |
9111 | Show mips debugging."), _("\ | |
9112 | When non-zero, mips specific debugging is enabled."), | |
ccce17b0 YQ |
9113 | NULL, |
9114 | NULL, /* FIXME: i18n: Mips debugging is | |
9115 | currently %s. */ | |
9116 | &setdebuglist, &showdebuglist); | |
c906108c | 9117 | } |