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1 | /* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger. |
2 | ||
4a94e368 | 3 | Copyright (C) 2002-2022 Free Software Foundation, Inc. |
d1973055 KB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
d1973055 KB |
10 | (at your option) any later version. |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
d1973055 KB |
19 | |
20 | #ifndef MIPS_TDEP_H | |
21 | #define MIPS_TDEP_H | |
22 | ||
3e5d3a5a | 23 | #include "objfiles.h" |
76eb8ef1 | 24 | #include "gdbarch.h" |
3e5d3a5a | 25 | |
da3331ec AC |
26 | struct gdbarch; |
27 | ||
025bb325 | 28 | /* All the possible MIPS ABIs. */ |
d1973055 KB |
29 | enum mips_abi |
30 | { | |
31 | MIPS_ABI_UNKNOWN = 0, | |
32 | MIPS_ABI_N32, | |
33 | MIPS_ABI_O32, | |
34 | MIPS_ABI_N64, | |
35 | MIPS_ABI_O64, | |
36 | MIPS_ABI_EABI32, | |
37 | MIPS_ABI_EABI64, | |
38 | MIPS_ABI_LAST | |
39 | }; | |
40 | ||
41 | /* Return the MIPS ABI associated with GDBARCH. */ | |
42 | enum mips_abi mips_abi (struct gdbarch *gdbarch); | |
43 | ||
4cc0665f MR |
44 | /* Base and compressed MIPS ISA variations. */ |
45 | enum mips_isa | |
46 | { | |
47 | ISA_MIPS = -1, /* mips_compression_string depends on it. */ | |
48 | ISA_MIPS16, | |
49 | ISA_MICROMIPS | |
50 | }; | |
51 | ||
f161c171 MR |
52 | /* Corresponding MSYMBOL_TARGET_FLAG aliases. */ |
53 | #define MSYMBOL_TARGET_FLAG_MIPS16 MSYMBOL_TARGET_FLAG_1 | |
54 | #define MSYMBOL_TARGET_FLAG_MICROMIPS MSYMBOL_TARGET_FLAG_2 | |
55 | ||
1b13c4f6 | 56 | /* Return the MIPS ISA's register size. Just a short cut to the BFD |
4246e332 | 57 | architecture's word size. */ |
1b13c4f6 | 58 | extern int mips_isa_regsize (struct gdbarch *gdbarch); |
4246e332 | 59 | |
56cea623 AC |
60 | /* Return the current index for various MIPS registers. */ |
61 | struct mips_regnum | |
62 | { | |
63 | int pc; | |
64 | int fp0; | |
65 | int fp_implementation_revision; | |
66 | int fp_control_status; | |
67 | int badvaddr; /* Bad vaddr for addressing exception. */ | |
68 | int cause; /* Describes last exception. */ | |
69 | int hi; /* Multiply/divide temp. */ | |
70 | int lo; /* ... */ | |
1faeff08 MR |
71 | int dspacc; /* SmartMIPS/DSP accumulators. */ |
72 | int dspctl; /* DSP control. */ | |
56cea623 AC |
73 | }; |
74 | extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch); | |
75 | ||
e38d4e1a DJ |
76 | /* Some MIPS boards don't support floating point while others only |
77 | support single-precision floating-point operations. */ | |
78 | ||
79 | enum mips_fpu_type | |
80 | { | |
81 | MIPS_FPU_DOUBLE, /* Full double precision floating point. */ | |
82 | MIPS_FPU_SINGLE, /* Single precision floating point (R4650). */ | |
83 | MIPS_FPU_NONE /* No floating point. */ | |
84 | }; | |
85 | ||
025bb325 | 86 | /* MIPS specific per-architecture information. */ |
345bd07c | 87 | struct mips_gdbarch_tdep : gdbarch_tdep |
e38d4e1a DJ |
88 | { |
89 | /* from the elf header */ | |
345bd07c | 90 | int elf_flags = 0; |
e38d4e1a DJ |
91 | |
92 | /* mips options */ | |
345bd07c SM |
93 | enum mips_abi mips_abi {}; |
94 | enum mips_abi found_abi {}; | |
95 | enum mips_isa mips_isa {}; | |
96 | enum mips_fpu_type mips_fpu_type {}; | |
97 | int mips_last_arg_regnum = 0; | |
98 | int mips_last_fp_arg_regnum = 0; | |
99 | int default_mask_address_p = 0; | |
e38d4e1a DJ |
100 | /* Is the target using 64-bit raw integer registers but only |
101 | storing a left-aligned 32-bit value in each? */ | |
345bd07c | 102 | int mips64_transfers_32bit_regs_p = 0; |
e38d4e1a DJ |
103 | /* Indexes for various registers. IRIX and embedded have |
104 | different values. This contains the "public" fields. Don't | |
105 | add any that do not need to be public. */ | |
345bd07c | 106 | const struct mips_regnum *regnum = nullptr; |
e38d4e1a | 107 | /* Register names table for the current register set. */ |
345bd07c | 108 | const char * const *mips_processor_reg_names = nullptr; |
e38d4e1a DJ |
109 | |
110 | /* The size of register data available from the target, if known. | |
111 | This doesn't quite obsolete the manual | |
112 | mips64_transfers_32bit_regs_p, since that is documented to force | |
113 | left alignment even for big endian (very strange). */ | |
345bd07c SM |
114 | int register_size_valid_p = 0; |
115 | int register_size = 0; | |
e38d4e1a DJ |
116 | |
117 | /* Return the expected next PC if FRAME is stopped at a syscall | |
118 | instruction. */ | |
345bd07c | 119 | CORE_ADDR (*syscall_next_pc) (struct frame_info *frame) = nullptr; |
e38d4e1a DJ |
120 | }; |
121 | ||
7157eed4 | 122 | /* Register numbers of various important registers. */ |
613e114f | 123 | |
9c46b6f0 MK |
124 | enum |
125 | { | |
613e114f | 126 | MIPS_ZERO_REGNUM = 0, /* Read-only register, always 0. */ |
9c46b6f0 | 127 | MIPS_AT_REGNUM = 1, |
613e114f | 128 | MIPS_V0_REGNUM = 2, /* Function integer return value. */ |
025bb325 | 129 | MIPS_A0_REGNUM = 4, /* Loc of first arg during a subr call. */ |
14132e89 | 130 | MIPS_S2_REGNUM = 18, /* Contains return address in MIPS16 thunks. */ |
613e114f | 131 | MIPS_T9_REGNUM = 25, /* Contains address of callee in PIC. */ |
14132e89 | 132 | MIPS_GP_REGNUM = 28, |
f10683bb | 133 | MIPS_SP_REGNUM = 29, |
9c46b6f0 | 134 | MIPS_RA_REGNUM = 31, |
24e05951 | 135 | MIPS_PS_REGNUM = 32, /* Contains processor status. */ |
56cea623 AC |
136 | MIPS_EMBED_LO_REGNUM = 33, |
137 | MIPS_EMBED_HI_REGNUM = 34, | |
138 | MIPS_EMBED_BADVADDR_REGNUM = 35, | |
139 | MIPS_EMBED_CAUSE_REGNUM = 36, | |
140 | MIPS_EMBED_PC_REGNUM = 37, | |
613e114f | 141 | MIPS_EMBED_FP0_REGNUM = 38, |
025bb325 | 142 | MIPS_UNUSED_REGNUM = 73, /* Never used, FIXME. */ |
607fc93c | 143 | MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use. */ |
a5c9623c | 144 | MIPS_PRID_REGNUM = 89, /* Processor ID. */ |
607fc93c | 145 | MIPS_LAST_EMBED_REGNUM = 89 /* Last one. */ |
56cea623 AC |
146 | }; |
147 | ||
95ac2dcf AC |
148 | /* Instruction sizes and other useful constants. */ |
149 | enum | |
9c46b6f0 | 150 | { |
95ac2dcf AC |
151 | MIPS_INSN16_SIZE = 2, |
152 | MIPS_INSN32_SIZE = 4, | |
153 | /* The number of floating-point or integer registers. */ | |
154 | MIPS_NUMREGS = 32 | |
9c46b6f0 MK |
155 | }; |
156 | ||
0d0266c6 | 157 | /* Single step based on where the current instruction will take us. */ |
a0ff9e1a SM |
158 | extern std::vector<CORE_ADDR> mips_software_single_step |
159 | (struct regcache *regcache); | |
691c0433 | 160 | |
3e29f34a MR |
161 | /* Strip the ISA (compression) bit off from ADDR. */ |
162 | extern CORE_ADDR mips_unmake_compact_addr (CORE_ADDR addr); | |
163 | ||
4cc0665f MR |
164 | /* Tell if the program counter value in MEMADDR is in a standard |
165 | MIPS function. */ | |
dfdeeca1 | 166 | extern int mips_pc_is_mips (CORE_ADDR memaddr); |
4cc0665f | 167 | |
0fe7e7c8 AC |
168 | /* Tell if the program counter value in MEMADDR is in a MIPS16 |
169 | function. */ | |
e94e944b | 170 | extern int mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr); |
4cc0665f MR |
171 | |
172 | /* Tell if the program counter value in MEMADDR is in a microMIPS | |
173 | function. */ | |
e94e944b | 174 | extern int mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr); |
0fe7e7c8 | 175 | |
025bb325 | 176 | /* Return the currently configured (or set) saved register size. */ |
e6bc2e8a AC |
177 | extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch); |
178 | ||
5a439849 MR |
179 | /* Make PC the address of the next instruction to execute. */ |
180 | extern void mips_write_pc (struct regcache *regcache, CORE_ADDR pc); | |
181 | ||
4eb0ad19 DJ |
182 | /* Target descriptions which only indicate the size of general |
183 | registers. */ | |
184 | extern struct target_desc *mips_tdesc_gp32; | |
185 | extern struct target_desc *mips_tdesc_gp64; | |
186 | ||
3e5d3a5a MR |
187 | /* Return non-zero if PC is in a MIPS SVR4 lazy binding stub section. */ |
188 | ||
189 | static inline int | |
190 | in_mips_stubs_section (CORE_ADDR pc) | |
191 | { | |
192 | return pc_in_section (pc, ".MIPS.stubs"); | |
193 | } | |
194 | ||
d1973055 | 195 | #endif /* MIPS_TDEP_H */ |