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342ee437
MS
1/* Target-dependent code for the Matsushita MN10300 for GDB, the GNU debugger.
2
6aba47ca
DJ
3 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
4 2007 Free Software Foundation, Inc.
342ee437
MS
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
197e01b6
EZ
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
342ee437 22
342ee437
MS
23#include "defs.h"
24#include "arch-utils.h"
25#include "dis-asm.h"
26#include "gdbtypes.h"
27#include "regcache.h"
28#include "gdb_string.h"
29#include "gdb_assert.h"
30#include "gdbcore.h" /* for write_memory_unsigned_integer */
31#include "value.h"
32#include "gdbtypes.h"
33#include "frame.h"
34#include "frame-unwind.h"
35#include "frame-base.h"
36#include "trad-frame.h"
37#include "symtab.h"
38#include "dwarf2-frame.h"
697e3bc9 39#include "osabi.h"
342ee437
MS
40
41#include "mn10300-tdep.h"
42
9cacebf5
MS
43/* Forward decl. */
44extern struct trad_frame_cache *mn10300_frame_unwind_cache (struct frame_info*,
45 void **);
342ee437
MS
46
47/* Compute the alignment required by a type. */
48
49static int
50mn10300_type_align (struct type *type)
51{
52 int i, align = 1;
53
54 switch (TYPE_CODE (type))
55 {
56 case TYPE_CODE_INT:
57 case TYPE_CODE_ENUM:
58 case TYPE_CODE_SET:
59 case TYPE_CODE_RANGE:
60 case TYPE_CODE_CHAR:
61 case TYPE_CODE_BOOL:
62 case TYPE_CODE_FLT:
63 case TYPE_CODE_PTR:
64 case TYPE_CODE_REF:
65 return TYPE_LENGTH (type);
66
67 case TYPE_CODE_COMPLEX:
68 return TYPE_LENGTH (type) / 2;
69
70 case TYPE_CODE_STRUCT:
71 case TYPE_CODE_UNION:
72 for (i = 0; i < TYPE_NFIELDS (type); i++)
73 {
74 int falign = mn10300_type_align (TYPE_FIELD_TYPE (type, i));
75 while (align < falign)
76 align <<= 1;
77 }
78 return align;
79
80 case TYPE_CODE_ARRAY:
81 /* HACK! Structures containing arrays, even small ones, are not
82 elligible for returning in registers. */
83 return 256;
84
85 case TYPE_CODE_TYPEDEF:
86 return mn10300_type_align (check_typedef (type));
87
88 default:
89 internal_error (__FILE__, __LINE__, _("bad switch"));
90 }
91}
92
342ee437 93/* Should call_function allocate stack space for a struct return? */
342ee437 94static int
99fe5f9d 95mn10300_use_struct_convention (struct type *type)
342ee437
MS
96{
97 /* Structures bigger than a pair of words can't be returned in
98 registers. */
99 if (TYPE_LENGTH (type) > 8)
100 return 1;
101
102 switch (TYPE_CODE (type))
103 {
104 case TYPE_CODE_STRUCT:
105 case TYPE_CODE_UNION:
106 /* Structures with a single field are handled as the field
107 itself. */
108 if (TYPE_NFIELDS (type) == 1)
99fe5f9d 109 return mn10300_use_struct_convention (TYPE_FIELD_TYPE (type, 0));
342ee437
MS
110
111 /* Structures with word or double-word size are passed in memory, as
112 long as they require at least word alignment. */
113 if (mn10300_type_align (type) >= 4)
114 return 0;
115
116 return 1;
117
118 /* Arrays are addressable, so they're never returned in
119 registers. This condition can only hold when the array is
120 the only field of a struct or union. */
121 case TYPE_CODE_ARRAY:
122 return 1;
123
124 case TYPE_CODE_TYPEDEF:
99fe5f9d 125 return mn10300_use_struct_convention (check_typedef (type));
342ee437
MS
126
127 default:
128 return 0;
129 }
130}
131
342ee437 132static void
99fe5f9d 133mn10300_store_return_value (struct gdbarch *gdbarch, struct type *type,
342ee437
MS
134 struct regcache *regcache, const void *valbuf)
135{
342ee437
MS
136 int len = TYPE_LENGTH (type);
137 int reg, regsz;
138
139 if (TYPE_CODE (type) == TYPE_CODE_PTR)
140 reg = 4;
141 else
142 reg = 0;
143
144 regsz = register_size (gdbarch, reg);
145
146 if (len <= regsz)
147 regcache_raw_write_part (regcache, reg, 0, len, valbuf);
148 else if (len <= 2 * regsz)
149 {
150 regcache_raw_write (regcache, reg, valbuf);
151 gdb_assert (regsz == register_size (gdbarch, reg + 1));
152 regcache_raw_write_part (regcache, reg+1, 0,
153 len - regsz, (char *) valbuf + regsz);
154 }
155 else
156 internal_error (__FILE__, __LINE__,
157 _("Cannot store return value %d bytes long."), len);
158}
159
342ee437 160static void
99fe5f9d 161mn10300_extract_return_value (struct gdbarch *gdbarch, struct type *type,
342ee437
MS
162 struct regcache *regcache, void *valbuf)
163{
342ee437
MS
164 char buf[MAX_REGISTER_SIZE];
165 int len = TYPE_LENGTH (type);
166 int reg, regsz;
167
168 if (TYPE_CODE (type) == TYPE_CODE_PTR)
169 reg = 4;
170 else
171 reg = 0;
172
173 regsz = register_size (gdbarch, reg);
174 if (len <= regsz)
175 {
176 regcache_raw_read (regcache, reg, buf);
177 memcpy (valbuf, buf, len);
178 }
179 else if (len <= 2 * regsz)
180 {
181 regcache_raw_read (regcache, reg, buf);
182 memcpy (valbuf, buf, regsz);
183 gdb_assert (regsz == register_size (gdbarch, reg + 1));
184 regcache_raw_read (regcache, reg + 1, buf);
185 memcpy ((char *) valbuf + regsz, buf, len - regsz);
186 }
187 else
188 internal_error (__FILE__, __LINE__,
189 _("Cannot extract return value %d bytes long."), len);
190}
191
99fe5f9d
KB
192/* Determine, for architecture GDBARCH, how a return value of TYPE
193 should be returned. If it is supposed to be returned in registers,
194 and READBUF is non-zero, read the appropriate value from REGCACHE,
195 and copy it into READBUF. If WRITEBUF is non-zero, write the value
196 from WRITEBUF into REGCACHE. */
197
198static enum return_value_convention
199mn10300_return_value (struct gdbarch *gdbarch, struct type *type,
200 struct regcache *regcache, gdb_byte *readbuf,
201 const gdb_byte *writebuf)
202{
203 if (mn10300_use_struct_convention (type))
204 return RETURN_VALUE_STRUCT_CONVENTION;
205
206 if (readbuf)
207 mn10300_extract_return_value (gdbarch, type, regcache, readbuf);
208 if (writebuf)
209 mn10300_store_return_value (gdbarch, type, regcache, writebuf);
210
211 return RETURN_VALUE_REGISTER_CONVENTION;
212}
213
342ee437
MS
214static char *
215register_name (int reg, char **regs, long sizeof_regs)
216{
217 if (reg < 0 || reg >= sizeof_regs / sizeof (regs[0]))
218 return NULL;
219 else
220 return regs[reg];
221}
222
223static const char *
224mn10300_generic_register_name (int reg)
225{
226 static char *regs[] =
227 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
228 "sp", "pc", "mdr", "psw", "lir", "lar", "", "",
229 "", "", "", "", "", "", "", "",
230 "", "", "", "", "", "", "", "fp"
231 };
232 return register_name (reg, regs, sizeof regs);
233}
234
235
236static const char *
237am33_register_name (int reg)
238{
239 static char *regs[] =
240 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
241 "sp", "pc", "mdr", "psw", "lir", "lar", "",
242 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
243 "ssp", "msp", "usp", "mcrh", "mcrl", "mcvf", "", "", ""
244 };
245 return register_name (reg, regs, sizeof regs);
246}
247
4640dd91
KB
248static const char *
249am33_2_register_name (int reg)
250{
251 static char *regs[] =
252 {
253 "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3",
254 "sp", "pc", "mdr", "psw", "lir", "lar", "mdrq", "r0",
255 "r1", "r2", "r3", "r4", "r5", "r6", "r7", "ssp",
256 "msp", "usp", "mcrh", "mcrl", "mcvf", "fpcr", "", "",
257 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
258 "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15",
259 "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23",
260 "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31"
261 };
262 return register_name (reg, regs, sizeof regs);
263}
342ee437
MS
264
265static struct type *
266mn10300_register_type (struct gdbarch *gdbarch, int reg)
267{
268 return builtin_type_int;
269}
270
271static CORE_ADDR
272mn10300_read_pc (ptid_t ptid)
273{
274 return read_register_pid (E_PC_REGNUM, ptid);
275}
276
277static void
278mn10300_write_pc (CORE_ADDR val, ptid_t ptid)
279{
280 return write_register_pid (E_PC_REGNUM, val, ptid);
281}
282
283/* The breakpoint instruction must be the same size as the smallest
284 instruction in the instruction set.
285
286 The Matsushita mn10x00 processors have single byte instructions
287 so we need a single byte breakpoint. Matsushita hasn't defined
288 one, so we defined it ourselves. */
289
290const static unsigned char *
291mn10300_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
292{
293 static char breakpoint[] = {0xff};
294 *bp_size = 1;
295 return breakpoint;
296}
297
4640dd91 298/* Set offsets of saved registers.
9cacebf5
MS
299 This is a helper function for mn10300_analyze_prologue. */
300
301static void
4640dd91 302set_reg_offsets (struct frame_info *fi,
9cacebf5 303 void **this_cache,
4640dd91
KB
304 int movm_args,
305 int fpregmask,
306 int stack_extra_size,
307 int frame_in_fp)
9cacebf5
MS
308{
309 struct trad_frame_cache *cache;
310 int offset = 0;
311 CORE_ADDR base;
312
313 if (fi == NULL || this_cache == NULL)
314 return;
315
316 cache = mn10300_frame_unwind_cache (fi, this_cache);
317 if (cache == NULL)
318 return;
319
4640dd91
KB
320 if (frame_in_fp)
321 {
322 base = frame_unwind_register_unsigned (fi, E_A3_REGNUM);
323 }
324 else
325 {
326 base = frame_unwind_register_unsigned (fi, E_SP_REGNUM) + stack_extra_size;
327 }
328
329 trad_frame_set_this_base (cache, base);
330
331 if (AM33_MODE == 2)
332 {
333 /* If bit N is set in fpregmask, fsN is saved on the stack.
334 The floating point registers are saved in ascending order.
335 For example: fs16 <- Frame Pointer
336 fs17 Frame Pointer + 4 */
337 if (fpregmask != 0)
338 {
339 int i;
340 for (i = 0; i < 32; i++)
341 {
342 if (fpregmask & (1 << i))
343 {
344 trad_frame_set_reg_addr (cache, E_FS0_REGNUM + i, base + offset);
345 offset += 4;
346 }
347 }
348 }
349 }
350
351
9cacebf5
MS
352 if (movm_args & movm_other_bit)
353 {
354 /* The `other' bit leaves a blank area of four bytes at the
355 beginning of its block of saved registers, making it 32 bytes
356 long in total. */
357 trad_frame_set_reg_addr (cache, E_LAR_REGNUM, base + offset + 4);
358 trad_frame_set_reg_addr (cache, E_LIR_REGNUM, base + offset + 8);
359 trad_frame_set_reg_addr (cache, E_MDR_REGNUM, base + offset + 12);
360 trad_frame_set_reg_addr (cache, E_A0_REGNUM + 1, base + offset + 16);
361 trad_frame_set_reg_addr (cache, E_A0_REGNUM, base + offset + 20);
362 trad_frame_set_reg_addr (cache, E_D0_REGNUM + 1, base + offset + 24);
363 trad_frame_set_reg_addr (cache, E_D0_REGNUM, base + offset + 28);
364 offset += 32;
365 }
366
367 if (movm_args & movm_a3_bit)
368 {
369 trad_frame_set_reg_addr (cache, E_A3_REGNUM, base + offset);
370 offset += 4;
371 }
372 if (movm_args & movm_a2_bit)
373 {
374 trad_frame_set_reg_addr (cache, E_A2_REGNUM, base + offset);
375 offset += 4;
376 }
377 if (movm_args & movm_d3_bit)
378 {
379 trad_frame_set_reg_addr (cache, E_D3_REGNUM, base + offset);
380 offset += 4;
381 }
382 if (movm_args & movm_d2_bit)
383 {
384 trad_frame_set_reg_addr (cache, E_D2_REGNUM, base + offset);
385 offset += 4;
386 }
387 if (AM33_MODE)
388 {
389 if (movm_args & movm_exother_bit)
390 {
391 trad_frame_set_reg_addr (cache, E_MCVF_REGNUM, base + offset);
392 trad_frame_set_reg_addr (cache, E_MCRL_REGNUM, base + offset + 4);
393 trad_frame_set_reg_addr (cache, E_MCRH_REGNUM, base + offset + 8);
394 trad_frame_set_reg_addr (cache, E_MDRQ_REGNUM, base + offset + 12);
395 trad_frame_set_reg_addr (cache, E_E1_REGNUM, base + offset + 16);
396 trad_frame_set_reg_addr (cache, E_E0_REGNUM, base + offset + 20);
397 offset += 24;
398 }
399 if (movm_args & movm_exreg1_bit)
400 {
401 trad_frame_set_reg_addr (cache, E_E7_REGNUM, base + offset);
402 trad_frame_set_reg_addr (cache, E_E6_REGNUM, base + offset + 4);
403 trad_frame_set_reg_addr (cache, E_E5_REGNUM, base + offset + 8);
404 trad_frame_set_reg_addr (cache, E_E4_REGNUM, base + offset + 12);
405 offset += 16;
406 }
407 if (movm_args & movm_exreg0_bit)
408 {
409 trad_frame_set_reg_addr (cache, E_E3_REGNUM, base + offset);
410 trad_frame_set_reg_addr (cache, E_E2_REGNUM, base + offset + 4);
411 offset += 8;
412 }
413 }
414 /* The last (or first) thing on the stack will be the PC. */
415 trad_frame_set_reg_addr (cache, E_PC_REGNUM, base + offset);
416 /* Save the SP in the 'traditional' way.
417 This will be the same location where the PC is saved. */
418 trad_frame_set_reg_value (cache, E_SP_REGNUM, base + offset);
419}
420
421/* The main purpose of this file is dealing with prologues to extract
422 information about stack frames and saved registers.
423
424 In gcc/config/mn13000/mn10300.c, the expand_prologue prologue
425 function is pretty readable, and has a nice explanation of how the
426 prologue is generated. The prologues generated by that code will
427 have the following form (NOTE: the current code doesn't handle all
428 this!):
429
430 + If this is an old-style varargs function, then its arguments
431 need to be flushed back to the stack:
432
433 mov d0,(4,sp)
434 mov d1,(4,sp)
435
436 + If we use any of the callee-saved registers, save them now.
437
438 movm [some callee-saved registers],(sp)
439
440 + If we have any floating-point registers to save:
441
442 - Decrement the stack pointer to reserve space for the registers.
443 If the function doesn't need a frame pointer, we may combine
444 this with the adjustment that reserves space for the frame.
445
446 add -SIZE, sp
447
448 - Save the floating-point registers. We have two possible
449 strategies:
450
451 . Save them at fixed offset from the SP:
452
453 fmov fsN,(OFFSETN,sp)
454 fmov fsM,(OFFSETM,sp)
455 ...
456
457 Note that, if OFFSETN happens to be zero, you'll get the
458 different opcode: fmov fsN,(sp)
459
460 . Or, set a0 to the start of the save area, and then use
461 post-increment addressing to save the FP registers.
462
463 mov sp, a0
464 add SIZE, a0
465 fmov fsN,(a0+)
466 fmov fsM,(a0+)
467 ...
468
469 + If the function needs a frame pointer, we set it here.
470
471 mov sp, a3
472
473 + Now we reserve space for the stack frame proper. This could be
474 merged into the `add -SIZE, sp' instruction for FP saves up
475 above, unless we needed to set the frame pointer in the previous
476 step, or the frame is so large that allocating the whole thing at
477 once would put the FP register save slots out of reach of the
478 addressing mode (128 bytes).
479
480 add -SIZE, sp
481
482 One day we might keep the stack pointer constant, that won't
483 change the code for prologues, but it will make the frame
484 pointerless case much more common. */
485
486/* Analyze the prologue to determine where registers are saved,
487 the end of the prologue, etc etc. Return the end of the prologue
488 scanned.
489
490 We store into FI (if non-null) several tidbits of information:
491
492 * stack_size -- size of this stack frame. Note that if we stop in
493 certain parts of the prologue/epilogue we may claim the size of the
494 current frame is zero. This happens when the current frame has
495 not been allocated yet or has already been deallocated.
496
497 * fsr -- Addresses of registers saved in the stack by this frame.
498
499 * status -- A (relatively) generic status indicator. It's a bitmask
500 with the following bits:
501
502 MY_FRAME_IN_SP: The base of the current frame is actually in
503 the stack pointer. This can happen for frame pointerless
504 functions, or cases where we're stopped in the prologue/epilogue
505 itself. For these cases mn10300_analyze_prologue will need up
506 update fi->frame before returning or analyzing the register
507 save instructions.
508
509 MY_FRAME_IN_FP: The base of the current frame is in the
510 frame pointer register ($a3).
511
512 NO_MORE_FRAMES: Set this if the current frame is "start" or
513 if the first instruction looks like mov <imm>,sp. This tells
514 frame chain to not bother trying to unwind past this frame. */
515
516static CORE_ADDR
517mn10300_analyze_prologue (struct frame_info *fi,
518 void **this_cache,
519 CORE_ADDR pc)
520{
521 CORE_ADDR func_addr, func_end, addr, stop;
4640dd91 522 long stack_extra_size = 0;
9cacebf5
MS
523 int imm_size;
524 unsigned char buf[4];
4640dd91
KB
525 int status;
526 int movm_args = 0;
527 int fpregmask = 0;
9cacebf5 528 char *name;
4640dd91 529 int frame_in_fp = 0;
9cacebf5
MS
530
531 /* Use the PC in the frame if it's provided to look up the
532 start of this function.
533
534 Note: kevinb/2003-07-16: We used to do the following here:
535 pc = (fi ? get_frame_pc (fi) : pc);
536 But this is (now) badly broken when called from analyze_dummy_frame().
537 */
538 if (fi)
539 {
540 pc = (pc ? pc : get_frame_pc (fi));
9cacebf5
MS
541 }
542
543 /* Find the start of this function. */
544 status = find_pc_partial_function (pc, &name, &func_addr, &func_end);
545
546 /* Do nothing if we couldn't find the start of this function
547
548 MVS: comment went on to say "or if we're stopped at the first
549 instruction in the prologue" -- but code doesn't reflect that,
550 and I don't want to do that anyway. */
551 if (status == 0)
552 {
4640dd91
KB
553 addr = pc;
554 goto finish_prologue;
9cacebf5
MS
555 }
556
557 /* If we're in start, then give up. */
558 if (strcmp (name, "start") == 0)
559 {
4640dd91
KB
560 addr = pc;
561 goto finish_prologue;
9cacebf5
MS
562 }
563
9cacebf5
MS
564 /* Figure out where to stop scanning. */
565 stop = fi ? pc : func_end;
566
567 /* Don't walk off the end of the function. */
568 stop = stop > func_end ? func_end : stop;
569
570 /* Start scanning on the first instruction of this function. */
571 addr = func_addr;
572
573 /* Suck in two bytes. */
4640dd91 574 if (addr + 2 > stop || !safe_frame_unwind_memory (fi, addr, buf, 2))
9cacebf5
MS
575 goto finish_prologue;
576
577 /* First see if this insn sets the stack pointer from a register; if
578 so, it's probably the initialization of the stack pointer in _start,
579 so mark this as the bottom-most frame. */
580 if (buf[0] == 0xf2 && (buf[1] & 0xf3) == 0xf0)
581 {
9cacebf5
MS
582 goto finish_prologue;
583 }
584
585 /* Now look for movm [regs],sp, which saves the callee saved registers.
586
587 At this time we don't know if fi->frame is valid, so we only note
588 that we encountered a movm instruction. Later, we'll set the entries
589 in fsr.regs as needed. */
590 if (buf[0] == 0xcf)
591 {
592 /* Extract the register list for the movm instruction. */
593 movm_args = buf[1];
594
595 addr += 2;
596
597 /* Quit now if we're beyond the stop point. */
598 if (addr >= stop)
599 goto finish_prologue;
600
601 /* Get the next two bytes so the prologue scan can continue. */
f2c8bc43 602 if (!safe_frame_unwind_memory (fi, addr, buf, 2))
9cacebf5
MS
603 goto finish_prologue;
604 }
605
4640dd91
KB
606 if (AM33_MODE == 2)
607 {
608 /* Determine if any floating point registers are to be saved.
609 Look for one of the following three prologue formats:
610
611 [movm [regs],(sp)] [movm [regs],(sp)] [movm [regs],(sp)]
612
613 add -SIZE,sp add -SIZE,sp add -SIZE,sp
614 fmov fs#,(sp) mov sp,a0/a1 mov sp,a0/a1
615 fmov fs#,(#,sp) fmov fs#,(a0/a1+) add SIZE2,a0/a1
616 ... ... fmov fs#,(a0/a1+)
617 ... ... ...
618 fmov fs#,(#,sp) fmov fs#,(a0/a1+) fmov fs#,(a0/a1+)
619
620 [mov sp,a3] [mov sp,a3]
621 [add -SIZE2,sp] [add -SIZE2,sp] */
622
e92e42f5
KB
623 /* Remember the address at which we started in the event that we
624 don't ultimately find an fmov instruction. Once we're certain
625 that we matched one of the above patterns, we'll set
626 ``restore_addr'' to the appropriate value. Note: At one time
627 in the past, this code attempted to not adjust ``addr'' until
628 there was a fair degree of certainty that the pattern would be
629 matched. However, that code did not wait until an fmov instruction
630 was actually encountered. As a consequence, ``addr'' would
631 sometimes be advanced even when no fmov instructions were found. */
632 CORE_ADDR restore_addr = addr;
633
4640dd91
KB
634 /* First, look for add -SIZE,sp (i.e. add imm8,sp (0xf8feXX)
635 or add imm16,sp (0xfafeXXXX)
636 or add imm32,sp (0xfcfeXXXXXXXX)) */
637 imm_size = 0;
638 if (buf[0] == 0xf8 && buf[1] == 0xfe)
639 imm_size = 1;
640 else if (buf[0] == 0xfa && buf[1] == 0xfe)
641 imm_size = 2;
642 else if (buf[0] == 0xfc && buf[1] == 0xfe)
643 imm_size = 4;
644 if (imm_size != 0)
645 {
646 /* An "add -#,sp" instruction has been found. "addr + 2 + imm_size"
647 is the address of the next instruction. Don't modify "addr" until
648 the next "floating point prologue" instruction is found. If this
649 is not a prologue that saves floating point registers we need to
650 be able to back out of this bit of code and continue with the
651 prologue analysis. */
652 if (addr + 2 + imm_size < stop)
653 {
654 if (!safe_frame_unwind_memory (fi, addr + 2 + imm_size, buf, 3))
655 goto finish_prologue;
656 if ((buf[0] & 0xfc) == 0x3c)
657 {
658 /* Occasionally, especially with C++ code, the "fmov"
659 instructions will be preceded by "mov sp,aN"
660 (aN => a0, a1, a2, or a3).
661
662 This is a one byte instruction: mov sp,aN = 0011 11XX
663 where XX is the register number.
664
e92e42f5
KB
665 Skip this instruction by incrementing addr. The "fmov"
666 instructions will have the form "fmov fs#,(aN+)" in this
667 case, but that will not necessitate a change in the
668 "fmov" parsing logic below. */
4640dd91
KB
669
670 addr++;
671
672 if ((buf[1] & 0xfc) == 0x20)
673 {
674 /* Occasionally, especially with C++ code compiled with
675 the -fomit-frame-pointer or -O3 options, the
676 "mov sp,aN" instruction will be followed by an
677 "add #,aN" instruction. This indicates the
678 "stack_size", the size of the portion of the stack
679 containing the arguments. This instruction format is:
680 add #,aN = 0010 00XX YYYY YYYY
681 where XX is the register number
682 YYYY YYYY is the constant.
683 Note the size of the stack (as a negative number) in
684 the frame info structure. */
685 if (fi)
686 stack_extra_size += -buf[2];
687
688 addr += 2;
689 }
690 }
691
692 if ((buf[0] & 0xfc) == 0x3c ||
693 buf[0] == 0xf9 || buf[0] == 0xfb)
694 {
695 /* An "fmov" instruction has been found indicating that this
696 prologue saves floating point registers (or, as described
697 above, a "mov sp,aN" and possible "add #,aN" have been
698 found and we will assume an "fmov" follows). Process the
699 consecutive "fmov" instructions. */
700 for (addr += 2 + imm_size;;addr += imm_size)
701 {
702 int regnum;
703
704 /* Read the "fmov" instruction. */
705 if (addr >= stop ||
706 !safe_frame_unwind_memory (fi, addr, buf, 4))
707 goto finish_prologue;
708
709 if (buf[0] != 0xf9 && buf[0] != 0xfb)
710 break;
711
e92e42f5
KB
712 /* An fmov instruction has just been seen. We can
713 now really commit to the pattern match. Set the
714 address to restore at the end of this speculative
715 bit of code to the actually address that we've
716 been incrementing (or not) throughout the
717 speculation. */
718 restore_addr = addr;
719
4640dd91
KB
720 /* Get the floating point register number from the
721 2nd and 3rd bytes of the "fmov" instruction:
722 Machine Code: 0000 00X0 YYYY 0000 =>
723 Regnum: 000X YYYY */
724 regnum = (buf[1] & 0x02) << 3;
725 regnum |= ((buf[2] & 0xf0) >> 4) & 0x0f;
726
727 /* Add this register number to the bit mask of floating
728 point registers that have been saved. */
729 fpregmask |= 1 << regnum;
730
731 /* Determine the length of this "fmov" instruction.
732 fmov fs#,(sp) => 3 byte instruction
733 fmov fs#,(#,sp) => 4 byte instruction */
734 imm_size = (buf[0] == 0xf9) ? 3 : 4;
735 }
736 }
737 else
738 {
739 /* No "fmov" was found. Reread the two bytes at the original
740 "addr" to reset the state. */
e92e42f5 741 addr = restore_addr;
4640dd91
KB
742 if (!safe_frame_unwind_memory (fi, addr, buf, 2))
743 goto finish_prologue;
744 }
745 }
746 /* else the prologue consists entirely of an "add -SIZE,sp"
747 instruction. Handle this below. */
748 }
749 /* else no "add -SIZE,sp" was found indicating no floating point
e92e42f5
KB
750 registers are saved in this prologue. */
751
752 /* In the pattern match code contained within this block, `restore_addr'
753 is set to the starting address at the very beginning and then
754 iteratively to the next address to start scanning at once the
755 pattern match has succeeded. Thus `restore_addr' will contain
756 the address to rewind to if the pattern match failed. If the
757 match succeeded, `restore_addr' and `addr' will already have the
758 same value. */
759 addr = restore_addr;
4640dd91
KB
760 }
761
9cacebf5
MS
762 /* Now see if we set up a frame pointer via "mov sp,a3" */
763 if (buf[0] == 0x3f)
764 {
765 addr += 1;
766
767 /* The frame pointer is now valid. */
768 if (fi)
769 {
4640dd91 770 frame_in_fp = 1;
9cacebf5
MS
771 }
772
773 /* Quit now if we're beyond the stop point. */
774 if (addr >= stop)
775 goto finish_prologue;
776
777 /* Get two more bytes so scanning can continue. */
f2c8bc43 778 if (!safe_frame_unwind_memory (fi, addr, buf, 2))
9cacebf5
MS
779 goto finish_prologue;
780 }
781
782 /* Next we should allocate the local frame. No more prologue insns
783 are found after allocating the local frame.
784
785 Search for add imm8,sp (0xf8feXX)
786 or add imm16,sp (0xfafeXXXX)
787 or add imm32,sp (0xfcfeXXXXXXXX).
788
789 If none of the above was found, then this prologue has no
790 additional stack. */
791
792 imm_size = 0;
793 if (buf[0] == 0xf8 && buf[1] == 0xfe)
794 imm_size = 1;
795 else if (buf[0] == 0xfa && buf[1] == 0xfe)
796 imm_size = 2;
797 else if (buf[0] == 0xfc && buf[1] == 0xfe)
798 imm_size = 4;
799
800 if (imm_size != 0)
801 {
802 /* Suck in imm_size more bytes, they'll hold the size of the
803 current frame. */
f2c8bc43 804 if (!safe_frame_unwind_memory (fi, addr + 2, buf, imm_size))
9cacebf5
MS
805 goto finish_prologue;
806
4640dd91 807 /* Note the size of the stack. */
e92e42f5 808 stack_extra_size -= extract_signed_integer (buf, imm_size);
9cacebf5
MS
809
810 /* We just consumed 2 + imm_size bytes. */
811 addr += 2 + imm_size;
812
813 /* No more prologue insns follow, so begin preparation to return. */
814 goto finish_prologue;
815 }
816 /* Do the essentials and get out of here. */
817 finish_prologue:
818 /* Note if/where callee saved registers were saved. */
819 if (fi)
4640dd91 820 set_reg_offsets (fi, this_cache, movm_args, fpregmask, stack_extra_size, frame_in_fp);
9cacebf5
MS
821 return addr;
822}
823
342ee437
MS
824/* Function: skip_prologue
825 Return the address of the first inst past the prologue of the function. */
826
827static CORE_ADDR
828mn10300_skip_prologue (CORE_ADDR pc)
829{
9b3c083c 830 return mn10300_analyze_prologue (NULL, NULL, pc);
342ee437
MS
831}
832
833/* Simple frame_unwind_cache.
834 This finds the "extra info" for the frame. */
835struct trad_frame_cache *
836mn10300_frame_unwind_cache (struct frame_info *next_frame,
837 void **this_prologue_cache)
838{
839 struct trad_frame_cache *cache;
1fb1ca27 840 CORE_ADDR pc, start, end;
342ee437
MS
841
842 if (*this_prologue_cache)
843 return (*this_prologue_cache);
844
845 cache = trad_frame_cache_zalloc (next_frame);
846 pc = gdbarch_unwind_pc (current_gdbarch, next_frame);
847 mn10300_analyze_prologue (next_frame, (void **) &cache, pc);
1fb1ca27
MS
848 if (find_pc_partial_function (pc, NULL, &start, &end))
849 trad_frame_set_id (cache,
850 frame_id_build (trad_frame_get_this_base (cache),
851 start));
852 else
853 trad_frame_set_id (cache,
854 frame_id_build (trad_frame_get_this_base (cache),
855 frame_func_unwind (next_frame)));
342ee437
MS
856
857 (*this_prologue_cache) = cache;
858 return cache;
859}
860
861/* Here is a dummy implementation. */
862static struct frame_id
863mn10300_unwind_dummy_id (struct gdbarch *gdbarch,
864 struct frame_info *next_frame)
865{
866 return frame_id_build (frame_sp_unwind (next_frame),
867 frame_pc_unwind (next_frame));
868}
869
870/* Trad frame implementation. */
871static void
872mn10300_frame_this_id (struct frame_info *next_frame,
873 void **this_prologue_cache,
874 struct frame_id *this_id)
875{
876 struct trad_frame_cache *cache =
877 mn10300_frame_unwind_cache (next_frame, this_prologue_cache);
878
879 trad_frame_get_id (cache, this_id);
880}
881
882static void
883mn10300_frame_prev_register (struct frame_info *next_frame,
884 void **this_prologue_cache,
885 int regnum, int *optimizedp,
886 enum lval_type *lvalp, CORE_ADDR *addrp,
3e6b1689 887 int *realnump, gdb_byte *bufferp)
342ee437
MS
888{
889 struct trad_frame_cache *cache =
890 mn10300_frame_unwind_cache (next_frame, this_prologue_cache);
891
892 trad_frame_get_register (cache, next_frame, regnum, optimizedp,
893 lvalp, addrp, realnump, bufferp);
894 /* Or...
895 trad_frame_get_prev_register (next_frame, cache->prev_regs, regnum,
896 optimizedp, lvalp, addrp, realnump, bufferp);
897 */
898}
899
900static const struct frame_unwind mn10300_frame_unwind = {
901 NORMAL_FRAME,
902 mn10300_frame_this_id,
903 mn10300_frame_prev_register
904};
905
906static CORE_ADDR
907mn10300_frame_base_address (struct frame_info *next_frame,
908 void **this_prologue_cache)
909{
910 struct trad_frame_cache *cache =
911 mn10300_frame_unwind_cache (next_frame, this_prologue_cache);
912
913 return trad_frame_get_this_base (cache);
914}
915
916static const struct frame_unwind *
917mn10300_frame_sniffer (struct frame_info *next_frame)
918{
919 return &mn10300_frame_unwind;
920}
921
922static const struct frame_base mn10300_frame_base = {
923 &mn10300_frame_unwind,
924 mn10300_frame_base_address,
925 mn10300_frame_base_address,
926 mn10300_frame_base_address
927};
928
929static CORE_ADDR
930mn10300_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
931{
932 ULONGEST pc;
933
934 frame_unwind_unsigned_register (next_frame, E_PC_REGNUM, &pc);
935 return pc;
936}
937
938static CORE_ADDR
939mn10300_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
940{
941 ULONGEST sp;
942
943 frame_unwind_unsigned_register (next_frame, E_SP_REGNUM, &sp);
944 return sp;
945}
946
947static void
948mn10300_frame_unwind_init (struct gdbarch *gdbarch)
949{
950 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
951 frame_unwind_append_sniffer (gdbarch, mn10300_frame_sniffer);
952 frame_base_set_default (gdbarch, &mn10300_frame_base);
953 set_gdbarch_unwind_dummy_id (gdbarch, mn10300_unwind_dummy_id);
954 set_gdbarch_unwind_pc (gdbarch, mn10300_unwind_pc);
955 set_gdbarch_unwind_sp (gdbarch, mn10300_unwind_sp);
956}
957
958/* Function: push_dummy_call
959 *
960 * Set up machine state for a target call, including
961 * function arguments, stack, return address, etc.
962 *
963 */
964
965static CORE_ADDR
966mn10300_push_dummy_call (struct gdbarch *gdbarch,
967 struct value *target_func,
968 struct regcache *regcache,
969 CORE_ADDR bp_addr,
970 int nargs, struct value **args,
971 CORE_ADDR sp,
972 int struct_return,
973 CORE_ADDR struct_addr)
974{
975 const int push_size = register_size (gdbarch, E_PC_REGNUM);
1fb1ca27 976 int regs_used;
342ee437
MS
977 int len, arg_len;
978 int stack_offset = 0;
979 int argnum;
1fb1ca27 980 char *val, valbuf[MAX_REGISTER_SIZE];
342ee437 981
342ee437
MS
982 /* This should be a nop, but align the stack just in case something
983 went wrong. Stacks are four byte aligned on the mn10300. */
984 sp &= ~3;
985
986 /* Now make space on the stack for the args.
987
988 XXX This doesn't appear to handle pass-by-invisible reference
989 arguments. */
1fb1ca27 990 regs_used = struct_return ? 1 : 0;
342ee437
MS
991 for (len = 0, argnum = 0; argnum < nargs; argnum++)
992 {
993 arg_len = (TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3;
342ee437
MS
994 while (regs_used < 2 && arg_len > 0)
995 {
996 regs_used++;
997 arg_len -= push_size;
998 }
999 len += arg_len;
1000 }
1001
1002 /* Allocate stack space. */
1003 sp -= len;
1004
1fb1ca27
MS
1005 if (struct_return)
1006 {
1007 regs_used = 1;
1008 write_register (E_D0_REGNUM, struct_addr);
1009 }
1010 else
1011 regs_used = 0;
1012
342ee437
MS
1013 /* Push all arguments onto the stack. */
1014 for (argnum = 0; argnum < nargs; argnum++)
1015 {
1fb1ca27
MS
1016 /* FIXME what about structs? Unions? */
1017 if (TYPE_CODE (value_type (*args)) == TYPE_CODE_STRUCT
1018 && TYPE_LENGTH (value_type (*args)) > 8)
1019 {
1020 /* Change to pointer-to-type. */
1021 arg_len = push_size;
1022 store_unsigned_integer (valbuf, push_size,
1023 VALUE_ADDRESS (*args));
1024 val = &valbuf[0];
1025 }
1026 else
1027 {
1028 arg_len = TYPE_LENGTH (value_type (*args));
1029 val = (char *) value_contents (*args);
1030 }
342ee437
MS
1031
1032 while (regs_used < 2 && arg_len > 0)
1033 {
1fb1ca27
MS
1034 write_register (regs_used,
1035 extract_unsigned_integer (val, push_size));
342ee437
MS
1036 val += push_size;
1037 arg_len -= push_size;
1038 regs_used++;
1039 }
1040
1041 while (arg_len > 0)
1042 {
1043 write_memory (sp + stack_offset, val, push_size);
1044 arg_len -= push_size;
1045 val += push_size;
1046 stack_offset += push_size;
1047 }
1048
1049 args++;
1050 }
1051
1052 /* Make space for the flushback area. */
1053 sp -= 8;
1054
1055 /* Push the return address that contains the magic breakpoint. */
1056 sp -= 4;
1057 write_memory_unsigned_integer (sp, push_size, bp_addr);
a64ae7e0
CV
1058
1059 /* The CPU also writes the return address always into the
1060 MDR register on "call". */
1061 regcache_cooked_write_unsigned (regcache, E_MDR_REGNUM, bp_addr);
1062
342ee437
MS
1063 /* Update $sp. */
1064 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp);
1065 return sp;
1066}
1067
336c28c5
KB
1068/* If DWARF2 is a register number appearing in Dwarf2 debug info, then
1069 mn10300_dwarf2_reg_to_regnum (DWARF2) is the corresponding GDB
1070 register number. Why don't Dwarf2 and GDB use the same numbering?
1071 Who knows? But since people have object files lying around with
1072 the existing Dwarf2 numbering, and other people have written stubs
1073 to work with the existing GDB, neither of them can change. So we
1074 just have to cope. */
1075static int
1076mn10300_dwarf2_reg_to_regnum (int dwarf2)
1077{
1078 /* This table is supposed to be shaped like the REGISTER_NAMES
1079 initializer in gcc/config/mn10300/mn10300.h. Registers which
1080 appear in GCC's numbering, but have no counterpart in GDB's
1081 world, are marked with a -1. */
1082 static int dwarf2_to_gdb[] = {
1083 0, 1, 2, 3, 4, 5, 6, 7, -1, 8,
1084 15, 16, 17, 18, 19, 20, 21, 22,
1085 32, 33, 34, 35, 36, 37, 38, 39,
1086 40, 41, 42, 43, 44, 45, 46, 47,
1087 48, 49, 50, 51, 52, 53, 54, 55,
1088 56, 57, 58, 59, 60, 61, 62, 63
1089 };
1090
1091 if (dwarf2 < 0
52f0b832 1092 || dwarf2 >= ARRAY_SIZE (dwarf2_to_gdb)
336c28c5 1093 || dwarf2_to_gdb[dwarf2] == -1)
154b82dc
KB
1094 {
1095 warning (_("Bogus register number in debug info: %d"), dwarf2);
1096 return 0;
1097 }
336c28c5
KB
1098
1099 return dwarf2_to_gdb[dwarf2];
1100}
342ee437
MS
1101
1102static struct gdbarch *
1103mn10300_gdbarch_init (struct gdbarch_info info,
1104 struct gdbarch_list *arches)
1105{
1106 struct gdbarch *gdbarch;
1107 struct gdbarch_tdep *tdep;
4640dd91 1108 int num_regs;
342ee437
MS
1109
1110 arches = gdbarch_list_lookup_by_info (arches, &info);
1111 if (arches != NULL)
1112 return arches->gdbarch;
1113
1114 tdep = xmalloc (sizeof (struct gdbarch_tdep));
1115 gdbarch = gdbarch_alloc (&info, tdep);
1116
1117 switch (info.bfd_arch_info->mach)
1118 {
1119 case 0:
1120 case bfd_mach_mn10300:
1121 set_gdbarch_register_name (gdbarch, mn10300_generic_register_name);
1122 tdep->am33_mode = 0;
4640dd91 1123 num_regs = 32;
342ee437
MS
1124 break;
1125 case bfd_mach_am33:
1126 set_gdbarch_register_name (gdbarch, am33_register_name);
1127 tdep->am33_mode = 1;
4640dd91
KB
1128 num_regs = 32;
1129 break;
1130 case bfd_mach_am33_2:
1131 set_gdbarch_register_name (gdbarch, am33_2_register_name);
1132 tdep->am33_mode = 2;
1133 num_regs = 64;
1134 set_gdbarch_fp0_regnum (gdbarch, 32);
342ee437
MS
1135 break;
1136 default:
1137 internal_error (__FILE__, __LINE__,
1138 _("mn10300_gdbarch_init: Unknown mn10300 variant"));
1139 break;
1140 }
1141
1142 /* Registers. */
4640dd91 1143 set_gdbarch_num_regs (gdbarch, num_regs);
342ee437
MS
1144 set_gdbarch_register_type (gdbarch, mn10300_register_type);
1145 set_gdbarch_skip_prologue (gdbarch, mn10300_skip_prologue);
1146 set_gdbarch_read_pc (gdbarch, mn10300_read_pc);
1147 set_gdbarch_write_pc (gdbarch, mn10300_write_pc);
1148 set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM);
1149 set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM);
336c28c5 1150 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mn10300_dwarf2_reg_to_regnum);
342ee437
MS
1151
1152 /* Stack unwinding. */
1153 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1154 /* Breakpoints. */
1155 set_gdbarch_breakpoint_from_pc (gdbarch, mn10300_breakpoint_from_pc);
1156 /* decr_pc_after_break? */
1157 /* Disassembly. */
1158 set_gdbarch_print_insn (gdbarch, print_insn_mn10300);
1159
1160 /* Stage 2 */
99fe5f9d 1161 set_gdbarch_return_value (gdbarch, mn10300_return_value);
342ee437
MS
1162
1163 /* Stage 3 -- get target calls working. */
1164 set_gdbarch_push_dummy_call (gdbarch, mn10300_push_dummy_call);
1165 /* set_gdbarch_return_value (store, extract) */
1166
1167
1168 mn10300_frame_unwind_init (gdbarch);
1169
697e3bc9
KB
1170 /* Hook in ABI-specific overrides, if they have been registered. */
1171 gdbarch_init_osabi (info, gdbarch);
1172
342ee437
MS
1173 return gdbarch;
1174}
1175
1176/* Dump out the mn10300 specific architecture information. */
1177
1178static void
1179mn10300_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
1180{
1181 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1182 fprintf_unfiltered (file, "mn10300_dump_tdep: am33_mode = %d\n",
1183 tdep->am33_mode);
1184}
1185
1186void
1187_initialize_mn10300_tdep (void)
1188{
1189 gdbarch_register (bfd_arch_mn10300, mn10300_gdbarch_init, mn10300_dump_tdep);
1190}
1191