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a994fec4 | 1 | /* Target-dependent code for the 32-bit OpenRISC 1000, for the GDB. |
4a94e368 | 2 | Copyright (C) 2008-2022 Free Software Foundation, Inc. |
a994fec4 FJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
19 | #include "defs.h" | |
20 | #include "frame.h" | |
21 | #include "inferior.h" | |
22 | #include "symtab.h" | |
23 | #include "value.h" | |
24 | #include "gdbcmd.h" | |
25 | #include "language.h" | |
26 | #include "gdbcore.h" | |
27 | #include "symfile.h" | |
28 | #include "objfiles.h" | |
29 | #include "gdbtypes.h" | |
30 | #include "target.h" | |
31 | #include "regcache.h" | |
32 | #include "safe-ctype.h" | |
33 | #include "block.h" | |
34 | #include "reggroups.h" | |
35 | #include "arch-utils.h" | |
a994fec4 FJ |
36 | #include "frame-unwind.h" |
37 | #include "frame-base.h" | |
82ca8957 | 38 | #include "dwarf2/frame.h" |
a994fec4 FJ |
39 | #include "trad-frame.h" |
40 | #include "regset.h" | |
41 | #include "remote.h" | |
42 | #include "target-descriptions.h" | |
43 | #include <inttypes.h> | |
44 | #include "dis-asm.h" | |
76eb8ef1 | 45 | #include "gdbarch.h" |
a994fec4 FJ |
46 | |
47 | /* OpenRISC specific includes. */ | |
48 | #include "or1k-tdep.h" | |
49 | #include "features/or1k.c" | |
50 | \f | |
51 | ||
52 | /* Global debug flag. */ | |
53 | ||
491144b5 | 54 | static bool or1k_debug = false; |
a994fec4 FJ |
55 | |
56 | static void | |
57 | show_or1k_debug (struct ui_file *file, int from_tty, | |
38af1824 | 58 | struct cmd_list_element *c, const char *value) |
a994fec4 | 59 | { |
6cb06a8c | 60 | gdb_printf (file, _("OpenRISC debugging is %s.\n"), value); |
a994fec4 FJ |
61 | } |
62 | ||
63 | ||
64 | /* The target-dependent structure for gdbarch. */ | |
65 | ||
ab25d9bb | 66 | struct or1k_gdbarch_tdep : gdbarch_tdep_base |
a994fec4 | 67 | { |
345bd07c SM |
68 | int bytes_per_word = 0; |
69 | int bytes_per_address = 0; | |
70 | CGEN_CPU_DESC gdb_cgen_cpu_desc = nullptr; | |
a994fec4 FJ |
71 | }; |
72 | ||
73 | /* Support functions for the architecture definition. */ | |
74 | ||
75 | /* Get an instruction from memory. */ | |
76 | ||
77 | static ULONGEST | |
78 | or1k_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) | |
79 | { | |
80 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
81 | gdb_byte buf[OR1K_INSTLEN]; | |
82 | ||
83 | if (target_read_code (addr, buf, OR1K_INSTLEN)) { | |
84 | memory_error (TARGET_XFER_E_IO, addr); | |
85 | } | |
86 | ||
87 | return extract_unsigned_integer (buf, OR1K_INSTLEN, byte_order); | |
88 | } | |
89 | ||
90 | /* Generic function to read bits from an instruction. */ | |
91 | ||
92 | static bool | |
93 | or1k_analyse_inst (uint32_t inst, const char *format, ...) | |
94 | { | |
95 | /* Break out each field in turn, validating as we go. */ | |
96 | va_list ap; | |
97 | int i; | |
98 | int iptr = 0; /* Instruction pointer */ | |
99 | ||
100 | va_start (ap, format); | |
101 | ||
102 | for (i = 0; 0 != format[i];) | |
103 | { | |
104 | const char *start_ptr; | |
105 | char *end_ptr; | |
106 | ||
107 | uint32_t bits; /* Bit substring of interest */ | |
108 | uint32_t width; /* Substring width */ | |
109 | uint32_t *arg_ptr; | |
110 | ||
111 | switch (format[i]) | |
112 | { | |
113 | case ' ': | |
114 | i++; | |
115 | break; /* Formatting: ignored */ | |
116 | ||
117 | case '0': | |
118 | case '1': /* Constant bit field */ | |
119 | bits = (inst >> (OR1K_INSTBITLEN - iptr - 1)) & 0x1; | |
120 | ||
121 | if ((format[i] - '0') != bits) | |
122 | return false; | |
123 | ||
124 | iptr++; | |
125 | i++; | |
126 | break; | |
127 | ||
128 | case '%': /* Bit field */ | |
129 | i++; | |
130 | start_ptr = &(format[i]); | |
131 | width = strtoul (start_ptr, &end_ptr, 10); | |
132 | ||
133 | /* Check we got something, and if so skip on. */ | |
134 | if (start_ptr == end_ptr) | |
96647014 | 135 | error (_("bitstring \"%s\" at offset %d has no length field."), |
38af1824 | 136 | format, i); |
a994fec4 FJ |
137 | |
138 | i += end_ptr - start_ptr; | |
139 | ||
140 | /* Look for and skip the terminating 'b'. If it's not there, we | |
141 | still give a fatal error, because these are fixed strings that | |
142 | just should not be wrong. */ | |
143 | if ('b' != format[i++]) | |
96647014 | 144 | error (_("bitstring \"%s\" at offset %d has no terminating 'b'."), |
38af1824 | 145 | format, i); |
a994fec4 FJ |
146 | |
147 | /* Break out the field. There is a special case with a bit width | |
148 | of 32. */ | |
149 | if (32 == width) | |
150 | bits = inst; | |
151 | else | |
152 | bits = | |
153 | (inst >> (OR1K_INSTBITLEN - iptr - width)) & ((1 << width) - 1); | |
154 | ||
155 | arg_ptr = va_arg (ap, uint32_t *); | |
156 | *arg_ptr = bits; | |
157 | iptr += width; | |
158 | break; | |
159 | ||
160 | default: | |
96647014 | 161 | error (_("invalid character in bitstring \"%s\" at offset %d."), |
38af1824 | 162 | format, i); |
a994fec4 FJ |
163 | break; |
164 | } | |
165 | } | |
166 | ||
167 | /* Is the length OK? */ | |
168 | gdb_assert (OR1K_INSTBITLEN == iptr); | |
169 | ||
170 | return true; /* Success */ | |
171 | } | |
172 | ||
173 | /* This is used to parse l.addi instructions during various prologue | |
174 | analysis routines. The l.addi instruction has semantics: | |
175 | ||
176 | assembly: l.addi rD,rA,I | |
177 | implementation: rD = rA + sign_extend(Immediate) | |
178 | ||
179 | The rd_ptr, ra_ptr and simm_ptr must be non NULL pointers and are used | |
180 | to store the parse results. Upon successful parsing true is returned, | |
181 | false on failure. */ | |
182 | ||
183 | static bool | |
184 | or1k_analyse_l_addi (uint32_t inst, unsigned int *rd_ptr, | |
185 | unsigned int *ra_ptr, int *simm_ptr) | |
186 | { | |
187 | /* Instruction fields */ | |
188 | uint32_t rd, ra, i; | |
189 | ||
190 | if (or1k_analyse_inst (inst, "10 0111 %5b %5b %16b", &rd, &ra, &i)) | |
191 | { | |
192 | /* Found it. Construct the result fields. */ | |
193 | *rd_ptr = (unsigned int) rd; | |
194 | *ra_ptr = (unsigned int) ra; | |
195 | *simm_ptr = (int) (((i & 0x8000) == 0x8000) ? 0xffff0000 | i : i); | |
196 | ||
197 | return true; /* Success */ | |
198 | } | |
199 | else | |
200 | return false; /* Failure */ | |
201 | } | |
202 | ||
203 | /* This is used to to parse store instructions during various prologue | |
204 | analysis routines. The l.sw instruction has semantics: | |
205 | ||
206 | assembly: l.sw I(rA),rB | |
207 | implementation: store rB contents to memory at effective address of | |
208 | rA + sign_extend(Immediate) | |
209 | ||
210 | The simm_ptr, ra_ptr and rb_ptr must be non NULL pointers and are used | |
211 | to store the parse results. Upon successful parsing true is returned, | |
212 | false on failure. */ | |
213 | ||
214 | static bool | |
215 | or1k_analyse_l_sw (uint32_t inst, int *simm_ptr, unsigned int *ra_ptr, | |
216 | unsigned int *rb_ptr) | |
217 | { | |
218 | /* Instruction fields */ | |
219 | uint32_t ihi, ilo, ra, rb; | |
220 | ||
221 | if (or1k_analyse_inst (inst, "11 0101 %5b %5b %5b %11b", &ihi, &ra, &rb, | |
222 | &ilo)) | |
223 | ||
224 | { | |
225 | /* Found it. Construct the result fields. */ | |
226 | *simm_ptr = (int) ((ihi << 11) | ilo); | |
227 | *simm_ptr |= ((ihi & 0x10) == 0x10) ? 0xffff0000 : 0; | |
228 | ||
229 | *ra_ptr = (unsigned int) ra; | |
230 | *rb_ptr = (unsigned int) rb; | |
231 | ||
232 | return true; /* Success */ | |
233 | } | |
234 | else | |
235 | return false; /* Failure */ | |
236 | } | |
237 | \f | |
238 | ||
239 | /* Functions defining the architecture. */ | |
240 | ||
241 | /* Implement the return_value gdbarch method. */ | |
242 | ||
243 | static enum return_value_convention | |
244 | or1k_return_value (struct gdbarch *gdbarch, struct value *functype, | |
245 | struct type *valtype, struct regcache *regcache, | |
246 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
247 | { | |
248 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
78134374 | 249 | enum type_code rv_type = valtype->code (); |
df86565b | 250 | unsigned int rv_size = valtype->length (); |
08106042 | 251 | or1k_gdbarch_tdep *tdep = gdbarch_tdep<or1k_gdbarch_tdep> (gdbarch); |
345bd07c | 252 | int bpw = tdep->bytes_per_word; |
a994fec4 FJ |
253 | |
254 | /* Deal with struct/union as addresses. If an array won't fit in a | |
255 | single register it is returned as address. Anything larger than 2 | |
256 | registers needs to also be passed as address (matches gcc | |
257 | default_return_in_memory). */ | |
258 | if ((TYPE_CODE_STRUCT == rv_type) || (TYPE_CODE_UNION == rv_type) | |
259 | || ((TYPE_CODE_ARRAY == rv_type) && (rv_size > bpw)) | |
260 | || (rv_size > 2 * bpw)) | |
261 | { | |
262 | if (readbuf != NULL) | |
263 | { | |
264 | ULONGEST tmp; | |
265 | ||
266 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp); | |
267 | read_memory (tmp, readbuf, rv_size); | |
268 | } | |
269 | if (writebuf != NULL) | |
270 | { | |
271 | ULONGEST tmp; | |
272 | ||
273 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp); | |
274 | write_memory (tmp, writebuf, rv_size); | |
275 | } | |
276 | ||
277 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
278 | } | |
279 | ||
280 | if (rv_size <= bpw) | |
281 | { | |
282 | /* Up to one word scalars are returned in R11. */ | |
283 | if (readbuf != NULL) | |
284 | { | |
285 | ULONGEST tmp; | |
286 | ||
287 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, &tmp); | |
288 | store_unsigned_integer (readbuf, rv_size, byte_order, tmp); | |
289 | ||
290 | } | |
291 | if (writebuf != NULL) | |
292 | { | |
293 | gdb_byte *buf = XCNEWVEC(gdb_byte, bpw); | |
294 | ||
295 | if (BFD_ENDIAN_BIG == byte_order) | |
296 | memcpy (buf + (sizeof (gdb_byte) * bpw) - rv_size, writebuf, | |
297 | rv_size); | |
298 | else | |
299 | memcpy (buf, writebuf, rv_size); | |
300 | ||
b66f5587 | 301 | regcache->cooked_write (OR1K_RV_REGNUM, buf); |
a994fec4 FJ |
302 | |
303 | free (buf); | |
304 | } | |
305 | } | |
306 | else | |
307 | { | |
308 | /* 2 word scalars are returned in r11/r12 (with the MS word in r11). */ | |
309 | if (readbuf != NULL) | |
310 | { | |
311 | ULONGEST tmp_lo; | |
312 | ULONGEST tmp_hi; | |
313 | ULONGEST tmp; | |
314 | ||
315 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM, | |
316 | &tmp_hi); | |
317 | regcache_cooked_read_unsigned (regcache, OR1K_RV_REGNUM + 1, | |
318 | &tmp_lo); | |
319 | tmp = (tmp_hi << (bpw * 8)) | tmp_lo; | |
320 | ||
321 | store_unsigned_integer (readbuf, rv_size, byte_order, tmp); | |
322 | } | |
323 | if (writebuf != NULL) | |
324 | { | |
325 | gdb_byte *buf_lo = XCNEWVEC(gdb_byte, bpw); | |
326 | gdb_byte *buf_hi = XCNEWVEC(gdb_byte, bpw); | |
327 | ||
328 | /* This is cheating. We assume that we fit in 2 words exactly, | |
329 | which wouldn't work if we had (say) a 6-byte scalar type on a | |
330 | big endian architecture (with the OpenRISC 1000 usually is). */ | |
331 | memcpy (buf_hi, writebuf, rv_size - bpw); | |
332 | memcpy (buf_lo, writebuf + bpw, bpw); | |
333 | ||
b66f5587 SM |
334 | regcache->cooked_write (OR1K_RV_REGNUM, buf_hi); |
335 | regcache->cooked_write (OR1K_RV_REGNUM + 1, buf_lo); | |
a994fec4 FJ |
336 | |
337 | free (buf_lo); | |
338 | free (buf_hi); | |
339 | } | |
340 | } | |
341 | ||
342 | return RETURN_VALUE_REGISTER_CONVENTION; | |
343 | } | |
344 | ||
345 | /* OR1K always uses a l.trap instruction for breakpoints. */ | |
346 | ||
347 | constexpr gdb_byte or1k_break_insn[] = {0x21, 0x00, 0x00, 0x01}; | |
348 | ||
349 | typedef BP_MANIPULATION (or1k_break_insn) or1k_breakpoint; | |
350 | ||
57293590 SH |
351 | static int |
352 | or1k_delay_slot_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
353 | { | |
354 | const CGEN_INSN *insn; | |
355 | CGEN_FIELDS tmp_fields; | |
08106042 | 356 | or1k_gdbarch_tdep *tdep = gdbarch_tdep<or1k_gdbarch_tdep> (gdbarch); |
57293590 SH |
357 | |
358 | insn = cgen_lookup_insn (tdep->gdb_cgen_cpu_desc, | |
359 | NULL, | |
360 | or1k_fetch_instruction (gdbarch, pc), | |
361 | NULL, 32, &tmp_fields, 0); | |
362 | ||
363 | /* NULL here would mean the last instruction was not understood by cgen. | |
364 | This should not usually happen, but if does its not a delay slot. */ | |
365 | if (insn == NULL) | |
366 | return 0; | |
367 | ||
368 | /* TODO: we should add a delay slot flag to the CGEN_INSN and remove | |
369 | this hard coded test. */ | |
370 | return ((CGEN_INSN_NUM (insn) == OR1K_INSN_L_J) | |
371 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JAL) | |
372 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JR) | |
373 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_JALR) | |
374 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_BNF) | |
375 | || (CGEN_INSN_NUM (insn) == OR1K_INSN_L_BF)); | |
376 | } | |
377 | ||
a994fec4 FJ |
378 | /* Implement the single_step_through_delay gdbarch method. */ |
379 | ||
380 | static int | |
381 | or1k_single_step_through_delay (struct gdbarch *gdbarch, | |
382 | struct frame_info *this_frame) | |
383 | { | |
384 | ULONGEST val; | |
385 | CORE_ADDR ppc; | |
386 | CORE_ADDR npc; | |
a994fec4 | 387 | struct regcache *regcache = get_current_regcache (); |
a994fec4 FJ |
388 | |
389 | /* Get the previous and current instruction addresses. If they are not | |
390 | adjacent, we cannot be in a delay slot. */ | |
391 | regcache_cooked_read_unsigned (regcache, OR1K_PPC_REGNUM, &val); | |
392 | ppc = (CORE_ADDR) val; | |
393 | regcache_cooked_read_unsigned (regcache, OR1K_NPC_REGNUM, &val); | |
394 | npc = (CORE_ADDR) val; | |
395 | ||
396 | if (0x4 != (npc - ppc)) | |
397 | return 0; | |
398 | ||
57293590 SH |
399 | return or1k_delay_slot_p (gdbarch, ppc); |
400 | } | |
a994fec4 | 401 | |
57293590 SH |
402 | /* or1k_software_single_step() is called just before we want to resume |
403 | the inferior, if we want to single-step it but there is no hardware | |
404 | or kernel single-step support (OpenRISC on GNU/Linux for example). We | |
405 | find the target of the coming instruction skipping over delay slots | |
406 | and breakpoint it. */ | |
a994fec4 | 407 | |
57293590 SH |
408 | std::vector<CORE_ADDR> |
409 | or1k_software_single_step (struct regcache *regcache) | |
410 | { | |
411 | struct gdbarch *gdbarch = regcache->arch (); | |
412 | CORE_ADDR pc, next_pc; | |
413 | ||
414 | pc = regcache_read_pc (regcache); | |
415 | next_pc = pc + 4; | |
416 | ||
417 | if (or1k_delay_slot_p (gdbarch, pc)) | |
418 | next_pc += 4; | |
419 | ||
420 | return {next_pc}; | |
a994fec4 FJ |
421 | } |
422 | ||
423 | /* Name for or1k general registers. */ | |
424 | ||
425 | static const char *const or1k_reg_names[OR1K_NUM_REGS] = { | |
426 | /* general purpose registers */ | |
427 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
428 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
429 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
430 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
431 | ||
432 | /* previous program counter, next program counter and status register */ | |
433 | "ppc", "npc", "sr" | |
434 | }; | |
435 | ||
436 | static int | |
437 | or1k_is_arg_reg (unsigned int regnum) | |
438 | { | |
439 | return (OR1K_FIRST_ARG_REGNUM <= regnum) | |
440 | && (regnum <= OR1K_LAST_ARG_REGNUM); | |
441 | } | |
442 | ||
443 | static int | |
444 | or1k_is_callee_saved_reg (unsigned int regnum) | |
445 | { | |
446 | return (OR1K_FIRST_SAVED_REGNUM <= regnum) && (0 == regnum % 2); | |
447 | } | |
448 | ||
449 | /* Implement the skip_prologue gdbarch method. */ | |
450 | ||
451 | static CORE_ADDR | |
452 | or1k_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
453 | { | |
454 | CORE_ADDR start_pc; | |
455 | CORE_ADDR addr; | |
456 | uint32_t inst; | |
457 | ||
458 | unsigned int ra, rb, rd; /* for instruction analysis */ | |
459 | int simm; | |
460 | ||
461 | int frame_size = 0; | |
462 | ||
463 | /* Try using SAL first if we have symbolic information available. This | |
464 | only works for DWARF 2, not STABS. */ | |
465 | ||
466 | if (find_pc_partial_function (pc, NULL, &start_pc, NULL)) | |
467 | { | |
468 | CORE_ADDR prologue_end = skip_prologue_using_sal (gdbarch, pc); | |
469 | ||
470 | if (0 != prologue_end) | |
471 | { | |
472 | struct symtab_and_line prologue_sal = find_pc_line (start_pc, 0); | |
473 | struct compunit_symtab *compunit | |
c6159652 | 474 | = prologue_sal.symtab->compunit (); |
422f1ea2 | 475 | const char *debug_format = compunit->debugformat (); |
a994fec4 FJ |
476 | |
477 | if ((NULL != debug_format) | |
478 | && (strlen ("dwarf") <= strlen (debug_format)) | |
479 | && (0 == strncasecmp ("dwarf", debug_format, strlen ("dwarf")))) | |
480 | return (prologue_end > pc) ? prologue_end : pc; | |
481 | } | |
482 | } | |
483 | ||
484 | /* Look to see if we can find any of the standard prologue sequence. All | |
485 | quite difficult, since any or all of it may be missing. So this is | |
486 | just a best guess! */ | |
487 | ||
488 | addr = pc; /* Where we have got to */ | |
489 | inst = or1k_fetch_instruction (gdbarch, addr); | |
490 | ||
491 | /* Look for the new stack pointer being set up. */ | |
492 | if (or1k_analyse_l_addi (inst, &rd, &ra, &simm) | |
493 | && (OR1K_SP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) | |
494 | && (simm < 0) && (0 == (simm % 4))) | |
495 | { | |
496 | frame_size = -simm; | |
497 | addr += OR1K_INSTLEN; | |
498 | inst = or1k_fetch_instruction (gdbarch, addr); | |
499 | } | |
500 | ||
501 | /* Look for the frame pointer being manipulated. */ | |
502 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
503 | && (OR1K_SP_REGNUM == ra) && (OR1K_FP_REGNUM == rb) | |
504 | && (simm >= 0) && (0 == (simm % 4))) | |
505 | { | |
506 | addr += OR1K_INSTLEN; | |
507 | inst = or1k_fetch_instruction (gdbarch, addr); | |
508 | ||
509 | gdb_assert (or1k_analyse_l_addi (inst, &rd, &ra, &simm) | |
510 | && (OR1K_FP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) | |
511 | && (simm == frame_size)); | |
512 | ||
513 | addr += OR1K_INSTLEN; | |
514 | inst = or1k_fetch_instruction (gdbarch, addr); | |
515 | } | |
516 | ||
517 | /* Look for the link register being saved. */ | |
518 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
519 | && (OR1K_SP_REGNUM == ra) && (OR1K_LR_REGNUM == rb) | |
520 | && (simm >= 0) && (0 == (simm % 4))) | |
521 | { | |
522 | addr += OR1K_INSTLEN; | |
523 | inst = or1k_fetch_instruction (gdbarch, addr); | |
524 | } | |
525 | ||
526 | /* Look for arguments or callee-saved register being saved. The register | |
527 | must be one of the arguments (r3-r8) or the 10 callee saved registers | |
528 | (r10, r12, r14, r16, r18, r20, r22, r24, r26, r28, r30). The base | |
529 | register must be the FP (for the args) or the SP (for the callee_saved | |
530 | registers). */ | |
531 | while (1) | |
532 | { | |
533 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
534 | && (((OR1K_FP_REGNUM == ra) && or1k_is_arg_reg (rb)) | |
535 | || ((OR1K_SP_REGNUM == ra) && or1k_is_callee_saved_reg (rb))) | |
536 | && (0 == (simm % 4))) | |
537 | { | |
538 | addr += OR1K_INSTLEN; | |
539 | inst = or1k_fetch_instruction (gdbarch, addr); | |
540 | } | |
541 | else | |
542 | { | |
543 | /* Nothing else to look for. We have found the end of the | |
544 | prologue. */ | |
545 | break; | |
546 | } | |
547 | } | |
548 | return addr; | |
549 | } | |
550 | ||
551 | /* Implement the frame_align gdbarch method. */ | |
552 | ||
553 | static CORE_ADDR | |
554 | or1k_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
555 | { | |
556 | return align_down (sp, OR1K_STACK_ALIGN); | |
557 | } | |
558 | ||
559 | /* Implement the unwind_pc gdbarch method. */ | |
560 | ||
561 | static CORE_ADDR | |
562 | or1k_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
563 | { | |
564 | CORE_ADDR pc; | |
565 | ||
566 | if (or1k_debug) | |
6cb06a8c TT |
567 | gdb_printf (gdb_stdlog, "or1k_unwind_pc, next_frame=%d\n", |
568 | frame_relative_level (next_frame)); | |
a994fec4 FJ |
569 | |
570 | pc = frame_unwind_register_unsigned (next_frame, OR1K_NPC_REGNUM); | |
571 | ||
572 | if (or1k_debug) | |
6cb06a8c TT |
573 | gdb_printf (gdb_stdlog, "or1k_unwind_pc, pc=%s\n", |
574 | paddress (gdbarch, pc)); | |
a994fec4 FJ |
575 | |
576 | return pc; | |
577 | } | |
578 | ||
579 | /* Implement the unwind_sp gdbarch method. */ | |
580 | ||
581 | static CORE_ADDR | |
582 | or1k_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | |
583 | { | |
584 | CORE_ADDR sp; | |
585 | ||
586 | if (or1k_debug) | |
6cb06a8c TT |
587 | gdb_printf (gdb_stdlog, "or1k_unwind_sp, next_frame=%d\n", |
588 | frame_relative_level (next_frame)); | |
a994fec4 FJ |
589 | |
590 | sp = frame_unwind_register_unsigned (next_frame, OR1K_SP_REGNUM); | |
591 | ||
592 | if (or1k_debug) | |
6cb06a8c TT |
593 | gdb_printf (gdb_stdlog, "or1k_unwind_sp, sp=%s\n", |
594 | paddress (gdbarch, sp)); | |
a994fec4 FJ |
595 | |
596 | return sp; | |
597 | } | |
598 | ||
599 | /* Implement the push_dummy_code gdbarch method. */ | |
600 | ||
601 | static CORE_ADDR | |
602 | or1k_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, | |
603 | CORE_ADDR function, struct value **args, int nargs, | |
604 | struct type *value_type, CORE_ADDR * real_pc, | |
605 | CORE_ADDR * bp_addr, struct regcache *regcache) | |
606 | { | |
607 | CORE_ADDR bp_slot; | |
608 | ||
609 | /* Reserve enough room on the stack for our breakpoint instruction. */ | |
610 | bp_slot = sp - 4; | |
611 | /* Store the address of that breakpoint. */ | |
612 | *bp_addr = bp_slot; | |
613 | /* keeping the stack aligned. */ | |
614 | sp = or1k_frame_align (gdbarch, bp_slot); | |
615 | /* The call starts at the callee's entry point. */ | |
616 | *real_pc = function; | |
617 | ||
618 | return sp; | |
619 | } | |
620 | ||
621 | /* Implement the push_dummy_call gdbarch method. */ | |
622 | ||
623 | static CORE_ADDR | |
624 | or1k_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
625 | struct regcache *regcache, CORE_ADDR bp_addr, | |
626 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
627 | function_call_return_method return_method, |
628 | CORE_ADDR struct_addr) | |
a994fec4 FJ |
629 | { |
630 | ||
631 | int argreg; | |
632 | int argnum; | |
633 | int first_stack_arg; | |
634 | int stack_offset = 0; | |
635 | int heap_offset = 0; | |
636 | CORE_ADDR heap_sp = sp - 128; | |
637 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
08106042 | 638 | or1k_gdbarch_tdep *tdep = gdbarch_tdep<or1k_gdbarch_tdep> (gdbarch); |
345bd07c SM |
639 | int bpa = tdep->bytes_per_address; |
640 | int bpw = tdep->bytes_per_word; | |
a994fec4 FJ |
641 | struct type *func_type = value_type (function); |
642 | ||
643 | /* Return address */ | |
644 | regcache_cooked_write_unsigned (regcache, OR1K_LR_REGNUM, bp_addr); | |
645 | ||
646 | /* Register for the next argument. */ | |
647 | argreg = OR1K_FIRST_ARG_REGNUM; | |
648 | ||
649 | /* Location for a returned structure. This is passed as a silent first | |
650 | argument. */ | |
cf84fa6b | 651 | if (return_method == return_method_struct) |
a994fec4 FJ |
652 | { |
653 | regcache_cooked_write_unsigned (regcache, OR1K_FIRST_ARG_REGNUM, | |
654 | struct_addr); | |
655 | argreg++; | |
656 | } | |
657 | ||
658 | /* Put as many args as possible in registers. */ | |
659 | for (argnum = 0; argnum < nargs; argnum++) | |
660 | { | |
661 | const gdb_byte *val; | |
662 | gdb_byte valbuf[sizeof (ULONGEST)]; | |
663 | ||
664 | struct value *arg = args[argnum]; | |
665 | struct type *arg_type = check_typedef (value_type (arg)); | |
df86565b | 666 | int len = arg_type->length (); |
78134374 | 667 | enum type_code typecode = arg_type->code (); |
a994fec4 | 668 | |
a409645d | 669 | if (func_type->has_varargs () && argnum >= func_type->num_fields ()) |
a994fec4 FJ |
670 | break; /* end or regular args, varargs go to stack. */ |
671 | ||
672 | /* Extract the value, either a reference or the data. */ | |
673 | if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode) | |
674 | || (len > bpw * 2)) | |
675 | { | |
676 | CORE_ADDR valaddr = value_address (arg); | |
677 | ||
678 | /* If the arg is fabricated (i.e. 3*i, instead of i) valaddr is | |
679 | undefined. */ | |
680 | if (valaddr == 0) | |
681 | { | |
682 | /* The argument needs to be copied into the target space. | |
683 | Since the bottom of the stack is reserved for function | |
684 | arguments we store this at the these at the top growing | |
685 | down. */ | |
686 | heap_offset += align_up (len, bpw); | |
687 | valaddr = heap_sp + heap_offset; | |
688 | ||
50888e42 | 689 | write_memory (valaddr, value_contents (arg).data (), len); |
a994fec4 FJ |
690 | } |
691 | ||
692 | /* The ABI passes all structures by reference, so get its | |
693 | address. */ | |
694 | store_unsigned_integer (valbuf, bpa, byte_order, valaddr); | |
695 | len = bpa; | |
696 | val = valbuf; | |
697 | } | |
698 | else | |
699 | { | |
700 | /* Everything else, we just get the value. */ | |
50888e42 | 701 | val = value_contents (arg).data (); |
a994fec4 FJ |
702 | } |
703 | ||
704 | /* Stick the value in a register. */ | |
705 | if (len > bpw) | |
706 | { | |
707 | /* Big scalars use two registers, but need NOT be pair aligned. */ | |
708 | ||
709 | if (argreg <= (OR1K_LAST_ARG_REGNUM - 1)) | |
710 | { | |
711 | ULONGEST regval = extract_unsigned_integer (val, len, | |
712 | byte_order); | |
713 | ||
714 | unsigned int bits_per_word = bpw * 8; | |
715 | ULONGEST mask = (((ULONGEST) 1) << bits_per_word) - 1; | |
716 | ULONGEST lo = regval & mask; | |
717 | ULONGEST hi = regval >> bits_per_word; | |
718 | ||
719 | regcache_cooked_write_unsigned (regcache, argreg, hi); | |
720 | regcache_cooked_write_unsigned (regcache, argreg + 1, lo); | |
721 | argreg += 2; | |
722 | } | |
723 | else | |
724 | { | |
725 | /* Run out of regs */ | |
726 | break; | |
727 | } | |
728 | } | |
729 | else if (argreg <= OR1K_LAST_ARG_REGNUM) | |
730 | { | |
731 | /* Smaller scalars fit in a single register. */ | |
732 | regcache_cooked_write_unsigned | |
733 | (regcache, argreg, extract_unsigned_integer (val, len, | |
734 | byte_order)); | |
735 | argreg++; | |
736 | } | |
737 | else | |
738 | { | |
739 | /* Ran out of regs. */ | |
740 | break; | |
741 | } | |
742 | } | |
743 | ||
744 | first_stack_arg = argnum; | |
745 | ||
746 | /* If we get here with argnum < nargs, then arguments remain to be | |
747 | placed on the stack. This is tricky, since they must be pushed in | |
748 | reverse order and the stack in the end must be aligned. The only | |
749 | solution is to do it in two stages, the first to compute the stack | |
750 | size, the second to save the args. */ | |
751 | ||
752 | for (argnum = first_stack_arg; argnum < nargs; argnum++) | |
753 | { | |
754 | struct value *arg = args[argnum]; | |
755 | struct type *arg_type = check_typedef (value_type (arg)); | |
df86565b | 756 | int len = arg_type->length (); |
78134374 | 757 | enum type_code typecode = arg_type->code (); |
a994fec4 FJ |
758 | |
759 | if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode) | |
760 | || (len > bpw * 2)) | |
761 | { | |
762 | /* Structures are passed as addresses. */ | |
763 | sp -= bpa; | |
764 | } | |
765 | else | |
766 | { | |
767 | /* Big scalars use more than one word. Code here allows for | |
768 | future quad-word entities (e.g. long double.) */ | |
769 | sp -= align_up (len, bpw); | |
770 | } | |
771 | ||
772 | /* Ensure our dummy heap doesn't touch the stack, this could only | |
773 | happen if we have many arguments including fabricated arguments. */ | |
774 | gdb_assert (heap_offset == 0 || ((heap_sp + heap_offset) < sp)); | |
775 | } | |
776 | ||
777 | sp = gdbarch_frame_align (gdbarch, sp); | |
778 | stack_offset = 0; | |
779 | ||
780 | /* Push the remaining args on the stack. */ | |
781 | for (argnum = first_stack_arg; argnum < nargs; argnum++) | |
782 | { | |
783 | const gdb_byte *val; | |
784 | gdb_byte valbuf[sizeof (ULONGEST)]; | |
785 | ||
786 | struct value *arg = args[argnum]; | |
787 | struct type *arg_type = check_typedef (value_type (arg)); | |
df86565b | 788 | int len = arg_type->length (); |
78134374 | 789 | enum type_code typecode = arg_type->code (); |
a994fec4 | 790 | /* The EABI passes structures that do not fit in a register by |
dda83cd7 | 791 | reference. In all other cases, pass the structure by value. */ |
a994fec4 FJ |
792 | if ((TYPE_CODE_STRUCT == typecode) || (TYPE_CODE_UNION == typecode) |
793 | || (len > bpw * 2)) | |
794 | { | |
795 | store_unsigned_integer (valbuf, bpa, byte_order, | |
796 | value_address (arg)); | |
797 | len = bpa; | |
798 | val = valbuf; | |
799 | } | |
800 | else | |
50888e42 | 801 | val = value_contents (arg).data (); |
a994fec4 FJ |
802 | |
803 | while (len > 0) | |
804 | { | |
805 | int partial_len = (len < bpw ? len : bpw); | |
806 | ||
807 | write_memory (sp + stack_offset, val, partial_len); | |
808 | stack_offset += align_up (partial_len, bpw); | |
809 | len -= partial_len; | |
810 | val += partial_len; | |
811 | } | |
812 | } | |
813 | ||
814 | /* Save the updated stack pointer. */ | |
815 | regcache_cooked_write_unsigned (regcache, OR1K_SP_REGNUM, sp); | |
816 | ||
817 | if (heap_offset > 0) | |
818 | sp = heap_sp; | |
819 | ||
820 | return sp; | |
821 | } | |
822 | ||
a994fec4 FJ |
823 | \f |
824 | ||
825 | /* Support functions for frame handling. */ | |
826 | ||
827 | /* Initialize a prologue cache | |
828 | ||
829 | We build a cache, saying where registers of the prev frame can be found | |
830 | from the data so far set up in this this. | |
831 | ||
832 | We also compute a unique ID for this frame, based on the function start | |
833 | address and the stack pointer (as it will be, even if it has yet to be | |
834 | computed. | |
835 | ||
836 | STACK FORMAT | |
837 | ============ | |
838 | ||
839 | The OR1K has a falling stack frame and a simple prolog. The Stack | |
840 | pointer is R1 and the frame pointer R2. The frame base is therefore the | |
841 | address held in R2 and the stack pointer (R1) is the frame base of the | |
842 | next frame. | |
843 | ||
844 | l.addi r1,r1,-frame_size # SP now points to end of new stack frame | |
845 | ||
846 | The stack pointer may not be set up in a frameless function (e.g. a | |
847 | simple leaf function). | |
848 | ||
849 | l.sw fp_loc(r1),r2 # old FP saved in new stack frame | |
850 | l.addi r2,r1,frame_size # FP now points to base of new stack frame | |
851 | ||
852 | The frame pointer is not necessarily saved right at the end of the stack | |
853 | frame - OR1K saves enough space for any args to called functions right | |
854 | at the end (this is a difference from the Architecture Manual). | |
855 | ||
856 | l.sw lr_loc(r1),r9 # Link (return) address | |
857 | ||
85102364 | 858 | The link register is usually saved at fp_loc - 4. It may not be saved at |
a994fec4 FJ |
859 | all in a leaf function. |
860 | ||
861 | l.sw reg_loc(r1),ry # Save any callee saved regs | |
862 | ||
863 | The offsets x for the callee saved registers generally (always?) rise in | |
864 | increments of 4, starting at fp_loc + 4. If the frame pointer is | |
865 | omitted (an option to GCC), then it may not be saved at all. There may | |
866 | be no callee saved registers. | |
867 | ||
868 | So in summary none of this may be present. However what is present | |
869 | seems always to follow this fixed order, and occur before any | |
870 | substantive code (it is possible for GCC to have more flexible | |
871 | scheduling of the prologue, but this does not seem to occur for OR1K). | |
872 | ||
873 | ANALYSIS | |
874 | ======== | |
875 | ||
876 | This prolog is used, even for -O3 with GCC. | |
877 | ||
878 | All this analysis must allow for the possibility that the PC is in the | |
879 | middle of the prologue. Data in the cache should only be set up insofar | |
880 | as it has been computed. | |
881 | ||
882 | HOWEVER. The frame_id must be created with the SP *as it will be* at | |
883 | the end of the Prologue. Otherwise a recursive call, checking the frame | |
884 | with the PC at the start address will end up with the same frame_id as | |
885 | the caller. | |
886 | ||
887 | A suite of "helper" routines are used, allowing reuse for | |
888 | or1k_skip_prologue(). | |
889 | ||
890 | Reportedly, this is only valid for frames less than 0x7fff in size. */ | |
891 | ||
892 | static struct trad_frame_cache * | |
893 | or1k_frame_cache (struct frame_info *this_frame, void **prologue_cache) | |
894 | { | |
895 | struct gdbarch *gdbarch; | |
896 | struct trad_frame_cache *info; | |
897 | ||
898 | CORE_ADDR this_pc; | |
899 | CORE_ADDR this_sp; | |
900 | CORE_ADDR this_sp_for_id; | |
901 | int frame_size = 0; | |
902 | ||
903 | CORE_ADDR start_addr; | |
904 | CORE_ADDR end_addr; | |
905 | ||
906 | if (or1k_debug) | |
6cb06a8c TT |
907 | gdb_printf (gdb_stdlog, |
908 | "or1k_frame_cache, prologue_cache = %s\n", | |
909 | host_address_to_string (*prologue_cache)); | |
a994fec4 FJ |
910 | |
911 | /* Nothing to do if we already have this info. */ | |
912 | if (NULL != *prologue_cache) | |
913 | return (struct trad_frame_cache *) *prologue_cache; | |
914 | ||
915 | /* Get a new prologue cache and populate it with default values. */ | |
916 | info = trad_frame_cache_zalloc (this_frame); | |
917 | *prologue_cache = info; | |
918 | ||
919 | /* Find the start address of this function (which is a normal frame, even | |
920 | if the next frame is the sentinel frame) and the end of its prologue. */ | |
921 | this_pc = get_frame_pc (this_frame); | |
922 | find_pc_partial_function (this_pc, NULL, &start_addr, NULL); | |
923 | ||
924 | /* Get the stack pointer if we have one (if there's no process executing | |
925 | yet we won't have a frame. */ | |
926 | this_sp = (NULL == this_frame) ? 0 : | |
927 | get_frame_register_unsigned (this_frame, OR1K_SP_REGNUM); | |
928 | ||
929 | /* Return early if GDB couldn't find the function. */ | |
930 | if (start_addr == 0) | |
931 | { | |
932 | if (or1k_debug) | |
6cb06a8c | 933 | gdb_printf (gdb_stdlog, " couldn't find function\n"); |
a994fec4 FJ |
934 | |
935 | /* JPB: 28-Apr-11. This is a temporary patch, to get round GDB | |
936 | crashing right at the beginning. Build the frame ID as best we | |
937 | can. */ | |
938 | trad_frame_set_id (info, frame_id_build (this_sp, this_pc)); | |
939 | ||
940 | return info; | |
941 | } | |
942 | ||
943 | /* The default frame base of this frame (for ID purposes only - frame | |
944 | base is an overloaded term) is its stack pointer. For now we use the | |
945 | value of the SP register in this frame. However if the PC is in the | |
946 | prologue of this frame, before the SP has been set up, then the value | |
947 | will actually be that of the prev frame, and we'll need to adjust it | |
948 | later. */ | |
949 | trad_frame_set_this_base (info, this_sp); | |
950 | this_sp_for_id = this_sp; | |
951 | ||
952 | /* The default is to find the PC of the previous frame in the link | |
953 | register of this frame. This may be changed if we find the link | |
954 | register was saved on the stack. */ | |
955 | trad_frame_set_reg_realreg (info, OR1K_NPC_REGNUM, OR1K_LR_REGNUM); | |
956 | ||
957 | /* We should only examine code that is in the prologue. This is all code | |
958 | up to (but not including) end_addr. We should only populate the cache | |
959 | while the address is up to (but not including) the PC or end_addr, | |
960 | whichever is first. */ | |
961 | gdbarch = get_frame_arch (this_frame); | |
962 | end_addr = or1k_skip_prologue (gdbarch, start_addr); | |
963 | ||
964 | /* All the following analysis only occurs if we are in the prologue and | |
965 | have executed the code. Check we have a sane prologue size, and if | |
966 | zero we are frameless and can give up here. */ | |
967 | if (end_addr < start_addr) | |
38af1824 SH |
968 | error (_("end addr %s is less than start addr %s"), |
969 | paddress (gdbarch, end_addr), paddress (gdbarch, start_addr)); | |
a994fec4 FJ |
970 | |
971 | if (end_addr == start_addr) | |
972 | frame_size = 0; | |
973 | else | |
974 | { | |
975 | /* We have a frame. Look for the various components. */ | |
976 | CORE_ADDR addr = start_addr; /* Where we have got to */ | |
977 | uint32_t inst = or1k_fetch_instruction (gdbarch, addr); | |
978 | ||
979 | unsigned int ra, rb, rd; /* for instruction analysis */ | |
980 | int simm; | |
981 | ||
982 | /* Look for the new stack pointer being set up. */ | |
983 | if (or1k_analyse_l_addi (inst, &rd, &ra, &simm) | |
984 | && (OR1K_SP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) | |
985 | && (simm < 0) && (0 == (simm % 4))) | |
986 | { | |
987 | frame_size = -simm; | |
988 | addr += OR1K_INSTLEN; | |
989 | inst = or1k_fetch_instruction (gdbarch, addr); | |
990 | ||
991 | /* If the PC has not actually got to this point, then the frame | |
992 | base will be wrong, and we adjust it. | |
993 | ||
994 | If we are past this point, then we need to populate the stack | |
995 | accordingly. */ | |
996 | if (this_pc <= addr) | |
997 | { | |
998 | /* Only do if executing. */ | |
999 | if (0 != this_sp) | |
1000 | { | |
1001 | this_sp_for_id = this_sp + frame_size; | |
1002 | trad_frame_set_this_base (info, this_sp_for_id); | |
1003 | } | |
1004 | } | |
1005 | else | |
1006 | { | |
1007 | /* We are past this point, so the stack pointer of the prev | |
dda83cd7 SM |
1008 | frame is frame_size greater than the stack pointer of this |
1009 | frame. */ | |
a994fec4 FJ |
1010 | trad_frame_set_reg_value (info, OR1K_SP_REGNUM, |
1011 | this_sp + frame_size); | |
1012 | } | |
1013 | } | |
1014 | ||
1015 | /* From now on we are only populating the cache, so we stop once we | |
1016 | get to either the end OR the current PC. */ | |
1017 | end_addr = (this_pc < end_addr) ? this_pc : end_addr; | |
1018 | ||
1019 | /* Look for the frame pointer being manipulated. */ | |
1020 | if ((addr < end_addr) | |
1021 | && or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
1022 | && (OR1K_SP_REGNUM == ra) && (OR1K_FP_REGNUM == rb) | |
1023 | && (simm >= 0) && (0 == (simm % 4))) | |
1024 | { | |
1025 | addr += OR1K_INSTLEN; | |
1026 | inst = or1k_fetch_instruction (gdbarch, addr); | |
1027 | ||
1028 | /* At this stage, we can find the frame pointer of the previous | |
1029 | frame on the stack of the current frame. */ | |
1030 | trad_frame_set_reg_addr (info, OR1K_FP_REGNUM, this_sp + simm); | |
1031 | ||
1032 | /* Look for the new frame pointer being set up. */ | |
1033 | if ((addr < end_addr) | |
1034 | && or1k_analyse_l_addi (inst, &rd, &ra, &simm) | |
1035 | && (OR1K_FP_REGNUM == rd) && (OR1K_SP_REGNUM == ra) | |
1036 | && (simm == frame_size)) | |
1037 | { | |
1038 | addr += OR1K_INSTLEN; | |
1039 | inst = or1k_fetch_instruction (gdbarch, addr); | |
1040 | ||
1041 | /* If we have got this far, the stack pointer of the previous | |
dda83cd7 | 1042 | frame is the frame pointer of this frame. */ |
a994fec4 FJ |
1043 | trad_frame_set_reg_realreg (info, OR1K_SP_REGNUM, |
1044 | OR1K_FP_REGNUM); | |
1045 | } | |
1046 | } | |
1047 | ||
1048 | /* Look for the link register being saved. */ | |
1049 | if ((addr < end_addr) | |
1050 | && or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
1051 | && (OR1K_SP_REGNUM == ra) && (OR1K_LR_REGNUM == rb) | |
1052 | && (simm >= 0) && (0 == (simm % 4))) | |
1053 | { | |
1054 | addr += OR1K_INSTLEN; | |
1055 | inst = or1k_fetch_instruction (gdbarch, addr); | |
1056 | ||
1057 | /* If the link register is saved in the this frame, it holds the | |
1058 | value of the PC in the previous frame. This overwrites the | |
1059 | previous information about finding the PC in the link | |
1060 | register. */ | |
1061 | trad_frame_set_reg_addr (info, OR1K_NPC_REGNUM, this_sp + simm); | |
1062 | } | |
1063 | ||
1064 | /* Look for arguments or callee-saved register being saved. The | |
1065 | register must be one of the arguments (r3-r8) or the 10 callee | |
1066 | saved registers (r10, r12, r14, r16, r18, r20, r22, r24, r26, r28, | |
1067 | r30). The base register must be the FP (for the args) or the SP | |
1068 | (for the callee_saved registers). */ | |
1069 | while (addr < end_addr) | |
1070 | { | |
1071 | if (or1k_analyse_l_sw (inst, &simm, &ra, &rb) | |
1072 | && (((OR1K_FP_REGNUM == ra) && or1k_is_arg_reg (rb)) | |
1073 | || ((OR1K_SP_REGNUM == ra) | |
1074 | && or1k_is_callee_saved_reg (rb))) | |
1075 | && (0 == (simm % 4))) | |
1076 | { | |
1077 | addr += OR1K_INSTLEN; | |
1078 | inst = or1k_fetch_instruction (gdbarch, addr); | |
1079 | ||
1080 | /* The register in the previous frame can be found at this | |
dda83cd7 | 1081 | location in this frame. */ |
a994fec4 FJ |
1082 | trad_frame_set_reg_addr (info, rb, this_sp + simm); |
1083 | } | |
1084 | else | |
1085 | break; /* Not a register save instruction. */ | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | /* Build the frame ID */ | |
1090 | trad_frame_set_id (info, frame_id_build (this_sp_for_id, start_addr)); | |
1091 | ||
1092 | if (or1k_debug) | |
1093 | { | |
6cb06a8c TT |
1094 | gdb_printf (gdb_stdlog, " this_sp_for_id = %s\n", |
1095 | paddress (gdbarch, this_sp_for_id)); | |
1096 | gdb_printf (gdb_stdlog, " start_addr = %s\n", | |
1097 | paddress (gdbarch, start_addr)); | |
a994fec4 FJ |
1098 | } |
1099 | ||
1100 | return info; | |
1101 | } | |
1102 | ||
1103 | /* Implement the this_id function for the stub unwinder. */ | |
1104 | ||
1105 | static void | |
1106 | or1k_frame_this_id (struct frame_info *this_frame, | |
1107 | void **prologue_cache, struct frame_id *this_id) | |
1108 | { | |
1109 | struct trad_frame_cache *info = or1k_frame_cache (this_frame, | |
1110 | prologue_cache); | |
1111 | ||
1112 | trad_frame_get_id (info, this_id); | |
1113 | } | |
1114 | ||
1115 | /* Implement the prev_register function for the stub unwinder. */ | |
1116 | ||
1117 | static struct value * | |
1118 | or1k_frame_prev_register (struct frame_info *this_frame, | |
1119 | void **prologue_cache, int regnum) | |
1120 | { | |
1121 | struct trad_frame_cache *info = or1k_frame_cache (this_frame, | |
1122 | prologue_cache); | |
1123 | ||
1124 | return trad_frame_get_register (info, this_frame, regnum); | |
1125 | } | |
1126 | ||
1127 | /* Data structures for the normal prologue-analysis-based unwinder. */ | |
1128 | ||
1129 | static const struct frame_unwind or1k_frame_unwind = { | |
a154d838 | 1130 | "or1k prologue", |
a994fec4 FJ |
1131 | NORMAL_FRAME, |
1132 | default_frame_unwind_stop_reason, | |
1133 | or1k_frame_this_id, | |
1134 | or1k_frame_prev_register, | |
1135 | NULL, | |
1136 | default_frame_sniffer, | |
1137 | NULL, | |
1138 | }; | |
1139 | ||
1140 | /* Architecture initialization for OpenRISC 1000. */ | |
1141 | ||
1142 | static struct gdbarch * | |
1143 | or1k_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1144 | { | |
1145 | struct gdbarch *gdbarch; | |
a994fec4 | 1146 | const struct bfd_arch_info *binfo; |
c1e1314d | 1147 | tdesc_arch_data_up tdesc_data; |
a994fec4 FJ |
1148 | const struct target_desc *tdesc = info.target_desc; |
1149 | ||
1150 | /* Find a candidate among the list of pre-declared architectures. */ | |
1151 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
1152 | if (NULL != arches) | |
1153 | return arches->gdbarch; | |
1154 | ||
1155 | /* None found, create a new architecture from the information | |
1156 | provided. Can't initialize all the target dependencies until we | |
1157 | actually know which target we are talking to, but put in some defaults | |
1158 | for now. */ | |
1159 | binfo = info.bfd_arch_info; | |
345bd07c | 1160 | or1k_gdbarch_tdep *tdep = new or1k_gdbarch_tdep; |
a994fec4 FJ |
1161 | tdep->bytes_per_word = binfo->bits_per_word / binfo->bits_per_byte; |
1162 | tdep->bytes_per_address = binfo->bits_per_address / binfo->bits_per_byte; | |
1163 | gdbarch = gdbarch_alloc (&info, tdep); | |
1164 | ||
1165 | /* Target data types */ | |
1166 | set_gdbarch_short_bit (gdbarch, 16); | |
1167 | set_gdbarch_int_bit (gdbarch, 32); | |
1168 | set_gdbarch_long_bit (gdbarch, 32); | |
1169 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1170 | set_gdbarch_float_bit (gdbarch, 32); | |
1171 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); | |
1172 | set_gdbarch_double_bit (gdbarch, 64); | |
1173 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
1174 | set_gdbarch_long_double_bit (gdbarch, 64); | |
1175 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double); | |
1176 | set_gdbarch_ptr_bit (gdbarch, binfo->bits_per_address); | |
1177 | set_gdbarch_addr_bit (gdbarch, binfo->bits_per_address); | |
1178 | set_gdbarch_char_signed (gdbarch, 1); | |
1179 | ||
1180 | /* Information about the target architecture */ | |
1181 | set_gdbarch_return_value (gdbarch, or1k_return_value); | |
1182 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, | |
1183 | or1k_breakpoint::kind_from_pc); | |
1184 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1185 | or1k_breakpoint::bp_from_kind); | |
1186 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
1187 | ||
1188 | /* Register architecture */ | |
1189 | set_gdbarch_num_regs (gdbarch, OR1K_NUM_REGS); | |
1190 | set_gdbarch_num_pseudo_regs (gdbarch, OR1K_NUM_PSEUDO_REGS); | |
1191 | set_gdbarch_sp_regnum (gdbarch, OR1K_SP_REGNUM); | |
1192 | set_gdbarch_pc_regnum (gdbarch, OR1K_NPC_REGNUM); | |
1193 | set_gdbarch_ps_regnum (gdbarch, OR1K_SR_REGNUM); | |
1194 | set_gdbarch_deprecated_fp_regnum (gdbarch, OR1K_FP_REGNUM); | |
1195 | ||
1196 | /* Functions to analyse frames */ | |
1197 | set_gdbarch_skip_prologue (gdbarch, or1k_skip_prologue); | |
1198 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1199 | set_gdbarch_frame_align (gdbarch, or1k_frame_align); | |
1200 | set_gdbarch_frame_red_zone_size (gdbarch, OR1K_FRAME_RED_ZONE_SIZE); | |
1201 | ||
1202 | /* Functions to access frame data */ | |
1203 | set_gdbarch_unwind_pc (gdbarch, or1k_unwind_pc); | |
1204 | set_gdbarch_unwind_sp (gdbarch, or1k_unwind_sp); | |
1205 | ||
1206 | /* Functions handling dummy frames */ | |
1207 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); | |
1208 | set_gdbarch_push_dummy_code (gdbarch, or1k_push_dummy_code); | |
1209 | set_gdbarch_push_dummy_call (gdbarch, or1k_push_dummy_call); | |
a994fec4 FJ |
1210 | |
1211 | /* Frame unwinders. Use DWARF debug info if available, otherwise use our | |
1212 | own unwinder. */ | |
1213 | dwarf2_append_unwinders (gdbarch); | |
1214 | frame_unwind_append_unwinder (gdbarch, &or1k_frame_unwind); | |
1215 | ||
1216 | /* Get a CGEN CPU descriptor for this architecture. */ | |
1217 | { | |
1218 | ||
1219 | const char *mach_name = binfo->printable_name; | |
1220 | enum cgen_endian endian = (info.byte_order == BFD_ENDIAN_BIG | |
1221 | ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); | |
1222 | ||
1223 | tdep->gdb_cgen_cpu_desc = | |
1224 | or1k_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, | |
1225 | CGEN_CPU_OPEN_ENDIAN, endian, CGEN_CPU_OPEN_END); | |
1226 | ||
1227 | or1k_cgen_init_asm (tdep->gdb_cgen_cpu_desc); | |
1228 | } | |
1229 | ||
1230 | /* If this mach has a delay slot. */ | |
1231 | if (binfo->mach == bfd_mach_or1k) | |
1232 | set_gdbarch_single_step_through_delay (gdbarch, | |
1233 | or1k_single_step_through_delay); | |
1234 | ||
1235 | if (!tdesc_has_registers (info.target_desc)) | |
1236 | /* Pick a default target description. */ | |
1237 | tdesc = tdesc_or1k; | |
1238 | ||
1239 | /* Check any target description for validity. */ | |
1240 | if (tdesc_has_registers (tdesc)) | |
1241 | { | |
1242 | const struct tdesc_feature *feature; | |
1243 | int valid_p; | |
1244 | int i; | |
1245 | ||
1246 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.or1k.group0"); | |
1247 | if (feature == NULL) | |
dda83cd7 | 1248 | return NULL; |
a994fec4 FJ |
1249 | |
1250 | tdesc_data = tdesc_data_alloc (); | |
1251 | ||
1252 | valid_p = 1; | |
1253 | ||
1254 | for (i = 0; i < OR1K_NUM_REGS; i++) | |
dda83cd7 SM |
1255 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
1256 | or1k_reg_names[i]); | |
a994fec4 FJ |
1257 | |
1258 | if (!valid_p) | |
c1e1314d | 1259 | return NULL; |
a994fec4 FJ |
1260 | } |
1261 | ||
1262 | if (tdesc_data != NULL) | |
e7d69e72 | 1263 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); |
a994fec4 | 1264 | |
42e151bf SH |
1265 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1266 | gdbarch_init_osabi (info, gdbarch); | |
1267 | ||
a994fec4 FJ |
1268 | return gdbarch; |
1269 | } | |
1270 | ||
1271 | /* Dump the target specific data for this architecture. */ | |
1272 | ||
1273 | static void | |
1274 | or1k_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
1275 | { | |
08106042 | 1276 | or1k_gdbarch_tdep *tdep = gdbarch_tdep<or1k_gdbarch_tdep> (gdbarch); |
a994fec4 FJ |
1277 | |
1278 | if (NULL == tdep) | |
1279 | return; /* Nothing to report */ | |
1280 | ||
6cb06a8c TT |
1281 | gdb_printf (file, "or1k_dump_tdep: %d bytes per word\n", |
1282 | tdep->bytes_per_word); | |
1283 | gdb_printf (file, "or1k_dump_tdep: %d bytes per address\n", | |
1284 | tdep->bytes_per_address); | |
a994fec4 FJ |
1285 | } |
1286 | \f | |
1287 | ||
6c265988 | 1288 | void _initialize_or1k_tdep (); |
a994fec4 | 1289 | void |
6c265988 | 1290 | _initialize_or1k_tdep () |
a994fec4 FJ |
1291 | { |
1292 | /* Register this architecture. */ | |
1293 | gdbarch_register (bfd_arch_or1k, or1k_gdbarch_init, or1k_dump_tdep); | |
1294 | ||
1295 | initialize_tdesc_or1k (); | |
1296 | ||
1297 | /* Debugging flag. */ | |
1298 | add_setshow_boolean_cmd ("or1k", class_maintenance, &or1k_debug, | |
1299 | _("Set OpenRISC debugging."), | |
1300 | _("Show OpenRISC debugging."), | |
1301 | _("When on, OpenRISC specific debugging is enabled."), | |
1302 | NULL, | |
1303 | show_or1k_debug, | |
1304 | &setdebuglist, &showdebuglist); | |
1305 | } |