]>
Commit | Line | Data |
---|---|---|
ed65e20b | 1 | /* Target-dependent code for FreeBSD on RISC-V processors. |
1d506c26 | 2 | Copyright (C) 2018-2024 Free Software Foundation, Inc. |
ed65e20b JB |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 3 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
18 | ||
ed65e20b JB |
19 | #include "fbsd-tdep.h" |
20 | #include "osabi.h" | |
21 | #include "riscv-tdep.h" | |
22 | #include "riscv-fbsd-tdep.h" | |
23 | #include "solib-svr4.h" | |
24 | #include "target.h" | |
25 | #include "trad-frame.h" | |
26 | #include "tramp-frame.h" | |
0d12e84c | 27 | #include "gdbarch.h" |
5b6d1e4f | 28 | #include "inferior.h" |
ed65e20b JB |
29 | |
30 | /* Register maps. */ | |
31 | ||
32 | static const struct regcache_map_entry riscv_fbsd_gregmap[] = | |
33 | { | |
34 | { 1, RISCV_RA_REGNUM, 0 }, | |
35 | { 1, RISCV_SP_REGNUM, 0 }, | |
36 | { 1, RISCV_GP_REGNUM, 0 }, | |
37 | { 1, RISCV_TP_REGNUM, 0 }, | |
38 | { 3, 5, 0 }, /* t0 - t2 */ | |
39 | { 4, 28, 0 }, /* t3 - t6 */ | |
40 | { 2, RISCV_FP_REGNUM, 0 }, /* s0 - s1 */ | |
41 | { 10, 18, 0 }, /* s2 - s11 */ | |
42 | { 8, RISCV_A0_REGNUM, 0 }, /* a0 - a7 */ | |
43 | { 1, RISCV_PC_REGNUM, 0 }, | |
44 | { 1, RISCV_CSR_SSTATUS_REGNUM, 0 }, | |
45 | { 0 } | |
46 | }; | |
47 | ||
48 | static const struct regcache_map_entry riscv_fbsd_fpregmap[] = | |
49 | { | |
50 | { 32, RISCV_FIRST_FP_REGNUM, 16 }, | |
51 | { 1, RISCV_CSR_FCSR_REGNUM, 8 }, | |
52 | { 0 } | |
53 | }; | |
54 | ||
ed65e20b JB |
55 | /* Register set definitions. */ |
56 | ||
57 | const struct regset riscv_fbsd_gregset = | |
58 | { | |
6a9ad81c | 59 | riscv_fbsd_gregmap, riscv_supply_regset, regcache_collect_regset |
ed65e20b JB |
60 | }; |
61 | ||
62 | const struct regset riscv_fbsd_fpregset = | |
63 | { | |
6a9ad81c | 64 | riscv_fbsd_fpregmap, riscv_supply_regset, regcache_collect_regset |
ed65e20b JB |
65 | }; |
66 | ||
89203d40 | 67 | /* Implement the "iterate_over_regset_sections" gdbarch method. */ |
ed65e20b JB |
68 | |
69 | static void | |
70 | riscv_fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
71 | iterate_over_regset_sections_cb *cb, | |
72 | void *cb_data, | |
73 | const struct regcache *regcache) | |
74 | { | |
75 | cb (".reg", RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch), | |
76 | RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch), | |
77 | &riscv_fbsd_gregset, NULL, cb_data); | |
78 | cb (".reg2", RISCV_FBSD_SIZEOF_FPREGSET, RISCV_FBSD_SIZEOF_FPREGSET, | |
79 | &riscv_fbsd_fpregset, NULL, cb_data); | |
80 | } | |
81 | ||
82 | /* In a signal frame, sp points to a 'struct sigframe' which is | |
83 | defined as: | |
84 | ||
85 | struct sigframe { | |
86 | siginfo_t sf_si; | |
87 | ucontext_t sf_uc; | |
88 | }; | |
89 | ||
90 | ucontext_t is defined as: | |
91 | ||
92 | struct __ucontext { | |
93 | sigset_t uc_sigmask; | |
94 | mcontext_t uc_mcontext; | |
95 | ... | |
96 | }; | |
97 | ||
98 | The mcontext_t contains the general purpose register set followed | |
99 | by the floating point register set. The floating point register | |
100 | set is only valid if the _MC_FP_VALID flag is set in mc_flags. */ | |
101 | ||
102 | #define RISCV_SIGFRAME_UCONTEXT_OFFSET 80 | |
103 | #define RISCV_UCONTEXT_MCONTEXT_OFFSET 16 | |
104 | #define RISCV_MCONTEXT_FLAG_FP_VALID 0x1 | |
105 | ||
106 | /* Implement the "init" method of struct tramp_frame. */ | |
107 | ||
108 | static void | |
109 | riscv_fbsd_sigframe_init (const struct tramp_frame *self, | |
8480a37e | 110 | const frame_info_ptr &this_frame, |
ed65e20b JB |
111 | struct trad_frame_cache *this_cache, |
112 | CORE_ADDR func) | |
113 | { | |
114 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
115 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
116 | CORE_ADDR sp = get_frame_register_unsigned (this_frame, RISCV_SP_REGNUM); | |
117 | CORE_ADDR mcontext_addr | |
118 | = (sp | |
119 | + RISCV_SIGFRAME_UCONTEXT_OFFSET | |
120 | + RISCV_UCONTEXT_MCONTEXT_OFFSET); | |
121 | gdb_byte buf[4]; | |
ed65e20b JB |
122 | |
123 | trad_frame_set_reg_regmap (this_cache, riscv_fbsd_gregmap, mcontext_addr, | |
124 | RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch)); | |
125 | ||
126 | CORE_ADDR fpregs_addr | |
127 | = mcontext_addr + RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch); | |
128 | CORE_ADDR fp_flags_addr | |
129 | = fpregs_addr + RISCV_FBSD_SIZEOF_FPREGSET; | |
130 | if (target_read_memory (fp_flags_addr, buf, 4) == 0 | |
131 | && (extract_unsigned_integer (buf, 4, byte_order) | |
132 | & RISCV_MCONTEXT_FLAG_FP_VALID)) | |
133 | trad_frame_set_reg_regmap (this_cache, riscv_fbsd_fpregmap, fpregs_addr, | |
134 | RISCV_FBSD_SIZEOF_FPREGSET); | |
135 | ||
136 | trad_frame_set_id (this_cache, frame_id_build (sp, func)); | |
137 | } | |
138 | ||
139 | /* RISC-V supports 16-bit instructions ("C") as well as 32-bit | |
140 | instructions. The signal trampoline on FreeBSD uses a mix of | |
141 | these, but tramp_frame assumes a fixed instruction size. To cope, | |
142 | claim that all instructions are 16 bits and use two "slots" for | |
143 | 32-bit instructions. */ | |
144 | ||
145 | static const struct tramp_frame riscv_fbsd_sigframe = | |
146 | { | |
147 | SIGTRAMP_FRAME, | |
148 | 2, | |
149 | { | |
150 | {0x850a, ULONGEST_MAX}, /* mov a0, sp */ | |
151 | {0x0513, ULONGEST_MAX}, /* addi a0, a0, #SF_UC */ | |
152 | {0x0505, ULONGEST_MAX}, | |
153 | {0x0293, ULONGEST_MAX}, /* li t0, #SYS_sigreturn */ | |
154 | {0x1a10, ULONGEST_MAX}, | |
155 | {0x0073, ULONGEST_MAX}, /* ecall */ | |
156 | {0x0000, ULONGEST_MAX}, | |
157 | {TRAMP_SENTINEL_INSN, ULONGEST_MAX} | |
158 | }, | |
159 | riscv_fbsd_sigframe_init | |
160 | }; | |
161 | ||
b0f87ed0 JB |
162 | /* Implement the "get_thread_local_address" gdbarch method. */ |
163 | ||
164 | static CORE_ADDR | |
165 | riscv_fbsd_get_thread_local_address (struct gdbarch *gdbarch, ptid_t ptid, | |
166 | CORE_ADDR lm_addr, CORE_ADDR offset) | |
167 | { | |
74387712 SM |
168 | regcache *regcache |
169 | = get_thread_arch_regcache (current_inferior (), ptid, gdbarch); | |
b0f87ed0 JB |
170 | |
171 | target_fetch_registers (regcache, RISCV_TP_REGNUM); | |
172 | ||
173 | ULONGEST tp; | |
174 | if (regcache->cooked_read (RISCV_TP_REGNUM, &tp) != REG_VALID) | |
175 | error (_("Unable to fetch %%tp")); | |
176 | ||
177 | /* %tp points to the end of the TCB which contains two pointers. | |
178 | The first pointer in the TCB points to the DTV array. */ | |
179 | CORE_ADDR dtv_addr = tp - (gdbarch_ptr_bit (gdbarch) / 8) * 2; | |
180 | return fbsd_get_thread_local_address (gdbarch, dtv_addr, lm_addr, offset); | |
181 | } | |
182 | ||
ed65e20b JB |
183 | /* Implement the 'init_osabi' method of struct gdb_osabi_handler. */ |
184 | ||
185 | static void | |
186 | riscv_fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
187 | { | |
ed65e20b JB |
188 | /* Generic FreeBSD support. */ |
189 | fbsd_init_abi (info, gdbarch); | |
190 | ||
191 | set_gdbarch_software_single_step (gdbarch, riscv_software_single_step); | |
192 | ||
193 | set_solib_svr4_fetch_link_map_offsets (gdbarch, | |
194 | (riscv_isa_xlen (gdbarch) == 4 | |
195 | ? svr4_ilp32_fetch_link_map_offsets | |
196 | : svr4_lp64_fetch_link_map_offsets)); | |
197 | ||
198 | tramp_frame_prepend_unwinder (gdbarch, &riscv_fbsd_sigframe); | |
199 | ||
200 | set_gdbarch_iterate_over_regset_sections | |
201 | (gdbarch, riscv_fbsd_iterate_over_regset_sections); | |
b0f87ed0 JB |
202 | |
203 | set_gdbarch_fetch_tls_load_module_address (gdbarch, | |
204 | svr4_fetch_objfile_link_map); | |
205 | set_gdbarch_get_thread_local_address (gdbarch, | |
206 | riscv_fbsd_get_thread_local_address); | |
ed65e20b JB |
207 | } |
208 | ||
6c265988 | 209 | void _initialize_riscv_fbsd_tdep (); |
ed65e20b | 210 | void |
6c265988 | 211 | _initialize_riscv_fbsd_tdep () |
ed65e20b JB |
212 | { |
213 | gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_FREEBSD, | |
214 | riscv_fbsd_init_abi); | |
215 | } |