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9058f767
KB		 1/* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
2
28e7fd62 3 Copyright (C) 2011-2013 Free Software Foundation, Inc.
9058f767
KB		 4
5 Contributed by Red Hat, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22#include "defs.h"
23#include "arch-utils.h"
24#include "prologue-value.h"
25#include "target.h"
26#include "regcache.h"
27#include "opcode/rl78.h"
28#include "dis-asm.h"
29#include "gdbtypes.h"
30#include "frame.h"
31#include "frame-unwind.h"
32#include "frame-base.h"
33#include "value.h"
34#include "gdbcore.h"
35#include "dwarf2-frame.h"
c47a44f4 36#include "reggroups.h"
9058f767
KB		 37
38#include "elf/rl78.h"
39#include "elf-bfd.h"
40
41/* Register Banks. */
42
43enum
44{
45 RL78_BANK0 = 0,
46 RL78_BANK1 = 1,
47 RL78_BANK2 = 2,
48 RL78_BANK3 = 3,
49 RL78_NUMBANKS = 4,
50 RL78_REGS_PER_BANK = 8
51};
52
53/* Register Numbers. */
54
55enum
56{
57 /* All general purpose registers are 8 bits wide. */
c47a44f4
KB		 58 RL78_RAW_BANK0_R0_REGNUM = 0,
59 RL78_RAW_BANK0_R1_REGNUM,
60 RL78_RAW_BANK0_R2_REGNUM,
61 RL78_RAW_BANK0_R3_REGNUM,
62 RL78_RAW_BANK0_R4_REGNUM,
63 RL78_RAW_BANK0_R5_REGNUM,
64 RL78_RAW_BANK0_R6_REGNUM,
65 RL78_RAW_BANK0_R7_REGNUM,
66
67 RL78_RAW_BANK1_R0_REGNUM,
68 RL78_RAW_BANK1_R1_REGNUM,
69 RL78_RAW_BANK1_R2_REGNUM,
70 RL78_RAW_BANK1_R3_REGNUM,
71 RL78_RAW_BANK1_R4_REGNUM,
72 RL78_RAW_BANK1_R5_REGNUM,
73 RL78_RAW_BANK1_R6_REGNUM,
74 RL78_RAW_BANK1_R7_REGNUM,
75
76 RL78_RAW_BANK2_R0_REGNUM,
77 RL78_RAW_BANK2_R1_REGNUM,
78 RL78_RAW_BANK2_R2_REGNUM,
79 RL78_RAW_BANK2_R3_REGNUM,
80 RL78_RAW_BANK2_R4_REGNUM,
81 RL78_RAW_BANK2_R5_REGNUM,
82 RL78_RAW_BANK2_R6_REGNUM,
83 RL78_RAW_BANK2_R7_REGNUM,
84
85 RL78_RAW_BANK3_R0_REGNUM,
86 RL78_RAW_BANK3_R1_REGNUM,
87 RL78_RAW_BANK3_R2_REGNUM,
88 RL78_RAW_BANK3_R3_REGNUM,
89 RL78_RAW_BANK3_R4_REGNUM,
90 RL78_RAW_BANK3_R5_REGNUM,
91 RL78_RAW_BANK3_R6_REGNUM,
92 RL78_RAW_BANK3_R7_REGNUM,
93
94 RL78_PSW_REGNUM, /* 8 bits */
95 RL78_ES_REGNUM, /* 8 bits */
96 RL78_CS_REGNUM, /* 8 bits */
97 RL78_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
98
99 /* Fixed address SFRs (some of those above are SFRs too.) */
100 RL78_SPL_REGNUM, /* 8 bits; lower half of SP */
101 RL78_SPH_REGNUM, /* 8 bits; upper half of SP */
102 RL78_PMC_REGNUM, /* 8 bits */
103 RL78_MEM_REGNUM, /* 8 bits ?? */
104
105 RL78_NUM_REGS,
106
107 /* Pseudo registers. */
108 RL78_SP_REGNUM = RL78_NUM_REGS,
109
110 RL78_X_REGNUM,
111 RL78_A_REGNUM,
112 RL78_C_REGNUM,
113 RL78_B_REGNUM,
114 RL78_E_REGNUM,
115 RL78_D_REGNUM,
116 RL78_L_REGNUM,
117 RL78_H_REGNUM,
118
119 RL78_AX_REGNUM,
120 RL78_BC_REGNUM,
121 RL78_DE_REGNUM,
122 RL78_HL_REGNUM,
123
124 RL78_BANK0_R0_REGNUM,
9058f767
KB		 125 RL78_BANK0_R1_REGNUM,
126 RL78_BANK0_R2_REGNUM,
127 RL78_BANK0_R3_REGNUM,
128 RL78_BANK0_R4_REGNUM,
129 RL78_BANK0_R5_REGNUM,
130 RL78_BANK0_R6_REGNUM,
131 RL78_BANK0_R7_REGNUM,
132
133 RL78_BANK1_R0_REGNUM,
134 RL78_BANK1_R1_REGNUM,
135 RL78_BANK1_R2_REGNUM,
136 RL78_BANK1_R3_REGNUM,
137 RL78_BANK1_R4_REGNUM,
138 RL78_BANK1_R5_REGNUM,
139 RL78_BANK1_R6_REGNUM,
140 RL78_BANK1_R7_REGNUM,
141
142 RL78_BANK2_R0_REGNUM,
143 RL78_BANK2_R1_REGNUM,
144 RL78_BANK2_R2_REGNUM,
145 RL78_BANK2_R3_REGNUM,
146 RL78_BANK2_R4_REGNUM,
147 RL78_BANK2_R5_REGNUM,
148 RL78_BANK2_R6_REGNUM,
149 RL78_BANK2_R7_REGNUM,
150
151 RL78_BANK3_R0_REGNUM,
152 RL78_BANK3_R1_REGNUM,
153 RL78_BANK3_R2_REGNUM,
154 RL78_BANK3_R3_REGNUM,
155 RL78_BANK3_R4_REGNUM,
156 RL78_BANK3_R5_REGNUM,
157 RL78_BANK3_R6_REGNUM,
158 RL78_BANK3_R7_REGNUM,
159
c47a44f4 160 RL78_BANK0_RP0_REGNUM,
9058f767
KB		 161 RL78_BANK0_RP1_REGNUM,
162 RL78_BANK0_RP2_REGNUM,
163 RL78_BANK0_RP3_REGNUM,
164
165 RL78_BANK1_RP0_REGNUM,
166 RL78_BANK1_RP1_REGNUM,
167 RL78_BANK1_RP2_REGNUM,
168 RL78_BANK1_RP3_REGNUM,
169
170 RL78_BANK2_RP0_REGNUM,
171 RL78_BANK2_RP1_REGNUM,
172 RL78_BANK2_RP2_REGNUM,
173 RL78_BANK2_RP3_REGNUM,
174
175 RL78_BANK3_RP0_REGNUM,
176 RL78_BANK3_RP1_REGNUM,
177 RL78_BANK3_RP2_REGNUM,
178 RL78_BANK3_RP3_REGNUM,
179
9058f767
KB		 180 RL78_NUM_TOTAL_REGS,
181 RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
182};
183
184/* Architecture specific data. */
185
186struct gdbarch_tdep
187{
188 /* The ELF header flags specify the multilib used. */
189 int elf_flags;
190
191 struct type *rl78_void,
192 *rl78_uint8,
193 *rl78_int8,
194 *rl78_uint16,
195 *rl78_int16,
196 *rl78_uint32,
197 *rl78_int32,
198 *rl78_data_pointer,
199 *rl78_code_pointer;
200};
201
202/* This structure holds the results of a prologue analysis. */
203
204struct rl78_prologue
205{
206 /* The offset from the frame base to the stack pointer --- always
207 zero or negative.
208
209 Calling this a "size" is a bit misleading, but given that the
210 stack grows downwards, using offsets for everything keeps one
211 from going completely sign-crazy: you never change anything's
212 sign for an ADD instruction; always change the second operand's
213 sign for a SUB instruction; and everything takes care of
214 itself. */
215 int frame_size;
216
217 /* Non-zero if this function has initialized the frame pointer from
218 the stack pointer, zero otherwise. */
219 int has_frame_ptr;
220
221 /* If has_frame_ptr is non-zero, this is the offset from the frame
222 base to where the frame pointer points. This is always zero or
223 negative. */
224 int frame_ptr_offset;
225
226 /* The address of the first instruction at which the frame has been
227 set up and the arguments are where the debug info says they are
228 --- as best as we can tell. */
229 CORE_ADDR prologue_end;
230
231 /* reg_offset[R] is the offset from the CFA at which register R is
232 saved, or 1 if register R has not been saved. (Real values are
233 always zero or negative.) */
234 int reg_offset[RL78_NUM_TOTAL_REGS];
235};
236
237/* Implement the "register_type" gdbarch method. */
238
239static struct type *
240rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
241{
242 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
243
244 if (reg_nr == RL78_PC_REGNUM)
245 return tdep->rl78_code_pointer;
246 else if (reg_nr <= RL78_MEM_REGNUM
c47a44f4
KB		 247 || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
248 || (RL78_BANK0_R0_REGNUM <= reg_nr
249 && reg_nr <= RL78_BANK3_R7_REGNUM))
9058f767
KB		 250 return tdep->rl78_int8;
251 else
252 return tdep->rl78_data_pointer;
253}
254
255/* Implement the "register_name" gdbarch method. */
256
257static const char *
258rl78_register_name (struct gdbarch *gdbarch, int regnr)
259{
260 static const char *const reg_names[] =
261 {
c47a44f4
KB		 262 "", /* bank0_r0 */
263 "", /* bank0_r1 */
264 "", /* bank0_r2 */
265 "", /* bank0_r3 */
266 "", /* bank0_r4 */
267 "", /* bank0_r5 */
268 "", /* bank0_r6 */
269 "", /* bank0_r7 */
270
271 "", /* bank1_r0 */
272 "", /* bank1_r1 */
273 "", /* bank1_r2 */
274 "", /* bank1_r3 */
275 "", /* bank1_r4 */
276 "", /* bank1_r5 */
277 "", /* bank1_r6 */
278 "", /* bank1_r7 */
279
280 "", /* bank2_r0 */
281 "", /* bank2_r1 */
282 "", /* bank2_r2 */
283 "", /* bank2_r3 */
284 "", /* bank2_r4 */
285 "", /* bank2_r5 */
286 "", /* bank2_r6 */
287 "", /* bank2_r7 */
288
289 "", /* bank3_r0 */
290 "", /* bank3_r1 */
291 "", /* bank3_r2 */
292 "", /* bank3_r3 */
293 "", /* bank3_r4 */
294 "", /* bank3_r5 */
295 "", /* bank3_r6 */
296 "", /* bank3_r7 */
297
298 "psw",
299 "es",
300 "cs",
301 "pc",
302
303 "", /* spl */
304 "", /* sph */
305 "pmc",
306 "mem",
307
308 "sp",
309
310 "x",
311 "a",
312 "c",
313 "b",
314 "e",
315 "d",
316 "l",
317 "h",
318
319 "ax",
320 "bc",
321 "de",
322 "hl",
323
9058f767
KB		 324 "bank0_r0",
325 "bank0_r1",
326 "bank0_r2",
327 "bank0_r3",
328 "bank0_r4",
329 "bank0_r5",
330 "bank0_r6",
331 "bank0_r7",
332
333 "bank1_r0",
334 "bank1_r1",
335 "bank1_r2",
336 "bank1_r3",
337 "bank1_r4",
338 "bank1_r5",
339 "bank1_r6",
340 "bank1_r7",
341
342 "bank2_r0",
343 "bank2_r1",
344 "bank2_r2",
345 "bank2_r3",
346 "bank2_r4",
347 "bank2_r5",
348 "bank2_r6",
349 "bank2_r7",
350
351 "bank3_r0",
352 "bank3_r1",
353 "bank3_r2",
354 "bank3_r3",
355 "bank3_r4",
356 "bank3_r5",
357 "bank3_r6",
358 "bank3_r7",
359
9058f767
KB		 360 "bank0_rp0",
361 "bank0_rp1",
362 "bank0_rp2",
363 "bank0_rp3",
364
365 "bank1_rp0",
366 "bank1_rp1",
367 "bank1_rp2",
368 "bank1_rp3",
369
370 "bank2_rp0",
371 "bank2_rp1",
372 "bank2_rp2",
373 "bank2_rp3",
374
375 "bank3_rp0",
376 "bank3_rp1",
377 "bank3_rp2",
c47a44f4
KB		 378 "bank3_rp3"
379 };
9058f767 380
c47a44f4
KB		 381 return reg_names[regnr];
382}
9058f767 383
c47a44f4 384/* Implement the "register_reggroup_p" gdbarch method. */
9058f767 385
c47a44f4
KB		 386static int
387rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
388 struct reggroup *group)
389{
390 if (group == all_reggroup)
391 return 1;
9058f767 392
c47a44f4
KB		 393 /* All other registers are saved and restored. */
394 if (group == save_reggroup || group == restore_reggroup)
395 {
b3ce41ea
KB		 396 if ((regnum < RL78_NUM_REGS
397 && regnum != RL78_SPL_REGNUM
398 && regnum != RL78_SPH_REGNUM)
399 || regnum == RL78_SP_REGNUM)
c47a44f4
KB		 400 return 1;
401 else
402 return 0;
403 }
404
405 if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
406 || regnum == RL78_ES_REGNUM
407 || regnum == RL78_CS_REGNUM
408 || regnum == RL78_SPL_REGNUM
409 || regnum == RL78_SPH_REGNUM
410 || regnum == RL78_PMC_REGNUM
411 || regnum == RL78_MEM_REGNUM
412 || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
413 return group == system_reggroup;
414
415 return group == general_reggroup;
9058f767
KB		 416}
417
418/* Strip bits to form an instruction address. (When fetching a
419 32-bit address from the stack, the high eight bits are garbage.
420 This function strips off those unused bits.) */
421
422static CORE_ADDR
423rl78_make_instruction_address (CORE_ADDR addr)
424{
425 return addr & 0xffffff;
426}
427
428/* Set / clear bits necessary to make a data address. */
429
430static CORE_ADDR
431rl78_make_data_address (CORE_ADDR addr)
432{
433 return (addr & 0xffff) | 0xf0000;
434}
435
436/* Implement the "pseudo_register_read" gdbarch method. */
437
438static enum register_status
439rl78_pseudo_register_read (struct gdbarch *gdbarch,
440 struct regcache *regcache,
441 int reg, gdb_byte *buffer)
442{
443 enum register_status status;
444
c47a44f4
KB		 445 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
446 {
447 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
448 + (reg - RL78_BANK0_R0_REGNUM);
449
450 status = regcache_raw_read (regcache, raw_regnum, buffer);
451 }
452 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 453 {
454 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 455 + RL78_RAW_BANK0_R0_REGNUM;
9058f767
KB		 456
457 status = regcache_raw_read (regcache, raw_regnum, buffer);
458 if (status == REG_VALID)
459 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
460 }
461 else if (reg == RL78_SP_REGNUM)
462 {
463 status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
464 if (status == REG_VALID)
465 status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
466 }
467 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
468 {
469 ULONGEST psw;
470
471 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
472 if (status == REG_VALID)
473 {
474 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
475 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 476 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 477 + (reg - RL78_X_REGNUM);
478 status = regcache_raw_read (regcache, raw_regnum, buffer);
479 }
480 }
481 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
482 {
483 ULONGEST psw;
484
485 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
486 if (status == REG_VALID)
487 {
488 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
489 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
c47a44f4 490 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 491 + 2 * (reg - RL78_AX_REGNUM);
492 status = regcache_raw_read (regcache, raw_regnum, buffer);
493 if (status == REG_VALID)
494 status = regcache_raw_read (regcache, raw_regnum + 1,
495 buffer + 1);
496 }
497 }
498 else
499 gdb_assert_not_reached ("invalid pseudo register number");
500 return status;
501}
502
503/* Implement the "pseudo_register_write" gdbarch method. */
504
505static void
506rl78_pseudo_register_write (struct gdbarch *gdbarch,
507 struct regcache *regcache,
508 int reg, const gdb_byte *buffer)
509{
c47a44f4
KB		 510 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
511 {
512 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
513 + (reg - RL78_BANK0_R0_REGNUM);
514
515 regcache_raw_write (regcache, raw_regnum, buffer);
516 }
517 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
9058f767
KB		 518 {
519 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
c47a44f4 520 + RL78_RAW_BANK0_R0_REGNUM;
9058f767
KB		 521
522 regcache_raw_write (regcache, raw_regnum, buffer);
523 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
524 }
525 else if (reg == RL78_SP_REGNUM)
526 {
527 regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
528 regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
529 }
530 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
531 {
532 ULONGEST psw;
533 int bank;
534 int raw_regnum;
535
536 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
537 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
538 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 539 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 540 + (reg - RL78_X_REGNUM);
541 regcache_raw_write (regcache, raw_regnum, buffer);
542 }
543 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
544 {
545 ULONGEST psw;
546 int bank, raw_regnum;
547
548 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
549 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
550 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
c47a44f4 551 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
9058f767
KB		 552 + 2 * (reg - RL78_AX_REGNUM);
553 regcache_raw_write (regcache, raw_regnum, buffer);
554 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
555 }
556 else
557 gdb_assert_not_reached ("invalid pseudo register number");
558}
559
560/* Implement the "breakpoint_from_pc" gdbarch method. */
561
693be288 562static const gdb_byte *
9058f767
KB		 563rl78_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
564 int *lenptr)
565{
566 /* The documented BRK instruction is actually a two byte sequence,
567 {0x61, 0xcc}, but instructions may be as short as one byte.
568 Correspondence with Renesas revealed that the one byte sequence
569 0xff is used when a one byte breakpoint instruction is required. */
570 static gdb_byte breakpoint[] = { 0xff };
571
572 *lenptr = sizeof breakpoint;
573 return breakpoint;
574}
575
576/* Define a "handle" struct for fetching the next opcode. */
577
578struct rl78_get_opcode_byte_handle
579{
580 CORE_ADDR pc;
581};
582
583/* Fetch a byte on behalf of the opcode decoder. HANDLE contains
584 the memory address of the next byte to fetch. If successful,
585 the address in the handle is updated and the byte fetched is
586 returned as the value of the function. If not successful, -1
587 is returned. */
588
589static int
590rl78_get_opcode_byte (void *handle)
591{
592 struct rl78_get_opcode_byte_handle *opcdata = handle;
593 int status;
594 gdb_byte byte;
595
596 status = target_read_memory (opcdata->pc, &byte, 1);
597 if (status == 0)
598 {
599 opcdata->pc += 1;
600 return byte;
601 }
602 else
603 return -1;
604}
605
606/* Function for finding saved registers in a 'struct pv_area'; this
607 function is passed to pv_area_scan.
608
609 If VALUE is a saved register, ADDR says it was saved at a constant
610 offset from the frame base, and SIZE indicates that the whole
611 register was saved, record its offset. */
612
613static void
614check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
615 pv_t value)
616{
617 struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
618
619 if (value.kind == pvk_register
620 && value.k == 0
621 && pv_is_register (addr, RL78_SP_REGNUM)
f5656ead 622 && size == register_size (target_gdbarch (), value.reg))
9058f767
KB		 623 result->reg_offset[value.reg] = addr.k;
624}
625
626/* Analyze a prologue starting at START_PC, going no further than
627 LIMIT_PC. Fill in RESULT as appropriate. */
628
629static void
630rl78_analyze_prologue (CORE_ADDR start_pc,
631 CORE_ADDR limit_pc, struct rl78_prologue *result)
632{
633 CORE_ADDR pc, next_pc;
634 int rn;
635 pv_t reg[RL78_NUM_TOTAL_REGS];
636 struct pv_area *stack;
637 struct cleanup *back_to;
638 CORE_ADDR after_last_frame_setup_insn = start_pc;
639 int bank = 0;
640
641 memset (result, 0, sizeof (*result));
642
643 for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
644 {
645 reg[rn] = pv_register (rn, 0);
646 result->reg_offset[rn] = 1;
647 }
648
f5656ead 649 stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
9058f767
KB		 650 back_to = make_cleanup_free_pv_area (stack);
651
652 /* The call instruction has saved the return address on the stack. */
653 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
654 pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
655
656 pc = start_pc;
657 while (pc < limit_pc)
658 {
659 int bytes_read;
660 struct rl78_get_opcode_byte_handle opcode_handle;
661 RL78_Opcode_Decoded opc;
662
663 opcode_handle.pc = pc;
664 bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
665 &opcode_handle);
666 next_pc = pc + bytes_read;
667
668 if (opc.id == RLO_sel)
669 {
670 bank = opc.op[1].addend;
671 }
672 else if (opc.id == RLO_mov
673 && opc.op[0].type == RL78_Operand_PreDec
674 && opc.op[0].reg == RL78_Reg_SP
675 && opc.op[1].type == RL78_Operand_Register)
676 {
677 int rsrc = (bank * RL78_REGS_PER_BANK)
678 + 2 * (opc.op[1].reg - RL78_Reg_AX);
679
680 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
681 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
682 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
683 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
684 after_last_frame_setup_insn = next_pc;
685 }
686 else if (opc.id == RLO_sub
687 && opc.op[0].type == RL78_Operand_Register
688 && opc.op[0].reg == RL78_Reg_SP
689 && opc.op[1].type == RL78_Operand_Immediate)
690 {
691 int addend = opc.op[1].addend;
692
693 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
694 -addend);
695 after_last_frame_setup_insn = next_pc;
696 }
697 else
698 {
699 /* Terminate the prologue scan. */
700 break;
701 }
702
703 pc = next_pc;
704 }
705
706 /* Is the frame size (offset, really) a known constant? */
707 if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
708 result->frame_size = reg[RL78_SP_REGNUM].k;
709
710 /* Record where all the registers were saved. */
711 pv_area_scan (stack, check_for_saved, (void *) result);
712
713 result->prologue_end = after_last_frame_setup_insn;
714
715 do_cleanups (back_to);
716}
717
718/* Implement the "addr_bits_remove" gdbarch method. */
719
720static CORE_ADDR
721rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
722{
723 return addr & 0xffffff;
724}
725
726/* Implement the "address_to_pointer" gdbarch method. */
727
728static void
729rl78_address_to_pointer (struct gdbarch *gdbarch,
730 struct type *type, gdb_byte *buf, CORE_ADDR addr)
731{
732 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
733
734 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
735 addr & 0xffffff);
736}
737
738/* Implement the "pointer_to_address" gdbarch method. */
739
740static CORE_ADDR
741rl78_pointer_to_address (struct gdbarch *gdbarch,
742 struct type *type, const gdb_byte *buf)
743{
744 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
745 CORE_ADDR addr
746 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
747
748 /* Is it a code address? */
749 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
750 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
751 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))
752 || TYPE_LENGTH (type) == 4)
753 return rl78_make_instruction_address (addr);
754 else
755 return rl78_make_data_address (addr);
756}
757
758/* Implement the "skip_prologue" gdbarch method. */
759
760static CORE_ADDR
761rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
762{
e4569f1e 763 const char *name;
9058f767
KB		 764 CORE_ADDR func_addr, func_end;
765 struct rl78_prologue p;
766
767 /* Try to find the extent of the function that contains PC. */
768 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
769 return pc;
770
771 rl78_analyze_prologue (pc, func_end, &p);
772 return p.prologue_end;
773}
774
775/* Implement the "unwind_pc" gdbarch method. */
776
777static CORE_ADDR
778rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
779{
780 return rl78_addr_bits_remove
781 (arch, frame_unwind_register_unsigned (next_frame,
782 RL78_PC_REGNUM));
783}
784
785/* Implement the "unwind_sp" gdbarch method. */
786
787static CORE_ADDR
788rl78_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
789{
790 return frame_unwind_register_unsigned (next_frame, RL78_SP_REGNUM);
791}
792
793/* Given a frame described by THIS_FRAME, decode the prologue of its
794 associated function if there is not cache entry as specified by
795 THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and
796 return that struct as the value of this function. */
797
798static struct rl78_prologue *
799rl78_analyze_frame_prologue (struct frame_info *this_frame,
800 void **this_prologue_cache)
801{
802 if (!*this_prologue_cache)
803 {
804 CORE_ADDR func_start, stop_addr;
805
806 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);
807
808 func_start = get_frame_func (this_frame);
809 stop_addr = get_frame_pc (this_frame);
810
811 /* If we couldn't find any function containing the PC, then
812 just initialize the prologue cache, but don't do anything. */
813 if (!func_start)
814 stop_addr = func_start;
815
816 rl78_analyze_prologue (func_start, stop_addr, *this_prologue_cache);
817 }
818
819 return *this_prologue_cache;
820}
821
822/* Given a frame and a prologue cache, return this frame's base. */
823
824static CORE_ADDR
825rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
826{
827 struct rl78_prologue *p
828 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
829 CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);
830
831 return rl78_make_data_address (sp - p->frame_size);
832}
833
834/* Implement the "frame_this_id" method for unwinding frames. */
835
836static void
837rl78_this_id (struct frame_info *this_frame,
838 void **this_prologue_cache, struct frame_id *this_id)
839{
840 *this_id = frame_id_build (rl78_frame_base (this_frame,
841 this_prologue_cache),
842 get_frame_func (this_frame));
843}
844
845/* Implement the "frame_prev_register" method for unwinding frames. */
846
847static struct value *
848rl78_prev_register (struct frame_info *this_frame,
849 void **this_prologue_cache, int regnum)
850{
851 struct rl78_prologue *p
852 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
853 CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);
854
855 if (regnum == RL78_SP_REGNUM)
856 return frame_unwind_got_constant (this_frame, regnum, frame_base);
857
858 else if (regnum == RL78_SPL_REGNUM)
859 return frame_unwind_got_constant (this_frame, regnum,
860 (frame_base & 0xff));
861
862 else if (regnum == RL78_SPH_REGNUM)
863 return frame_unwind_got_constant (this_frame, regnum,
864 ((frame_base >> 8) & 0xff));
865
866 /* If prologue analysis says we saved this register somewhere,
867 return a description of the stack slot holding it. */
868 else if (p->reg_offset[regnum] != 1)
869 {
870 struct value *rv =
871 frame_unwind_got_memory (this_frame, regnum,
872 frame_base + p->reg_offset[regnum]);
873
874 if (regnum == RL78_PC_REGNUM)
875 {
876 ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));
877
878 return frame_unwind_got_constant (this_frame, regnum, pc);
879 }
880 return rv;
881 }
882
883 /* Otherwise, presume we haven't changed the value of this
884 register, and get it from the next frame. */
885 else
886 return frame_unwind_got_register (this_frame, regnum, regnum);
887}
888
889static const struct frame_unwind rl78_unwind =
890{
891 NORMAL_FRAME,
892 default_frame_unwind_stop_reason,
893 rl78_this_id,
894 rl78_prev_register,
895 NULL,
896 default_frame_sniffer
897};
898
899/* Implement the "dwarf_reg_to_regnum" gdbarch method. */
900
901static int
902rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
903{
904 if (0 <= reg && reg <= 31)
905 {
906 if ((reg & 1) == 0)
907 /* Map even registers to their 16-bit counterparts. This
908 is usually what is required from the DWARF info. */
909 return (reg >> 1) + RL78_BANK0_RP0_REGNUM;
910 else
911 return reg;
912 }
913 else if (reg == 32)
914 return RL78_SP_REGNUM;
915 else if (reg == 33)
b3ce41ea
KB		 916 return -1; /* ap */
917 else if (reg == 34)
918 return RL78_PSW_REGNUM;
919 else if (reg == 35)
920 return RL78_ES_REGNUM;
921 else if (reg == 36)
922 return RL78_CS_REGNUM;
923 else if (reg == 37)
9058f767
KB		 924 return RL78_PC_REGNUM;
925 else
926 internal_error (__FILE__, __LINE__,
927 _("Undefined dwarf2 register mapping of reg %d"),
928 reg);
929}
930
c47a44f4
KB		 931/* Implement the `register_sim_regno' gdbarch method. */
932
933static int
934rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum)
935{
936 gdb_assert (regnum < RL78_NUM_REGS);
937
938 /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We
939 just want to override the default here which disallows register
940 numbers which have no names. */
941 return regnum;
942}
943
9058f767
KB		 944/* Implement the "return_value" gdbarch method. */
945
946static enum return_value_convention
947rl78_return_value (struct gdbarch *gdbarch,
6a3a010b 948 struct value *function,
9058f767
KB		 949 struct type *valtype,
950 struct regcache *regcache,
951 gdb_byte *readbuf, const gdb_byte *writebuf)
952{
953 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
954 ULONGEST valtype_len = TYPE_LENGTH (valtype);
955
956 if (valtype_len > 8)
957 return RETURN_VALUE_STRUCT_CONVENTION;
958
959 if (readbuf)
960 {
961 ULONGEST u;
c47a44f4 962 int argreg = RL78_RAW_BANK1_R0_REGNUM;
9058f767
KB		 963 int offset = 0;
964
965 while (valtype_len > 0)
966 {
967 regcache_cooked_read_unsigned (regcache, argreg, &u);
968 store_unsigned_integer (readbuf + offset, 1, byte_order, u);
969 valtype_len -= 1;
970 offset += 1;
971 argreg++;
972 }
973 }
974
975 if (writebuf)
976 {
977 ULONGEST u;
c47a44f4 978 int argreg = RL78_RAW_BANK1_R0_REGNUM;
9058f767
KB		 979 int offset = 0;
980
981 while (valtype_len > 0)
982 {
983 u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
984 regcache_cooked_write_unsigned (regcache, argreg, u);
985 valtype_len -= 1;
986 offset += 1;
987 argreg++;
988 }
989 }
990
991 return RETURN_VALUE_REGISTER_CONVENTION;
992}
993
994
995/* Implement the "frame_align" gdbarch method. */
996
997static CORE_ADDR
998rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
999{
1000 return rl78_make_data_address (align_down (sp, 2));
1001}
1002
1003
1004/* Implement the "dummy_id" gdbarch method. */
1005
1006static struct frame_id
1007rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1008{
1009 return
1010 frame_id_build (rl78_make_data_address
1011 (get_frame_register_unsigned
1012 (this_frame, RL78_SP_REGNUM)),
1013 get_frame_pc (this_frame));
1014}
1015
1016
1017/* Implement the "push_dummy_call" gdbarch method. */
1018
1019static CORE_ADDR
1020rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1021 struct regcache *regcache, CORE_ADDR bp_addr,
1022 int nargs, struct value **args, CORE_ADDR sp,
1023 int struct_return, CORE_ADDR struct_addr)
1024{
1025 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1026 gdb_byte buf[4];
1027 int i;
1028
1029 /* Push arguments in reverse order. */
1030 for (i = nargs - 1; i >= 0; i--)
1031 {
1032 struct type *value_type = value_enclosing_type (args[i]);
1033 int len = TYPE_LENGTH (value_type);
1034 int container_len = (len + 1) & ~1;
9058f767
KB		 1035
1036 sp -= container_len;
1037 write_memory (rl78_make_data_address (sp),
1038 value_contents_all (args[i]), len);
1039 }
1040
1041 /* Store struct value address. */
1042 if (struct_return)
1043 {
1044 store_unsigned_integer (buf, 2, byte_order, struct_addr);
1045 sp -= 2;
1046 write_memory (rl78_make_data_address (sp), buf, 2);
1047 }
1048
1049 /* Store return address. */
1050 sp -= 4;
1051 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1052 write_memory (rl78_make_data_address (sp), buf, 4);
1053
1054 /* Finally, update the stack pointer... */
1055 regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);
1056
1057 /* DWARF2/GCC uses the stack address *before* the function call as a
1058 frame's CFA. */
1059 return rl78_make_data_address (sp + 4);
1060}
1061
1062/* Allocate and initialize a gdbarch object. */
1063
1064static struct gdbarch *
1065rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1066{
1067 struct gdbarch *gdbarch;
1068 struct gdbarch_tdep *tdep;
1069 int elf_flags;
1070
1071 /* Extract the elf_flags if available. */
1072 if (info.abfd != NULL
1073 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1074 elf_flags = elf_elfheader (info.abfd)->e_flags;
1075 else
1076 elf_flags = 0;
1077
1078
1079 /* Try to find the architecture in the list of already defined
1080 architectures. */
1081 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1082 arches != NULL;
1083 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1084 {
1085 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
1086 continue;
1087
1088 return arches->gdbarch;
1089 }
1090
1091 /* None found, create a new architecture from the information
1092 provided. */
1093 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
1094 gdbarch = gdbarch_alloc (&info, tdep);
1095 tdep->elf_flags = elf_flags;
1096
1097 /* Initialize types. */
1098 tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
1099 tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
1100 tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
1101 tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
1102 tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
1103 tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
1104 tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
1105
1106 tdep->rl78_data_pointer
1107 = arch_type (gdbarch, TYPE_CODE_PTR, 16 / TARGET_CHAR_BIT,
1108 xstrdup ("rl78_data_addr_t"));
1109 TYPE_TARGET_TYPE (tdep->rl78_data_pointer) = tdep->rl78_void;
1110 TYPE_UNSIGNED (tdep->rl78_data_pointer) = 1;
1111
1112 tdep->rl78_code_pointer
1113 = arch_type (gdbarch, TYPE_CODE_PTR, 32 / TARGET_CHAR_BIT,
1114 xstrdup ("rl78_code_addr_t"));
1115 TYPE_TARGET_TYPE (tdep->rl78_code_pointer) = tdep->rl78_void;
1116 TYPE_UNSIGNED (tdep->rl78_code_pointer) = 1;
1117
1118 /* Registers. */
1119 set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
1120 set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
1121 set_gdbarch_register_name (gdbarch, rl78_register_name);
1122 set_gdbarch_register_type (gdbarch, rl78_register_type);
1123 set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
1124 set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
1125 set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
1126 set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
1127 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
c47a44f4
KB		 1128 set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p);
1129 set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno);
9058f767
KB		 1130
1131 /* Data types. */
1132 set_gdbarch_char_signed (gdbarch, 0);
1133 set_gdbarch_short_bit (gdbarch, 16);
1134 set_gdbarch_int_bit (gdbarch, 16);
1135 set_gdbarch_long_bit (gdbarch, 32);
1136 set_gdbarch_long_long_bit (gdbarch, 64);
1137 set_gdbarch_ptr_bit (gdbarch, 16);
1138 set_gdbarch_addr_bit (gdbarch, 32);
b3ce41ea 1139 set_gdbarch_dwarf2_addr_size (gdbarch, 4);
9058f767
KB		 1140 set_gdbarch_float_bit (gdbarch, 32);
1141 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1142 set_gdbarch_double_bit (gdbarch, 32);
1143 set_gdbarch_long_double_bit (gdbarch, 64);
1144 set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
1145 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1146 set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
1147 set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
1148 set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
1149
1150 /* Breakpoints. */
1151 set_gdbarch_breakpoint_from_pc (gdbarch, rl78_breakpoint_from_pc);
1152 set_gdbarch_decr_pc_after_break (gdbarch, 1);
1153
1154 /* Disassembly. */
1155 set_gdbarch_print_insn (gdbarch, print_insn_rl78);
1156
1157 /* Frames, prologues, etc. */
1158 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1159 set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
1160 set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
1161 set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
1162 set_gdbarch_frame_align (gdbarch, rl78_frame_align);
b3ce41ea
KB		 1163
1164 dwarf2_append_unwinders (gdbarch);
9058f767
KB		 1165 frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
1166
1167 /* Dummy frames, return values. */
1168 set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
1169 set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
1170 set_gdbarch_return_value (gdbarch, rl78_return_value);
1171
1172 /* Virtual tables. */
1173 set_gdbarch_vbit_in_delta (gdbarch, 1);
1174
1175 return gdbarch;
1176}
1177
693be288
JK		 1178/* -Wmissing-prototypes */
1179extern initialize_file_ftype _initialize_rl78_tdep;
1180
9058f767
KB		 1181/* Register the above initialization routine. */
1182
1183void
1184_initialize_rl78_tdep (void)
1185{
1186 register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init);
1187}
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