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c906108c SS |
1 | /* Target-dependent code for the SPARC for GDB, the GNU debugger. |
2 | Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997 | |
3 | Free Software Foundation, Inc. | |
4 | ||
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | /* ??? Support for calling functions from gdb in sparc64 is unfinished. */ | |
23 | ||
24 | #include "defs.h" | |
25 | #include "frame.h" | |
26 | #include "inferior.h" | |
27 | #include "obstack.h" | |
28 | #include "target.h" | |
29 | #include "value.h" | |
30 | #include "bfd.h" | |
31 | #include "gdb_string.h" | |
32 | ||
33 | #ifdef USE_PROC_FS | |
34 | #include <sys/procfs.h> | |
35 | #endif | |
36 | ||
37 | #include "gdbcore.h" | |
38 | ||
39 | #if defined(TARGET_SPARCLET) || defined(TARGET_SPARCLITE) | |
40 | #define SPARC_HAS_FPU 0 | |
41 | #else | |
42 | #define SPARC_HAS_FPU 1 | |
43 | #endif | |
44 | ||
45 | #ifdef GDB_TARGET_IS_SPARC64 | |
46 | #define FP_REGISTER_BYTES (64 * 4) | |
60054393 MS |
47 | #else |
48 | #if (SPARC_HAS_FPU) | |
c906108c | 49 | #define FP_REGISTER_BYTES (32 * 4) |
60054393 MS |
50 | #else |
51 | #define FP_REGISTER_BYTES 0 | |
52 | #endif | |
c906108c SS |
53 | #endif |
54 | ||
55 | /* If not defined, assume 32 bit sparc. */ | |
56 | #ifndef FP_MAX_REGNUM | |
57 | #define FP_MAX_REGNUM (FP0_REGNUM + 32) | |
58 | #endif | |
59 | ||
60 | #define SPARC_INTREG_SIZE (REGISTER_RAW_SIZE (G0_REGNUM)) | |
61 | ||
62 | /* From infrun.c */ | |
63 | extern int stop_after_trap; | |
64 | ||
65 | /* We don't store all registers immediately when requested, since they | |
66 | get sent over in large chunks anyway. Instead, we accumulate most | |
67 | of the changes and send them over once. "deferred_stores" keeps | |
68 | track of which sets of registers we have locally-changed copies of, | |
69 | so we only need send the groups that have changed. */ | |
70 | ||
71 | int deferred_stores = 0; /* Cumulates stores we want to do eventually. */ | |
72 | ||
73 | ||
74 | /* Some machines, such as Fujitsu SPARClite 86x, have a bi-endian mode | |
75 | where instructions are big-endian and data are little-endian. | |
76 | This flag is set when we detect that the target is of this type. */ | |
77 | ||
78 | int bi_endian = 0; | |
79 | ||
80 | ||
81 | /* Fetch a single instruction. Even on bi-endian machines | |
82 | such as sparc86x, instructions are always big-endian. */ | |
83 | ||
84 | static unsigned long | |
85 | fetch_instruction (pc) | |
86 | CORE_ADDR pc; | |
87 | { | |
88 | unsigned long retval; | |
89 | int i; | |
90 | unsigned char buf[4]; | |
91 | ||
92 | read_memory (pc, buf, sizeof (buf)); | |
93 | ||
94 | /* Start at the most significant end of the integer, and work towards | |
95 | the least significant. */ | |
96 | retval = 0; | |
97 | for (i = 0; i < sizeof (buf); ++i) | |
98 | retval = (retval << 8) | buf[i]; | |
99 | return retval; | |
100 | } | |
101 | ||
102 | ||
103 | /* Branches with prediction are treated like their non-predicting cousins. */ | |
104 | /* FIXME: What about floating point branches? */ | |
105 | ||
106 | /* Macros to extract fields from sparc instructions. */ | |
107 | #define X_OP(i) (((i) >> 30) & 0x3) | |
108 | #define X_RD(i) (((i) >> 25) & 0x1f) | |
109 | #define X_A(i) (((i) >> 29) & 1) | |
110 | #define X_COND(i) (((i) >> 25) & 0xf) | |
111 | #define X_OP2(i) (((i) >> 22) & 0x7) | |
112 | #define X_IMM22(i) ((i) & 0x3fffff) | |
113 | #define X_OP3(i) (((i) >> 19) & 0x3f) | |
114 | #define X_RS1(i) (((i) >> 14) & 0x1f) | |
115 | #define X_I(i) (((i) >> 13) & 1) | |
116 | #define X_IMM13(i) ((i) & 0x1fff) | |
117 | /* Sign extension macros. */ | |
118 | #define X_SIMM13(i) ((X_IMM13 (i) ^ 0x1000) - 0x1000) | |
119 | #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) | |
120 | #define X_CC(i) (((i) >> 20) & 3) | |
121 | #define X_P(i) (((i) >> 19) & 1) | |
122 | #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) | |
123 | #define X_RCOND(i) (((i) >> 25) & 7) | |
124 | #define X_DISP16(i) ((((((i) >> 6) && 0xc000) | ((i) & 0x3fff)) ^ 0x8000) - 0x8000) | |
125 | #define X_FCN(i) (((i) >> 25) & 31) | |
126 | ||
127 | typedef enum | |
128 | { | |
129 | Error, not_branch, bicc, bicca, ba, baa, ticc, ta, | |
130 | #ifdef GDB_TARGET_IS_SPARC64 | |
131 | done_retry | |
132 | #endif | |
c5aa993b JM |
133 | } |
134 | branch_type; | |
c906108c SS |
135 | |
136 | /* Simulate single-step ptrace call for sun4. Code written by Gary | |
137 | Beihl (beihl@mcc.com). */ | |
138 | ||
139 | /* npc4 and next_pc describe the situation at the time that the | |
140 | step-breakpoint was set, not necessary the current value of NPC_REGNUM. */ | |
141 | static CORE_ADDR next_pc, npc4, target; | |
142 | static int brknpc4, brktrg; | |
143 | typedef char binsn_quantum[BREAKPOINT_MAX]; | |
144 | static binsn_quantum break_mem[3]; | |
145 | ||
146 | static branch_type isbranch PARAMS ((long, CORE_ADDR, CORE_ADDR *)); | |
147 | ||
148 | /* single_step() is called just before we want to resume the inferior, | |
149 | if we want to single-step it but there is no hardware or kernel single-step | |
150 | support (as on all SPARCs). We find all the possible targets of the | |
151 | coming instruction and breakpoint them. | |
152 | ||
153 | single_step is also called just after the inferior stops. If we had | |
154 | set up a simulated single-step, we undo our damage. */ | |
155 | ||
156 | void | |
157 | sparc_software_single_step (ignore, insert_breakpoints_p) | |
c5aa993b | 158 | enum target_signal ignore; /* pid, but we don't need it */ |
c906108c SS |
159 | int insert_breakpoints_p; |
160 | { | |
161 | branch_type br; | |
162 | CORE_ADDR pc; | |
163 | long pc_instruction; | |
164 | ||
165 | if (insert_breakpoints_p) | |
166 | { | |
167 | /* Always set breakpoint for NPC. */ | |
168 | next_pc = read_register (NPC_REGNUM); | |
c5aa993b | 169 | npc4 = next_pc + 4; /* branch not taken */ |
c906108c SS |
170 | |
171 | target_insert_breakpoint (next_pc, break_mem[0]); | |
172 | /* printf_unfiltered ("set break at %x\n",next_pc); */ | |
173 | ||
174 | pc = read_register (PC_REGNUM); | |
175 | pc_instruction = fetch_instruction (pc); | |
176 | br = isbranch (pc_instruction, pc, &target); | |
177 | brknpc4 = brktrg = 0; | |
178 | ||
179 | if (br == bicca) | |
180 | { | |
181 | /* Conditional annulled branch will either end up at | |
182 | npc (if taken) or at npc+4 (if not taken). | |
183 | Trap npc+4. */ | |
184 | brknpc4 = 1; | |
185 | target_insert_breakpoint (npc4, break_mem[1]); | |
186 | } | |
187 | else if (br == baa && target != next_pc) | |
188 | { | |
189 | /* Unconditional annulled branch will always end up at | |
190 | the target. */ | |
191 | brktrg = 1; | |
192 | target_insert_breakpoint (target, break_mem[2]); | |
193 | } | |
194 | #ifdef GDB_TARGET_IS_SPARC64 | |
195 | else if (br == done_retry) | |
196 | { | |
197 | brktrg = 1; | |
198 | target_insert_breakpoint (target, break_mem[2]); | |
199 | } | |
200 | #endif | |
201 | } | |
202 | else | |
203 | { | |
204 | /* Remove breakpoints */ | |
205 | target_remove_breakpoint (next_pc, break_mem[0]); | |
206 | ||
207 | if (brknpc4) | |
208 | target_remove_breakpoint (npc4, break_mem[1]); | |
209 | ||
210 | if (brktrg) | |
211 | target_remove_breakpoint (target, break_mem[2]); | |
212 | } | |
213 | } | |
214 | \f | |
215 | /* Call this for each newly created frame. For SPARC, we need to calculate | |
216 | the bottom of the frame, and do some extra work if the prologue | |
217 | has been generated via the -mflat option to GCC. In particular, | |
218 | we need to know where the previous fp and the pc have been stashed, | |
219 | since their exact position within the frame may vary. */ | |
220 | ||
221 | void | |
222 | sparc_init_extra_frame_info (fromleaf, fi) | |
223 | int fromleaf; | |
224 | struct frame_info *fi; | |
225 | { | |
226 | char *name; | |
227 | CORE_ADDR prologue_start, prologue_end; | |
228 | int insn; | |
229 | ||
230 | fi->bottom = | |
231 | (fi->next ? | |
232 | (fi->frame == fi->next->frame ? fi->next->bottom : fi->next->frame) : | |
233 | read_sp ()); | |
234 | ||
235 | /* If fi->next is NULL, then we already set ->frame by passing read_fp() | |
236 | to create_new_frame. */ | |
237 | if (fi->next) | |
238 | { | |
239 | char buf[MAX_REGISTER_RAW_SIZE]; | |
240 | ||
241 | /* Compute ->frame as if not flat. If it is flat, we'll change | |
c5aa993b | 242 | it later. */ |
c906108c SS |
243 | if (fi->next->next != NULL |
244 | && (fi->next->next->signal_handler_caller | |
245 | || frame_in_dummy (fi->next->next)) | |
246 | && frameless_look_for_prologue (fi->next)) | |
247 | { | |
248 | /* A frameless function interrupted by a signal did not change | |
249 | the frame pointer, fix up frame pointer accordingly. */ | |
250 | fi->frame = FRAME_FP (fi->next); | |
251 | fi->bottom = fi->next->bottom; | |
252 | } | |
253 | else | |
254 | { | |
255 | /* Should we adjust for stack bias here? */ | |
256 | get_saved_register (buf, 0, 0, fi, FP_REGNUM, 0); | |
257 | fi->frame = extract_address (buf, REGISTER_RAW_SIZE (FP_REGNUM)); | |
258 | #ifdef GDB_TARGET_IS_SPARC64 | |
259 | if (fi->frame & 1) | |
260 | fi->frame += 2047; | |
261 | #endif | |
c5aa993b | 262 | |
c906108c SS |
263 | } |
264 | } | |
265 | ||
266 | /* Decide whether this is a function with a ``flat register window'' | |
267 | frame. For such functions, the frame pointer is actually in %i7. */ | |
268 | fi->flat = 0; | |
269 | fi->in_prologue = 0; | |
270 | if (find_pc_partial_function (fi->pc, &name, &prologue_start, &prologue_end)) | |
271 | { | |
272 | /* See if the function starts with an add (which will be of a | |
c5aa993b JM |
273 | negative number if a flat frame) to the sp. FIXME: Does not |
274 | handle large frames which will need more than one instruction | |
275 | to adjust the sp. */ | |
c906108c SS |
276 | insn = fetch_instruction (prologue_start, 4); |
277 | if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0 | |
278 | && X_I (insn) && X_SIMM13 (insn) < 0) | |
279 | { | |
280 | int offset = X_SIMM13 (insn); | |
281 | ||
282 | /* Then look for a save of %i7 into the frame. */ | |
283 | insn = fetch_instruction (prologue_start + 4); | |
284 | if (X_OP (insn) == 3 | |
285 | && X_RD (insn) == 31 | |
286 | && X_OP3 (insn) == 4 | |
287 | && X_RS1 (insn) == 14) | |
288 | { | |
289 | char buf[MAX_REGISTER_RAW_SIZE]; | |
290 | ||
291 | /* We definitely have a flat frame now. */ | |
292 | fi->flat = 1; | |
293 | ||
294 | fi->sp_offset = offset; | |
295 | ||
296 | /* Overwrite the frame's address with the value in %i7. */ | |
297 | get_saved_register (buf, 0, 0, fi, I7_REGNUM, 0); | |
298 | fi->frame = extract_address (buf, REGISTER_RAW_SIZE (I7_REGNUM)); | |
299 | #ifdef GDB_TARGET_IS_SPARC64 | |
300 | if (fi->frame & 1) | |
301 | fi->frame += 2047; | |
302 | #endif | |
303 | /* Record where the fp got saved. */ | |
304 | fi->fp_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn); | |
305 | ||
306 | /* Also try to collect where the pc got saved to. */ | |
307 | fi->pc_addr = 0; | |
308 | insn = fetch_instruction (prologue_start + 12); | |
309 | if (X_OP (insn) == 3 | |
310 | && X_RD (insn) == 15 | |
311 | && X_OP3 (insn) == 4 | |
312 | && X_RS1 (insn) == 14) | |
313 | fi->pc_addr = fi->frame + fi->sp_offset + X_SIMM13 (insn); | |
314 | } | |
315 | } | |
c5aa993b JM |
316 | else |
317 | { | |
318 | /* Check if the PC is in the function prologue before a SAVE | |
319 | instruction has been executed yet. If so, set the frame | |
320 | to the current value of the stack pointer and set | |
321 | the in_prologue flag. */ | |
322 | CORE_ADDR addr; | |
323 | struct symtab_and_line sal; | |
324 | ||
325 | sal = find_pc_line (prologue_start, 0); | |
326 | if (sal.line == 0) /* no line info, use PC */ | |
327 | prologue_end = fi->pc; | |
328 | else if (sal.end < prologue_end) | |
329 | prologue_end = sal.end; | |
330 | if (fi->pc < prologue_end) | |
331 | { | |
332 | for (addr = prologue_start; addr < fi->pc; addr += 4) | |
333 | { | |
334 | insn = read_memory_integer (addr, 4); | |
335 | if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c) | |
336 | break; /* SAVE seen, stop searching */ | |
337 | } | |
338 | if (addr >= fi->pc) | |
339 | { | |
340 | fi->in_prologue = 1; | |
341 | fi->frame = read_register (SP_REGNUM); | |
342 | } | |
343 | } | |
344 | } | |
c906108c SS |
345 | } |
346 | if (fi->next && fi->frame == 0) | |
347 | { | |
348 | /* Kludge to cause init_prev_frame_info to destroy the new frame. */ | |
349 | fi->frame = fi->next->frame; | |
350 | fi->pc = fi->next->pc; | |
351 | } | |
352 | } | |
353 | ||
354 | CORE_ADDR | |
355 | sparc_frame_chain (frame) | |
356 | struct frame_info *frame; | |
357 | { | |
358 | /* Value that will cause FRAME_CHAIN_VALID to not worry about the chain | |
359 | value. If it realy is zero, we detect it later in | |
360 | sparc_init_prev_frame. */ | |
c5aa993b | 361 | return (CORE_ADDR) 1; |
c906108c SS |
362 | } |
363 | ||
364 | CORE_ADDR | |
365 | sparc_extract_struct_value_address (regbuf) | |
366 | char regbuf[REGISTER_BYTES]; | |
367 | { | |
368 | return extract_address (regbuf + REGISTER_BYTE (O0_REGNUM), | |
369 | REGISTER_RAW_SIZE (O0_REGNUM)); | |
370 | } | |
371 | ||
372 | /* Find the pc saved in frame FRAME. */ | |
373 | ||
374 | CORE_ADDR | |
375 | sparc_frame_saved_pc (frame) | |
376 | struct frame_info *frame; | |
377 | { | |
378 | char buf[MAX_REGISTER_RAW_SIZE]; | |
379 | CORE_ADDR addr; | |
380 | ||
381 | if (frame->signal_handler_caller) | |
382 | { | |
383 | /* This is the signal trampoline frame. | |
c5aa993b | 384 | Get the saved PC from the sigcontext structure. */ |
c906108c SS |
385 | |
386 | #ifndef SIGCONTEXT_PC_OFFSET | |
387 | #define SIGCONTEXT_PC_OFFSET 12 | |
388 | #endif | |
389 | ||
390 | CORE_ADDR sigcontext_addr; | |
391 | char scbuf[TARGET_PTR_BIT / HOST_CHAR_BIT]; | |
392 | int saved_pc_offset = SIGCONTEXT_PC_OFFSET; | |
393 | char *name = NULL; | |
394 | ||
395 | /* Solaris2 ucbsigvechandler passes a pointer to a sigcontext | |
c5aa993b | 396 | as the third parameter. The offset to the saved pc is 12. */ |
c906108c | 397 | find_pc_partial_function (frame->pc, &name, |
c5aa993b | 398 | (CORE_ADDR *) NULL, (CORE_ADDR *) NULL); |
c906108c SS |
399 | if (name && STREQ (name, "ucbsigvechandler")) |
400 | saved_pc_offset = 12; | |
401 | ||
402 | /* The sigcontext address is contained in register O2. */ | |
c5aa993b JM |
403 | get_saved_register (buf, (int *) NULL, (CORE_ADDR *) NULL, |
404 | frame, O0_REGNUM + 2, (enum lval_type *) NULL); | |
c906108c SS |
405 | sigcontext_addr = extract_address (buf, REGISTER_RAW_SIZE (O0_REGNUM + 2)); |
406 | ||
407 | /* Don't cause a memory_error when accessing sigcontext in case the | |
c5aa993b | 408 | stack layout has changed or the stack is corrupt. */ |
c906108c SS |
409 | target_read_memory (sigcontext_addr + saved_pc_offset, |
410 | scbuf, sizeof (scbuf)); | |
411 | return extract_address (scbuf, sizeof (scbuf)); | |
412 | } | |
413 | else if (frame->in_prologue || | |
414 | (frame->next != NULL | |
415 | && (frame->next->signal_handler_caller | |
c5aa993b | 416 | || frame_in_dummy (frame->next)) |
c906108c SS |
417 | && frameless_look_for_prologue (frame))) |
418 | { | |
419 | /* A frameless function interrupted by a signal did not save | |
c5aa993b JM |
420 | the PC, it is still in %o7. */ |
421 | get_saved_register (buf, (int *) NULL, (CORE_ADDR *) NULL, | |
422 | frame, O7_REGNUM, (enum lval_type *) NULL); | |
c906108c SS |
423 | return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); |
424 | } | |
425 | if (frame->flat) | |
426 | addr = frame->pc_addr; | |
427 | else | |
428 | addr = frame->bottom + FRAME_SAVED_I0 + | |
429 | SPARC_INTREG_SIZE * (I7_REGNUM - I0_REGNUM); | |
430 | ||
431 | if (addr == 0) | |
432 | /* A flat frame leaf function might not save the PC anywhere, | |
433 | just leave it in %o7. */ | |
434 | return PC_ADJUST (read_register (O7_REGNUM)); | |
435 | ||
436 | read_memory (addr, buf, SPARC_INTREG_SIZE); | |
437 | return PC_ADJUST (extract_address (buf, SPARC_INTREG_SIZE)); | |
438 | } | |
439 | ||
440 | /* Since an individual frame in the frame cache is defined by two | |
441 | arguments (a frame pointer and a stack pointer), we need two | |
442 | arguments to get info for an arbitrary stack frame. This routine | |
443 | takes two arguments and makes the cached frames look as if these | |
444 | two arguments defined a frame on the cache. This allows the rest | |
445 | of info frame to extract the important arguments without | |
446 | difficulty. */ | |
447 | ||
448 | struct frame_info * | |
449 | setup_arbitrary_frame (argc, argv) | |
450 | int argc; | |
451 | CORE_ADDR *argv; | |
452 | { | |
453 | struct frame_info *frame; | |
454 | ||
455 | if (argc != 2) | |
456 | error ("Sparc frame specifications require two arguments: fp and sp"); | |
457 | ||
458 | frame = create_new_frame (argv[0], 0); | |
459 | ||
460 | if (!frame) | |
96baa820 | 461 | internal_error ("create_new_frame returned invalid frame"); |
c5aa993b | 462 | |
c906108c SS |
463 | frame->bottom = argv[1]; |
464 | frame->pc = FRAME_SAVED_PC (frame); | |
465 | return frame; | |
466 | } | |
467 | ||
468 | /* Given a pc value, skip it forward past the function prologue by | |
469 | disassembling instructions that appear to be a prologue. | |
470 | ||
471 | If FRAMELESS_P is set, we are only testing to see if the function | |
472 | is frameless. This allows a quicker answer. | |
473 | ||
474 | This routine should be more specific in its actions; making sure | |
475 | that it uses the same register in the initial prologue section. */ | |
476 | ||
477 | static CORE_ADDR examine_prologue PARAMS ((CORE_ADDR, int, struct frame_info *, | |
478 | struct frame_saved_regs *)); | |
479 | ||
c5aa993b | 480 | static CORE_ADDR |
c906108c SS |
481 | examine_prologue (start_pc, frameless_p, fi, saved_regs) |
482 | CORE_ADDR start_pc; | |
483 | int frameless_p; | |
484 | struct frame_info *fi; | |
485 | struct frame_saved_regs *saved_regs; | |
486 | { | |
487 | int insn; | |
488 | int dest = -1; | |
489 | CORE_ADDR pc = start_pc; | |
490 | int is_flat = 0; | |
491 | ||
492 | insn = fetch_instruction (pc); | |
493 | ||
494 | /* Recognize the `sethi' insn and record its destination. */ | |
495 | if (X_OP (insn) == 0 && X_OP2 (insn) == 4) | |
496 | { | |
497 | dest = X_RD (insn); | |
498 | pc += 4; | |
499 | insn = fetch_instruction (pc); | |
500 | } | |
501 | ||
502 | /* Recognize an add immediate value to register to either %g1 or | |
503 | the destination register recorded above. Actually, this might | |
504 | well recognize several different arithmetic operations. | |
505 | It doesn't check that rs1 == rd because in theory "sub %g0, 5, %g1" | |
506 | followed by "save %sp, %g1, %sp" is a valid prologue (Not that | |
507 | I imagine any compiler really does that, however). */ | |
508 | if (X_OP (insn) == 2 | |
509 | && X_I (insn) | |
510 | && (X_RD (insn) == 1 || X_RD (insn) == dest)) | |
511 | { | |
512 | pc += 4; | |
513 | insn = fetch_instruction (pc); | |
514 | } | |
515 | ||
516 | /* Recognize any SAVE insn. */ | |
517 | if (X_OP (insn) == 2 && X_OP3 (insn) == 60) | |
518 | { | |
519 | pc += 4; | |
c5aa993b JM |
520 | if (frameless_p) /* If the save is all we care about, */ |
521 | return pc; /* return before doing more work */ | |
c906108c SS |
522 | insn = fetch_instruction (pc); |
523 | } | |
524 | /* Recognize add to %sp. */ | |
525 | else if (X_OP (insn) == 2 && X_RD (insn) == 14 && X_OP3 (insn) == 0) | |
526 | { | |
527 | pc += 4; | |
c5aa993b JM |
528 | if (frameless_p) /* If the add is all we care about, */ |
529 | return pc; /* return before doing more work */ | |
c906108c SS |
530 | is_flat = 1; |
531 | insn = fetch_instruction (pc); | |
532 | /* Recognize store of frame pointer (i7). */ | |
533 | if (X_OP (insn) == 3 | |
534 | && X_RD (insn) == 31 | |
535 | && X_OP3 (insn) == 4 | |
536 | && X_RS1 (insn) == 14) | |
537 | { | |
538 | pc += 4; | |
539 | insn = fetch_instruction (pc); | |
540 | ||
541 | /* Recognize sub %sp, <anything>, %i7. */ | |
c5aa993b | 542 | if (X_OP (insn) == 2 |
c906108c SS |
543 | && X_OP3 (insn) == 4 |
544 | && X_RS1 (insn) == 14 | |
545 | && X_RD (insn) == 31) | |
546 | { | |
547 | pc += 4; | |
548 | insn = fetch_instruction (pc); | |
549 | } | |
550 | else | |
551 | return pc; | |
552 | } | |
553 | else | |
554 | return pc; | |
555 | } | |
556 | else | |
557 | /* Without a save or add instruction, it's not a prologue. */ | |
558 | return start_pc; | |
559 | ||
560 | while (1) | |
561 | { | |
562 | /* Recognize stores into the frame from the input registers. | |
c5aa993b JM |
563 | This recognizes all non alternate stores of input register, |
564 | into a location offset from the frame pointer. */ | |
c906108c | 565 | if ((X_OP (insn) == 3 |
c5aa993b JM |
566 | && (X_OP3 (insn) & 0x3c) == 4 /* Store, non-alternate. */ |
567 | && (X_RD (insn) & 0x18) == 0x18 /* Input register. */ | |
568 | && X_I (insn) /* Immediate mode. */ | |
c906108c | 569 | && X_RS1 (insn) == 30 /* Off of frame pointer. */ |
c5aa993b | 570 | /* Into reserved stack space. */ |
c906108c SS |
571 | && X_SIMM13 (insn) >= 0x44 |
572 | && X_SIMM13 (insn) < 0x5b)) | |
573 | ; | |
574 | else if (is_flat | |
575 | && X_OP (insn) == 3 | |
576 | && X_OP3 (insn) == 4 | |
577 | && X_RS1 (insn) == 14 | |
c5aa993b | 578 | ) |
c906108c SS |
579 | { |
580 | if (saved_regs && X_I (insn)) | |
581 | saved_regs->regs[X_RD (insn)] = | |
582 | fi->frame + fi->sp_offset + X_SIMM13 (insn); | |
583 | } | |
584 | else | |
585 | break; | |
586 | pc += 4; | |
587 | insn = fetch_instruction (pc); | |
588 | } | |
589 | ||
590 | return pc; | |
591 | } | |
592 | ||
c5aa993b | 593 | CORE_ADDR |
b83266a0 | 594 | sparc_skip_prologue (start_pc, frameless_p) |
c906108c SS |
595 | CORE_ADDR start_pc; |
596 | int frameless_p; | |
597 | { | |
598 | return examine_prologue (start_pc, frameless_p, NULL, NULL); | |
599 | } | |
600 | ||
601 | /* Check instruction at ADDR to see if it is a branch. | |
602 | All non-annulled instructions will go to NPC or will trap. | |
603 | Set *TARGET if we find a candidate branch; set to zero if not. | |
604 | ||
605 | This isn't static as it's used by remote-sa.sparc.c. */ | |
606 | ||
607 | static branch_type | |
608 | isbranch (instruction, addr, target) | |
609 | long instruction; | |
610 | CORE_ADDR addr, *target; | |
611 | { | |
612 | branch_type val = not_branch; | |
613 | long int offset = 0; /* Must be signed for sign-extend. */ | |
614 | ||
615 | *target = 0; | |
616 | ||
617 | if (X_OP (instruction) == 0 | |
618 | && (X_OP2 (instruction) == 2 | |
619 | || X_OP2 (instruction) == 6 | |
620 | || X_OP2 (instruction) == 1 | |
621 | || X_OP2 (instruction) == 3 | |
622 | || X_OP2 (instruction) == 5 | |
623 | #ifndef GDB_TARGET_IS_SPARC64 | |
624 | || X_OP2 (instruction) == 7 | |
625 | #endif | |
c5aa993b | 626 | )) |
c906108c SS |
627 | { |
628 | if (X_COND (instruction) == 8) | |
629 | val = X_A (instruction) ? baa : ba; | |
630 | else | |
631 | val = X_A (instruction) ? bicca : bicc; | |
632 | switch (X_OP2 (instruction)) | |
633 | { | |
634 | case 2: | |
635 | case 6: | |
636 | #ifndef GDB_TARGET_IS_SPARC64 | |
637 | case 7: | |
638 | #endif | |
639 | offset = 4 * X_DISP22 (instruction); | |
640 | break; | |
641 | case 1: | |
642 | case 5: | |
643 | offset = 4 * X_DISP19 (instruction); | |
644 | break; | |
645 | case 3: | |
646 | offset = 4 * X_DISP16 (instruction); | |
647 | break; | |
648 | } | |
649 | *target = addr + offset; | |
650 | } | |
651 | #ifdef GDB_TARGET_IS_SPARC64 | |
652 | else if (X_OP (instruction) == 2 | |
653 | && X_OP3 (instruction) == 62) | |
654 | { | |
655 | if (X_FCN (instruction) == 0) | |
656 | { | |
657 | /* done */ | |
658 | *target = read_register (TNPC_REGNUM); | |
659 | val = done_retry; | |
660 | } | |
661 | else if (X_FCN (instruction) == 1) | |
662 | { | |
663 | /* retry */ | |
664 | *target = read_register (TPC_REGNUM); | |
665 | val = done_retry; | |
666 | } | |
667 | } | |
668 | #endif | |
669 | ||
670 | return val; | |
671 | } | |
672 | \f | |
673 | /* Find register number REGNUM relative to FRAME and put its | |
674 | (raw) contents in *RAW_BUFFER. Set *OPTIMIZED if the variable | |
675 | was optimized out (and thus can't be fetched). If the variable | |
676 | was fetched from memory, set *ADDRP to where it was fetched from, | |
677 | otherwise it was fetched from a register. | |
678 | ||
679 | The argument RAW_BUFFER must point to aligned memory. */ | |
680 | ||
681 | void | |
7a292a7a | 682 | sparc_get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval) |
c906108c SS |
683 | char *raw_buffer; |
684 | int *optimized; | |
685 | CORE_ADDR *addrp; | |
686 | struct frame_info *frame; | |
687 | int regnum; | |
688 | enum lval_type *lval; | |
689 | { | |
690 | struct frame_info *frame1; | |
691 | CORE_ADDR addr; | |
692 | ||
693 | if (!target_has_registers) | |
694 | error ("No registers."); | |
695 | ||
696 | if (optimized) | |
697 | *optimized = 0; | |
698 | ||
699 | addr = 0; | |
700 | ||
701 | /* FIXME This code extracted from infcmd.c; should put elsewhere! */ | |
702 | if (frame == NULL) | |
703 | { | |
704 | /* error ("No selected frame."); */ | |
705 | if (!target_has_registers) | |
c5aa993b JM |
706 | error ("The program has no registers now."); |
707 | if (selected_frame == NULL) | |
708 | error ("No selected frame."); | |
c906108c | 709 | /* Try to use selected frame */ |
c5aa993b | 710 | frame = get_prev_frame (selected_frame); |
c906108c | 711 | if (frame == 0) |
c5aa993b | 712 | error ("Cmd not meaningful in the outermost frame."); |
c906108c SS |
713 | } |
714 | ||
715 | ||
716 | frame1 = frame->next; | |
717 | ||
718 | /* Get saved PC from the frame info if not in innermost frame. */ | |
719 | if (regnum == PC_REGNUM && frame1 != NULL) | |
720 | { | |
721 | if (lval != NULL) | |
722 | *lval = not_lval; | |
723 | if (raw_buffer != NULL) | |
724 | { | |
725 | /* Put it back in target format. */ | |
726 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), frame->pc); | |
727 | } | |
728 | if (addrp != NULL) | |
729 | *addrp = 0; | |
730 | return; | |
731 | } | |
732 | ||
733 | while (frame1 != NULL) | |
734 | { | |
735 | if (frame1->pc >= (frame1->bottom ? frame1->bottom : | |
736 | read_sp ()) | |
737 | && frame1->pc <= FRAME_FP (frame1)) | |
738 | { | |
739 | /* Dummy frame. All but the window regs are in there somewhere. | |
740 | The window registers are saved on the stack, just like in a | |
741 | normal frame. */ | |
742 | if (regnum >= G1_REGNUM && regnum < G1_REGNUM + 7) | |
743 | addr = frame1->frame + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE | |
744 | - (FP_REGISTER_BYTES + 8 * SPARC_INTREG_SIZE); | |
745 | else if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) | |
746 | addr = (frame1->prev->bottom | |
747 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE | |
748 | + FRAME_SAVED_I0); | |
749 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) | |
750 | addr = (frame1->prev->bottom | |
751 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE | |
752 | + FRAME_SAVED_L0); | |
753 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) | |
754 | addr = frame1->frame + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE | |
755 | - (FP_REGISTER_BYTES + 16 * SPARC_INTREG_SIZE); | |
60054393 MS |
756 | else if (FP0_REGNUM >= 0 && |
757 | regnum >= FP0_REGNUM && regnum < FP0_REGNUM + 32) | |
c906108c SS |
758 | addr = frame1->frame + (regnum - FP0_REGNUM) * 4 |
759 | - (FP_REGISTER_BYTES); | |
760 | #ifdef GDB_TARGET_IS_SPARC64 | |
60054393 MS |
761 | else if (FP0_REGNUM >= 0 && |
762 | regnum >= FP0_REGNUM + 32 && regnum < FP_MAX_REGNUM) | |
c906108c SS |
763 | addr = frame1->frame + 32 * 4 + (regnum - FP0_REGNUM - 32) * 8 |
764 | - (FP_REGISTER_BYTES); | |
765 | #endif | |
c906108c SS |
766 | else if (regnum >= Y_REGNUM && regnum < NUM_REGS) |
767 | addr = frame1->frame + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE | |
768 | - (FP_REGISTER_BYTES + 24 * SPARC_INTREG_SIZE); | |
769 | } | |
770 | else if (frame1->flat) | |
771 | { | |
772 | ||
773 | if (regnum == RP_REGNUM) | |
774 | addr = frame1->pc_addr; | |
775 | else if (regnum == I7_REGNUM) | |
776 | addr = frame1->fp_addr; | |
777 | else | |
778 | { | |
779 | CORE_ADDR func_start; | |
780 | struct frame_saved_regs regs; | |
781 | memset (®s, 0, sizeof (regs)); | |
782 | ||
783 | find_pc_partial_function (frame1->pc, NULL, &func_start, NULL); | |
784 | examine_prologue (func_start, 0, frame1, ®s); | |
785 | addr = regs.regs[regnum]; | |
786 | } | |
787 | } | |
788 | else | |
789 | { | |
790 | /* Normal frame. Local and In registers are saved on stack. */ | |
791 | if (regnum >= I0_REGNUM && regnum < I0_REGNUM + 8) | |
792 | addr = (frame1->prev->bottom | |
793 | + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE | |
794 | + FRAME_SAVED_I0); | |
795 | else if (regnum >= L0_REGNUM && regnum < L0_REGNUM + 8) | |
796 | addr = (frame1->prev->bottom | |
797 | + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE | |
798 | + FRAME_SAVED_L0); | |
799 | else if (regnum >= O0_REGNUM && regnum < O0_REGNUM + 8) | |
800 | { | |
801 | /* Outs become ins. */ | |
802 | get_saved_register (raw_buffer, optimized, addrp, frame1, | |
803 | (regnum - O0_REGNUM + I0_REGNUM), lval); | |
804 | return; | |
805 | } | |
806 | } | |
807 | if (addr != 0) | |
808 | break; | |
809 | frame1 = frame1->next; | |
810 | } | |
811 | if (addr != 0) | |
812 | { | |
813 | if (lval != NULL) | |
814 | *lval = lval_memory; | |
815 | if (regnum == SP_REGNUM) | |
816 | { | |
817 | if (raw_buffer != NULL) | |
818 | { | |
819 | /* Put it back in target format. */ | |
820 | store_address (raw_buffer, REGISTER_RAW_SIZE (regnum), addr); | |
821 | } | |
822 | if (addrp != NULL) | |
823 | *addrp = 0; | |
824 | return; | |
825 | } | |
826 | if (raw_buffer != NULL) | |
827 | read_memory (addr, raw_buffer, REGISTER_RAW_SIZE (regnum)); | |
828 | } | |
829 | else | |
830 | { | |
831 | if (lval != NULL) | |
832 | *lval = lval_register; | |
833 | addr = REGISTER_BYTE (regnum); | |
834 | if (raw_buffer != NULL) | |
835 | read_register_gen (regnum, raw_buffer); | |
836 | } | |
837 | if (addrp != NULL) | |
838 | *addrp = addr; | |
839 | } | |
840 | ||
841 | /* Push an empty stack frame, and record in it the current PC, regs, etc. | |
842 | ||
843 | We save the non-windowed registers and the ins. The locals and outs | |
844 | are new; they don't need to be saved. The i's and l's of | |
845 | the last frame were already saved on the stack. */ | |
846 | ||
847 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
848 | ||
849 | #ifdef GDB_TARGET_IS_SPARC64 | |
850 | #define DUMMY_REG_SAVE_OFFSET (128 + 16) | |
851 | #else | |
852 | #define DUMMY_REG_SAVE_OFFSET 0x60 | |
853 | #endif | |
854 | ||
855 | /* See tm-sparc.h for how this is calculated. */ | |
c906108c | 856 | #define DUMMY_STACK_REG_BUF_SIZE \ |
60054393 | 857 | (((8+8+8) * SPARC_INTREG_SIZE) + FP_REGISTER_BYTES) |
c906108c SS |
858 | #define DUMMY_STACK_SIZE (DUMMY_STACK_REG_BUF_SIZE + DUMMY_REG_SAVE_OFFSET) |
859 | ||
860 | void | |
861 | sparc_push_dummy_frame () | |
862 | { | |
863 | CORE_ADDR sp, old_sp; | |
864 | char register_temp[DUMMY_STACK_SIZE]; | |
865 | ||
866 | old_sp = sp = read_sp (); | |
867 | ||
868 | #ifdef GDB_TARGET_IS_SPARC64 | |
869 | /* PC, NPC, CCR, FSR, FPRS, Y, ASI */ | |
870 | read_register_bytes (REGISTER_BYTE (PC_REGNUM), ®ister_temp[0], | |
871 | REGISTER_RAW_SIZE (PC_REGNUM) * 7); | |
872 | read_register_bytes (REGISTER_BYTE (PSTATE_REGNUM), ®ister_temp[8], | |
873 | REGISTER_RAW_SIZE (PSTATE_REGNUM)); | |
874 | /* FIXME: not sure what needs to be saved here. */ | |
875 | #else | |
876 | /* Y, PS, WIM, TBR, PC, NPC, FPS, CPS regs */ | |
877 | read_register_bytes (REGISTER_BYTE (Y_REGNUM), ®ister_temp[0], | |
878 | REGISTER_RAW_SIZE (Y_REGNUM) * 8); | |
879 | #endif | |
880 | ||
881 | read_register_bytes (REGISTER_BYTE (O0_REGNUM), | |
882 | ®ister_temp[8 * SPARC_INTREG_SIZE], | |
883 | SPARC_INTREG_SIZE * 8); | |
884 | ||
885 | read_register_bytes (REGISTER_BYTE (G0_REGNUM), | |
886 | ®ister_temp[16 * SPARC_INTREG_SIZE], | |
887 | SPARC_INTREG_SIZE * 8); | |
888 | ||
60054393 MS |
889 | if (FP0_REGNUM >= 0) |
890 | read_register_bytes (REGISTER_BYTE (FP0_REGNUM), | |
891 | ®ister_temp[24 * SPARC_INTREG_SIZE], | |
892 | FP_REGISTER_BYTES); | |
c906108c SS |
893 | |
894 | sp -= DUMMY_STACK_SIZE; | |
895 | ||
896 | write_sp (sp); | |
897 | ||
898 | write_memory (sp + DUMMY_REG_SAVE_OFFSET, ®ister_temp[0], | |
899 | DUMMY_STACK_REG_BUF_SIZE); | |
900 | ||
901 | if (strcmp (target_shortname, "sim") != 0) | |
902 | { | |
903 | write_fp (old_sp); | |
904 | ||
905 | /* Set return address register for the call dummy to the current PC. */ | |
c5aa993b | 906 | write_register (I7_REGNUM, read_pc () - 8); |
c906108c SS |
907 | } |
908 | else | |
909 | { | |
910 | /* The call dummy will write this value to FP before executing | |
911 | the 'save'. This ensures that register window flushes work | |
c5aa993b JM |
912 | correctly in the simulator. */ |
913 | write_register (G0_REGNUM + 1, read_register (FP_REGNUM)); | |
914 | ||
c906108c SS |
915 | /* The call dummy will write this value to FP after executing |
916 | the 'save'. */ | |
c5aa993b JM |
917 | write_register (G0_REGNUM + 2, old_sp); |
918 | ||
c906108c | 919 | /* The call dummy will write this value to the return address (%i7) after |
c5aa993b JM |
920 | executing the 'save'. */ |
921 | write_register (G0_REGNUM + 3, read_pc () - 8); | |
922 | ||
c906108c | 923 | /* Set the FP that the call dummy will be using after the 'save'. |
c5aa993b | 924 | This makes backtraces from an inferior function call work properly. */ |
c906108c SS |
925 | write_register (FP_REGNUM, old_sp); |
926 | } | |
927 | } | |
928 | ||
929 | /* sparc_frame_find_saved_regs (). This function is here only because | |
930 | pop_frame uses it. Note there is an interesting corner case which | |
931 | I think few ports of GDB get right--if you are popping a frame | |
932 | which does not save some register that *is* saved by a more inner | |
933 | frame (such a frame will never be a dummy frame because dummy | |
934 | frames save all registers). Rewriting pop_frame to use | |
935 | get_saved_register would solve this problem and also get rid of the | |
936 | ugly duplication between sparc_frame_find_saved_regs and | |
937 | get_saved_register. | |
938 | ||
939 | Stores, into a struct frame_saved_regs, | |
940 | the addresses of the saved registers of frame described by FRAME_INFO. | |
941 | This includes special registers such as pc and fp saved in special | |
942 | ways in the stack frame. sp is even more special: | |
943 | the address we return for it IS the sp for the next frame. | |
944 | ||
945 | Note that on register window machines, we are currently making the | |
946 | assumption that window registers are being saved somewhere in the | |
947 | frame in which they are being used. If they are stored in an | |
948 | inferior frame, find_saved_register will break. | |
949 | ||
950 | On the Sun 4, the only time all registers are saved is when | |
951 | a dummy frame is involved. Otherwise, the only saved registers | |
952 | are the LOCAL and IN registers which are saved as a result | |
953 | of the "save/restore" opcodes. This condition is determined | |
954 | by address rather than by value. | |
955 | ||
956 | The "pc" is not stored in a frame on the SPARC. (What is stored | |
957 | is a return address minus 8.) sparc_pop_frame knows how to | |
958 | deal with that. Other routines might or might not. | |
959 | ||
960 | See tm-sparc.h (PUSH_DUMMY_FRAME and friends) for CRITICAL information | |
961 | about how this works. */ | |
962 | ||
963 | static void sparc_frame_find_saved_regs PARAMS ((struct frame_info *, | |
964 | struct frame_saved_regs *)); | |
965 | ||
966 | static void | |
967 | sparc_frame_find_saved_regs (fi, saved_regs_addr) | |
968 | struct frame_info *fi; | |
969 | struct frame_saved_regs *saved_regs_addr; | |
970 | { | |
971 | register int regnum; | |
972 | CORE_ADDR frame_addr = FRAME_FP (fi); | |
973 | ||
974 | if (!fi) | |
96baa820 | 975 | internal_error ("Bad frame info struct in FRAME_FIND_SAVED_REGS"); |
c906108c SS |
976 | |
977 | memset (saved_regs_addr, 0, sizeof (*saved_regs_addr)); | |
978 | ||
979 | if (fi->pc >= (fi->bottom ? fi->bottom : | |
c5aa993b JM |
980 | read_sp ()) |
981 | && fi->pc <= FRAME_FP (fi)) | |
c906108c SS |
982 | { |
983 | /* Dummy frame. All but the window regs are in there somewhere. */ | |
c5aa993b | 984 | for (regnum = G1_REGNUM; regnum < G1_REGNUM + 7; regnum++) |
c906108c SS |
985 | saved_regs_addr->regs[regnum] = |
986 | frame_addr + (regnum - G0_REGNUM) * SPARC_INTREG_SIZE | |
c5aa993b JM |
987 | - DUMMY_STACK_REG_BUF_SIZE + 16 * SPARC_INTREG_SIZE; |
988 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) | |
c906108c SS |
989 | saved_regs_addr->regs[regnum] = |
990 | frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE | |
c5aa993b | 991 | - DUMMY_STACK_REG_BUF_SIZE + 8 * SPARC_INTREG_SIZE; |
60054393 MS |
992 | if (FP0_REGNUM >= 0) |
993 | { | |
994 | for (regnum = FP0_REGNUM; regnum < FP0_REGNUM + 32; regnum++) | |
995 | saved_regs_addr->regs[regnum] = | |
996 | frame_addr + (regnum - FP0_REGNUM) * 4 | |
997 | - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE; | |
c906108c | 998 | #ifdef GDB_TARGET_IS_SPARC64 |
60054393 MS |
999 | for (regnum = FP0_REGNUM + 32; regnum < FP_MAX_REGNUM; regnum++) |
1000 | saved_regs_addr->regs[regnum] = | |
1001 | frame_addr + 32 * 4 + (regnum - FP0_REGNUM - 32) * 4 | |
1002 | - DUMMY_STACK_REG_BUF_SIZE + 24 * SPARC_INTREG_SIZE; | |
c906108c | 1003 | #endif |
60054393 MS |
1004 | } |
1005 | ||
c906108c SS |
1006 | #ifdef GDB_TARGET_IS_SPARC64 |
1007 | for (regnum = PC_REGNUM; regnum < PC_REGNUM + 7; regnum++) | |
1008 | { | |
1009 | saved_regs_addr->regs[regnum] = | |
c5aa993b JM |
1010 | frame_addr + (regnum - PC_REGNUM) * SPARC_INTREG_SIZE |
1011 | - DUMMY_STACK_REG_BUF_SIZE; | |
c906108c | 1012 | } |
c5aa993b | 1013 | saved_regs_addr->regs[PSTATE_REGNUM] = |
c906108c SS |
1014 | frame_addr + 8 * SPARC_INTREG_SIZE - DUMMY_STACK_REG_BUF_SIZE; |
1015 | #else | |
1016 | for (regnum = Y_REGNUM; regnum < NUM_REGS; regnum++) | |
1017 | saved_regs_addr->regs[regnum] = | |
c5aa993b JM |
1018 | frame_addr + (regnum - Y_REGNUM) * SPARC_INTREG_SIZE |
1019 | - DUMMY_STACK_REG_BUF_SIZE; | |
c906108c SS |
1020 | #endif |
1021 | frame_addr = fi->bottom ? | |
1022 | fi->bottom : read_sp (); | |
1023 | } | |
1024 | else if (fi->flat) | |
1025 | { | |
1026 | CORE_ADDR func_start; | |
1027 | find_pc_partial_function (fi->pc, NULL, &func_start, NULL); | |
1028 | examine_prologue (func_start, 0, fi, saved_regs_addr); | |
1029 | ||
1030 | /* Flat register window frame. */ | |
1031 | saved_regs_addr->regs[RP_REGNUM] = fi->pc_addr; | |
1032 | saved_regs_addr->regs[I7_REGNUM] = fi->fp_addr; | |
1033 | } | |
1034 | else | |
1035 | { | |
1036 | /* Normal frame. Just Local and In registers */ | |
1037 | frame_addr = fi->bottom ? | |
1038 | fi->bottom : read_sp (); | |
c5aa993b | 1039 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; regnum++) |
c906108c SS |
1040 | saved_regs_addr->regs[regnum] = |
1041 | (frame_addr + (regnum - L0_REGNUM) * SPARC_INTREG_SIZE | |
1042 | + FRAME_SAVED_L0); | |
c5aa993b | 1043 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; regnum++) |
c906108c SS |
1044 | saved_regs_addr->regs[regnum] = |
1045 | (frame_addr + (regnum - I0_REGNUM) * SPARC_INTREG_SIZE | |
1046 | + FRAME_SAVED_I0); | |
1047 | } | |
1048 | if (fi->next) | |
1049 | { | |
1050 | if (fi->flat) | |
1051 | { | |
1052 | saved_regs_addr->regs[O7_REGNUM] = fi->pc_addr; | |
1053 | } | |
1054 | else | |
1055 | { | |
1056 | /* Pull off either the next frame pointer or the stack pointer */ | |
1057 | CORE_ADDR next_next_frame_addr = | |
c5aa993b JM |
1058 | (fi->next->bottom ? |
1059 | fi->next->bottom : | |
1060 | read_sp ()); | |
1061 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 8; regnum++) | |
c906108c SS |
1062 | saved_regs_addr->regs[regnum] = |
1063 | (next_next_frame_addr | |
1064 | + (regnum - O0_REGNUM) * SPARC_INTREG_SIZE | |
1065 | + FRAME_SAVED_I0); | |
1066 | } | |
1067 | } | |
1068 | /* Otherwise, whatever we would get from ptrace(GETREGS) is accurate */ | |
1069 | /* FIXME -- should this adjust for the sparc64 offset? */ | |
1070 | saved_regs_addr->regs[SP_REGNUM] = FRAME_FP (fi); | |
1071 | } | |
1072 | ||
1073 | /* Discard from the stack the innermost frame, restoring all saved registers. | |
1074 | ||
1075 | Note that the values stored in fsr by get_frame_saved_regs are *in | |
1076 | the context of the called frame*. What this means is that the i | |
1077 | regs of fsr must be restored into the o regs of the (calling) frame that | |
1078 | we pop into. We don't care about the output regs of the calling frame, | |
1079 | since unless it's a dummy frame, it won't have any output regs in it. | |
1080 | ||
1081 | We never have to bother with %l (local) regs, since the called routine's | |
1082 | locals get tossed, and the calling routine's locals are already saved | |
1083 | on its stack. */ | |
1084 | ||
1085 | /* Definitely see tm-sparc.h for more doc of the frame format here. */ | |
1086 | ||
1087 | void | |
1088 | sparc_pop_frame () | |
1089 | { | |
1090 | register struct frame_info *frame = get_current_frame (); | |
1091 | register CORE_ADDR pc; | |
1092 | struct frame_saved_regs fsr; | |
1093 | char raw_buffer[REGISTER_BYTES]; | |
1094 | int regnum; | |
1095 | ||
1096 | sparc_frame_find_saved_regs (frame, &fsr); | |
60054393 | 1097 | if (FP0_REGNUM >= 0) |
c906108c | 1098 | { |
60054393 MS |
1099 | if (fsr.regs[FP0_REGNUM]) |
1100 | { | |
1101 | read_memory (fsr.regs[FP0_REGNUM], raw_buffer, FP_REGISTER_BYTES); | |
1102 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM), | |
1103 | raw_buffer, FP_REGISTER_BYTES); | |
1104 | } | |
c906108c | 1105 | #ifndef GDB_TARGET_IS_SPARC64 |
60054393 MS |
1106 | if (fsr.regs[FPS_REGNUM]) |
1107 | { | |
1108 | read_memory (fsr.regs[FPS_REGNUM], raw_buffer, 4); | |
1109 | write_register_bytes (REGISTER_BYTE (FPS_REGNUM), raw_buffer, 4); | |
1110 | } | |
1111 | if (fsr.regs[CPS_REGNUM]) | |
1112 | { | |
1113 | read_memory (fsr.regs[CPS_REGNUM], raw_buffer, 4); | |
1114 | write_register_bytes (REGISTER_BYTE (CPS_REGNUM), raw_buffer, 4); | |
1115 | } | |
c906108c | 1116 | #endif |
60054393 | 1117 | } |
c906108c SS |
1118 | if (fsr.regs[G1_REGNUM]) |
1119 | { | |
1120 | read_memory (fsr.regs[G1_REGNUM], raw_buffer, 7 * SPARC_INTREG_SIZE); | |
1121 | write_register_bytes (REGISTER_BYTE (G1_REGNUM), raw_buffer, | |
1122 | 7 * SPARC_INTREG_SIZE); | |
1123 | } | |
1124 | ||
1125 | if (frame->flat) | |
1126 | { | |
1127 | /* Each register might or might not have been saved, need to test | |
c5aa993b | 1128 | individually. */ |
c906108c SS |
1129 | for (regnum = L0_REGNUM; regnum < L0_REGNUM + 8; ++regnum) |
1130 | if (fsr.regs[regnum]) | |
1131 | write_register (regnum, read_memory_integer (fsr.regs[regnum], | |
1132 | SPARC_INTREG_SIZE)); | |
1133 | for (regnum = I0_REGNUM; regnum < I0_REGNUM + 8; ++regnum) | |
1134 | if (fsr.regs[regnum]) | |
1135 | write_register (regnum, read_memory_integer (fsr.regs[regnum], | |
1136 | SPARC_INTREG_SIZE)); | |
1137 | ||
1138 | /* Handle all outs except stack pointer (o0-o5; o7). */ | |
1139 | for (regnum = O0_REGNUM; regnum < O0_REGNUM + 6; ++regnum) | |
1140 | if (fsr.regs[regnum]) | |
1141 | write_register (regnum, read_memory_integer (fsr.regs[regnum], | |
1142 | SPARC_INTREG_SIZE)); | |
1143 | if (fsr.regs[O0_REGNUM + 7]) | |
1144 | write_register (O0_REGNUM + 7, | |
1145 | read_memory_integer (fsr.regs[O0_REGNUM + 7], | |
1146 | SPARC_INTREG_SIZE)); | |
1147 | ||
1148 | write_sp (frame->frame); | |
1149 | } | |
1150 | else if (fsr.regs[I0_REGNUM]) | |
1151 | { | |
1152 | CORE_ADDR sp; | |
1153 | ||
1154 | char reg_temp[REGISTER_BYTES]; | |
1155 | ||
1156 | read_memory (fsr.regs[I0_REGNUM], raw_buffer, 8 * SPARC_INTREG_SIZE); | |
1157 | ||
1158 | /* Get the ins and locals which we are about to restore. Just | |
c5aa993b JM |
1159 | moving the stack pointer is all that is really needed, except |
1160 | store_inferior_registers is then going to write the ins and | |
1161 | locals from the registers array, so we need to muck with the | |
1162 | registers array. */ | |
c906108c SS |
1163 | sp = fsr.regs[SP_REGNUM]; |
1164 | #ifdef GDB_TARGET_IS_SPARC64 | |
1165 | if (sp & 1) | |
1166 | sp += 2047; | |
1167 | #endif | |
1168 | read_memory (sp, reg_temp, SPARC_INTREG_SIZE * 16); | |
1169 | ||
1170 | /* Restore the out registers. | |
c5aa993b | 1171 | Among other things this writes the new stack pointer. */ |
c906108c SS |
1172 | write_register_bytes (REGISTER_BYTE (O0_REGNUM), raw_buffer, |
1173 | SPARC_INTREG_SIZE * 8); | |
1174 | ||
1175 | write_register_bytes (REGISTER_BYTE (L0_REGNUM), reg_temp, | |
1176 | SPARC_INTREG_SIZE * 16); | |
1177 | } | |
1178 | #ifndef GDB_TARGET_IS_SPARC64 | |
1179 | if (fsr.regs[PS_REGNUM]) | |
1180 | write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4)); | |
1181 | #endif | |
1182 | if (fsr.regs[Y_REGNUM]) | |
1183 | write_register (Y_REGNUM, read_memory_integer (fsr.regs[Y_REGNUM], REGISTER_RAW_SIZE (Y_REGNUM))); | |
1184 | if (fsr.regs[PC_REGNUM]) | |
1185 | { | |
1186 | /* Explicitly specified PC (and maybe NPC) -- just restore them. */ | |
1187 | write_register (PC_REGNUM, read_memory_integer (fsr.regs[PC_REGNUM], | |
c5aa993b | 1188 | REGISTER_RAW_SIZE (PC_REGNUM))); |
c906108c SS |
1189 | if (fsr.regs[NPC_REGNUM]) |
1190 | write_register (NPC_REGNUM, | |
1191 | read_memory_integer (fsr.regs[NPC_REGNUM], | |
c5aa993b | 1192 | REGISTER_RAW_SIZE (NPC_REGNUM))); |
c906108c SS |
1193 | } |
1194 | else if (frame->flat) | |
1195 | { | |
1196 | if (frame->pc_addr) | |
1197 | pc = PC_ADJUST ((CORE_ADDR) | |
1198 | read_memory_integer (frame->pc_addr, | |
1199 | REGISTER_RAW_SIZE (PC_REGNUM))); | |
1200 | else | |
1201 | { | |
1202 | /* I think this happens only in the innermost frame, if so then | |
1203 | it is a complicated way of saying | |
1204 | "pc = read_register (O7_REGNUM);". */ | |
1205 | char buf[MAX_REGISTER_RAW_SIZE]; | |
1206 | get_saved_register (buf, 0, 0, frame, O7_REGNUM, 0); | |
1207 | pc = PC_ADJUST (extract_address | |
1208 | (buf, REGISTER_RAW_SIZE (O7_REGNUM))); | |
1209 | } | |
1210 | ||
c5aa993b | 1211 | write_register (PC_REGNUM, pc); |
c906108c SS |
1212 | write_register (NPC_REGNUM, pc + 4); |
1213 | } | |
1214 | else if (fsr.regs[I7_REGNUM]) | |
1215 | { | |
1216 | /* Return address in %i7 -- adjust it, then restore PC and NPC from it */ | |
1217 | pc = PC_ADJUST ((CORE_ADDR) read_memory_integer (fsr.regs[I7_REGNUM], | |
1218 | SPARC_INTREG_SIZE)); | |
c5aa993b | 1219 | write_register (PC_REGNUM, pc); |
c906108c SS |
1220 | write_register (NPC_REGNUM, pc + 4); |
1221 | } | |
1222 | flush_cached_frames (); | |
1223 | } | |
1224 | ||
1225 | /* On the Sun 4 under SunOS, the compile will leave a fake insn which | |
1226 | encodes the structure size being returned. If we detect such | |
1227 | a fake insn, step past it. */ | |
1228 | ||
1229 | CORE_ADDR | |
c5aa993b | 1230 | sparc_pc_adjust (pc) |
c906108c SS |
1231 | CORE_ADDR pc; |
1232 | { | |
1233 | unsigned long insn; | |
1234 | char buf[4]; | |
1235 | int err; | |
1236 | ||
1237 | err = target_read_memory (pc + 8, buf, 4); | |
1238 | insn = extract_unsigned_integer (buf, 4); | |
1239 | if ((err == 0) && (insn & 0xffc00000) == 0) | |
c5aa993b | 1240 | return pc + 12; |
c906108c | 1241 | else |
c5aa993b | 1242 | return pc + 8; |
c906108c SS |
1243 | } |
1244 | ||
1245 | /* If pc is in a shared library trampoline, return its target. | |
1246 | The SunOs 4.x linker rewrites the jump table entries for PIC | |
1247 | compiled modules in the main executable to bypass the dynamic linker | |
1248 | with jumps of the form | |
c5aa993b JM |
1249 | sethi %hi(addr),%g1 |
1250 | jmp %g1+%lo(addr) | |
c906108c SS |
1251 | and removes the corresponding jump table relocation entry in the |
1252 | dynamic relocations. | |
1253 | find_solib_trampoline_target relies on the presence of the jump | |
1254 | table relocation entry, so we have to detect these jump instructions | |
1255 | by hand. */ | |
1256 | ||
1257 | CORE_ADDR | |
1258 | sunos4_skip_trampoline_code (pc) | |
1259 | CORE_ADDR pc; | |
1260 | { | |
1261 | unsigned long insn1; | |
1262 | char buf[4]; | |
1263 | int err; | |
1264 | ||
1265 | err = target_read_memory (pc, buf, 4); | |
1266 | insn1 = extract_unsigned_integer (buf, 4); | |
1267 | if (err == 0 && (insn1 & 0xffc00000) == 0x03000000) | |
1268 | { | |
1269 | unsigned long insn2; | |
1270 | ||
1271 | err = target_read_memory (pc + 4, buf, 4); | |
1272 | insn2 = extract_unsigned_integer (buf, 4); | |
1273 | if (err == 0 && (insn2 & 0xffffe000) == 0x81c06000) | |
1274 | { | |
1275 | CORE_ADDR target_pc = (insn1 & 0x3fffff) << 10; | |
1276 | int delta = insn2 & 0x1fff; | |
1277 | ||
1278 | /* Sign extend the displacement. */ | |
1279 | if (delta & 0x1000) | |
1280 | delta |= ~0x1fff; | |
1281 | return target_pc + delta; | |
1282 | } | |
1283 | } | |
1284 | return find_solib_trampoline_target (pc); | |
1285 | } | |
1286 | \f | |
c5aa993b | 1287 | #ifdef USE_PROC_FS /* Target dependent support for /proc */ |
9846de1b | 1288 | /* *INDENT-OFF* */ |
c906108c SS |
1289 | /* The /proc interface divides the target machine's register set up into |
1290 | two different sets, the general register set (gregset) and the floating | |
1291 | point register set (fpregset). For each set, there is an ioctl to get | |
1292 | the current register set and another ioctl to set the current values. | |
1293 | ||
1294 | The actual structure passed through the ioctl interface is, of course, | |
1295 | naturally machine dependent, and is different for each set of registers. | |
1296 | For the sparc for example, the general register set is typically defined | |
1297 | by: | |
1298 | ||
1299 | typedef int gregset_t[38]; | |
1300 | ||
1301 | #define R_G0 0 | |
1302 | ... | |
1303 | #define R_TBR 37 | |
1304 | ||
1305 | and the floating point set by: | |
1306 | ||
1307 | typedef struct prfpregset { | |
1308 | union { | |
1309 | u_long pr_regs[32]; | |
1310 | double pr_dregs[16]; | |
1311 | } pr_fr; | |
1312 | void * pr_filler; | |
1313 | u_long pr_fsr; | |
1314 | u_char pr_qcnt; | |
1315 | u_char pr_q_entrysize; | |
1316 | u_char pr_en; | |
1317 | u_long pr_q[64]; | |
1318 | } prfpregset_t; | |
1319 | ||
1320 | These routines provide the packing and unpacking of gregset_t and | |
1321 | fpregset_t formatted data. | |
1322 | ||
1323 | */ | |
9846de1b | 1324 | /* *INDENT-ON* */ |
c906108c | 1325 | |
c5aa993b JM |
1326 | |
1327 | ||
c906108c SS |
1328 | /* Given a pointer to a general register set in /proc format (gregset_t *), |
1329 | unpack the register contents and supply them as gdb's idea of the current | |
1330 | register values. */ | |
1331 | ||
1332 | void | |
1333 | supply_gregset (gregsetp) | |
c5aa993b | 1334 | prgregset_t *gregsetp; |
c906108c SS |
1335 | { |
1336 | register int regi; | |
1337 | register prgreg_t *regp = (prgreg_t *) gregsetp; | |
c5aa993b JM |
1338 | static char zerobuf[MAX_REGISTER_RAW_SIZE] = |
1339 | {0}; | |
c906108c SS |
1340 | |
1341 | /* GDB register numbers for Gn, On, Ln, In all match /proc reg numbers. */ | |
c5aa993b | 1342 | for (regi = G0_REGNUM; regi <= I7_REGNUM; regi++) |
c906108c SS |
1343 | { |
1344 | supply_register (regi, (char *) (regp + regi)); | |
1345 | } | |
1346 | ||
1347 | /* These require a bit more care. */ | |
1348 | supply_register (PS_REGNUM, (char *) (regp + R_PS)); | |
1349 | supply_register (PC_REGNUM, (char *) (regp + R_PC)); | |
c5aa993b JM |
1350 | supply_register (NPC_REGNUM, (char *) (regp + R_nPC)); |
1351 | supply_register (Y_REGNUM, (char *) (regp + R_Y)); | |
c906108c SS |
1352 | |
1353 | /* Fill inaccessible registers with zero. */ | |
1354 | supply_register (WIM_REGNUM, zerobuf); | |
1355 | supply_register (TBR_REGNUM, zerobuf); | |
1356 | supply_register (CPS_REGNUM, zerobuf); | |
1357 | } | |
1358 | ||
1359 | void | |
1360 | fill_gregset (gregsetp, regno) | |
c5aa993b JM |
1361 | prgregset_t *gregsetp; |
1362 | int regno; | |
c906108c SS |
1363 | { |
1364 | int regi; | |
1365 | register prgreg_t *regp = (prgreg_t *) gregsetp; | |
1366 | ||
c5aa993b | 1367 | for (regi = 0; regi <= R_I7; regi++) |
c906108c SS |
1368 | { |
1369 | if ((regno == -1) || (regno == regi)) | |
1370 | { | |
1371 | *(regp + regi) = *(int *) ®isters[REGISTER_BYTE (regi)]; | |
1372 | } | |
1373 | } | |
1374 | if ((regno == -1) || (regno == PS_REGNUM)) | |
1375 | { | |
1376 | *(regp + R_PS) = *(int *) ®isters[REGISTER_BYTE (PS_REGNUM)]; | |
1377 | } | |
1378 | if ((regno == -1) || (regno == PC_REGNUM)) | |
1379 | { | |
1380 | *(regp + R_PC) = *(int *) ®isters[REGISTER_BYTE (PC_REGNUM)]; | |
1381 | } | |
1382 | if ((regno == -1) || (regno == NPC_REGNUM)) | |
1383 | { | |
1384 | *(regp + R_nPC) = *(int *) ®isters[REGISTER_BYTE (NPC_REGNUM)]; | |
1385 | } | |
1386 | if ((regno == -1) || (regno == Y_REGNUM)) | |
1387 | { | |
1388 | *(regp + R_Y) = *(int *) ®isters[REGISTER_BYTE (Y_REGNUM)]; | |
1389 | } | |
1390 | } | |
1391 | ||
c906108c | 1392 | /* Given a pointer to a floating point register set in /proc format |
c5aa993b JM |
1393 | (fpregset_t *), unpack the register contents and supply them as gdb's |
1394 | idea of the current floating point register values. */ | |
c906108c | 1395 | |
c5aa993b | 1396 | void |
c906108c | 1397 | supply_fpregset (fpregsetp) |
c5aa993b | 1398 | prfpregset_t *fpregsetp; |
c906108c SS |
1399 | { |
1400 | register int regi; | |
1401 | char *from; | |
c5aa993b | 1402 | |
60054393 MS |
1403 | if (FP0_REGNUM < 0) |
1404 | return; | |
1405 | ||
c5aa993b | 1406 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) |
c906108c | 1407 | { |
c5aa993b | 1408 | from = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
c906108c SS |
1409 | supply_register (regi, from); |
1410 | } | |
1411 | supply_register (FPS_REGNUM, (char *) &(fpregsetp->pr_fsr)); | |
1412 | } | |
1413 | ||
1414 | /* Given a pointer to a floating point register set in /proc format | |
c5aa993b JM |
1415 | (fpregset_t *), update the register specified by REGNO from gdb's idea |
1416 | of the current floating point register set. If REGNO is -1, update | |
1417 | them all. */ | |
c906108c SS |
1418 | /* ??? This will probably need some changes for sparc64. */ |
1419 | ||
1420 | void | |
1421 | fill_fpregset (fpregsetp, regno) | |
c5aa993b JM |
1422 | prfpregset_t *fpregsetp; |
1423 | int regno; | |
c906108c SS |
1424 | { |
1425 | int regi; | |
1426 | char *to; | |
1427 | char *from; | |
1428 | ||
60054393 MS |
1429 | if (FP0_REGNUM < 0) |
1430 | return; | |
1431 | ||
c5aa993b | 1432 | for (regi = FP0_REGNUM; regi < FP_MAX_REGNUM; regi++) |
c906108c SS |
1433 | { |
1434 | if ((regno == -1) || (regno == regi)) | |
1435 | { | |
1436 | from = (char *) ®isters[REGISTER_BYTE (regi)]; | |
c5aa993b | 1437 | to = (char *) &fpregsetp->pr_fr.pr_regs[regi - FP0_REGNUM]; |
c906108c SS |
1438 | memcpy (to, from, REGISTER_RAW_SIZE (regi)); |
1439 | } | |
1440 | } | |
1441 | if ((regno == -1) || (regno == FPS_REGNUM)) | |
1442 | { | |
1443 | fpregsetp->pr_fsr = *(int *) ®isters[REGISTER_BYTE (FPS_REGNUM)]; | |
1444 | } | |
1445 | } | |
1446 | ||
c5aa993b | 1447 | #endif /* USE_PROC_FS */ |
c906108c SS |
1448 | |
1449 | ||
1450 | #ifdef GET_LONGJMP_TARGET | |
1451 | ||
1452 | /* Figure out where the longjmp will land. We expect that we have just entered | |
1453 | longjmp and haven't yet setup the stack frame, so the args are still in the | |
1454 | output regs. %o0 (O0_REGNUM) points at the jmp_buf structure from which we | |
1455 | extract the pc (JB_PC) that we will land at. The pc is copied into ADDR. | |
1456 | This routine returns true on success */ | |
1457 | ||
1458 | int | |
1459 | get_longjmp_target (pc) | |
1460 | CORE_ADDR *pc; | |
1461 | { | |
1462 | CORE_ADDR jb_addr; | |
1463 | #define LONGJMP_TARGET_SIZE 4 | |
1464 | char buf[LONGJMP_TARGET_SIZE]; | |
1465 | ||
1466 | jb_addr = read_register (O0_REGNUM); | |
1467 | ||
1468 | if (target_read_memory (jb_addr + JB_PC * JB_ELEMENT_SIZE, buf, | |
1469 | LONGJMP_TARGET_SIZE)) | |
1470 | return 0; | |
1471 | ||
1472 | *pc = extract_address (buf, LONGJMP_TARGET_SIZE); | |
1473 | ||
1474 | return 1; | |
1475 | } | |
1476 | #endif /* GET_LONGJMP_TARGET */ | |
1477 | \f | |
1478 | #ifdef STATIC_TRANSFORM_NAME | |
1479 | /* SunPRO (3.0 at least), encodes the static variables. This is not | |
1480 | related to C++ mangling, it is done for C too. */ | |
1481 | ||
1482 | char * | |
1483 | sunpro_static_transform_name (name) | |
1484 | char *name; | |
1485 | { | |
1486 | char *p; | |
1487 | if (name[0] == '$') | |
1488 | { | |
1489 | /* For file-local statics there will be a dollar sign, a bunch | |
c5aa993b JM |
1490 | of junk (the contents of which match a string given in the |
1491 | N_OPT), a period and the name. For function-local statics | |
1492 | there will be a bunch of junk (which seems to change the | |
1493 | second character from 'A' to 'B'), a period, the name of the | |
1494 | function, and the name. So just skip everything before the | |
1495 | last period. */ | |
c906108c SS |
1496 | p = strrchr (name, '.'); |
1497 | if (p != NULL) | |
1498 | name = p + 1; | |
1499 | } | |
1500 | return name; | |
1501 | } | |
1502 | #endif /* STATIC_TRANSFORM_NAME */ | |
1503 | \f | |
1504 | ||
1505 | /* Utilities for printing registers. | |
1506 | Page numbers refer to the SPARC Architecture Manual. */ | |
1507 | ||
1508 | static void dump_ccreg PARAMS ((char *, int)); | |
1509 | ||
1510 | static void | |
1511 | dump_ccreg (reg, val) | |
1512 | char *reg; | |
1513 | int val; | |
1514 | { | |
1515 | /* page 41 */ | |
1516 | printf_unfiltered ("%s:%s,%s,%s,%s", reg, | |
c5aa993b JM |
1517 | val & 8 ? "N" : "NN", |
1518 | val & 4 ? "Z" : "NZ", | |
1519 | val & 2 ? "O" : "NO", | |
1520 | val & 1 ? "C" : "NC" | |
1521 | ); | |
c906108c SS |
1522 | } |
1523 | ||
1524 | static char * | |
1525 | decode_asi (val) | |
1526 | int val; | |
1527 | { | |
1528 | /* page 72 */ | |
1529 | switch (val) | |
1530 | { | |
c5aa993b JM |
1531 | case 4: |
1532 | return "ASI_NUCLEUS"; | |
1533 | case 0x0c: | |
1534 | return "ASI_NUCLEUS_LITTLE"; | |
1535 | case 0x10: | |
1536 | return "ASI_AS_IF_USER_PRIMARY"; | |
1537 | case 0x11: | |
1538 | return "ASI_AS_IF_USER_SECONDARY"; | |
1539 | case 0x18: | |
1540 | return "ASI_AS_IF_USER_PRIMARY_LITTLE"; | |
1541 | case 0x19: | |
1542 | return "ASI_AS_IF_USER_SECONDARY_LITTLE"; | |
1543 | case 0x80: | |
1544 | return "ASI_PRIMARY"; | |
1545 | case 0x81: | |
1546 | return "ASI_SECONDARY"; | |
1547 | case 0x82: | |
1548 | return "ASI_PRIMARY_NOFAULT"; | |
1549 | case 0x83: | |
1550 | return "ASI_SECONDARY_NOFAULT"; | |
1551 | case 0x88: | |
1552 | return "ASI_PRIMARY_LITTLE"; | |
1553 | case 0x89: | |
1554 | return "ASI_SECONDARY_LITTLE"; | |
1555 | case 0x8a: | |
1556 | return "ASI_PRIMARY_NOFAULT_LITTLE"; | |
1557 | case 0x8b: | |
1558 | return "ASI_SECONDARY_NOFAULT_LITTLE"; | |
1559 | default: | |
1560 | return NULL; | |
c906108c SS |
1561 | } |
1562 | } | |
1563 | ||
1564 | /* PRINT_REGISTER_HOOK routine. | |
1565 | Pretty print various registers. */ | |
1566 | /* FIXME: Would be nice if this did some fancy things for 32 bit sparc. */ | |
1567 | ||
1568 | void | |
1569 | sparc_print_register_hook (regno) | |
1570 | int regno; | |
1571 | { | |
1572 | ULONGEST val; | |
1573 | ||
1574 | /* Handle double/quad versions of lower 32 fp regs. */ | |
1575 | if (regno >= FP0_REGNUM && regno < FP0_REGNUM + 32 | |
1576 | && (regno & 1) == 0) | |
1577 | { | |
1578 | char value[16]; | |
1579 | ||
1580 | if (!read_relative_register_raw_bytes (regno, value) | |
1581 | && !read_relative_register_raw_bytes (regno + 1, value + 4)) | |
1582 | { | |
1583 | printf_unfiltered ("\t"); | |
1584 | print_floating (value, builtin_type_double, gdb_stdout); | |
1585 | } | |
c5aa993b | 1586 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
c906108c SS |
1587 | if ((regno & 3) == 0) |
1588 | { | |
1589 | if (!read_relative_register_raw_bytes (regno + 2, value + 8) | |
1590 | && !read_relative_register_raw_bytes (regno + 3, value + 12)) | |
1591 | { | |
1592 | printf_unfiltered ("\t"); | |
1593 | print_floating (value, builtin_type_long_double, gdb_stdout); | |
1594 | } | |
1595 | } | |
1596 | #endif | |
1597 | return; | |
1598 | } | |
1599 | ||
c5aa993b | 1600 | #if 0 /* FIXME: gdb doesn't handle long doubles */ |
c906108c SS |
1601 | /* Print upper fp regs as long double if appropriate. */ |
1602 | if (regno >= FP0_REGNUM + 32 && regno < FP_MAX_REGNUM | |
c5aa993b JM |
1603 | /* We test for even numbered regs and not a multiple of 4 because |
1604 | the upper fp regs are recorded as doubles. */ | |
c906108c SS |
1605 | && (regno & 1) == 0) |
1606 | { | |
1607 | char value[16]; | |
1608 | ||
1609 | if (!read_relative_register_raw_bytes (regno, value) | |
1610 | && !read_relative_register_raw_bytes (regno + 1, value + 8)) | |
1611 | { | |
1612 | printf_unfiltered ("\t"); | |
1613 | print_floating (value, builtin_type_long_double, gdb_stdout); | |
1614 | } | |
1615 | return; | |
1616 | } | |
1617 | #endif | |
1618 | ||
1619 | /* FIXME: Some of these are priviledged registers. | |
1620 | Not sure how they should be handled. */ | |
1621 | ||
1622 | #define BITS(n, mask) ((int) (((val) >> (n)) & (mask))) | |
1623 | ||
1624 | val = read_register (regno); | |
1625 | ||
1626 | /* pages 40 - 60 */ | |
1627 | switch (regno) | |
1628 | { | |
1629 | #ifdef GDB_TARGET_IS_SPARC64 | |
c5aa993b JM |
1630 | case CCR_REGNUM: |
1631 | printf_unfiltered ("\t"); | |
c906108c | 1632 | dump_ccreg ("xcc", val >> 4); |
c5aa993b | 1633 | printf_unfiltered (", "); |
c906108c SS |
1634 | dump_ccreg ("icc", val & 15); |
1635 | break; | |
c5aa993b | 1636 | case FPRS_REGNUM: |
c906108c SS |
1637 | printf ("\tfef:%d, du:%d, dl:%d", |
1638 | BITS (2, 1), BITS (1, 1), BITS (0, 1)); | |
1639 | break; | |
c5aa993b | 1640 | case FSR_REGNUM: |
c906108c | 1641 | { |
c5aa993b JM |
1642 | static char *fcc[4] = |
1643 | {"=", "<", ">", "?"}; | |
1644 | static char *rd[4] = | |
1645 | {"N", "0", "+", "-"}; | |
c906108c SS |
1646 | /* Long, yes, but I'd rather leave it as is and use a wide screen. */ |
1647 | printf ("\t0:%s, 1:%s, 2:%s, 3:%s, rd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, aexc:%d, cexc:%d", | |
1648 | fcc[BITS (10, 3)], fcc[BITS (32, 3)], | |
1649 | fcc[BITS (34, 3)], fcc[BITS (36, 3)], | |
1650 | rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7), | |
1651 | BITS (14, 7), BITS (13, 1), BITS (5, 31), BITS (0, 31)); | |
1652 | break; | |
1653 | } | |
c5aa993b | 1654 | case ASI_REGNUM: |
c906108c SS |
1655 | { |
1656 | char *asi = decode_asi (val); | |
1657 | if (asi != NULL) | |
1658 | printf ("\t%s", asi); | |
1659 | break; | |
1660 | } | |
c5aa993b | 1661 | case VER_REGNUM: |
c906108c SS |
1662 | printf ("\tmanuf:%d, impl:%d, mask:%d, maxtl:%d, maxwin:%d", |
1663 | BITS (48, 0xffff), BITS (32, 0xffff), | |
1664 | BITS (24, 0xff), BITS (8, 0xff), BITS (0, 31)); | |
1665 | break; | |
c5aa993b | 1666 | case PSTATE_REGNUM: |
c906108c | 1667 | { |
c5aa993b JM |
1668 | static char *mm[4] = |
1669 | {"tso", "pso", "rso", "?"}; | |
c906108c SS |
1670 | printf ("\tcle:%d, tle:%d, mm:%s, red:%d, pef:%d, am:%d, priv:%d, ie:%d, ag:%d", |
1671 | BITS (9, 1), BITS (8, 1), mm[BITS (6, 3)], BITS (5, 1), | |
1672 | BITS (4, 1), BITS (3, 1), BITS (2, 1), BITS (1, 1), | |
1673 | BITS (0, 1)); | |
1674 | break; | |
1675 | } | |
c5aa993b | 1676 | case TSTATE_REGNUM: |
c906108c SS |
1677 | /* FIXME: print all 4? */ |
1678 | break; | |
c5aa993b | 1679 | case TT_REGNUM: |
c906108c SS |
1680 | /* FIXME: print all 4? */ |
1681 | break; | |
c5aa993b | 1682 | case TPC_REGNUM: |
c906108c SS |
1683 | /* FIXME: print all 4? */ |
1684 | break; | |
c5aa993b | 1685 | case TNPC_REGNUM: |
c906108c SS |
1686 | /* FIXME: print all 4? */ |
1687 | break; | |
c5aa993b | 1688 | case WSTATE_REGNUM: |
c906108c SS |
1689 | printf ("\tother:%d, normal:%d", BITS (3, 7), BITS (0, 7)); |
1690 | break; | |
c5aa993b | 1691 | case CWP_REGNUM: |
c906108c SS |
1692 | printf ("\t%d", BITS (0, 31)); |
1693 | break; | |
c5aa993b | 1694 | case CANSAVE_REGNUM: |
c906108c SS |
1695 | printf ("\t%-2d before spill", BITS (0, 31)); |
1696 | break; | |
c5aa993b | 1697 | case CANRESTORE_REGNUM: |
c906108c SS |
1698 | printf ("\t%-2d before fill", BITS (0, 31)); |
1699 | break; | |
c5aa993b | 1700 | case CLEANWIN_REGNUM: |
c906108c SS |
1701 | printf ("\t%-2d before clean", BITS (0, 31)); |
1702 | break; | |
c5aa993b | 1703 | case OTHERWIN_REGNUM: |
c906108c SS |
1704 | printf ("\t%d", BITS (0, 31)); |
1705 | break; | |
1706 | #else | |
1707 | case PS_REGNUM: | |
1708 | printf ("\ticc:%c%c%c%c, pil:%d, s:%d, ps:%d, et:%d, cwp:%d", | |
1709 | BITS (23, 1) ? 'N' : '-', BITS (22, 1) ? 'Z' : '-', | |
1710 | BITS (21, 1) ? 'V' : '-', BITS (20, 1) ? 'C' : '-', | |
1711 | BITS (8, 15), BITS (7, 1), BITS (6, 1), BITS (5, 1), | |
1712 | BITS (0, 31)); | |
1713 | break; | |
1714 | case FPS_REGNUM: | |
1715 | { | |
c5aa993b JM |
1716 | static char *fcc[4] = |
1717 | {"=", "<", ">", "?"}; | |
1718 | static char *rd[4] = | |
1719 | {"N", "0", "+", "-"}; | |
c906108c SS |
1720 | /* Long, yes, but I'd rather leave it as is and use a wide screen. */ |
1721 | printf ("\trd:%s, tem:%d, ns:%d, ver:%d, ftt:%d, qne:%d, " | |
1722 | "fcc:%s, aexc:%d, cexc:%d", | |
1723 | rd[BITS (30, 3)], BITS (23, 31), BITS (22, 1), BITS (17, 7), | |
1724 | BITS (14, 7), BITS (13, 1), fcc[BITS (10, 3)], BITS (5, 31), | |
1725 | BITS (0, 31)); | |
1726 | break; | |
1727 | } | |
1728 | ||
c5aa993b | 1729 | #endif /* GDB_TARGET_IS_SPARC64 */ |
c906108c SS |
1730 | } |
1731 | ||
1732 | #undef BITS | |
1733 | } | |
1734 | \f | |
1735 | int | |
1736 | gdb_print_insn_sparc (memaddr, info) | |
1737 | bfd_vma memaddr; | |
1738 | disassemble_info *info; | |
1739 | { | |
1740 | /* It's necessary to override mach again because print_insn messes it up. */ | |
96baa820 | 1741 | info->mach = TARGET_ARCHITECTURE->mach; |
c906108c SS |
1742 | return print_insn_sparc (memaddr, info); |
1743 | } | |
1744 | \f | |
1745 | /* The SPARC passes the arguments on the stack; arguments smaller | |
1746 | than an int are promoted to an int. */ | |
1747 | ||
1748 | CORE_ADDR | |
1749 | sparc_push_arguments (nargs, args, sp, struct_return, struct_addr) | |
1750 | int nargs; | |
1751 | value_ptr *args; | |
1752 | CORE_ADDR sp; | |
1753 | int struct_return; | |
1754 | CORE_ADDR struct_addr; | |
1755 | { | |
1756 | int i; | |
1757 | int accumulate_size = 0; | |
1758 | struct sparc_arg | |
1759 | { | |
1760 | char *contents; | |
1761 | int len; | |
1762 | int offset; | |
1763 | }; | |
1764 | struct sparc_arg *sparc_args = | |
c5aa993b | 1765 | (struct sparc_arg *) alloca (nargs * sizeof (struct sparc_arg)); |
c906108c SS |
1766 | struct sparc_arg *m_arg; |
1767 | ||
1768 | /* Promote arguments if necessary, and calculate their stack offsets | |
1769 | and sizes. */ | |
1770 | for (i = 0, m_arg = sparc_args; i < nargs; i++, m_arg++) | |
1771 | { | |
1772 | value_ptr arg = args[i]; | |
1773 | struct type *arg_type = check_typedef (VALUE_TYPE (arg)); | |
1774 | /* Cast argument to long if necessary as the compiler does it too. */ | |
1775 | switch (TYPE_CODE (arg_type)) | |
1776 | { | |
1777 | case TYPE_CODE_INT: | |
1778 | case TYPE_CODE_BOOL: | |
1779 | case TYPE_CODE_CHAR: | |
1780 | case TYPE_CODE_RANGE: | |
1781 | case TYPE_CODE_ENUM: | |
1782 | if (TYPE_LENGTH (arg_type) < TYPE_LENGTH (builtin_type_long)) | |
1783 | { | |
1784 | arg_type = builtin_type_long; | |
1785 | arg = value_cast (arg_type, arg); | |
1786 | } | |
1787 | break; | |
1788 | default: | |
1789 | break; | |
1790 | } | |
1791 | m_arg->len = TYPE_LENGTH (arg_type); | |
1792 | m_arg->offset = accumulate_size; | |
1793 | accumulate_size = (accumulate_size + m_arg->len + 3) & ~3; | |
c5aa993b | 1794 | m_arg->contents = VALUE_CONTENTS (arg); |
c906108c SS |
1795 | } |
1796 | ||
1797 | /* Make room for the arguments on the stack. */ | |
1798 | accumulate_size += CALL_DUMMY_STACK_ADJUST; | |
1799 | sp = ((sp - accumulate_size) & ~7) + CALL_DUMMY_STACK_ADJUST; | |
1800 | ||
1801 | /* `Push' arguments on the stack. */ | |
c5aa993b JM |
1802 | for (i = nargs; m_arg--, --i >= 0;) |
1803 | write_memory (sp + m_arg->offset, m_arg->contents, m_arg->len); | |
c906108c SS |
1804 | |
1805 | return sp; | |
1806 | } | |
1807 | ||
1808 | ||
1809 | /* Extract from an array REGBUF containing the (raw) register state | |
1810 | a function return value of type TYPE, and copy that, in virtual format, | |
1811 | into VALBUF. */ | |
1812 | ||
1813 | void | |
1814 | sparc_extract_return_value (type, regbuf, valbuf) | |
1815 | struct type *type; | |
1816 | char *regbuf; | |
1817 | char *valbuf; | |
1818 | { | |
1819 | int typelen = TYPE_LENGTH (type); | |
1820 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); | |
1821 | ||
1822 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
c5aa993b | 1823 | memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen); |
c906108c SS |
1824 | else |
1825 | memcpy (valbuf, | |
c5aa993b JM |
1826 | ®buf[O0_REGNUM * regsize + |
1827 | (typelen >= regsize | |
1828 | || TARGET_BYTE_ORDER == LITTLE_ENDIAN ? 0 | |
1829 | : regsize - typelen)], | |
c906108c SS |
1830 | typelen); |
1831 | } | |
1832 | ||
1833 | ||
1834 | /* Write into appropriate registers a function return value | |
1835 | of type TYPE, given in virtual format. On SPARCs with FPUs, | |
1836 | float values are returned in %f0 (and %f1). In all other cases, | |
1837 | values are returned in register %o0. */ | |
1838 | ||
1839 | void | |
1840 | sparc_store_return_value (type, valbuf) | |
1841 | struct type *type; | |
1842 | char *valbuf; | |
1843 | { | |
1844 | int regno; | |
1845 | char buffer[MAX_REGISTER_RAW_SIZE]; | |
1846 | ||
1847 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
1848 | /* Floating-point values are returned in the register pair */ | |
1849 | /* formed by %f0 and %f1 (doubles are, anyway). */ | |
1850 | regno = FP0_REGNUM; | |
1851 | else | |
1852 | /* Other values are returned in register %o0. */ | |
1853 | regno = O0_REGNUM; | |
1854 | ||
1855 | /* Add leading zeros to the value. */ | |
c5aa993b | 1856 | if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (regno)) |
c906108c | 1857 | { |
c5aa993b JM |
1858 | bzero (buffer, REGISTER_RAW_SIZE (regno)); |
1859 | memcpy (buffer + REGISTER_RAW_SIZE (regno) - TYPE_LENGTH (type), valbuf, | |
c906108c | 1860 | TYPE_LENGTH (type)); |
c5aa993b JM |
1861 | write_register_bytes (REGISTER_BYTE (regno), buffer, |
1862 | REGISTER_RAW_SIZE (regno)); | |
c906108c SS |
1863 | } |
1864 | else | |
1865 | write_register_bytes (REGISTER_BYTE (regno), valbuf, TYPE_LENGTH (type)); | |
1866 | } | |
1867 | ||
1868 | ||
1869 | /* Insert the function address into a call dummy instruction sequence | |
1870 | stored at DUMMY. | |
1871 | ||
1872 | For structs and unions, if the function was compiled with Sun cc, | |
1873 | it expects 'unimp' after the call. But gcc doesn't use that | |
1874 | (twisted) convention. So leave a nop there for gcc (FIX_CALL_DUMMY | |
1875 | can assume it is operating on a pristine CALL_DUMMY, not one that | |
1876 | has already been customized for a different function). */ | |
1877 | ||
1878 | void | |
1879 | sparc_fix_call_dummy (dummy, pc, fun, value_type, using_gcc) | |
1880 | char *dummy; | |
1881 | CORE_ADDR pc; | |
1882 | CORE_ADDR fun; | |
1883 | struct type *value_type; | |
1884 | int using_gcc; | |
1885 | { | |
1886 | int i; | |
1887 | ||
1888 | /* Store the relative adddress of the target function into the | |
1889 | 'call' instruction. */ | |
1890 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET, 4, | |
1891 | (0x40000000 | |
1892 | | (((fun - (pc + CALL_DUMMY_CALL_OFFSET)) >> 2) | |
c5aa993b | 1893 | & 0x3fffffff))); |
c906108c SS |
1894 | |
1895 | /* Comply with strange Sun cc calling convention for struct-returning | |
1896 | functions. */ | |
1897 | if (!using_gcc | |
1898 | && (TYPE_CODE (value_type) == TYPE_CODE_STRUCT | |
1899 | || TYPE_CODE (value_type) == TYPE_CODE_UNION)) | |
1900 | store_unsigned_integer (dummy + CALL_DUMMY_CALL_OFFSET + 8, 4, | |
1901 | TYPE_LENGTH (value_type) & 0x1fff); | |
1902 | ||
1903 | #ifndef GDB_TARGET_IS_SPARC64 | |
1904 | /* If this is not a simulator target, change the first four instructions | |
1905 | of the call dummy to NOPs. Those instructions include a 'save' | |
1906 | instruction and are designed to work around problems with register | |
1907 | window flushing in the simulator. */ | |
1908 | if (strcmp (target_shortname, "sim") != 0) | |
1909 | { | |
1910 | for (i = 0; i < 4; i++) | |
1911 | store_unsigned_integer (dummy + (i * 4), 4, 0x01000000); | |
1912 | } | |
1913 | #endif | |
1914 | ||
1915 | /* If this is a bi-endian target, GDB has written the call dummy | |
1916 | in little-endian order. We must byte-swap it back to big-endian. */ | |
1917 | if (bi_endian) | |
1918 | { | |
1919 | for (i = 0; i < CALL_DUMMY_LENGTH; i += 4) | |
1920 | { | |
c5aa993b JM |
1921 | char tmp = dummy[i]; |
1922 | dummy[i] = dummy[i + 3]; | |
1923 | dummy[i + 3] = tmp; | |
1924 | tmp = dummy[i + 1]; | |
1925 | dummy[i + 1] = dummy[i + 2]; | |
1926 | dummy[i + 2] = tmp; | |
c906108c SS |
1927 | } |
1928 | } | |
1929 | } | |
1930 | ||
1931 | ||
1932 | /* Set target byte order based on machine type. */ | |
1933 | ||
1934 | static int | |
1935 | sparc_target_architecture_hook (ap) | |
1936 | const bfd_arch_info_type *ap; | |
1937 | { | |
1938 | int i, j; | |
1939 | ||
1940 | if (ap->mach == bfd_mach_sparc_sparclite_le) | |
1941 | { | |
1942 | if (TARGET_BYTE_ORDER_SELECTABLE_P) | |
1943 | { | |
1944 | target_byte_order = LITTLE_ENDIAN; | |
1945 | bi_endian = 1; | |
1946 | } | |
1947 | else | |
1948 | { | |
1949 | warning ("This GDB does not support little endian sparclite."); | |
1950 | } | |
1951 | } | |
1952 | else | |
1953 | bi_endian = 0; | |
1954 | return 1; | |
1955 | } | |
c906108c | 1956 | \f |
c5aa993b | 1957 | |
c906108c SS |
1958 | void |
1959 | _initialize_sparc_tdep () | |
1960 | { | |
1961 | tm_print_insn = gdb_print_insn_sparc; | |
c5aa993b | 1962 | tm_print_insn_info.mach = TM_PRINT_INSN_MACH; /* Selects sparc/sparclite */ |
c906108c SS |
1963 | target_architecture_hook = sparc_target_architecture_hook; |
1964 | } | |
1965 | ||
1966 | ||
1967 | #ifdef GDB_TARGET_IS_SPARC64 | |
1968 | ||
1969 | /* Compensate for stack bias. Note that we currently don't handle mixed | |
1970 | 32/64 bit code. */ | |
1971 | CORE_ADDR | |
1972 | sparc64_read_sp () | |
1973 | { | |
1974 | CORE_ADDR sp = read_register (SP_REGNUM); | |
1975 | ||
1976 | if (sp & 1) | |
1977 | sp += 2047; | |
1978 | return sp; | |
1979 | } | |
1980 | ||
1981 | CORE_ADDR | |
1982 | sparc64_read_fp () | |
1983 | { | |
1984 | CORE_ADDR fp = read_register (FP_REGNUM); | |
1985 | ||
1986 | if (fp & 1) | |
1987 | fp += 2047; | |
1988 | return fp; | |
1989 | } | |
1990 | ||
1991 | void | |
1992 | sparc64_write_sp (val) | |
1993 | CORE_ADDR val; | |
1994 | { | |
1995 | CORE_ADDR oldsp = read_register (SP_REGNUM); | |
1996 | if (oldsp & 1) | |
1997 | write_register (SP_REGNUM, val - 2047); | |
1998 | else | |
1999 | write_register (SP_REGNUM, val); | |
2000 | } | |
2001 | ||
2002 | void | |
2003 | sparc64_write_fp (val) | |
2004 | CORE_ADDR val; | |
2005 | { | |
2006 | CORE_ADDR oldfp = read_register (FP_REGNUM); | |
2007 | if (oldfp & 1) | |
2008 | write_register (FP_REGNUM, val - 2047); | |
2009 | else | |
2010 | write_register (FP_REGNUM, val); | |
2011 | } | |
2012 | ||
2013 | /* The SPARC 64 ABI passes floating-point arguments in FP0-31. They are | |
2014 | also copied onto the stack in the correct places. */ | |
2015 | ||
2016 | CORE_ADDR | |
2017 | sp64_push_arguments (nargs, args, sp, struct_return, struct_retaddr) | |
2018 | int nargs; | |
2019 | value_ptr *args; | |
2020 | CORE_ADDR sp; | |
2021 | unsigned char struct_return; | |
2022 | CORE_ADDR struct_retaddr; | |
2023 | { | |
2024 | int x; | |
2025 | int regnum = 0; | |
2026 | CORE_ADDR tempsp; | |
c5aa993b JM |
2027 | |
2028 | sp = (sp & ~(((unsigned long) TYPE_LENGTH (builtin_type_long)) - 1UL)); | |
c906108c SS |
2029 | |
2030 | /* Figure out how much space we'll need. */ | |
2031 | for (x = nargs - 1; x >= 0; x--) | |
2032 | { | |
2033 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x]))); | |
2034 | value_ptr copyarg = args[x]; | |
2035 | int copylen = len; | |
2036 | ||
2037 | /* This code is, of course, no longer correct. */ | |
2038 | if (copylen < TYPE_LENGTH (builtin_type_long)) | |
2039 | { | |
c5aa993b JM |
2040 | copyarg = value_cast (builtin_type_long, copyarg); |
2041 | copylen = TYPE_LENGTH (builtin_type_long); | |
2042 | } | |
c906108c SS |
2043 | sp -= copylen; |
2044 | } | |
2045 | ||
2046 | /* Round down. */ | |
2047 | sp = sp & ~7; | |
2048 | tempsp = sp; | |
2049 | ||
2050 | /* Now write the arguments onto the stack, while writing FP arguments | |
2051 | into the FP registers. */ | |
2052 | for (x = 0; x < nargs; x++) | |
2053 | { | |
2054 | int len = TYPE_LENGTH (check_typedef (VALUE_TYPE (args[x]))); | |
2055 | value_ptr copyarg = args[x]; | |
2056 | int copylen = len; | |
2057 | ||
2058 | /* This code is, of course, no longer correct. */ | |
2059 | if (copylen < TYPE_LENGTH (builtin_type_long)) | |
2060 | { | |
c5aa993b JM |
2061 | copyarg = value_cast (builtin_type_long, copyarg); |
2062 | copylen = TYPE_LENGTH (builtin_type_long); | |
2063 | } | |
c906108c SS |
2064 | write_memory (tempsp, VALUE_CONTENTS (copyarg), copylen); |
2065 | tempsp += copylen; | |
2066 | if (TYPE_CODE (VALUE_TYPE (args[x])) == TYPE_CODE_FLT && regnum < 32) | |
2067 | { | |
2068 | /* This gets copied into a FP register. */ | |
2069 | int nextreg = regnum + 2; | |
2070 | char *data = VALUE_CONTENTS (args[x]); | |
2071 | /* Floats go into the lower half of a FP register pair; quads | |
2072 | use 2 pairs. */ | |
2073 | ||
2074 | if (len == 16) | |
2075 | nextreg += 2; | |
2076 | else if (len == 4) | |
2077 | regnum++; | |
2078 | ||
2079 | write_register_bytes (REGISTER_BYTE (FP0_REGNUM + regnum), | |
2080 | data, | |
2081 | len); | |
2082 | regnum = nextreg; | |
2083 | } | |
2084 | } | |
2085 | return sp; | |
2086 | } | |
2087 | ||
2088 | /* Values <= 32 bytes are returned in o0-o3 (floating-point values are | |
2089 | returned in f0-f3). */ | |
2090 | void | |
2091 | sparc64_extract_return_value (type, regbuf, valbuf, bitoffset) | |
2092 | struct type *type; | |
2093 | char *regbuf; | |
2094 | char *valbuf; | |
2095 | int bitoffset; | |
2096 | { | |
2097 | int typelen = TYPE_LENGTH (type); | |
2098 | int regsize = REGISTER_RAW_SIZE (O0_REGNUM); | |
2099 | ||
2100 | if (TYPE_CODE (type) == TYPE_CODE_FLT && SPARC_HAS_FPU) | |
2101 | { | |
c5aa993b | 2102 | memcpy (valbuf, ®buf[REGISTER_BYTE (FP0_REGNUM)], typelen); |
c906108c SS |
2103 | return; |
2104 | } | |
2105 | ||
2106 | if (TYPE_CODE (type) != TYPE_CODE_STRUCT | |
2107 | || (TYPE_LENGTH (type) > 32)) | |
2108 | { | |
2109 | memcpy (valbuf, | |
c5aa993b | 2110 | ®buf[O0_REGNUM * regsize + |
c906108c SS |
2111 | (typelen >= regsize ? 0 : regsize - typelen)], |
2112 | typelen); | |
2113 | return; | |
2114 | } | |
2115 | else | |
2116 | { | |
2117 | char *o0 = ®buf[O0_REGNUM * regsize]; | |
2118 | char *f0 = ®buf[FP0_REGNUM * regsize]; | |
2119 | int x; | |
2120 | ||
2121 | for (x = 0; x < TYPE_NFIELDS (type); x++) | |
2122 | { | |
c5aa993b | 2123 | struct field *f = &TYPE_FIELDS (type)[x]; |
c906108c SS |
2124 | /* FIXME: We may need to handle static fields here. */ |
2125 | int whichreg = (f->loc.bitpos + bitoffset) / 32; | |
2126 | int remainder = ((f->loc.bitpos + bitoffset) % 32) / 8; | |
2127 | int where = (f->loc.bitpos + bitoffset) / 8; | |
2128 | int size = TYPE_LENGTH (f->type); | |
2129 | int typecode = TYPE_CODE (f->type); | |
2130 | ||
2131 | if (typecode == TYPE_CODE_STRUCT) | |
2132 | { | |
2133 | sparc64_extract_return_value (f->type, | |
2134 | regbuf, | |
2135 | valbuf, | |
2136 | bitoffset + f->loc.bitpos); | |
2137 | } | |
2138 | else if (typecode == TYPE_CODE_FLT) | |
2139 | { | |
2140 | memcpy (valbuf + where, &f0[whichreg * 4] + remainder, size); | |
2141 | } | |
2142 | else | |
2143 | { | |
2144 | memcpy (valbuf + where, &o0[whichreg * 4] + remainder, size); | |
2145 | } | |
2146 | } | |
2147 | } | |
2148 | } | |
2acceee2 JM |
2149 | |
2150 | ||
c906108c | 2151 | #endif |