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618f726f | 1 | # Copyright (C) 2008-2016 Free Software Foundation, Inc. |
604c2f83 LM |
2 | # |
3 | # This program is free software; you can redistribute it and/or modify | |
4 | # it under the terms of the GNU General Public License as published by | |
5 | # the Free Software Foundation; either version 3 of the License, or | |
6 | # (at your option) any later version. | |
7 | # | |
8 | # This program is distributed in the hope that it will be useful, | |
9 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | # GNU General Public License for more details. | |
12 | # | |
13 | # You should have received a copy of the GNU General Public License | |
14 | # along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | # | |
604c2f83 | 16 | |
604c2f83 LM |
17 | # |
18 | # Test the use of VSX registers, for Powerpc. | |
19 | # | |
20 | ||
604c2f83 LM |
21 | |
22 | if {![istarget "powerpc*"] || [skip_vsx_tests]} then { | |
23 | verbose "Skipping vsx register tests." | |
604c2f83 LM |
24 | return |
25 | } | |
26 | ||
27 | set testfile "vsx-regs" | |
28 | set binfile ${objdir}/${subdir}/${testfile} | |
29 | set srcfile ${testfile}.c | |
30 | ||
31 | set compile_flags {debug nowarnings quiet} | |
4c93b1db | 32 | if [get_compiler_info] { |
604c2f83 LM |
33 | warning "get_compiler failed" |
34 | return -1 | |
35 | } | |
36 | ||
37 | if [test_compiler_info gcc*] { | |
38 | set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec" | |
39 | } elseif [test_compiler_info xlc*] { | |
40 | set compile_flags "$compile_flags additional_flags=-qaltivec" | |
41 | } else { | |
42 | warning "unknown compiler" | |
43 | return -1 | |
44 | } | |
45 | ||
46 | if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } { | |
47 | untested vsx-regs.exp | |
48 | return -1 | |
49 | } | |
50 | ||
51 | gdb_start | |
52 | gdb_reinitialize_dir $srcdir/$subdir | |
53 | gdb_load ${binfile} | |
54 | ||
55 | # Run to `main' where we begin our tests. | |
56 | ||
57 | if ![runto_main] then { | |
58 | gdb_suppress_tests | |
59 | } | |
60 | ||
084ee545 UW |
61 | set endianness "" |
62 | set msg "detect endianness" | |
63 | gdb_test_multiple "show endian" "$msg" { | |
64 | -re "(The target endianness is set automatically .currently )(big|little)( endian.*)$gdb_prompt $" { | |
65 | pass "$msg" | |
66 | set endianness $expect_out(2,string) | |
67 | } | |
68 | -re ".*$gdb_prompt $" { | |
69 | fail "$msg" | |
70 | } | |
71 | } | |
72 | ||
604c2f83 LM |
73 | # Data sets used throughout the test |
74 | ||
084ee545 UW |
75 | if {$endianness == "big"} { |
76 | set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." | |
77 | ||
78 | set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." | |
4572cbac | 79 | |
084ee545 | 80 | set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." |
d9492458 | 81 | |
084ee545 | 82 | set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." |
604c2f83 | 83 | |
084ee545 UW |
84 | set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." |
85 | ||
86 | set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." | |
87 | } else { | |
88 | set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x0, 0x1., v4_float = .0x0, 0x0, 0xf99999a0, 0x1., v4_int32 = .0x0, 0x0, 0xcccccccc, 0x3ff4cccc., v8_int16 = .0x0, 0x0, 0x0, 0x0, 0xcccc, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." | |
d9492458 | 89 | |
084ee545 | 90 | set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x0, 0x0, 0xf99999a0, 0x1., v4_int32 = .0x1, 0x1, 0xcccccccc, 0x3ff4cccc., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0xcccc, 0xcccc, 0xcccc, 0x3ff4., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xf4, 0x3f.." |
604c2f83 | 91 | |
084ee545 UW |
92 | set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." |
93 | ||
94 | set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead., v16_int8 = .0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde, 0xef, 0xbe, 0xad, 0xde.." | |
95 | ||
96 | set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." | |
97 | ||
98 | set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0., v16_int8 = .0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0.." | |
99 | } | |
604c2f83 LM |
100 | |
101 | set float_register ".raw 0xdeadbeefdeadbeef." | |
102 | ||
103 | # First run the F0~F31/VS0~VS31 tests | |
104 | ||
105 | # 1: Set F0~F31 registers and check if it reflects on VS0~VS31. | |
106 | for {set i 0} {$i < 32} {incr i 1} { | |
4572cbac | 107 | gdb_test_no_output "set \$f$i = 1\.3" |
604c2f83 LM |
108 | } |
109 | ||
110 | for {set i 0} {$i < 32} {incr i 1} { | |
111 | gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)" | |
112 | } | |
113 | ||
114 | # 2: Set VS0~VS31 registers and check if it reflects on F0~F31. | |
115 | for {set i 0} {$i < 32} {incr i 1} { | |
116 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 117 | gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef" |
604c2f83 LM |
118 | } |
119 | } | |
120 | ||
121 | for {set i 0} {$i < 32} {incr i 1} { | |
122 | gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i" | |
123 | } | |
124 | ||
125 | for {set i 0} {$i < 32} {incr i 1} { | |
126 | gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)" | |
127 | } | |
128 | ||
129 | # Now run the VR0~VR31/VS32~VS63 tests | |
130 | ||
131 | # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63. | |
132 | for {set i 0} {$i < 32} {incr i 1} { | |
133 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 134 | gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1" |
604c2f83 LM |
135 | } |
136 | } | |
137 | ||
138 | for {set i 32} {$i < 64} {incr i 1} { | |
139 | gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i" | |
140 | } | |
141 | # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31. | |
142 | for {set i 32} {$i < 64} {incr i 1} { | |
143 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 144 | gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1" |
604c2f83 LM |
145 | } |
146 | } | |
147 | ||
148 | for {set i 0} {$i < 32} {incr i 1} { | |
4572cbac | 149 | gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i" |
604c2f83 LM |
150 | } |
151 | ||
d9492458 TJB |
152 | # Create a core file. We create the core file before the F32~F63/VR0~VR31 test |
153 | # below because then we'll have more interesting register values to verify | |
154 | # later when loading the core file (i.e., different register values for different | |
155 | # vector register banks). | |
156 | ||
fac51dd9 DE |
157 | set corefile "${objdir}/${subdir}/vsx-core.test" |
158 | set core_supported [gdb_gcore_cmd "$corefile" "Save a VSX-enabled corefile"] | |
604c2f83 | 159 | |
d9492458 TJB |
160 | # Now run the F32~F63/VR0~VR31 tests. |
161 | ||
162 | # 1: Set F32~F63 registers and check if it reflects on VR0~VR31. | |
163 | for {set i 32} {$i < 64} {incr i 1} { | |
164 | gdb_test_no_output "set \$f$i = 1\.3" | |
165 | } | |
166 | ||
167 | for {set i 0} {$i < 32} {incr i 1} { | |
168 | gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)" | |
169 | } | |
170 | ||
171 | # 2: Set VR0~VR31 registers and check if it reflects on F32~F63. | |
172 | for {set i 0} {$i < 32} {incr i 1} { | |
173 | for {set j 0} {$j < 4} {incr j 1} { | |
174 | gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef" | |
175 | } | |
176 | } | |
177 | ||
178 | for {set i 32} {$i < 64} {incr i 1} { | |
179 | gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i" | |
180 | } | |
181 | ||
182 | for {set i 0} {$i < 32} {incr i 1} { | |
183 | gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)" | |
184 | } | |
185 | ||
186 | # Test reading the core file. | |
187 | ||
604c2f83 LM |
188 | if {!$core_supported} { |
189 | return -1 | |
190 | } | |
191 | ||
192 | gdb_exit | |
193 | gdb_start | |
194 | gdb_reinitialize_dir $srcdir/$subdir | |
195 | gdb_load ${binfile} | |
196 | ||
fac51dd9 DE |
197 | set core_loaded [gdb_core_cmd "$corefile" "re-load generated corefile"] |
198 | if { $core_loaded == -1 } { | |
199 | # No use proceeding from here. | |
200 | return | |
604c2f83 LM |
201 | } |
202 | ||
203 | for {set i 0} {$i < 32} {incr i 1} { | |
204 | gdb_test "info reg vs$i" "vs$i.*$vector_register2" "Restore vs$i from core file" | |
205 | } | |
206 | ||
207 | for {set i 32} {$i < 64} {incr i 1} { | |
208 | gdb_test "info reg vs$i" "vs$i.*$vector_register3" "Restore vs$i from core file" | |
209 | } |