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28e7fd62 | 1 | # Copyright (C) 2008-2013 Free Software Foundation, Inc. |
604c2f83 LM |
2 | # |
3 | # This program is free software; you can redistribute it and/or modify | |
4 | # it under the terms of the GNU General Public License as published by | |
5 | # the Free Software Foundation; either version 3 of the License, or | |
6 | # (at your option) any later version. | |
7 | # | |
8 | # This program is distributed in the hope that it will be useful, | |
9 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | # GNU General Public License for more details. | |
12 | # | |
13 | # You should have received a copy of the GNU General Public License | |
14 | # along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | # | |
604c2f83 | 16 | |
604c2f83 LM |
17 | # |
18 | # Test the use of VSX registers, for Powerpc. | |
19 | # | |
20 | ||
604c2f83 LM |
21 | |
22 | if {![istarget "powerpc*"] || [skip_vsx_tests]} then { | |
23 | verbose "Skipping vsx register tests." | |
604c2f83 LM |
24 | return |
25 | } | |
26 | ||
27 | set testfile "vsx-regs" | |
28 | set binfile ${objdir}/${subdir}/${testfile} | |
29 | set srcfile ${testfile}.c | |
30 | ||
31 | set compile_flags {debug nowarnings quiet} | |
4c93b1db | 32 | if [get_compiler_info] { |
604c2f83 LM |
33 | warning "get_compiler failed" |
34 | return -1 | |
35 | } | |
36 | ||
37 | if [test_compiler_info gcc*] { | |
38 | set compile_flags "$compile_flags additional_flags=-maltivec additional_flags=-mabi=altivec" | |
39 | } elseif [test_compiler_info xlc*] { | |
40 | set compile_flags "$compile_flags additional_flags=-qaltivec" | |
41 | } else { | |
42 | warning "unknown compiler" | |
43 | return -1 | |
44 | } | |
45 | ||
46 | if { [gdb_compile ${srcdir}/${subdir}/${srcfile} ${binfile} executable $compile_flags] != "" } { | |
47 | untested vsx-regs.exp | |
48 | return -1 | |
49 | } | |
50 | ||
51 | gdb_start | |
52 | gdb_reinitialize_dir $srcdir/$subdir | |
53 | gdb_load ${binfile} | |
54 | ||
55 | # Run to `main' where we begin our tests. | |
56 | ||
57 | if ![runto_main] then { | |
58 | gdb_suppress_tests | |
59 | } | |
60 | ||
61 | # Data sets used throughout the test | |
62 | ||
4572cbac TJB |
63 | set vector_register1 ".uint128 = 0x3ff4cccccccccccc0000000000000000, v2_double = .0x1, 0x0., v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x0, 0x0., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x0, 0x0, 0x0., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0.." |
64 | ||
d9492458 TJB |
65 | set vector_register1_vr ".uint128 = 0x3ff4cccccccccccc0000000100000001, v4_float = .0x1, 0xf99999a0, 0x0, 0x0., v4_int32 = .0x3ff4cccc, 0xcccccccc, 0x1, 0x1., v8_int16 = .0x3ff4, 0xcccc, 0xcccc, 0xcccc, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x3f, 0xf4, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0xcc, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." |
66 | ||
4572cbac | 67 | set vector_register2 "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v2_double = .0x1, 0x1., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." |
604c2f83 | 68 | |
d9492458 TJB |
69 | set vector_register2_vr "uint128 = 0xdeadbeefdeadbeefdeadbeefdeadbeef, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef., v8_int16 = .0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef, 0xdead, 0xbeef., v16_int8 = .0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef, 0xde, 0xad, 0xbe, 0xef.." |
70 | ||
4572cbac | 71 | set vector_register3 ".uint128 = 0x00000001000000010000000100000001, v2_double = .0x0, 0x0., v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." |
604c2f83 | 72 | |
4572cbac | 73 | set vector_register3_vr ".uint128 = 0x00000001000000010000000100000001, v4_float = .0x0, 0x0, 0x0, 0x0., v4_int32 = .0x1, 0x1, 0x1, 0x1., v8_int16 = .0x0, 0x1, 0x0, 0x1, 0x0, 0x1, 0x0, 0x1., v16_int8 = .0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x1.." |
604c2f83 LM |
74 | |
75 | set float_register ".raw 0xdeadbeefdeadbeef." | |
76 | ||
77 | # First run the F0~F31/VS0~VS31 tests | |
78 | ||
79 | # 1: Set F0~F31 registers and check if it reflects on VS0~VS31. | |
80 | for {set i 0} {$i < 32} {incr i 1} { | |
4572cbac | 81 | gdb_test_no_output "set \$f$i = 1\.3" |
604c2f83 LM |
82 | } |
83 | ||
84 | for {set i 0} {$i < 32} {incr i 1} { | |
85 | gdb_test "info reg vs$i" "vs$i.*$vector_register1" "info reg vs$i (doubleword 0)" | |
86 | } | |
87 | ||
88 | # 2: Set VS0~VS31 registers and check if it reflects on F0~F31. | |
89 | for {set i 0} {$i < 32} {incr i 1} { | |
90 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 91 | gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 0xdeadbeef" |
604c2f83 LM |
92 | } |
93 | } | |
94 | ||
95 | for {set i 0} {$i < 32} {incr i 1} { | |
96 | gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i" | |
97 | } | |
98 | ||
99 | for {set i 0} {$i < 32} {incr i 1} { | |
100 | gdb_test "info reg vs$i" "vs$i.*$vector_register2" "info reg vs$i (doubleword 1)" | |
101 | } | |
102 | ||
103 | # Now run the VR0~VR31/VS32~VS63 tests | |
104 | ||
105 | # 1: Set VR0~VR31 registers and check if it reflects on VS32~VS63. | |
106 | for {set i 0} {$i < 32} {incr i 1} { | |
107 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 108 | gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 1" |
604c2f83 LM |
109 | } |
110 | } | |
111 | ||
112 | for {set i 32} {$i < 64} {incr i 1} { | |
113 | gdb_test "info reg vs$i" "vs$i.*$vector_register3" "info reg vs$i" | |
114 | } | |
115 | # 2: Set VS32~VS63 registers and check if it reflects on VR0~VR31. | |
116 | for {set i 32} {$i < 64} {incr i 1} { | |
117 | for {set j 0} {$j < 4} {incr j 1} { | |
4572cbac | 118 | gdb_test_no_output "set \$vs$i.v4_int32\[$j\] = 1" |
604c2f83 LM |
119 | } |
120 | } | |
121 | ||
122 | for {set i 0} {$i < 32} {incr i 1} { | |
4572cbac | 123 | gdb_test "info reg vr$i" "vr$i.*$vector_register3_vr" "info reg vr$i" |
604c2f83 LM |
124 | } |
125 | ||
d9492458 TJB |
126 | # Create a core file. We create the core file before the F32~F63/VR0~VR31 test |
127 | # below because then we'll have more interesting register values to verify | |
128 | # later when loading the core file (i.e., different register values for different | |
129 | # vector register banks). | |
130 | ||
2d338fa9 TT |
131 | set core_supported [gdb_gcore_cmd "${objdir}/${subdir}/vsx-core.test" \ |
132 | "Save a VSX-enabled corefile"] | |
604c2f83 | 133 | |
d9492458 TJB |
134 | # Now run the F32~F63/VR0~VR31 tests. |
135 | ||
136 | # 1: Set F32~F63 registers and check if it reflects on VR0~VR31. | |
137 | for {set i 32} {$i < 64} {incr i 1} { | |
138 | gdb_test_no_output "set \$f$i = 1\.3" | |
139 | } | |
140 | ||
141 | for {set i 0} {$i < 32} {incr i 1} { | |
142 | gdb_test "info reg vr$i" "vr$i.*$vector_register1_vr" "info reg vr$i (doubleword 0)" | |
143 | } | |
144 | ||
145 | # 2: Set VR0~VR31 registers and check if it reflects on F32~F63. | |
146 | for {set i 0} {$i < 32} {incr i 1} { | |
147 | for {set j 0} {$j < 4} {incr j 1} { | |
148 | gdb_test_no_output "set \$vr$i.v4_int32\[$j\] = 0xdeadbeef" | |
149 | } | |
150 | } | |
151 | ||
152 | for {set i 32} {$i < 64} {incr i 1} { | |
153 | gdb_test "info reg f$i" "f$i.*$float_register" "info reg f$i" | |
154 | } | |
155 | ||
156 | for {set i 0} {$i < 32} {incr i 1} { | |
157 | gdb_test "info reg vr$i" "vr$i.*$vector_register2_vr" "info reg vr$i (doubleword 1)" | |
158 | } | |
159 | ||
160 | # Test reading the core file. | |
161 | ||
604c2f83 LM |
162 | if {!$core_supported} { |
163 | return -1 | |
164 | } | |
165 | ||
166 | gdb_exit | |
167 | gdb_start | |
168 | gdb_reinitialize_dir $srcdir/$subdir | |
169 | gdb_load ${binfile} | |
170 | ||
171 | gdb_test_multiple "core ${objdir}/${subdir}/vsx-core.test" \ | |
172 | "re-load generated corefile" \ | |
173 | { | |
174 | -re ".* is not a core dump:.*$gdb_prompt $" { | |
175 | fail "re-load generated corefile (bad file format)" | |
176 | # No use proceeding from here. | |
177 | return; | |
178 | } | |
179 | -re ".*: No such file or directory.*$gdb_prompt $" { | |
180 | fail "re-load generated corefile (file not found)" | |
181 | # No use proceeding from here. | |
182 | return; | |
183 | } | |
184 | -re ".*Couldn't find .* registers in core file.*$gdb_prompt $" { | |
185 | fail "re-load generated corefile (incomplete note section)" | |
186 | } | |
187 | -re "Core was generated by .*$gdb_prompt $" { | |
188 | pass "re-load generated corefile" | |
189 | } | |
190 | -re ".*$gdb_prompt $" { | |
191 | fail "re-load generated corefile" | |
192 | } | |
193 | timeout { | |
194 | fail "re-load generated corefile (timeout)" | |
195 | } | |
196 | } | |
197 | ||
198 | for {set i 0} {$i < 32} {incr i 1} { | |
199 | gdb_test "info reg vs$i" "vs$i.*$vector_register2" "Restore vs$i from core file" | |
200 | } | |
201 | ||
202 | for {set i 32} {$i < 64} {incr i 1} { | |
203 | gdb_test "info reg vs$i" "vs$i.*$vector_register3" "Restore vs$i from core file" | |
204 | } |