]>
Commit | Line | Data |
---|---|---|
8cd64e00 YQ |
1 | /* Target dependent code for GDB on TI C6x systems. |
2 | ||
1d506c26 | 3 | Copyright (C) 2010-2024 Free Software Foundation, Inc. |
8cd64e00 YQ |
4 | Contributed by Andrew Jenner <andrew@codesourcery.com> |
5 | Contributed by Yao Qi <yao@codesourcery.com> | |
6 | ||
7 | This file is part of GDB. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
21 | ||
ec452525 | 22 | #include "extract-store-integer.h" |
8cd64e00 YQ |
23 | #include "frame.h" |
24 | #include "frame-unwind.h" | |
25 | #include "frame-base.h" | |
26 | #include "trad-frame.h" | |
82ca8957 | 27 | #include "dwarf2/frame.h" |
8cd64e00 YQ |
28 | #include "symtab.h" |
29 | #include "inferior.h" | |
30 | #include "gdbtypes.h" | |
31 | #include "gdbcore.h" | |
32 | #include "gdbcmd.h" | |
33 | #include "target.h" | |
34 | #include "dis-asm.h" | |
35 | #include "regcache.h" | |
36 | #include "value.h" | |
37 | #include "symfile.h" | |
38 | #include "arch-utils.h" | |
8cd64e00 YQ |
39 | #include "glibc-tdep.h" |
40 | #include "infcall.h" | |
41 | #include "regset.h" | |
42 | #include "tramp-frame.h" | |
43 | #include "linux-tdep.h" | |
44 | #include "solib.h" | |
45 | #include "objfiles.h" | |
8cd64e00 YQ |
46 | #include "osabi.h" |
47 | #include "tic6x-tdep.h" | |
48 | #include "language.h" | |
49 | #include "target-descriptions.h" | |
325fac50 | 50 | #include <algorithm> |
8cd64e00 | 51 | |
8cd64e00 YQ |
52 | #define TIC6X_OPCODE_SIZE 4 |
53 | #define TIC6X_FETCH_PACKET_SIZE 32 | |
54 | ||
55 | #define INST_S_BIT(INST) ((INST >> 1) & 1) | |
56 | #define INST_X_BIT(INST) ((INST >> 12) & 1) | |
57 | ||
85661b1e YQ |
58 | const gdb_byte tic6x_bkpt_illegal_opcode_be[] = { 0x56, 0x45, 0x43, 0x14 }; |
59 | const gdb_byte tic6x_bkpt_illegal_opcode_le[] = { 0x14, 0x43, 0x45, 0x56 }; | |
60 | ||
8cd64e00 YQ |
61 | struct tic6x_unwind_cache |
62 | { | |
63 | /* The frame's base, optionally used by the high-level debug info. */ | |
64 | CORE_ADDR base; | |
65 | ||
66 | /* The previous frame's inner most stack address. Used as this | |
67 | frame ID's stack_addr. */ | |
68 | CORE_ADDR cfa; | |
69 | ||
70 | /* The address of the first instruction in this function */ | |
71 | CORE_ADDR pc; | |
72 | ||
73 | /* Which register holds the return address for the frame. */ | |
74 | int return_regnum; | |
75 | ||
76 | /* The offset of register saved on stack. If register is not saved, the | |
77 | corresponding element is -1. */ | |
78 | CORE_ADDR reg_saved[TIC6X_NUM_CORE_REGS]; | |
79 | }; | |
80 | ||
81 | ||
82 | /* Name of TI C6x core registers. */ | |
83 | static const char *const tic6x_register_names[] = | |
84 | { | |
85 | "A0", "A1", "A2", "A3", /* 0 1 2 3 */ | |
86 | "A4", "A5", "A6", "A7", /* 4 5 6 7 */ | |
87 | "A8", "A9", "A10", "A11", /* 8 9 10 11 */ | |
88 | "A12", "A13", "A14", "A15", /* 12 13 14 15 */ | |
89 | "B0", "B1", "B2", "B3", /* 16 17 18 19 */ | |
90 | "B4", "B5", "B6", "B7", /* 20 21 22 23 */ | |
91 | "B8", "B9", "B10", "B11", /* 24 25 26 27 */ | |
92 | "B12", "B13", "B14", "B15", /* 28 29 30 31 */ | |
93 | "CSR", "PC", /* 32 33 */ | |
94 | }; | |
95 | ||
96 | /* This array maps the arguments to the register number which passes argument | |
97 | in function call according to C6000 ELF ABI. */ | |
98 | static const int arg_regs[] = { 4, 20, 6, 22, 8, 24, 10, 26, 12, 28 }; | |
99 | ||
100 | /* This is the implementation of gdbarch method register_name. */ | |
101 | ||
102 | static const char * | |
103 | tic6x_register_name (struct gdbarch *gdbarch, int regno) | |
104 | { | |
8cd64e00 YQ |
105 | if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
106 | return tdesc_register_name (gdbarch, regno); | |
107 | else if (regno >= ARRAY_SIZE (tic6x_register_names)) | |
108 | return ""; | |
109 | else | |
110 | return tic6x_register_names[regno]; | |
111 | } | |
112 | ||
113 | /* This is the implementation of gdbarch method register_type. */ | |
114 | ||
115 | static struct type * | |
116 | tic6x_register_type (struct gdbarch *gdbarch, int regno) | |
117 | { | |
118 | ||
119 | if (regno == TIC6X_PC_REGNUM) | |
120 | return builtin_type (gdbarch)->builtin_func_ptr; | |
121 | else | |
122 | return builtin_type (gdbarch)->builtin_uint32; | |
123 | } | |
124 | ||
125 | static void | |
126 | tic6x_setup_default (struct tic6x_unwind_cache *cache) | |
127 | { | |
128 | int i; | |
129 | ||
130 | for (i = 0; i < TIC6X_NUM_CORE_REGS; i++) | |
131 | cache->reg_saved[i] = -1; | |
132 | } | |
133 | ||
134 | static unsigned long tic6x_fetch_instruction (struct gdbarch *, CORE_ADDR); | |
135 | static int tic6x_register_number (int reg, int side, int crosspath); | |
136 | ||
137 | /* Do a full analysis of the prologue at START_PC and update CACHE accordingly. | |
138 | Bail out early if CURRENT_PC is reached. Returns the address of the first | |
139 | instruction after the prologue. */ | |
140 | ||
693be288 | 141 | static CORE_ADDR |
8cd64e00 YQ |
142 | tic6x_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc, |
143 | const CORE_ADDR current_pc, | |
144 | struct tic6x_unwind_cache *cache, | |
8480a37e | 145 | const frame_info_ptr &this_frame) |
8cd64e00 | 146 | { |
8cd64e00 YQ |
147 | unsigned int src_reg, base_reg, dst_reg; |
148 | int i; | |
149 | CORE_ADDR pc = start_pc; | |
150 | CORE_ADDR return_pc = start_pc; | |
151 | int frame_base_offset_to_sp = 0; | |
152 | /* Counter of non-stw instructions after first insn ` sub sp, xxx, sp'. */ | |
153 | int non_stw_insn_counter = 0; | |
154 | ||
155 | if (start_pc >= current_pc) | |
156 | return_pc = current_pc; | |
157 | ||
158 | cache->base = 0; | |
159 | ||
160 | /* The landmarks in prologue is one or two SUB instructions to SP. | |
161 | Instructions on setting up dsbt are in the last part of prologue, if | |
162 | needed. In maxim, prologue can be divided to three parts by two | |
163 | `sub sp, xx, sp' insns. */ | |
164 | ||
165 | /* Step 1: Look for the 1st and 2nd insn `sub sp, xx, sp', in which, the | |
166 | 2nd one is optional. */ | |
167 | while (pc < current_pc) | |
168 | { | |
8cd64e00 YQ |
169 | unsigned long inst = tic6x_fetch_instruction (gdbarch, pc); |
170 | ||
171 | if ((inst & 0x1ffc) == 0x1dc0 || (inst & 0x1ffc) == 0x1bc0 | |
172 | || (inst & 0x0ffc) == 0x9c0) | |
173 | { | |
174 | /* SUBAW/SUBAH/SUB, and src1 is ucst 5. */ | |
175 | unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f, | |
176 | INST_S_BIT (inst), 0); | |
177 | unsigned int dst = tic6x_register_number ((inst >> 23) & 0x1f, | |
178 | INST_S_BIT (inst), 0); | |
179 | ||
180 | if (src2 == TIC6X_SP_REGNUM && dst == TIC6X_SP_REGNUM) | |
181 | { | |
182 | /* Extract const from insn SUBAW/SUBAH/SUB, and translate it to | |
183 | offset. The constant offset is decoded in bit 13-17 in all | |
184 | these three kinds of instructions. */ | |
185 | unsigned int ucst5 = (inst >> 13) & 0x1f; | |
186 | ||
187 | if ((inst & 0x1ffc) == 0x1dc0) /* SUBAW */ | |
188 | frame_base_offset_to_sp += ucst5 << 2; | |
189 | else if ((inst & 0x1ffc) == 0x1bc0) /* SUBAH */ | |
190 | frame_base_offset_to_sp += ucst5 << 1; | |
191 | else if ((inst & 0x0ffc) == 0x9c0) /* SUB */ | |
192 | frame_base_offset_to_sp += ucst5; | |
193 | else | |
194 | gdb_assert_not_reached ("unexpected instruction"); | |
195 | ||
196 | return_pc = pc + 4; | |
197 | } | |
198 | } | |
199 | else if ((inst & 0x174) == 0x74) /* stw SRC, *+b15(uconst) */ | |
200 | { | |
201 | /* The y bit determines which file base is read from. */ | |
202 | base_reg = tic6x_register_number ((inst >> 18) & 0x1f, | |
203 | (inst >> 7) & 1, 0); | |
204 | ||
205 | if (base_reg == TIC6X_SP_REGNUM) | |
206 | { | |
207 | src_reg = tic6x_register_number ((inst >> 23) & 0x1f, | |
208 | INST_S_BIT (inst), 0); | |
209 | ||
210 | cache->reg_saved[src_reg] = ((inst >> 13) & 0x1f) << 2; | |
211 | ||
212 | return_pc = pc + 4; | |
213 | } | |
214 | non_stw_insn_counter = 0; | |
215 | } | |
216 | else | |
217 | { | |
218 | non_stw_insn_counter++; | |
219 | /* Following instruction sequence may be emitted in prologue: | |
220 | ||
221 | <+0>: subah .D2 b15,28,b15 | |
222 | <+4>: or .L2X 0,a4,b0 | |
223 | <+8>: || stw .D2T2 b14,*+b15(56) | |
224 | <+12>:[!b0] b .S1 0xe50e4c1c <sleep+220> | |
225 | <+16>:|| stw .D2T1 a10,*+b15(48) | |
226 | <+20>:stw .D2T2 b3,*+b15(52) | |
227 | <+24>:stw .D2T1 a4,*+b15(40) | |
228 | ||
229 | we should look forward for next instruction instead of breaking loop | |
230 | here. So far, we allow almost two sequential non-stw instructions | |
231 | in prologue. */ | |
232 | if (non_stw_insn_counter >= 2) | |
233 | break; | |
234 | } | |
235 | ||
236 | ||
237 | pc += 4; | |
238 | } | |
239 | /* Step 2: Skip insn on setting up dsbt if it is. Usually, it looks like, | |
240 | ldw .D2T2 *+b14(0),b14 */ | |
b926417a | 241 | unsigned long inst = tic6x_fetch_instruction (gdbarch, pc); |
8cd64e00 YQ |
242 | /* The s bit determines which file dst will be loaded into, same effect as |
243 | other places. */ | |
244 | dst_reg = tic6x_register_number ((inst >> 23) & 0x1f, (inst >> 1) & 1, 0); | |
245 | /* The y bit (bit 7), instead of s bit, determines which file base be | |
246 | used. */ | |
247 | base_reg = tic6x_register_number ((inst >> 18) & 0x1f, (inst >> 7) & 1, 0); | |
248 | ||
249 | if ((inst & 0x164) == 0x64 /* ldw */ | |
250 | && dst_reg == TIC6X_DP_REGNUM /* dst is B14 */ | |
251 | && base_reg == TIC6X_DP_REGNUM) /* baseR is B14 */ | |
252 | { | |
253 | return_pc = pc + 4; | |
254 | } | |
255 | ||
256 | if (this_frame) | |
257 | { | |
258 | cache->base = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM); | |
259 | ||
260 | if (cache->reg_saved[TIC6X_FP_REGNUM] != -1) | |
261 | { | |
262 | /* If the FP now holds an offset from the CFA then this is a frame | |
263 | which uses the frame pointer. */ | |
264 | ||
265 | cache->cfa = get_frame_register_unsigned (this_frame, | |
266 | TIC6X_FP_REGNUM); | |
267 | } | |
268 | else | |
269 | { | |
270 | /* FP doesn't hold an offset from the CFA. If SP still holds an | |
271 | offset from the CFA then we might be in a function which omits | |
272 | the frame pointer. */ | |
273 | ||
274 | cache->cfa = cache->base + frame_base_offset_to_sp; | |
275 | } | |
276 | } | |
277 | ||
278 | /* Adjust all the saved registers such that they contain addresses | |
279 | instead of offsets. */ | |
280 | for (i = 0; i < TIC6X_NUM_CORE_REGS; i++) | |
281 | if (cache->reg_saved[i] != -1) | |
282 | cache->reg_saved[i] = cache->base + cache->reg_saved[i]; | |
283 | ||
284 | return return_pc; | |
285 | } | |
286 | ||
287 | /* This is the implementation of gdbarch method skip_prologue. */ | |
288 | ||
693be288 | 289 | static CORE_ADDR |
8cd64e00 YQ |
290 | tic6x_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
291 | { | |
8cd64e00 YQ |
292 | CORE_ADDR func_addr; |
293 | struct tic6x_unwind_cache cache; | |
294 | ||
295 | /* See if we can determine the end of the prologue via the symbol table. | |
296 | If so, then return either PC, or the PC after the prologue, whichever is | |
297 | greater. */ | |
298 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) | |
299 | { | |
300 | CORE_ADDR post_prologue_pc | |
301 | = skip_prologue_using_sal (gdbarch, func_addr); | |
302 | if (post_prologue_pc != 0) | |
325fac50 | 303 | return std::max (start_pc, post_prologue_pc); |
8cd64e00 YQ |
304 | } |
305 | ||
306 | /* Can't determine prologue from the symbol table, need to examine | |
307 | instructions. */ | |
308 | return tic6x_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, | |
309 | NULL); | |
310 | } | |
311 | ||
cd6c3b4f YQ |
312 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
313 | ||
d19280ad YQ |
314 | static int |
315 | tic6x_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
316 | { | |
317 | return 4; | |
318 | } | |
8cd64e00 | 319 | |
cd6c3b4f YQ |
320 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
321 | ||
948f8e3d | 322 | static const gdb_byte * |
d19280ad | 323 | tic6x_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) |
8cd64e00 | 324 | { |
08106042 | 325 | tic6x_gdbarch_tdep *tdep = gdbarch_tdep<tic6x_gdbarch_tdep> (gdbarch); |
8cd64e00 | 326 | |
d19280ad | 327 | *size = kind; |
8cd64e00 YQ |
328 | |
329 | if (tdep == NULL || tdep->breakpoint == NULL) | |
330 | { | |
331 | if (BFD_ENDIAN_BIG == gdbarch_byte_order_for_code (gdbarch)) | |
332 | return tic6x_bkpt_illegal_opcode_be; | |
333 | else | |
334 | return tic6x_bkpt_illegal_opcode_le; | |
335 | } | |
336 | else | |
337 | return tdep->breakpoint; | |
338 | } | |
339 | ||
8cd64e00 YQ |
340 | static void |
341 | tic6x_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
342 | struct dwarf2_frame_state_reg *reg, | |
8480a37e | 343 | const frame_info_ptr &this_frame) |
8cd64e00 YQ |
344 | { |
345 | /* Mark the PC as the destination for the return address. */ | |
346 | if (regnum == gdbarch_pc_regnum (gdbarch)) | |
347 | reg->how = DWARF2_FRAME_REG_RA; | |
348 | ||
349 | /* Mark the stack pointer as the call frame address. */ | |
350 | else if (regnum == gdbarch_sp_regnum (gdbarch)) | |
351 | reg->how = DWARF2_FRAME_REG_CFA; | |
352 | ||
353 | /* The above was taken from the default init_reg in dwarf2-frame.c | |
354 | while the below is c6x specific. */ | |
355 | ||
356 | /* Callee save registers. The ABI designates A10-A15 and B10-B15 as | |
357 | callee-save. */ | |
358 | else if ((regnum >= 10 && regnum <= 15) || (regnum >= 26 && regnum <= 31)) | |
359 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
360 | else | |
361 | /* All other registers are caller-save. */ | |
362 | reg->how = DWARF2_FRAME_REG_UNDEFINED; | |
363 | } | |
364 | ||
365 | /* This is the implementation of gdbarch method unwind_pc. */ | |
366 | ||
367 | static CORE_ADDR | |
8480a37e | 368 | tic6x_unwind_pc (struct gdbarch *gdbarch, const frame_info_ptr &next_frame) |
8cd64e00 YQ |
369 | { |
370 | gdb_byte buf[8]; | |
371 | ||
372 | frame_unwind_register (next_frame, TIC6X_PC_REGNUM, buf); | |
373 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); | |
374 | } | |
375 | ||
8cd64e00 YQ |
376 | /* Frame base handling. */ |
377 | ||
693be288 | 378 | static struct tic6x_unwind_cache* |
8480a37e | 379 | tic6x_frame_unwind_cache (const frame_info_ptr &this_frame, |
8cd64e00 YQ |
380 | void **this_prologue_cache) |
381 | { | |
382 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
383 | CORE_ADDR current_pc; | |
384 | struct tic6x_unwind_cache *cache; | |
8cd64e00 YQ |
385 | |
386 | if (*this_prologue_cache) | |
19ba03f4 | 387 | return (struct tic6x_unwind_cache *) *this_prologue_cache; |
8cd64e00 YQ |
388 | |
389 | cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache); | |
390 | (*this_prologue_cache) = cache; | |
391 | ||
392 | cache->return_regnum = TIC6X_RA_REGNUM; | |
393 | ||
394 | tic6x_setup_default (cache); | |
395 | ||
396 | cache->pc = get_frame_func (this_frame); | |
397 | current_pc = get_frame_pc (this_frame); | |
398 | ||
399 | /* Prologue analysis does the rest... */ | |
400 | if (cache->pc != 0) | |
401 | tic6x_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame); | |
402 | ||
403 | return cache; | |
404 | } | |
405 | ||
406 | static void | |
8480a37e | 407 | tic6x_frame_this_id (const frame_info_ptr &this_frame, void **this_cache, |
8cd64e00 YQ |
408 | struct frame_id *this_id) |
409 | { | |
410 | struct tic6x_unwind_cache *cache = | |
411 | tic6x_frame_unwind_cache (this_frame, this_cache); | |
412 | ||
413 | /* This marks the outermost frame. */ | |
414 | if (cache->base == 0) | |
415 | return; | |
416 | ||
417 | (*this_id) = frame_id_build (cache->cfa, cache->pc); | |
418 | } | |
419 | ||
420 | static struct value * | |
8480a37e | 421 | tic6x_frame_prev_register (const frame_info_ptr &this_frame, void **this_cache, |
8cd64e00 YQ |
422 | int regnum) |
423 | { | |
424 | struct tic6x_unwind_cache *cache = | |
425 | tic6x_frame_unwind_cache (this_frame, this_cache); | |
426 | ||
427 | gdb_assert (regnum >= 0); | |
428 | ||
429 | /* The PC of the previous frame is stored in the RA register of | |
430 | the current frame. Frob regnum so that we pull the value from | |
431 | the correct place. */ | |
432 | if (regnum == TIC6X_PC_REGNUM) | |
433 | regnum = cache->return_regnum; | |
434 | ||
435 | if (regnum == TIC6X_SP_REGNUM && cache->cfa) | |
436 | return frame_unwind_got_constant (this_frame, regnum, cache->cfa); | |
437 | ||
438 | /* If we've worked out where a register is stored then load it from | |
439 | there. */ | |
440 | if (regnum < TIC6X_NUM_CORE_REGS && cache->reg_saved[regnum] != -1) | |
441 | return frame_unwind_got_memory (this_frame, regnum, | |
442 | cache->reg_saved[regnum]); | |
443 | ||
444 | return frame_unwind_got_register (this_frame, regnum, regnum); | |
445 | } | |
446 | ||
447 | static CORE_ADDR | |
8480a37e | 448 | tic6x_frame_base_address (const frame_info_ptr &this_frame, void **this_cache) |
8cd64e00 YQ |
449 | { |
450 | struct tic6x_unwind_cache *info | |
451 | = tic6x_frame_unwind_cache (this_frame, this_cache); | |
452 | return info->base; | |
453 | } | |
454 | ||
455 | static const struct frame_unwind tic6x_frame_unwind = | |
456 | { | |
a154d838 | 457 | "tic6x prologue", |
8cd64e00 YQ |
458 | NORMAL_FRAME, |
459 | default_frame_unwind_stop_reason, | |
460 | tic6x_frame_this_id, | |
461 | tic6x_frame_prev_register, | |
462 | NULL, | |
463 | default_frame_sniffer | |
464 | }; | |
465 | ||
466 | static const struct frame_base tic6x_frame_base = | |
467 | { | |
468 | &tic6x_frame_unwind, | |
469 | tic6x_frame_base_address, | |
470 | tic6x_frame_base_address, | |
471 | tic6x_frame_base_address | |
472 | }; | |
473 | ||
474 | ||
475 | static struct tic6x_unwind_cache * | |
8480a37e | 476 | tic6x_make_stub_cache (const frame_info_ptr &this_frame) |
8cd64e00 YQ |
477 | { |
478 | struct tic6x_unwind_cache *cache; | |
479 | ||
480 | cache = FRAME_OBSTACK_ZALLOC (struct tic6x_unwind_cache); | |
481 | ||
482 | cache->return_regnum = TIC6X_RA_REGNUM; | |
483 | ||
484 | tic6x_setup_default (cache); | |
485 | ||
486 | cache->cfa = get_frame_register_unsigned (this_frame, TIC6X_SP_REGNUM); | |
487 | ||
488 | return cache; | |
489 | } | |
490 | ||
491 | static void | |
8480a37e | 492 | tic6x_stub_this_id (const frame_info_ptr &this_frame, void **this_cache, |
8cd64e00 YQ |
493 | struct frame_id *this_id) |
494 | { | |
495 | struct tic6x_unwind_cache *cache; | |
496 | ||
497 | if (*this_cache == NULL) | |
498 | *this_cache = tic6x_make_stub_cache (this_frame); | |
19ba03f4 | 499 | cache = (struct tic6x_unwind_cache *) *this_cache; |
8cd64e00 YQ |
500 | |
501 | *this_id = frame_id_build (cache->cfa, get_frame_pc (this_frame)); | |
502 | } | |
503 | ||
504 | static int | |
505 | tic6x_stub_unwind_sniffer (const struct frame_unwind *self, | |
8480a37e | 506 | const frame_info_ptr &this_frame, |
8cd64e00 YQ |
507 | void **this_prologue_cache) |
508 | { | |
509 | CORE_ADDR addr_in_block; | |
510 | ||
511 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 512 | if (in_plt_section (addr_in_block)) |
8cd64e00 YQ |
513 | return 1; |
514 | ||
515 | return 0; | |
516 | } | |
517 | ||
518 | static const struct frame_unwind tic6x_stub_unwind = | |
519 | { | |
a154d838 | 520 | "tic6x stub", |
8cd64e00 YQ |
521 | NORMAL_FRAME, |
522 | default_frame_unwind_stop_reason, | |
523 | tic6x_stub_this_id, | |
524 | tic6x_frame_prev_register, | |
525 | NULL, | |
526 | tic6x_stub_unwind_sniffer | |
527 | }; | |
528 | ||
529 | /* Return the instruction on address PC. */ | |
530 | ||
531 | static unsigned long | |
532 | tic6x_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR pc) | |
533 | { | |
534 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
535 | return read_memory_unsigned_integer (pc, TIC6X_OPCODE_SIZE, byte_order); | |
536 | } | |
537 | ||
538 | /* Compute the condition of INST if it is a conditional instruction. Always | |
539 | return 1 if INST is not a conditional instruction. */ | |
540 | ||
541 | static int | |
fb090cfa | 542 | tic6x_condition_true (struct regcache *regcache, unsigned long inst) |
8cd64e00 YQ |
543 | { |
544 | int register_number; | |
545 | int register_value; | |
546 | static const int register_numbers[8] = { -1, 16, 17, 18, 1, 2, 0, -1 }; | |
547 | ||
548 | register_number = register_numbers[(inst >> 29) & 7]; | |
549 | if (register_number == -1) | |
550 | return 1; | |
551 | ||
fb090cfa | 552 | register_value = regcache_raw_get_signed (regcache, register_number); |
8cd64e00 YQ |
553 | if ((inst & 0x10000000) != 0) |
554 | return register_value == 0; | |
555 | return register_value != 0; | |
556 | } | |
557 | ||
558 | /* Get the register number by decoding raw bits REG, SIDE, and CROSSPATH in | |
559 | instruction. */ | |
560 | ||
561 | static int | |
562 | tic6x_register_number (int reg, int side, int crosspath) | |
563 | { | |
564 | int r = (reg & 15) | ((crosspath ^ side) << 4); | |
565 | if ((reg & 16) != 0) /* A16 - A31, B16 - B31 */ | |
566 | r += 37; | |
567 | return r; | |
568 | } | |
569 | ||
570 | static int | |
571 | tic6x_extract_signed_field (int value, int low_bit, int bits) | |
572 | { | |
573 | int mask = (1 << bits) - 1; | |
574 | int r = (value >> low_bit) & mask; | |
575 | if ((r & (1 << (bits - 1))) != 0) | |
576 | r -= mask + 1; | |
577 | return r; | |
578 | } | |
579 | ||
580 | /* Determine where to set a single step breakpoint. */ | |
581 | ||
582 | static CORE_ADDR | |
fb090cfa | 583 | tic6x_get_next_pc (struct regcache *regcache, CORE_ADDR pc) |
8cd64e00 | 584 | { |
ac7936df | 585 | struct gdbarch *gdbarch = regcache->arch (); |
8cd64e00 | 586 | unsigned long inst; |
8cd64e00 YQ |
587 | int register_number; |
588 | int last = 0; | |
589 | ||
590 | do | |
591 | { | |
592 | inst = tic6x_fetch_instruction (gdbarch, pc); | |
593 | ||
594 | last = !(inst & 1); | |
595 | ||
596 | if (inst == TIC6X_INST_SWE) | |
597 | { | |
345bd07c | 598 | tic6x_gdbarch_tdep *tdep |
08106042 | 599 | = gdbarch_tdep<tic6x_gdbarch_tdep> (gdbarch); |
8cd64e00 YQ |
600 | |
601 | if (tdep->syscall_next_pc != NULL) | |
fb090cfa | 602 | return tdep->syscall_next_pc (get_current_frame ()); |
8cd64e00 YQ |
603 | } |
604 | ||
fb090cfa | 605 | if (tic6x_condition_true (regcache, inst)) |
8cd64e00 YQ |
606 | { |
607 | if ((inst & 0x0000007c) == 0x00000010) | |
608 | { | |
609 | /* B with displacement */ | |
610 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
611 | pc += tic6x_extract_signed_field (inst, 7, 21) << 2; | |
612 | break; | |
613 | } | |
614 | if ((inst & 0x0f83effc) == 0x00000360) | |
615 | { | |
616 | /* B with register */ | |
617 | ||
618 | register_number = tic6x_register_number ((inst >> 18) & 0x1f, | |
619 | INST_S_BIT (inst), | |
620 | INST_X_BIT (inst)); | |
fb090cfa | 621 | pc = regcache_raw_get_unsigned (regcache, register_number); |
8cd64e00 YQ |
622 | break; |
623 | } | |
624 | if ((inst & 0x00001ffc) == 0x00001020) | |
625 | { | |
626 | /* BDEC */ | |
627 | register_number = tic6x_register_number ((inst >> 23) & 0x1f, | |
628 | INST_S_BIT (inst), 0); | |
fb090cfa | 629 | if (regcache_raw_get_signed (regcache, register_number) >= 0) |
8cd64e00 YQ |
630 | { |
631 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
632 | pc += tic6x_extract_signed_field (inst, 7, 10) << 2; | |
633 | } | |
634 | break; | |
635 | } | |
636 | if ((inst & 0x00001ffc) == 0x00000120) | |
637 | { | |
638 | /* BNOP with displacement */ | |
639 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
640 | pc += tic6x_extract_signed_field (inst, 16, 12) << 2; | |
641 | break; | |
642 | } | |
643 | if ((inst & 0x0f830ffe) == 0x00800362) | |
644 | { | |
645 | /* BNOP with register */ | |
646 | register_number = tic6x_register_number ((inst >> 18) & 0x1f, | |
647 | 1, INST_X_BIT (inst)); | |
fb090cfa | 648 | pc = regcache_raw_get_unsigned (regcache, register_number); |
8cd64e00 YQ |
649 | break; |
650 | } | |
651 | if ((inst & 0x00001ffc) == 0x00000020) | |
652 | { | |
653 | /* BPOS */ | |
654 | register_number = tic6x_register_number ((inst >> 23) & 0x1f, | |
655 | INST_S_BIT (inst), 0); | |
fb090cfa | 656 | if (regcache_raw_get_signed (regcache, register_number) >= 0) |
8cd64e00 YQ |
657 | { |
658 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
659 | pc += tic6x_extract_signed_field (inst, 13, 10) << 2; | |
660 | } | |
661 | break; | |
662 | } | |
663 | if ((inst & 0xf000007c) == 0x10000010) | |
664 | { | |
665 | /* CALLP */ | |
666 | pc &= ~(TIC6X_FETCH_PACKET_SIZE - 1); | |
667 | pc += tic6x_extract_signed_field (inst, 7, 21) << 2; | |
668 | break; | |
669 | } | |
670 | } | |
671 | pc += TIC6X_OPCODE_SIZE; | |
672 | } | |
673 | while (!last); | |
674 | return pc; | |
675 | } | |
676 | ||
677 | /* This is the implementation of gdbarch method software_single_step. */ | |
678 | ||
a0ff9e1a | 679 | static std::vector<CORE_ADDR> |
f5ea389a | 680 | tic6x_software_single_step (struct regcache *regcache) |
8cd64e00 | 681 | { |
fb090cfa | 682 | CORE_ADDR next_pc = tic6x_get_next_pc (regcache, regcache_read_pc (regcache)); |
8cd64e00 | 683 | |
a0ff9e1a | 684 | return {next_pc}; |
8cd64e00 YQ |
685 | } |
686 | ||
687 | /* This is the implementation of gdbarch method frame_align. */ | |
688 | ||
689 | static CORE_ADDR | |
690 | tic6x_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | |
691 | { | |
692 | return align_down (addr, 8); | |
693 | } | |
694 | ||
8cd64e00 YQ |
695 | /* Given a return value in REGCACHE with a type VALTYPE, extract and copy its |
696 | value into VALBUF. */ | |
697 | ||
698 | static void | |
699 | tic6x_extract_return_value (struct type *valtype, struct regcache *regcache, | |
700 | enum bfd_endian byte_order, gdb_byte *valbuf) | |
701 | { | |
df86565b | 702 | int len = valtype->length (); |
8cd64e00 YQ |
703 | |
704 | /* pointer types are returned in register A4, | |
705 | up to 32-bit types in A4 | |
706 | up to 64-bit types in A5:A4 */ | |
707 | if (len <= 4) | |
708 | { | |
709 | /* In big-endian, | |
710 | - one-byte structure or union occupies the LSB of single even register. | |
711 | - for two-byte structure or union, the first byte occupies byte 1 of | |
712 | register and the second byte occupies byte 0. | |
713 | so, we read the contents in VAL from the LSBs of register. */ | |
714 | if (len < 3 && byte_order == BFD_ENDIAN_BIG) | |
73bb0000 | 715 | regcache->cooked_read_part (TIC6X_A4_REGNUM, 4 - len, len, valbuf); |
8cd64e00 | 716 | else |
dca08e1f | 717 | regcache->cooked_read (TIC6X_A4_REGNUM, valbuf); |
8cd64e00 YQ |
718 | } |
719 | else if (len <= 8) | |
720 | { | |
721 | /* For a 5-8 byte structure or union in big-endian, the first byte | |
722 | occupies byte 3 (the MSB) of the upper (odd) register and the | |
723 | remaining bytes fill the decreasingly significant bytes. 5-7 | |
724 | byte structures or unions have padding in the LSBs of the | |
725 | lower (even) register. */ | |
726 | if (byte_order == BFD_ENDIAN_BIG) | |
727 | { | |
dca08e1f SM |
728 | regcache->cooked_read (TIC6X_A4_REGNUM, valbuf + 4); |
729 | regcache->cooked_read (TIC6X_A5_REGNUM, valbuf); | |
8cd64e00 YQ |
730 | } |
731 | else | |
732 | { | |
dca08e1f SM |
733 | regcache->cooked_read (TIC6X_A4_REGNUM, valbuf); |
734 | regcache->cooked_read (TIC6X_A5_REGNUM, valbuf + 4); | |
8cd64e00 YQ |
735 | } |
736 | } | |
737 | } | |
738 | ||
739 | /* Write into appropriate registers a function return value | |
740 | of type TYPE, given in virtual format. */ | |
741 | ||
742 | static void | |
743 | tic6x_store_return_value (struct type *valtype, struct regcache *regcache, | |
744 | enum bfd_endian byte_order, const gdb_byte *valbuf) | |
745 | { | |
df86565b | 746 | int len = valtype->length (); |
8cd64e00 YQ |
747 | |
748 | /* return values of up to 8 bytes are returned in A5:A4 */ | |
749 | ||
750 | if (len <= 4) | |
751 | { | |
752 | if (len < 3 && byte_order == BFD_ENDIAN_BIG) | |
e4c4a59b | 753 | regcache->cooked_write_part (TIC6X_A4_REGNUM, 4 - len, len, valbuf); |
8cd64e00 | 754 | else |
b66f5587 | 755 | regcache->cooked_write (TIC6X_A4_REGNUM, valbuf); |
8cd64e00 YQ |
756 | } |
757 | else if (len <= 8) | |
758 | { | |
759 | if (byte_order == BFD_ENDIAN_BIG) | |
760 | { | |
b66f5587 SM |
761 | regcache->cooked_write (TIC6X_A4_REGNUM, valbuf + 4); |
762 | regcache->cooked_write (TIC6X_A5_REGNUM, valbuf); | |
8cd64e00 YQ |
763 | } |
764 | else | |
765 | { | |
b66f5587 SM |
766 | regcache->cooked_write (TIC6X_A4_REGNUM, valbuf); |
767 | regcache->cooked_write (TIC6X_A5_REGNUM, valbuf + 4); | |
8cd64e00 YQ |
768 | } |
769 | } | |
770 | } | |
771 | ||
772 | /* This is the implementation of gdbarch method return_value. */ | |
773 | ||
774 | static enum return_value_convention | |
6a3a010b | 775 | tic6x_return_value (struct gdbarch *gdbarch, struct value *function, |
8cd64e00 YQ |
776 | struct type *type, struct regcache *regcache, |
777 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
778 | { | |
18648a37 YQ |
779 | /* In C++, when function returns an object, even its size is small |
780 | enough, it stii has to be passed via reference, pointed by register | |
781 | A3. */ | |
782 | if (current_language->la_language == language_cplus) | |
783 | { | |
784 | if (type != NULL) | |
785 | { | |
f168693b | 786 | type = check_typedef (type); |
9d084466 | 787 | if (!(language_pass_by_reference (type).trivially_copyable)) |
18648a37 YQ |
788 | return RETURN_VALUE_STRUCT_CONVENTION; |
789 | } | |
790 | } | |
791 | ||
df86565b | 792 | if (type->length () > 8) |
8cd64e00 YQ |
793 | return RETURN_VALUE_STRUCT_CONVENTION; |
794 | ||
795 | if (readbuf) | |
796 | tic6x_extract_return_value (type, regcache, | |
797 | gdbarch_byte_order (gdbarch), readbuf); | |
798 | if (writebuf) | |
799 | tic6x_store_return_value (type, regcache, | |
800 | gdbarch_byte_order (gdbarch), writebuf); | |
801 | ||
802 | return RETURN_VALUE_REGISTER_CONVENTION; | |
803 | } | |
804 | ||
8cd64e00 YQ |
805 | /* Get the alignment requirement of TYPE. */ |
806 | ||
807 | static int | |
808 | tic6x_arg_type_alignment (struct type *type) | |
809 | { | |
df86565b | 810 | int len = check_typedef (type)->length (); |
78134374 | 811 | enum type_code typecode = check_typedef (type)->code (); |
8cd64e00 YQ |
812 | |
813 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
814 | { | |
815 | /* The stack alignment of a structure (and union) passed by value is the | |
816 | smallest power of two greater than or equal to its size. | |
817 | This cannot exceed 8 bytes, which is the largest allowable size for | |
818 | a structure passed by value. */ | |
819 | ||
820 | if (len <= 2) | |
821 | return len; | |
822 | else if (len <= 4) | |
823 | return 4; | |
824 | else if (len <= 8) | |
825 | return 8; | |
826 | else | |
827 | gdb_assert_not_reached ("unexpected length of data"); | |
828 | } | |
829 | else | |
830 | { | |
831 | if (len <= 4) | |
832 | return 4; | |
833 | else if (len == 8) | |
834 | { | |
835 | if (typecode == TYPE_CODE_COMPLEX) | |
836 | return 4; | |
837 | else | |
838 | return 8; | |
839 | } | |
840 | else if (len == 16) | |
841 | { | |
842 | if (typecode == TYPE_CODE_COMPLEX) | |
843 | return 8; | |
844 | else | |
845 | return 16; | |
846 | } | |
847 | else | |
f34652de | 848 | internal_error (_("unexpected length %d of type"), |
8cd64e00 YQ |
849 | len); |
850 | } | |
851 | } | |
852 | ||
853 | /* This is the implementation of gdbarch method push_dummy_call. */ | |
854 | ||
855 | static CORE_ADDR | |
856 | tic6x_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
857 | struct regcache *regcache, CORE_ADDR bp_addr, | |
858 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
859 | function_call_return_method return_method, |
860 | CORE_ADDR struct_addr) | |
8cd64e00 YQ |
861 | { |
862 | int argreg = 0; | |
863 | int argnum; | |
8cd64e00 YQ |
864 | int stack_offset = 4; |
865 | int references_offset = 4; | |
8cd64e00 | 866 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
d0c97917 | 867 | struct type *func_type = function->type (); |
8cd64e00 YQ |
868 | /* The first arg passed on stack. Mostly the first 10 args are passed by |
869 | registers. */ | |
870 | int first_arg_on_stack = 10; | |
8cd64e00 | 871 | |
8cd64e00 YQ |
872 | /* Set the return address register to point to the entry point of |
873 | the program, where a breakpoint lies in wait. */ | |
874 | regcache_cooked_write_unsigned (regcache, TIC6X_RA_REGNUM, bp_addr); | |
875 | ||
876 | /* The caller must pass an argument in A3 containing a destination address | |
877 | for the returned value. The callee returns the object by copying it to | |
878 | the address in A3. */ | |
cf84fa6b | 879 | if (return_method == return_method_struct) |
8cd64e00 | 880 | regcache_cooked_write_unsigned (regcache, 3, struct_addr); |
8cd64e00 YQ |
881 | |
882 | /* Determine the type of this function. */ | |
883 | func_type = check_typedef (func_type); | |
78134374 | 884 | if (func_type->code () == TYPE_CODE_PTR) |
27710edb | 885 | func_type = check_typedef (func_type->target_type ()); |
8cd64e00 | 886 | |
78134374 SM |
887 | gdb_assert (func_type->code () == TYPE_CODE_FUNC |
888 | || func_type->code () == TYPE_CODE_METHOD); | |
8cd64e00 YQ |
889 | |
890 | /* For a variadic C function, the last explicitly declared argument and all | |
891 | remaining arguments are passed on the stack. */ | |
a409645d | 892 | if (func_type->has_varargs ()) |
1f704f76 | 893 | first_arg_on_stack = func_type->num_fields () - 1; |
8cd64e00 | 894 | |
18648a37 YQ |
895 | /* Now make space on the stack for the args. */ |
896 | for (argnum = 0; argnum < nargs; argnum++) | |
8cd64e00 | 897 | { |
d0c97917 | 898 | int len = align_up (args[argnum]->type ()->length (), 4); |
8cd64e00 YQ |
899 | if (argnum >= 10 - argreg) |
900 | references_offset += len; | |
901 | stack_offset += len; | |
902 | } | |
903 | sp -= stack_offset; | |
904 | /* SP should be 8-byte aligned, see C6000 ABI section 4.4.1 | |
905 | Stack Alignment. */ | |
906 | sp = align_down (sp, 8); | |
907 | stack_offset = 4; | |
908 | ||
909 | /* Now load as many as possible of the first arguments into | |
910 | registers, and push the rest onto the stack. Loop through args | |
911 | from first to last. */ | |
18648a37 | 912 | for (argnum = 0; argnum < nargs; argnum++) |
8cd64e00 YQ |
913 | { |
914 | const gdb_byte *val; | |
915 | struct value *arg = args[argnum]; | |
d0c97917 | 916 | struct type *arg_type = check_typedef (arg->type ()); |
df86565b | 917 | int len = arg_type->length (); |
78134374 | 918 | enum type_code typecode = arg_type->code (); |
8cd64e00 | 919 | |
efaf1ae0 | 920 | val = arg->contents ().data (); |
8cd64e00 YQ |
921 | |
922 | /* Copy the argument to general registers or the stack in | |
dda83cd7 | 923 | register-sized pieces. */ |
8cd64e00 YQ |
924 | if (argreg < first_arg_on_stack) |
925 | { | |
926 | if (len <= 4) | |
927 | { | |
928 | if (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) | |
929 | { | |
930 | /* In big-endian, | |
931 | - one-byte structure or union occupies the LSB of single | |
932 | even register. | |
933 | - for two-byte structure or union, the first byte | |
934 | occupies byte 1 of register and the second byte occupies | |
935 | byte 0. | |
936 | so, we write the contents in VAL to the lsp of | |
937 | register. */ | |
938 | if (len < 3 && byte_order == BFD_ENDIAN_BIG) | |
e4c4a59b SM |
939 | regcache->cooked_write_part (arg_regs[argreg], 4 - len, len, |
940 | val); | |
8cd64e00 | 941 | else |
b66f5587 | 942 | regcache->cooked_write (arg_regs[argreg], val); |
8cd64e00 YQ |
943 | } |
944 | else | |
945 | { | |
946 | /* The argument is being passed by value in a single | |
947 | register. */ | |
948 | CORE_ADDR regval = extract_unsigned_integer (val, len, | |
949 | byte_order); | |
950 | ||
951 | regcache_cooked_write_unsigned (regcache, arg_regs[argreg], | |
952 | regval); | |
953 | } | |
954 | } | |
955 | else | |
956 | { | |
957 | if (len <= 8) | |
958 | { | |
959 | if (typecode == TYPE_CODE_STRUCT | |
960 | || typecode == TYPE_CODE_UNION) | |
961 | { | |
962 | /* For a 5-8 byte structure or union in big-endian, the | |
dda83cd7 SM |
963 | first byte occupies byte 3 (the MSB) of the upper (odd) |
964 | register and the remaining bytes fill the decreasingly | |
965 | significant bytes. 5-7 byte structures or unions have | |
966 | padding in the LSBs of the lower (even) register. */ | |
8cd64e00 YQ |
967 | if (byte_order == BFD_ENDIAN_BIG) |
968 | { | |
b66f5587 | 969 | regcache->cooked_write (arg_regs[argreg] + 1, val); |
e4c4a59b SM |
970 | regcache->cooked_write_part (arg_regs[argreg], 0, |
971 | len - 4, val + 4); | |
8cd64e00 YQ |
972 | } |
973 | else | |
974 | { | |
b66f5587 | 975 | regcache->cooked_write (arg_regs[argreg], val); |
e4c4a59b SM |
976 | regcache->cooked_write_part (arg_regs[argreg] + 1, 0, |
977 | len - 4, val + 4); | |
8cd64e00 YQ |
978 | } |
979 | } | |
980 | else | |
981 | { | |
982 | /* The argument is being passed by value in a pair of | |
dda83cd7 | 983 | registers. */ |
8cd64e00 YQ |
984 | ULONGEST regval = extract_unsigned_integer (val, len, |
985 | byte_order); | |
986 | ||
987 | regcache_cooked_write_unsigned (regcache, | |
988 | arg_regs[argreg], | |
989 | regval); | |
990 | regcache_cooked_write_unsigned (regcache, | |
991 | arg_regs[argreg] + 1, | |
992 | regval >> 32); | |
993 | } | |
994 | } | |
995 | else | |
996 | { | |
997 | /* The argument is being passed by reference in a single | |
998 | register. */ | |
999 | CORE_ADDR addr; | |
1000 | ||
1001 | /* It is not necessary to adjust REFERENCES_OFFSET to | |
1002 | 8-byte aligned in some cases, in which 4-byte alignment | |
1003 | is sufficient. For simplicity, we adjust | |
1004 | REFERENCES_OFFSET to 8-byte aligned. */ | |
1005 | references_offset = align_up (references_offset, 8); | |
1006 | ||
1007 | addr = sp + references_offset; | |
1008 | write_memory (addr, val, len); | |
1009 | references_offset += align_up (len, 4); | |
1010 | regcache_cooked_write_unsigned (regcache, arg_regs[argreg], | |
1011 | addr); | |
1012 | } | |
1013 | } | |
1014 | argreg++; | |
1015 | } | |
1016 | else | |
1017 | { | |
1018 | /* The argument is being passed on the stack. */ | |
1019 | CORE_ADDR addr; | |
1020 | ||
1021 | /* There are six different cases of alignment, and these rules can | |
1022 | be found in tic6x_arg_type_alignment: | |
1023 | ||
1024 | 1) 4-byte aligned if size is less than or equal to 4 byte, such | |
1025 | as short, int, struct, union etc. | |
1026 | 2) 8-byte aligned if size is less than or equal to 8-byte, such | |
1027 | as double, long long, | |
1028 | 3) 4-byte aligned if it is of type _Complex float, even its size | |
1029 | is 8-byte. | |
1030 | 4) 8-byte aligned if it is of type _Complex double or _Complex | |
1031 | long double, even its size is 16-byte. Because, the address of | |
1032 | variable is passed as reference. | |
1033 | 5) struct and union larger than 8-byte are passed by reference, so | |
1034 | it is 4-byte aligned. | |
1035 | 6) struct and union of size between 4 byte and 8 byte varies. | |
1036 | alignment of struct variable is the alignment of its first field, | |
1037 | while alignment of union variable is the max of all its fields' | |
1038 | alignment. */ | |
1039 | ||
1040 | if (len <= 4) | |
1041 | ; /* Default is 4-byte aligned. Nothing to be done. */ | |
1042 | else if (len <= 8) | |
1043 | stack_offset = align_up (stack_offset, | |
1044 | tic6x_arg_type_alignment (arg_type)); | |
1045 | else if (len == 16) | |
1046 | { | |
1047 | /* _Complex double or _Complex long double */ | |
1048 | if (typecode == TYPE_CODE_COMPLEX) | |
1049 | { | |
1050 | /* The argument is being passed by reference on stack. */ | |
8cd64e00 YQ |
1051 | references_offset = align_up (references_offset, 8); |
1052 | ||
1053 | addr = sp + references_offset; | |
1054 | /* Store variable on stack. */ | |
1055 | write_memory (addr, val, len); | |
1056 | ||
1057 | references_offset += align_up (len, 4); | |
1058 | ||
1059 | /* Pass the address of variable on stack as reference. */ | |
1060 | store_unsigned_integer ((gdb_byte *) val, 4, byte_order, | |
1061 | addr); | |
1062 | len = 4; | |
1063 | ||
1064 | } | |
1065 | else | |
f34652de | 1066 | internal_error (_("unexpected type %d of arg %d"), |
8cd64e00 YQ |
1067 | typecode, argnum); |
1068 | } | |
1069 | else | |
f34652de | 1070 | internal_error (_("unexpected length %d of arg %d"), len, argnum); |
8cd64e00 YQ |
1071 | |
1072 | addr = sp + stack_offset; | |
1073 | write_memory (addr, val, len); | |
1074 | stack_offset += align_up (len, 4); | |
1075 | } | |
1076 | } | |
1077 | ||
1078 | regcache_cooked_write_signed (regcache, TIC6X_SP_REGNUM, sp); | |
1079 | ||
1080 | /* Return adjusted stack pointer. */ | |
1081 | return sp; | |
1082 | } | |
1083 | ||
c9cf6e20 | 1084 | /* This is the implementation of gdbarch method stack_frame_destroyed_p. */ |
8cd64e00 YQ |
1085 | |
1086 | static int | |
c9cf6e20 | 1087 | tic6x_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
8cd64e00 YQ |
1088 | { |
1089 | unsigned long inst = tic6x_fetch_instruction (gdbarch, pc); | |
1090 | /* Normally, the epilogue is composed by instruction `b .S2 b3'. */ | |
1091 | if ((inst & 0x0f83effc) == 0x360) | |
1092 | { | |
1093 | unsigned int src2 = tic6x_register_number ((inst >> 18) & 0x1f, | |
1094 | INST_S_BIT (inst), | |
1095 | INST_X_BIT (inst)); | |
1096 | if (src2 == TIC6X_RA_REGNUM) | |
1097 | return 1; | |
1098 | } | |
1099 | ||
1100 | return 0; | |
1101 | } | |
1102 | ||
1103 | /* This is the implementation of gdbarch method get_longjmp_target. */ | |
1104 | ||
1105 | static int | |
8480a37e | 1106 | tic6x_get_longjmp_target (const frame_info_ptr &frame, CORE_ADDR *pc) |
8cd64e00 YQ |
1107 | { |
1108 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
1109 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1110 | CORE_ADDR jb_addr; | |
e362b510 | 1111 | gdb_byte buf[4]; |
8cd64e00 YQ |
1112 | |
1113 | /* JMP_BUF is passed by reference in A4. */ | |
1114 | jb_addr = get_frame_register_unsigned (frame, 4); | |
1115 | ||
1116 | /* JMP_BUF contains 13 elements of type int, and return address is stored | |
1117 | in the last slot. */ | |
1118 | if (target_read_memory (jb_addr + 12 * 4, buf, 4)) | |
1119 | return 0; | |
1120 | ||
1121 | *pc = extract_unsigned_integer (buf, 4, byte_order); | |
1122 | ||
1123 | return 1; | |
1124 | } | |
1125 | ||
18648a37 YQ |
1126 | /* This is the implementation of gdbarch method |
1127 | return_in_first_hidden_param_p. */ | |
1128 | ||
1129 | static int | |
1130 | tic6x_return_in_first_hidden_param_p (struct gdbarch *gdbarch, | |
1131 | struct type *type) | |
1132 | { | |
1133 | return 0; | |
1134 | } | |
1135 | ||
8cd64e00 YQ |
1136 | static struct gdbarch * |
1137 | tic6x_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
1138 | { | |
c1e1314d | 1139 | tdesc_arch_data_up tdesc_data; |
8cd64e00 YQ |
1140 | const struct target_desc *tdesc = info.target_desc; |
1141 | int has_gp = 0; | |
1142 | ||
1143 | /* Check any target description for validity. */ | |
1144 | if (tdesc_has_registers (tdesc)) | |
1145 | { | |
1146 | const struct tdesc_feature *feature; | |
1147 | int valid_p, i; | |
1148 | ||
1149 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.core"); | |
1150 | ||
1151 | if (feature == NULL) | |
1152 | return NULL; | |
1153 | ||
1154 | tdesc_data = tdesc_data_alloc (); | |
1155 | ||
1156 | valid_p = 1; | |
1157 | for (i = 0; i < 32; i++) /* A0 - A15, B0 - B15 */ | |
c1e1314d | 1158 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, |
8cd64e00 YQ |
1159 | tic6x_register_names[i]); |
1160 | ||
1161 | /* CSR */ | |
c1e1314d | 1162 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i++, |
8cd64e00 | 1163 | tic6x_register_names[TIC6X_CSR_REGNUM]); |
c1e1314d | 1164 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i++, |
8cd64e00 YQ |
1165 | tic6x_register_names[TIC6X_PC_REGNUM]); |
1166 | ||
1167 | if (!valid_p) | |
c1e1314d | 1168 | return NULL; |
8cd64e00 YQ |
1169 | |
1170 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.gp"); | |
1171 | if (feature) | |
1172 | { | |
1173 | int j = 0; | |
1174 | static const char *const gp[] = | |
1175 | { | |
1176 | "A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23", | |
1177 | "A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31", | |
1178 | "B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23", | |
1179 | "B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31", | |
1180 | }; | |
1181 | ||
1182 | has_gp = 1; | |
1183 | valid_p = 1; | |
1184 | for (j = 0; j < 32; j++) /* A16 - A31, B16 - B31 */ | |
c1e1314d TT |
1185 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
1186 | i++, gp[j]); | |
8cd64e00 YQ |
1187 | |
1188 | if (!valid_p) | |
c1e1314d | 1189 | return NULL; |
8cd64e00 YQ |
1190 | } |
1191 | ||
1192 | feature = tdesc_find_feature (tdesc, "org.gnu.gdb.tic6x.c6xp"); | |
1193 | if (feature) | |
1194 | { | |
c1e1314d TT |
1195 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), |
1196 | i++, "TSR"); | |
1197 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
1198 | i++, "ILC"); | |
1199 | valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), | |
1200 | i++, "RILC"); | |
8cd64e00 YQ |
1201 | |
1202 | if (!valid_p) | |
c1e1314d | 1203 | return NULL; |
8cd64e00 YQ |
1204 | } |
1205 | ||
1206 | } | |
1207 | ||
1208 | /* Find a candidate among extant architectures. */ | |
1209 | for (arches = gdbarch_list_lookup_by_info (arches, &info); | |
1210 | arches != NULL; | |
1211 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
1212 | { | |
345bd07c | 1213 | tic6x_gdbarch_tdep *tdep |
08106042 | 1214 | = gdbarch_tdep<tic6x_gdbarch_tdep> (arches->gdbarch); |
8cd64e00 YQ |
1215 | |
1216 | if (has_gp != tdep->has_gp) | |
1217 | continue; | |
1218 | ||
1219 | if (tdep && tdep->breakpoint) | |
1220 | return arches->gdbarch; | |
1221 | } | |
1222 | ||
2b16913c SM |
1223 | gdbarch *gdbarch |
1224 | = gdbarch_alloc (&info, gdbarch_tdep_up (new tic6x_gdbarch_tdep)); | |
1225 | tic6x_gdbarch_tdep *tdep = gdbarch_tdep<tic6x_gdbarch_tdep> (gdbarch); | |
8cd64e00 YQ |
1226 | |
1227 | tdep->has_gp = has_gp; | |
8cd64e00 YQ |
1228 | |
1229 | /* Data type sizes. */ | |
1230 | set_gdbarch_ptr_bit (gdbarch, 32); | |
1231 | set_gdbarch_addr_bit (gdbarch, 32); | |
1232 | set_gdbarch_short_bit (gdbarch, 16); | |
1233 | set_gdbarch_int_bit (gdbarch, 32); | |
1234 | set_gdbarch_long_bit (gdbarch, 32); | |
1235 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1236 | set_gdbarch_float_bit (gdbarch, 32); | |
1237 | set_gdbarch_double_bit (gdbarch, 64); | |
1238 | ||
1239 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); | |
1240 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
1241 | ||
1242 | /* The register set. */ | |
1243 | set_gdbarch_num_regs (gdbarch, TIC6X_NUM_REGS); | |
1244 | set_gdbarch_sp_regnum (gdbarch, TIC6X_SP_REGNUM); | |
1245 | set_gdbarch_pc_regnum (gdbarch, TIC6X_PC_REGNUM); | |
1246 | ||
1247 | set_gdbarch_register_name (gdbarch, tic6x_register_name); | |
1248 | set_gdbarch_register_type (gdbarch, tic6x_register_type); | |
1249 | ||
1250 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
1251 | ||
1252 | set_gdbarch_skip_prologue (gdbarch, tic6x_skip_prologue); | |
04180708 YQ |
1253 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1254 | tic6x_breakpoint_kind_from_pc); | |
1255 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1256 | tic6x_sw_breakpoint_from_kind); | |
8cd64e00 YQ |
1257 | |
1258 | set_gdbarch_unwind_pc (gdbarch, tic6x_unwind_pc); | |
8cd64e00 YQ |
1259 | |
1260 | /* Unwinding. */ | |
1261 | dwarf2_append_unwinders (gdbarch); | |
1262 | ||
1263 | frame_unwind_append_unwinder (gdbarch, &tic6x_stub_unwind); | |
1264 | frame_unwind_append_unwinder (gdbarch, &tic6x_frame_unwind); | |
195abc10 | 1265 | frame_base_set_default (gdbarch, &tic6x_frame_base); |
8cd64e00 YQ |
1266 | |
1267 | dwarf2_frame_set_init_reg (gdbarch, tic6x_dwarf2_frame_init_reg); | |
1268 | ||
1269 | /* Single stepping. */ | |
1270 | set_gdbarch_software_single_step (gdbarch, tic6x_software_single_step); | |
1271 | ||
8cd64e00 YQ |
1272 | /* Call dummy code. */ |
1273 | set_gdbarch_frame_align (gdbarch, tic6x_frame_align); | |
1274 | ||
8cd64e00 YQ |
1275 | set_gdbarch_return_value (gdbarch, tic6x_return_value); |
1276 | ||
8cd64e00 YQ |
1277 | /* Enable inferior call support. */ |
1278 | set_gdbarch_push_dummy_call (gdbarch, tic6x_push_dummy_call); | |
1279 | ||
1280 | set_gdbarch_get_longjmp_target (gdbarch, tic6x_get_longjmp_target); | |
1281 | ||
c9cf6e20 | 1282 | set_gdbarch_stack_frame_destroyed_p (gdbarch, tic6x_stack_frame_destroyed_p); |
8cd64e00 | 1283 | |
18648a37 YQ |
1284 | set_gdbarch_return_in_first_hidden_param_p (gdbarch, |
1285 | tic6x_return_in_first_hidden_param_p); | |
1286 | ||
8cd64e00 YQ |
1287 | /* Hook in ABI-specific overrides, if they have been registered. */ |
1288 | gdbarch_init_osabi (info, gdbarch); | |
1289 | ||
c1e1314d TT |
1290 | if (tdesc_data != nullptr) |
1291 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); | |
8cd64e00 YQ |
1292 | |
1293 | return gdbarch; | |
1294 | } | |
1295 | ||
6c265988 | 1296 | void _initialize_tic6x_tdep (); |
8cd64e00 | 1297 | void |
6c265988 | 1298 | _initialize_tic6x_tdep () |
8cd64e00 | 1299 | { |
ec29a63c | 1300 | gdbarch_register (bfd_arch_tic6x, tic6x_gdbarch_init); |
8cd64e00 | 1301 | } |