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[thirdparty/binutils-gdb.git] / gdb / v850-tdep.c
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181124bc
CV		 1/* Target-dependent code for the NEC V850 for GDB, the GNU debugger.
2
213516ef 3 Copyright (C) 1996-2023 Free Software Foundation, Inc.
181124bc
CV		 4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
a9762ec7 9 the Free Software Foundation; either version 3 of the License, or
181124bc
CV		 10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
a9762ec7 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
181124bc
CV		 19
20#include "defs.h"
21#include "frame.h"
22#include "frame-base.h"
23#include "trad-frame.h"
24#include "frame-unwind.h"
82ca8957 25#include "dwarf2/frame.h"
181124bc
CV		 26#include "gdbtypes.h"
27#include "inferior.h"
181124bc
CV		 28#include "gdbcore.h"
29#include "arch-utils.h"
30#include "regcache.h"
31#include "dis-asm.h"
32#include "osabi.h"
83b2706a
KB		 33#include "elf-bfd.h"
34#include "elf/v850.h"
76eb8ef1 35#include "gdbarch.h"
181124bc
CV		 36
37enum
38 {
a2d13a0d 39 /* General purpose registers. */
181124bc
CV		 40 E_R0_REGNUM,
41 E_R1_REGNUM,
42 E_R2_REGNUM,
43 E_R3_REGNUM, E_SP_REGNUM = E_R3_REGNUM,
44 E_R4_REGNUM,
45 E_R5_REGNUM,
46 E_R6_REGNUM, E_ARG0_REGNUM = E_R6_REGNUM,
47 E_R7_REGNUM,
48 E_R8_REGNUM,
49 E_R9_REGNUM, E_ARGLAST_REGNUM = E_R9_REGNUM,
50 E_R10_REGNUM, E_V0_REGNUM = E_R10_REGNUM,
51 E_R11_REGNUM, E_V1_REGNUM = E_R11_REGNUM,
52 E_R12_REGNUM,
53 E_R13_REGNUM,
54 E_R14_REGNUM,
55 E_R15_REGNUM,
56 E_R16_REGNUM,
57 E_R17_REGNUM,
58 E_R18_REGNUM,
59 E_R19_REGNUM,
60 E_R20_REGNUM,
61 E_R21_REGNUM,
62 E_R22_REGNUM,
63 E_R23_REGNUM,
64 E_R24_REGNUM,
65 E_R25_REGNUM,
66 E_R26_REGNUM,
67 E_R27_REGNUM,
68 E_R28_REGNUM,
69 E_R29_REGNUM, E_FP_REGNUM = E_R29_REGNUM,
70 E_R30_REGNUM, E_EP_REGNUM = E_R30_REGNUM,
71 E_R31_REGNUM, E_LP_REGNUM = E_R31_REGNUM,
a2d13a0d
KB		 72
73 /* System registers - main banks. */
181124bc
CV		 74 E_R32_REGNUM, E_SR0_REGNUM = E_R32_REGNUM,
75 E_R33_REGNUM,
76 E_R34_REGNUM,
77 E_R35_REGNUM,
78 E_R36_REGNUM,
79 E_R37_REGNUM, E_PS_REGNUM = E_R37_REGNUM,
80 E_R38_REGNUM,
81 E_R39_REGNUM,
82 E_R40_REGNUM,
83 E_R41_REGNUM,
84 E_R42_REGNUM,
85 E_R43_REGNUM,
86 E_R44_REGNUM,
87 E_R45_REGNUM,
88 E_R46_REGNUM,
89 E_R47_REGNUM,
90 E_R48_REGNUM,
91 E_R49_REGNUM,
92 E_R50_REGNUM,
93 E_R51_REGNUM,
94 E_R52_REGNUM, E_CTBP_REGNUM = E_R52_REGNUM,
95 E_R53_REGNUM,
96 E_R54_REGNUM,
97 E_R55_REGNUM,
98 E_R56_REGNUM,
99 E_R57_REGNUM,
100 E_R58_REGNUM,
101 E_R59_REGNUM,
102 E_R60_REGNUM,
103 E_R61_REGNUM,
104 E_R62_REGNUM,
105 E_R63_REGNUM,
a2d13a0d
KB		 106
107 /* PC. */
181124bc 108 E_R64_REGNUM, E_PC_REGNUM = E_R64_REGNUM,
55fa75c3
KB		 109 E_R65_REGNUM,
110 E_NUM_OF_V850_REGS,
111 E_NUM_OF_V850E_REGS = E_NUM_OF_V850_REGS,
2aaed979 112
a2d13a0d 113 /* System registers - MPV (PROT00) bank. */
55fa75c3 114 E_R66_REGNUM = E_NUM_OF_V850_REGS,
2aaed979
KB		 115 E_R67_REGNUM,
116 E_R68_REGNUM,
117 E_R69_REGNUM,
118 E_R70_REGNUM,
119 E_R71_REGNUM,
120 E_R72_REGNUM,
121 E_R73_REGNUM,
122 E_R74_REGNUM,
123 E_R75_REGNUM,
124 E_R76_REGNUM,
125 E_R77_REGNUM,
126 E_R78_REGNUM,
127 E_R79_REGNUM,
128 E_R80_REGNUM,
129 E_R81_REGNUM,
130 E_R82_REGNUM,
131 E_R83_REGNUM,
132 E_R84_REGNUM,
133 E_R85_REGNUM,
134 E_R86_REGNUM,
135 E_R87_REGNUM,
136 E_R88_REGNUM,
137 E_R89_REGNUM,
138 E_R90_REGNUM,
139 E_R91_REGNUM,
140 E_R92_REGNUM,
141 E_R93_REGNUM,
142
a2d13a0d 143 /* System registers - MPU (PROT01) bank. */
2aaed979
KB		 144 E_R94_REGNUM,
145 E_R95_REGNUM,
146 E_R96_REGNUM,
147 E_R97_REGNUM,
148 E_R98_REGNUM,
149 E_R99_REGNUM,
150 E_R100_REGNUM,
151 E_R101_REGNUM,
152 E_R102_REGNUM,
153 E_R103_REGNUM,
154 E_R104_REGNUM,
155 E_R105_REGNUM,
156 E_R106_REGNUM,
157 E_R107_REGNUM,
158 E_R108_REGNUM,
159 E_R109_REGNUM,
160 E_R110_REGNUM,
161 E_R111_REGNUM,
162 E_R112_REGNUM,
163 E_R113_REGNUM,
164 E_R114_REGNUM,
165 E_R115_REGNUM,
166 E_R116_REGNUM,
167 E_R117_REGNUM,
168 E_R118_REGNUM,
169 E_R119_REGNUM,
170 E_R120_REGNUM,
171 E_R121_REGNUM,
172
a2d13a0d 173 /* FPU system registers. */
2aaed979
KB		 174 E_R122_REGNUM,
175 E_R123_REGNUM,
176 E_R124_REGNUM,
177 E_R125_REGNUM,
178 E_R126_REGNUM,
179 E_R127_REGNUM,
180 E_R128_REGNUM, E_FPSR_REGNUM = E_R128_REGNUM,
181 E_R129_REGNUM, E_FPEPC_REGNUM = E_R129_REGNUM,
182 E_R130_REGNUM, E_FPST_REGNUM = E_R130_REGNUM,
183 E_R131_REGNUM, E_FPCC_REGNUM = E_R131_REGNUM,
184 E_R132_REGNUM, E_FPCFG_REGNUM = E_R132_REGNUM,
185 E_R133_REGNUM,
186 E_R134_REGNUM,
187 E_R135_REGNUM,
188 E_R136_REGNUM,
189 E_R137_REGNUM,
190 E_R138_REGNUM,
191 E_R139_REGNUM,
192 E_R140_REGNUM,
193 E_R141_REGNUM,
194 E_R142_REGNUM,
195 E_R143_REGNUM,
196 E_R144_REGNUM,
197 E_R145_REGNUM,
198 E_R146_REGNUM,
199 E_R147_REGNUM,
200 E_R148_REGNUM,
83b2706a
KB		 201 E_R149_REGNUM,
202 E_NUM_OF_V850E2_REGS,
203
204 /* v850e3v5 system registers, selID 1 thru 7. */
205 E_SELID_1_R0_REGNUM = E_NUM_OF_V850E2_REGS,
206 E_SELID_1_R31_REGNUM = E_SELID_1_R0_REGNUM + 31,
207
208 E_SELID_2_R0_REGNUM,
209 E_SELID_2_R31_REGNUM = E_SELID_2_R0_REGNUM + 31,
210
211 E_SELID_3_R0_REGNUM,
212 E_SELID_3_R31_REGNUM = E_SELID_3_R0_REGNUM + 31,
213
214 E_SELID_4_R0_REGNUM,
215 E_SELID_4_R31_REGNUM = E_SELID_4_R0_REGNUM + 31,
216
217 E_SELID_5_R0_REGNUM,
218 E_SELID_5_R31_REGNUM = E_SELID_5_R0_REGNUM + 31,
219
220 E_SELID_6_R0_REGNUM,
221 E_SELID_6_R31_REGNUM = E_SELID_6_R0_REGNUM + 31,
222
223 E_SELID_7_R0_REGNUM,
224 E_SELID_7_R31_REGNUM = E_SELID_7_R0_REGNUM + 31,
225
226 /* v850e3v5 vector registers. */
227 E_VR0_REGNUM,
228 E_VR31_REGNUM = E_VR0_REGNUM + 31,
229
230 E_NUM_OF_V850E3V5_REGS,
231
232 /* Total number of possible registers. */
233 E_NUM_REGS = E_NUM_OF_V850E3V5_REGS
181124bc
CV		 234 };
235
236enum
237{
238 v850_reg_size = 4
239};
240
241/* Size of return datatype which fits into all return registers. */
242enum
243{
244 E_MAX_RETTYPE_SIZE_IN_REGS = 2 * v850_reg_size
245};
246
83b2706a
KB		 247/* When v850 support was added to GCC in the late nineties, the intention
248 was to follow the Green Hills ABI for v850. In fact, the authors of
249 that support at the time thought that they were doing so. As far as
250 I can tell, the calling conventions are correct, but the return value
251 conventions were not quite right. Over time, the return value code
252 in this file was modified to mostly reflect what GCC was actually
253 doing instead of to actually follow the Green Hills ABI as it did
254 when the code was first written.
255
256 Renesas defined the RH850 ABI which they use in their compiler. It
257 is similar to the original Green Hills ABI with some minor
258 differences. */
259
260enum v850_abi
261{
262 V850_ABI_GCC,
263 V850_ABI_RH850
264};
265
266/* Architecture specific data. */
267
ab25d9bb 268struct v850_gdbarch_tdep : gdbarch_tdep_base
83b2706a
KB		 269{
270 /* Fields from the ELF header. */
345bd07c
SM		 271 int e_flags = 0;
272 int e_machine = 0;
83b2706a
KB		 273
274 /* Which ABI are we using? */
345bd07c
SM		 275 enum v850_abi abi {};
276 int eight_byte_align = 0;
83b2706a
KB		 277};
278
181124bc
CV		 279struct v850_frame_cache
280{
281 /* Base address. */
282 CORE_ADDR base;
283 LONGEST sp_offset;
284 CORE_ADDR pc;
285
286 /* Flag showing that a frame has been created in the prologue code. */
287 int uses_fp;
288
289 /* Saved registers. */
098caef4 290 trad_frame_saved_reg *saved_regs;
181124bc
CV		 291};
292
293/* Info gleaned from scanning a function's prologue. */
294struct pifsr /* Info about one saved register. */
295{
296 int offset; /* Offset from sp or fp. */
297 int cur_frameoffset; /* Current frameoffset. */
298 int reg; /* Saved register number. */
299};
300
301static const char *
d93859e2 302v850_register_name (struct gdbarch *gdbarch, int regnum)
181124bc
CV		 303{
304 static const char *v850_reg_names[] =
305 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
306 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
307 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
308 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
309 "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
310 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
311 "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
312 "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
313 "pc", "fp"
314 };
9b9e61c7 315 gdb_static_assert (E_NUM_OF_V850_REGS == ARRAY_SIZE (v850_reg_names));
181124bc
CV		 316 return v850_reg_names[regnum];
317}
318
319static const char *
d93859e2 320v850e_register_name (struct gdbarch *gdbarch, int regnum)
181124bc
CV		 321{
322 static const char *v850e_reg_names[] =
323 {
324 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
325 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
326 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
327 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
328 "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
329 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
330 "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
331 "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
332 "pc", "fp"
333 };
9b9e61c7 334 gdb_static_assert (E_NUM_OF_V850E_REGS == ARRAY_SIZE (v850e_reg_names));
181124bc
CV		 335 return v850e_reg_names[regnum];
336}
337
2aaed979
KB		 338static const char *
339v850e2_register_name (struct gdbarch *gdbarch, int regnum)
340{
341 static const char *v850e2_reg_names[] =
342 {
a2d13a0d 343 /* General purpose registers. */
2aaed979
KB		 344 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
345 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
346 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
347 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
348
a2d13a0d
KB		 349 /* System registers - main banks. */
350 "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "pid", "cfg",
351 "", "", "", "sccfg", "scbp", "eiic", "feic", "dbic",
352 "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "dir", "", "",
353 "", "", "", "", "eiwr", "fewr", "dbwr", "bsel",
354
355
356 /* PC. */
357 "pc", "",
2aaed979 358
a2d13a0d
KB		 359 /* System registers - MPV (PROT00) bank. */
360 "vsecr", "vstid", "vsadr", "", "vmecr", "vmtid", "vmadr", "",
361 "vpecr", "vptid", "vpadr", "", "", "", "", "",
362 "", "", "", "", "", "", "", "",
363 "mca", "mcs", "mcc", "mcr",
2aaed979 364
a2d13a0d
KB		 365 /* System registers - MPU (PROT01) bank. */
366 "mpm", "mpc", "tid", "", "", "", "ipa0l", "ipa0u",
367 "ipa1l", "ipa1u", "ipa2l", "ipa2u", "ipa3l", "ipa3u", "ipa4l", "ipa4u",
368 "dpa0l", "dpa0u", "dpa1l", "dpa1u", "dpa2l", "dpa2u", "dpa3l", "dpa3u",
369 "dpa4l", "dpa4u", "dpa5l", "dpa5u",
2aaed979 370
a2d13a0d
KB		 371 /* FPU system registers. */
372 "", "", "", "", "", "", "fpsr", "fpepc",
373 "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
374 "", "", "", "", "", "", "", "",
375 "", "", "", "fpspc"
2aaed979 376 };
9b9e61c7 377 if (regnum >= E_NUM_OF_V850E2_REGS)
9a972b54 378 return "";
2aaed979
KB		 379 return v850e2_reg_names[regnum];
380}
381
83b2706a
KB		 382/* Implement the "register_name" gdbarch method for v850e3v5. */
383
384static const char *
385v850e3v5_register_name (struct gdbarch *gdbarch, int regnum)
386{
387 static const char *v850e3v5_reg_names[] =
388 {
389 /* General purpose registers. */
390 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
391 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
392 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
393 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
394
395 /* selID 0, not including FPU registers. The FPU registers are
396 listed later on. */
397 "eipc", "eipsw", "fepc", "fepsw",
398 "", "psw", "" /* fpsr */, "" /* fpepc */,
399 "" /* fpst */, "" /* fpcc */, "" /* fpcfg */, "" /* fpec */,
400 "sesr", "eiic", "feic", "",
401 "ctpc", "ctpsw", "", "", "ctbp", "", "", "",
402 "", "", "", "", "eiwr", "fewr", "", "bsel",
403
404
405 /* PC. */
406 "pc", "",
407
408 /* v850e2 MPV bank. */
409 "", "", "", "", "", "", "", "",
410 "", "", "", "", "", "", "", "",
411 "", "", "", "", "", "", "", "",
412 "", "", "", "",
413
414 /* Skip v850e2 MPU bank. It's tempting to reuse these, but we need
415 32 entries for this bank. */
416 "", "", "", "", "", "", "", "",
417 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
419 "", "", "", "",
420
421 /* FPU system registers. These are actually in selID 0, but
422 are placed here to preserve register numbering compatibility
423 with previous architectures. */
424 "", "", "", "", "", "", "fpsr", "fpepc",
425 "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
426 "", "", "", "", "", "", "", "",
427 "", "", "", "",
428
429 /* selID 1. */
430 "mcfg0", "mcfg1", "rbase", "ebase", "intbp", "mctl", "pid", "fpipr",
431 "", "", "tcsel", "sccfg", "scbp", "hvccfg", "hvcbp", "vsel",
432 "vmprt0", "vmprt1", "vmprt2", "", "", "", "", "vmscctl",
433 "vmsctbl0", "vmsctbl1", "vmsctbl2", "vmsctbl3", "", "", "", "",
434
435 /* selID 2. */
436 "htcfg0", "", "", "", "", "htctl", "mea", "asid",
437 "mei", "ispr", "pmr", "icsr", "intcfg", "", "", "",
438 "tlbsch", "", "", "", "", "", "", "htscctl",
439 "htsctbl0", "htsctbl1", "htsctbl2", "htsctbl3",
440 "htsctbl4", "htsctbl5", "htsctbl6", "htsctbl7",
441
442 /* selID 3. */
443 "", "", "", "", "", "", "", "",
444 "", "", "", "", "", "", "", "",
445 "", "", "", "", "", "", "", "",
446 "", "", "", "", "", "", "", "",
447
448 /* selID 4. */
449 "tlbidx", "", "", "", "telo0", "telo1", "tehi0", "tehi1",
450 "", "", "tlbcfg", "", "bwerrl", "bwerrh", "brerrl", "brerrh",
451 "ictagl", "ictagh", "icdatl", "icdath",
452 "dctagl", "dctagh", "dcdatl", "dcdath",
453 "icctrl", "dcctrl", "iccfg", "dccfg", "icerr", "dcerr", "", "",
454
455 /* selID 5. */
456 "mpm", "mprc", "", "", "mpbrgn", "mptrgn", "", "",
457 "mca", "mcs", "mcc", "mcr", "", "", "", "",
458 "", "", "", "", "mpprt0", "mpprt1", "mpprt2", "",
459 "", "", "", "", "", "", "", "",
460
461 /* selID 6. */
462 "mpla0", "mpua0", "mpat0", "", "mpla1", "mpua1", "mpat1", "",
463 "mpla2", "mpua2", "mpat2", "", "mpla3", "mpua3", "mpat3", "",
464 "mpla4", "mpua4", "mpat4", "", "mpla5", "mpua5", "mpat5", "",
465 "mpla6", "mpua6", "mpat6", "", "mpla7", "mpua7", "mpat7", "",
466
467 /* selID 7. */
468 "mpla8", "mpua8", "mpat8", "", "mpla9", "mpua9", "mpat9", "",
469 "mpla10", "mpua10", "mpat10", "", "mpla11", "mpua11", "mpat11", "",
470 "mpla12", "mpua12", "mpat12", "", "mpla13", "mpua13", "mpat13", "",
471 "mpla14", "mpua14", "mpat14", "", "mpla15", "mpua15", "mpat15", "",
472
473 /* Vector Registers */
474 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
475 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
476 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
477 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31",
478 };
479
9b9e61c7
AB		 480 gdb_static_assert (E_NUM_OF_V850E3V5_REGS
481 == ARRAY_SIZE (v850e3v5_reg_names));
83b2706a
KB		 482 return v850e3v5_reg_names[regnum];
483}
484
181124bc
CV		 485/* Returns the default type for register N. */
486
487static struct type *
488v850_register_type (struct gdbarch *gdbarch, int regnum)
489{
490 if (regnum == E_PC_REGNUM)
0dfff4cb 491 return builtin_type (gdbarch)->builtin_func_ptr;
83b2706a
KB		 492 else if (E_VR0_REGNUM <= regnum && regnum <= E_VR31_REGNUM)
493 return builtin_type (gdbarch)->builtin_uint64;
df4df182 494 return builtin_type (gdbarch)->builtin_int32;
181124bc
CV		 495}
496
497static int
498v850_type_is_scalar (struct type *t)
499{
78134374
SM		 500 return (t->code () != TYPE_CODE_STRUCT
501 && t->code () != TYPE_CODE_UNION
502 && t->code () != TYPE_CODE_ARRAY);
181124bc
CV		 503}
504
505/* Should call_function allocate stack space for a struct return? */
83b2706a 506
181124bc 507static int
83b2706a 508v850_use_struct_convention (struct gdbarch *gdbarch, struct type *type)
181124bc
CV		 509{
510 int i;
511 struct type *fld_type, *tgt_type;
08106042 512 v850_gdbarch_tdep *tdep = gdbarch_tdep<v850_gdbarch_tdep> (gdbarch);
181124bc 513
345bd07c 514 if (tdep->abi == V850_ABI_RH850)
83b2706a 515 {
df86565b 516 if (v850_type_is_scalar (type) && type->length () <= 8)
83b2706a
KB		 517 return 0;
518
519 /* Structs are never returned in registers for this ABI. */
520 return 1;
521 }
181124bc 522 /* 1. The value is greater than 8 bytes -> returned by copying. */
df86565b 523 if (type->length () > 8)
181124bc
CV		 524 return 1;
525
526 /* 2. The value is a single basic type -> returned in register. */
527 if (v850_type_is_scalar (type))
528 return 0;
529
530 /* The value is a structure or union with a single element and that
531 element is either a single basic type or an array of a single basic
532 type whose size is greater than or equal to 4 -> returned in register. */
78134374
SM		 533 if ((type->code () == TYPE_CODE_STRUCT
534 || type->code () == TYPE_CODE_UNION)
1f704f76 535 && type->num_fields () == 1)
181124bc 536 {
940da03e 537 fld_type = type->field (0).type ();
df86565b 538 if (v850_type_is_scalar (fld_type) && fld_type->length () >= 4)
181124bc
CV		 539 return 0;
540
78134374 541 if (fld_type->code () == TYPE_CODE_ARRAY)
dda83cd7 542 {
27710edb 543 tgt_type = fld_type->target_type ();
df86565b 544 if (v850_type_is_scalar (tgt_type) && tgt_type->length () >= 4)
181124bc
CV		 545 return 0;
546 }
547 }
548
549 /* The value is a structure whose first element is an integer or a float,
550 and which contains no arrays of more than two elements -> returned in
551 register. */
78134374 552 if (type->code () == TYPE_CODE_STRUCT
940da03e 553 && v850_type_is_scalar (type->field (0).type ())
df86565b 554 && type->field (0).type ()->length () == 4)
181124bc 555 {
1f704f76 556 for (i = 1; i < type->num_fields (); ++i)
dda83cd7 557 {
940da03e 558 fld_type = type->field (0).type ();
78134374 559 if (fld_type->code () == TYPE_CODE_ARRAY)
181124bc 560 {
27710edb 561 tgt_type = fld_type->target_type ();
df86565b
SM		 562 if (tgt_type->length () > 0
563 && fld_type->length () / tgt_type->length () > 2)
181124bc
CV		 564 return 1;
565 }
566 }
567 return 0;
568 }
569
581e13c1
MS		 570 /* The value is a union which contains at least one field which
571 would be returned in registers according to these rules ->
572 returned in register. */
78134374 573 if (type->code () == TYPE_CODE_UNION)
181124bc 574 {
1f704f76 575 for (i = 0; i < type->num_fields (); ++i)
dda83cd7 576 {
940da03e 577 fld_type = type->field (0).type ();
83b2706a 578 if (!v850_use_struct_convention (gdbarch, fld_type))
181124bc
CV		 579 return 0;
580 }
581 }
582
583 return 1;
584}
585
586/* Structure for mapping bits in register lists to register numbers. */
83b2706a 587
181124bc
CV		 588struct reg_list
589{
590 long mask;
591 int regno;
592};
593
594/* Helper function for v850_scan_prologue to handle prepare instruction. */
595
596static void
597v850_handle_prepare (int insn, int insn2, CORE_ADDR * current_pc_ptr,
598 struct v850_frame_cache *pi, struct pifsr **pifsr_ptr)
599{
600 CORE_ADDR current_pc = *current_pc_ptr;
601 struct pifsr *pifsr = *pifsr_ptr;
602 long next = insn2 & 0xffff;
603 long list12 = ((insn & 1) << 16) + (next & 0xffe0);
604 long offset = (insn & 0x3e) << 1;
605 static struct reg_list reg_table[] =
606 {
607 {0x00800, 20}, /* r20 */
608 {0x00400, 21}, /* r21 */
609 {0x00200, 22}, /* r22 */
610 {0x00100, 23}, /* r23 */
611 {0x08000, 24}, /* r24 */
612 {0x04000, 25}, /* r25 */
613 {0x02000, 26}, /* r26 */
614 {0x01000, 27}, /* r27 */
615 {0x00080, 28}, /* r28 */
616 {0x00040, 29}, /* r29 */
617 {0x10000, 30}, /* ep */
618 {0x00020, 31}, /* lp */
619 {0, 0} /* end of table */
620 };
621 int i;
622
623 if ((next & 0x1f) == 0x0b) /* skip imm16 argument */
624 current_pc += 2;
625 else if ((next & 0x1f) == 0x13) /* skip imm16 argument */
626 current_pc += 2;
627 else if ((next & 0x1f) == 0x1b) /* skip imm32 argument */
628 current_pc += 4;
629
630 /* Calculate the total size of the saved registers, and add it to the
631 immediate value used to adjust SP. */
632 for (i = 0; reg_table[i].mask != 0; i++)
633 if (list12 & reg_table[i].mask)
634 offset += v850_reg_size;
635 pi->sp_offset -= offset;
636
637 /* Calculate the offsets of the registers relative to the value the SP
638 will have after the registers have been pushed and the imm5 value has
639 been subtracted from it. */
640 if (pifsr)
641 {
642 for (i = 0; reg_table[i].mask != 0; i++)
643 {
644 if (list12 & reg_table[i].mask)
645 {
646 int reg = reg_table[i].regno;
647 offset -= v850_reg_size;
648 pifsr->reg = reg;
649 pifsr->offset = offset;
650 pifsr->cur_frameoffset = pi->sp_offset;
651 pifsr++;
652 }
653 }
654 }
655
656 /* Set result parameters. */
657 *current_pc_ptr = current_pc;
658 *pifsr_ptr = pifsr;
659}
660
661
662/* Helper function for v850_scan_prologue to handle pushm/pushl instructions.
663 The SR bit of the register list is not supported. gcc does not generate
664 this bit. */
665
666static void
667v850_handle_pushm (int insn, int insn2, struct v850_frame_cache *pi,
668 struct pifsr **pifsr_ptr)
669{
670 struct pifsr *pifsr = *pifsr_ptr;
671 long list12 = ((insn & 0x0f) << 16) + (insn2 & 0xfff0);
672 long offset = 0;
673 static struct reg_list pushml_reg_table[] =
674 {
675 {0x80000, E_PS_REGNUM}, /* PSW */
676 {0x40000, 1}, /* r1 */
677 {0x20000, 2}, /* r2 */
678 {0x10000, 3}, /* r3 */
679 {0x00800, 4}, /* r4 */
680 {0x00400, 5}, /* r5 */
681 {0x00200, 6}, /* r6 */
682 {0x00100, 7}, /* r7 */
683 {0x08000, 8}, /* r8 */
684 {0x04000, 9}, /* r9 */
685 {0x02000, 10}, /* r10 */
686 {0x01000, 11}, /* r11 */
687 {0x00080, 12}, /* r12 */
688 {0x00040, 13}, /* r13 */
689 {0x00020, 14}, /* r14 */
690 {0x00010, 15}, /* r15 */
691 {0, 0} /* end of table */
692 };
693 static struct reg_list pushmh_reg_table[] =
694 {
695 {0x80000, 16}, /* r16 */
696 {0x40000, 17}, /* r17 */
697 {0x20000, 18}, /* r18 */
698 {0x10000, 19}, /* r19 */
699 {0x00800, 20}, /* r20 */
700 {0x00400, 21}, /* r21 */
701 {0x00200, 22}, /* r22 */
702 {0x00100, 23}, /* r23 */
703 {0x08000, 24}, /* r24 */
704 {0x04000, 25}, /* r25 */
705 {0x02000, 26}, /* r26 */
706 {0x01000, 27}, /* r27 */
707 {0x00080, 28}, /* r28 */
708 {0x00040, 29}, /* r29 */
709 {0x00010, 30}, /* r30 */
710 {0x00020, 31}, /* r31 */
711 {0, 0} /* end of table */
712 };
713 struct reg_list *reg_table;
714 int i;
715
716 /* Is this a pushml or a pushmh? */
717 if ((insn2 & 7) == 1)
718 reg_table = pushml_reg_table;
719 else
720 reg_table = pushmh_reg_table;
721
7a9dd1b2 722 /* Calculate the total size of the saved registers, and add it to the
181124bc
CV		 723 immediate value used to adjust SP. */
724 for (i = 0; reg_table[i].mask != 0; i++)
725 if (list12 & reg_table[i].mask)
726 offset += v850_reg_size;
727 pi->sp_offset -= offset;
728
729 /* Calculate the offsets of the registers relative to the value the SP
730 will have after the registers have been pushed and the imm5 value is
731 subtracted from it. */
732 if (pifsr)
733 {
734 for (i = 0; reg_table[i].mask != 0; i++)
735 {
736 if (list12 & reg_table[i].mask)
737 {
738 int reg = reg_table[i].regno;
739 offset -= v850_reg_size;
740 pifsr->reg = reg;
741 pifsr->offset = offset;
742 pifsr->cur_frameoffset = pi->sp_offset;
743 pifsr++;
744 }
745 }
746 }
747
748 /* Set result parameters. */
749 *pifsr_ptr = pifsr;
750}
751
752/* Helper function to evaluate if register is one of the "save" registers.
753 This allows to simplify conditionals in v850_analyze_prologue a lot. */
754
755static int
756v850_is_save_register (int reg)
757{
758 /* The caller-save registers are R2, R20 - R29 and R31. All other
759 registers are either special purpose (PC, SP), argument registers,
581e13c1 760 or just considered free for use in the caller. */
181124bc
CV		 761 return reg == E_R2_REGNUM
762 || (reg >= E_R20_REGNUM && reg <= E_R29_REGNUM)
763 || reg == E_R31_REGNUM;
764}
765
766/* Scan the prologue of the function that contains PC, and record what
767 we find in PI. Returns the pc after the prologue. Note that the
768 addresses saved in frame->saved_regs are just frame relative (negative
769 offsets from the frame pointer). This is because we don't know the
770 actual value of the frame pointer yet. In some circumstances, the
771 frame pointer can't be determined till after we have scanned the
772 prologue. */
773
774static CORE_ADDR
e17a4113
UW		 775v850_analyze_prologue (struct gdbarch *gdbarch,
776 CORE_ADDR func_addr, CORE_ADDR pc,
d2ca4222 777 struct v850_frame_cache *pi, ULONGEST ctbp)
181124bc 778{
e17a4113 779 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
181124bc
CV		 780 CORE_ADDR prologue_end, current_pc;
781 struct pifsr pifsrs[E_NUM_REGS + 1];
782 struct pifsr *pifsr, *pifsr_tmp;
181124bc
CV		 783 int ep_used;
784 int reg;
785 CORE_ADDR save_pc, save_end;
786 int regsave_func_p;
787 int r12_tmp;
788
789 memset (&pifsrs, 0, sizeof pifsrs);
790 pifsr = &pifsrs[0];
791
792 prologue_end = pc;
793
794 /* Now, search the prologue looking for instructions that setup fp, save
795 rp, adjust sp and such. We also record the frame offset of any saved
796 registers. */
797
798 pi->sp_offset = 0;
799 pi->uses_fp = 0;
800 ep_used = 0;
801 regsave_func_p = 0;
802 save_pc = 0;
803 save_end = 0;
804 r12_tmp = 0;
805
806 for (current_pc = func_addr; current_pc < prologue_end;)
807 {
808 int insn;
809 int insn2 = -1; /* dummy value */
810
e17a4113 811 insn = read_memory_integer (current_pc, 2, byte_order);
181124bc 812 current_pc += 2;
581e13c1 813 if ((insn & 0x0780) >= 0x0600) /* Four byte instruction? */
181124bc 814 {
e17a4113 815 insn2 = read_memory_integer (current_pc, 2, byte_order);
181124bc
CV		 816 current_pc += 2;
817 }
818
819 if ((insn & 0xffc0) == ((10 << 11) | 0x0780) && !regsave_func_p)
820 { /* jarl <func>,10 */
821 long low_disp = insn2 & ~(long) 1;
822 long disp = (((((insn & 0x3f) << 16) + low_disp)
823 & ~(long) 1) ^ 0x00200000) - 0x00200000;
824
825 save_pc = current_pc;
826 save_end = prologue_end;
827 regsave_func_p = 1;
828 current_pc += disp - 4;
829 prologue_end = (current_pc
830 + (2 * 3) /* moves to/from ep */
831 + 4 /* addi <const>,sp,sp */
832 + 2 /* jmp [r10] */
833 + (2 * 12) /* sst.w to save r2, r20-r29, r31 */
834 + 20); /* slop area */
835 }
836 else if ((insn & 0xffc0) == 0x0200 && !regsave_func_p)
837 { /* callt <imm6> */
181124bc
CV		 838 long adr = ctbp + ((insn & 0x3f) << 1);
839
840 save_pc = current_pc;
841 save_end = prologue_end;
842 regsave_func_p = 1;
e17a4113
UW		 843 current_pc = ctbp + (read_memory_unsigned_integer (adr, 2, byte_order)
844 & 0xffff);
181124bc
CV		 845 prologue_end = (current_pc
846 + (2 * 3) /* prepare list2,imm5,sp/imm */
847 + 4 /* ctret */
848 + 20); /* slop area */
849 continue;
850 }
851 else if ((insn & 0xffc0) == 0x0780) /* prepare list2,imm5 */
852 {
853 v850_handle_prepare (insn, insn2, &current_pc, pi, &pifsr);
854 continue;
855 }
856 else if (insn == 0x07e0 && regsave_func_p && insn2 == 0x0144)
857 { /* ctret after processing register save. */
858 current_pc = save_pc;
859 prologue_end = save_end;
860 regsave_func_p = 0;
861 continue;
862 }
863 else if ((insn & 0xfff0) == 0x07e0 && (insn2 & 5) == 1)
864 { /* pushml, pushmh */
865 v850_handle_pushm (insn, insn2, pi, &pifsr);
866 continue;
867 }
868 else if ((insn & 0xffe0) == 0x0060 && regsave_func_p)
869 { /* jmp after processing register save. */
870 current_pc = save_pc;
871 prologue_end = save_end;
872 regsave_func_p = 0;
873 continue;
874 }
875 else if ((insn & 0x07c0) == 0x0780 /* jarl or jr */
876 || (insn & 0xffe0) == 0x0060 /* jmp */
877 || (insn & 0x0780) == 0x0580) /* branch */
878 {
581e13c1 879 break; /* Ran into end of prologue. */
181124bc
CV		 880 }
881
882 else if ((insn & 0xffe0) == ((E_SP_REGNUM << 11) | 0x0240))
dda83cd7 883 /* add <imm>,sp */
181124bc
CV		 884 pi->sp_offset += ((insn & 0x1f) ^ 0x10) - 0x10;
885 else if (insn == ((E_SP_REGNUM << 11) | 0x0600 | E_SP_REGNUM))
dda83cd7 886 /* addi <imm>,sp,sp */
181124bc
CV		 887 pi->sp_offset += insn2;
888 else if (insn == ((E_FP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
dda83cd7 889 /* mov sp,fp */
181124bc
CV		 890 pi->uses_fp = 1;
891 else if (insn == ((E_R12_REGNUM << 11) | 0x0640 | E_R0_REGNUM))
dda83cd7 892 /* movhi hi(const),r0,r12 */
181124bc
CV		 893 r12_tmp = insn2 << 16;
894 else if (insn == ((E_R12_REGNUM << 11) | 0x0620 | E_R12_REGNUM))
dda83cd7 895 /* movea lo(const),r12,r12 */
181124bc
CV		 896 r12_tmp += insn2;
897 else if (insn == ((E_SP_REGNUM << 11) | 0x01c0 | E_R12_REGNUM) && r12_tmp)
dda83cd7 898 /* add r12,sp */
181124bc
CV		 899 pi->sp_offset += r12_tmp;
900 else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
dda83cd7 901 /* mov sp,ep */
181124bc
CV		 902 ep_used = 1;
903 else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_R1_REGNUM))
dda83cd7 904 /* mov r1,ep */
181124bc
CV		 905 ep_used = 0;
906 else if (((insn & 0x07ff) == (0x0760 | E_SP_REGNUM)
907 || (pi->uses_fp
908 && (insn & 0x07ff) == (0x0760 | E_FP_REGNUM)))
909 && pifsr
910 && v850_is_save_register (reg = (insn >> 11) & 0x1f))
911 {
912 /* st.w <reg>,<offset>[sp] or st.w <reg>,<offset>[fp] */
913 pifsr->reg = reg;
914 pifsr->offset = insn2 & ~1;
915 pifsr->cur_frameoffset = pi->sp_offset;
916 pifsr++;
917 }
918 else if (ep_used
919 && ((insn & 0x0781) == 0x0501)
920 && pifsr
921 && v850_is_save_register (reg = (insn >> 11) & 0x1f))
922 {
923 /* sst.w <reg>,<offset>[ep] */
924 pifsr->reg = reg;
925 pifsr->offset = (insn & 0x007e) << 1;
926 pifsr->cur_frameoffset = pi->sp_offset;
927 pifsr++;
928 }
929 }
930
931 /* Fix up any offsets to the final offset. If a frame pointer was created,
932 use it instead of the stack pointer. */
933 for (pifsr_tmp = pifsrs; pifsr_tmp != pifsr; pifsr_tmp++)
934 {
935 pifsr_tmp->offset -= pi->sp_offset - pifsr_tmp->cur_frameoffset;
098caef4 936 pi->saved_regs[pifsr_tmp->reg].set_addr (pifsr_tmp->offset);
181124bc
CV		 937 }
938
939 return current_pc;
940}
941
942/* Return the address of the first code past the prologue of the function. */
943
944static CORE_ADDR
6093d2eb 945v850_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
181124bc
CV		 946{
947 CORE_ADDR func_addr, func_end;
948
581e13c1 949 /* See what the symbol table says. */
181124bc
CV		 950
951 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
952 {
953 struct symtab_and_line sal;
954
955 sal = find_pc_line (func_addr, 0);
956 if (sal.line != 0 && sal.end < func_end)
957 return sal.end;
958
959 /* Either there's no line info, or the line after the prologue is after
960 the end of the function. In this case, there probably isn't a
961 prologue. */
962 return pc;
963 }
964
581e13c1
MS		 965 /* We can't find the start of this function, so there's nothing we
966 can do. */
181124bc
CV		 967 return pc;
968}
969
83b2706a
KB		 970/* Return 1 if the data structure has any 8-byte fields that'll require
971 the entire data structure to be aligned. Otherwise, return 0. */
972
973static int
974v850_eight_byte_align_p (struct type *type)
975{
976 type = check_typedef (type);
977
978 if (v850_type_is_scalar (type))
df86565b 979 return (type->length () == 8);
83b2706a
KB		 980 else
981 {
982 int i;
983
1f704f76 984 for (i = 0; i < type->num_fields (); i++)
83b2706a 985 {
940da03e 986 if (v850_eight_byte_align_p (type->field (i).type ()))
83b2706a
KB		 987 return 1;
988 }
989 }
990 return 0;
991}
992
181124bc
CV		 993static CORE_ADDR
994v850_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
995{
996 return sp & ~3;
997}
998
999/* Setup arguments and LP for a call to the target. First four args
1000 go in R6->R9, subsequent args go into sp + 16 -> sp + ... Structs
1001 are passed by reference. 64 bit quantities (doubles and long longs)
1002 may be split between the regs and the stack. When calling a function
1003 that returns a struct, a pointer to the struct is passed in as a secret
1004 first argument (always in R6).
1005
1006 Stack space for the args has NOT been allocated: that job is up to us. */
1007
1008static CORE_ADDR
1009v850_push_dummy_call (struct gdbarch *gdbarch,
1010 struct value *function,
1011 struct regcache *regcache,
1012 CORE_ADDR bp_addr,
1013 int nargs,
1014 struct value **args,
1015 CORE_ADDR sp,
cf84fa6b 1016 function_call_return_method return_method,
181124bc
CV		 1017 CORE_ADDR struct_addr)
1018{
e17a4113 1019 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
181124bc
CV		 1020 int argreg;
1021 int argnum;
b926417a 1022 int arg_space = 0;
181124bc 1023 int stack_offset;
08106042 1024 v850_gdbarch_tdep *tdep = gdbarch_tdep<v850_gdbarch_tdep> (gdbarch);
181124bc 1025
345bd07c 1026 if (tdep->abi == V850_ABI_RH850)
83b2706a
KB		 1027 stack_offset = 0;
1028 else
01add95b
SM		 1029 {
1030 /* The offset onto the stack at which we will start copying parameters
1031 (after the registers are used up) begins at 16 rather than at zero.
1032 That's how the ABI is defined, though there's no indication that these
1033 16 bytes are used for anything, not even for saving incoming
1034 argument registers. */
1035 stack_offset = 16;
1036 }
181124bc
CV		 1037
1038 /* Now make space on the stack for the args. */
1039 for (argnum = 0; argnum < nargs; argnum++)
df86565b 1040 arg_space += ((value_type (args[argnum])->length () + 3) & ~3);
b926417a 1041 sp -= arg_space + stack_offset;
181124bc
CV		 1042
1043 argreg = E_ARG0_REGNUM;
1044 /* The struct_return pointer occupies the first parameter register. */
cf84fa6b 1045 if (return_method == return_method_struct)
181124bc
CV		 1046 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
1047
1048 /* Now load as many as possible of the first arguments into
1049 registers, and push the rest onto the stack. There are 16 bytes
1050 in four registers available. Loop thru args from first to last. */
1051 for (argnum = 0; argnum < nargs; argnum++)
1052 {
1053 int len;
1054 gdb_byte *val;
1055 gdb_byte valbuf[v850_reg_size];
1056
1057 if (!v850_type_is_scalar (value_type (*args))
345bd07c 1058 && tdep->abi == V850_ABI_GCC
df86565b 1059 && value_type (*args)->length () > E_MAX_RETTYPE_SIZE_IN_REGS)
181124bc 1060 {
e17a4113
UW		 1061 store_unsigned_integer (valbuf, 4, byte_order,
1062 value_address (*args));
181124bc
CV		 1063 len = 4;
1064 val = valbuf;
1065 }
1066 else
1067 {
df86565b 1068 len = value_type (*args)->length ();
50888e42 1069 val = (gdb_byte *) value_contents (*args).data ();
181124bc
CV		 1070 }
1071
345bd07c 1072 if (tdep->eight_byte_align
dda83cd7
SM		 1073 && v850_eight_byte_align_p (value_type (*args)))
1074 {
83b2706a
KB		 1075 if (argreg <= E_ARGLAST_REGNUM && (argreg & 1))
1076 argreg++;
1077 else if (stack_offset & 0x4)
1078 stack_offset += 4;
1079 }
1080
181124bc
CV		 1081 while (len > 0)
1082 if (argreg <= E_ARGLAST_REGNUM)
1083 {
1084 CORE_ADDR regval;
1085
e17a4113 1086 regval = extract_unsigned_integer (val, v850_reg_size, byte_order);
181124bc
CV		 1087 regcache_cooked_write_unsigned (regcache, argreg, regval);
1088
1089 len -= v850_reg_size;
1090 val += v850_reg_size;
1091 argreg++;
1092 }
1093 else
1094 {
1095 write_memory (sp + stack_offset, val, 4);
1096
1097 len -= 4;
1098 val += 4;
1099 stack_offset += 4;
1100 }
1101 args++;
1102 }
1103
1104 /* Store return address. */
1105 regcache_cooked_write_unsigned (regcache, E_LP_REGNUM, bp_addr);
1106
1107 /* Update stack pointer. */
1108 regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp);
1109
1110 return sp;
1111}
1112
1113static void
1114v850_extract_return_value (struct type *type, struct regcache *regcache,
1115 gdb_byte *valbuf)
1116{
ac7936df 1117 struct gdbarch *gdbarch = regcache->arch ();
e17a4113 1118 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
df86565b 1119 int len = type->length ();
181124bc
CV		 1120
1121 if (len <= v850_reg_size)
1122 {
1123 ULONGEST val;
1124
1125 regcache_cooked_read_unsigned (regcache, E_V0_REGNUM, &val);
e17a4113 1126 store_unsigned_integer (valbuf, len, byte_order, val);
181124bc
CV		 1127 }
1128 else if (len <= 2 * v850_reg_size)
1129 {
1130 int i, regnum = E_V0_REGNUM;
1131 gdb_byte buf[v850_reg_size];
1132 for (i = 0; len > 0; i += 4, len -= 4)
1133 {
0b883586 1134 regcache->raw_read (regnum++, buf);
181124bc
CV		 1135 memcpy (valbuf + i, buf, len > 4 ? 4 : len);
1136 }
1137 }
1138}
1139
1140static void
1141v850_store_return_value (struct type *type, struct regcache *regcache,
1142 const gdb_byte *valbuf)
1143{
ac7936df 1144 struct gdbarch *gdbarch = regcache->arch ();
e17a4113 1145 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
df86565b 1146 int len = type->length ();
181124bc
CV		 1147
1148 if (len <= v850_reg_size)
e17a4113
UW		 1149 regcache_cooked_write_unsigned
1150 (regcache, E_V0_REGNUM,
1151 extract_unsigned_integer (valbuf, len, byte_order));
181124bc
CV		 1152 else if (len <= 2 * v850_reg_size)
1153 {
1154 int i, regnum = E_V0_REGNUM;
1155 for (i = 0; i < len; i += 4)
10eaee5f 1156 regcache->raw_write (regnum++, valbuf + i);
181124bc
CV		 1157 }
1158}
1159
1160static enum return_value_convention
6a3a010b 1161v850_return_value (struct gdbarch *gdbarch, struct value *function,
c055b101 1162 struct type *type, struct regcache *regcache,
181124bc
CV		 1163 gdb_byte *readbuf, const gdb_byte *writebuf)
1164{
83b2706a 1165 if (v850_use_struct_convention (gdbarch, type))
181124bc
CV		 1166 return RETURN_VALUE_STRUCT_CONVENTION;
1167 if (writebuf)
1168 v850_store_return_value (type, regcache, writebuf);
1169 else if (readbuf)
1170 v850_extract_return_value (type, regcache, readbuf);
1171 return RETURN_VALUE_REGISTER_CONVENTION;
1172}
1173
cd6c3b4f
YQ		 1174/* Implement the breakpoint_kind_from_pc gdbarch method. */
1175
d19280ad
YQ		 1176static int
1177v850_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
181124bc 1178{
d19280ad
YQ		 1179 return 2;
1180}
83b2706a 1181
cd6c3b4f
YQ		 1182/* Implement the sw_breakpoint_from_kind gdbarch method. */
1183
d19280ad
YQ		 1184static const gdb_byte *
1185v850_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1186{
1187 *size = kind;
1188
1189 switch (gdbarch_bfd_arch_info (gdbarch)->mach)
ff12a659
YQ		 1190 {
1191 case bfd_mach_v850e2:
1192 case bfd_mach_v850e2v3:
1193 case bfd_mach_v850e3v5:
1194 {
1195 /* Implement software breakpoints by using the dbtrap instruction.
1196 Older architectures had no such instruction. For those, an
1197 unconditional branch to self instruction is used. */
83b2706a 1198
ff12a659 1199 static unsigned char dbtrap_breakpoint[] = { 0x40, 0xf8 };
83b2706a 1200
ff12a659
YQ		 1201 return dbtrap_breakpoint;
1202 }
1203 break;
1204 default:
1205 {
1206 static unsigned char breakpoint[] = { 0x85, 0x05 };
83b2706a 1207
ff12a659
YQ		 1208 return breakpoint;
1209 }
1210 break;
1211 }
181124bc
CV		 1212}
1213
1214static struct v850_frame_cache *
bd2b40ac 1215v850_alloc_frame_cache (frame_info_ptr this_frame)
181124bc
CV		 1216{
1217 struct v850_frame_cache *cache;
181124bc
CV		 1218
1219 cache = FRAME_OBSTACK_ZALLOC (struct v850_frame_cache);
94afd7a6 1220 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
181124bc
CV		 1221
1222 /* Base address. */
1223 cache->base = 0;
1224 cache->sp_offset = 0;
1225 cache->pc = 0;
1226
1227 /* Frameless until proven otherwise. */
1228 cache->uses_fp = 0;
1229
1230 return cache;
1231}
1232
1233static struct v850_frame_cache *
bd2b40ac 1234v850_frame_cache (frame_info_ptr this_frame, void **this_cache)
181124bc 1235{
e17a4113 1236 struct gdbarch *gdbarch = get_frame_arch (this_frame);
181124bc
CV		 1237 struct v850_frame_cache *cache;
1238 CORE_ADDR current_pc;
1239 int i;
1240
1241 if (*this_cache)
19ba03f4 1242 return (struct v850_frame_cache *) *this_cache;
181124bc 1243
94afd7a6 1244 cache = v850_alloc_frame_cache (this_frame);
181124bc
CV		 1245 *this_cache = cache;
1246
1247 /* In principle, for normal frames, fp holds the frame pointer,
1248 which holds the base address for the current stack frame.
1249 However, for functions that don't need it, the frame pointer is
1250 optional. For these "frameless" functions the frame pointer is
1251 actually the frame pointer of the calling frame. */
94afd7a6 1252 cache->base = get_frame_register_unsigned (this_frame, E_FP_REGNUM);
181124bc
CV		 1253 if (cache->base == 0)
1254 return cache;
1255
94afd7a6
UW		 1256 cache->pc = get_frame_func (this_frame);
1257 current_pc = get_frame_pc (this_frame);
181124bc 1258 if (cache->pc != 0)
d2ca4222
UW		 1259 {
1260 ULONGEST ctbp;
94afd7a6 1261 ctbp = get_frame_register_unsigned (this_frame, E_CTBP_REGNUM);
e17a4113 1262 v850_analyze_prologue (gdbarch, cache->pc, current_pc, cache, ctbp);
d2ca4222 1263 }
181124bc
CV		 1264
1265 if (!cache->uses_fp)
1266 {
1267 /* We didn't find a valid frame, which means that CACHE->base
dda83cd7
SM		 1268 currently holds the frame pointer for our calling frame. If
1269 we're at the start of a function, or somewhere half-way its
1270 prologue, the function's frame probably hasn't been fully
1271 setup yet. Try to reconstruct the base address for the stack
1272 frame by looking at the stack pointer. For truly "frameless"
1273 functions this might work too. */
94afd7a6 1274 cache->base = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
181124bc
CV		 1275 }
1276
1277 /* Now that we have the base address for the stack frame we can
1278 calculate the value of sp in the calling frame. */
a9a87d35 1279 cache->saved_regs[E_SP_REGNUM].set_value (cache->base - cache->sp_offset);
181124bc
CV		 1280
1281 /* Adjust all the saved registers such that they contain addresses
1282 instead of offsets. */
55fa75c3 1283 for (i = 0; i < gdbarch_num_regs (gdbarch); i++)
a9a87d35 1284 if (cache->saved_regs[i].is_addr ())
098caef4
LM		 1285 cache->saved_regs[i].set_addr (cache->saved_regs[i].addr ()
1286 + cache->base);
181124bc
CV		 1287
1288 /* The call instruction moves the caller's PC in the callee's LP.
1289 Since this is an unwind, do the reverse. Copy the location of LP
1290 into PC (the address / regnum) so that a request for PC will be
1291 converted into a request for the LP. */
1292
1293 cache->saved_regs[E_PC_REGNUM] = cache->saved_regs[E_LP_REGNUM];
1294
1295 return cache;
1296}
1297
1298
94afd7a6 1299static struct value *
bd2b40ac 1300v850_frame_prev_register (frame_info_ptr this_frame,
94afd7a6 1301 void **this_cache, int regnum)
181124bc 1302{
94afd7a6 1303 struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
181124bc
CV		 1304
1305 gdb_assert (regnum >= 0);
1306
94afd7a6 1307 return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum);
181124bc
CV		 1308}
1309
1310static void
bd2b40ac 1311v850_frame_this_id (frame_info_ptr this_frame, void **this_cache,
181124bc
CV		 1312 struct frame_id *this_id)
1313{
94afd7a6 1314 struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
181124bc
CV		 1315
1316 /* This marks the outermost frame. */
1317 if (cache->base == 0)
1318 return;
1319
098caef4 1320 *this_id = frame_id_build (cache->saved_regs[E_SP_REGNUM].addr (), cache->pc);
181124bc
CV		 1321}
1322
1323static const struct frame_unwind v850_frame_unwind = {
a154d838 1324 "v850 prologue",
181124bc 1325 NORMAL_FRAME,
8fbca658 1326 default_frame_unwind_stop_reason,
181124bc 1327 v850_frame_this_id,
94afd7a6
UW		 1328 v850_frame_prev_register,
1329 NULL,
1330 default_frame_sniffer
181124bc 1331};
181124bc 1332
181124bc 1333static CORE_ADDR
bd2b40ac 1334v850_frame_base_address (frame_info_ptr this_frame, void **this_cache)
181124bc 1335{
94afd7a6 1336 struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
181124bc
CV		 1337
1338 return cache->base;
1339}
1340
1341static const struct frame_base v850_frame_base = {
1342 &v850_frame_unwind,
1343 v850_frame_base_address,
1344 v850_frame_base_address,
1345 v850_frame_base_address
1346};
1347
1348static struct gdbarch *
1349v850_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1350{
1351 struct gdbarch *gdbarch;
83b2706a
KB		 1352 int e_flags, e_machine;
1353
1354 /* Extract the elf_flags if available. */
1355 if (info.abfd != NULL
1356 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1357 {
1358 e_flags = elf_elfheader (info.abfd)->e_flags;
1359 e_machine = elf_elfheader (info.abfd)->e_machine;
1360 }
1361 else
1362 {
1363 e_flags = 0;
1364 e_machine = 0;
1365 }
181124bc 1366
181124bc 1367
83b2706a
KB		 1368 /* Try to find the architecture in the list of already defined
1369 architectures. */
1370 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1371 arches != NULL;
1372 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1373 {
345bd07c 1374 v850_gdbarch_tdep *tdep
08106042 1375 = gdbarch_tdep<v850_gdbarch_tdep> (arches->gdbarch);
345bd07c
SM		 1376
1377 if (tdep->e_flags != e_flags || tdep->e_machine != e_machine)
83b2706a
KB		 1378 continue;
1379
1380 return arches->gdbarch;
1381 }
345bd07c
SM		 1382
1383 v850_gdbarch_tdep *tdep = new v850_gdbarch_tdep;
83b2706a
KB		 1384 tdep->e_flags = e_flags;
1385 tdep->e_machine = e_machine;
1386
1387 switch (tdep->e_machine)
1388 {
1389 case EM_V800:
1390 tdep->abi = V850_ABI_RH850;
1391 break;
1392 default:
1393 tdep->abi = V850_ABI_GCC;
1394 break;
1395 }
1396
1397 tdep->eight_byte_align = (tdep->e_flags & EF_RH850_DATA_ALIGN8) ? 1 : 0;
1398 gdbarch = gdbarch_alloc (&info, tdep);
181124bc
CV		 1399
1400 switch (info.bfd_arch_info->mach)
1401 {
1402 case bfd_mach_v850:
1403 set_gdbarch_register_name (gdbarch, v850_register_name);
55fa75c3 1404 set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850_REGS);
181124bc
CV		 1405 break;
1406 case bfd_mach_v850e:
1407 case bfd_mach_v850e1:
1408 set_gdbarch_register_name (gdbarch, v850e_register_name);
55fa75c3 1409 set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850E_REGS);
181124bc 1410 break;
2aaed979
KB		 1411 case bfd_mach_v850e2:
1412 case bfd_mach_v850e2v3:
1413 set_gdbarch_register_name (gdbarch, v850e2_register_name);
55fa75c3 1414 set_gdbarch_num_regs (gdbarch, E_NUM_REGS);
2aaed979 1415 break;
83b2706a
KB		 1416 case bfd_mach_v850e3v5:
1417 set_gdbarch_register_name (gdbarch, v850e3v5_register_name);
1418 set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850E3V5_REGS);
1419 break;
181124bc
CV		 1420 }
1421
181124bc
CV		 1422 set_gdbarch_num_pseudo_regs (gdbarch, 0);
1423 set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM);
1424 set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM);
1425 set_gdbarch_fp0_regnum (gdbarch, -1);
1426
1427 set_gdbarch_register_type (gdbarch, v850_register_type);
1428
351a3e56 1429 set_gdbarch_char_signed (gdbarch, 1);
181124bc
CV		 1430 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1431 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1432 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1433 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1434
1435 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1436 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1437 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1438
1439 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1440 set_gdbarch_addr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1441
1442 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
181124bc 1443
04180708
YQ		 1444 set_gdbarch_breakpoint_kind_from_pc (gdbarch, v850_breakpoint_kind_from_pc);
1445 set_gdbarch_sw_breakpoint_from_kind (gdbarch, v850_sw_breakpoint_from_kind);
181124bc
CV		 1446 set_gdbarch_return_value (gdbarch, v850_return_value);
1447 set_gdbarch_push_dummy_call (gdbarch, v850_push_dummy_call);
1448 set_gdbarch_skip_prologue (gdbarch, v850_skip_prologue);
1449
181124bc 1450 set_gdbarch_frame_align (gdbarch, v850_frame_align);
181124bc
CV		 1451 frame_base_set_default (gdbarch, &v850_frame_base);
1452
1453 /* Hook in ABI-specific overrides, if they have been registered. */
1454 gdbarch_init_osabi (info, gdbarch);
1455
94afd7a6
UW		 1456 dwarf2_append_unwinders (gdbarch);
1457 frame_unwind_append_unwinder (gdbarch, &v850_frame_unwind);
181124bc
CV		 1458
1459 return gdbarch;
1460}
1461
6c265988 1462void _initialize_v850_tdep ();
181124bc 1463void
6c265988 1464_initialize_v850_tdep ()
181124bc 1465{
ec29a63c
TT		 1466 gdbarch_register (bfd_arch_v850, v850_gdbarch_init);
1467 gdbarch_register (bfd_arch_v850_rh850, v850_gdbarch_init);
181124bc 1468}
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